first version of pre-check clean database

checks/full_log.log

diff --git a/checks/full_log.log b/checks/full_log.log
index 41c487f..912e28a 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -3,8 +3,8 @@
 Step 0 done without fatal errors.
  Executing Step 1 of 8: Project License Check
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
- SPDX COMPLIANCE Found 2 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/verilog/rtl/syntacore/scr1/README.md']
+ SPDX COMPLIANCE Found 503 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/a', '/home/dinesha/workarea/opencore/git/yifive_r0/README.md', '/home/dinesha/workarea/opencore/git/yifive_r0/test.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-fastroute_4.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.param', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/21-fastroute_5.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/24-tritonRoute.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/19-fastroute_3.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/18-fastroute_2.guide', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext']
  Executing Step 2 of 8: YAML File Check
  YAML file valid!
 Step 2 done without fatal errors.
@@ -16,3 +16,27 @@
 b'Running sha1sum checks'
  Manifest Checks Passed. Caravel Version Matches.
  Makefile Checks Passed.
+ Documentation Checks Passed.
+ Executing Step 4 of 8: Fuzzy Consistency Checks
+instance caravel found
+instance user_project_wrapper found
+Design is complex and contains: 47 modules
+Design is complex and contains: 18 modules
+verilog Consistency Checks Passed.
+ Basic Hierarchy Checks Passed.
+{PROGRESS} Running Pins and Power Checks...
+Pins check passed
+Internal Power Checks Passed!
+Power Checks Passed
+ Fuzzy Consistency Checks Passed!
+Step 4 done without fatal errors.
+ Executing Step 5 of 8: XOR Consistency Checks
+ Running XOR Checks...
+Total XOR differences = 0
+ XOR Checks on User Project GDS Passed!
+Step 5 done without fatal errors.
+ Executing Step 6 of 8: DRC Violations Checks
+ Running Magic DRC Checks...
+ DRC Checks on User Project GDS Passed!
+Step 6 done without fatal errors.
+ All Checks PASSED !!!

checks/spdx_compliance_report.log

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index ac9524b..b4c0380 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -1,4 +1,505 @@
 FULL RUN LOG:
 SPDX NON-COMPLIANT FILES
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 /home/dinesha/workarea/opencore/git/yifive_r0/README.md
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mag/syntacore.mag.gz

diff --git a/mag/syntacore.mag.gz b/mag/syntacore.mag.gz
index 7f5952e..7973747 100644
--- a/mag/syntacore.mag.gz
+++ b/mag/syntacore.mag.gz
Binary files differ

mag/uart.mag.gz

diff --git a/mag/uart.mag.gz b/mag/uart.mag.gz
index 50f9d3b..15a379a 100644
--- a/mag/uart.mag.gz
+++ b/mag/uart.mag.gz
Binary files differ

mag/user_project_wrapper.mag.gz

diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 3071475..4d4c1bf 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ

mag/wb_host.mag.gz

diff --git a/mag/wb_host.mag.gz b/mag/wb_host.mag.gz
index 5ab917e..313e996 100644
--- a/mag/wb_host.mag.gz
+++ b/mag/wb_host.mag.gz
Binary files differ

mag/wb_interconnect.mag.gz

diff --git a/mag/wb_interconnect.mag.gz b/mag/wb_interconnect.mag.gz
index 23eab2b..887792b 100644
--- a/mag/wb_interconnect.mag.gz
+++ b/mag/wb_interconnect.mag.gz
Binary files differ

maglef/clk_skew_adjust.mag.gz

diff --git a/maglef/clk_skew_adjust.mag.gz b/maglef/clk_skew_adjust.mag.gz
new file mode 100644
index 0000000..3220071
--- /dev/null
+++ b/maglef/clk_skew_adjust.mag.gz
Binary files differ

maglef/glbl_cfg.mag.gz

diff --git a/maglef/glbl_cfg.mag.gz b/maglef/glbl_cfg.mag.gz
index 487ed6a..c34cf4c 100644
--- a/maglef/glbl_cfg.mag.gz
+++ b/maglef/glbl_cfg.mag.gz
Binary files differ

maglef/sdram.mag.gz

diff --git a/maglef/sdram.mag.gz b/maglef/sdram.mag.gz
index 5155289..35fac2a 100644
--- a/maglef/sdram.mag.gz
+++ b/maglef/sdram.mag.gz
Binary files differ

maglef/spi_master.mag.gz

diff --git a/maglef/spi_master.mag.gz b/maglef/spi_master.mag.gz
index 2497b05..efa750f 100644
--- a/maglef/spi_master.mag.gz
+++ b/maglef/spi_master.mag.gz
Binary files differ

maglef/syntacore.mag.gz

diff --git a/maglef/syntacore.mag.gz b/maglef/syntacore.mag.gz
index 6c291de..1e3d8eb 100644
--- a/maglef/syntacore.mag.gz
+++ b/maglef/syntacore.mag.gz
Binary files differ

maglef/uart.mag.gz

diff --git a/maglef/uart.mag.gz b/maglef/uart.mag.gz
index 4cf3602..150e21b 100644
--- a/maglef/uart.mag.gz
+++ b/maglef/uart.mag.gz
Binary files differ

maglef/user_project_wrapper.mag.gz

diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index 313ad62..abe0fef 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ

maglef/wb_host.mag.gz

diff --git a/maglef/wb_host.mag.gz b/maglef/wb_host.mag.gz
index 97a248d..e86fa14 100644
--- a/maglef/wb_host.mag.gz
+++ b/maglef/wb_host.mag.gz
Binary files differ

maglef/wb_interconnect.mag.gz

diff --git a/maglef/wb_interconnect.mag.gz b/maglef/wb_interconnect.mag.gz
index 966e536..8ff48c8 100644
--- a/maglef/wb_interconnect.mag.gz
+++ b/maglef/wb_interconnect.mag.gz
Binary files differ

signoff/clk_skew_adjust/OPENLANE_VERSION

diff --git a/signoff/clk_skew_adjust/OPENLANE_VERSION b/signoff/clk_skew_adjust/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/clk_skew_adjust/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7

signoff/clk_skew_adjust/PDK_SOURCES

diff --git a/signoff/clk_skew_adjust/PDK_SOURCES b/signoff/clk_skew_adjust/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/clk_skew_adjust/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6

signoff/clk_skew_adjust/final_summary_report.csv

diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
new file mode 100644
index 0000000..3d2887c
--- /dev/null
+++ b/signoff/clk_skew_adjust/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m8s,0h0m33s,20000.0,0.0025,12000.0,28,387.16,30,0,0,0,0,0,0,0,0,0,-1,0,389,195,-2.16,-2.16,-2.16,-2.16,-2.03,-2.16,-2.16,-2.16,-2.16,-2.03,237416,0.0,3.57,4.52,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,20,12,0,32,83.1255195344971,12.03,10,AREA 0,5,60,1,153.6,153.18,0.85,0,sky130_fd_sc_hd,0,4

signoff/glbl_cfg/final_summary_report.csv

diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index cddcb14..7678a6e 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m48s,0h3m34s,47033.33333333334,0.12,23516.66666666667,41,556.01,2822,0,0,0,0,0,0,0,2,0,-1,0,156023,24257,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,114388749,0.0,31.41,31.61,0.34,-1,-1,2676,2872,476,672,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m17s,0h3m22s,47033.33333333334,0.12,23516.66666666667,41,563.02,2822,0,0,0,0,0,0,0,5,0,-1,0,155613,24467,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,112650425,0.0,31.24,31.63,0.44,-1,-1,2677,2873,477,673,0,0,0,2822,1,0,3,9,474,0,3,571,588,548,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4

signoff/sdram/final_summary_report.csv

diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 5971cda..e90cae1 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m14s,0h4m9s,39520.0,0.35,19760.0,26,632.18,6916,0,0,0,0,0,0,0,10,0,-1,0,290277,48450,-3.59,-3.59,-3.59,-3.59,-4.13,-3.59,-3.59,-3.59,-3.59,-4.13,232393261,0.0,19.76,15.43,1.33,-1,-1,6851,7079,1140,1368,0,0,0,6916,132,107,80,108,350,212,30,2197,1189,1088,27,350,4248,0,4598,70.7714083510262,14.129999999999999,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m41s,0h5m12s,40668.57142857143,0.35,20334.285714285714,27,639.77,7117,0,0,0,0,0,0,0,15,0,-1,0,302912,50760,-3.59,-3.59,-3.59,-3.59,-4.18,-3.59,-3.59,-3.59,-3.59,-4.18,239724191,0.0,20.25,16.33,1.79,-1,-1,7052,7280,1239,1467,0,0,0,7117,197,107,81,102,354,212,31,2263,1256,1154,27,350,4248,0,4598,70.52186177715092,14.18,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3

signoff/syntacore/final_summary_report.csv

diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 1c146a1..2fc1d06 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h57m56s,0h33m31s,34420.0,1.8,17210.0,23,1202.9,30978,0,0,0,0,0,0,0,82,2,-1,0,1618491,250568,-0.3,-0.3,-0.44,-0.44,-0.73,-12.11,-12.11,-18.83,-18.83,-29.4,1353757569,0.0,19.59,15.78,4.41,0.64,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,93.19664492078284,10.73,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h50m19s,0h27m57s,34420.0,1.8,17210.0,22,1198.49,30978,0,0,0,0,0,0,0,56,2,-1,0,1529372,247821,-0.3,-0.3,-0.44,-0.44,-0.49,-12.11,-12.11,-25.78,-25.78,-26.46,1263825045,0.0,18.47,15.11,4.15,0.29,-1,30864,31102,2807,3045,0,0,0,30978,631,0,685,2044,4015,2105,1318,7432,2838,2786,94,866,22836,0,23702,95.32888465204957,10.49,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3

signoff/user_project_wrapper/final_summary_report.csv

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7cae2d2..d2284fa 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h39m29s,0h5m43s,1.362079701120797,10.2784,0.6810398505603985,0,578.61,7,0,0,0,0,0,0,0,0,0,-1,-1,1229122,6052,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.38,3.7,0.68,1.42,0.27,842,1460,842,1460,0,0,0,7,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h40m41s,0h5m14s,3.3079078455790785,10.2784,1.6539539227895392,0,577.98,17,0,0,0,0,0,0,0,0,28,-1,-1,1297769,6216,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,2.22,3.66,1.51,1.63,-1,852,1470,852,1470,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0

signoff/wb_host/final_summary_report.csv

diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index ca1bdbe..7565689 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h9m40s,0h6m56s,30470.0,0.2,15235.0,25,613.2,3047,0,0,0,0,0,0,0,1,0,-1,0,335681,32215,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,282222295,0.0,47.7,13.38,29.5,-1,-1,2769,3411,458,1100,0,0,0,3047,83,0,5,8,30,27,9,776,590,739,15,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h10m23s,0h7m30s,30760.0,0.2,15380.0,25,615.57,3076,0,0,0,0,0,0,0,1,0,-1,0,327997,31894,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,274634123,0.0,48.31,13.11,27.06,-1,-1,2798,3440,464,1106,0,0,0,3076,83,0,5,14,30,26,9,783,597,752,15,130,2343,0,2473,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5

spi/lvs/clk_skew_adjust.spice.gz

diff --git a/spi/lvs/clk_skew_adjust.spice.gz b/spi/lvs/clk_skew_adjust.spice.gz
new file mode 100644
index 0000000..aeb5d3f
--- /dev/null
+++ b/spi/lvs/clk_skew_adjust.spice.gz
Binary files differ

spi/lvs/glbl_cfg.spice.gz

diff --git a/spi/lvs/glbl_cfg.spice.gz b/spi/lvs/glbl_cfg.spice.gz
index ff319a8..41501d0 100644
--- a/spi/lvs/glbl_cfg.spice.gz
+++ b/spi/lvs/glbl_cfg.spice.gz
Binary files differ

spi/lvs/sdram.spice.gz

diff --git a/spi/lvs/sdram.spice.gz b/spi/lvs/sdram.spice.gz
index 0d24af4..6b6c750 100644
--- a/spi/lvs/sdram.spice.gz
+++ b/spi/lvs/sdram.spice.gz
Binary files differ

spi/lvs/spi_master.spice.gz

diff --git a/spi/lvs/spi_master.spice.gz b/spi/lvs/spi_master.spice.gz
index 3f1e5c2..f5b4dd5 100644
--- a/spi/lvs/spi_master.spice.gz
+++ b/spi/lvs/spi_master.spice.gz
Binary files differ

spi/lvs/syntacore.spice.gz

diff --git a/spi/lvs/syntacore.spice.gz b/spi/lvs/syntacore.spice.gz
index 9567b04..6d84553 100644
--- a/spi/lvs/syntacore.spice.gz
+++ b/spi/lvs/syntacore.spice.gz
Binary files differ

spi/lvs/uart.spice.gz

diff --git a/spi/lvs/uart.spice.gz b/spi/lvs/uart.spice.gz
index 6f0d210..5c4d266 100644
--- a/spi/lvs/uart.spice.gz
+++ b/spi/lvs/uart.spice.gz
Binary files differ

spi/lvs/user_project_wrapper.spice.gz

diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 1f2a7c0..8b0ce00 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ

spi/lvs/wb_host.spice.gz

diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz
index ec70633..5198c9f 100644
--- a/spi/lvs/wb_host.spice.gz
+++ b/spi/lvs/wb_host.spice.gz
Binary files differ

spi/lvs/wb_interconnect.spice.gz

diff --git a/spi/lvs/wb_interconnect.spice.gz b/spi/lvs/wb_interconnect.spice.gz
index 132e4c3..a0bacb7 100644
--- a/spi/lvs/wb_interconnect.spice.gz
+++ b/spi/lvs/wb_interconnect.spice.gz
Binary files differ

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 4d41c2d..a0a372d 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1445,7 +1445,23 @@
     \u_core.wbd_sdram_sel_o[2] ,
     \u_core.wbd_sdram_sel_o[1] ,
     \u_core.wbd_sdram_sel_o[0] }));
- clk_skew_adjust \u_core.u_skew_adj_sd_ci  (.clk_in(io_in[29]),
+ clk_skew_adjust \u_core.u_skew_glbl  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_glbl ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[23] ,
+    \u_core.cfg_clk_ctrl1[22] ,
+    \u_core.cfg_clk_ctrl1[21] ,
+    \u_core.cfg_clk_ctrl1[20] }));
+ clk_skew_adjust \u_core.u_skew_riscv  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_riscv ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[7] ,
+    \u_core.cfg_clk_ctrl1[6] ,
+    \u_core.cfg_clk_ctrl1[5] ,
+    \u_core.cfg_clk_ctrl1[4] }));
+ clk_skew_adjust \u_core.u_skew_sd_ci  (.clk_in(io_in[29]),
     .clk_out(\u_core.io_in_29_ ),
     .vccd1(vccd1),
     .vssd1(vssd1),
@@ -1453,7 +1469,7 @@
     \u_core.cfg_clk_ctrl2[6] ,
     \u_core.cfg_clk_ctrl2[5] ,
     \u_core.cfg_clk_ctrl2[4] }));
- clk_skew_adjust \u_core.u_skew_adj_sd_co  (.clk_in(\u_core.io_out_29_ ),
+ clk_skew_adjust \u_core.u_skew_sd_co  (.clk_in(\u_core.io_out_29_ ),
     .clk_out(io_out[29]),
     .vccd1(vccd1),
     .vssd1(vssd1),
@@ -1461,7 +1477,15 @@
     \u_core.cfg_clk_ctrl2[2] ,
     \u_core.cfg_clk_ctrl2[1] ,
     \u_core.cfg_clk_ctrl2[0] }));
- clk_skew_adjust \u_core.u_skew_adj_sp_co  (.clk_in(\u_core.io_in_30_ ),
+ clk_skew_adjust \u_core.u_skew_sdram  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_sdram ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[19] ,
+    \u_core.cfg_clk_ctrl1[18] ,
+    \u_core.cfg_clk_ctrl1[17] ,
+    \u_core.cfg_clk_ctrl1[16] }));
+ clk_skew_adjust \u_core.u_skew_sp_co  (.clk_in(\u_core.io_in_30_ ),
     .clk_out(io_out[30]),
     .vccd1(vccd1),
     .vssd1(vssd1),
@@ -1469,6 +1493,38 @@
     \u_core.cfg_clk_ctrl2[10] ,
     \u_core.cfg_clk_ctrl2[9] ,
     \u_core.cfg_clk_ctrl2[8] }));
+ clk_skew_adjust \u_core.u_skew_spi  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_spi ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[15] ,
+    \u_core.cfg_clk_ctrl1[14] ,
+    \u_core.cfg_clk_ctrl1[13] ,
+    \u_core.cfg_clk_ctrl1[12] }));
+ clk_skew_adjust \u_core.u_skew_uart  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_uart ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[11] ,
+    \u_core.cfg_clk_ctrl1[10] ,
+    \u_core.cfg_clk_ctrl1[9] ,
+    \u_core.cfg_clk_ctrl1[8] }));
+ clk_skew_adjust \u_core.u_skew_wh  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_wh ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[27] ,
+    \u_core.cfg_clk_ctrl1[26] ,
+    \u_core.cfg_clk_ctrl1[25] ,
+    \u_core.cfg_clk_ctrl1[24] }));
+ clk_skew_adjust \u_core.u_skew_wi  (.clk_in(\u_core.wbd_clk_int ),
+    .clk_out(\u_core.wbd_clk_wi ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .sel({\u_core.cfg_clk_ctrl1[3] ,
+    \u_core.cfg_clk_ctrl1[2] ,
+    \u_core.cfg_clk_ctrl1[1] ,
+    \u_core.cfg_clk_ctrl1[0] }));
  spim_top \u_core.u_spi_master  (.mclk(\u_core.wbd_clk_spi ),
     .rst_n(\u_core.cfg_glb_ctrl[2] ),
     .wbd_ack_o(\u_core.wbd_spim_ack_i ),
@@ -2302,60 +2358,4 @@
     \u_core.wbd_int_sel_i[2] ,
     \u_core.wbd_int_sel_i[1] ,
     \u_core.wbd_int_sel_i[0] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_glbl  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_glbl ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[23] ,
-    \u_core.cfg_clk_ctrl1[22] ,
-    \u_core.cfg_clk_ctrl1[21] ,
-    \u_core.cfg_clk_ctrl1[20] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_riscv  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_riscv ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[7] ,
-    \u_core.cfg_clk_ctrl1[6] ,
-    \u_core.cfg_clk_ctrl1[5] ,
-    \u_core.cfg_clk_ctrl1[4] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_sdram  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_sdram ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[19] ,
-    \u_core.cfg_clk_ctrl1[18] ,
-    \u_core.cfg_clk_ctrl1[17] ,
-    \u_core.cfg_clk_ctrl1[16] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_spi  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_spi ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[15] ,
-    \u_core.cfg_clk_ctrl1[14] ,
-    \u_core.cfg_clk_ctrl1[13] ,
-    \u_core.cfg_clk_ctrl1[12] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_uart  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_uart ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[11] ,
-    \u_core.cfg_clk_ctrl1[10] ,
-    \u_core.cfg_clk_ctrl1[9] ,
-    \u_core.cfg_clk_ctrl1[8] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_wh  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_wh ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[27] ,
-    \u_core.cfg_clk_ctrl1[26] ,
-    \u_core.cfg_clk_ctrl1[25] ,
-    \u_core.cfg_clk_ctrl1[24] }));
- clk_skew_adjust \u_core.u_wb_skew_adj_wi  (.clk_in(\u_core.wbd_clk_int ),
-    .clk_out(\u_core.wbd_clk_wi ),
-    .vccd1(vccd1),
-    .vssd1(vssd1),
-    .sel({\u_core.cfg_clk_ctrl1[3] ,
-    \u_core.cfg_clk_ctrl1[2] ,
-    \u_core.cfg_clk_ctrl1[1] ,
-    \u_core.cfg_clk_ctrl1[0] }));
 endmodule