commit	4f0afc4051d2573f35243dc0f357e2ebc210bb4c	[log] [tgz]
author	dinesha <dineshannayya@users.noreply.github.com>	Sun Jun 06 09:28:32 2021 +0000
committer	dinesha <dineshannayya@users.noreply.github.com>	Sun Jun 06 09:28:32 2021 +0000
tree	df97a23fd421b162059a73f53d06d6fdbf6c6a20
parent	9e5d826da74b7ba1541c57d7db7bd021ca2c8dce [diff]

1. Initial version of westbone interface files copied from turbo8051 open core project
2. Initial version of RISCV Open core project copied from Syntacore SCR1 package

verilog/rtl/lib/wb_crossbar.v[Added - diff]
verilog/rtl/lib/wb_interface.v[Added - diff]
verilog/rtl/syntacore_scr1/.gitignore[Added - diff]
verilog/rtl/syntacore_scr1/.gitmodules[Added - diff]
verilog/rtl/syntacore_scr1/LICENSE[Added - diff]
verilog/rtl/syntacore_scr1/Makefile[Added - diff]
verilog/rtl/syntacore_scr1/README.md[Added - diff]
verilog/rtl/syntacore_scr1/docs/img/scr1_cluster.svg[Added - diff]
verilog/rtl/syntacore_scr1/docs/scr1_eas.pdf[Added - diff]
verilog/rtl/syntacore_scr1/docs/scr1_um.pdf[Added - diff]
verilog/rtl/syntacore_scr1/src/ahb_top.files[Added - diff]
verilog/rtl/syntacore_scr1/src/axi_tb.files[Added - diff]
verilog/rtl/syntacore_scr1/src/axi_top.files[Added - diff]
verilog/rtl/syntacore_scr1/src/core.files[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_tracelog.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/primitives/scr1_cg.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_ahb.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_arch_description.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_arch_types.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_csr.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_dm.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_hdu.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_ipic.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_memif.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_riscv_isa_decoding.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_scu.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_search_ms1.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_tapc.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_tdu.svh[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dmem_ahb.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dp_memory.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_imem_ahb.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_top_ahb.sv[Added - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv[Added - diff]

59 files changed

tree: df97a23fd421b162059a73f53d06d6fdbf6c6a20

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.