synta core cleanup
diff --git a/verilog/rtl/syntacore/scr1/src/core.files b/verilog/rtl/syntacore/scr1/src/core.files
index f310fe6..5a40ec6 100644
--- a/verilog/rtl/syntacore/scr1/src/core.files
+++ b/verilog/rtl/syntacore/scr1/src/core.files
@@ -25,6 +25,8 @@
core/pipeline/scr1_pipe_ifu.sv
core/pipeline/scr1_pipe_lsu.sv
core/pipeline/scr1_pipe_mprf.sv
+core/pipeline/scr1_pipe_mul.sv
+core/pipeline/scr1_pipe_div.sv
core/pipeline/scr1_pipe_top.sv
core/primitives/scr1_reset_cells.sv
core/primitives/scr1_cg.sv
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
index 60b732f..65a6abb 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
@@ -241,30 +241,30 @@
// Check Core interface
SCR1_SVA_IMEM_WB_BRIDGE_REQ_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
+ @(negedge core_clk) disable iff (~core_rst_n)
!$isunknown(imem_req)
) else $error("IMEM WB bridge Error: imem_req has unknown values");
SCR1_IMEM_WB_BRIDGE_ADDR_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
+ @(negedge core_clk) disable iff (~core_rst_n)
imem_req |-> !$isunknown(imem_addr)
) else $error("IMEM WB bridge Error: imem_addr has unknown values");
SCR1_IMEM_WB_BRIDGE_ADDR_ALLIGN : assert property (
- @(negedge clk) disable iff (~rst_n)
+ @(negedge core_clk) disable iff (~core_rst_n)
imem_req |-> (imem_addr[1:0] == '0)
) else $error("IMEM WB bridge Error: imem_addr has unalign values");
// Check WB interface
SCR1_IMEM_WB_BRIDGE_HREADY_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(hready)
- ) else $error("IMEM WB bridge Error: hready has unknown values");
+ @(negedge core_clk) disable iff (~core_rst_n)
+ !$isunknown(imem_req_ack)
+ ) else $error("IMEM WB bridge Error: imem_req_ack has unknown values");
SCR1_IMEM_WB_BRIDGE_HRESP_XCHECK : assert property (
- @(negedge clk) disable iff (~rst_n)
- !$isunknown(hresp)
- ) else $error("IMEM WB bridge Error: hresp has unknown values");
+ @(negedge core_clk) disable iff (~core_rst_n)
+ !$isunknown(imem_resp)
+ ) else $error("IMEM WB bridge Error: imem_resp has unknown values");
`endif // SCR1_TRGT_SIMULATION
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index 8ddd341..302adda 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -317,7 +317,7 @@
//-------------------------------------------------------------------------------
// SCR1 core instance
//-------------------------------------------------------------------------------
-scr1_core_top u_core_top (
+scr1_core_top i_core_top (
// Common
.pwrup_rst_n (pwrup_rst_n_sync ),
.rst_n (rst_n_sync ),
