Add pattern to dv Makefile and drop obselete openlane wrapper dir

openlane/user_analog_project_wrapper/config.tcl

diff --git a/openlane/user_analog_project_wrapper/config.tcl b/openlane/user_analog_project_wrapper/config.tcl
deleted file mode 100755
index 07f6245..0000000
--- a/openlane/user_analog_project_wrapper/config.tcl
+++ /dev/null
@@ -1,54 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Base Configurations. Don't Touch
-# section begin
-set script_dir [file dirname [file normalize [info script]]]
-
-source $script_dir/../../caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-
-set ::env(DESIGN_NAME) user_analog_project_wrapper
-#section end
-
-# User Configurations
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_analog_project_wrapper.v"
-
-## Clock configurations
-set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET)  "wb_clk_i"
-
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(FP_PDN_CHECK_NODES) 0
-
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0

openlane/user_analog_project_wrapper/pin_order.cfg

diff --git a/openlane/user_analog_project_wrapper/pin_order.cfg b/openlane/user_analog_project_wrapper/pin_order.cfg
deleted file mode 120000
index 267d91c..0000000
--- a/openlane/user_analog_project_wrapper/pin_order.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file

verilog/dv/Makefile

diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 69ad6a8..a9c2027 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = 
+PATTERNS = mprj_por
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \