commit: 5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7
[log] [tgz]
author: Tim Edwards <tim@opencircuitdesign.com>
Thu May 06 11:54:28 2021 -0400
committer: Tim Edwards <tim@opencircuitdesign.com>
Thu May 06 11:54:28 2021 -0400
tree: 3839b58f5e7c2df6cc3bd737b04f59502d7460f7
parent: a26abdd4844c5057f87540780fca689753eab258 [diff]

Added xschem schematic and symbol for the analog project wrapper, and a
script to run netgen LVS against the schematic.

netgen/comp.out[Added - diff]
netgen/run_lvs_wrapper_verilog.sh[Renamed from netgen/run_wrapper.sh - diff]
netgen/run_lvs_wrapper_xschem.sh[Copied from netgen/run_wrapper.sh - diff]
xschem/analog_wrapper_tb.sch[Added - diff]
xschem/analog_wrapper_tb.spice[Added - diff]
xschem/user_analog_project_wrapper.sch[Added - diff]
xschem/user_analog_project_wrapper.spice[Added - diff]
xschem/user_analog_project_wrapper.sym[Added - diff]

8 files changed

tree: 3839b58f5e7c2df6cc3bd737b04f59502d7460f7

README.md

Caravel Analog User

NOTE

Fill this README with your caravel user project documentation.

Refer to README for this sample project documentation.