commit	130720b314677f4a7560f6aa2ba66762c88b9b0c	[log] [tgz]
author	Javier Contreras <jacontreras5@uc.cl>	Thu Dec 30 12:47:10 2021 -0300
committer	Javier Contreras <jacontreras5@uc.cl>	Thu Dec 30 12:47:10 2021 -0300
tree	f02e19c12a9564ae6a800551a2666a9c3f7a4ce4
parent	656a5d2eed1c541084f0beaa57cbd433d5f3d4b4 [diff]

Netlist & remove verilog

info.yaml[Deleted - diff]
netgen/user_analog_project_wrapper.spice[diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/mprj_por/Makefile[Deleted - diff]
verilog/dv/mprj_por/mprj_por.c[Deleted - diff]
verilog/dv/mprj_por/mprj_por_tb.v[Deleted - diff]
verilog/rtl/example_por.v[Deleted - diff]
verilog/rtl/uprj_analog_netlists.v[Deleted - diff]
verilog/rtl/user_analog_proj_example.v[Deleted - diff]
verilog/rtl/user_analog_project_wrapper.v[Deleted - diff]

11 files changed

tree: f02e19c12a9564ae6a800551a2666a9c3f7a4ce4

README.md

Sky130 RadTol Test Chip

Purpose

Validate models for standard transistors
Study enclosed-layout transistors
Study performance variations due to total ionizing radiation
Benchmark soft error rates using a shift register

Design

To-do

Refer to README for this sample project documentation.