update gds

gds/user_analog_project_wrapper.gds

diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 09cad70..ad85bd6 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ

verilog/rtl/user_analog_project_wrapper.v

diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index bd6a843..ee1766f 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -122,8 +122,8 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-//user_analog_proj_example mprj (
-rram_LUT2 mprj (
+user_analog_proj_example mprj (
+//rram_LUT2 mprj (
     `ifdef USE_POWER_PINS
         .vdda1(vdda1),  // User area 1 3.3V power
         .vdda2(vdda2),  // User area 2 3.3V power