| commit | 78f10993515bf07c037c7451ce029555a266f63e | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Tue Jan 04 16:56:01 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Tue Jan 04 16:56:01 2022 +0000 |
| tree | 062a41e6cb28d0cc0cf4675e7b07a5d22a04d46a | |
| parent | 5ff7854097d150832078bd953f4fc48fcbd1163b [diff] |
update gds
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index c42ac41..09cad70 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v index a4a8c1a..bd6a843 100644 --- a/verilog/rtl/user_analog_project_wrapper.v +++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -122,7 +122,8 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_analog_proj_example mprj ( +//user_analog_proj_example mprj ( +rram_LUT2 mprj ( `ifdef USE_POWER_PINS .vdda1(vdda1), // User area 1 3.3V power .vdda2(vdda2), // User area 2 3.3V power