| commit | 3272392052ef4e9e2c938cea8e4ea558f3b02c7d | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sun Jan 09 08:41:43 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sun Jan 09 08:41:43 2022 -0800 |
| tree | c1efcf5759684782394dc2859922f8e41640d5b5 | |
| parent | 4a6cbcce7d88042de1b4d68e1a8257cb1935035e [diff] |
final gds oasis
Proposed project implement WPT system having the capability of a passive backscattering using the single power transfer coils. The design goal of project will be to implement an on-chip resonant WPT system that capable of harvesting energy from external off chip coils, harvest the megnteic energy using an active recitifier and derive a load.
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Wireless Power Transmission (WPT) is realized using resonant coils. Primary and Secondary coils are loaded with capacitors which are tuned at same frequency. Despite of low coupling coefficients MCR-WPT provides high power transfer at a single resonant frequency . Active rectification was used technique for improving the efficiency of rectification by replacing diodes with actively controlled switches with or power bipolar junction transistors. Normal semiconductor diodes have a roughly fixed voltage drop of around 0.5-1 volts, active rectifiers behave as resistances, and can have arbitrarily low voltage drop. The voltage drop across the transistor is then much lower, which reduces the power loss. Finally an off chip ‘backscattered signal’ is used to change the impedence of coils.
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TDD (Time division duplexing) RF front ends operate in such a manner that during Transmission, receiver side is isolated using and switch and power amplifier is driving the transmission antenna, During Reception, transmitter chain is isolated and the received signal from the antenna is fed to a low noise amplifier.
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Figure below shows the 2-stage amplifier that is used to provide voltage gain in the circuit. In the first stage Transistors M0 and M1 provide transconductance. Transistor M1 also reduces current through M2 and increases the value of Resistor and drain of M2. Due to this cascode and current re-use technique we obtain a large voltage gain. Transistor M4 is used to provide voltage to current feedback from output to input such that the input impedance is governed transistor M4. Transistor M5 establishes bias voltage for the gate of M0. The second stage combines the differential output from stage 1 in such a way that the noise contribution of transistor M4 is cancelled.
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Operational Amplifier is a fundamental analog circuit that is used in numerous applications. A conventional two stage opamp is implemented to be tested on chip and be further used in ADC circuits.
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Differential Gain 60 dB
Common Mode Gain 5 dB CMRR 55 dB Voltage $\pm \ 0.9$ V GBW 190MHz Phase Margin 55 Degrees
Bandgap Reference (BGR) is general purpose IP block that generates a constant dc voltage independent of all variations including supply, temperature and process. Analog circuits such as opamps, DC-DC converters, voltage control oscillators (VCO) and current mirrors used voltage references extensively. The figure of merit for these systems mainly depends on the accuracy and preciseness of voltage reference.
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Schematic:
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Explanation:
The proposed first order BGR is auto start which eliminates the start-up circuit. The cascode structure is designed to give a large swing, which is not limited by the supply voltage headroom. This design does not need a bias circuit. The VDS voltage of MN1 and MN2 is utilized to create the bias voltage for MP5 and MP4 instead of employing a PMOS transistor. So, a complementary cross-coupled structure is designed instead of simple cascode to create the V_Bias (at node B) voltage by itself, as illustrated in Fig. 1-1. Furthermore, this architecture improves the gain of cascode stage and accurately mirrors the PTAT, improving the temperature coefficient and minimising the mismatches between node X and Y.
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V ref 1.21 V
Temperature Range -40 ^o^C to 140 ^o^C Supply voltage 2.5 to 4 V Temperature Coefficient 10 ppm/°C Lin regulation 8 mV Start-up time 40 µS
