final gds oasis
88 files changed
tree: 740266b9f30402c97858f4d6176c52b05c74cae3
  1. .github/
  2. docs/
  3. gds/
  4. Images/
  5. jobs/
  6. mag/
  7. netgen/
  8. oas/
  9. openlane/
  10. signoff/
  11. verilog/
  12. xschem/
  13. .gitignore
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. pll_full.mag
  18. README.md
  19. ro_div.mag
README.md

CMOS frequency synthesizer

This project contains a 2.87 GHz fractional-N frequency synthesizer based microwave generator in skywater 130nm technology. This frequency synthersizer makes use of a phase locked loop to produce the output frequency. The PLL consists of a phase detector, charge pump, loop filter, varactor based 3 stage voltage controlled oscillator and multi-modulus divider.

Project implementation

The figure below shows the block diagram for the 2.87 GHz fractional-N sythesizer implemented in skywater 130nm tecnology.
PLL loop

Simulation results

To validate our circuit, we have tested it in 180 nm technology and the results for the same are shown in the figure below.

Phase Frequency Detector

Voltage controlled Oscillator

Fractional-N divider

Sources

This repository mainly contains all the required building blocks for the implementation of the PLL(gds/mag/netlists). We have the complete fractional-N PLL loop, individual blocks - PFD, fresctional-N divider, VCO, charge pump and loop filter. In addition to these we have combinations of phase dectector - divider and VCO - divider.

DOCUMENTATION UNDER DEVELOPMENT