updated
diff --git a/gds/and.ext b/gds/and.ext
index 25d194d..242234d 100644
--- a/gds/and.ext
+++ b/gds/and.ext
@@ -27,10 +27,13 @@
node "out1" 6488 1253.5 280 -220 li 0 0 0 0 0 0 0 0 32000 960 83200 2400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3340 0 0 136500 4640 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 1983 2469.6 -170 880 nw 0 0 0 0 823200 3640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n126_n696#" 0 0 -126 -696 pw 310384 2388 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "OUT" 2.3125
cap "gnd!" "Z1" 409.78
cap "OUT" "Z1" 43.6452
cap "OUT" "gnd!" 198
cap "B" "Z1" 67.1786
+cap "VDD" "vdd!" 48.86
+cap "VDD" "out1" 6.1975
cap "A" "gnd!" 57.75
cap "B" "OUT" 8.8
cap "vdd!" "Z1" 7.96552
@@ -42,12 +45,9 @@
cap "out1" "OUT" 261.752
cap "vdd!" "B" 13.5882
cap "vdd!" "A" 13.5882
-cap "VDD" "OUT" 2.3125
cap "out1" "B" 176.792
cap "out1" "A" 13.5179
cap "out1" "vdd!" 1441.54
-cap "VDD" "vdd!" 48.86
-cap "VDD" "out1" 6.1975
device msubckt sky130_fd_pr__nfet_01v8 480 -670 481 -669 l=30 w=300 "w_n126_n696#" "out1" 60 0 "gnd!" 300 0 "OUT" 300 0
device msubckt sky130_fd_pr__nfet_01v8 230 -670 231 -669 l=30 w=400 "w_n126_n696#" "B" 60 0 "Z1" 400 0 "out1" 400 0
device msubckt sky130_fd_pr__nfet_01v8 -20 -670 -19 -669 l=30 w=400 "w_n126_n696#" "A" 60 0 "gnd!" 400 0 "Z1" 400 0
diff --git a/gds/cbank.ext b/gds/cbank.ext
index b96a4ae..78a2e26 100644
--- a/gds/cbank.ext
+++ b/gds/cbank.ext
@@ -35,17 +35,17 @@
node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd!" 0 0 4950 -1370 li 415872 7104 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
cap "a_2730_n30#" "li_1720_n30#" 199.5
+cap "v" "li_1720_n30#" 1301.39
cap "a_1720_n30#" "li_1720_n30#" 18.13
+cap "a_2730_n30#" "v" 1301.39
cap "a_6660_n30#" "v" 1301.39
cap "a_5640_n30#" "v" 1301.39
cap "a_5640_n30#" "a_6660_n30#" 191.52
cap "a_4660_n30#" "v" 1301.39
cap "a_3680_n30#" "v" 1301.39
-cap "a_4660_n30#" "a_5640_n30#" 199.5
-cap "a_2730_n30#" "v" 1301.39
-cap "a_3680_n30#" "a_4660_n30#" 199.5
cap "a_2730_n30#" "a_3680_n30#" 199.5
-cap "v" "li_1720_n30#" 1301.39
+cap "a_4660_n30#" "a_5640_n30#" 199.5
+cap "a_3680_n30#" "a_4660_n30#" 199.5
device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1856 0 "a_6660_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1856 0 "a_5640_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1856 0 "a_4660_n30#" 1440 0
@@ -54,19 +54,19 @@
device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1856 0 "li_1720_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3616 0 "gnd!" 1440 0
cap "switch_4/vin" "switch_4/vout" -0.157143
+cap "a0" "switch_5/vin" 83.635
cap "a1" "switch_4/vin" -183.5
cap "a0" "switch_5/vout" 4.23077
-cap "a0" "switch_5/vin" 83.635
-cap "a1" "switch_4/vout" 4.23077
cap "a1" "switch_4/vin" 83.635
-cap "a2" "switch_3/vout" 4.23077
-cap "a2" "switch_3/vin" 83.635
-cap "switch_2/vout" "a3" 4.23077
-cap "switch_2/vin" "a3" 83.635
+cap "switch_3/vout" "a2" 4.23077
+cap "switch_3/vin" "a2" 83.635
+cap "switch_4/vout" "a1" 4.23077
+cap "a3" "switch_2/vout" 4.23077
+cap "a3" "switch_2/vin" 83.635
+cap "switch_1/vout" "a4" 4.23077
+cap "switch_1/vin" "a4" 83.635
+cap "a5" "switch_0/vout" 4.23077
cap "a5" "switch_0/vin" 83.635
-cap "a4" "switch_1/vout" 4.23077
-cap "a4" "switch_1/vin" 83.635
-cap "switch_0/vout" "a5" 4.23077
merge "switch_0/vout" "switch_0/w_n216_n26#" -343.969 -1102432 -12828 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -29100 -494 0 0 0 0
merge "switch_0/w_n216_n26#" "switch_2/vout"
merge "switch_2/vout" "switch_2/w_n216_n26#"
diff --git a/gds/cp.ext b/gds/cp.ext
index f84eca9..8ef9721 100644
--- a/gds/cp.ext
+++ b/gds/cp.ext
@@ -27,22 +27,22 @@
node "vdd!" 18302 139352 4230 3990 li 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0
substrate "gnd!" 0 0 4280 -3300 li 16003824 41948 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0
cap "a_10_n50#" "vbias" 192.9
-cap "vdd!" "a_7110_0#" 42.55
-cap "vdd!" "a_3060_n2840#" 320.4
-cap "upbar" "down" 20.625
-cap "a_1710_0#" "down" 320.4
-cap "a_1710_n2840#" "out" 606.81
+cap "a_7110_0#" "vdd!" 42.55
+cap "a_6370_0#" "vdd!" 402.828
+cap "a_3060_0#" "vdd!" 1788.27
+cap "down" "a_1710_0#" 320.4
+cap "a_3060_n2840#" "vdd!" 320.4
+cap "down" "upbar" 20.625
cap "out" "a_1710_0#" 841.733
-cap "vdd!" "out" 376.075
-cap "upbar" "a_1710_n2840#" 291.6
cap "a_1710_n2840#" "a_1710_0#" 828.847
-cap "vdd!" "a_1710_n2840#" 254.08
cap "a_10_n50#" "a_1710_0#" 41.6842
-cap "vdd!" "a_6370_0#" 402.828
-cap "vdd!" "a_10_n50#" 530.297
-cap "vdd!" "a_3060_0#" 1788.27
-cap "vdd!" "upbar" 149.92
-cap "vdd!" "a_1710_0#" 714.147
+cap "a_1710_n2840#" "out" 606.81
+cap "a_1710_0#" "vdd!" 714.147
+cap "out" "vdd!" 376.075
+cap "a_1710_n2840#" "vdd!" 254.08
+cap "upbar" "a_1710_n2840#" 291.6
+cap "a_10_n50#" "vdd!" 530.297
+cap "upbar" "vdd!" 149.92
device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/gds/divider.ext b/gds/divider.ext
index cb767ce..803759d 100644
--- a/gds/divider.ext
+++ b/gds/divider.ext
@@ -51,243 +51,242 @@
node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0
node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0
substrate "w_n966_n46#" 0 0 -966 -46 pw 2535060 32560 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0
-cap "li_5740_3250#" "li_5560_680#" 21.9534
-cap "li_5740_3250#" "li_3980_680#" 22.5
-cap "mc2" "m1_5770_3360#" 35.7143
-cap "mc2" "li_7140_680#" 61.52
-cap "li_5740_3250#" "li_5460_820#" 128.305
-cap "w_2780_1920#" "m1_5770_3360#" 53.84
-cap "li_6130_3350#" "li_5740_3250#" 68.1032
-cap "mc2" "li_5740_3250#" 22.679
-cap "w_2780_1920#" "li_3310_1810#" 24.0375
-cap "w_2780_1920#" "li_5740_3250#" 72.945
-cap "w_2780_1920#" "li_6130_3350#" 7.215
-cap "w_2780_1920#" "li_2870_2670#" 76.8485
-cap "vdd" "vdd" 33.5
-cap "vdd" "vdd" 51.2353
-cap "vdd" "vdd" 20.1
-cap "li_5560_680#" "m4_7020_30#" 24.425
-cap "li_3980_680#" "gnd" 24.425
-cap "li_3980_680#" "gnd" 27.1625
-cap "li_5740_3250#" "vdd" 27.9
-cap "li_3310_1810#" "vdd" 35.39
-cap "li_5740_3250#" "vdd" 27.9
+cap "w_2780_1920#" "vdd" 8.88
cap "li_7140_680#" "m1_5770_3360#" 19.2857
cap "li_5560_680#" "m1_5770_3360#" 16.875
cap "li_5560_680#" "li_7140_680#" 437.5
-cap "w_2780_1920#" "m4_7030_1860#" 40.0711
-cap "w_2780_1920#" "vdd" 0.84
cap "li_7040_820#" "m1_5770_3360#" 90
cap "li_3980_680#" "li_5560_680#" 782.5
cap "Out" "li_7140_680#" 23.5
-cap "w_2780_1920#" "vdd" 9.82
-cap "w_2780_1920#" "vdd" 4.08
+cap "w_2780_1920#" "m1_5770_3360#" 53.84
cap "li_7040_820#" "li_5560_680#" 15
-cap "w_2780_1920#" "vdd" 8.88
cap "li_5740_3250#" "m1_5770_3360#" 286.375
cap "mc2" "gnd" 27.9
cap "li_5460_820#" "li_3980_680#" 20
cap "li_6130_3350#" "m1_5770_3360#" 136.842
-cap "w_n966_n46#" "prescaler_0/nand_1/A" 17.3684
+cap "li_5740_3250#" "li_5560_680#" 21.9534
+cap "li_5740_3250#" "li_3980_680#" 22.5
+cap "vdd" "vdd" 33.5
+cap "vdd" "vdd" 51.2353
+cap "mc2" "m1_5770_3360#" 35.7143
+cap "w_2780_1920#" "li_3310_1810#" 24.0375
+cap "mc2" "li_7140_680#" 61.52
+cap "vdd" "vdd" 20.1
+cap "w_2780_1920#" "li_5740_3250#" 72.945
+cap "li_5740_3250#" "li_5460_820#" 128.305
+cap "w_2780_1920#" "li_6130_3350#" 7.215
+cap "li_5560_680#" "m4_7020_30#" 24.425
+cap "w_2780_1920#" "li_2870_2670#" 76.8485
+cap "li_3980_680#" "gnd" 24.425
+cap "li_6130_3350#" "li_5740_3250#" 68.1032
+cap "li_3980_680#" "gnd" 27.1625
+cap "mc2" "li_5740_3250#" 22.679
+cap "w_2780_1920#" "m4_7030_1860#" 40.0711
+cap "w_2780_1920#" "vdd" 0.84
+cap "w_2780_1920#" "vdd" 9.82
+cap "w_2780_1920#" "vdd" 4.08
+cap "li_5740_3250#" "vdd" 27.9
+cap "li_3310_1810#" "vdd" 35.39
+cap "li_5740_3250#" "vdd" 27.9
+cap "prescaler_0/nand_1/A" "w_n966_n46#" 17.3684
+cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/tspc_2/a_630_n680#" 9.78378
cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/GND" 21.945
cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/tspc_2/Z2" 27.6618
-cap "prescaler_0/tspc_2/a_630_n680#" "prescaler_0/nand_1/w_n46_n476#" 9.78378
cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/Z2" 27.6618
cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/GND" 30.14
-cap "tspc_0/Z4" "tspc_0/D" 35.0633
-cap "tspc_0/Z2" "tspc_0/D" 141.466
-cap "gnd" "tspc_0/D" 413.181
-cap "tspc_0/Z3" "tspc_0/D" 1.36364
-cap "tspc_0/Z2" "prescaler_0/tspc_1/w_n146_n706#" 27.6618
-cap "prescaler_0/tspc_1/a_630_n680#" "prescaler_0/tspc_1/w_n146_n706#" 4.89189
-cap "gnd" "prescaler_0/tspc_1/w_n146_n706#" 21.945
-cap "gnd" "tspc_0/w_n140_n70#" 0.12
-cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
-cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
+cap "tspc_0/D" "tspc_0/Z4" 35.0633
+cap "tspc_0/D" "tspc_0/Z2" 141.466
cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
-cap "tspc_0/a_740_n680#" "tspc_0/Q" 145.525
-cap "tspc_0/Q" "tspc_1/D" 70.641
-cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
-cap "tspc_1/w_n140_n70#" "tspc_0/Q" 5.55112e-17
-cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
+cap "tspc_0/w_n140_n70#" "gnd" 0.12
+cap "prescaler_0/tspc_1/w_n146_n706#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
+cap "prescaler_0/tspc_1/w_n146_n706#" "gnd" 21.945
+cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
+cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
+cap "tspc_0/D" "gnd" 413.181
+cap "tspc_0/D" "tspc_0/Z3" 1.36364
+cap "prescaler_0/tspc_1/w_n146_n706#" "tspc_0/Z2" 27.6618
+cap "gnd" "tspc_1/Z2" 7.81579
+cap "tspc_0/Q" "tspc_1/w_n140_n70#" 5.55112e-17
cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583
-cap "tspc_1/Z4" "tspc_1/D" 33.0938
cap "tspc_0/a_740_n680#" "gnd" 281.141
-cap "tspc_1/Z2" "tspc_1/D" 213.298
-cap "tspc_0/a_630_n680#" "tspc_1/D" 5.45455
-cap "gnd" "tspc_1/D" 346.096
-cap "tspc_1/Z4" "tspc_0/Q" 30.4615
-cap "tspc_1/Z2" "tspc_0/Q" 25.8231
-cap "gnd" "tspc_0/Q" 21.2143
-cap "w_n966_n46#" "tspc_1/Z2" 27.6618
+cap "tspc_1/D" "tspc_0/a_630_n680#" 5.45455
+cap "tspc_1/D" "gnd" 346.096
+cap "tspc_0/Q" "gnd" 21.2143
cap "w_n966_n46#" "tspc_0/a_630_n680#" 9.78378
cap "w_n966_n46#" "gnd" 23.265
-cap "gnd" "tspc_1/Z2" 7.81579
+cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
+cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
+cap "tspc_1/D" "tspc_1/Z4" 33.0938
+cap "tspc_1/D" "tspc_1/Z2" 213.298
+cap "tspc_0/Q" "tspc_1/Z4" 30.4615
+cap "tspc_0/Q" "tspc_1/Z2" 25.8231
cap "gnd" "tspc_0/a_630_n680#" 7.61538
+cap "w_n966_n46#" "tspc_1/Z2" 27.6618
cap "tspc_1/D" "tspc_1/Z3" 1.36364
-cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795
+cap "tspc_1/D" "tspc_0/a_740_n680#" -7.31795
+cap "tspc_0/Q" "tspc_0/a_740_n680#" 145.525
+cap "tspc_0/Q" "tspc_1/D" 70.641
+cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
+cap "w_n966_n46#" "tspc_1/a_630_n680#" 9.78378
+cap "tspc_1/GND" "tspc_1/a_630_n680#" 7.61538
+cap "tspc_1/a_740_n680#" "tspc_2/w_n140_n70#" 0.065
+cap "w_n966_n46#" "tspc_1/GND" 30.14
+cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
cap "tspc_2/D" "tspc_1/GND" 339.551
cap "w_n966_n46#" "tspc_2/Z2" 12.6176
cap "tspc_1/GND" "tspc_2/Z2" 7.81579
-cap "tspc_1/a_740_n680#" "tspc_1/Q" 155.525
-cap "tspc_2/D" "tspc_2/Z3" 0.681818
-cap "tspc_2/D" "tspc_2/Z4" 20.0553
-cap "tspc_1/a_740_n680#" "tspc_2/w_n140_n70#" 0.065
-cap "tspc_2/D" "tspc_2/Z2" 309.898
cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107
cap "tspc_1/Q" "tspc_1/GND" 21.2143
+cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "tspc_2/D" "tspc_2/Z4" 20.0553
cap "tspc_1/a_740_n680#" "tspc_1/GND" 440.385
-cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
+cap "tspc_2/D" "tspc_2/Z2" 309.898
cap "tspc_1/Q" "tspc_2/D" 70.641
-cap "w_n966_n46#" "tspc_1/GND" 30.14
-cap "w_n966_n46#" "tspc_1/a_630_n680#" 9.78378
+cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
cap "tspc_1/Q" "tspc_2/Z4" 30.4615
cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882
-cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
cap "tspc_1/Q" "tspc_2/Z2" 25.8231
-cap "tspc_1/GND" "tspc_1/a_630_n680#" 7.61538
-cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
+cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
+cap "tspc_1/a_740_n680#" "tspc_1/Q" 155.525
+cap "tspc_2/D" "tspc_1/Q" -1.77636e-15
+cap "Out" "tspc_2/D" 20.775
+cap "tspc_2/Z4" "li_5560_680#" 10.5882
cap "tspc_2/a_630_n680#" "tspc_2/D" 159.583
cap "tspc_2/GND" "tspc_2/D" 450.398
cap "tspc_2/Z4" "tspc_2/D" 17.815
cap "tspc_2/a_630_n680#" "tspc_1/w_n146_n706#" 9.78378
cap "tspc_2/GND" "tspc_1/w_n146_n706#" 23.265
cap "tspc_2/Z2" "tspc_1/w_n146_n706#" 15.0441
-cap "tspc_2/Z4" "li_5560_680#" 10.5882
-cap "Out" "tspc_2/D" 20.775
-cap "tspc_2/Z3" "tspc_2/D" 0.681818
-cap "tspc_2/D" "tspc_1/Q" -1.77636e-15
-cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 78.0797
-cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/A" 12.2938
-cap "w_n966_n46#" "prescaler_0/nand_1/A" 14.7632
-cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/OUT" -2.84217e-14
-cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/vdd!" 4.57853
+cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "prescaler_0/mc1" "prescaler_0/nand_1/VDD" 78.0797
+cap "prescaler_0/nand_1/OUT" "prescaler_0/nand_1/VDD" -2.84217e-14
+cap "prescaler_0/tspc_0/vdd!" "prescaler_0/nand_1/VDD" 4.57853
+cap "prescaler_0/nand_1/A" "prescaler_0/nand_1/VDD" 12.2938
+cap "prescaler_0/nand_1/A" "w_n966_n46#" 14.7632
cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557
cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557
-cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z2" -1.77636e-15
-cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 2.73
-cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z1" 3.19744e-14
-cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 73.8879
-cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/a_280_n230#" 16.0962
+cap "prescaler_0/tspc_2/Z2" "prescaler_0/nand_1/VDD" -1.77636e-15
+cap "prescaler_0/mc1" "prescaler_0/nand_1/VDD" 2.73
+cap "prescaler_0/tspc_2/Z1" "prescaler_0/nand_1/VDD" 3.19744e-14
cap "prescaler_0/tspc_1/Z3" "prescaler_0/nand_0/VDD" -2.37588e-14
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 73.8879
cap "prescaler_0/tspc_1/Z1" "prescaler_0/nand_0/VDD" 3.55271e-15
cap "prescaler_0/tspc_1/Z2" "prescaler_0/nand_0/VDD" -4.61853e-14
-cap "vdd" "and_0/OUT" 7.5
+cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/a_280_n230#" 16.0962
+cap "vdd" "prescaler_0/GND" 244.839
cap "vdd" "prescaler_0/mc1" 4.79032
+cap "vdd" "prescaler_0/tspc_1/Q" 19.25
+cap "vdd" "and_0/OUT" 7.5
+cap "vdd" "prescaler_0/tspc_1/a_740_n680#" 114.95
cap "vdd" "tspc_0/Z2" 10
cap "vdd" "tspc_0/Z1" 8.88178e-14
-cap "vdd" "prescaler_0/tspc_1/Q" 19.25
-cap "vdd" "prescaler_0/GND" 244.839
-cap "vdd" "prescaler_0/tspc_1/a_740_n680#" 114.95
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927
cap "nor_0/VDD" "vdd" -3.46
+cap "tspc_0/a_740_n680#" "tspc_0/Q" 75.365
cap "vdd" "tspc_0/Q" 93.7845
+cap "tspc_0/Q" "tspc_1/Z1" 7
cap "nor_0/VDD" "tspc_0/a_740_n680#" 4.63
cap "vdd" "tspc_0/a_740_n680#" 177.528
-cap "tspc_0/a_740_n680#" "tspc_0/Q" 75.365
-cap "tspc_0/Q" "tspc_1/Z1" 7
-cap "nor_0/VDD" "vdd" 224.245
+cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927
cap "tspc_1/Q" "tspc_2/Z1" 7
cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351
cap "tspc_1/a_740_n680#" "tspc_1/Q" 75.365
cap "nor_0/VDD" "tspc_2/Z2" 7.54952e-15
cap "nor_0/VDD" "tspc_2/Z1" 2.25375e-14
-cap "nor_0/VDD" "tspc_1/Z3" -2.37588e-14
cap "nor_0/VDD" "tspc_1/Q" 93.7845
+cap "nor_0/VDD" "tspc_1/Z3" -2.37588e-14
cap "nor_0/VDD" "tspc_1/Z2" -2.57572e-14
-cap "vdd" "tspc_1/a_740_n680#" 13.3333
cap "nor_0/VDD" "tspc_1/a_740_n680#" 76.5957
-cap "tspc_2/Z1" "tspc_2/vdd!" -1.86517e-14
-cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125
+cap "vdd" "tspc_1/a_740_n680#" 13.3333
+cap "nor_0/VDD" "vdd" 224.245
cap "tspc_2/Z3" "tspc_2/vdd!" -2.37588e-14
cap "Out" "tspc_2/vdd!" 5.9508e-14
cap "tspc_2/Z2" "tspc_2/vdd!" -2.13163e-14
+cap "tspc_2/Z1" "tspc_2/vdd!" -1.86517e-14
+cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125
cap "prescaler_0/tspc_0/vdd!" "w_n140_1520#" 6.56545
cap "w_n140_1520#" "prescaler_0/tspc_0/Q" 27.2014
-cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 9.75806
-cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Q" 9.57252
-cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/a_300_n150#" 5.55112e-16
-cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Z3" -1.15019e-13
-cap "mc2" "prescaler_0/tspc_0/a_630_n680#" 328.675
-cap "mc2" "prescaler_0/GND" 319.267
cap "mc2" "prescaler_0/tspc_0/Z2" 126.915
cap "prescaler_0/tspc_0/a_630_n680#" "prescaler_0/tspc_0/w_n146_n706#" 5.04167
cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 12.1359
-cap "mc2" "prescaler_0/tspc_0/Z2" -393.365
-cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 19.9143
+cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Q" 9.57252
+cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/a_300_n150#" 5.55112e-16
+cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Z3" -1.15019e-13
+cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 9.75806
+cap "prescaler_0/tspc_0/a_630_n680#" "mc2" 328.675
+cap "prescaler_0/GND" "mc2" 319.267
cap "prescaler_0/nand_0/a_280_n230#" "prescaler_0/nand_0/VDD" 34.0634
cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 3.58696
-cap "prescaler_0/nand_0/OUT" "prescaler_0/nand_0/VDD" 5.68434e-14
+cap "prescaler_0/nand_0/OUT" "prescaler_0/nand_0/VDD" 1.13687e-13
+cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 4.5
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 19.9143
cap "prescaler_0/GND" "mc2" 127.942
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z2" 1.66533e-15
-cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5
+cap "prescaler_0/tspc_0/Z2" "mc2" -393.365
+cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566
+cap "and_0/OUT" "gnd" 22.72
+cap "and_0/VDD" "gnd" 23.0856
+cap "w_n966_n46#" "and_0/Z1" 5.5
+cap "and_0/out1" "and_0/OUT" 48.6223
+cap "w_n966_n46#" "gnd" 1.50595
+cap "and_0/VDD" "and_0/OUT" 0.870968
+cap "w_n966_n46#" "and_0/OUT" 3.20833
+cap "w_n966_n46#" "and_0/out1" 3.20833
cap "and_0/Z1" "mc2" 74.215
cap "gnd" "mc2" 117.19
cap "and_0/OUT" "mc2" 46.015
cap "and_0/B" "mc2" 13.94
cap "and_0/OUT" "vdd" 39.6
cap "and_0/out1" "mc2" 59.955
-cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566
-cap "and_0/OUT" "gnd" 22.72
-cap "and_0/VDD" "gnd" 23.0856
-cap "w_n966_n46#" "and_0/Z1" 5.5
-cap "and_0/out1" "and_0/OUT" 48.6223
-cap "w_n966_n46#" "and_0/OUT" 3.20833
-cap "w_n966_n46#" "gnd" 1.50595
-cap "and_0/VDD" "and_0/OUT" 0.870968
-cap "w_n966_n46#" "and_0/out1" 3.20833
+cap "mc2" "nor_1/Out" 161.385
+cap "nor_1/Z1" "nor_1/Out" 22.8782
+cap "vdd" "nor_0/Out" 90.78
+cap "nor_1/Z1" "nor_0/Out" 181.56
+cap "nor_0/gnd!" "nor_1/Out" 16.9459
+cap "nor_1/A" "nor_0/Out" 15.1125
+cap "nor_1/B" "nor_0/Out" 84.4673
+cap "nor_1/A" "nor_0/VDD" 0.99
cap "and_0/Z1" "mc2" -164.32
+cap "nor_1/B" "nor_1/Out" 13.2
cap "nor_0/gnd!" "mc2" 364.635
cap "nor_1/A" "mc2" 12.84
cap "nor_1/B" "mc2" 12.84
cap "nor_1/A" "nor_0/gnd!" 1.28205
-cap "nor_1/Out" "mc2" 161.385
-cap "nor_1/Out" "nor_1/Z1" 22.8782
-cap "nor_0/Out" "vdd" 90.78
-cap "nor_0/Out" "nor_1/Z1" 181.56
-cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667
-cap "and_0/w_n126_n696#" "nor_0/gnd!" 2.91667
-cap "nor_1/B" "nor_0/B" 2.64706
-cap "nor_1/Out" "nor_0/gnd!" 16.9459
-cap "nor_1/B" "nor_1/A" 58.3333
-cap "nor_0/Out" "nor_1/A" 15.1125
-cap "nor_0/VDD" "nor_1/A" 0.99
cap "and_0/w_n126_n696#" "nor_1/Out" 7
-cap "nor_1/Out" "nor_1/B" 13.2
-cap "nor_0/Out" "nor_1/B" 84.4673
+cap "nor_1/B" "nor_0/B" 2.64706
+cap "nor_1/B" "nor_1/A" 58.3333
+cap "and_0/Z1" "and_0/w_n126_n696#" 0.916667
+cap "nor_0/gnd!" "and_0/w_n126_n696#" 2.91667
cap "nor_0/Out" "nor_1/Out" 90.78
cap "nor_0/VDD" "nor_0/Out" 4.29
+cap "nor_1/B" "vdd" 90.78
+cap "nor_0/GND" "nor_1/w_n66_n446#" 2
+cap "nor_0/Out" "nor_1/w_n66_n446#" 7
+cap "nor_1/B" "nor_0/Out" 90.78
+cap "nor_1/B" "nor_0/A" 15.1125
+cap "nor_1/B" "nor_0/B" 17.7596
+cap "nor_1/B" "nor_0/VDD" -7.41
cap "nor_0/A" "nor_0/Out" 180.039
cap "nor_0/A" "nor_0/GND" 305.362
cap "nor_0/B" "nor_0/Out" 41.7957
cap "nor_0/VDD" "nor_0/Out" 4.29
cap "nor_0/B" "nor_0/A" 14.5768
-cap "nor_1/w_n66_n446#" "nor_0/Out" 7
-cap "nor_1/w_n66_n446#" "nor_0/GND" 2
cap "nor_0/Z1" "nor_1/B" 181.56
-cap "nor_1/B" "vdd" 90.78
-cap "nor_1/B" "nor_0/Out" 90.78
-cap "nor_1/B" "nor_0/A" 15.1125
-cap "nor_1/B" "nor_0/B" 17.7596
-cap "nor_1/B" "nor_0/VDD" -7.41
-cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 9.75806
-cap "prescaler_0/tspc_0/a_630_n680#" "prescaler_0/tspc_0/w_n146_n706#" 5.04167
-cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 12.1359
-cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 3.58696
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/a_630_n680#" 5.04167
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 12.1359
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 9.75806
cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 3.58696
+cap "gnd" "w_n966_n46#" 9.75595
cap "w_n966_n46#" "and_0/OUT" 3.20833
cap "and_0/Z1" "w_n966_n46#" 5.5
cap "and_0/out1" "w_n966_n46#" 3.20833
-cap "gnd" "w_n966_n46#" 9.75595
-cap "nor_0/gnd!" "mc2" 41.6667
-cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667
-cap "and_0/w_n126_n696#" "nor_0/gnd!" 29.5
+cap "and_0/Z1" "and_0/w_n126_n696#" 0.916667
+cap "nor_0/gnd!" "and_0/w_n126_n696#" 29.5
cap "and_0/w_n126_n696#" "nor_1/Out" 7
-cap "nor_0/GND" "mc2" 41.6667
+cap "nor_0/gnd!" "mc2" 41.6667
cap "nor_1/w_n66_n446#" "nor_0/Out" 7
cap "nor_1/w_n66_n446#" "nor_0/GND" 20.3333
+cap "nor_0/GND" "mc2" 41.6667
merge "nor_1/gnd!" "nor_0/GND" -277.358 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34184 -2250 0 0 0 0
merge "nor_0/GND" "nor_1/GND"
merge "nor_1/GND" "nor_0/gnd!"
diff --git a/gds/nand.ext b/gds/nand.ext
index 6c1b916..2995280 100644
--- a/gds/nand.ext
+++ b/gds/nand.ext
@@ -22,22 +22,22 @@
node "A" 1521 380.56 -50 -210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 2060 0 0 9600 480 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 1727 1248 -80 520 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n46_n476#" 0 0 -46 -476 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "A" "a_280_n230#" 81.6947
+cap "z1" "a_280_n230#" 70.125
+cap "z1" "A" 8.25
+cap "gnd!" "A" 57.75
+cap "OUT" "a_280_n230#" 150.608
+cap "vdd!" "a_280_n230#" 13.0842
+cap "OUT" "A" 9.74286
+cap "vdd!" "A" 13.0842
+cap "OUT" "VDD" 2.96
+cap "vdd!" "VDD" 29.2
cap "gnd!" "z1" 159.5
cap "OUT" "z1" 210.754
cap "OUT" "gnd!" 22
cap "vdd!" "z1" 8.55556
-cap "a_280_n230#" "z1" 70.125
cap "vdd!" "gnd!" 8.55556
-cap "A" "z1" 8.25
cap "vdd!" "OUT" 838.2
-cap "A" "gnd!" 57.75
-cap "a_280_n230#" "OUT" 150.608
-cap "a_280_n230#" "vdd!" 13.0842
-cap "A" "OUT" 9.74286
-cap "A" "vdd!" 13.0842
-cap "VDD" "OUT" 2.96
-cap "VDD" "vdd!" 29.2
-cap "A" "a_280_n230#" 81.6947
device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "w_n46_n476#" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0
device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "w_n46_n476#" "A" 60 0 "gnd!" 200 0 "z1" 200 0
device msubckt sky130_fd_pr__pfet_01v8 310 20 311 21 l=30 w=400 "VDD" "a_280_n230#" 60 0 "vdd!" 400 0 "OUT" 400 0
diff --git a/gds/nor.ext b/gds/nor.ext
index 2b8fdd3..5d25de5 100644
--- a/gds/nor.ext
+++ b/gds/nor.ext
@@ -23,22 +23,22 @@
node "A" 2231 379.695 -110 -80 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 3542 2250 -110 990 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n66_n446#" 0 0 -66 -446 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "A" "Out" 8.8
-cap "B" "Z1" 57.75
-cap "VDD" "Out" 2.3125
-cap "A" "vdd!" 57.75
-cap "VDD" "Z1" 2.775
-cap "VDD" "vdd!" 16.2425
-cap "A" "B" 72.9302
cap "Out" "gnd!" 453.75
cap "Z1" "gnd!" 9.625
-cap "Z1" "Out" 779.396
cap "vdd!" "gnd!" 9.625
cap "B" "gnd!" 39.7045
-cap "vdd!" "Out" 99
cap "A" "gnd!" 19.25
+cap "Z1" "Out" 779.396
+cap "vdd!" "Out" 99
cap "vdd!" "Z1" 749.833
cap "B" "Out" 246.8
+cap "Out" "VDD" 2.3125
+cap "A" "Out" 8.8
+cap "B" "Z1" 57.75
+cap "Z1" "VDD" 2.775
+cap "vdd!" "VDD" 16.2425
+cap "A" "vdd!" 57.75
+cap "A" "B" 72.9302
device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "w_n66_n446#" "B" 60 0 "gnd!" 200 0 "Out" 200 0
device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "w_n66_n446#" "A" 60 0 "gnd!" 200 0 "Out" 200 0
device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0
diff --git a/gds/pd.ext b/gds/pd.ext
index 8a35633..dceaca9 100644
--- a/gds/pd.ext
+++ b/gds/pd.ext
@@ -31,68 +31,68 @@
substrate "w_n446_n1456#" 0 0 -446 -1456 pw 870472 15844 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0
cap "R" "GND" 53.75
cap "DOWN" "GND" 50.15
-cap "VDD" "GND" 113.9
-cap "m1_2010_600#" "UP" 4.5
-cap "VDD" "DIV" 27.9
-cap "R" "UP" 72
-cap "VDD" "m4_1440_1280#" 4.92
-cap "VDD" "REF" 27.9
-cap "DOWN" "UP" 101.25
-cap "DOWN" "m1_2010_600#" 41.625
-cap "DOWN" "R" 185.417
-cap "VDD" "UP" 7.2
-cap "VDD" "R" 11.2838
cap "w_0_n1460#" "VDD" 0.48
cap "VDD" "VDD" 0.48
+cap "UP" "VDD" 7.2
+cap "R" "VDD" 11.2838
+cap "m1_2010_600#" "UP" 4.5
+cap "R" "UP" 72
+cap "DOWN" "UP" 101.25
+cap "DOWN" "m1_2010_600#" 41.625
+cap "VDD" "GND" 113.9
+cap "DOWN" "R" 185.417
+cap "VDD" "DIV" 27.9
+cap "VDD" "m4_1440_1280#" 4.92
+cap "VDD" "REF" 27.9
cap "tspc_r_0/R" "tspc_r_0/Z3" -7.021
cap "VDD" "tspc_r_0/Z3" 10.9091
-cap "GND" "tspc_r_0/Z1" 14.4375
-cap "VDD" "DIV" 62.5
cap "VDD" "tspc_r_0/R" 100
+cap "VDD" "DIV" 62.5
cap "VDD" "tspc_r_0/Z2" 72
-cap "GND" "tspc_r_0/Z3" 7.21875
+cap "tspc_r_0/Z3" "GND" 7.21875
cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775
-cap "GND" "VDD" 99.8267
-cap "GND" "tspc_r_0/Z2" 9.69375
cap "tspc_r_0/w_n290_n40#" "VDD" 33.548
-cap "tspc_r_0/Q" "tspc_r_0/VDD" 5.68434e-14
-cap "tspc_r_0/Qbar1" "tspc_r_0/w_n276_n506#" 7.21875
-cap "tspc_r_0/R" "tspc_r_0/Z3" 136.361
+cap "tspc_r_0/Z2" "GND" 9.69375
+cap "VDD" "GND" 99.8267
+cap "GND" "tspc_r_0/Z1" 14.4375
+cap "tspc_r_0/VDD" "tspc_r_0/Qbar" 30.4615
cap "tspc_r_0/Qbar" "tspc_r_0/w_n276_n506#" 7.21875
-cap "tspc_r_0/VDD" "tspc_r_0/w_n276_n506#" 45.2812
cap "tspc_r_0/Q" "tspc_r_0/w_n276_n506#" 7.21875
+cap "tspc_r_0/R" "tspc_r_0/Z3" 136.361
+cap "tspc_r_0/VDD" "tspc_r_0/Q" 5.68434e-14
+cap "tspc_r_0/Qbar1" "tspc_r_0/w_n276_n506#" 7.21875
cap "tspc_r_0/VDD" "tspc_r_0/Z3" -2.84217e-14
-cap "tspc_r_0/Qbar" "tspc_r_0/VDD" 30.4615
+cap "tspc_r_0/VDD" "tspc_r_0/w_n276_n506#" 45.2812
cap "tspc_r_1/Z4" "tspc_r_0/Z4" 19.4595
-cap "GND" "tspc_r_0/Z4" 13.3333
+cap "tspc_r_0/Z4" "GND" 13.3333
+cap "tspc_r_0/R" "VDD" 66.6667
+cap "tspc_r_1/Z4" "GND" 13.3333
+cap "tspc_r_0/R" "GND" 64.2857
cap "tspc_r_1/Z3" "tspc_r_0/R" -9.042
-cap "GND" "tspc_r_1/Z4" 13.3333
-cap "VDD" "tspc_r_0/R" 66.6667
-cap "GND" "tspc_r_0/R" 64.2857
-cap "VDD" "tspc_r_1/Z2" 72
-cap "VDD" "tspc_r_1/Z3" 10.9091
-cap "VDD" "REF" 44.4444
+cap "tspc_r_1/Z2" "VDD" 72
+cap "tspc_r_1/Z3" "VDD" 10.9091
cap "GND" "VDD" 148.505
-cap "and_pd_0/Z1" "tspc_r_1/Qbar" 21.0517
+cap "REF" "VDD" 44.4444
+cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 64.7625
+cap "and_pd_0/Out1" "tspc_r_1/Qbar" 45.8071
+cap "tspc_r_0/Q" "tspc_r_1/Qbar" 17.9186
+cap "tspc_r_1/Qbar" "GND" 44.4044
+cap "tspc_r_1/Qbar" "R" 31.025
+cap "tspc_r_1/VDD" "GND" 8.88178e-16
+cap "tspc_r_1/Q" "and_pd_0/Out1" -12.43
+cap "tspc_r_1/Q" "tspc_r_0/Q" 180.938
+cap "tspc_r_0/Q" "GND" 308.57
cap "tspc_r_0/Q" "R" 86.5
cap "tspc_r_1/Q" "R" 150.845
cap "tspc_r_1/Qbar1" "R" 287.105
-cap "tspc_r_1/Z3" "R" 160.382
cap "R" "GND" 145.652
+cap "tspc_r_1/Z3" "R" 160.382
+cap "tspc_r_1/z5" "tspc_r_0/z5" 19.4595
cap "tspc_r_1/clk" "R" 103.99
-cap "tspc_r_1/Q" "and_pd_0/Out1" -12.43
-cap "R" "tspc_r_1/Qbar" 31.025
-cap "tspc_r_1/VDD" "GND" 8.88178e-16
-cap "tspc_r_1/Q" "tspc_r_0/Q" 180.938
-cap "tspc_r_0/Q" "GND" 308.57
-cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 64.7625
-cap "and_pd_0/Out1" "tspc_r_1/Qbar" 45.8071
-cap "tspc_r_0/z5" "GND" 13.3333
-cap "tspc_r_0/Q" "tspc_r_1/Qbar" 17.9186
+cap "GND" "tspc_r_0/z5" 13.3333
+cap "tspc_r_1/Qbar" "and_pd_0/Z1" 21.0517
cap "tspc_r_0/Q" "and_pd_0/Z1" 76.112
-cap "tspc_r_1/Qbar" "GND" 44.4044
-cap "tspc_r_1/z5" "GND" 13.3333
-cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595
+cap "GND" "tspc_r_1/z5" 13.3333
cap "R" "tspc_r_0/GND" 16.129
cap "tspc_r_1/Qbar" "and_pd_0/Z1" 1.76471
cap "DOWN" "and_pd_0/Z1" -9.852
@@ -118,14 +118,14 @@
cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.548
cap "w_n446_n1456#" "tspc_r_1/VDD" 58.522
cap "tspc_r_1/Qbar" "and_pd_0/Out1" 5.42143
-cap "and_pd_0/Out1" "w_n446_n1456#" 7.21875
-cap "tspc_r_1/Qbar" "w_n446_n1456#" 7.21875
+cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 9.4875
+cap "w_n446_n1456#" "and_pd_0/Out1" 7.21875
+cap "w_n446_n1456#" "tspc_r_1/Qbar" 7.21875
cap "w_n446_n1456#" "tspc_r_1/Q" 7.21875
cap "w_n446_n1456#" "tspc_r_1/Qbar1" 7.21875
+cap "w_n446_n1456#" "tspc_r_1/VDD" 54.6607
cap "VDD" "tspc_r_1/VDD" 43.262
cap "tspc_r_1/Q" "and_pd_0/A" 2.15625
-cap "tspc_r_1/Qbar" "tspc_r_1/VDD" 9.4875
-cap "w_n446_n1456#" "tspc_r_1/VDD" 54.6607
cap "w_n446_n1456#" "and_pd_0/Out" 11.4354
cap "w_n446_n1456#" "and_pd_0/Out1" 7.21875
cap "w_n446_n1456#" "VDD" 18.7589
diff --git a/gds/prescaler.ext b/gds/prescaler.ext
index a491d54..0e3d770 100644
--- a/gds/prescaler.ext
+++ b/gds/prescaler.ext
@@ -41,10 +41,6 @@
node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "GND" "m4_2730_1520#" 23.6471
-cap "mc1" "m4_2730_1520#" 23.175
-cap "m2_970_460#" "VDD" 42
-cap "Out" "GND" 27.9
cap "mc1" "VDD" 41.675
cap "li_3590_420#" "clk" 168.462
cap "mc1" "m4_350_1060#" 84.575
@@ -66,64 +62,72 @@
cap "li_n310_330#" "mc1" 37.515
cap "w_1930_2072#" "mc1" 2.7456
cap "w_1930_2072#" "li_1980_2130#" 10.7855
-cap "nand_1/OUT" "nand_1/A" 29.5549
-cap "clk" "nand_1/A" 17.42
-cap "nand_1/OUT" "tspc_2/vdd!" 45.9643
-cap "nand_1/OUT" "clk" 127.12
-cap "nand_1/a_280_n230#" "GND" 124.422
+cap "GND" "m4_2730_1520#" 23.6471
+cap "m2_970_460#" "VDD" 42
+cap "Out" "GND" 27.9
+cap "mc1" "m4_2730_1520#" 23.175
cap "nand_1/a_280_n230#" "tspc_2/Z3" 75.9225
+cap "tspc_2/Z4" "nand_1/a_280_n230#" 106.442
+cap "GND" "nand_1/a_280_n230#" 124.422
+cap "nand_1/z1" "nand_1/a_280_n230#" 153.26
cap "nand_1/a_280_n230#" "tspc_2/Z2" 56.16
-cap "nand_1/a_280_n230#" "tspc_2/Z4" 106.442
-cap "nand_1/a_280_n230#" "nand_1/z1" 153.26
-cap "nand_1/OUT" "tspc_2/Z4" 12.3811
+cap "tspc_2/Z4" "nand_1/OUT" 12.3811
+cap "nand_1/z1" "nand_1/OUT" 2.11538
cap "nand_1/A" "nand_1/vdd!" 44.8462
-cap "nand_1/OUT" "nand_1/z1" 2.11538
cap "nand_1/A" "nand_1/a_280_n230#" 13.02
cap "clk" "nand_1/a_280_n230#" 94.1074
cap "nand_1/OUT" "nand_1/a_280_n230#" 165.278
-cap "tspc_2/vdd!" "tspc_1/vdd!" 38.2105
-cap "tspc_2/a_740_n680#" "tspc_1/D" 32.1861
-cap "tspc_1/a_300_n150#" "tspc_2/Z3" 198.42
+cap "clk" "nand_1/A" 17.42
+cap "nand_1/OUT" "nand_1/A" 29.5549
+cap "nand_1/OUT" "tspc_2/vdd!" 45.9643
+cap "nand_1/OUT" "clk" 127.12
cap "tspc_2/a_740_n680#" "tspc_1/a_300_n150#" 129.16
-cap "tspc_1/Z4" "li_3590_420#" 51.8
-cap "tspc_1/gnd!" "li_3590_420#" 198.939
-cap "tspc_2/Z4" "li_3590_420#" 107.677
-cap "tspc_1/Z2" "li_3590_420#" 43.32
-cap "tspc_1/D" "li_3590_420#" 142.71
+cap "li_3590_420#" "tspc_1/Z4" 51.8
cap "tspc_1/gnd!" "tspc_2/a_630_n680#" 17.3347
-cap "tspc_2/Z3" "li_3590_420#" 57.62
-cap "tspc_1/a_300_n150#" "li_3590_420#" 83.0378
+cap "li_3590_420#" "tspc_1/gnd!" 198.939
+cap "li_3590_420#" "tspc_2/Z4" 107.677
+cap "li_3590_420#" "tspc_1/Z2" 43.32
cap "tspc_1/Z2" "tspc_1/gnd!" 16.9342
cap "tspc_1/D" "tspc_1/Z3" 3.50402
cap "tspc_1/D" "tspc_1/Z4" 102.17
-cap "tspc_2/a_740_n680#" "li_3590_420#" 150.46
+cap "li_3590_420#" "tspc_1/D" 142.71
cap "tspc_1/D" "tspc_1/gnd!" 51.0882
+cap "li_3590_420#" "tspc_2/Z3" 57.62
cap "tspc_1/D" "tspc_1/Z2" 85.89
cap "tspc_1/D" "tspc_1/Z1" 39.5832
cap "tspc_1/D" "tspc_1/vdd!" 59.1194
+cap "li_3590_420#" "tspc_1/a_300_n150#" 83.0378
cap "tspc_2/a_740_n680#" "tspc_1/Z4" 4.09091
+cap "li_3590_420#" "tspc_2/a_740_n680#" 150.46
cap "tspc_2/a_740_n680#" "tspc_1/Z2" 5.4
+cap "tspc_2/vdd!" "tspc_1/vdd!" 38.2105
cap "tspc_1/a_300_n150#" "tspc_1/D" 177.533
+cap "tspc_1/a_300_n150#" "tspc_2/Z3" 198.42
+cap "tspc_2/a_740_n680#" "tspc_1/D" 32.1861
+cap "GND" "Out" 39.1
+cap "tspc_1/Z3" "Out" 59.529
+cap "tspc_1/Q" "Out" 50.6
+cap "tspc_1/Z4" "Out" 76.1789
+cap "tspc_1/Z2" "Out" 9.99
+cap "tspc_1/Q" "tspc_1/a_740_n680#" 175.043
+cap "tspc_1/a_740_n680#" "Out" 82.65
+cap "tspc_1/Q" "tspc_1/a_300_n150#" 68.7785
+cap "tspc_1/a_300_n150#" "Out" 179.587
+cap "tspc_1/Z4" "tspc_2/a_740_n680#" 1.92857
cap "tspc_1/Q" "tspc_1/Z4" -74.25
cap "tspc_1/Q" "GND" 218.86
-cap "tspc_1/Z3" "tspc_1/Q" 156.507
-cap "tspc_1/Z2" "tspc_1/Q" 12.84
-cap "Out" "GND" 39.1
-cap "Out" "tspc_1/Q" 50.6
-cap "Out" "tspc_1/Z4" 76.1789
-cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785
-cap "Out" "tspc_1/Z3" 59.529
-cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
-cap "Out" "tspc_1/Z2" 9.99
-cap "Out" "tspc_1/a_300_n150#" 179.587
-cap "tspc_1/a_740_n680#" "Out" 82.65
-cap "tspc_1/Z4" "tspc_2/a_740_n680#" 1.92857
-cap "nand_1/vdd!" "tspc_2/Z2" 10
+cap "tspc_1/Q" "tspc_1/Z3" 156.507
+cap "tspc_1/Q" "tspc_1/Z2" 12.84
cap "tspc_0/Q" "nand_1/vdd!" 32.5248
-cap "nand_1/VDD" "nand_1/vdd!" -3.656
cap "nand_1/vdd!" "mc1" 162.542
+cap "nand_1/vdd!" "tspc_2/Z2" 10
+cap "mc1" "nand_1/VDD" 9.165
+cap "nand_1/vdd!" "nand_1/VDD" -3.656
cap "tspc_2/Z2" "mc1" 46.8
-cap "nand_1/VDD" "mc1" 9.165
+cap "nand_0/a_280_n230#" "VDD" 7.33333
+cap "nand_0/VDD" "nand_0/OUT" 8.1659
+cap "nand_0/OUT" "VDD" 272.242
+cap "nand_0/OUT" "nand_0/a_280_n230#" 9.77778
cap "tspc_2/Q" "tspc_1/Z1" 10.4211
cap "tspc_2/Z2" "mc1" 17.4522
cap "VDD" "tspc_2/Q" 44.0676
@@ -131,40 +135,36 @@
cap "tspc_0/Z2" "mc1" 53.3571
cap "nand_0/VDD" "mc1" 24.5544
cap "VDD" "mc1" 414.897
-cap "nand_0/VDD" "tspc_0/a_300_n150#" 2.0976
cap "tspc_0/a_300_n150#" "VDD" 166.667
+cap "nand_0/VDD" "tspc_0/a_300_n150#" 2.0976
cap "VDD" "tspc_1/Z2" 4.35484
cap "tspc_0/a_300_n150#" "nand_0/OUT" -6.9
cap "VDD" "tspc_0/Z2" 10
cap "nand_0/VDD" "VDD" -11.884
cap "nand_0/OUT" "nand_0/z1" 6
-cap "nand_0/a_280_n230#" "VDD" 7.33333
cap "nand_0/OUT" "tspc_0/Z1" 99.6765
-cap "nand_0/VDD" "nand_0/OUT" 8.1659
-cap "nand_0/OUT" "VDD" 272.242
-cap "nand_0/OUT" "nand_0/a_280_n230#" 9.77778
-cap "VDD" "tspc_0/a_300_n150#" 1.66667
-cap "VDD" "tspc_1/Z2" 11.9132
-cap "nand_0/a_280_n230#" "tspc_1/a_740_n680#" 1.36364
-cap "mc1" "tspc_1/Z2" 46.2522
-cap "GND" "VDD" 39.5155
-cap "mc1" "VDD" 227.695
cap "nand_0/a_280_n230#" "VDD" 13.125
-cap "nand_0/OUT" "nand_0/z1" 2.2
cap "nand_0/VDD" "VDD" -6.44
cap "mc1" "nand_0/OUT" 22.3793
cap "nand_0/a_280_n230#" "nand_0/OUT" 0.275
+cap "GND" "VDD" 39.5155
+cap "nand_0/a_280_n230#" "tspc_1/a_740_n680#" 1.36364
+cap "mc1" "tspc_1/Z2" 46.2522
+cap "nand_0/OUT" "nand_0/z1" 2.2
+cap "VDD" "tspc_0/a_300_n150#" 1.66667
+cap "VDD" "tspc_1/Z2" 11.9132
cap "nand_0/VDD" "mc1" 9.555
+cap "mc1" "VDD" 227.695
cap "tspc_0/Q" "tspc_0/a_740_n680#" 18.4737
cap "nand_0/OUT" "nand_0/z1" 14
cap "nand_0/OUT" "tspc_0/vdd!" 47.4
cap "nand_0/OUT" "tspc_0/Z1" 20.5588
cap "nand_0/OUT" "tspc_0/Z4" 7.71692
cap "nand_0/OUT" "GND" -5.32907e-15
-cap "tspc_0/a_300_n150#" "nand_0/OUT" 0.18
cap "tspc_0/Z3" "nand_0/OUT" 5.25747
-cap "tspc_0/w_n140_n70#" "nand_0/OUT" 3.0525
-cap "nand_0/OUT" "nand_0/z1" 3.85
+cap "tspc_0/a_300_n150#" "nand_0/OUT" 0.18
+cap "nand_0/OUT" "tspc_0/w_n140_n70#" 3.0525
+cap "nand_0/z1" "nand_0/OUT" 3.85
merge "tspc_0/gnd!" "tspc_0/GND" -422.046 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -213980 -2050 0 0 0 0
merge "tspc_0/GND" "nand_0/GND"
merge "nand_0/GND" "tspc_1/GND"
diff --git a/gds/ro_complete.ext b/gds/ro_complete.ext
index 741322c..23f9db7 100644
--- a/gds/ro_complete.ext
+++ b/gds/ro_complete.ext
@@ -35,29 +35,29 @@
cap "cbank_1/switch_0/vin" "li_7140_1400#" 23.3333
cap "cbank_1/a5" "cbank_1/switch_0/vout" 33.8462
cap "cbank_1/v" "cbank_2/gnd!" 86.7059
-cap "a0" "cbank_1/v" 53.41
-cap "cbank_2/gnd!" "cbank_1/v" 275.882
cap "cbank_2/switch_4/vin" "a0" 21.2667
+cap "a0" "cbank_1/v" 53.41
cap "cbank_2/gnd!" "a0" 180.338
-cap "a1" "cbank_1/v" 53.41
-cap "cbank_2/switch_4/vout" "cbank_1/v" 275.882
+cap "cbank_2/gnd!" "cbank_1/v" 275.882
cap "cbank_2/switch_4/vout" "a2" 59.4701
cap "cbank_2/switch_3/vin" "a1" 23.0602
cap "cbank_2/switch_4/vout" "a1" 208.707
+cap "a1" "cbank_1/v" 53.41
+cap "cbank_2/switch_4/vout" "cbank_1/v" 275.882
cap "a3" "cbank_1/v" 53.41
cap "a2" "cbank_1/v" 53.41
-cap "cbank_2/gnd!" "cbank_1/v" 275.882
cap "cbank_2/switch_1/vin" "a3" 11.1279
-cap "cbank_2/switch_2/vin" "a2" 22.9222
-cap "cbank_2/gnd!" "a3" 191.198
-cap "cbank_2/gnd!" "a2" 123.77
+cap "cbank_1/v" "cbank_2/gnd!" 275.882
+cap "a2" "cbank_2/switch_2/vin" 22.9222
+cap "a3" "cbank_2/gnd!" 191.198
+cap "a2" "cbank_2/gnd!" 123.77
+cap "li_7140_1400#" "cbank_2/switch_1/vout" 275.882
+cap "a4" "cbank_2/switch_0/vin" 20.0419
+cap "a4" "cbank_2/switch_1/vout" 189.52
+cap "a3" "cbank_2/switch_1/vin" 11.1279
cap "a4" "li_7140_1400#" 53.41
-cap "cbank_2/switch_1/vout" "li_7140_1400#" 275.882
-cap "cbank_2/switch_0/vin" "a4" 20.0419
-cap "cbank_2/switch_1/vout" "a4" 189.52
-cap "cbank_2/switch_1/vin" "a3" 11.1279
-cap "cbank_2/switch_0/vout" "w_7764_n10666#" 162.097
cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126
+cap "cbank_2/switch_0/vout" "w_7764_n10666#" 162.097
cap "cbank_2/switch_0/vout" "li_7140_1400#" 233.936
cap "cbank_2/switch_0/vout" "a5" 124.366
cap "cbank_2/gnd!" "w_7764_n10666#" 45.6818
@@ -66,51 +66,51 @@
cap "cbank_2/a2" "cbank_2/switch_3/vout" 150.151
cap "cbank_2/a1" "cbank_2/switch_3/vin" 116.096
cap "cbank_2/a1" "cbank_2/switch_4/vout" 290.488
+cap "cbank_2/gnd!" "cbank_2/a3" 265.538
cap "cbank_2/a3" "cbank_2/switch_1/vin" 56.0233
cap "cbank_2/a2" "cbank_2/switch_2/vin" 115.401
cap "cbank_2/a2" "cbank_2/switch_3/vout" 103.613
-cap "cbank_2/gnd!" "cbank_2/a3" 265.538
cap "cbank_2/switch_1/vin" "a3" 56.0233
cap "cbank_2/a5" "cbank_2/switch_0/vout" 12.6923
cap "cbank_2/a4" "cbank_2/switch_0/vin" 100.901
cap "cbank_2/a4" "cbank_2/switch_1/vout" 263.078
cap "cbank_2/a5" "cbank_2/switch_0/vout" 143.972
cap "cbank_0/gnd!" "cbank_2/v" 47.5484
-cap "cbank_0/gnd!" "cbank_2/v" 151.29
cap "cbank_2/a0" "cbank_2/v" 53.41
cap "cbank_0/gnd!" "cbank_2/v" 151.29
+cap "cbank_0/gnd!" "cbank_2/v" 151.29
cap "cbank_2/a1" "cbank_2/v" 53.41
cap "cbank_2/a3" "cbank_2/v" 53.41
-cap "cbank_2/a2" "cbank_2/v" 53.41
cap "cbank_2/w_3654_n56#" "cbank_2/v" 151.29
-cap "cbank_2/a4" "li_4080_1390#" 53.41
+cap "cbank_2/a2" "cbank_2/v" 53.41
cap "cbank_0/gnd!" "li_4080_1390#" 151.29
-cap "li_4080_1390#" "cbank_0/gnd!" 41.6979
-cap "li_4080_1390#" "cbank_2/switch_0/vin" 133.875
+cap "cbank_2/a4" "li_4080_1390#" 53.41
+cap "cbank_0/gnd!" "li_4080_1390#" 41.6979
+cap "cbank_2/switch_0/vin" "li_4080_1390#" 133.875
cap "cbank_2/v" "cbank_0/gnd!" 47.5484
-cap "cbank_0/gnd!" "a0" 294.969
cap "cbank_0/gnd!" "cbank_2/v" 151.29
cap "cbank_0/switch_4/vin" "a0" 81.7667
-cap "cbank_2/v" "cbank_0/switch_4/vout" 151.29
-cap "a2" "cbank_0/switch_4/vout" 118.019
-cap "a1" "cbank_0/switch_4/vout" 346.555
+cap "cbank_0/gnd!" "a0" 294.969
+cap "cbank_0/switch_4/vout" "cbank_2/v" 151.29
+cap "cbank_0/switch_4/vout" "a2" 118.019
cap "cbank_0/switch_3/vin" "a1" 88.6627
-cap "cbank_0/gnd!" "cbank_2/v" 151.29
+cap "cbank_0/switch_4/vout" "a1" 346.555
+cap "cbank_2/v" "cbank_0/gnd!" 151.29
cap "cbank_0/switch_1/vin" "a3" 42.7849
cap "cbank_0/switch_2/vin" "a2" 88.1317
cap "cbank_0/gnd!" "a3" 314.948
cap "cbank_0/gnd!" "a2" 182.319
cap "li_4080_1390#" "cbank_0/switch_1/vout" 151.29
-cap "cbank_0/switch_0/vin" "a4" 77.0576
-cap "cbank_0/switch_1/vout" "a4" 311.879
cap "cbank_0/switch_1/vin" "a3" 42.7849
+cap "a4" "cbank_0/switch_0/vin" 77.0576
+cap "a4" "cbank_0/switch_1/vout" 311.879
cap "cbank_0/switch_0/vout" "w_7764_n10666#" 193.269
-cap "cbank_0/switch_0/vout" "a5" 186.594
cap "cbank_0/switch_0/vout" "li_4080_1390#" 438.698
cap "cbank_0/switch_0/vout" "li_7140_1400#" 142.26
+cap "cbank_0/switch_0/vout" "a5" 186.594
cap "cbank_0/gnd!" "w_7764_n10666#" 45.6818
-cap "a0" "cbank_0/switch_5/vout" 134.77
cap "a0" "cbank_0/switch_4/vin" 46.5667
+cap "a0" "cbank_0/switch_5/vout" 134.77
cap "a2" "cbank_0/switch_3/vout" 91.603
cap "a1" "cbank_0/switch_3/vin" 50.494
cap "a1" "cbank_0/switch_4/vout" 152.64
@@ -118,28 +118,28 @@
cap "a3" "cbank_0/switch_2/vout" 141.788
cap "a2" "cbank_0/switch_2/vin" 50.1916
cap "a2" "cbank_0/switch_3/vout" 45.0645
-cap "cbank_0/switch_0/vout" "cbank_0/a5" 12.6923
-cap "cbank_0/switch_0/vin" "a4" 43.8848
-cap "cbank_0/switch_1/vout" "a4" 140.718
cap "cbank_0/switch_1/vin" "a3" 24.3663
+cap "cbank_0/a5" "cbank_0/switch_0/vout" 12.6923
+cap "a4" "cbank_0/switch_0/vin" 43.8848
+cap "a4" "cbank_0/switch_1/vout" 140.718
cap "a5" "cbank_0/switch_0/vout" 81.7433
cap "cbank_0/v" "ro_var_extend_0/gnd" 151.9
-cap "li_4080_1390#" "ro_var_extend_0/gnd" 796.97
-cap "ro_var_extend_0/gnd" "li_4080_1390#" 645.27
-cap "ro_var_extend_0/gnd" "li_4080_1390#" 291.625
-cap "ro_var_extend_0/gnd" "li_7140_1400#" 292.345
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 69.0462
-cap "ro_var_extend_0/out1" "ro_var_extend_0/w_n120_n750#" 100.15
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 129.703
+cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97
+cap "li_4080_1390#" "ro_var_extend_0/gnd" 645.27
+cap "li_4080_1390#" "ro_var_extend_0/gnd" 291.625
+cap "li_7140_1400#" "ro_var_extend_0/gnd" 292.345
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
+cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
cap "ro_var_extend_0/out2" "ro_var_extend_0/w_n120_n750#" 184.5
cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55
-cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
+cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 322.14
-cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" -11.167
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 394.496
+cap "ro_var_extend_0/vcont" "ro_var_extend_0/w_n120_n750#" -11.167
+cap "ro_var_extend_0/out3" "ro_var_extend_0/gnd" 394.496
cap "ro_var_extend_0/gnd" "ro_var_extend_0/w_n120_n750#" -86.444
cap "ro_var_extend_0/gnd" "w_7764_n10666#" -79.966
merge "cbank_0/a4" "cbank_2/a4" -1880.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -239756 -6032 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/gds/ro_var_extend.ext b/gds/ro_var_extend.ext
index bed1989..67b0a17 100644
--- a/gds/ro_var_extend.ext
+++ b/gds/ro_var_extend.ext
@@ -21,16 +21,16 @@
node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
node "vdd" 21463 18367.8 6020 900 li 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 5980 -160 li 2627212 34004 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vcont" "w_n120_n750#" 140.194
-cap "out2" "w_n120_n750#" 789.263
-cap "out1" "w_n120_n750#" 569.035
-cap "out2" "vdd" 235.622
-cap "out3" "w_n120_n750#" 215.464
-cap "out1" "vdd" 230.66
-cap "out3" "vdd" 230.554
+cap "vdd" "out2" 235.622
+cap "vdd" "out1" 230.66
+cap "vdd" "out3" 230.554
cap "out1" "out2" 40.8506
+cap "w_n120_n750#" "vcont" 140.194
cap "out3" "out2" 1263.05
+cap "w_n120_n750#" "out2" 789.263
cap "out3" "out1" 1156.32
+cap "w_n120_n750#" "out1" 569.035
+cap "w_n120_n750#" "out3" 215.464
device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0
device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0
device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0
diff --git a/gds/switch.ext b/gds/switch.ext
index b9c796c..d24029c 100644
--- a/gds/switch.ext
+++ b/gds/switch.ext
@@ -12,7 +12,7 @@
node "vin" 1082 0 -150 1410 li 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0
node "vcont" 1139 384.82 20 1590 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n216_n26#" 0 0 -216 -26 pw 719144 3948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "vcont" "vin" 8.25
cap "vin" "vout" 420
cap "vcont" "vout" 16.5
-cap "vcont" "vin" 8.25
device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "w_n216_n26#" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/gds/tspc.ext b/gds/tspc.ext
index 6d3ad8a..20b7efa 100644
--- a/gds/tspc.ext
+++ b/gds/tspc.ext
@@ -32,41 +32,17 @@
node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0
node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n146_n706#" 0 0 -146 -706 pw 475604 4208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "gnd!" "a_630_n680#" 610.469
-cap "Z4" "a_630_n680#" 121.707
-cap "Q" "a_630_n680#" 36.6667
-cap "Z4" "gnd!" 441.644
-cap "Z3" "a_630_n680#" 54.2903
cap "Q" "gnd!" 289.808
-cap "Z2" "a_630_n680#" 6.6
-cap "Z3" "gnd!" 265.176
-cap "Z3" "Z4" 651.52
-cap "Z2" "gnd!" 156.712
-cap "Z2" "Z4" 361.112
-cap "a_300_n150#" "a_630_n680#" 9.625
-cap "Z3" "Q" 52.8649
-cap "a_300_n150#" "gnd!" 22.7597
-cap "Z1" "Z4" 3.38462
-cap "D" "gnd!" 27.9314
-cap "a_300_n150#" "Z4" 118.945
cap "Z2" "Z3" 161.5
-cap "a_740_n680#" "a_630_n680#" 190.867
-cap "D" "Z4" 97.7372
cap "Z1" "Z3" 62.0085
-cap "a_740_n680#" "gnd!" 224.895
-cap "vdd!" "Z4" 7.7
cap "Z1" "Z2" 1068.12
cap "a_300_n150#" "Z3" 446.312
-cap "a_740_n680#" "Z4" 82.0167
cap "D" "Z3" 46.1286
-cap "vdd!" "Q" 607.82
cap "a_300_n150#" "Z2" 110.226
-cap "a_740_n680#" "Q" 178.823
cap "vdd!" "Z3" 671.367
cap "D" "Z2" 91.0218
cap "D" "Z1" 26.4
cap "vdd!" "Z2" 359.159
-cap "w_n140_n70#" "Q" 6.845
cap "a_740_n680#" "Z3" 334.495
cap "vdd!" "Z1" 583.229
cap "w_n140_n70#" "Z3" 2.3125
@@ -80,6 +56,30 @@
cap "a_740_n680#" "vdd!" 515.003
cap "w_n140_n70#" "vdd!" 85.4425
cap "w_n140_n70#" "a_740_n680#" 18.5775
+cap "a_630_n680#" "Z3" 54.2903
+cap "a_630_n680#" "Z2" 6.6
+cap "gnd!" "Z3" 265.176
+cap "Z4" "Z3" 651.52
+cap "gnd!" "Z2" 156.712
+cap "Z4" "Z2" 361.112
+cap "a_630_n680#" "a_300_n150#" 9.625
+cap "Q" "Z3" 52.8649
+cap "gnd!" "a_300_n150#" 22.7597
+cap "Z4" "Z1" 3.38462
+cap "gnd!" "D" 27.9314
+cap "Z4" "a_300_n150#" 118.945
+cap "a_630_n680#" "a_740_n680#" 190.867
+cap "Z4" "D" 97.7372
+cap "gnd!" "a_740_n680#" 224.895
+cap "Z4" "vdd!" 7.7
+cap "Z4" "a_740_n680#" 82.0167
+cap "Q" "vdd!" 607.82
+cap "Q" "a_740_n680#" 178.823
+cap "Q" "w_n140_n70#" 6.845
+cap "gnd!" "a_630_n680#" 610.469
+cap "Z4" "a_630_n680#" 121.707
+cap "Q" "a_630_n680#" 36.6667
+cap "Z4" "gnd!" 441.644
device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "w_n146_n706#" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0
device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "w_n146_n706#" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0
device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "w_n146_n706#" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0
diff --git a/gds/tspc_r.ext b/gds/tspc_r.ext
index 04a3ff2..cf4291b 100644
--- a/gds/tspc_r.ext
+++ b/gds/tspc_r.ext
@@ -41,6 +41,7 @@
node "D" 1470 418.74 -290 -120 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_n276_n506#" 0 0 -276 -506 pw 462144 4448 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n290_n40#" "Z3" 11.56
cap "Z4" "z5" 42.0885
cap "GND" "z5" 558.112
cap "GND" "Z4" 527.304
@@ -57,45 +58,44 @@
cap "Q" "GND" 263.95
cap "Z3" "Z4" 201.943
cap "Qbar1" "GND" 157.761
-cap "clk" "z5" 38.3774
cap "VDD" "Qbar" 237.6
cap "Z1" "Z2" 709.991
cap "Qbar1" "R" 11.3571
cap "Z3" "GND" 324.951
-cap "clk" "Z4" 18.15
cap "Q" "Qbar" 213.204
cap "VDD" "Z2" 95.0921
cap "Qbar1" "Qbar" 7.54286
-cap "clk" "GND" 37.5833
cap "Z3" "R" 137.379
cap "VDD" "Z1" 316.564
-cap "D" "GND" 14.4375
-cap "clk" "R" 508.778
cap "Q" "VDD" 334.95
cap "Z3" "Z2" 249.04
-cap "D" "R" 16.14
cap "Qbar1" "VDD" 315.732
cap "Z3" "Z1" 85.3
-cap "clk" "Z2" 187.91
cap "Z3" "VDD" 509.325
+cap "Qbar1" "Q" 109.835
+cap "Z3" "Q" 28.6775
+cap "Z3" "Qbar1" 379.384
+cap "D" "clk" 31.5485
+cap "w_n290_n40#" "clk" 10.355
+cap "clk" "z5" 38.3774
+cap "clk" "Z4" 18.15
+cap "clk" "GND" 37.5833
+cap "D" "GND" 14.4375
+cap "clk" "R" 508.778
+cap "D" "R" 16.14
+cap "clk" "Z2" 187.91
cap "clk" "Z1" 170.927
cap "w_n290_n40#" "Qbar" 1.85
cap "D" "Z2" 47.3222
-cap "Qbar1" "Q" 109.835
cap "clk" "VDD" 129.37
cap "w_n290_n40#" "Z2" 3.04
-cap "Z3" "Q" 28.6775
cap "D" "VDD" 38.5
cap "w_n290_n40#" "Z1" 7.4
-cap "Z3" "Qbar1" 379.384
cap "w_n290_n40#" "VDD" 7.4
cap "clk" "Qbar1" 121.715
cap "w_n290_n40#" "Q" 1.85
cap "clk" "Z3" 652.716
cap "w_n290_n40#" "Qbar1" 1.82
-cap "w_n290_n40#" "Z3" 11.56
-cap "D" "clk" 31.5485
-cap "w_n290_n40#" "clk" 10.355
device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "w_n276_n506#" "Q" 60 0 "GND" 180 0 "Qbar" 180 0
device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "w_n276_n506#" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0
device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "w_n276_n506#" "Z3" 60 0 "GND" 180 0 "z5" 180 0
diff --git a/gds/user_analog_project_wrapper.ext b/gds/user_analog_project_wrapper.ext
index 82a1a5e..f5024a8 100644
--- a/gds/user_analog_project_wrapper.ext
+++ b/gds/user_analog_project_wrapper.ext
@@ -4,12 +4,11 @@
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use ro_complete ro_complete_0 1 0 31596 0 1 681444
-use pd pd_0 1 0 87306 0 1 647408
+use cp cp_0 1 0 531400 0 1 683270
+use cp cp_1 1 0 196464 0 1 608714
use divider divider_0 1 0 163690 0 1 648664
-use filter filter_0 1 0 224356 0 1 680484
-use cp cp_0 1 0 196464 0 1 608714
-use cp cp_1 1 0 531400 0 1 683270
+use pd pd_0 1 0 87306 0 1 647408
+use ro_complete ro_complete_0 1 0 31596 0 1 681444
port "io_analog[4]" 42 329294 702300 334294 704800 m5
port "io_analog[4]" 42 318994 702300 323994 704800 m5
port "io_analog[5]" 43 227594 702300 232594 704800 m5
@@ -1393,65 +1392,64 @@
node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "io_analog[4]" "io_analog[4]" 26250
-cap "io_analog[5]" "io_analog[5]" 26250
cap "io_analog[5]" "io_analog[5]" 26250
cap "io_analog[4]" "io_analog[4]" 21250
cap "io_analog[6]" "io_analog[6]" 26250
cap "io_analog[4]" "io_analog[4]" 21250
-cap "io_analog[1]" "io_analog[0]" 12301.4
cap "io_analog[5]" "io_analog[5]" 21250
cap "io_analog[6]" "io_analog[6]" 26250
cap "io_analog[5]" "io_analog[5]" 21250
cap "io_analog[6]" "io_analog[6]" 21250
cap "io_analog[6]" "io_analog[6]" 21250
-cap "w_534750_683750#" "w_534690_682780#" 224.4
cap "io_clamp_high[0]" "io_analog[4]" 525
cap "io_clamp_low[0]" "io_clamp_high[0]" 525
-cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "io_clamp_high[1]" "io_analog[5]" 525
-cap "io_clamp_low[1]" "io_clamp_high[1]" 525
cap "io_analog[0]" "vdda1" 18313.2
-cap "io_analog[5]" "io_clamp_low[1]" 525
cap "io_analog[1]" "vdda1" 23516.2
+cap "io_analog[4]" "io_clamp_low[0]" 525
cap "io_analog[2]" "vdda1" 219.25
cap "io_analog[3]" "vssa1" 6389.64
-cap "io_clamp_high[2]" "io_analog[6]" 525
cap "io_analog[2]" "vssa1" 9275.17
+cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "io_clamp_low[1]" "io_clamp_high[1]" 525
+cap "io_analog[5]" "io_clamp_low[1]" 525
+cap "io_analog[1]" "io_analog[0]" 12301.4
+cap "io_clamp_high[2]" "io_analog[6]" 525
cap "io_analog[4]" "io_analog[4]" 26250
cap "io_clamp_low[2]" "io_clamp_high[2]" 525
cap "io_analog[6]" "io_clamp_low[2]" 525
-cap "cp_1/w_6344_n2866#" "cp_1/down" 439.89
-cap "cp_1/gnd!" "io_analog[1]" -20.89
-cap "cp_1/vbias" "cp_1/gnd!" 6.79412
-cap "cp_1/vbias" "cp_1/gnd!" 8.73529
-cap "cp_1/vbias" "cp_1/gnd!" 6.79412
-cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68
-cap "cp_1/gnd!" "cp_1/vbias" 8.73529
-cap "cp_1/a_3060_0#" "w_534750_683750#" 99.11
-cap "w_534750_683750#" "cp_1/a_3060_0#" 243.801
-cap "cp_1/a_1710_0#" "w_534750_683750#" 37.5
-cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "w_534690_682780#" "w_534750_683750#" 224.4
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "cp_0/w_6344_n2866#" "cp_0/down" 439.89
+cap "cp_0/gnd!" "io_analog[1]" -20.89
+cap "cp_0/vbias" "cp_0/gnd!" 6.79412
+cap "cp_0/vbias" "cp_0/gnd!" 8.73529
+cap "cp_0/vbias" "cp_0/gnd!" 6.79412
+cap "cp_0/vbias" "cp_0/gnd!" 8.73529
+cap "cp_0/a_10_n50#" "cp_0/vbias" 31.68
+cap "w_534750_683750#" "cp_0/a_1710_0#" 37.5
+cap "w_534750_683750#" "cp_0/a_3060_0#" 99.11
+cap "w_534750_683750#" "cp_0/a_3060_0#" 243.801
+cap "cp_0/a_3060_0#" "w_534690_682780#" 1083.86
cap "w_534750_683750#" "w_534690_682780#" -39.04
-cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4
+cap "cp_0/a_3060_0#" "w_534690_682780#" 904.4
cap "w_534750_683750#" "w_534690_682780#" -28
-cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25
-cap "w_534690_682780#" "w_534750_683750#" -15.96
-cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49
-cap "cp_1/vdd!" "cp_1/vdd!" 27.826
-cap "cp_1/vdd!" "cp_1/upbar" 248.023
-merge "cp_1/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0
-merge "vdda1" "cp_1/vdd!"
-merge "cp_1/vdd!" "w_534690_682780#"
+cap "w_534750_683750#" "w_534690_682780#" -15.96
+cap "cp_0/a_3060_0#" "w_534690_682780#" 50.49
+cap "cp_0/a_3060_0#" "w_534690_682780#" 119.25
+cap "cp_0/vdd!" "cp_0/vdd!" 27.826
+cap "cp_0/vdd!" "cp_0/upbar" 248.023
+merge "cp_0/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0
+merge "vdda1" "cp_0/vdd!"
+merge "cp_0/vdd!" "w_534690_682780#"
merge "w_534690_682780#" "w_534750_683750#"
-merge "cp_1/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0
+merge "cp_0/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0
merge "vssa1" "ro_complete_0/w_7764_n10666#"
-merge "ro_complete_0/w_7764_n10666#" "filter_0/v"
-merge "filter_0/v" "divider_0/w_n966_n46#"
+merge "ro_complete_0/w_7764_n10666#" "divider_0/w_n966_n46#"
merge "divider_0/w_n966_n46#" "pd_0/w_n446_n1456#"
-merge "pd_0/w_n446_n1456#" "cp_0/gnd!"
-merge "cp_0/gnd!" "VSUBS"
-merge "cp_1/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0
-merge "cp_1/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
-merge "cp_1/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
-merge "cp_1/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0
+merge "pd_0/w_n446_n1456#" "cp_1/gnd!"
+merge "cp_1/gnd!" "VSUBS"
+merge "cp_0/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0
+merge "cp_0/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0
+merge "cp_0/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "cp_0/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 3215525..d5e55d1 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/and.ext b/mag/and.ext
index 81972f1..f23957b 100644
--- a/mag/and.ext
+++ b/mag/and.ext
@@ -1,4 +1,4 @@
-timestamp 1640957225
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -15,18 +15,18 @@
node "out1" 6488 1253.5 10 20 pdif 0 0 0 0 0 0 0 0 32000 960 83200 2400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3340 0 0 136500 4640 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 1983 2469.6 -170 -30 nw 0 0 0 0 823200 3640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "OUT" "VDD" 2.3125
+cap "vdd!" "VDD" 48.86
+cap "out1" "VDD" 6.1975
cap "gnd!" "Z1" 409.78
cap "OUT" "Z1" 43.6452
-cap "VDD" "OUT" 2.3125
cap "OUT" "gnd!" 198
cap "B" "Z1" 67.1786
cap "A" "gnd!" 57.75
cap "B" "OUT" 8.8
cap "vdd!" "Z1" 7.96552
-cap "VDD" "vdd!" 48.86
cap "out1" "Z1" 356.371
cap "vdd!" "gnd!" 13.8886
-cap "VDD" "out1" 6.1975
cap "out1" "gnd!" 226.769
cap "vdd!" "OUT" 574.768
cap "A" "B" 87.6201
diff --git a/mag/and_pd.ext b/mag/and_pd.ext
index 3fe6c54..8600084 100644
--- a/mag/and_pd.ext
+++ b/mag/and_pd.ext
@@ -1,4 +1,4 @@
-timestamp 1640776259
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -15,15 +15,6 @@
node "A" 1358 374.675 -60 -250 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 1960 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 2352 1494 -160 -70 nw 0 0 0 0 498000 2860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "GND" "Z1" 192.37
-cap "Out" "Z1" 19.8
-cap "Out" "GND" 118.8
-cap "a_n60_n30#" "Z1" 8.88462
-cap "Out1" "Z1" 178.758
-cap "a_n60_n30#" "GND" 17.7692
-cap "Out1" "GND" 176.55
-cap "B" "Z1" 57.75
-cap "a_n60_n30#" "Out" 277.2
cap "Out1" "Out" 188.1
cap "B" "Out" 8.8
cap "A" "GND" 57.75
@@ -36,6 +27,15 @@
cap "A" "Out1" 13.5179
cap "VDD" "Out1" 3.7
cap "A" "B" 75.0211
+cap "GND" "Z1" 192.37
+cap "Out" "Z1" 19.8
+cap "Out" "GND" 118.8
+cap "a_n60_n30#" "Z1" 8.88462
+cap "Out1" "Z1" 178.758
+cap "a_n60_n30#" "GND" 17.7692
+cap "Out1" "GND" 176.55
+cap "B" "Z1" 57.75
+cap "a_n60_n30#" "Out" 277.2
device msubckt sky130_fd_pr__nfet_01v8 520 -470 521 -469 l=30 w=180 "VSUBS" "Out1" 60 0 "GND" 180 0 "Out" 180 0
device msubckt sky130_fd_pr__nfet_01v8 270 -470 271 -469 l=30 w=180 "VSUBS" "B" 60 0 "Z1" 180 0 "Out1" 180 0
device msubckt sky130_fd_pr__nfet_01v8 20 -470 21 -469 l=30 w=180 "VSUBS" "A" 60 0 "GND" 180 0 "Z1" 180 0
diff --git a/mag/cbank.ext b/mag/cbank.ext
index 0b0597d..c4139f2 100644
--- a/mag/cbank.ext
+++ b/mag/cbank.ext
@@ -1,4 +1,4 @@
-timestamp 1640959832
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -26,18 +26,18 @@
node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd!" 0 0 950 -1660 ppd 0 0 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
-cap "a_4660_n30#" "a_5640_n30#" 199.5
-cap "a_2730_n30#" "v" 1301.39
-cap "a_3680_n30#" "a_4660_n30#" 199.5
-cap "a_2730_n30#" "li_1720_n30#" 199.5
-cap "a_2730_n30#" "a_3680_n30#" 199.5
-cap "a_1720_n30#" "li_1720_n30#" 18.13
-cap "a_6660_n30#" "v" 1301.39
-cap "a_5640_n30#" "v" 1301.39
cap "v" "li_1720_n30#" 1301.39
+cap "a_2730_n30#" "li_1720_n30#" 199.5
+cap "a_6660_n30#" "v" 1301.39
+cap "a_2730_n30#" "v" 1301.39
+cap "a_5640_n30#" "v" 1301.39
cap "a_5640_n30#" "a_6660_n30#" 191.52
cap "a_4660_n30#" "v" 1301.39
cap "a_3680_n30#" "v" 1301.39
+cap "a_4660_n30#" "a_5640_n30#" 199.5
+cap "a_2730_n30#" "a_3680_n30#" 199.5
+cap "a_3680_n30#" "a_4660_n30#" 199.5
+cap "a_1720_n30#" "li_1720_n30#" 18.13
device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1920 0 "a_6660_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1920 0 "a_5640_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1920 0 "a_4660_n30#" 1440 0
@@ -45,20 +45,20 @@
device csubckt sky130_fd_pr__cap_mim_m3_1 2540 590 2541 591 w=560 l=560 "None" "v" 1920 0 "a_2730_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1920 0 "li_1720_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3760 0 "gnd!" 1440 0
+cap "switch_1/vin" "switch_1/vout" -0.157143
cap "switch_0/vcont" "switch_0/vout" 4.23077
cap "switch_0/vcont" "switch_0/vin" 83.635
-cap "switch_1/vin" "switch_1/vout" -0.157143
-cap "switch_1/vcont" "switch_1/vin" -136.5
-cap "switch_2/vout" "switch_2/vcont" 4.23077
-cap "switch_2/vin" "switch_2/vcont" 83.635
-cap "switch_1/vout" "switch_1/vcont" 4.23077
+cap "switch_1/vin" "switch_1/vcont" -136.5
+cap "switch_2/vcont" "switch_2/vout" 4.23077
+cap "switch_2/vcont" "switch_2/vin" 83.635
+cap "switch_1/vcont" "switch_1/vout" 4.23077
cap "switch_1/vcont" "switch_1/vin" 83.635
cap "switch_3/vcont" "switch_3/vout" 4.23077
cap "switch_3/vcont" "switch_3/vin" 83.635
+cap "switch_5/vcont" "switch_5/vout" 4.23077
+cap "switch_5/vcont" "switch_5/vin" 83.635
cap "switch_4/vcont" "switch_4/vout" 4.23077
cap "switch_4/vcont" "switch_4/vin" 83.635
-cap "switch_5/vout" "switch_5/vcont" 4.23077
-cap "switch_5/vin" "switch_5/vcont" 83.635
merge "switch_5/VSUBS" "switch_5/vout" -332.789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -21300 -442 0 0 0 0
merge "switch_5/vout" "switch_4/VSUBS"
merge "switch_4/VSUBS" "switch_4/vout"
diff --git a/mag/cp.ext b/mag/cp.ext
index d02f0a3..88e958a 100644
--- a/mag/cp.ext
+++ b/mag/cp.ext
@@ -1,4 +1,4 @@
-timestamp 1640911461
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -20,23 +20,23 @@
node "upbar" 658 1347.77 6750 -50 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0
node "vdd!" 18302 139352 -830 -170 nw 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0
substrate "gnd!" 0 0 -370 -2840 ndif 0 0 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0
+cap "a_1710_n2840#" "out" 606.81
+cap "vdd!" "out" 376.075
cap "upbar" "a_1710_n2840#" 291.6
cap "vdd!" "a_1710_n2840#" 254.08
cap "vdd!" "a_10_n50#" 530.297
-cap "a_10_n50#" "vbias" 192.9
-cap "vdd!" "upbar" 149.92
-cap "a_1710_n2840#" "a_1710_0#" 828.847
-cap "a_10_n50#" "a_1710_0#" 41.6842
-cap "a_1710_n2840#" "out" 606.81
cap "vdd!" "a_3060_n2840#" 320.4
cap "upbar" "down" 20.625
-cap "vdd!" "a_7110_0#" 42.55
+cap "vdd!" "upbar" 149.92
+cap "out" "a_1710_0#" 841.733
+cap "a_1710_n2840#" "a_1710_0#" 828.847
+cap "a_10_n50#" "a_1710_0#" 41.6842
cap "vdd!" "a_6370_0#" 402.828
cap "vdd!" "a_3060_0#" 1788.27
-cap "vdd!" "a_1710_0#" 714.147
-cap "vdd!" "out" 376.075
cap "a_1710_0#" "down" 320.4
-cap "out" "a_1710_0#" 841.733
+cap "vdd!" "a_1710_0#" 714.147
+cap "a_10_n50#" "vbias" 192.9
+cap "vdd!" "a_7110_0#" 42.55
device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/mag/divider.ext b/mag/divider.ext
index 9dc9e59..43e02d3 100644
--- a/mag/divider.ext
+++ b/mag/divider.ext
@@ -1,4 +1,4 @@
-timestamp 1640957771
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -40,62 +40,70 @@
node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0
node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0
substrate "a_n940_n20#" 0 0 -940 -20 ppd 0 0 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_5740_3250#" "li_5460_820#" 128.305
+cap "li_6130_3350#" "li_5740_3250#" 68.1032
+cap "w_2780_1920#" "m4_7030_1860#" 40.0711
+cap "w_2780_1920#" "vdd" 0.84
+cap "w_2780_1920#" "vdd" 9.82
+cap "w_2780_1920#" "vdd" 4.08
+cap "w_2780_1920#" "vdd" 8.88
+cap "mc2" "gnd" 27.9
cap "mc2" "m1_5770_3360#" 35.7143
cap "mc2" "li_7140_680#" 61.52
+cap "w_2780_1920#" "m1_5770_3360#" 53.84
+cap "vdd" "vdd" 33.5
+cap "vdd" "vdd" 51.2353
+cap "vdd" "vdd" 20.1
+cap "li_5560_680#" "m4_7020_30#" 24.425
+cap "mc2" "li_5740_3250#" 22.679
+cap "li_3980_680#" "gnd" 24.425
+cap "w_2780_1920#" "li_3310_1810#" 24.0375
+cap "li_3980_680#" "gnd" 27.1625
+cap "w_2780_1920#" "li_5740_3250#" 72.945
+cap "w_2780_1920#" "li_6130_3350#" 7.215
+cap "li_5740_3250#" "vdd" 27.9
+cap "li_3310_1810#" "vdd" 35.39
+cap "li_5740_3250#" "vdd" 27.9
cap "li_7140_680#" "m1_5770_3360#" 19.2857
cap "li_5560_680#" "m1_5770_3360#" 16.875
cap "li_5560_680#" "li_7140_680#" 437.5
cap "li_7040_820#" "m1_5770_3360#" 90
cap "li_3980_680#" "li_5560_680#" 782.5
cap "Out" "li_7140_680#" 23.5
-cap "mc2" "li_5740_3250#" 22.679
-cap "gnd" "li_3980_680#" 24.425
cap "li_7040_820#" "li_5560_680#" 15
-cap "gnd" "li_3980_680#" 27.1625
cap "li_5740_3250#" "m1_5770_3360#" 286.375
cap "li_5460_820#" "li_3980_680#" 20
cap "li_6130_3350#" "m1_5770_3360#" 136.842
cap "li_5740_3250#" "li_5560_680#" 21.9534
-cap "gnd" "mc2" 27.9
cap "li_5740_3250#" "li_3980_680#" 22.5
-cap "li_5740_3250#" "li_5460_820#" 128.305
-cap "vdd" "li_5740_3250#" 27.9
-cap "vdd" "li_3310_1810#" 35.39
-cap "vdd" "vdd" 33.5
-cap "vdd" "li_5740_3250#" 27.9
-cap "li_6130_3350#" "li_5740_3250#" 68.1032
-cap "vdd" "vdd" 51.2353
-cap "vdd" "vdd" 20.1
cap "w_2780_1920#" "li_2870_2670#" 76.8485
-cap "w_2780_1920#" "m1_5770_3360#" 53.84
-cap "w_2780_1920#" "m4_7030_1860#" 40.0711
-cap "m4_7020_30#" "li_5560_680#" 24.425
-cap "w_2780_1920#" "vdd" 0.84
-cap "w_2780_1920#" "li_3310_1810#" 24.0375
-cap "w_2780_1920#" "vdd" 9.82
-cap "w_2780_1920#" "li_5740_3250#" 72.945
-cap "w_2780_1920#" "vdd" 4.08
-cap "w_2780_1920#" "li_6130_3350#" 7.215
-cap "w_2780_1920#" "vdd" 8.88
cap "a_n940_n20#" "prescaler_0/nand_0/A" 17.3684
-cap "prescaler_0/tspc_0/a_630_n680#" "a_n940_n20#" 9.78378
-cap "prescaler_0/GND" "a_n940_n20#" 21.945
-cap "prescaler_0/tspc_0/Z2" "a_n940_n20#" 27.6618
+cap "a_n940_n20#" "prescaler_0/tspc_0/a_630_n680#" 9.78378
+cap "a_n940_n20#" "prescaler_0/GND" 21.945
+cap "a_n940_n20#" "prescaler_0/tspc_0/Z2" 27.6618
cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
cap "a_n940_n20#" "prescaler_0/tspc_1/Z2" 27.6618
cap "a_n940_n20#" "prescaler_0/tspc_1/GND" 30.14
-cap "a_n940_n20#" "tspc_0/GND" 21.945
-cap "tspc_0/Z4" "tspc_0/D" 35.0633
-cap "tspc_0/GND" "tspc_0/a_300_n150#" -3.55271e-15
-cap "tspc_0/Z2" "tspc_0/D" 141.466
-cap "tspc_0/GND" "tspc_0/D" 413.181
+cap "tspc_0/D" "tspc_0/Z4" 35.0633
+cap "tspc_0/a_300_n150#" "tspc_0/GND" -3.55271e-15
+cap "tspc_0/D" "tspc_0/Z2" 141.466
+cap "tspc_0/D" "tspc_0/GND" 413.181
cap "tspc_0/D" "tspc_0/Z3" 1.36364
-cap "tspc_0/GND" "tspc_0/w_n140_n70#" 0.12
-cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
-cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
-cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
cap "a_n940_n20#" "tspc_0/Z2" 27.6618
+cap "tspc_0/w_n140_n70#" "tspc_0/GND" 0.12
+cap "a_n940_n20#" "tspc_0/GND" 21.945
cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
+cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
+cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
+cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
+cap "tspc_1/D" "tspc_1/Z4" 33.0938
+cap "tspc_1/D" "tspc_1/Z2" 213.298
+cap "tspc_1/a_300_n150#" "tspc_1/Z4" 30.4615
+cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
+cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
+cap "tspc_1/a_300_n150#" "tspc_1/Z2" 25.8231
+cap "tspc_1/GND" "tspc_0/a_630_n680#" 7.61538
+cap "a_n940_n20#" "tspc_1/Z2" 27.6618
cap "tspc_1/D" "tspc_0/a_630_n680#" 5.45455
cap "tspc_1/D" "tspc_1/GND" 346.096
cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583
@@ -104,176 +112,172 @@
cap "tspc_0/a_740_n680#" "tspc_1/GND" 281.141
cap "tspc_1/a_300_n150#" "tspc_1/D" 70.641
cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795
-cap "a_n940_n20#" "tspc_1/Z2" 27.6618
cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 145.525
-cap "tspc_1/GND" "tspc_1/Z2" 7.81579
-cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17
-cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
-cap "tspc_1/D" "tspc_1/Z4" 33.0938
-cap "tspc_1/D" "tspc_1/Z2" 213.298
-cap "a_n940_n20#" "tspc_0/a_630_n680#" 9.78378
-cap "tspc_1/a_300_n150#" "tspc_1/Z4" 30.4615
-cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
cap "a_n940_n20#" "tspc_1/GND" 23.265
-cap "tspc_1/a_300_n150#" "tspc_1/Z2" 25.8231
-cap "tspc_1/GND" "tspc_0/a_630_n680#" 7.61538
+cap "a_n940_n20#" "tspc_0/a_630_n680#" 9.78378
+cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
+cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17
+cap "tspc_1/GND" "tspc_1/Z2" 7.81579
+cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
+cap "tspc_2/D" "tspc_2/gnd!" 339.551
+cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107
+cap "tspc_2/a_300_n150#" "tspc_2/gnd!" 21.2143
+cap "tspc_1/a_740_n680#" "tspc_2/gnd!" 440.385
+cap "tspc_2/a_300_n150#" "tspc_2/D" 70.641
+cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
+cap "a_n940_n20#" "tspc_2/Z2" 12.6176
+cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 155.525
cap "tspc_2/gnd!" "tspc_2/Z2" 7.81579
+cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378
cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "a_n940_n20#" "tspc_2/gnd!" 30.14
cap "tspc_2/D" "tspc_2/Z4" 20.0553
cap "tspc_2/D" "tspc_2/Z2" 309.898
cap "tspc_2/a_300_n150#" "tspc_2/Z4" 30.4615
cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882
cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
cap "tspc_2/a_300_n150#" "tspc_2/Z2" 25.8231
-cap "a_n940_n20#" "tspc_2/Z2" 12.6176
-cap "tspc_2/gnd!" "tspc_1/a_630_n680#" 7.61538
-cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
-cap "tspc_2/D" "tspc_2/gnd!" 339.551
-cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107
-cap "tspc_2/a_300_n150#" "tspc_2/gnd!" 21.2143
-cap "tspc_1/a_740_n680#" "tspc_2/gnd!" 440.385
cap "tspc_2/w_n140_n70#" "tspc_1/a_740_n680#" 0.065
-cap "tspc_2/a_300_n150#" "tspc_2/D" 70.641
-cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378
-cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
-cap "a_n940_n20#" "tspc_2/gnd!" 30.14
-cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 155.525
+cap "tspc_2/gnd!" "tspc_1/a_630_n680#" 7.61538
+cap "tspc_2/Z4" "li_5560_680#" 10.5882
cap "tspc_2/D" "tspc_2/a_630_n680#" 159.583
cap "tspc_2/D" "tspc_2/GND" 450.398
-cap "tspc_2/D" "tspc_2/Z4" 17.815
-cap "tspc_2/Z4" "li_5560_680#" 10.5882
-cap "a_n940_n20#" "tspc_2/GND" 23.265
cap "a_n940_n20#" "tspc_2/a_630_n680#" 9.78378
-cap "tspc_2/D" "tspc_2/Q" 20.775
+cap "tspc_2/D" "tspc_2/Z4" 17.815
+cap "a_n940_n20#" "tspc_2/GND" 23.265
cap "a_n940_n20#" "tspc_2/Z2" 15.0441
+cap "tspc_2/D" "tspc_2/Q" 20.775
cap "tspc_2/D" "tspc_2/Z3" 0.681818
cap "tspc_2/D" "tspc_2/a_300_n150#" -1.77636e-15
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 78.0797
cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/A" 12.2938
cap "a_n940_n20#" "prescaler_0/nand_0/A" 14.7632
+cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/D" -2.84217e-14
cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/vdd!" 4.57853
cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557
-cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 78.0797
-cap "prescaler_0/tspc_0/Z2" "prescaler_0/nand_0/VDD" -1.77636e-15
-cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 2.73
-cap "prescaler_0/tspc_2/Q" "prescaler_0/nand_0/VDD" 6.67557
+cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z2" -1.77636e-15
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 2.73
cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z1" -2.4869e-14
-cap "prescaler_0/tspc_1/vdd!" "prescaler_0/mc1" 73.8879
-cap "prescaler_0/tspc_1/Z3" "prescaler_0/tspc_1/vdd!" -2.37588e-14
-cap "prescaler_0/tspc_1/vdd!" "prescaler_0/nand_1/a_280_n230#" 14.3654
+cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557
cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z1" 3.19744e-14
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/mc1" 73.8879
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/nand_1/a_280_n230#" 14.3654
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z3" -2.37588e-14
cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z2" 6.92779e-14
-cap "tspc_0/vdd!" "prescaler_0/GND" 244.839
-cap "tspc_0/vdd!" "prescaler_0/mc1" 2.6129
-cap "tspc_0/vdd!" "tspc_0/Z2" 10
-cap "tspc_0/vdd!" "prescaler_0/tspc_1/Q" 19.25
-cap "tspc_0/vdd!" "prescaler_0/tspc_1/a_740_n680#" 114.95
+cap "prescaler_0/GND" "tspc_0/vdd!" 244.839
+cap "prescaler_0/mc1" "tspc_0/vdd!" 2.6129
cap "tspc_0/vdd!" "and_0/OUT" 7.5
-cap "tspc_1/w_n140_n70#" "tspc_1/vdd!" -3.46
-cap "tspc_1/a_300_n150#" "tspc_1/Z1" 7
+cap "tspc_0/Z2" "tspc_0/vdd!" 10
+cap "tspc_0/Z1" "tspc_0/vdd!" -2.4869e-14
+cap "prescaler_0/tspc_1/Q" "tspc_0/vdd!" 19.25
+cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/vdd!" 114.95
cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927
-cap "tspc_1/vdd!" "tspc_1/a_300_n150#" 93.7845
-cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 4.63
-cap "tspc_1/vdd!" "tspc_0/a_740_n680#" 177.528
+cap "tspc_1/w_n140_n70#" "tspc_1/vdd!" -3.46
cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 75.365
-cap "tspc_2/vdd!" "nor_0/vdd!" 224.245
+cap "tspc_1/vdd!" "tspc_1/a_300_n150#" 93.7845
+cap "tspc_1/vdd!" "tspc_0/a_740_n680#" 177.528
+cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 4.63
+cap "tspc_1/a_300_n150#" "tspc_1/Z1" 7
+cap "tspc_2/a_300_n150#" "tspc_2/Z1" 7
cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351
cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 75.365
cap "tspc_2/vdd!" "tspc_2/Z2" 4.44089e-16
cap "tspc_2/vdd!" "tspc_2/Z1" 2.2482e-14
-cap "tspc_2/vdd!" "tspc_2/a_300_n150#" 93.7845
cap "tspc_2/vdd!" "tspc_1/Z3" -2.37588e-14
+cap "tspc_2/vdd!" "tspc_2/a_300_n150#" 93.7845
cap "tspc_2/vdd!" "tspc_1/Z2" 3.10862e-14
-cap "tspc_2/a_300_n150#" "tspc_2/Z1" 7
cap "nor_0/vdd!" "tspc_1/a_740_n680#" 13.3333
cap "tspc_2/vdd!" "tspc_1/a_740_n680#" 76.5957
+cap "tspc_2/vdd!" "nor_0/vdd!" 224.245
cap "tspc_2/vdd!" "tspc_2/Q" -5.32907e-14
cap "tspc_2/vdd!" "tspc_2/Z3" -2.37588e-14
-cap "tspc_2/vdd!" "tspc_2/Z2" 3.73035e-14
cap "tspc_2/vdd!" "tspc_2/Z1" -1.90958e-14
+cap "tspc_2/vdd!" "tspc_2/Z2" 3.73035e-14
cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125
cap "w_n140_1520#" "prescaler_0/tspc_2/vdd!" 6.56545
cap "w_n140_1520#" "prescaler_0/tspc_2/Q" 27.2014
cap "prescaler_0/tspc_2/a_630_n680#" "mc2" 328.675
cap "prescaler_0/GND" "mc2" 319.267
cap "prescaler_0/tspc_2/Z2" "mc2" 136.815
-cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z1" -2.84217e-14
-cap "prescaler_0/tspc_2/a_630_n680#" "a_n940_n20#" 5.04167
-cap "prescaler_0/GND" "a_n940_n20#" 12.1359
-cap "prescaler_0/tspc_2/Q" "prescaler_0/tspc_2/vdd!" 9.57252
+cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z1" -2.4869e-14
+cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167
+cap "a_n940_n20#" "prescaler_0/GND" 12.1359
+cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Q" 9.57252
+cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/a_300_n150#" 5.55112e-16
+cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z3" -1.33227e-15
cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/a_740_n680#" -1.13687e-13
cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806
-cap "prescaler_0/tspc_2/Z2" "mc2" -280.235
-cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 19.9143
+cap "mc2" "prescaler_0/GND" 127.942
cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/a_280_n230#" 34.0634
+cap "mc2" "prescaler_0/tspc_2/Z2" -280.235
+cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 19.9143
cap "a_n940_n20#" "prescaler_0/GND" 3.58696
-cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/D" 1.13687e-13
+cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/D" 5.68434e-14
cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z2" 1.66533e-15
cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
-cap "prescaler_0/GND" "mc2" 127.942
-cap "and_0/out1" "prescaler_0/mc1" 48.6223
-cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566
+cap "mc2" "and_0/Z1" 74.215
+cap "prescaler_0/mc1" "and_0/vdd!" 39.6
+cap "mc2" "prescaler_0/mc1" 46.015
+cap "mc2" "prescaler_0/GND" 117.19
cap "and_0/VDD" "prescaler_0/GND" 23.0856
+cap "prescaler_0/m1_2700_2190#" "and_0/VDD" 36.6566
cap "a_n940_n20#" "and_0/Z1" 5.5
-cap "and_0/Z1" "mc2" 74.215
+cap "prescaler_0/mc1" "prescaler_0/GND" 22.72
+cap "mc2" "and_0/B" 13.94
cap "a_n940_n20#" "prescaler_0/GND" 5.09291
cap "and_0/VDD" "prescaler_0/mc1" 0.870968
-cap "prescaler_0/mc1" "mc2" 46.015
+cap "mc2" "and_0/out1" 59.955
+cap "and_0/out1" "prescaler_0/mc1" 48.6223
cap "a_n940_n20#" "prescaler_0/mc1" 3.20833
-cap "prescaler_0/GND" "mc2" 117.19
-cap "prescaler_0/mc1" "and_0/vdd!" 39.6
cap "a_n940_n20#" "and_0/out1" 3.20833
-cap "and_0/B" "mc2" 13.94
-cap "and_0/out1" "mc2" 59.955
-cap "prescaler_0/mc1" "prescaler_0/GND" 22.72
-cap "and_0/Z1" "mc2" -164.32
-cap "and_0/GND" "mc2" 364.635
-cap "nor_0/A" "mc2" 12.84
-cap "nor_0/B" "mc2" 12.84
cap "and_0/GND" "and_0/vdd!" -8.88178e-16
-cap "and_0/A" "mc2" 161.385
-cap "and_0/A" "nor_0/Z1" 22.8782
-cap "and_0/B" "nor_0/Z1" 181.56
-cap "and_0/A" "and_0/vdd!" 5.32907e-15
-cap "and_0/B" "and_0/vdd!" 90.78
-cap "nor_0/A" "and_0/GND" 1.28205
cap "nor_0/B" "nor_1/B" 2.64706
-cap "and_0/A" "and_0/GND" 16.9459
-cap "a_n940_n20#" "and_0/Z1" 0.916667
cap "nor_0/B" "nor_0/A" 58.3333
cap "and_0/B" "nor_0/A" 15.1125
-cap "a_n940_n20#" "and_0/GND" 6.50362
-cap "and_0/A" "nor_0/B" 13.2
cap "and_0/B" "nor_0/B" 84.4673
cap "and_0/VDD" "nor_0/A" 0.99
+cap "and_0/A" "nor_0/B" 13.2
cap "and_0/B" "and_0/A" 90.78
cap "and_0/VDD" "and_0/B" 4.29
cap "a_n940_n20#" "and_0/A" 7
-cap "nor_1/A" "nor_0/B" 15.1125
-cap "nor_1/A" "nor_1/Out" 180.039
-cap "nor_1/A" "nor_1/GND" 305.362
-cap "a_n940_n20#" "nor_1/GND" 2
-cap "a_n940_n20#" "nor_1/Out" 7
-cap "nor_1/B" "nor_0/B" 17.7596
+cap "mc2" "nor_0/A" 12.84
+cap "mc2" "nor_0/B" 12.84
+cap "mc2" "and_0/A" 161.385
+cap "nor_0/Z1" "and_0/A" 22.8782
+cap "and_0/vdd!" "and_0/B" 90.78
+cap "nor_0/Z1" "and_0/B" 181.56
+cap "and_0/vdd!" "and_0/A" 5.32907e-15
+cap "and_0/GND" "nor_0/A" 1.28205
+cap "and_0/Z1" "a_n940_n20#" 0.916667
+cap "and_0/GND" "and_0/A" 16.9459
+cap "and_0/GND" "a_n940_n20#" 6.50362
+cap "and_0/Z1" "mc2" -164.32
+cap "and_0/GND" "mc2" 364.635
cap "nor_0/VDD" "nor_0/B" -7.41
-cap "nor_1/B" "nor_1/Out" 41.7957
+cap "a_n940_n20#" "nor_1/Out" 7
cap "nor_0/VDD" "nor_1/Out" 4.29
-cap "nor_1/B" "nor_1/A" 14.5768
+cap "a_n940_n20#" "nor_1/GND" 2
cap "nor_1/Z1" "nor_0/B" 181.56
cap "nor_0/vdd!" "nor_0/B" 90.78
cap "nor_1/Out" "nor_0/B" 90.78
+cap "nor_1/A" "nor_0/B" 15.1125
+cap "nor_1/B" "nor_0/B" 17.7596
+cap "nor_1/A" "nor_1/GND" 305.362
+cap "nor_1/A" "nor_1/Out" 180.039
+cap "nor_1/B" "nor_1/Out" 41.7957
+cap "nor_1/B" "nor_1/A" 14.5768
cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806
cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167
cap "a_n940_n20#" "prescaler_0/GND" 12.1359
-cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
cap "a_n940_n20#" "prescaler_0/GND" 3.58696
-cap "a_n940_n20#" "and_0/Z1" 5.5
-cap "a_n940_n20#" "and_0/out1" 3.20833
+cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
cap "a_n940_n20#" "and_0/GND" 9.75595
cap "a_n940_n20#" "and_0/OUT" 3.20833
-cap "a_n940_n20#" "and_0/Z1" 0.916667
-cap "a_n940_n20#" "and_0/GND" 29.5
-cap "a_n940_n20#" "nor_0/Out" 7
+cap "a_n940_n20#" "and_0/Z1" 5.5
+cap "a_n940_n20#" "and_0/out1" 3.20833
+cap "and_0/Z1" "a_n940_n20#" 0.916667
+cap "nor_0/Out" "a_n940_n20#" 7
+cap "and_0/GND" "a_n940_n20#" 29.5
cap "a_n940_n20#" "nor_1/Out" 7
cap "a_n940_n20#" "nor_1/GND" 20.3333
merge "nor_1/GND" "nor_0/gnd!" -270.175 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70100 -2250 0 0 0 0
diff --git a/mag/nand.ext b/mag/nand.ext
index 6c9c973..b350f08 100644
--- a/mag/nand.ext
+++ b/mag/nand.ext
@@ -1,4 +1,4 @@
-timestamp 1640957032
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -15,9 +15,7 @@
node "VDD" 1727 1248 -80 -20 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "gnd!" "z1" 159.5
-cap "VDD" "OUT" 2.96
cap "OUT" "z1" 210.754
-cap "VDD" "vdd!" 29.2
cap "OUT" "gnd!" 22
cap "vdd!" "z1" 8.55556
cap "a_280_n230#" "z1" 70.125
@@ -29,6 +27,8 @@
cap "a_280_n230#" "vdd!" 13.0842
cap "A" "OUT" 9.74286
cap "A" "vdd!" 13.0842
+cap "VDD" "OUT" 2.96
+cap "VDD" "vdd!" 29.2
cap "A" "a_280_n230#" 81.6947
device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "VSUBS" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0
device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "z1" 200 0
diff --git a/mag/nor.ext b/mag/nor.ext
index 709296b..1ca382c 100644
--- a/mag/nor.ext
+++ b/mag/nor.ext
@@ -1,4 +1,4 @@
-timestamp 1640957264
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -14,22 +14,22 @@
node "A" 2231 379.695 -40 -100 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 3542 2250 -110 -30 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "Out" "VDD" 2.3125
-cap "B" "Z1" 57.75
-cap "vdd!" "gnd!" 9.625
-cap "Z1" "VDD" 2.775
-cap "B" "gnd!" 39.7045
-cap "vdd!" "VDD" 16.2425
-cap "A" "Out" 8.8
-cap "A" "gnd!" 19.25
-cap "A" "vdd!" 57.75
-cap "A" "B" 72.9302
+cap "Out" "gnd!" 453.75
+cap "Z1" "gnd!" 9.625
cap "Z1" "Out" 779.396
-cap "gnd!" "Out" 453.75
-cap "gnd!" "Z1" 9.625
+cap "vdd!" "gnd!" 9.625
+cap "B" "gnd!" 39.7045
cap "vdd!" "Out" 99
+cap "A" "gnd!" 19.25
cap "vdd!" "Z1" 749.833
cap "B" "Out" 246.8
+cap "A" "Out" 8.8
+cap "B" "Z1" 57.75
+cap "A" "vdd!" 57.75
+cap "A" "B" 72.9302
+cap "VDD" "Out" 2.3125
+cap "VDD" "Z1" 2.775
+cap "VDD" "vdd!" 16.2425
device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "VSUBS" "B" 60 0 "gnd!" 200 0 "Out" 200 0
device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "Out" 200 0
device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0
diff --git a/mag/pd.ext b/mag/pd.ext
index 3bbc905..925559a 100644
--- a/mag/pd.ext
+++ b/mag/pd.ext
@@ -1,4 +1,4 @@
-timestamp 1640958486
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -19,51 +19,51 @@
node "w_0_n1460#" 18910 2199.75 0 -1460 nw 0 0 0 0 662500 5900 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 45800 1300 0 0 0 0
node "VDD" 27087 2548.65 0 1160 nw 0 0 0 0 793200 7540 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 37400 1040 0 0 0 0
substrate "a_n420_n1430#" 0 0 -420 -1430 ppd 0 0 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0
-cap "w_0_n1460#" "VDD" 0.48
cap "VDD" "m4_1440_1280#" 4.92
+cap "VDD" "REF" 27.9
+cap "DOWN" "R" 185.417
cap "VDD" "UP" 7.2
+cap "VDD" "R" 11.2838
+cap "w_0_n1460#" "VDD" 0.48
+cap "VDD" "VDD" 0.48
cap "R" "GND" 53.75
cap "DOWN" "GND" 50.15
-cap "VDD" "GND" 113.9
cap "m1_2010_600#" "UP" 4.5
+cap "VDD" "GND" 113.9
cap "R" "UP" 72
-cap "VDD" "DIV" 27.9
cap "DOWN" "UP" 101.25
-cap "VDD" "REF" 27.9
-cap "VDD" "R" 11.2838
-cap "VDD" "VDD" 0.48
+cap "VDD" "DIV" 27.9
cap "DOWN" "m1_2010_600#" 41.625
-cap "DOWN" "R" 185.417
+cap "tspc_r_0/GND" "tspc_r_1/Z1" 14.4375
+cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375
+cap "tspc_r_0/GND" "tspc_r_1/VDD" 99.8267
+cap "tspc_r_0/GND" "tspc_r_1/Z3" 7.21875
+cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775
+cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.74
cap "tspc_r_1/VDD" "tspc_r_1/Z2" 72
-cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355
-cap "tspc_r_1/VDD" "tspc_r_1/w_n290_n40#" 33.74
-cap "tspc_r_1/VDD" "tspc_r_0/GND" 99.8267
cap "tspc_r_1/VDD" "tspc_r_1/Z3" 10.9091
cap "tspc_r_1/VDD" "tspc_r_1/R" 100
+cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355
cap "tspc_r_1/VDD" "tspc_r_1/clk" 62.5
-cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775
-cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375
-cap "tspc_r_0/GND" "tspc_r_1/Z1" 14.4375
-cap "tspc_r_0/GND" "tspc_r_1/Z3" 7.21875
cap "a_n420_n1430#" "tspc_r_1/Qbar" 7.21875
cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615
cap "a_n420_n1430#" "tspc_r_1/Q" 7.21875
-cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785
cap "a_n420_n1430#" "tspc_r_1/Qbar1" 7.21875
-cap "tspc_r_1/VDD" "tspc_r_1/Q" -2.37588e-14
cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 6.30607e-14
cap "tspc_r_1/VDD" "tspc_r_1/Z3" 8.88178e-15
+cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785
cap "tspc_r_1/VDD" "a_n420_n1430#" 45.2812
+cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31
+cap "tspc_r_0/GND" "tspc_r_0/Z4" 13.3333
+cap "tspc_r_0/GND" "tspc_r_0/R" 64.2857
+cap "tspc_r_0/VDD" "tspc_r_0/R" 66.6667
+cap "tspc_r_0/VDD" "tspc_r_0/Z2" 72
+cap "tspc_r_1/Z4" "tspc_r_0/GND" 13.3333
+cap "tspc_r_0/VDD" "tspc_r_0/Z3" 10.9091
cap "tspc_r_0/VDD" "tspc_r_0/clk" 44.4444
cap "tspc_r_0/GND" "tspc_r_0/VDD" 150.325
-cap "tspc_r_0/GND" "tspc_r_1/Z4" 13.3333
-cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595
-cap "tspc_r_0/GND" "tspc_r_0/Z4" 13.3333
-cap "tspc_r_0/VDD" "tspc_r_0/R" 66.6667
-cap "tspc_r_0/GND" "tspc_r_0/R" 64.2857
-cap "tspc_r_0/VDD" "tspc_r_0/Z2" 72
-cap "tspc_r_0/VDD" "tspc_r_0/Z3" 10.9091
-cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31
+cap "tspc_r_1/Z4" "tspc_r_0/Z4" 19.4595
+cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595
cap "and_pd_0/GND" "tspc_r_1/z5" 13.3333
cap "and_pd_0/GND" "tspc_r_0/z5" 13.3333
cap "tspc_r_0/Qbar" "and_pd_0/Z1" 21.0517
@@ -83,42 +83,41 @@
cap "tspc_r_0/clk" "tspc_r_0/R" 103.99
cap "and_pd_0/B" "and_pd_0/Out1" -14.35
cap "and_pd_0/B" "and_pd_0/A" 183.938
-cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595
-cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231
-cap "and_pd_0/A" "and_pd_0/Z1" -23.46
-cap "a_n420_n1430#" "and_pd_0/Z1" 0.916667
cap "and_pd_0/Out" "and_pd_0/GND" 16.129
+cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231
cap "and_pd_0/Out1" "and_pd_0/Out" 137.14
-cap "and_pd_0/A" "and_pd_0/GND" 113.28
cap "and_pd_0/B" "and_pd_0/Out" 222.129
-cap "and_pd_0/A" "and_pd_0/Out" 90.78
-cap "a_n420_n1430#" "and_pd_0/GND" 9.20833
-cap "and_pd_0/VDD" "and_pd_0/Out" 56.5714
cap "and_pd_0/B" "and_pd_0/Out1" 70.6975
+cap "a_n420_n1430#" "and_pd_0/GND" 9.20833
+cap "a_n420_n1430#" "and_pd_0/Z1" 0.916667
cap "a_n420_n1430#" "and_pd_0/Out" 72.7883
-cap "and_pd_0/A" "and_pd_0/Out1" 105.892
cap "a_n420_n1430#" "and_pd_0/Out1" 6.41667
-cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15
+cap "and_pd_0/A" "and_pd_0/Z1" -23.46
+cap "and_pd_0/A" "and_pd_0/Out" 90.78
+cap "and_pd_0/A" "and_pd_0/GND" 113.28
+cap "and_pd_0/VDD" "and_pd_0/Out" 56.5714
cap "and_pd_0/VDD" "and_pd_0/Out1" 12.375
+cap "and_pd_0/A" "and_pd_0/Out1" 105.892
cap "and_pd_0/A" "and_pd_0/B" 58.428
-cap "a_n420_n1430#" "tspc_r_0/Z3" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375
+cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15
cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775
+cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375
cap "a_n420_n1430#" "tspc_r_0/Z1" 14.4375
-cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74
cap "a_n420_n1430#" "tspc_r_0/VDD" 56.7013
-cap "tspc_r_0/Q" "and_pd_0/A" 2.15625
-cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Qbar" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Q" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Qbar1" 7.21875
-cap "and_pd_0/VDD" "and_pd_0/a_n60_n30#" 43.07
-cap "a_n420_n1430#" "and_pd_0/a_n60_n30#" 54.6607
-cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571
+cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74
+cap "a_n420_n1430#" "tspc_r_0/Z3" 7.21875
cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 6.1875
-cap "a_n420_n1430#" "and_pd_0/VDD" 18.7589
-cap "a_n420_n1430#" "and_pd_0/Out" 9.96875
-cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875
+cap "and_pd_0/Out1" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Qbar" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Q" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Qbar1" "a_n420_n1430#" 7.21875
+cap "and_pd_0/a_n60_n30#" "a_n420_n1430#" 54.6607
+cap "and_pd_0/a_n60_n30#" "and_pd_0/VDD" 43.07
+cap "and_pd_0/A" "tspc_r_0/Q" 2.15625
+cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571
+cap "and_pd_0/Out" "a_n420_n1430#" 9.96875
+cap "and_pd_0/Out1" "a_n420_n1430#" 7.21875
+cap "and_pd_0/VDD" "a_n420_n1430#" 18.7589
merge "and_pd_0/VSUBS" "and_pd_0/GND" -6351.75 0 0 0 0 0 0 0 0 0 0 -55010 -7926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 572500 -19033 0 0 0 0 0 0 -601300 -9300 0 0 0 0
merge "and_pd_0/GND" "tspc_r_1/VSUBS"
merge "tspc_r_1/VSUBS" "tspc_r_1/GND"
diff --git a/mag/prescaler.ext b/mag/prescaler.ext
index 4c762aa..e0e18d2 100644
--- a/mag/prescaler.ext
+++ b/mag/prescaler.ext
@@ -1,4 +1,4 @@
-timestamp 1640957100
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -29,36 +29,31 @@
node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "m4_2730_1520#" 23.6471
+cap "m2_970_460#" "VDD" 42
+cap "Out" "GND" 27.9
+cap "mc1" "m4_2730_1520#" 23.175
+cap "mc1" "VDD" 41.675
+cap "li_3590_420#" "clk" 168.462
+cap "mc1" "m4_350_1060#" 84.575
cap "li_3590_420#" "m2_970_460#" 183.333
cap "Out" "m1_2700_2190#" 27.465
-cap "w_1930_2072#" "m2_970_460#" 42.9324
cap "li_3590_420#" "m1_2700_2190#" 23.5
cap "li_2030_420#" "m2_970_460#" 17.38
cap "li_450_280#" "clk" 28.72
-cap "w_390_530#" "m4_350_1060#" 2.9032
cap "li_3590_420#" "Out" 716.418
cap "mc1" "m2_970_460#" 37.515
cap "li_2030_420#" "Out" 197.97
cap "li_n310_330#" "clk" 28.72
cap "mc1" "m1_2700_2190#" 63.2343
cap "li_1980_2130#" "m2_970_460#" 138.025
-cap "w_1930_2072#" "mc1" 2.7456
-cap "w_1930_2072#" "li_1980_2130#" 10.7855
+cap "w_390_530#" "m4_350_1060#" 2.9032
+cap "w_1930_2072#" "VDD" 1.964
cap "li_n310_330#" "li_3590_420#" 92.2845
cap "li_n310_330#" "mc1" 37.515
-cap "GND" "m4_2730_1520#" 23.6471
-cap "m2_970_460#" "VDD" 42
-cap "w_1930_2072#" "VDD" 1.964
-cap "Out" "GND" 27.9
-cap "mc1" "m4_2730_1520#" 23.175
-cap "mc1" "VDD" 41.675
-cap "li_3590_420#" "clk" 168.462
-cap "mc1" "m4_350_1060#" 84.575
-cap "tspc_0/a_300_n150#" "nand_0/A" 17.42
-cap "tspc_0/D" "nand_0/A" 29.5549
-cap "nand_0/a_280_n230#" "tspc_0/Z4" 106.442
-cap "tspc_0/D" "tspc_0/vdd!" 45.9643
-cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12
+cap "w_1930_2072#" "m2_970_460#" 42.9324
+cap "w_1930_2072#" "mc1" 2.7456
+cap "w_1930_2072#" "li_1980_2130#" 10.7855
cap "nand_0/a_280_n230#" "nand_0/z1" 153.26
cap "nand_0/a_280_n230#" "tspc_0/GND" 124.422
cap "tspc_0/D" "tspc_0/Z4" 12.3811
@@ -69,87 +64,92 @@
cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225
cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16
cap "tspc_0/D" "nand_0/z1" 2.11538
-cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861
-cap "tspc_0/Q" "li_3590_420#" 142.71
-cap "tspc_0/Q" "tspc_1/Z3" 3.50402
-cap "tspc_0/Z3" "li_3590_420#" 57.62
-cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378
-cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16
-cap "tspc_0/a_740_n680#" "li_3590_420#" 150.46
-cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347
-cap "tspc_1/Z2" "tspc_0/GND" 16.9342
-cap "tspc_0/Q" "tspc_1/Z4" 102.17
+cap "tspc_0/a_300_n150#" "nand_0/A" 17.42
+cap "tspc_0/D" "tspc_0/vdd!" 45.9643
+cap "tspc_0/D" "nand_0/A" 29.5549
+cap "nand_0/a_280_n230#" "tspc_0/Z4" 106.442
+cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12
+cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533
cap "tspc_0/Q" "tspc_0/GND" 51.0882
-cap "tspc_0/Q" "tspc_1/Z2" 85.89
+cap "tspc_1/Z4" "li_3590_420#" 55.1
cap "tspc_0/Q" "tspc_1/Z1" 39.5832
cap "tspc_0/Q" "tspc_1/vdd!" 59.1194
-cap "tspc_0/a_740_n680#" "tspc_1/Z4" 4.09091
-cap "tspc_1/Z4" "li_3590_420#" 55.1
-cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533
-cap "tspc_0/GND" "li_3590_420#" 198.939
+cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16
+cap "tspc_1/Z2" "tspc_0/GND" 16.9342
cap "tspc_0/vdd!" "tspc_1/vdd!" 38.2105
+cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861
cap "tspc_0/a_300_n150#" "tspc_0/Z3" 198.42
-cap "tspc_0/Z4" "li_3590_420#" 107.677
-cap "tspc_1/Z2" "li_3590_420#" 43.32
+cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378
+cap "tspc_0/Q" "tspc_1/Z2" 85.89
+cap "tspc_0/GND" "li_3590_420#" 198.939
+cap "tspc_0/Q" "li_3590_420#" 142.71
+cap "tspc_0/Q" "tspc_1/Z3" 3.50402
+cap "tspc_0/Q" "tspc_1/Z4" 102.17
cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4
-cap "tspc_1/Z2" "tspc_1/Q" 12.84
+cap "tspc_0/Z4" "li_3590_420#" 107.677
+cap "tspc_0/a_740_n680#" "li_3590_420#" 150.46
+cap "tspc_1/Z2" "li_3590_420#" 43.32
+cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347
+cap "tspc_0/a_740_n680#" "tspc_1/Z4" 4.09091
+cap "tspc_0/Z3" "li_3590_420#" 57.62
cap "tspc_1/Z4" "tspc_0/a_740_n680#" 1.92857
-cap "tspc_0/Q" "tspc_1/Q" 50.6
+cap "tspc_1/Q" "tspc_1/Z4" 104.585
+cap "tspc_1/Q" "tspc_1/GND" 218.86
+cap "tspc_1/Z3" "tspc_1/Q" 156.507
+cap "tspc_1/Z2" "tspc_1/Q" 12.84
+cap "tspc_0/Q" "tspc_1/GND" 39.1
cap "tspc_0/Q" "tspc_1/Z4" 78.2567
cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785
-cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
+cap "tspc_0/Q" "tspc_1/Q" 50.6
cap "tspc_0/Q" "tspc_1/Z3" 59.529
+cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
cap "tspc_0/Q" "tspc_1/Z2" 9.99
cap "tspc_0/Q" "tspc_1/a_300_n150#" 179.587
cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65
-cap "tspc_1/Q" "tspc_1/GND" 218.86
-cap "tspc_0/Q" "tspc_1/GND" 39.1
-cap "tspc_1/Q" "tspc_1/Z4" 104.585
-cap "tspc_1/Z3" "tspc_1/Q" 156.507
+cap "tspc_0/w_n140_n70#" "mc1" 9.165
cap "tspc_0/vdd!" "mc1" 162.542
cap "tspc_0/vdd!" "tspc_0/Z2" 10
+cap "tspc_0/Z2" "mc1" 46.8
cap "tspc_2/Q" "tspc_0/vdd!" 32.5248
cap "tspc_0/w_n140_n70#" "tspc_0/vdd!" -3.656
-cap "tspc_0/Z2" "mc1" 46.8
-cap "tspc_0/w_n140_n70#" "mc1" 9.165
-cap "tspc_0/Z2" "mc1" 17.4522
cap "tspc_0/vdd!" "tspc_2/Z2" 10
cap "tspc_0/vdd!" "tspc_0/Q" 44.0676
cap "tspc_2/D" "tspc_2/Z1" 99.6765
cap "nand_1/a_280_n230#" "tspc_0/vdd!" 7.33333
cap "tspc_2/D" "tspc_0/vdd!" 272.242
-cap "tspc_2/w_n140_n70#" "tspc_0/vdd!" -11.884
cap "tspc_2/D" "nand_1/a_280_n230#" 9.77778
-cap "tspc_2/w_n140_n70#" "tspc_2/D" 8.1659
-cap "tspc_1/Z2" "mc1" 18
cap "tspc_2/a_300_n150#" "tspc_0/vdd!" 166.667
-cap "tspc_2/w_n140_n70#" "tspc_2/a_300_n150#" 2.0976
+cap "tspc_1/Z2" "mc1" 18
+cap "tspc_2/w_n140_n70#" "mc1" 24.5544
cap "tspc_2/a_300_n150#" "tspc_2/D" -6.9
cap "tspc_2/D" "nand_1/z1" 6
cap "tspc_2/Z2" "mc1" 53.3571
cap "tspc_0/vdd!" "mc1" 414.897
+cap "tspc_2/w_n140_n70#" "tspc_0/vdd!" -11.884
cap "tspc_0/vdd!" "tspc_1/Z2" 4.35484
-cap "tspc_2/w_n140_n70#" "mc1" 24.5544
cap "tspc_0/Q" "tspc_1/Z1" 10.4211
-cap "tspc_1/Z2" "nand_1/A" 46.2522
-cap "tspc_1/vdd!" "nand_1/A" 227.695
-cap "tspc_1/vdd!" "nand_1/a_280_n230#" 13.125
-cap "tspc_1/vdd!" "tspc_2/w_n140_n70#" -6.44
+cap "tspc_2/w_n140_n70#" "tspc_2/D" 8.1659
+cap "tspc_0/Z2" "mc1" 17.4522
+cap "tspc_2/w_n140_n70#" "tspc_2/a_300_n150#" 2.0976
+cap "nand_1/GND" "tspc_1/vdd!" 39.5155
cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889
-cap "nand_1/OUT" "nand_1/z1" 1.83333
+cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132
cap "nand_1/A" "nand_1/OUT" 22.3793
cap "tspc_2/w_n140_n70#" "nand_1/A" 9.555
-cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132
-cap "tspc_1/a_740_n680#" "nand_1/a_280_n230#" 1.36364
-cap "nand_1/GND" "tspc_1/vdd!" 39.5155
+cap "nand_1/A" "tspc_1/vdd!" 227.695
+cap "nand_1/a_280_n230#" "tspc_1/vdd!" 13.125
+cap "nand_1/OUT" "nand_1/z1" 1.83333
+cap "tspc_2/w_n140_n70#" "tspc_1/vdd!" -6.44
+cap "nand_1/a_280_n230#" "tspc_1/a_740_n680#" 1.36364
+cap "nand_1/A" "tspc_1/Z2" 46.2522
cap "tspc_2/Q" "tspc_2/a_740_n680#" 18.4737
cap "nand_1/z1" "tspc_2/D" 14
+cap "tspc_2/D" "tspc_2/Z4" 7.71692
cap "tspc_2/vdd!" "tspc_2/D" 47.4
cap "tspc_2/Z1" "tspc_2/D" 20.5588
-cap "tspc_2/D" "tspc_2/a_300_n150#" 0.18
-cap "tspc_2/D" "tspc_2/Z3" 5.25747
-cap "tspc_2/D" "tspc_2/w_n140_n70#" 3.0525
-cap "tspc_2/Z4" "tspc_2/D" 7.71692
+cap "tspc_2/a_300_n150#" "tspc_2/D" 0.18
+cap "tspc_2/Z3" "tspc_2/D" 5.25747
+cap "tspc_2/w_n140_n70#" "tspc_2/D" 3.0525
cap "nand_1/OUT" "nand_1/z1" 2.75
merge "tspc_2/gnd!" "tspc_2/GND" -681.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -218700 -3450 0 0 0 0
merge "tspc_2/GND" "nand_1/GND"
diff --git a/mag/ro_complete.ext b/mag/ro_complete.ext
index 699ee8a..e00dc88 100644
--- a/mag/ro_complete.ext
+++ b/mag/ro_complete.ext
@@ -1,4 +1,4 @@
-timestamp 1640959832
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -18,119 +18,119 @@
node "li_1010_1400#" 88 1456.19 1010 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1200 19600 560 19600 560 19600 560 196600 4100 0 0 0 0
node "li_7140_1400#" 85 6989.63 7140 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50400 1320 32400 720 2607360 22208 57600 960 57600 960 0 0 0 0
substrate "a_7790_n10640#" 0 0 7790 -10640 ppd 0 0 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1036800 17280 1349800 21100 1085200 18160 1085200 18160 3951000 27540 0 0 0 0
-cap "a5" "li_4080_1390#" 77.72
+cap "li_4080_1390#" "a5" 77.72
cap "a5" "li_7140_1400#" 100.96
-cap "cbank_2/a0" "cbank_2/switch_0/vout" 46.5385
+cap "cbank_2/switch_0/vout" "cbank_2/a0" 46.5385
cap "cbank_2/a2" "cbank_2/switch_2/vout" 46.5385
cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385
-cap "cbank_2/switch_3/vout" "cbank_2/a3" 46.5385
+cap "cbank_2/a3" "cbank_2/switch_3/vout" 46.5385
cap "cbank_2/a5" "cbank_2/switch_5/vout" 12.6923
cap "cbank_2/a4" "cbank_2/switch_4/vout" 46.5385
-cap "li_7140_1400#" "cbank_2/switch_5/vin" 24
-cap "cbank_2/switch_5/vout" "cbank_2/a5" 33.8462
+cap "cbank_2/switch_5/vin" "li_7140_1400#" 24
+cap "cbank_2/a5" "cbank_2/switch_5/vout" 33.8462
cap "cbank_1/gnd!" "cbank_2/v" 86.7059
-cap "cbank_1/switch_1/vin" "a0" 21.8167
-cap "cbank_1/gnd!" "cbank_2/v" 275.882
-cap "cbank_1/gnd!" "a0" 181.38
cap "a0" "cbank_2/v" 53.41
-cap "cbank_2/v" "cbank_1/switch_1/vout" 275.882
-cap "a2" "cbank_1/switch_1/vout" 60.0024
-cap "a1" "cbank_1/switch_1/vout" 209.96
-cap "a1" "cbank_2/v" 53.41
-cap "cbank_1/switch_2/vin" "a1" 23.6566
-cap "cbank_1/switch_4/vin" "a3" 11.4157
cap "cbank_1/gnd!" "cbank_2/v" 275.882
+cap "cbank_1/switch_1/vin" "a0" 21.8167
+cap "cbank_1/gnd!" "a0" 181.38
+cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882
+cap "a1" "cbank_2/v" 53.41
+cap "cbank_1/switch_1/vout" "a2" 60.0024
+cap "cbank_1/switch_2/vin" "a1" 23.6566
+cap "cbank_1/switch_1/vout" "a1" 209.96
+cap "a3" "cbank_2/v" 53.41
+cap "cbank_1/switch_4/vin" "a3" 11.4157
+cap "a2" "cbank_2/v" 53.41
cap "cbank_1/switch_3/vin" "a2" 23.515
+cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/gnd!" "a3" 192.323
cap "cbank_1/gnd!" "a2" 124.302
-cap "a3" "cbank_2/v" 53.41
-cap "a2" "cbank_2/v" 53.41
-cap "a4" "li_7140_1400#" 53.41
cap "cbank_1/switch_4/vout" "li_7140_1400#" 275.882
cap "cbank_1/switch_5/vin" "a4" 20.5602
cap "cbank_1/switch_4/vout" "a4" 190.632
+cap "a4" "li_7140_1400#" 53.41
cap "cbank_1/switch_4/vin" "a3" 11.4157
+cap "cbank_1/switch_5/vout" "a5" 124.931
cap "cbank_1/switch_5/vout" "a_7790_n10640#" 162.097
cap "li_7140_1400#" "cbank_2/a_6660_n30#" 126
cap "cbank_1/switch_5/vout" "li_7140_1400#" 233.936
-cap "cbank_1/switch_5/vout" "a5" 124.931
cap "cbank_1/gnd!" "a_7790_n10640#" 45.6818
cap "cbank_1/a0" "cbank_1/switch_1/vin" 106.517
cap "cbank_1/a0" "cbank_1/switch_0/vout" 248.36
cap "cbank_1/a2" "cbank_1/switch_1/vout" 149.619
cap "cbank_1/a1" "cbank_1/switch_2/vin" 115.5
cap "cbank_1/a1" "cbank_1/switch_1/vout" 289.235
-cap "cbank_1/a3" "cbank_1/switch_4/vin" 55.7355
+cap "cbank_1/gnd!" "cbank_1/a2" 103.081
cap "cbank_1/a2" "cbank_1/switch_3/vin" 114.808
cap "cbank_1/gnd!" "cbank_1/a3" 264.413
-cap "cbank_1/gnd!" "cbank_1/a2" 103.081
-cap "cbank_1/switch_4/vin" "a3" 55.7355
+cap "cbank_1/a3" "cbank_1/switch_4/vin" 55.7355
cap "cbank_1/a5" "cbank_1/switch_4/vout" 12.6923
-cap "cbank_1/a4" "cbank_1/switch_5/vin" 100.382
+cap "cbank_1/switch_4/vin" "a3" 55.7355
cap "cbank_1/a4" "cbank_1/switch_4/vout" 261.965
+cap "cbank_1/a4" "cbank_1/switch_5/vin" 100.382
cap "cbank_1/a5" "cbank_1/switch_5/vout" 143.406
cap "cbank_0/gnd!" "cbank_1/v" 47.5484
-cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_1/a0" "cbank_1/v" 53.41
-cap "cbank_1/v" "cbank_1/a1" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 151.29
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
+cap "cbank_1/a1" "cbank_1/v" 53.41
+cap "cbank_1/v" "cbank_1/a2" 53.41
cap "cbank_1/v" "cbank_0/gnd!" 151.29
cap "cbank_1/v" "cbank_1/a3" 53.41
-cap "cbank_1/v" "cbank_1/a2" 53.41
cap "cbank_0/gnd!" "li_4080_1390#" 151.29
cap "cbank_1/a4" "li_4080_1390#" 53.41
cap "cbank_0/gnd!" "li_4080_1390#" 41.6979
cap "cbank_1/switch_5/vin" "li_4080_1390#" 133.875
cap "cbank_0/gnd!" "cbank_1/v" 47.5484
cap "cbank_0/switch_1/vin" "a0" 82.3167
-cap "cbank_1/v" "cbank_0/gnd!" 151.29
-cap "a0" "cbank_0/gnd!" 296.011
-cap "cbank_0/switch_1/vout" "cbank_1/v" 151.29
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
+cap "cbank_0/gnd!" "a0" 296.011
cap "cbank_0/switch_1/vout" "a2" 118.551
cap "cbank_0/switch_2/vin" "a1" 89.259
cap "cbank_0/switch_1/vout" "a1" 347.808
+cap "cbank_0/switch_1/vout" "cbank_1/v" 151.29
cap "cbank_0/switch_4/vin" "a3" 43.0727
cap "cbank_0/switch_3/vin" "a2" 88.7246
-cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_0/gnd!" "a3" 316.073
cap "cbank_0/gnd!" "a2" 182.851
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_0/switch_4/vout" "li_4080_1390#" 151.29
cap "cbank_0/switch_5/vin" "a4" 77.5759
cap "cbank_0/switch_4/vout" "a4" 312.991
cap "cbank_0/switch_4/vin" "a3" 43.0727
-cap "cbank_0/switch_5/vout" "a5" 187.16
-cap "cbank_0/switch_5/vout" "a_7790_n10640#" 193.269
cap "cbank_0/switch_5/vout" "li_4080_1390#" 438.698
cap "cbank_0/switch_5/vout" "li_7140_1400#" 142.26
+cap "cbank_0/switch_5/vout" "a5" 187.16
+cap "cbank_0/switch_5/vout" "a_7790_n10640#" 193.269
cap "cbank_0/gnd!" "a_7790_n10640#" 45.6818
cap "cbank_0/a0" "cbank_0/switch_1/vin" 46.0167
cap "cbank_0/a0" "cbank_0/switch_0/vout" 133.728
-cap "cbank_0/a2" "cbank_0/switch_2/vout" 91.0707
cap "cbank_0/a1" "cbank_0/switch_2/vin" 49.8976
cap "cbank_0/a1" "cbank_0/switch_1/vout" 151.387
-cap "cbank_0/switch_3/vout" "cbank_0/a3" 140.663
-cap "cbank_0/switch_4/vin" "cbank_0/a3" 24.0785
-cap "cbank_0/switch_3/vin" "cbank_0/a2" 49.5988
-cap "cbank_0/switch_2/vout" "cbank_0/a2" 44.5323
+cap "cbank_0/a2" "cbank_0/switch_2/vout" 91.0707
+cap "cbank_0/a3" "cbank_0/switch_4/vin" 24.0785
+cap "cbank_0/a3" "cbank_0/switch_3/vout" 140.663
+cap "cbank_0/a2" "cbank_0/switch_3/vin" 49.5988
+cap "cbank_0/a2" "cbank_0/switch_2/vout" 44.5323
+cap "cbank_0/a4" "cbank_0/switch_4/vout" 139.606
cap "cbank_0/switch_4/vin" "a3" 24.0785
cap "cbank_0/a5" "cbank_0/switch_5/vout" 12.6923
cap "cbank_0/a4" "cbank_0/switch_5/vin" 43.3665
-cap "cbank_0/a4" "cbank_0/switch_4/vout" 139.606
cap "cbank_0/a5" "cbank_0/switch_5/vout" 81.1776
cap "ro_var_extend_0/gnd" "cbank_0/v" 151.9
-cap "li_4080_1390#" "ro_var_extend_0/gnd" 796.97
+cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97
cap "ro_var_extend_0/gnd" "li_4080_1390#" 769.58
cap "ro_var_extend_0/w_n120_n750#" "li_4080_1390#" 415.935
cap "ro_var_extend_0/w_n120_n750#" "li_7140_1400#" 294.59
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 69.0462
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
-cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55
-cap "ro_var_extend_0/out2" "ro_var_extend_0/w_n120_n750#" 184.5
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
+cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 214.76
cap "ro_var_extend_0/gnd" "ro_var_extend_0/vcont" -11.167
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 392.251
diff --git a/mag/ro_var_extend.ext b/mag/ro_var_extend.ext
index de1eaa2..caeb12f 100644
--- a/mag/ro_var_extend.ext
+++ b/mag/ro_var_extend.ext
@@ -1,4 +1,4 @@
-timestamp 1640959680
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -14,15 +14,15 @@
node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
node "vdd" 21463 18367.8 -250 320 nw 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 -710 -890 ppd 0 0 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
-cap "out1" "out2" 40.8506
cap "w_n120_n750#" "vcont" 140.194
cap "out3" "out2" 1263.05
cap "w_n120_n750#" "out2" 789.263
cap "out3" "out1" 1156.32
cap "w_n120_n750#" "out1" 569.035
cap "vdd" "out2" 235.622
-cap "w_n120_n750#" "out3" 215.464
cap "vdd" "out1" 230.66
+cap "out1" "out2" 40.8506
+cap "w_n120_n750#" "out3" 215.464
cap "vdd" "out3" 230.554
device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0
device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0
diff --git a/mag/switch.ext b/mag/switch.ext
index fadf98e..bde0ba2 100644
--- a/mag/switch.ext
+++ b/mag/switch.ext
@@ -1,4 +1,4 @@
-timestamp 1640608635
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -10,6 +10,6 @@
node "vcont" 1139 384.82 -40 1460 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "vin" "vout" 420
+cap "vin" "vcont" 8.25
cap "vcont" "vout" 16.5
-cap "vcont" "vin" 8.25
device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "VSUBS" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/mag/tspc.ext b/mag/tspc.ext
index 9b3f9ec..53116c0 100644
--- a/mag/tspc.ext
+++ b/mag/tspc.ext
@@ -1,4 +1,4 @@
-timestamp 1640956963
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -19,54 +19,54 @@
node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0
node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "Q" "w_n140_n70#" 6.845
-cap "Z1" "w_n140_n70#" 4.1625
-cap "vdd!" "a_300_n150#" 20.3736
-cap "vdd!" "Z3" 671.367
-cap "D" "Z2" 91.0218
-cap "a_300_n150#" "w_n140_n70#" 0.665
-cap "Z3" "w_n140_n70#" 2.3125
-cap "vdd!" "Z2" 359.159
-cap "Z2" "w_n140_n70#" 14.44
-cap "vdd!" "D" 19.4229
-cap "vdd!" "w_n140_n70#" 85.4425
-cap "a_740_n680#" "a_630_n680#" 190.867
-cap "a_740_n680#" "gnd!" 224.895
-cap "a_740_n680#" "Z4" 82.0167
+cap "gnd!" "a_630_n680#" 610.469
+cap "Z4" "a_630_n680#" 121.707
cap "Q" "a_630_n680#" 36.6667
-cap "a_300_n150#" "a_630_n680#" 9.625
+cap "Z4" "gnd!" 441.644
cap "Z3" "a_630_n680#" 54.2903
cap "Q" "gnd!" 289.808
cap "Z2" "a_630_n680#" 6.6
cap "Z3" "gnd!" 265.176
-cap "a_300_n150#" "gnd!" 22.7597
-cap "Z1" "Z4" 3.38462
-cap "a_300_n150#" "Z4" 118.945
cap "Z3" "Z4" 651.52
cap "Z2" "gnd!" 156.712
cap "Z2" "Z4" 361.112
-cap "D" "gnd!" 27.9314
-cap "D" "Z4" 97.7372
-cap "vdd!" "Z4" 7.7
-cap "a_740_n680#" "Q" 178.823
-cap "a_740_n680#" "a_300_n150#" 12.4103
-cap "a_740_n680#" "Z3" 334.495
-cap "a_740_n680#" "vdd!" 515.003
-cap "a_740_n680#" "w_n140_n70#" 18.5775
-cap "gnd!" "a_630_n680#" 610.469
+cap "a_300_n150#" "a_630_n680#" 9.625
cap "Z3" "Q" 52.8649
-cap "Z3" "Z1" 62.0085
-cap "Z4" "a_630_n680#" 121.707
-cap "Z2" "Z1" 1068.12
-cap "Z3" "a_300_n150#" 446.312
-cap "Z4" "gnd!" 441.644
+cap "a_300_n150#" "gnd!" 22.7597
+cap "Z1" "Z4" 3.38462
+cap "D" "gnd!" 27.9314
+cap "a_300_n150#" "Z4" 118.945
cap "Z2" "Z3" 161.5
-cap "Z2" "a_300_n150#" 110.226
-cap "D" "Z1" 26.4
+cap "a_740_n680#" "a_630_n680#" 190.867
+cap "D" "Z4" 97.7372
+cap "Z1" "Z3" 62.0085
+cap "a_740_n680#" "gnd!" 224.895
+cap "vdd!" "Z4" 7.7
+cap "Z1" "Z2" 1068.12
+cap "a_300_n150#" "Z3" 446.312
+cap "a_740_n680#" "Z4" 82.0167
cap "D" "Z3" 46.1286
-cap "vdd!" "Z1" 583.229
cap "vdd!" "Q" 607.82
+cap "a_300_n150#" "Z2" 110.226
+cap "a_740_n680#" "Q" 178.823
+cap "vdd!" "Z3" 671.367
+cap "D" "Z2" 91.0218
+cap "D" "Z1" 26.4
+cap "vdd!" "Z2" 359.159
+cap "w_n140_n70#" "Q" 6.845
+cap "a_740_n680#" "Z3" 334.495
+cap "vdd!" "Z1" 583.229
+cap "w_n140_n70#" "Z3" 2.3125
cap "D" "a_300_n150#" 132.679
+cap "vdd!" "a_300_n150#" 20.3736
+cap "w_n140_n70#" "Z2" 14.44
+cap "a_740_n680#" "a_300_n150#" 12.4103
+cap "vdd!" "D" 19.4229
+cap "w_n140_n70#" "Z1" 4.1625
+cap "w_n140_n70#" "a_300_n150#" 0.665
+cap "a_740_n680#" "vdd!" 515.003
+cap "w_n140_n70#" "vdd!" 85.4425
+cap "w_n140_n70#" "a_740_n680#" 18.5775
device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "VSUBS" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0
device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "VSUBS" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0
device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "VSUBS" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0
diff --git a/mag/tspc_r.ext b/mag/tspc_r.ext
index 44bd29b..4cfeba5 100644
--- a/mag/tspc_r.ext
+++ b/mag/tspc_r.ext
@@ -1,4 +1,4 @@
-timestamp 1640770827
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
@@ -21,61 +21,61 @@
node "D" 1470 418.74 -250 -140 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "clk" "Z3" 652.716
-cap "D" "clk" 31.5485
-cap "w_n290_n40#" "Qbar" 1.85
-cap "w_n290_n40#" "Z2" 3.04
-cap "w_n290_n40#" "Z1" 7.4
-cap "w_n290_n40#" "VDD" 7.4
-cap "Q" "z5" 33
-cap "Qbar1" "z5" 203.056
-cap "Z3" "z5" 110
-cap "Q" "GND" 263.95
-cap "Z3" "Z4" 201.943
-cap "Qbar1" "GND" 157.761
-cap "Qbar1" "R" 11.3571
-cap "clk" "z5" 38.3774
-cap "Z3" "GND" 324.951
-cap "Q" "Qbar" 213.204
-cap "Qbar1" "Qbar" 7.54286
-cap "clk" "Z4" 18.15
-cap "Z3" "R" 137.379
-cap "clk" "GND" 37.5833
-cap "D" "GND" 14.4375
-cap "Q" "VDD" 334.95
-cap "Z3" "Z2" 249.04
-cap "clk" "R" 508.778
-cap "Qbar1" "VDD" 315.732
-cap "Z3" "Z1" 85.3
-cap "D" "R" 16.14
-cap "Z3" "VDD" 509.325
-cap "clk" "Z2" 187.91
-cap "clk" "Z1" 170.927
-cap "D" "Z2" 47.3222
-cap "clk" "VDD" 129.37
-cap "D" "VDD" 38.5
cap "Z4" "z5" 42.0885
-cap "w_n290_n40#" "Q" 1.85
-cap "w_n290_n40#" "Qbar1" 1.82
cap "GND" "z5" 558.112
cap "GND" "Z4" 527.304
-cap "w_n290_n40#" "Z3" 11.56
-cap "w_n290_n40#" "clk" 10.355
cap "R" "GND" 35.3744
cap "Qbar" "GND" 138.6
cap "Z2" "Z4" 137.657
cap "VDD" "z5" 6.6
cap "Z2" "GND" 142.361
+cap "Q" "z5" 33
cap "Z2" "R" 208.97
+cap "Qbar1" "z5" 203.056
cap "VDD" "GND" 17.6
+cap "Z3" "z5" 110
+cap "Q" "GND" 263.95
+cap "Z3" "Z4" 201.943
+cap "Qbar1" "GND" 157.761
+cap "clk" "z5" 38.3774
cap "VDD" "Qbar" 237.6
cap "Z1" "Z2" 709.991
-cap "Qbar1" "Q" 109.835
+cap "Qbar1" "R" 11.3571
+cap "Z3" "GND" 324.951
+cap "clk" "Z4" 18.15
+cap "Q" "Qbar" 213.204
cap "VDD" "Z2" 95.0921
-cap "Z3" "Q" 28.6775
+cap "Qbar1" "Qbar" 7.54286
+cap "clk" "GND" 37.5833
+cap "Z3" "R" 137.379
cap "VDD" "Z1" 316.564
+cap "D" "GND" 14.4375
+cap "clk" "R" 508.778
+cap "Q" "VDD" 334.95
+cap "Z3" "Z2" 249.04
+cap "D" "R" 16.14
+cap "Qbar1" "VDD" 315.732
+cap "Z3" "Z1" 85.3
+cap "clk" "Z2" 187.91
+cap "Z3" "VDD" 509.325
+cap "clk" "Z1" 170.927
+cap "w_n290_n40#" "Qbar" 1.85
+cap "D" "Z2" 47.3222
+cap "Qbar1" "Q" 109.835
+cap "clk" "VDD" 129.37
+cap "w_n290_n40#" "Z2" 3.04
+cap "Z3" "Q" 28.6775
+cap "D" "VDD" 38.5
+cap "w_n290_n40#" "Z1" 7.4
cap "Z3" "Qbar1" 379.384
+cap "w_n290_n40#" "VDD" 7.4
cap "clk" "Qbar1" 121.715
+cap "w_n290_n40#" "Q" 1.85
+cap "clk" "Z3" 652.716
+cap "w_n290_n40#" "Qbar1" 1.82
+cap "w_n290_n40#" "Z3" 11.56
+cap "D" "clk" 31.5485
+cap "w_n290_n40#" "clk" 10.355
device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "VSUBS" "Q" 60 0 "GND" 180 0 "Qbar" 180 0
device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "VSUBS" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0
device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "VSUBS" "Z3" 60 0 "GND" 180 0 "z5" 180 0
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
index cdc468b..9ebbad4 100644
--- a/mag/user_analog_project_wrapper.ext
+++ b/mag/user_analog_project_wrapper.ext
@@ -1,15 +1,14 @@
-timestamp 1640959832
+timestamp 1640960365
version 8.3
tech sky130A
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use cp cp_1 1 0 531400 0 1 683270
-use cp cp_0 1 0 196464 0 1 608714
-use filter filter_0 1 0 224356 0 1 680484
-use divider divider_0 1 0 163690 0 1 648664
-use pd pd_0 1 0 87306 0 1 647408
use ro_complete ro_complete_0 1 0 31596 0 1 681444
+use pd pd_0 1 0 87306 0 1 647408
+use divider divider_0 1 0 163690 0 1 648664
+use cp cp_0 1 0 196464 0 1 608714
+use cp cp_1 1 0 531400 0 1 683270
port "io_analog[4]" 41 329294 702300 334294 704800 m5
port "io_analog[4]" 47 318994 702300 323994 704800 m5
port "io_analog[5]" 42 227594 702300 232594 704800 m5
@@ -1393,13 +1392,17 @@
node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "io_analog[3]" "vssa1" 6389.64
+cap "io_analog[6]" "io_analog[6]" 21250
cap "io_analog[1]" "io_analog[0]" 12301.4
+cap "io_analog[0]" "vdda1" 18313.2
+cap "io_analog[1]" "vdda1" 23516.2
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[2]" "vdda1" 219.25
+cap "io_analog[3]" "vssa1" 6389.64
cap "io_analog[2]" "vssa1" 9275.17
cap "io_clamp_high[0]" "io_analog[4]" 525
cap "io_clamp_low[0]" "io_clamp_high[0]" 525
cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "w_534750_683750#" "w_534690_682780#" 224.4
cap "io_clamp_high[1]" "io_analog[5]" 525
cap "io_clamp_low[1]" "io_clamp_high[1]" 525
cap "io_analog[5]" "io_clamp_low[1]" 525
@@ -1412,31 +1415,27 @@
cap "io_analog[5]" "io_analog[5]" 26250
cap "io_analog[4]" "io_analog[4]" 21250
cap "io_analog[6]" "io_analog[6]" 26250
+cap "w_534690_682780#" "w_534750_683750#" 224.4
cap "io_analog[4]" "io_analog[4]" 21250
cap "io_analog[5]" "io_analog[5]" 21250
cap "io_analog[6]" "io_analog[6]" 26250
cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[0]" "vdda1" 18313.2
-cap "io_analog[1]" "vdda1" 23516.2
-cap "io_analog[2]" "vdda1" 219.25
cap "cp_1/gnd!" "cp_1/down" 439.89
cap "cp_1/gnd!" "io_analog[1]" -20.89
cap "cp_1/vbias" "cp_1/gnd!" 6.79412
cap "cp_1/vbias" "cp_1/gnd!" 8.73529
cap "cp_1/vbias" "cp_1/gnd!" 6.79412
-cap "cp_1/gnd!" "cp_1/vbias" 8.73529
+cap "cp_1/vbias" "cp_1/gnd!" 8.73529
cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68
-cap "cp_1/a_1710_0#" "cp_1/a_1710_n2840#" 37.5
cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 99.11
cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 243.801
-cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86
-cap "w_534750_683750#" "w_534690_682780#" -39.04
-cap "w_534690_682780#" "w_534750_683750#" -28
+cap "cp_1/a_1710_0#" "cp_1/a_1710_n2840#" 37.5
+cap "w_534690_682780#" "cp_1/a_3060_0#" 1083.86
+cap "w_534690_682780#" "w_534750_683750#" -39.04
cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4
-cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49
+cap "w_534750_683750#" "w_534690_682780#" -28
cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25
+cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49
cap "w_534750_683750#" "w_534690_682780#" -15.96
cap "cp_1/vdd!" "cp_1/vdd!" 27.826
cap "cp_1/vdd!" "cp_1/upbar" 248.023
@@ -1446,8 +1445,7 @@
merge "w_534690_682780#" "w_534750_683750#"
merge "cp_1/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0
merge "vssa1" "ro_complete_0/a_7790_n10640#"
-merge "ro_complete_0/a_7790_n10640#" "filter_0/v"
-merge "filter_0/v" "divider_0/a_n940_n20#"
+merge "ro_complete_0/a_7790_n10640#" "divider_0/a_n940_n20#"
merge "divider_0/a_n940_n20#" "pd_0/a_n420_n1430#"
merge "pd_0/a_n420_n1430#" "cp_0/gnd!"
merge "cp_0/gnd!" "VSUBS"
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 8e79934..fc16ed3 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1640959863
+timestamp 1640960365
<< nwell >>
rect 267375 341875 267540 343575
rect 267345 341390 267565 341585
@@ -862,30 +862,26 @@
rect -50 0 0 352000
rect 292000 0 292050 352000
rect -50 -50 292050 0
-use cp cp_1
-timestamp 1640911461
-transform 1 0 265700 0 1 341635
-box -415 -1715 4690 2035
-use cp cp_0
-timestamp 1640911461
-transform 1 0 98232 0 1 304357
-box -415 -1715 4690 2035
-use filter filter_0
-timestamp 1640921877
-transform 1 0 112178 0 1 340242
-box -1800 -10450 6065 390
-use divider divider_0
-timestamp 1640959863
-transform 1 0 81845 0 1 324332
-box -490 -235 4690 2150
-use pd pd_0
-timestamp 1640959863
-transform 1 0 43653 0 1 323704
-box -215 -855 1685 810
use ro_complete ro_complete_0
-timestamp 1640959832
+timestamp 1640960365
transform 1 0 15798 0 1 340722
box -57 -5330 4455 1440
+use pd pd_0
+timestamp 1640960365
+transform 1 0 43653 0 1 323704
+box -215 -855 1685 810
+use divider divider_0
+timestamp 1640960365
+transform 1 0 81845 0 1 324332
+box -490 -235 4690 2150
+use cp cp_0
+timestamp 1640960365
+transform 1 0 98232 0 1 304357
+box -415 -1715 4690 2035
+use cp cp_1
+timestamp 1640960365
+transform 1 0 265700 0 1 341635
+box -415 -1715 4690 2035
<< labels >>
flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index f5e5cb0..14390ac 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,427 +106,426 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-C0 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
-C1 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
-C2 gnd divider_0/clk 0.07fF
-C3 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
-C4 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
-C5 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
-C6 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C7 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
-C8 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
-C9 divider_0/mc2 divider_0/and_0/out1 0.06fF
-C10 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
-C11 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
-C12 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF
-C13 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
-C14 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C15 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
-C16 divider_0/and_0/OUT divider_0/clk 0.04fF
-C17 gnd divider_0/nor_0/B 1.08fF
-C18 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
-C19 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C20 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
-C21 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF
-C22 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF
-C23 pd_0/R pd_0/UP 0.45fF
-C24 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C25 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C26 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
-C27 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF
-C28 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
-C29 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF
-C30 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF
-C31 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C33 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C34 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
-C35 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
-C36 gnd divider_0/tspc_0/Z4 0.44fF
-C37 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C38 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C39 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C40 divider_0/and_0/A divider_0/and_0/B 0.18fF
-C41 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C42 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
-C43 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF
-C44 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF
-C45 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF
-C46 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
-C47 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
-C48 gnd divider_0/tspc_2/Z2 0.16fF
-C49 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF
-C50 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
-C51 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C52 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
-C53 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF
-C54 io_clamp_high[2] io_analog[6] 0.53fF
-C55 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C56 divider_0/tspc_1/Z3 gnd 0.27fF
-C57 divider_0/mc2 divider_0/nor_0/B 0.15fF
-C58 cp_0/upbar cp_0/down 0.02fF
-C59 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C60 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF
-C61 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF
-C62 divider_0/nor_1/A divider_0/and_0/A 0.01fF
-C63 io_analog[2] io_analog[1] 0.02fF
-C64 gnd divider_0/and_0/A 0.53fF
-C65 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C66 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C67 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
-C68 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
-C69 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
-C70 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C71 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C72 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF
-C73 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
-C74 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C75 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF
-C76 gnd divider_0/Out 0.29fF
-C77 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
-C78 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
-C79 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
-C80 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
-C81 io_clamp_low[1] io_analog[5] 0.53fF
-C82 divider_0/nor_1/B divider_0/tspc_0/Q 0.22fF
-C83 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF
-C84 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF
-C85 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
-C86 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
-C87 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C88 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF
-C89 divider_0/prescaler_0/tspc_2/D gnd 0.05fF
-C90 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF
-C91 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C92 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C93 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C94 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C95 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C96 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
-C97 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C98 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C99 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
-C100 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C101 pd_0/R pd_0/and_pd_0/Z1 0.02fF
-C102 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
-C103 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF
-C104 divider_0/mc2 divider_0/and_0/A 0.16fF
-C105 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
-C106 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
-C107 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C108 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
-C109 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C110 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF
-C111 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
-C112 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
-C113 pd_0/DIV pd_0/R 0.51fF
-C114 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
-C115 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C116 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
-C117 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
-C118 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
-C119 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C120 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C121 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
-C122 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF
-C123 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF
-C124 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C125 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF
-C126 gnd divider_0/prescaler_0/nand_1/z1 0.16fF
-C127 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
-C128 cp_1/a_10_n50# cp_1/a_1710_0# 0.04fF
-C129 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C130 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
-C131 gnd divider_0/and_0/Z1 0.41fF
-C132 pd_0/DOWN pd_0/UP 0.46fF
-C133 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
-C134 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C135 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C136 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C137 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C138 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
-C139 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF
-C140 divider_0/tspc_1/Z2 divider_0/tspc_0/Q 0.14fF
-C141 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
-C142 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
-C143 divider_0/tspc_0/Z3 gnd 0.27fF
-C144 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
-C145 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
-C146 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
-C147 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF
-C148 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
-C149 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
-C150 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
-C151 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF
-C152 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
-C153 io_clamp_high[0] io_analog[4] 0.53fF
-C154 divider_0/nor_1/B divider_0/and_0/B 0.31fF
-C155 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C156 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF
-C157 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
-C158 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C159 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C160 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
-C161 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C162 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
-C163 divider_0/tspc_1/Z4 divider_0/tspc_0/Q 0.15fF
-C164 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF
-C165 pd_0/R pd_0/REF 0.61fF
-C166 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C167 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
-C168 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF
-C169 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C170 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF
-C171 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF
-C172 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF
-C173 io_analog[0] cp_1/a_1710_0# 0.84fF
-C174 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C175 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C176 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
-C177 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
-C178 divider_0/nor_0/B divider_0/Out 0.22fF
-C179 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF
-C180 gnd divider_0/prescaler_0/Out 0.46fF
-C181 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
-C182 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
-C183 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C184 divider_0/nor_1/B gnd 1.10fF
-C185 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
-C186 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
-C187 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
-C188 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
-C189 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF
-C190 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
-C191 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF
-C192 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
-C193 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF
-C194 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF
-C195 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C196 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
-C197 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF
-C198 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C199 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF
-C200 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C201 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
-C202 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
-C203 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
-C204 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
-C205 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C206 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
-C207 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF
-C208 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C209 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF
-C210 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF
-C211 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
-C212 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
-C213 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
-C214 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
-C215 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C216 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
-C217 gnd divider_0/tspc_0/Q 0.33fF
-C218 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
-C219 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
-C220 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
-C221 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C222 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
-C223 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C224 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C225 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF
-C226 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
-C227 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C228 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
-C229 divider_0/tspc_0/Z2 gnd 0.16fF
-C230 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
-C231 divider_0/nor_1/B divider_0/mc2 0.06fF
-C232 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
-C233 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF
-C234 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
-C235 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C236 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
-C237 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
-C238 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF
-C239 io_clamp_low[2] io_analog[6] 0.53fF
-C240 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
-C241 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C242 divider_0/tspc_1/Z2 gnd 0.16fF
-C243 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
-C244 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
-C245 divider_0/nor_1/Z1 gnd 0.01fF
-C246 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
-C247 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF
-C248 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C249 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C250 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C251 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
-C252 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
-C253 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C254 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C255 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
-C256 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
-C257 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C258 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C259 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF
-C260 cp_0/a_1710_0# cp_0/out 0.84fF
-C261 pd_0/R pd_0/and_pd_0/Out1 0.33fF
-C262 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
-C263 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
-C264 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF
-C265 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
-C266 divider_0/tspc_1/Z4 gnd 0.44fF
-C267 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF
-C268 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C269 gnd divider_0/tspc_2/Z3 0.27fF
-C270 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
-C271 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
-C272 cp_1/a_1710_0# io_analog[1] 0.32fF
-C273 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C274 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C275 divider_0/tspc_1/a_630_n680# gnd 0.62fF
-C276 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
-C277 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF
-C278 divider_0/prescaler_0/Out divider_0/clk 0.51fF
-C279 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
-C280 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C281 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C282 divider_0/tspc_1/Q gnd 0.33fF
-C283 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
-C284 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/mc2 0.33fF
-C285 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
-C286 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C287 divider_0/nor_1/A divider_0/and_0/B 0.08fF
-C288 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF
-C289 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF
-C290 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
-C291 io_analog[0] io_analog[1] 12.30fF
-C292 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
-C293 gnd divider_0/and_0/B 0.45fF
-C294 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C295 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
-C296 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C297 cp_0/a_1710_0# cp_0/down 0.32fF
-C298 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
-C299 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C300 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF
-C301 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C302 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
-C303 gnd divider_0/tspc_2/Z4 0.44fF
-C304 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF
-C305 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
-C306 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C307 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
-C308 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
-C309 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C310 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF
-C311 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
-C312 io_clamp_high[1] io_analog[5] 0.53fF
-C313 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
-C314 divider_0/tspc_1/Z1 divider_0/tspc_0/Q 0.01fF
-C315 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C316 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
-C317 divider_0/nor_1/A gnd 1.02fF
-C318 cp_0/a_1710_n2840# cp_0/out 0.61fF
-C319 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C320 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF
-C321 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C322 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C323 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C324 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
-C325 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
-C326 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C327 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
-C328 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C329 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF
-C330 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
-C331 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
-C332 divider_0/tspc_0/a_630_n680# gnd 0.62fF
-C333 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C334 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
-C335 divider_0/and_0/OUT gnd 0.28fF
-C336 divider_0/mc2 divider_0/and_0/B 0.20fF
-C337 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C338 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
-C339 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
-C340 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C341 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C342 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF
-C343 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
-C344 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
-C345 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
-C346 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
-C347 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C348 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
-C349 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
-C350 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
-C351 cp_0/upbar cp_0/a_1710_n2840# 0.29fF
-C352 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
-C353 io_clamp_low[0] io_analog[4] 0.53fF
-C354 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C355 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C356 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
-C357 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
-C358 divider_0/nor_1/B divider_0/and_0/A 0.26fF
-C359 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
-C360 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C361 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF
-C362 divider_0/nor_0/Z1 gnd 0.01fF
-C363 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C364 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF
-C365 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C366 divider_0/mc2 divider_0/nor_1/A 0.04fF
-C367 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
-C368 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C369 divider_0/mc2 gnd 1.36fF
-C370 cp_0/a_10_n50# cp_0/vbias 0.19fF
-C371 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
-C372 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C373 divider_0/tspc_1/Z3 divider_0/tspc_0/Q 0.45fF
-C374 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF
-C375 divider_0/prescaler_0/tspc_0/D gnd 0.05fF
-C376 io_analog[3] cp_1/a_10_n50# 0.22fF
-C377 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C378 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C379 gnd divider_0/and_0/out1 0.23fF
-C380 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
-C381 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
-C382 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
-C383 pd_0/DOWN pd_0/R 0.36fF
-C384 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
-C385 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
-C386 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
-C387 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
-C388 divider_0/mc2 divider_0/and_0/OUT 0.05fF
-C389 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
-C390 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C391 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
-C392 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
-C393 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
-C394 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
-C395 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C396 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
-C397 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF
-C398 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
-C399 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF
-C400 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
-C401 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
-C402 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
-C403 gnd divider_0/tspc_2/a_630_n680# 0.61fF
-C404 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C405 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C406 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
-C407 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF
-C408 divider_0/nor_0/B divider_0/and_0/B 0.29fF
-C409 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
-C410 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C411 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF
-C412 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF
-C413 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF
-C414 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C415 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
-C416 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C0 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
+C1 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C2 divider_0/nor_1/B gnd 1.10fF
+C3 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
+C4 cp_0/a_10_n50# io_analog[3] 0.22fF
+C5 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
+C6 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
+C7 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF
+C8 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF
+C9 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
+C10 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
+C11 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
+C12 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF
+C13 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF
+C14 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C15 io_analog[0] io_analog[1] 12.30fF
+C16 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF
+C17 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C18 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
+C19 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF
+C20 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C21 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
+C22 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
+C23 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
+C24 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
+C25 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
+C26 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C27 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
+C28 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF
+C29 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
+C30 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C31 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF
+C32 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF
+C33 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
+C34 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
+C35 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
+C36 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
+C37 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C38 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
+C39 gnd divider_0/tspc_0/Q 0.33fF
+C40 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
+C41 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C42 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
+C43 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C44 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C45 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF
+C46 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C47 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
+C48 divider_0/tspc_0/Z2 gnd 0.16fF
+C49 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
+C50 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
+C51 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
+C52 divider_0/nor_1/B divider_0/mc2 0.06fF
+C53 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
+C54 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF
+C55 cp_1/upbar cp_1/down 0.02fF
+C56 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C57 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
+C58 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
+C59 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF
+C60 io_clamp_low[2] io_analog[6] 0.53fF
+C61 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
+C62 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
+C63 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
+C64 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C65 divider_0/tspc_1/Z2 gnd 0.16fF
+C66 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
+C67 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
+C68 divider_0/nor_1/Z1 gnd 0.01fF
+C69 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
+C70 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF
+C71 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
+C72 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C73 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C74 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
+C75 pd_0/R pd_0/UP 0.45fF
+C76 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C77 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
+C78 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C79 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
+C80 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C81 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C82 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF
+C83 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF
+C84 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
+C85 divider_0/tspc_1/Z4 gnd 0.44fF
+C86 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF
+C87 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
+C88 pd_0/DOWN pd_0/R 0.36fF
+C89 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
+C90 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
+C91 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
+C92 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C93 gnd divider_0/tspc_2/Z3 0.27fF
+C94 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C95 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C96 divider_0/tspc_1/a_630_n680# gnd 0.62fF
+C97 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
+C98 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF
+C99 divider_0/prescaler_0/Out divider_0/clk 0.51fF
+C100 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C101 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C102 divider_0/tspc_1/Q gnd 0.33fF
+C103 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
+C104 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/mc2 0.33fF
+C105 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
+C106 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C107 divider_0/nor_1/A divider_0/and_0/B 0.08fF
+C108 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF
+C109 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C110 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF
+C111 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
+C112 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C113 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
+C114 gnd divider_0/and_0/B 0.45fF
+C115 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C116 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
+C117 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C118 io_analog[2] io_analog[1] 0.02fF
+C119 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C120 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF
+C121 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
+C122 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
+C123 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C124 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
+C125 gnd divider_0/tspc_2/Z4 0.44fF
+C126 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF
+C127 cp_1/a_10_n50# cp_1/a_1710_0# 0.04fF
+C128 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C129 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
+C130 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
+C131 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C132 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF
+C133 io_clamp_high[1] io_analog[5] 0.53fF
+C134 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
+C135 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
+C136 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
+C137 divider_0/tspc_1/Z1 divider_0/tspc_0/Q 0.01fF
+C138 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C139 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
+C140 divider_0/nor_1/A gnd 1.02fF
+C141 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
+C142 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C143 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF
+C144 cp_1/upbar cp_1/a_1710_n2840# 0.29fF
+C145 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C146 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C147 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C148 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
+C149 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
+C150 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
+C151 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C152 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
+C153 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C154 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF
+C155 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
+C156 divider_0/tspc_0/a_630_n680# gnd 0.62fF
+C157 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
+C158 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
+C159 divider_0/and_0/OUT gnd 0.28fF
+C160 divider_0/mc2 divider_0/and_0/B 0.20fF
+C161 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C162 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
+C163 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
+C164 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C165 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C166 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF
+C167 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
+C168 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
+C169 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C170 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
+C171 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
+C172 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
+C173 io_clamp_low[0] io_analog[4] 0.53fF
+C174 pd_0/R pd_0/and_pd_0/Z1 0.02fF
+C175 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C176 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C177 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
+C178 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
+C179 divider_0/nor_1/B divider_0/and_0/A 0.26fF
+C180 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
+C181 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C182 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF
+C183 divider_0/nor_0/Z1 gnd 0.01fF
+C184 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C185 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF
+C186 cp_1/out cp_1/a_1710_0# 0.84fF
+C187 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C188 divider_0/mc2 divider_0/nor_1/A 0.04fF
+C189 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
+C190 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
+C191 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C192 divider_0/mc2 gnd 1.36fF
+C193 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C194 divider_0/tspc_1/Z3 divider_0/tspc_0/Q 0.45fF
+C195 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF
+C196 divider_0/prescaler_0/tspc_0/D gnd 0.05fF
+C197 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C198 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C199 gnd divider_0/and_0/out1 0.23fF
+C200 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
+C201 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
+C202 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
+C203 pd_0/DOWN pd_0/UP 0.46fF
+C204 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
+C205 divider_0/mc2 divider_0/and_0/OUT 0.05fF
+C206 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
+C207 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C208 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C209 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
+C210 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF
+C211 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
+C212 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF
+C213 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
+C214 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
+C215 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
+C216 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
+C217 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
+C218 gnd divider_0/tspc_2/a_630_n680# 0.61fF
+C219 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C220 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C221 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
+C222 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF
+C223 divider_0/nor_0/B divider_0/and_0/B 0.29fF
+C224 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
+C225 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C226 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF
+C227 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF
+C228 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF
+C229 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C230 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
+C231 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C232 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
+C233 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
+C234 gnd divider_0/clk 0.07fF
+C235 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
+C236 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C237 divider_0/mc2 divider_0/and_0/out1 0.06fF
+C238 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
+C239 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
+C240 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF
+C241 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
+C242 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
+C243 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C244 pd_0/DIV pd_0/R 0.51fF
+C245 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
+C246 divider_0/and_0/OUT divider_0/clk 0.04fF
+C247 gnd divider_0/nor_0/B 1.08fF
+C248 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C249 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
+C250 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF
+C251 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF
+C252 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
+C253 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
+C254 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C255 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C256 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
+C257 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF
+C258 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
+C259 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF
+C260 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF
+C261 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C262 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C263 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
+C264 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C265 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
+C266 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
+C267 gnd divider_0/tspc_0/Z4 0.44fF
+C268 cp_1/a_1710_0# cp_1/down 0.32fF
+C269 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
+C270 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
+C271 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C272 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C273 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C274 divider_0/and_0/A divider_0/and_0/B 0.18fF
+C275 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C276 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF
+C277 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF
+C278 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF
+C279 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
+C280 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
+C281 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
+C282 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
+C283 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
+C284 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
+C285 gnd divider_0/tspc_2/Z2 0.16fF
+C286 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF
+C287 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C288 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C289 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF
+C290 io_clamp_high[2] io_analog[6] 0.53fF
+C291 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
+C292 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C293 divider_0/tspc_1/Z3 gnd 0.27fF
+C294 divider_0/mc2 divider_0/nor_0/B 0.15fF
+C295 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C296 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF
+C297 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF
+C298 divider_0/nor_1/A divider_0/and_0/A 0.01fF
+C299 pd_0/R pd_0/REF 0.61fF
+C300 gnd divider_0/and_0/A 0.53fF
+C301 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C302 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C303 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C304 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C305 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF
+C306 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
+C307 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C308 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
+C309 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF
+C310 gnd divider_0/Out 0.29fF
+C311 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
+C312 io_clamp_low[1] io_analog[5] 0.53fF
+C313 cp_0/a_1710_0# io_analog[0] 0.84fF
+C314 pd_0/R pd_0/and_pd_0/Out1 0.33fF
+C315 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
+C316 divider_0/nor_1/B divider_0/tspc_0/Q 0.22fF
+C317 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF
+C318 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF
+C319 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
+C320 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C321 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C322 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
+C323 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF
+C324 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF
+C325 divider_0/prescaler_0/tspc_2/D gnd 0.05fF
+C326 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C327 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C328 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C329 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C330 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
+C331 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C332 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C333 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C334 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C335 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
+C336 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C337 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF
+C338 divider_0/mc2 divider_0/and_0/A 0.16fF
+C339 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
+C340 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
+C341 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C342 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
+C343 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
+C344 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
+C345 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C346 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF
+C347 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
+C348 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
+C349 cp_1/a_1710_n2840# cp_1/a_1710_0# 0.83fF
+C350 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
+C351 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C352 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
+C353 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
+C354 cp_0/a_1710_0# io_analog[1] 0.32fF
+C355 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
+C356 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C357 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C358 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
+C359 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF
+C360 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
+C361 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF
+C362 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C363 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
+C364 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF
+C365 gnd divider_0/prescaler_0/nand_1/z1 0.16fF
+C366 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
+C367 cp_1/vbias cp_1/a_10_n50# 0.19fF
+C368 cp_1/out cp_1/a_1710_n2840# 0.61fF
+C369 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C370 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
+C371 gnd divider_0/and_0/Z1 0.41fF
+C372 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C373 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C374 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C375 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
+C376 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C377 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
+C378 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF
+C379 divider_0/tspc_1/Z2 divider_0/tspc_0/Q 0.14fF
+C380 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
+C381 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
+C382 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
+C383 divider_0/tspc_0/Z3 gnd 0.27fF
+C384 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
+C385 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
+C386 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
+C387 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF
+C388 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF
+C389 io_clamp_high[0] io_analog[4] 0.53fF
+C390 divider_0/nor_1/B divider_0/and_0/B 0.31fF
+C391 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C392 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF
+C393 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
+C394 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C395 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C396 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
+C397 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
+C398 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
+C399 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C400 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
+C401 divider_0/tspc_1/Z4 divider_0/tspc_0/Q 0.15fF
+C402 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
+C403 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C404 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
+C405 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF
+C406 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C407 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF
+C408 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF
+C409 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF
+C410 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C411 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C412 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
+C413 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
+C414 divider_0/nor_0/B divider_0/Out 0.22fF
+C415 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF
+C416 gnd divider_0/prescaler_0/Out 0.46fF
Xpd_0 VDD vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd
-Xcp_0 cp_0/vbias vdd vssa1 cp_0/out cp_0/down cp_0/upbar cp
-Xcp_1 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp
-Xfilter_0 vssa1 filter
+Xcp_0 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp
+Xcp_1 cp_1/vbias vdd vssa1 cp_1/out cp_1/down cp_1/upbar cp
Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4
+ ro_complete_0/a3 ro_complete_0/a2 ro_complete
Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider
@@ -1271,50 +1270,48 @@
C1155 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
C1156 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
C1157 ro_complete_0/ro_var_extend_0/vcont vdda1 0.57fF
-C1158 filter_0/a_3976_n5230# vdda1 415.26fF **FLOATING
-C1159 filter_0/a_3976_n2998# vdda1 1.34fF **FLOATING
-C1160 io_analog[1] vdda1 108.63fF
-C1161 io_analog[3] vdda1 197.37fF
-C1162 io_analog[0] vdda1 74.25fF
-C1163 io_analog[2] vdda1 108.15fF
-C1164 cp_1/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1165 cp_1/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1166 cp_1/a_7110_0# vdda1 0.17fF **FLOATING
-C1167 cp_1/a_6370_0# vdda1 0.40fF **FLOATING
-C1168 cp_1/a_3060_0# vdda1 4.15fF **FLOATING
-C1169 cp_1/a_1710_0# vdda1 6.63fF **FLOATING
-C1170 cp_1/a_10_n50# vdda1 2.96fF **FLOATING
-C1171 cp_0/down vdda1 1.54fF
-C1172 cp_0/vbias vdda1 2.41fF
-C1173 cp_0/out vdda1 5.26fF
-C1174 cp_0/upbar vdda1 1.50fF
-C1175 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1176 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1177 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
-C1178 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
-C1179 cp_0/a_3060_0# vdda1 1.65fF **FLOATING
-C1180 cp_0/a_1710_0# vdda1 5.76fF **FLOATING
-C1181 cp_0/a_1710_n2840# vdda1 4.89fF **FLOATING
-C1182 cp_0/a_10_n50# vdda1 2.96fF **FLOATING
-C1183 pd_0/and_pd_0/Z1 vdda1 0.39fF
-C1184 pd_0/and_pd_0/Out1 vdda1 2.22fF
-C1185 pd_0/tspc_r_1/z5 vdda1 1.10fF
-C1186 pd_0/tspc_r_1/Z4 vdda1 1.07fF
-C1187 pd_0/tspc_r_1/Qbar vdda1 0.88fF
-C1188 pd_0/tspc_r_1/Z2 vdda1 1.22fF
-C1189 pd_0/tspc_r_1/Z1 vdda1 0.67fF
-C1190 pd_0/UP vdda1 2.21fF
-C1191 pd_0/tspc_r_1/Qbar1 vdda1 1.34fF
-C1192 pd_0/tspc_r_1/Z3 vdda1 2.12fF
-C1193 pd_0/REF vdda1 1.80fF
-C1194 pd_0/tspc_r_0/z5 vdda1 1.10fF
-C1195 pd_0/tspc_r_0/Z4 vdda1 1.07fF
-C1196 pd_0/R vdda1 3.05fF
-C1197 pd_0/tspc_r_0/Qbar vdda1 0.79fF
-C1198 pd_0/tspc_r_0/Z2 vdda1 1.22fF
-C1199 pd_0/tspc_r_0/Z1 vdda1 0.67fF
-C1200 pd_0/DOWN vdda1 3.08fF
-C1201 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
-C1202 pd_0/tspc_r_0/Z3 vdda1 2.12fF
-C1203 pd_0/DIV vdda1 1.82fF
+C1158 cp_1/down vdda1 1.54fF
+C1159 cp_1/vbias vdda1 2.41fF
+C1160 cp_1/out vdda1 5.26fF
+C1161 cp_1/upbar vdda1 1.50fF
+C1162 cp_1/a_7110_n2840# vdda1 0.17fF **FLOATING
+C1163 cp_1/a_3060_n2840# vdda1 1.71fF **FLOATING
+C1164 cp_1/a_7110_0# vdda1 0.17fF **FLOATING
+C1165 cp_1/a_6370_0# vdda1 0.40fF **FLOATING
+C1166 cp_1/a_3060_0# vdda1 1.65fF **FLOATING
+C1167 cp_1/a_1710_0# vdda1 5.76fF **FLOATING
+C1168 cp_1/a_1710_n2840# vdda1 4.89fF **FLOATING
+C1169 cp_1/a_10_n50# vdda1 2.96fF **FLOATING
+C1170 io_analog[1] vdda1 108.63fF
+C1171 io_analog[3] vdda1 197.37fF
+C1172 io_analog[0] vdda1 74.25fF
+C1173 io_analog[2] vdda1 108.15fF
+C1174 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
+C1175 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
+C1176 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
+C1177 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
+C1178 cp_0/a_3060_0# vdda1 4.15fF **FLOATING
+C1179 cp_0/a_1710_0# vdda1 6.63fF **FLOATING
+C1180 cp_0/a_10_n50# vdda1 2.96fF **FLOATING
+C1181 pd_0/and_pd_0/Z1 vdda1 0.39fF
+C1182 pd_0/and_pd_0/Out1 vdda1 2.22fF
+C1183 pd_0/tspc_r_1/z5 vdda1 1.10fF
+C1184 pd_0/tspc_r_1/Z4 vdda1 1.07fF
+C1185 pd_0/tspc_r_1/Qbar vdda1 0.88fF
+C1186 pd_0/tspc_r_1/Z2 vdda1 1.22fF
+C1187 pd_0/tspc_r_1/Z1 vdda1 0.67fF
+C1188 pd_0/UP vdda1 2.21fF
+C1189 pd_0/tspc_r_1/Qbar1 vdda1 1.34fF
+C1190 pd_0/tspc_r_1/Z3 vdda1 2.12fF
+C1191 pd_0/REF vdda1 1.80fF
+C1192 pd_0/tspc_r_0/z5 vdda1 1.10fF
+C1193 pd_0/tspc_r_0/Z4 vdda1 1.07fF
+C1194 pd_0/R vdda1 3.05fF
+C1195 pd_0/tspc_r_0/Qbar vdda1 0.79fF
+C1196 pd_0/tspc_r_0/Z2 vdda1 1.22fF
+C1197 pd_0/tspc_r_0/Z1 vdda1 0.67fF
+C1198 pd_0/DOWN vdda1 3.08fF
+C1199 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
+C1200 pd_0/tspc_r_0/Z3 vdda1 2.12fF
+C1201 pd_0/DIV vdda1 1.82fF
.ends
