cp and ro
diff --git a/gds/ashish.ext b/gds/ashish.ext
index 84e895c..d52effe 100644
--- a/gds/ashish.ext
+++ b/gds/ashish.ext
@@ -15,17 +15,17 @@
node "vop" 39321 16419.5 7440 -310 m4 0 0 0 0 0 0 0 0 1200000 16800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 858000 46200 0 0 833400 26640 598200 19920 1068600 28040 932400 22680 543400 15040 0 0 0 0
node "von" 39320 16410.5 7430 100 m4 0 0 0 0 0 0 0 0 1200000 16800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 858000 46200 0 0 833400 26640 598200 19920 1063800 28120 825800 20380 510500 14100 0 0 0 0
substrate "w_n2256_n1456#" 0 0 -2256 -1456 pw 11564760 49560 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11614200 51640 0 0 0 0 0 0 0 0 0 0 0 0
-cap "Gnd" "a_150_n710#" 1711.55
-cap "Gnd" "a_150_0#" 1735.6
-cap "Gnd" "vop" 327.431
-cap "Gnd" "von" 327.431
-cap "a_150_n710#" "a_150_0#" 6307.37
-cap "a_150_n710#" "vop" 9143.33
-cap "a_150_n710#" "von" 4332.97
-cap "vop" "a_150_0#" 4443.99
-cap "von" "a_150_0#" 9143.33
cap "von" "vop" 12870.6
-device csubckt sky130_fd_pr__cap_mim_m3_1 -1490 -1090 -1489 -1089 w=1042 l=2000 "None" "a_150_0#" 5696 0 "a_150_n710#" 0 0
+cap "vop" "a_150_n710#" 9143.33
+cap "von" "a_150_n710#" 4332.97
+cap "vop" "Gnd" 327.431
+cap "vop" "a_150_0#" 4443.99
+cap "von" "Gnd" 327.431
+cap "von" "a_150_0#" 9143.33
+cap "Gnd" "a_150_n710#" 1711.55
+cap "a_150_0#" "a_150_n710#" 6307.37
+cap "a_150_0#" "Gnd" 1735.6
+device csubckt sky130_fd_pr__cap_mim_m3_1 -1490 -1090 -1489 -1089 w=1042 l=2000 "None" "a_150_0#" 5696 0 "a_150_n710#" 400 0
device msubckt sky130_fd_pr__nfet_01v8 7020 -710 7021 -709 l=30 w=500 "w_n2256_n1456#" "von" 60 0 "vop" 500 0 "a_150_n710#" 500 0
device msubckt sky130_fd_pr__nfet_01v8 6790 -710 6791 -709 l=30 w=500 "w_n2256_n1456#" "von" 60 0 "a_150_n710#" 500 0 "vop" 500 0
device msubckt sky130_fd_pr__nfet_01v8 6560 -710 6561 -709 l=30 w=500 "w_n2256_n1456#" "von" 60 0 "vop" 500 0 "a_150_n710#" 500 0
diff --git a/gds/cbank.ext b/gds/cbank.ext
index dcc2345..a0e2825 100644
--- a/gds/cbank.ext
+++ b/gds/cbank.ext
@@ -34,18 +34,18 @@
node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd!" 0 0 4950 -1370 li 415872 7104 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
+cap "a_2730_n30#" "a_3680_n30#" 199.5
cap "a_2730_n30#" "li_1720_n30#" 199.5
cap "a_1720_n30#" "li_1720_n30#" 18.13
-cap "a_6660_n30#" "v" 1301.39
-cap "a_2730_n30#" "a_3680_n30#" 199.5
cap "a_5640_n30#" "v" 1301.39
-cap "a_4660_n30#" "v" 1301.39
-cap "v" "li_1720_n30#" 1301.39
-cap "v" "a_3680_n30#" 1301.39
-cap "v" "a_2730_n30#" 1301.39
cap "a_5640_n30#" "a_6660_n30#" 191.52
+cap "a_4660_n30#" "v" 1301.39
+cap "a_3680_n30#" "v" 1301.39
+cap "a_2730_n30#" "v" 1301.39
+cap "v" "li_1720_n30#" 1301.39
+cap "a_6660_n30#" "v" 1301.39
cap "a_4660_n30#" "a_5640_n30#" 199.5
-cap "a_4660_n30#" "a_3680_n30#" 199.5
+cap "a_3680_n30#" "a_4660_n30#" 199.5
device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1856 0 "a_6660_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1856 0 "a_5640_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1856 0 "a_4660_n30#" 1440 0
@@ -57,8 +57,8 @@
cap "a1" "switch_4/vin" -183.5
cap "a0" "switch_5/vout" 4.23077
cap "a0" "switch_5/vin" 83.635
-cap "a2" "switch_3/vin" 83.635
cap "a2" "switch_3/vout" 4.23077
+cap "a2" "switch_3/vin" 83.635
cap "a1" "switch_4/vout" 4.23077
cap "a1" "switch_4/vin" 83.635
cap "a3" "switch_2/vout" 4.23077
diff --git a/gds/divbuf.ext b/gds/divbuf.ext
index feee23e..3fb9950 100644
--- a/gds/divbuf.ext
+++ b/gds/divbuf.ext
@@ -29,27 +29,27 @@
node "a_492_n240#" 5680 1971.5 492 -240 ndif 0 0 0 0 0 0 0 0 8000 360 16000 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98500 6360 0 0 45700 1780 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 14648 361353 370 480 nw 0 0 0 0 65410992 211244 0 0 439400 13520 13732900 416520 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13282200 474060 6457100 321020 2194600 86640 2194600 86640 7414620 232084 0 0 0 0
substrate "GND" 0 0 42310 -560 m4 34146984 359528 0 0 0 0 0 0 6230000 216180 8240400 129360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44214000 575324 6574800 325500 2243600 88560 2372800 90180 11603420 130104 0 0 0 0
+cap "VDD" "OUT5" 83099.7
+cap "OUT3" "OUT4" 5155.49
cap "OUT2" "OUT3" 1365.26
cap "a_492_n240#" "OUT2" 422.539
cap "a_492_n240#" "IN" 129.055
-cap "OUT3" "OUT" 261.644
-cap "OUT2" "OUT" 55.9684
-cap "a_492_n240#" "OUT" 3.77143
cap "VDD" "OUT4" 26017.4
-cap "OUT5" "OUT4" 20262.7
-cap "VDD" "OUT5" 83099.7
-cap "OUT3" "OUT4" 5155.49
-cap "OUT" "OUT4" 1106.9
-cap "OUT3" "VDD" 6618.1
-cap "OUT2" "VDD" 1740.7
+cap "VDD" "OUT3" 6618.1
+cap "VDD" "OUT2" 1740.7
+cap "VDD" "IN" 43.09
+cap "VDD" "a_492_n240#" 485.687
+cap "OUT5" "OUT" 43383.3
+cap "OUT4" "OUT" 1106.9
+cap "OUT3" "OUT" 261.644
+cap "OUT4" "OUT5" 20262.7
+cap "OUT2" "OUT" 55.9684
cap "OUT3" "OUT5" 13.5294
-cap "IN" "VDD" 43.09
cap "OUT2" "OUT5" 19.4824
-cap "a_492_n240#" "VDD" 485.687
+cap "a_492_n240#" "OUT" 3.77143
cap "IN" "OUT5" 0.811765
cap "a_492_n240#" "OUT5" 5.95294
cap "VDD" "OUT" 180323
-cap "OUT" "OUT5" 43383.3
device msubckt sky130_fd_pr__pfet_01v8 61320 -1540 61321 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "OUT" 390 0 "VDD" 390 0
device msubckt sky130_fd_pr__pfet_01v8 61200 -1540 61201 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "VDD" 390 0 "OUT" 390 0
device msubckt sky130_fd_pr__pfet_01v8 61080 -1540 61081 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "OUT" 390 0 "VDD" 390 0
diff --git a/gds/filter.ext b/gds/filter.ext
index 8841c03..c801c2a 100644
--- a/gds/filter.ext
+++ b/gds/filter.ext
@@ -21,13 +21,13 @@
node "a_4216_n2998#" 382 1030.6 4216 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 4660 -21680 li 7113600 89280 0 0 0 0 0 0 0 0 4867200 74880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53899200 149720 172800 2880 172800 2880 263135300 79980 0 0 0 0 0 0
equiv "gnd" "gnd!"
-cap "a_4216_n2998#" "v" 311.161
cap "a_4216_n5230#" "v" 187.252
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -20940 -2459 -20939 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 200 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -20840 4471 -20839 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 200 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -14150 -2459 -14149 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 200 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -13970 4471 -13969 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 200 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 5290 -7130 5291 -7129 w=6000 l=6000 "None" "v" 23616 0 "gnd" 200 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 200 0
+cap "a_4216_n2998#" "v" 311.161
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -20940 -2459 -20939 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -20840 4471 -20839 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -14150 -2459 -14149 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -13970 4471 -13969 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 5290 -7130 5291 -7129 w=6000 l=6000 "None" "v" 23616 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 0 0
device rsubckt sky130_fd_pr__res_xhigh_po 4534 -4798 4535 -4797 l=1800 w=70 "gnd" "a_4534_n4798#" 0 0 "v" 70 0 "a_4216_n2998#" 70 0
device rsubckt sky130_fd_pr__res_xhigh_po 4216 -4798 4217 -4797 l=1800 w=70 "gnd" "a_4216_n4798#" 0 0 "a_4216_n5230#" 70 0 "a_4216_n2998#" 70 0
diff --git a/gds/ro_complete.ext b/gds/ro_complete.ext
index fb9fbd4..5a7009f 100644
--- a/gds/ro_complete.ext
+++ b/gds/ro_complete.ext
@@ -24,71 +24,71 @@
node "li_4080_1390#" 94 5201.91 4080 1390 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40000 1240 19600 560 19600 560 1919760 19328 57600 960 0 0 0 0
node "li_1010_1400#" 88 1456.19 1010 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1200 19600 560 19600 560 19600 560 196600 4100 0 0 0 0
substrate "w_7764_n10666#" 0 0 7764 -10666 pw 1752192 22464 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1096400 18460 1326400 20840 1085200 18160 1085200 18160 4224000 28760 0 0 0 0
-cap "a5" "li_4080_1390#" 77.72
cap "li_7140_1400#" "a5" 100.96
+cap "li_4080_1390#" "a5" 77.72
cap "cbank_1/a0" "cbank_1/switch_5/vout" 46.5385
cap "cbank_1/a2" "cbank_1/switch_3/vout" 46.5385
cap "cbank_1/a1" "cbank_1/switch_4/vout" 46.5385
-cap "cbank_1/a3" "cbank_1/switch_2/vout" 46.5385
+cap "cbank_1/switch_2/vout" "cbank_1/a3" 46.5385
cap "cbank_1/a5" "cbank_1/switch_0/vout" 12.6923
cap "cbank_1/a4" "cbank_1/switch_1/vout" 46.5385
cap "cbank_1/switch_0/vin" "li_7140_1400#" 23.3333
-cap "cbank_1/a5" "cbank_1/switch_0/vout" 33.8462
+cap "cbank_1/switch_0/vout" "cbank_1/a5" 33.8462
cap "cbank_1/v" "cbank_2/gnd!" 86.7059
-cap "cbank_2/switch_4/vin" "a0" 21.2667
cap "cbank_1/v" "cbank_2/gnd!" 275.882
+cap "a0" "cbank_2/switch_4/vin" 21.2667
cap "a0" "cbank_2/gnd!" 180.338
cap "a0" "cbank_1/v" 53.41
-cap "cbank_1/v" "cbank_2/switch_4/vout" 275.882
+cap "a1" "cbank_1/v" 53.41
+cap "cbank_2/switch_4/vout" "cbank_1/v" 275.882
cap "cbank_2/switch_4/vout" "a2" 59.4701
cap "cbank_2/switch_3/vin" "a1" 23.0602
cap "cbank_2/switch_4/vout" "a1" 208.707
-cap "cbank_1/v" "a1" 53.41
-cap "a3" "cbank_1/v" 53.41
-cap "a2" "cbank_1/v" 53.41
-cap "cbank_2/switch_1/vin" "a3" 11.1279
-cap "cbank_2/gnd!" "cbank_1/v" 275.882
-cap "cbank_2/switch_2/vin" "a2" 22.9222
cap "cbank_2/gnd!" "a3" 191.198
cap "cbank_2/gnd!" "a2" 123.77
+cap "cbank_1/v" "a3" 53.41
+cap "cbank_1/v" "a2" 53.41
+cap "a3" "cbank_2/switch_1/vin" 11.1279
+cap "a2" "cbank_2/switch_2/vin" 22.9222
+cap "cbank_2/gnd!" "cbank_1/v" 275.882
+cap "li_7140_1400#" "cbank_2/switch_1/vout" 275.882
+cap "a4" "cbank_2/switch_1/vout" 189.52
cap "a4" "li_7140_1400#" 53.41
-cap "cbank_2/switch_1/vout" "li_7140_1400#" 275.882
+cap "a3" "cbank_2/switch_1/vin" 11.1279
cap "cbank_2/switch_0/vin" "a4" 20.0419
-cap "cbank_2/switch_1/vout" "a4" 189.52
-cap "cbank_2/switch_1/vin" "a3" 11.1279
+cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126
cap "cbank_2/switch_0/vout" "li_7140_1400#" 91.6761
cap "cbank_2/switch_0/vout" "a5" 124.366
-cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126
cap "cbank_2/a0" "cbank_2/switch_4/vin" 107.067
cap "cbank_2/a0" "cbank_2/switch_5/vout" 249.402
-cap "cbank_2/a2" "cbank_2/switch_3/vout" 150.151
-cap "cbank_2/a1" "cbank_2/switch_3/vin" 116.096
-cap "cbank_2/a1" "cbank_2/switch_4/vout" 290.488
+cap "cbank_2/switch_3/vout" "cbank_2/a2" 150.151
+cap "cbank_2/switch_3/vin" "cbank_2/a1" 116.096
+cap "cbank_2/switch_4/vout" "cbank_2/a1" 290.488
cap "cbank_2/a3" "cbank_2/switch_1/vin" 56.0233
cap "cbank_2/a2" "cbank_2/switch_2/vin" 115.401
cap "cbank_2/a2" "cbank_2/switch_3/vout" 103.613
cap "cbank_2/gnd!" "cbank_2/a3" 265.538
cap "cbank_2/switch_1/vin" "a3" 56.0233
-cap "cbank_2/switch_0/vout" "cbank_2/a5" 12.6923
-cap "cbank_2/switch_0/vin" "cbank_2/a4" 100.901
-cap "cbank_2/switch_1/vout" "cbank_2/a4" 263.078
+cap "cbank_2/a5" "cbank_2/switch_0/vout" 12.6923
+cap "cbank_2/a4" "cbank_2/switch_0/vin" 100.901
+cap "cbank_2/a4" "cbank_2/switch_1/vout" 263.078
cap "cbank_2/a5" "cbank_2/switch_0/vout" 143.972
-cap "cbank_0/gnd!" "cbank_2/v" 47.5484
+cap "cbank_2/v" "cbank_0/gnd!" 47.5484
+cap "cbank_0/gnd!" "cbank_2/v" 151.29
cap "cbank_2/a0" "cbank_2/v" 53.41
-cap "cbank_0/gnd!" "cbank_2/v" 151.29
-cap "cbank_0/gnd!" "cbank_2/v" 151.29
+cap "cbank_2/v" "cbank_0/gnd!" 151.29
cap "cbank_2/a1" "cbank_2/v" 53.41
-cap "cbank_2/v" "cbank_2/a2" 53.41
-cap "cbank_2/v" "cbank_2/a3" 53.41
-cap "cbank_2/v" "cbank_2/w_3654_n56#" 151.29
-cap "cbank_0/gnd!" "li_4080_1390#" 151.29
+cap "cbank_2/a3" "cbank_2/v" 53.41
+cap "cbank_2/a2" "cbank_2/v" 53.41
+cap "cbank_2/w_3654_n56#" "cbank_2/v" 151.29
cap "cbank_2/a4" "li_4080_1390#" 53.41
+cap "cbank_0/gnd!" "li_4080_1390#" 151.29
cap "cbank_0/gnd!" "li_4080_1390#" 41.6979
cap "cbank_2/switch_0/vin" "li_4080_1390#" 133.875
cap "cbank_0/gnd!" "cbank_2/v" 47.5484
cap "cbank_0/gnd!" "cbank_2/v" 151.29
-cap "cbank_0/switch_4/vin" "a0" 81.7667
cap "cbank_0/gnd!" "a0" 294.969
+cap "cbank_0/switch_4/vin" "a0" 81.7667
cap "cbank_0/switch_4/vout" "cbank_2/v" 151.29
cap "cbank_0/switch_4/vout" "a2" 118.019
cap "cbank_0/switch_3/vin" "a1" 88.6627
@@ -102,37 +102,37 @@
cap "cbank_0/switch_0/vin" "a4" 77.0576
cap "cbank_0/switch_1/vout" "a4" 311.879
cap "cbank_0/switch_1/vin" "a3" 42.7849
+cap "cbank_0/switch_0/vout" "li_4080_1390#" 438.698
cap "cbank_0/switch_0/vout" "li_7140_1400#" -2.84217e-14
cap "cbank_0/switch_0/vout" "a5" 186.594
-cap "cbank_0/switch_0/vout" "li_4080_1390#" 438.698
-cap "cbank_0/switch_4/vin" "a0" 46.5667
-cap "cbank_0/switch_5/vout" "a0" 134.77
+cap "a0" "cbank_0/switch_4/vin" 46.5667
+cap "a0" "cbank_0/switch_5/vout" 134.77
cap "a2" "cbank_0/switch_3/vout" 91.603
cap "a1" "cbank_0/switch_3/vin" 50.494
cap "a1" "cbank_0/switch_4/vout" 152.64
-cap "a2" "cbank_0/switch_3/vout" 45.0645
cap "a3" "cbank_0/switch_1/vin" 24.3663
cap "a3" "cbank_0/switch_2/vout" 141.788
cap "a2" "cbank_0/switch_2/vin" 50.1916
-cap "a4" "cbank_0/switch_0/vin" 43.8848
-cap "a4" "cbank_0/switch_1/vout" 140.718
+cap "a2" "cbank_0/switch_3/vout" 45.0645
cap "cbank_0/switch_1/vin" "a3" 24.3663
cap "cbank_0/a5" "cbank_0/switch_0/vout" 12.6923
+cap "a4" "cbank_0/switch_0/vin" 43.8848
+cap "a4" "cbank_0/switch_1/vout" 140.718
cap "a5" "cbank_0/switch_0/vout" 81.7433
-cap "cbank_0/v" "ro_var_extend_0/gnd" 151.9
+cap "ro_var_extend_0/gnd" "cbank_0/v" 151.9
cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97
-cap "ro_var_extend_0/gnd" "li_4080_1390#" 645.27
+cap "li_4080_1390#" "ro_var_extend_0/gnd" 645.27
+cap "li_7140_1400#" "ro_var_extend_0/gnd" 292.345
cap "ro_var_extend_0/gnd" "li_4080_1390#" 291.625
-cap "ro_var_extend_0/gnd" "li_7140_1400#" 292.345
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 129.703
-cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
-cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
+cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
+cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
-cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
+cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 215.6
cap "ro_var_extend_0/gnd" "ro_var_extend_0/vcont" 3.86897
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 477.307
diff --git a/gds/ro_var_extend.ext b/gds/ro_var_extend.ext
index 1e4fe08..bdacb6e 100644
--- a/gds/ro_var_extend.ext
+++ b/gds/ro_var_extend.ext
@@ -22,10 +22,10 @@
node "vdd" 21463 18367.8 6020 900 li 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 5980 -160 li 2627212 34004 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
cap "out1" "out2" 40.8506
-cap "out2" "out3" 1263.05
-cap "out1" "out3" 1156.32
cap "w_n120_n750#" "vcont" 140.194
+cap "out3" "out2" 1263.05
cap "w_n120_n750#" "out2" 789.263
+cap "out3" "out1" 1156.32
cap "w_n120_n750#" "out1" 569.035
cap "w_n120_n750#" "out3" 215.464
cap "vdd" "out2" 235.622
diff --git a/gds/user_analog_project_wrapper.ext b/gds/user_analog_project_wrapper.ext
index 271608b..ef5c7ae 100644
--- a/gds/user_analog_project_wrapper.ext
+++ b/gds/user_analog_project_wrapper.ext
@@ -4,17 +4,11 @@
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use filter filter_0 1 0 57226 0 1 133758
-use divbuf divbuf_4 1 0 45140 0 1 213270
-use ro_complete ro_complete_0 1 0 31950 0 1 214900
-use pll_full pll_full_0 1 0 383720 0 1 542022
-use pd pd_0 1 0 23666 0 1 654896
-use divbuf divbuf_3 1 0 19884 0 1 665726
-use divbuf divbuf_2 1 0 19702 0 1 661018
-use divbuf divbuf_1 1 0 33336 0 1 653584
-use divbuf divbuf_0 1 0 33492 0 1 649208
-use ashish ashish_0 1 0 134960 0 1 695750
use cp cp_0 1 0 556210 0 1 661320
+use ashish ashish_0 1 0 134960 0 1 695750
+use ro_complete ro_complete_0 1 0 31950 0 1 214900
+use divbuf divbuf_0 1 0 45140 0 1 213270
+use filter filter_0 1 0 57226 0 1 133758
port "io_analog[4]" 42 329294 702300 334294 704800 m5
port "io_analog[4]" 42 318994 702300 323994 704800 m5
port "io_analog[5]" 43 227594 702300 232594 704800 m5
@@ -710,8 +704,6 @@
node "io_analog[5]" 0 2925 227594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
node "io_analog[6]" 0 2925 175894 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
node "m4_28900_141410#" 0 522112 28900 141410 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1293044300 1426300 0 0 0 0
-node "m4_374062_561532#" 1 1450.42 374062 561532 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 510708 7288 0 0 0 0
-node "m4_33166_649670#" 1 989.123 33166 649670 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 431616 4880 0 0 0 0
node "m4_115800_678290#" 0 74285.9 115800 678290 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 185113800 208280 0 0 0 0
node "io_analog[4]" 0 2775 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
node "io_analog[4]" 0 6748.8 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33255036 36480 0 0 0 0
@@ -858,7 +850,7 @@
node "io_out[12]" 1 613.728 583520 498868 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_oeb[12]" 1 613.728 583520 500050 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "vdda1" 0 6519 582340 540562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "vdda1" 0 1.52605e+06 582340 550562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38767100 31180 3774432368 4149300 0 0 0 0
+node "vdda1" 0 1.36295e+06 582340 550562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38767100 31180 3404867360 3673880 0 0 0 0
node "io_oeb[14]" 1 613.728 -800 505620 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_out[14]" 1 613.728 -800 506802 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in[14]" 1 613.728 -800 507984 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
@@ -878,9 +870,9 @@
node "vccd2" 0 6519 0 633842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vccd2" 0 6519 0 643842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "io_analog[10]" 0 9599.96 0 680242 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18838880 19260 0 0 0 0 0 0
-node "vssa1" 0 1.60767e+06 520594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111414492 212628 9904824 51484 4648652020 4347256 0 0
+node "vssa1" 1 1.40984e+06 520594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 93252996 143272 6153300 16820 4103788788 3879532 0 0
node "vssa1" 0 6519 510594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "io_analog[3]" 0 6863.94 413394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12588800 15060 0 0 0 0 0 0
+node "io_analog[3]" 0 56384.6 413394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104349800 122340 0 0 0 0 0 0
node "io_analog[4]" 0 6825 329294 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0 0 0
node "io_clamp_high[0]" 0 3577 326794 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5500000 9400 0 0 0 0 0 0
node "io_clamp_low[0]" 0 3577 324294 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5500000 9400 0 0 0 0 0 0
@@ -894,7 +886,7 @@
node "io_analog[6]" 0 13587.8 165594 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27075000 26660 0 0 0 0 0 0
node "io_analog[7]" 0 19886.5 120194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20826000 24200 10481900 52740 0 0 0 0
node "io_analog[8]" 0 6825 68194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0 0 0
-node "io_analog[9]" 0 25109.4 16194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44116712 57924 0 0 0 0 0 0
+node "io_analog[9]" 0 18049.3 16194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32527472 40444 0 0 0 0 0 0
node "user_irq[2]" 1 631.648 583250 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "user_irq[1]" 1 631.648 582068 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "user_irq[0]" 1 631.648 580886 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
@@ -1389,7 +1381,7 @@
node "wbs_ack_o" 1 631.648 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_rst_i" 1 631.648 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_clk_i" 1 631.648 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
-node "gpio_analog[7]" 1 92325.9 -800 511530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 101344120 236144 692248 5328 0 0 0 0 0 0
+node "gpio_analog[7]" 1 3924.79 -800 511530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2862724 9088 692248 5328 0 0 0 0 0 0
node "m2_560230_657890#" 0 373.1 560230 657890 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0
node "m1_560230_657890#" 0 373.1 560230 657890 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0
node "io_analog[0]" 2 38830.7 582300 677984 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1399200 8000 34491080 72944 15367748 18360 0 0 0 0 0 0
@@ -1403,99 +1395,86 @@
node "gpio_analog[12]" 716 98099.1 -800 295420 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1095100 16300 623200 3160 623200 3160 137147620 248060 0 0 0 0 0 0
node "vdda1" 15 593735 582340 225230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22400 600 429100 3760 65000 1020 1201464100 1132580 0 0 0 0 0 0
node "gpio_analog[13]" 1752 65155.7 -800 252398 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1736100 31800 623200 3160 623200 3160 89466360 131860 0 0 0 0 0 0
-node "li_32886_649070#" 19 8112.57 32886 649070 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69048 1052 3807848 25996 0 0 0 0 0 0 0 0 0 0
-node "li_32770_653524#" 18 4768.08 32770 653524 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44100 840 1514148 17272 0 0 0 0 0 0 0 0 0 0
node "io_analog[1]" 83 69573.1 566594 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 497300 4200 5607252 15716 66140716 123668 20262080 20024 0 0 0 0 0 0
node "li_560230_657890#" 12 691.975 560230 657890 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19160_659970#" 23 13020.1 19160 659970 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43788 856 482848 3292 10770156 36192 0 0 0 0 0 0 0 0
node "li_555470_660400#" 220 1823.62 555470 660400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 363696 5408 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19158_660978#" 17 33431.1 19158 660978 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52000 920 341300 2980 33575248 88620 0 0 0 0 0 0 0 0
-node "li_17838_664356#" 13 750.816 17838 664356 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 234936 1940 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19434_665672#" 148 533397 19434 665672 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 168364 3032 973960 10980 1089008 10716 326745336 531348 510727440 761616 414757328 548908 0 0
-node "li_17806_665450#" 13 750.816 17806 665450 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 234936 1940 0 0 0 0 0 0 0 0 0 0 0 0
node "io_analog[2]" 39 130432 465394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 531500 3408 422500 2600 155574764 265284 18083524 18844 0 0 0 0 0 0
node "li_133706_697044#" 14 433.006 133706 697044 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 97088 1248 0 0 0 0 0 0 0 0 0 0 0 0
node "w_559500_660830#" 2061 2427.03 559500 660830 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
node "w_559560_661800#" 17515 3366 559560 661800 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "w_560204_657864#" 0 0 560204 657864 pw 257024 2028 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m2_560230_657890#" "vssa1" 26.4
+cap "io_analog[5]" "vssa1" 23110.9
+cap "io_clamp_high[2]" "io_analog[6]" 525
cap "vssa1" "m4_115800_678290#" 6516.2
cap "io_clamp_low[2]" "io_clamp_high[2]" 525
+cap "vdda1" "vssa1" 3126.6
+cap "gpio_analog[14]" "gpio_analog[15]" 678.9
cap "io_analog[6]" "io_clamp_low[2]" 525
-cap "li_32770_653524#" "li_32886_649070#" 1704.54
cap "m3_31530_200540#" "vssd1" 336
-cap "w_559560_661800#" "w_559500_660830#" 224.4
+cap "li_15258_203018#" "gpio_analog[15]" 919.8
+cap "li_560230_657890#" "vssa1" 13.2
cap "vssa1" "vssd1" 598.6
cap "io_analog[4]" "io_analog[4]" 26250
-cap "vssa1" "vdda1" 55830.1
-cap "io_analog[5]" "m4_115800_678290#" 1008.9
-cap "gpio_noesd[15]" "gpio_analog[17]" 5801.25
-cap "gpio_analog[14]" "vssd1" 248
-cap "io_analog[4]" "io_analog[4]" 69835.6
-cap "gpio_analog[14]" "gpio_analog[17]" 508.4
-cap "li_19434_665672#" "li_32886_649070#" 1075.27
-cap "io_analog[5]" "io_analog[5]" 26250
-cap "li_19434_665672#" "li_32770_653524#" 247.927
-cap "li_27474_203846#" "gpio_analog[17]" 688.8
-cap "io_analog[5]" "vdda1" 45782.9
+cap "vssa1" "vdda1" 52732.6
cap "io_analog[2]" "vssa1" 1182.97
-cap "gpio_noesd[15]" "gpio_analog[16]" 9283.52
-cap "io_analog[6]" "io_analog[6]" 26250
-cap "li_19434_665672#" "li_19160_659970#" 21092.8
-cap "gpio_analog[14]" "gpio_analog[16]" 570.4
-cap "vdda1" "vdda1" 11170.4
-cap "li_19434_665672#" "li_19158_660978#" 9909.14
-cap "li_22752_203148#" "gpio_analog[16]" 772.8
-cap "io_analog[4]" "io_analog[4]" 21250
-cap "li_19434_665672#" "li_17838_664356#" 1028.87
-cap "io_analog[6]" "io_analog[6]" 57285.3
-cap "io_analog[4]" "io_analog[4]" 56533.6
-cap "io_analog[7]" "io_analog[6]" 454.755
-cap "m3_60440_111096#" "m4_28900_141410#" 18845.9
-cap "m2_560230_657890#" "m3_560230_657890#" 445.05
-cap "io_analog[5]" "io_analog[5]" 21250
-cap "vssa1" "m3_560230_657890#" 480.9
-cap "gpio_noesd[15]" "gpio_analog[15]" 11274.7
-cap "gpio_analog[14]" "gpio_analog[15]" 678.9
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "li_15258_203018#" "gpio_analog[15]" 919.8
-cap "vssd1" "m4_28900_141410#" 1117.2
-cap "m2_560230_657890#" "vssa1" 26.4
-cap "m1_560230_657890#" "m2_560230_657890#" 693.45
-cap "m1_560230_657890#" "vssa1" 19.8
-cap "vssd1" "m3_60440_111096#" 598.6
+cap "io_analog[3]" "vdda1" 8331.27
+cap "io_analog[5]" "io_clamp_low[1]" 525
cap "gpio_analog[14]" "m3_31530_200540#" 283.6
-cap "gpio_analog[17]" "m3_60440_111096#" 4031.6
+cap "io_analog[4]" "io_analog[4]" 69835.6
cap "li_15258_203018#" "m3_31530_200540#" 280.2
-cap "li_22752_203148#" "m3_31530_200540#" 280.2
-cap "li_27474_203846#" "m3_31530_200540#" 235.7
-cap "li_17806_665450#" "li_19434_665672#" 1017.32
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "li_27474_203846#" "li_22752_203148#" 485.58
+cap "m1_560230_657890#" "m2_560230_657890#" 693.45
+cap "io_analog[6]" "io_analog[6]" 57285.3
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "li_44580_213200#" "io_analog[5]" 342.875
+cap "io_analog[7]" "io_analog[6]" 454.755
+cap "io_analog[5]" "m4_115800_678290#" 1008.9
+cap "io_analog[4]" "io_analog[4]" 56533.6
+cap "vssa1" "m3_560230_657890#" 480.9
+cap "vdda1" "io_analog[5]" 10678
+cap "io_analog[0]" "io_analog[1]" 5625.78
+cap "m1_560230_657890#" "li_560230_657890#" 589.95
+cap "m3_60440_111096#" "m4_28900_141410#" 18845.9
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "gpio_analog[13]" "gpio_analog[12]" 1228.81
+cap "li_27474_203846#" "gpio_analog[17]" 688.8
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "gpio_noesd[15]" "gpio_analog[17]" 5801.25
+cap "io_analog[5]" "vdda1" 45782.9
+cap "vssd1" "m4_28900_141410#" 1117.2
+cap "vssd1" "m3_60440_111096#" 598.6
+cap "gpio_analog[14]" "li_22752_203148#" 627.84
+cap "gpio_analog[17]" "m3_60440_111096#" 4031.6
+cap "gpio_analog[14]" "li_27474_203846#" 561.64
+cap "li_15258_203018#" "li_22752_203148#" 534.48
+cap "vdda1" "vdda1" 11170.4
+cap "li_15258_203018#" "li_27474_203846#" 485.58
+cap "li_22752_203148#" "gpio_analog[16]" 772.8
+cap "gpio_noesd[15]" "gpio_analog[16]" 9283.52
cap "vdda1" "vssd1" 1117.2
cap "io_clamp_high[0]" "io_analog[4]" 525
-cap "io_analog[5]" "vssa1" 23110.9
-cap "li_15258_203018#" "gpio_analog[14]" 3134.17
-cap "li_22752_203148#" "gpio_analog[14]" 627.84
+cap "io_analog[2]" "vdda1" 2018.08
cap "gpio_analog[16]" "m3_60440_111096#" 4425.6
cap "io_clamp_low[0]" "io_clamp_high[0]" 525
-cap "li_27474_203846#" "gpio_analog[14]" 561.64
-cap "li_22752_203148#" "li_15258_203018#" 534.48
-cap "vdda1" "vssa1" 3126.6
-cap "li_27474_203846#" "li_15258_203018#" 485.58
-cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "li_27474_203846#" "li_22752_203148#" 485.58
-cap "io_analog[7]" "vssa1" 6884.47
-cap "io_analog[2]" "vdda1" 2018.08
-cap "io_clamp_high[1]" "io_analog[5]" 525
-cap "li_560230_657890#" "vssa1" 13.2
-cap "li_44580_213200#" "io_analog[5]" 342.875
-cap "io_analog[1]" "io_analog[0]" 5625.78
-cap "li_560230_657890#" "m1_560230_657890#" 589.95
+cap "gpio_analog[14]" "vssd1" 248
cap "w_559500_660830#" "vdda1" 11.8235
-cap "io_analog[5]" "io_clamp_low[1]" 525
+cap "gpio_analog[14]" "gpio_analog[17]" 508.4
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "gpio_noesd[15]" "gpio_analog[15]" 11274.7
+cap "io_analog[7]" "vssa1" 6884.47
+cap "w_559560_661800#" "w_559500_660830#" 224.4
+cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "li_15258_203018#" "gpio_analog[14]" 3134.17
+cap "m2_560230_657890#" "m3_560230_657890#" 445.05
cap "gpio_analog[15]" "m3_60440_111096#" 5372.79
cap "io_clamp_low[1]" "io_clamp_high[1]" 525
-cap "vdda1" "io_analog[5]" 10678
-cap "gpio_analog[13]" "gpio_analog[12]" 1228.81
-cap "io_clamp_high[2]" "io_analog[6]" 525
+cap "gpio_analog[14]" "gpio_analog[16]" 570.4
+cap "li_22752_203148#" "m3_31530_200540#" 280.2
+cap "m1_560230_657890#" "vssa1" 19.8
+cap "li_27474_203846#" "m3_31530_200540#" 235.7
cap "filter_0/a_4216_n2998#" "filter_0/v" 60.1993
cap "filter_0/gnd" "gpio_noesd[15]" 186.856
cap "filter_0/gnd" "gpio_noesd[15]" 383.726
@@ -1504,156 +1483,55 @@
cap "ro_complete_0/cbank_1/gnd!" "li_22752_203148#" 77.2083
cap "ro_complete_0/cbank_1/gnd!" "li_27474_203846#" 299.327
cap "ro_complete_0/cbank_1/switch_0/vin" "li_15258_203018#" 19.8431
-cap "ro_complete_0/cbank_1/gnd!" "li_15258_203018#" 230.111
cap "ro_complete_0/cbank_1/switch_1/vin" "li_22752_203148#" 38.4304
+cap "ro_complete_0/cbank_1/gnd!" "li_15258_203018#" 230.111
cap "ro_complete_0/cbank_1/gnd!" "li_22752_203148#" 156.208
cap "ro_complete_0/cbank_1/switch_0/vout" "gpio_analog[14]" 212.707
cap "ro_complete_0/cbank_1/switch_0/vin" "li_15258_203018#" 19.8431
+cap "ro_complete_0/cbank_1/a2" "ro_complete_0/cbank_1/switch_3/vout" 270.286
cap "ro_complete_0/cbank_1/a2" "ro_complete_0/cbank_1/switch_3/vin" 90.5745
cap "ro_complete_0/cbank_1/a3" "ro_complete_0/cbank_1/switch_2/vout" 97.8621
cap "ro_complete_0/cbank_1/a2" "ro_complete_0/cbank_1/switch_2/vin" 89.6211
-cap "ro_complete_0/cbank_1/a2" "ro_complete_0/cbank_1/switch_3/vout" 270.286
-cap "ro_complete_0/cbank_1/a4" "ro_complete_0/cbank_1/switch_0/vin" 55.6471
-cap "ro_complete_0/cbank_1/a4" "ro_complete_0/cbank_1/switch_1/vout" 175.546
cap "ro_complete_0/cbank_1/a3" "ro_complete_0/cbank_1/switch_1/vin" 107.772
cap "ro_complete_0/cbank_1/a3" "ro_complete_0/cbank_1/switch_2/vout" 97.8621
+cap "ro_complete_0/cbank_1/switch_0/vin" "ro_complete_0/cbank_1/a4" 55.6471
+cap "ro_complete_0/cbank_1/switch_1/vout" "ro_complete_0/cbank_1/a4" 175.546
cap "ro_complete_0/cbank_1/switch_0/vin" "li_15258_203018#" 55.6471
cap "ro_complete_0/cbank_1/a5" "ro_complete_0/cbank_1/switch_0/vout" 158.853
cap "gpio_analog[12]" "ro_complete_0/cbank_0/gnd!" 8.02703
-cap "gpio_analog[13]" "ro_complete_0/a0" 5.95361
-cap "ro_complete_0/cbank_0/switch_5/vout" "ro_complete_0/a0" 8.6194
-cap "ro_complete_0/cbank_0/switch_5/vin" "ro_complete_0/a0" 8.6194
-cap "ro_complete_0/li_7140_1400#" "ro_complete_0/w_7764_n10666#" 298.145
-cap "divbuf_4/VDD" "divbuf_4/OUT" 17.3563
-cap "divbuf_4/OUT" "divbuf_4/GND" 387.393
-cap "divbuf_4/IN" "divbuf_4/GND" 335.041
-cap "gpio_analog[12]" "ro_complete_0/cbank_0/v" 94.5
-cap "gpio_analog[12]" "gpio_analog[12]" 126.556
-cap "gpio_analog[12]" "ro_complete_0/cbank_0/v" -2.27374e-13
-cap "gpio_analog[12]" "ro_complete_0/cbank_0/gnd!" 8.02703
-cap "ro_complete_0/cbank_0/v" "gpio_analog[13]" 94.5
-cap "gpio_analog[12]" "gpio_analog[13]" 144.6
-cap "ro_complete_0/cbank_0/switch_5/vin" "gpio_analog[13]" 152.4
cap "ro_complete_0/a0" "gpio_analog[13]" 5.95361
cap "ro_complete_0/a0" "ro_complete_0/cbank_0/switch_5/vout" 8.6194
-cap "ro_complete_0/a0" "ro_complete_0/cbank_0/switch_5/vin" 0.298403
+cap "ro_complete_0/a0" "ro_complete_0/cbank_0/switch_5/vin" 8.6194
+cap "ro_complete_0/w_7764_n10666#" "ro_complete_0/li_7140_1400#" 298.145
+cap "divbuf_0/VDD" "divbuf_0/OUT" 17.3563
+cap "divbuf_0/GND" "divbuf_0/OUT" 387.393
+cap "divbuf_0/GND" "divbuf_0/IN" 335.041
+cap "gpio_analog[12]" "ro_complete_0/cbank_0/v" -2.27374e-13
+cap "gpio_analog[12]" "ro_complete_0/cbank_0/v" 94.5
+cap "gpio_analog[12]" "gpio_analog[12]" 126.556
+cap "gpio_analog[13]" "ro_complete_0/cbank_0/v" 94.5
+cap "gpio_analog[13]" "gpio_analog[12]" 144.6
+cap "gpio_analog[12]" "ro_complete_0/cbank_0/gnd!" 8.02703
cap "gpio_analog[13]" "ro_complete_0/cbank_0/v" 72.2
cap "gpio_analog[13]" "ro_complete_0/cbank_0/v" -74.55
cap "ro_complete_0/cbank_0/switch_5/vin" "ro_complete_0/cbank_0/v" -457.14
cap "ro_complete_0/a0" "ro_complete_0/cbank_0/v" -74.55
-cap "ro_complete_0/a1" "ro_complete_0/cbank_0/switch_4/vin" 177.588
+cap "ro_complete_0/cbank_0/switch_5/vin" "gpio_analog[13]" 152.4
+cap "ro_complete_0/a0" "gpio_analog[13]" 5.95361
+cap "ro_complete_0/a0" "ro_complete_0/cbank_0/switch_5/vout" 8.6194
+cap "ro_complete_0/a0" "ro_complete_0/cbank_0/switch_5/vin" 0.298403
cap "ro_complete_0/cbank_0/switch_4/vin" "ro_complete_0/cbank_0/a_3680_n30#" 0.975664
cap "ro_complete_0/a1" "ro_complete_0/cbank_0/v" 72.2
+cap "ro_complete_0/a1" "ro_complete_0/cbank_0/switch_4/vin" 177.588
cap "ro_complete_0/w_7764_n10666#" "ro_complete_0/li_7140_1400#" 230.888
-cap "vdda1" "ro_complete_0/ro_var_extend_0/gnd" 260.125
-cap "vdda1" "ro_complete_0/ro_var_extend_0/vdd" 2.84217e-14
+cap "ro_complete_0/ro_var_extend_0/vdd" "vdda1" 2.84217e-14
+cap "ro_complete_0/ro_var_extend_0/gnd" "vdda1" 260.125
cap "ro_complete_0/ro_var_extend_0/gnd" "vdda1" 312.18
-cap "pll_full_0/divbuf_0/GND" "vdda1" 50.938
-cap "pll_full_0/divbuf_0/VDD" "pll_full_0/divbuf_0/IN" 74.1
-cap "pll_full_0/divbuf_0/GND" "pll_full_0/divbuf_0/VDD" 1.086
-cap "pll_full_0/divbuf_0/VDD" "pll_full_0/divbuf_0/OUT" 96.22
-cap "pll_full_0/li_n10340_n3220#" "vssa1" 411.85
-cap "pll_full_0/li_n10470_n4240#" "vssa1" 495.75
-cap "vssa1" "pll_full_0/filter_0/gnd" 177.576
-cap "vssa1" "pll_full_0/filter_0/gnd" 374.37
-cap "vssa1" "pll_full_0/filter_0/gnd" 179.56
-cap "vssa1" "pll_full_0/filter_0/gnd" 225.4
-cap "vssa1" "pll_full_0/filter_0/gnd" 321.45
-cap "pll_full_0/li_n10340_n3220#" "vssa1" 34.656
-cap "pll_full_0/li_n10470_n4240#" "vssa1" 50.72
-cap "pll_full_0/filter_0/gnd" "vssa1" 156.648
-cap "pll_full_0/filter_0/gnd" "vssa1" 327.33
-cap "pll_full_0/filter_0/gnd" "vssa1" 151.83
-cap "pll_full_0/filter_0/gnd" "vssa1" -44.39
-cap "pll_full_0/divider_0/w_n966_n46#" "vdda1" 34.12
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/m2_n10320_4830#" 109.6
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/li_n10470_n4240#" 148.6
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/divider_0/prescaler_0/tspc_0/Q" 77.975
-cap "pll_full_0/divider_0/w_n966_n46#" "pll_full_0/divider_0/w_n140_1520#" -653.86
-cap "pll_full_0/divider_0/mc2" "pll_full_0/m2_n10320_4830#" 269.9
-cap "pll_full_0/divider_0/mc2" "pll_full_0/li_n10470_n4240#" 87.58
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "pll_full_0/divider_0/mc2" 10.4145
-cap "pll_full_0/pd_0/w_n446_n1456#" "pll_full_0/divider_0/prescaler_0/GND" 229.752
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_0/VDD" 0.867876
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_0/VDD" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_0/VDD" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_0/VDD" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/m2_n10320_4830#" 220.66
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "vssa1" 9.54663
-cap "pll_full_0/m2_n10320_4830#" "vssa1" 130.96
-cap "pll_full_0/m2_n10320_4830#" "vssa1" -20.79
-cap "vssa1" "pll_full_0/pd_0/VDD" 10.4145
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "vssa1" 0.867876
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/tspc_r_0/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/w_0_n1460#" "pll_full_0/pd_0/and_pd_0/GND" 9.54663
-cap "pll_full_0/pd_0/w_n446_n1456#" "pll_full_0/pd_0/and_pd_0/GND" 31.1864
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/REF" 14.96
-cap "pll_full_0/pd_0/w_n446_n1456#" "pll_full_0/pd_0/VDD" 39.696
-cap "pll_full_0/pd_0/and_pd_0/w_n86_n496#" "pll_full_0/pd_0/and_pd_0/GND" 106.318
-cap "pll_full_0/pd_0/w_n446_n1456#" "pll_full_0/pd_0/VDD" 89.248
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/VDD" 1.77636e-15
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/REF" 45.28
-cap "pll_full_0/cp_0/vdd!" "pll_full_0/li_n9940_24670#" 45.7
-cap "pll_full_0/cp_0/vdd!" "pll_full_0/li_n9940_24670#" 350
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/li_n9940_24670#" 350
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 128.714
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/divbuf_1/VDD" 2.92
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 12.4096
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/li_n9940_24670#" 37.41
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 106.269
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 59.4592
-cap "divbuf_0/GND" "li_19434_665672#" 241.484
-cap "divbuf_0/GND" "divbuf_0/OUT" -719.384
-cap "divbuf_0/OUT" "divbuf_0/VDD" 13.2711
-cap "divbuf_0/GND" "divbuf_0/OUT" 12.0622
-cap "divbuf_0/GND" "li_32886_649070#" 437.146
-cap "divbuf_0/GND" "divbuf_0/VDD" 195.428
-cap "divbuf_0/GND" "divbuf_0/IN" -612.03
-cap "divbuf_1/VDD" "divbuf_1/GND" 94.7136
-cap "divbuf_1/GND" "li_32886_649070#" -83.325
-cap "divbuf_1/GND" "divbuf_1/OUT" 451.039
-cap "divbuf_1/OUT" "divbuf_1/GND" 43.7618
-cap "divbuf_1/OUT" "divbuf_1/VDD" 14.4404
-cap "divbuf_1/VDD" "divbuf_1/VDD" 2.84
-cap "divbuf_1/VDD" "divbuf_1/GND" 52.6144
-cap "pd_0/w_n446_n1456#" "pd_0/DIV" 161.782
-cap "divbuf_1/GND" "li_32770_653524#" -48.3526
-cap "divbuf_1/GND" "li_32886_649070#" 34.2391
-cap "divbuf_1/GND" "li_19434_665672#" 3.47965
-cap "divbuf_1/GND" "divbuf_1/IN" 0.372138
-cap "divbuf_1/GND" "divbuf_1/VDD" 93.2072
-cap "divbuf_1/GND" "li_19434_665672#" 19.7791
-cap "pd_0/w_n446_n1456#" "pd_0/REF" 177.334
-cap "pd_0/R" "pd_0/DOWN" 19.5152
-cap "pd_0/UP" "pd_0/DOWN" -4.1413
-cap "pd_0/and_pd_0/w_n86_n496#" "pd_0/DOWN" 239.102
-cap "pd_0/and_pd_0/w_n86_n496#" "pd_0/and_pd_0/GND" 140.1
-cap "pd_0/UP" "pd_0/R" 5.68421
-cap "pd_0/VDD" "pd_0/UP" 7.87692
-cap "pd_0/and_pd_0/w_n86_n496#" "pd_0/UP" 221.854
-cap "divbuf_1/GND" "li_32770_653524#" -113.201
-cap "divbuf_1/GND" "li_32770_653524#" 56.4574
-cap "divbuf_1/GND" "divbuf_1/VDD" 141.229
-cap "pd_0/w_n446_n1456#" "pd_0/tspc_r_1/D" 163.508
-cap "pd_0/VDD" "pd_0/tspc_r_1/D" 3.216
-cap "pd_0/VDD" "pd_0/UP" 7.87692
cap "cp_0/gnd!" "cp_0/gnd!" 6.1875
cap "cp_0/down" "cp_0/gnd!" 116.74
cap "cp_0/w_6344_n2866#" "cp_0/down" 333.565
cap "cp_0/gnd!" "io_analog[1]" -98.8142
-cap "divbuf_2/GND" "li_19434_665672#" -52.89
-cap "divbuf_2/GND" "li_19160_659970#" -140.225
-cap "divbuf_2/OUT" "divbuf_2/VDD" 15
-cap "divbuf_2/GND" "li_19434_665672#" -29.785
-cap "divbuf_2/GND" "divbuf_2/OUT" -134.129
cap "cp_0/gnd!" "cp_0/gnd!" 1.98
-cap "divbuf_2/GND" "li_19160_659970#" -118.427
-cap "divbuf_2/GND" "li_19158_660978#" -140.976
-cap "divbuf_2/GND" "divbuf_2/OUT" 19.5108
-cap "divbuf_2/GND" "divbuf_2/IN" 37.7383
-cap "divbuf_2/GND" "divbuf_2/OUT" 118.833
cap "cp_0/vbias" "cp_0/vdd!" 70.1
cap "cp_0/vbias" "cp_0/gnd!" 70.4
cap "cp_0/vdd!" "cp_0/vdd!" -8.2
@@ -1662,85 +1540,42 @@
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 8.33333
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 7.5
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 5.5
+cap "w_559560_661800#" "cp_0/a_1710_0#" 37.5
cap "w_559560_661800#" "cp_0/a_3060_0#" 14.96
cap "w_559560_661800#" "cp_0/a_3060_0#" 37.2505
-cap "w_559560_661800#" "cp_0/a_1710_0#" 37.5
-cap "divbuf_2/GND" "divbuf_2/VDD" 203.264
cap "cp_0/vdd!" "cp_0/vdd!" 95.0847
cap "w_559560_661800#" "cp_0/a_3060_0#" 988.637
cap "cp_0/a_3060_0#" "w_559500_660830#" 1004.68
cap "w_559560_661800#" "w_559500_660830#" -34.44
-cap "divbuf_3/GND" "divbuf_3/OUT" 322.322
-cap "divbuf_3/GND" "divbuf_3/IN" 10.8621
cap "cp_0/a_3060_0#" "vdda1" 134.64
cap "cp_0/a_3060_0#" "vdda1" 325.8
cap "w_559560_661800#" "vdda1" -24.96
-cap "divbuf_3/GND" "divbuf_3/IN" 427.206
-cap "divbuf_3/GND" "divbuf_3/VDD" -52.192
-cap "divbuf_3/GND" "divbuf_3/VDD" -59.03
-cap "ashish_0/a_150_n710#" "vssa1" 445.586
cap "ashish_0/a_150_0#" "vssa1" 334.233
+cap "ashish_0/a_150_n710#" "vssa1" 445.586
cap "ashish_0/a_150_0#" "ashish_0/Gnd" 19.1739
-cap "ashish_0/von" "ashish_0/vop" -18.2655
cap "ashish_0/w_124_n736#" "ashish_0/vop" 286.85
cap "ashish_0/w_124_n736#" "ashish_0/von" 238.75
+cap "ashish_0/von" "ashish_0/vop" -18.2655
cap "vssa1" "ashish_0/a_150_n710#" 141.75
cap "ashish_0/w_n2256_n1456#" "vssa1" 273.3
-merge "cp_0/a_1710_n2840#" "cp_0/vbias" -34287.2 0 0 0 0 -1481520 -6252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -48637 -3264 30033 -2902 0 0 -47232000 -58080 -1013960 -14688 0 0 0 0
+merge "cp_0/a_1710_n2840#" "ro_complete_0/ro_var_extend_0/vdd" -17832.2 0 0 0 0 -5072600 -20364 0 0 86250 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10704 -2632 127380 -1040 132420 -1040 217000 -1660 -132960 -14866 0 0 0 0
+merge "ro_complete_0/ro_var_extend_0/vdd" "vdda1"
+merge "vdda1" "cp_0/vbias"
merge "cp_0/vbias" "li_555470_660400#"
merge "li_555470_660400#" "cp_0/vdd!"
merge "cp_0/vdd!" "w_559500_660830#"
merge "w_559500_660830#" "w_559560_661800#"
-merge "w_559560_661800#" "pll_full_0/divbuf_1/VDD"
-merge "pll_full_0/divbuf_1/VDD" "pll_full_0/cp_0/vdd!"
-merge "pll_full_0/cp_0/vdd!" "m4_374062_561532#"
-merge "m4_374062_561532#" "pll_full_0/pd_0/VDD"
-merge "pll_full_0/pd_0/VDD" "pll_full_0/divider_0/w_n140_1520#"
-merge "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/divbuf_0/VDD"
-merge "pll_full_0/divbuf_0/VDD" "ro_complete_0/ro_var_extend_0/vdd"
-merge "ro_complete_0/ro_var_extend_0/vdd" "vdda1"
merge "ro_complete_0/cbank_1/a5" "gpio_analog[14]" -108.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14000 -440 0 0 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_4/IN" "ro_complete_0/li_7140_1400#" -1022.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9480 -100 0 0 -210130 -3398 0 0 0 0 0 0 0 0
-merge "ro_complete_0/li_7140_1400#" "li_44580_213200#"
-merge "ashish_0/Gnd" "li_133706_697044#" -23598.9 -140904 -1508 0 0 0 0 0 0 0 0 -51450 -1140 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99700 -3048 177118 -2358 165198 -1754 -25907091 -55295 1999685 -19239 -100131 -12764 0 0
+merge "ashish_0/Gnd" "li_133706_697044#" -17052.7 -140904 -1508 0 0 0 0 0 0 0 0 -51450 -1140 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -122972 -2308 -56000 -1060 -52400 -1060 -25278340 -44229 1922 -3050 -92226 -3350 0 0
merge "li_133706_697044#" "ashish_0/w_n2256_n1456#"
-merge "ashish_0/w_n2256_n1456#" "divbuf_3/VDD"
-merge "divbuf_3/VDD" "divbuf_3/OUT"
-merge "divbuf_3/OUT" "divbuf_3/IN"
-merge "divbuf_3/IN" "divbuf_3/GND"
-merge "divbuf_3/GND" "divbuf_2/VDD"
-merge "divbuf_2/VDD" "divbuf_2/GND"
-merge "divbuf_2/GND" "cp_0/gnd!"
-merge "cp_0/gnd!" "pll_full_0/divbuf_1/GND"
-merge "pll_full_0/divbuf_1/GND" "pll_full_0/pd_0/and_pd_0/GND"
-merge "pll_full_0/pd_0/and_pd_0/GND" "pll_full_0/divider_0/prescaler_0/GND"
-merge "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/divider_0/prescaler_0/tspc_0/gnd!"
-merge "pll_full_0/divider_0/prescaler_0/tspc_0/gnd!" "pll_full_0/divider_0/mc2"
-merge "pll_full_0/divider_0/mc2" "pll_full_0/filter_0/gnd!"
-merge "pll_full_0/filter_0/gnd!" "pll_full_0/filter_0/gnd"
-merge "pll_full_0/filter_0/gnd" "pll_full_0/divbuf_0/GND"
-merge "pll_full_0/divbuf_0/GND" "vssa1"
+merge "ashish_0/w_n2256_n1456#" "cp_0/gnd!"
+merge "cp_0/gnd!" "vssa1"
merge "vssa1" "m3_560230_657890#"
merge "m3_560230_657890#" "m2_560230_657890#"
merge "m2_560230_657890#" "m1_560230_657890#"
merge "m1_560230_657890#" "li_560230_657890#"
-merge "li_560230_657890#" "pd_0/tspc_r_1/D"
-merge "pd_0/tspc_r_1/D" "pd_0/and_pd_0/GND"
-merge "pd_0/and_pd_0/GND" "pd_0/tspc_r_1/VDD"
-merge "pd_0/tspc_r_1/VDD" "pd_0/VDD"
-merge "pd_0/VDD" "pd_0/REF"
-merge "pd_0/REF" "divbuf_1/VDD"
-merge "divbuf_1/VDD" "divbuf_0/VDD"
-merge "divbuf_0/VDD" "m4_33166_649670#"
-merge "m4_33166_649670#" "divbuf_1/OUT"
-merge "divbuf_1/OUT" "pd_0/w_n446_n1456#"
-merge "pd_0/w_n446_n1456#" "divbuf_1/GND"
-merge "divbuf_1/GND" "divbuf_0/GND"
-merge "divbuf_0/GND" "divbuf_0/OUT"
-merge "divbuf_0/OUT" "li_19434_665672#"
-merge "li_19434_665672#" "pll_full_0/VSUBS"
-merge "pll_full_0/VSUBS" "divbuf_4/GND"
-merge "divbuf_4/GND" "ro_complete_0/w_7764_n10666#"
+merge "li_560230_657890#" "divbuf_0/GND"
+merge "divbuf_0/GND" "ro_complete_0/w_7764_n10666#"
merge "ro_complete_0/w_7764_n10666#" "filter_0/gnd!"
merge "filter_0/gnd!" "filter_0/gnd"
merge "filter_0/gnd" "m3_60440_111096#"
@@ -1752,21 +1587,16 @@
merge "ro_complete_0/cbank_0/switch_5/vin" "ro_complete_0/a0"
merge "ro_complete_0/a0" "ro_complete_0/cbank_0/gnd!"
merge "ro_complete_0/cbank_0/gnd!" "gpio_analog[12]"
+merge "divbuf_0/IN" "ro_complete_0/li_7140_1400#" -1022.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9480 -100 0 0 -210130 -3398 0 0 0 0 0 0 0 0
+merge "ro_complete_0/li_7140_1400#" "li_44580_213200#"
+merge "divbuf_0/OUT" "io_analog[5]" -28563.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10120 -140 0 0 0 0 -25041370 -30604 -25000000 -30000 -25000000 -30000 0 0
merge "cp_0/out" "io_analog[0]" -6988.98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18960 -860 0 0 -12500000 -15000 0 0 0 0 0 0
merge "ro_complete_0/a4" "ro_complete_0/cbank_1/a4" 57.5575 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 141900 -268 0 0 0 0 0 0 0 0 0 0 0 0
merge "ro_complete_0/cbank_1/a4" "li_15258_203018#"
merge "ro_complete_0/cbank_1/a2" "li_27474_203846#" -94.1672 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -11424 -304 0 0 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_2/IN" "li_19158_660978#" -172.879 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -632410 -152 424280 0 89938 -269 0 0 0 0 0 0 0 0
merge "cp_0/down" "io_analog[1]" -9840.22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -212059 -3882 76069 -1722 -1039615 -6232 -12500000 -15000 0 0 0 0 0 0
-merge "pd_0/UP" "divbuf_1/IN" -658.131 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5280 -128 -242260 -2208 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_1/IN" "li_32770_653524#"
-merge "pd_0/DOWN" "divbuf_0/IN" -2798.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5072 -132 -1498607 -10805 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_0/IN" "li_32886_649070#"
-merge "divbuf_2/OUT" "pd_0/DIV" 38.274 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3640 -200 0 0 -59840 -176 0 0 0 0 0 0 0 0
-merge "pd_0/DIV" "li_19160_659970#"
-merge "ro_complete_0/cbank_1/gnd!" "m3_31530_200540#" -1415.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -581600 -3054 -293050 -4580 0 0 0 0
merge "ashish_0/von" "io_analog[7]" -11658.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12500000 -15000 -1401036 -26026 0 0 0 0
+merge "ro_complete_0/cbank_1/gnd!" "m3_31530_200540#" -1415.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -581600 -3054 -293050 -4580 0 0 0 0
merge "ashish_0/vop" "io_analog[6]" -28414.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25000000 -30000 -24995350 -30672 -25000000 -30000 0 0
-merge "divbuf_4/OUT" "io_analog[5]" -28563.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10120 -140 0 0 0 0 -25041370 -30604 -25000000 -30000 -25000000 -30000 0 0
merge "ro_complete_0/cbank_1/a3" "li_22752_203148#" -243.61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -137308 -424 0 0 0 0 0 0 0 0 0 0 0 0
merge "filter_0/v" "gpio_noesd[15]" -5531.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29524 -318 -14120 -1840 -2672328 -19524 0 0 0 0 0 0 0 0
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index a29df35..7816128 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/ashish.ext b/mag/ashish.ext
index e6c2307..c28bff1 100644
--- a/mag/ashish.ext
+++ b/mag/ashish.ext
@@ -12,17 +12,17 @@
node "vop" 39321 16419.5 310 -840 p 0 0 0 0 0 0 0 0 1200000 16800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 858000 46200 0 0 833400 26640 598200 19920 1068600 28040 932400 22680 543400 15040 0 0 0 0
node "von" 39320 16410.5 310 520 p 0 0 0 0 0 0 0 0 1200000 16800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 858000 46200 0 0 833400 26640 598200 19920 1063800 28120 825800 20380 510500 14100 0 0 0 0
substrate "a_n2230_n1430#" 0 0 -2230 -1430 ppd 0 0 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11614200 51640 0 0 0 0 0 0 0 0 0 0 0 0
+cap "von" "a_150_0#" 9143.33
+cap "a_150_0#" "Gnd" 1735.6
cap "von" "vop" 12870.6
-cap "Gnd" "vop" 327.431
-cap "a_150_n710#" "vop" 9143.33
-cap "a_150_0#" "von" 9143.33
-cap "Gnd" "a_150_0#" 1735.6
-cap "a_150_n710#" "a_150_0#" 6307.37
-cap "Gnd" "von" 327.431
-cap "a_150_n710#" "von" 4332.97
-cap "a_150_n710#" "Gnd" 1711.55
-cap "a_150_0#" "vop" 4443.99
-device csubckt sky130_fd_pr__cap_mim_m3_1 -1490 -1090 -1489 -1089 w=1042 l=2000 "None" "a_150_0#" 5764 0 "a_150_n710#" 70 0
+cap "vop" "Gnd" 327.431
+cap "vop" "a_150_0#" 4443.99
+cap "von" "a_150_n710#" 4332.97
+cap "Gnd" "a_150_n710#" 1711.55
+cap "a_150_0#" "a_150_n710#" 6307.37
+cap "vop" "a_150_n710#" 9143.33
+cap "von" "Gnd" 327.431
+device csubckt sky130_fd_pr__cap_mim_m3_1 -1490 -1090 -1489 -1089 w=1042 l=2000 "None" "a_150_0#" 5764 0 "a_150_n710#" 3600 0
device msubckt sky130_fd_pr__nfet_01v8 7020 -710 7021 -709 l=30 w=500 "a_n2230_n1430#" "von" 60 0 "vop" 500 0 "a_150_n710#" 500 0
device msubckt sky130_fd_pr__nfet_01v8 6790 -710 6791 -709 l=30 w=500 "a_n2230_n1430#" "von" 60 0 "a_150_n710#" 500 0 "vop" 500 0
device msubckt sky130_fd_pr__nfet_01v8 6560 -710 6561 -709 l=30 w=500 "a_n2230_n1430#" "von" 60 0 "vop" 500 0 "a_150_n710#" 500 0
diff --git a/mag/cbank.ext b/mag/cbank.ext
index 0bbc41b..bf15d5f 100644
--- a/mag/cbank.ext
+++ b/mag/cbank.ext
@@ -26,18 +26,18 @@
node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd!" 0 0 950 -1660 ppd 0 0 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
-cap "a_5640_n30#" "a_6660_n30#" 191.52
-cap "a_4660_n30#" "a_5640_n30#" 199.5
-cap "a_3680_n30#" "a_4660_n30#" 199.5
+cap "a_1720_n30#" "li_1720_n30#" 18.13
+cap "v" "li_1720_n30#" 1301.39
+cap "a_2730_n30#" "li_1720_n30#" 199.5
cap "a_6660_n30#" "v" 1301.39
cap "a_5640_n30#" "v" 1301.39
+cap "a_5640_n30#" "a_6660_n30#" 191.52
cap "a_4660_n30#" "v" 1301.39
-cap "v" "li_1720_n30#" 1301.39
cap "a_3680_n30#" "v" 1301.39
-cap "a_1720_n30#" "li_1720_n30#" 18.13
-cap "a_2730_n30#" "li_1720_n30#" 199.5
-cap "a_2730_n30#" "a_3680_n30#" 199.5
+cap "a_4660_n30#" "a_5640_n30#" 199.5
cap "a_2730_n30#" "v" 1301.39
+cap "a_3680_n30#" "a_4660_n30#" 199.5
+cap "a_2730_n30#" "a_3680_n30#" 199.5
device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1920 0 "a_6660_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1920 0 "a_5640_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1920 0 "a_4660_n30#" 1440 0
@@ -55,10 +55,10 @@
cap "switch_1/vcont" "switch_1/vin" 83.635
cap "switch_3/vcont" "switch_3/vout" 4.23077
cap "switch_3/vcont" "switch_3/vin" 83.635
+cap "switch_5/vcont" "switch_5/vout" 4.23077
cap "switch_5/vcont" "switch_5/vin" 83.635
cap "switch_4/vcont" "switch_4/vout" 4.23077
cap "switch_4/vcont" "switch_4/vin" 83.635
-cap "switch_5/vcont" "switch_5/vout" 4.23077
merge "switch_5/VSUBS" "switch_5/vout" -332.789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -21300 -442 0 0 0 0
merge "switch_5/vout" "switch_4/VSUBS"
merge "switch_4/VSUBS" "switch_4/vout"
diff --git a/mag/cp.ext b/mag/cp.ext
index 6878327..f42b5ed 100644
--- a/mag/cp.ext
+++ b/mag/cp.ext
@@ -20,23 +20,23 @@
node "upbar" 658 1347.77 6750 -50 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0
node "vdd!" 18302 139352 -830 -170 nw 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0
substrate "gnd!" 0 0 -370 -2840 ndif 0 0 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0
-cap "a_1710_0#" "down" 320.4
-cap "a_10_n50#" "vdd!" 530.297
-cap "out" "a_1710_0#" 841.733
cap "vdd!" "a_3060_n2840#" 320.4
-cap "upbar" "down" 20.625
cap "vdd!" "a_7110_0#" 42.55
cap "vdd!" "a_6370_0#" 402.828
cap "vdd!" "a_3060_0#" 1788.27
cap "vdd!" "a_1710_0#" 714.147
cap "vdd!" "out" 376.075
+cap "vdd!" "a_1710_n2840#" 254.08
+cap "vdd!" "a_10_n50#" 530.297
+cap "vdd!" "upbar" 149.92
+cap "a_1710_0#" "down" 320.4
+cap "upbar" "down" 20.625
cap "a_10_n50#" "vbias" 192.9
+cap "out" "a_1710_0#" 841.733
cap "a_1710_n2840#" "a_1710_0#" 828.847
cap "a_10_n50#" "a_1710_0#" 41.6842
cap "a_1710_n2840#" "out" 606.81
-cap "vdd!" "upbar" 149.92
-cap "a_1710_n2840#" "upbar" 291.6
-cap "a_1710_n2840#" "vdd!" 254.08
+cap "upbar" "a_1710_n2840#" 291.6
device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/mag/divbuf.ext b/mag/divbuf.ext
index 3dabc69..dc30082 100644
--- a/mag/divbuf.ext
+++ b/mag/divbuf.ext
@@ -15,27 +15,27 @@
node "a_492_n240#" 5680 1971.5 492 -240 ndif 0 0 0 0 0 0 0 0 8000 360 16000 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98500 6360 0 0 45700 1780 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 14648 361353 -120 -1810 nw 0 0 0 0 65410992 211244 0 0 439400 13520 13732900 416520 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13282200 474060 6457100 321020 2194600 86640 2194600 86640 7414620 232084 0 0 0 0
substrate "GND" 0 0 -910 -1340 ppd 0 0 0 0 0 0 0 0 6230000 216180 8240400 129360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44214000 575324 6574800 325500 2243600 88560 2372800 90180 11603420 130104 0 0 0 0
-cap "OUT3" "OUT2" 1365.26
-cap "OUT3" "OUT" 261.644
-cap "OUT3" "OUT5" 13.5294
-cap "IN" "OUT5" 0.811765
-cap "a_492_n240#" "IN" 129.055
-cap "OUT3" "VDD" 6618.1
-cap "VDD" "IN" 43.09
-cap "OUT4" "OUT" 1106.9
-cap "OUT4" "OUT5" 20262.7
-cap "OUT2" "OUT" 55.9684
-cap "OUT4" "VDD" 26017.4
-cap "a_492_n240#" "OUT" 3.77143
-cap "OUT2" "OUT5" 19.4824
+cap "VDD" "OUT3" 6618.1
cap "a_492_n240#" "OUT2" 422.539
-cap "OUT5" "OUT" 43383.3
-cap "a_492_n240#" "OUT5" 5.95294
-cap "VDD" "OUT" 180323
cap "VDD" "OUT2" 1740.7
-cap "a_492_n240#" "VDD" 485.687
+cap "a_492_n240#" "IN" 129.055
+cap "VDD" "IN" 43.09
+cap "OUT4" "OUT5" 20262.7
+cap "VDD" "a_492_n240#" 485.687
+cap "OUT" "OUT5" 43383.3
+cap "OUT" "OUT4" 1106.9
+cap "OUT3" "OUT5" 13.5294
+cap "OUT2" "OUT5" 19.4824
+cap "OUT3" "OUT4" 5155.49
+cap "OUT" "OUT3" 261.644
+cap "IN" "OUT5" 0.811765
+cap "OUT" "OUT2" 55.9684
+cap "a_492_n240#" "OUT5" 5.95294
cap "VDD" "OUT5" 83099.7
-cap "OUT4" "OUT3" 5155.49
+cap "OUT2" "OUT3" 1365.26
+cap "OUT" "a_492_n240#" 3.77143
+cap "VDD" "OUT4" 26017.4
+cap "OUT" "VDD" 180323
device msubckt sky130_fd_pr__pfet_01v8 61320 -1540 61321 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "OUT" 390 0 "VDD" 390 0
device msubckt sky130_fd_pr__pfet_01v8 61200 -1540 61201 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "VDD" 390 0 "OUT" 390 0
device msubckt sky130_fd_pr__pfet_01v8 61080 -1540 61081 -1539 l=30 w=390 "VDD" "OUT5" 60 0 "OUT" 390 0 "VDD" 390 0
diff --git a/mag/filter.ext b/mag/filter.ext
index d2dc354..0c031de 100644
--- a/mag/filter.ext
+++ b/mag/filter.ext
@@ -17,8 +17,8 @@
node "a_4216_n4798#" 51429 0 4216 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "a_4216_n2998#" 382 1030.6 4216 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 -3380 -21770 ppd 0 0 0 0 0 0 0 0 0 0 4867200 74880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53899200 149720 172800 2880 172800 2880 263135300 79980 0 0 0 0 0 0
-cap "a_4216_n5230#" "v" 187.252
-cap "a_4216_n2998#" "v" 311.161
+cap "v" "a_4216_n5230#" 187.252
+cap "v" "a_4216_n2998#" 311.161
device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -20940 -2459 -20939 w=6000 l=6000 "None" "a_4216_n5230#" 22900 0 "gnd" 200 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -20840 4471 -20839 w=6000 l=6000 "None" "a_4216_n5230#" 22890 0 "gnd" 200 0
device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -14150 -2459 -14149 w=6000 l=6000 "None" "a_4216_n5230#" 23680 0 "gnd" 200 0
diff --git a/mag/ro_complete.ext b/mag/ro_complete.ext
index 1b7aac6..73e00c0 100644
--- a/mag/ro_complete.ext
+++ b/mag/ro_complete.ext
@@ -18,60 +18,60 @@
node "li_1010_1400#" 88 1456.19 1010 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1200 19600 560 19600 560 19600 560 196600 4100 0 0 0 0
node "li_7140_1400#" 85 7250.05 7140 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50400 1320 32400 720 2607360 22208 57600 960 57600 960 0 0 0 0
substrate "a_7790_n10640#" 0 0 7790 -10640 ppd 0 0 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1096400 18460 1326400 20840 1085200 18160 1085200 18160 4224000 28760 0 0 0 0
-cap "li_4080_1390#" "a5" 77.72
cap "li_7140_1400#" "a5" 100.96
+cap "li_4080_1390#" "a5" 77.72
cap "cbank_2/a0" "cbank_2/switch_0/vout" 46.5385
cap "cbank_2/a2" "cbank_2/switch_2/vout" 46.5385
cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385
-cap "cbank_2/a3" "cbank_2/switch_3/vout" 46.5385
-cap "cbank_2/switch_5/vout" "cbank_2/a5" 12.6923
-cap "cbank_2/switch_4/vout" "cbank_2/a4" 46.5385
+cap "cbank_2/switch_3/vout" "cbank_2/a3" 46.5385
+cap "cbank_2/a4" "cbank_2/switch_4/vout" 46.5385
+cap "cbank_2/a5" "cbank_2/switch_5/vout" 12.6923
cap "cbank_2/switch_5/vin" "li_7140_1400#" 24
cap "cbank_2/a5" "cbank_2/switch_5/vout" 33.8462
cap "cbank_1/gnd!" "cbank_2/v" 86.7059
-cap "a0" "cbank_2/v" 53.41
-cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/switch_1/vin" "a0" 21.8167
cap "cbank_1/gnd!" "a0" 181.38
-cap "a1" "cbank_2/v" 53.41
-cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882
+cap "a0" "cbank_2/v" 53.41
+cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/switch_1/vout" "a2" 60.0024
cap "cbank_1/switch_2/vin" "a1" 23.6566
cap "cbank_1/switch_1/vout" "a1" 209.96
-cap "cbank_2/v" "a2" 53.41
-cap "cbank_1/gnd!" "a3" 192.323
-cap "cbank_1/gnd!" "a2" 124.302
+cap "a1" "cbank_2/v" 53.41
+cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882
+cap "a3" "cbank_2/v" 53.41
+cap "a2" "cbank_2/v" 53.41
cap "cbank_1/switch_4/vin" "a3" 11.4157
cap "cbank_1/switch_3/vin" "a2" 23.515
cap "cbank_1/gnd!" "cbank_2/v" 275.882
-cap "cbank_2/v" "a3" 53.41
-cap "a4" "li_7140_1400#" 53.41
+cap "cbank_1/gnd!" "a3" 192.323
+cap "cbank_1/gnd!" "a2" 124.302
cap "cbank_1/switch_4/vout" "li_7140_1400#" 275.882
-cap "cbank_1/switch_5/vin" "a4" 20.5602
cap "cbank_1/switch_4/vout" "a4" 190.632
cap "cbank_1/switch_4/vin" "a3" 11.4157
+cap "a4" "li_7140_1400#" 53.41
+cap "a4" "cbank_1/switch_5/vin" 20.5602
cap "cbank_1/switch_5/vout" "li_7140_1400#" 91.6761
+cap "li_7140_1400#" "cbank_2/a_6660_n30#" 126
cap "cbank_1/switch_5/vout" "a5" 124.931
-cap "cbank_2/a_6660_n30#" "li_7140_1400#" 126
cap "cbank_1/a0" "cbank_1/switch_1/vin" 106.517
cap "cbank_1/a0" "cbank_1/switch_0/vout" 248.36
cap "cbank_1/a2" "cbank_1/switch_1/vout" 149.619
cap "cbank_1/a1" "cbank_1/switch_2/vin" 115.5
cap "cbank_1/a1" "cbank_1/switch_1/vout" 289.235
-cap "cbank_1/gnd!" "cbank_1/a3" 264.413
-cap "cbank_1/gnd!" "cbank_1/a2" 103.081
-cap "cbank_1/a3" "cbank_1/switch_4/vin" 55.7355
cap "cbank_1/a2" "cbank_1/switch_3/vin" 114.808
-cap "cbank_1/a4" "cbank_1/switch_4/vout" 261.965
-cap "cbank_1/switch_4/vin" "a3" 55.7355
+cap "cbank_1/gnd!" "cbank_1/a3" 264.413
+cap "cbank_1/a3" "cbank_1/switch_4/vin" 55.7355
+cap "cbank_1/gnd!" "cbank_1/a2" 103.081
cap "cbank_1/a5" "cbank_1/switch_4/vout" 12.6923
cap "cbank_1/a4" "cbank_1/switch_5/vin" 100.382
+cap "cbank_1/a4" "cbank_1/switch_4/vout" 261.965
+cap "cbank_1/switch_4/vin" "a3" 55.7355
cap "cbank_1/a5" "cbank_1/switch_5/vout" 143.406
cap "cbank_0/gnd!" "cbank_1/v" 47.5484
cap "cbank_1/a0" "cbank_1/v" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_1/a1" "cbank_1/v" 53.41
-cap "cbank_0/gnd!" "cbank_1/v" 151.29
+cap "cbank_1/v" "cbank_0/gnd!" 151.29
cap "cbank_1/a3" "cbank_1/v" 53.41
cap "cbank_1/a2" "cbank_1/v" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 151.29
@@ -88,8 +88,8 @@
cap "cbank_0/switch_2/vin" "a1" 89.259
cap "cbank_0/switch_1/vout" "a1" 347.808
cap "cbank_0/switch_4/vin" "a3" 43.0727
-cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_0/switch_3/vin" "a2" 88.7246
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_0/gnd!" "a3" 316.073
cap "cbank_0/gnd!" "a2" 182.851
cap "cbank_0/switch_4/vout" "li_4080_1390#" 151.29
@@ -104,9 +104,9 @@
cap "cbank_0/a2" "cbank_0/switch_2/vout" 91.0707
cap "cbank_0/a1" "cbank_0/switch_2/vin" 49.8976
cap "cbank_0/a1" "cbank_0/switch_1/vout" 151.387
-cap "cbank_0/switch_4/vin" "cbank_0/a3" 24.0785
-cap "cbank_0/switch_3/vout" "cbank_0/a3" 140.663
-cap "cbank_0/switch_3/vin" "cbank_0/a2" 49.5988
+cap "cbank_0/a3" "cbank_0/switch_4/vin" 24.0785
+cap "cbank_0/a3" "cbank_0/switch_3/vout" 140.663
+cap "cbank_0/a2" "cbank_0/switch_3/vin" 49.5988
cap "cbank_0/a2" "cbank_0/switch_2/vout" 44.5323
cap "cbank_0/switch_4/vin" "a3" 24.0785
cap "cbank_0/a5" "cbank_0/switch_5/vout" 12.6923
@@ -119,17 +119,17 @@
cap "ro_var_extend_0/gnd" "li_4080_1390#" 415.935
cap "ro_var_extend_0/gnd" "li_7140_1400#" 294.59
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
-cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
+cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 215.6
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 475.062
cap "ro_var_extend_0/gnd" "ro_var_extend_0/vcont" 3.86897
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 475.062
merge "cbank_0/a4" "cbank_1/a4" -1801.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -154480 -6032 0 0 0 0 0 0 0 0 0 0 0 0
merge "cbank_1/a4" "cbank_2/a4"
merge "cbank_2/a4" "a4"
diff --git a/mag/ro_var_extend.ext b/mag/ro_var_extend.ext
index 2880aa7..b8047f1 100644
--- a/mag/ro_var_extend.ext
+++ b/mag/ro_var_extend.ext
@@ -14,16 +14,16 @@
node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
node "vdd" 21463 18367.8 -250 320 nw 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 -710 -890 ppd 0 0 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
+cap "vcont" "w_n120_n750#" 140.194
cap "out1" "out2" 40.8506
cap "out3" "out2" 1263.05
cap "out3" "out1" 1156.32
-cap "vdd" "out2" 235.622
-cap "vdd" "out1" 230.66
-cap "w_n120_n750#" "vcont" 140.194
cap "w_n120_n750#" "out2" 789.263
cap "w_n120_n750#" "out1" 569.035
-cap "vdd" "out3" 230.554
+cap "vdd" "out2" 235.622
cap "w_n120_n750#" "out3" 215.464
+cap "vdd" "out1" 230.66
+cap "vdd" "out3" 230.554
device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0
device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0
device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0
diff --git a/mag/switch.ext b/mag/switch.ext
index b4ef9e9..b5399a5 100644
--- a/mag/switch.ext
+++ b/mag/switch.ext
@@ -9,7 +9,7 @@
node "vin" 1082 0 -190 0 ndif 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0
node "vcont" 1139 384.82 -40 1460 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vcont" "vin" 8.25
cap "vcont" "vout" 16.5
+cap "vcont" "vin" 8.25
cap "vin" "vout" 420
device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "VSUBS" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
index a91c343..eea82c0 100644
--- a/mag/user_analog_project_wrapper.ext
+++ b/mag/user_analog_project_wrapper.ext
@@ -1,4 +1,4 @@
-timestamp 1641019647
+timestamp 1641020346
version 8.3
tech sky130A
style ngspice()
@@ -7,12 +7,6 @@
use filter filter_0 1 0 57226 0 1 133758
use divbuf divbuf_3 1 0 45140 0 1 213270
use ro_complete ro_complete_1 1 0 31950 0 1 214900
-use pll_full pll_full_0 1 0 383720 0 1 542022
-use pd pd_0 1 0 23666 0 1 654896
-use divbuf divbuf_0 1 0 19884 0 1 665726
-use divbuf divbuf_1 1 0 19702 0 1 661018
-use divbuf divbuf_5 1 0 33336 0 1 653584
-use divbuf divbuf_4 1 0 33492 0 1 649208
use ashish ashish_1 1 0 134960 0 1 695750
use cp cp_0 1 0 556210 0 1 661320
port "io_analog[4]" 41 329294 702300 334294 704800 m5
@@ -710,8 +704,6 @@
node "io_analog[5]" 0 2925 227594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
node "io_analog[6]" 0 2925 175894 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
node "m4_28900_141410#" 0 522112 28900 141410 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1293044300 1426300 0 0 0 0
-node "m4_374062_561532#" 1 1450.42 374062 561532 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 510708 7288 0 0 0 0
-node "m4_33166_649670#" 1 989.123 33166 649670 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 431616 4880 0 0 0 0
node "m4_115800_678290#" 0 74285.9 115800 678290 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 185113800 208280 0 0 0 0
node "io_analog[4]" 0 2775 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
node "io_analog[4]" 0 6748.8 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33255036 36480 0 0 0 0
@@ -858,7 +850,7 @@
node "io_out[12]" 1 613.728 583520 498868 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_oeb[12]" 1 613.728 583520 500050 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "vdda1" 0 6519 582340 540562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "vdda1" 0 1.52605e+06 582340 550562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38767100 31180 3774432368 4149300 0 0 0 0
+node "vdda1" 0 1.36295e+06 582340 550562 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38767100 31180 3404867360 3673880 0 0 0 0
node "io_oeb[14]" 1 613.728 -800 505620 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_out[14]" 1 613.728 -800 506802 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in[14]" 1 613.728 -800 507984 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
@@ -878,9 +870,9 @@
node "vccd2" 0 6519 0 633842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vccd2" 0 6519 0 643842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "io_analog[10]" 0 9599.96 0 680242 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18838880 19260 0 0 0 0 0 0
-node "vssa1" 0 1.60767e+06 520594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111414492 212628 9904824 51484 4648652020 4347256 0 0
+node "vssa1" 1 1.40984e+06 520594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 93252996 143272 6153300 16820 4103788788 3879532 0 0
node "vssa1" 0 6519 510594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "io_analog[3]" 0 6863.94 413394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12588800 15060 0 0 0 0 0 0
+node "io_analog[3]" 0 56384.6 413394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104349800 122340 0 0 0 0 0 0
node "io_analog[4]" 0 6825 329294 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0 0 0
node "io_clamp_high[0]" 0 3577 326794 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5500000 9400 0 0 0 0 0 0
node "io_clamp_low[0]" 0 3577 324294 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5500000 9400 0 0 0 0 0 0
@@ -894,7 +886,7 @@
node "io_analog[6]" 0 13587.8 165594 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27075000 26660 0 0 0 0 0 0
node "io_analog[7]" 0 19886.5 120194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20826000 24200 10481900 52740 0 0 0 0
node "io_analog[8]" 0 6825 68194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0 0 0
-node "io_analog[9]" 0 25109.4 16194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44116712 57924 0 0 0 0 0 0
+node "io_analog[9]" 0 18049.3 16194 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32527472 40444 0 0 0 0 0 0
node "user_irq[2]" 1 631.648 583250 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "user_irq[1]" 1 631.648 582068 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "user_irq[0]" 1 631.648 580886 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
@@ -1389,7 +1381,7 @@
node "wbs_ack_o" 1 631.648 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_rst_i" 1 631.648 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
node "wb_clk_i" 1 631.648 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
-node "gpio_analog[7]" 1 92325.9 -800 511530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 101344120 236144 692248 5328 0 0 0 0 0 0
+node "gpio_analog[7]" 1 3924.79 -800 511530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2862724 9088 692248 5328 0 0 0 0 0 0
node "m2_560230_657890#" 0 373.1 560230 657890 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0
node "m1_560230_657890#" 0 373.1 560230 657890 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0
node "io_analog[0]" 2 38830.7 582300 677984 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1399200 8000 34491080 72944 15367748 18360 0 0 0 0 0 0
@@ -1403,116 +1395,103 @@
node "gpio_analog[12]" 716 98099.1 -800 295420 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1095100 16300 623200 3160 623200 3160 137147620 248060 0 0 0 0 0 0
node "vdda1" 15 593735 582340 225230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22400 600 429100 3760 65000 1020 1201464100 1132580 0 0 0 0 0 0
node "gpio_analog[13]" 1752 65155.7 -800 252398 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1736100 31800 623200 3160 623200 3160 89466360 131860 0 0 0 0 0 0
-node "li_32886_649070#" 19 8112.57 32886 649070 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69048 1052 3807848 25996 0 0 0 0 0 0 0 0 0 0
-node "li_32770_653524#" 18 4768.08 32770 653524 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44100 840 1514148 17272 0 0 0 0 0 0 0 0 0 0
node "io_analog[1]" 83 69573.1 566594 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 497300 4200 5607252 15716 66140716 123668 20262080 20024 0 0 0 0 0 0
node "li_560230_657890#" 12 691.975 560230 657890 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19160_659970#" 23 13020.1 19160 659970 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43788 856 482848 3292 10770156 36192 0 0 0 0 0 0 0 0
node "li_555470_660400#" 220 1823.62 555470 660400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 363696 5408 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19158_660978#" 17 33431.1 19158 660978 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52000 920 341300 2980 33575248 88620 0 0 0 0 0 0 0 0
-node "li_17838_664356#" 13 750.816 17838 664356 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 234936 1940 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_19434_665672#" 148 533397 19434 665672 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 168364 3032 973960 10980 1089008 10716 326745336 531348 510727440 761616 414757328 548908 0 0
-node "li_17806_665450#" 13 750.816 17806 665450 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 234936 1940 0 0 0 0 0 0 0 0 0 0 0 0
node "io_analog[2]" 39 130432 465394 702300 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 531500 3408 422500 2600 155574764 265284 18083524 18844 0 0 0 0 0 0
node "li_133706_697044#" 14 433.006 133706 697044 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 97088 1248 0 0 0 0 0 0 0 0 0 0 0 0
node "w_559500_660830#" 2061 2427.03 559500 660830 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
node "w_559560_661800#" 17515 3366 559560 661800 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "a_560230_657890#" 0 0 560230 657890 ppd 0 0 0 0 0 0 0 0 0 0 207000 1820 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "w_559560_661800#" "w_559500_660830#" 224.4
-cap "gpio_analog[15]" "m3_60440_111096#" 5372.79
-cap "io_analog[5]" "vssa1" 23110.9
-cap "gpio_noesd[15]" "gpio_analog[17]" 5801.25
-cap "gpio_analog[14]" "vssd1" 248
-cap "gpio_analog[14]" "gpio_analog[17]" 508.4
-cap "m1_560230_657890#" "m2_560230_657890#" 693.45
-cap "io_analog[5]" "m4_115800_678290#" 1008.9
-cap "gpio_noesd[15]" "gpio_analog[16]" 9283.52
-cap "gpio_analog[14]" "gpio_analog[16]" 570.4
-cap "m3_31530_200540#" "vssd1" 336
-cap "m2_560230_657890#" "vssa1" 26.4
-cap "li_32770_653524#" "li_32886_649070#" 1704.54
-cap "vdda1" "vssa1" 3126.6
-cap "io_analog[5]" "io_clamp_low[1]" 525
-cap "io_analog[1]" "io_analog[0]" 5625.78
-cap "li_560230_657890#" "m1_560230_657890#" 589.95
-cap "m1_560230_657890#" "vssa1" 19.8
-cap "li_22752_203148#" "gpio_analog[16]" 772.8
-cap "li_27474_203846#" "gpio_analog[17]" 688.8
-cap "io_analog[5]" "vdda1" 45782.9
-cap "li_560230_657890#" "vssa1" 13.2
-cap "li_15258_203018#" "gpio_analog[14]" 3134.17
-cap "gpio_noesd[15]" "gpio_analog[15]" 11274.7
-cap "li_22752_203148#" "gpio_analog[14]" 627.84
-cap "li_19434_665672#" "li_32886_649070#" 1075.27
-cap "gpio_analog[14]" "gpio_analog[15]" 678.9
-cap "li_22752_203148#" "li_15258_203018#" 534.48
-cap "li_15258_203018#" "gpio_analog[15]" 919.8
-cap "li_19434_665672#" "li_32770_653524#" 247.927
-cap "li_19434_665672#" "li_19160_659970#" 21092.8
-cap "vdda1" "vdda1" 11170.4
-cap "vssa1" "m4_115800_678290#" 6516.2
-cap "gpio_analog[14]" "m3_31530_200540#" 283.6
-cap "io_analog[2]" "vssa1" 1182.97
-cap "io_analog[4]" "io_analog[4]" 21250
-cap "io_clamp_high[0]" "io_analog[4]" 525
-cap "li_19434_665672#" "li_19158_660978#" 9909.14
-cap "li_15258_203018#" "m3_31530_200540#" 280.2
-cap "li_27474_203846#" "gpio_analog[14]" 561.64
-cap "li_22752_203148#" "m3_31530_200540#" 280.2
-cap "li_19434_665672#" "li_17838_664356#" 1028.87
-cap "li_27474_203846#" "li_15258_203018#" 485.58
-cap "io_analog[4]" "io_analog[4]" 56533.6
-cap "io_clamp_low[0]" "io_clamp_high[0]" 525
-cap "m3_60440_111096#" "m4_28900_141410#" 18845.9
-cap "li_27474_203846#" "li_22752_203148#" 485.58
-cap "vssa1" "vssd1" 598.6
-cap "io_analog[4]" "io_analog[4]" 26250
-cap "li_17806_665450#" "li_19434_665672#" 1017.32
-cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "io_analog[5]" "io_analog[5]" 21250
-cap "vssa1" "vdda1" 55830.1
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "vssd1" "m4_28900_141410#" 1117.2
-cap "io_analog[7]" "vssa1" 6884.47
-cap "io_analog[4]" "io_analog[4]" 69835.6
-cap "io_clamp_high[1]" "io_analog[5]" 525
-cap "li_27474_203846#" "m3_31530_200540#" 235.7
-cap "io_analog[5]" "io_analog[5]" 26250
cap "vssd1" "m3_60440_111096#" 598.6
-cap "io_clamp_low[1]" "io_clamp_high[1]" 525
+cap "li_560230_657890#" "vssa1" 13.2
cap "gpio_analog[17]" "m3_60440_111096#" 4031.6
-cap "io_analog[2]" "vdda1" 2018.08
-cap "li_44580_213200#" "io_analog[5]" 342.875
+cap "vdda1" "vdda1" 11170.4
+cap "io_analog[2]" "vssa1" 1182.97
cap "io_analog[6]" "io_analog[6]" 26250
-cap "io_clamp_high[2]" "io_analog[6]" 525
-cap "m2_560230_657890#" "m3_560230_657890#" 445.05
cap "vdda1" "vssd1" 1117.2
-cap "io_clamp_low[2]" "io_clamp_high[2]" 525
-cap "w_559500_660830#" "vdda1" 11.8235
+cap "io_clamp_high[0]" "io_analog[4]" 525
cap "gpio_analog[16]" "m3_60440_111096#" 4425.6
cap "io_analog[6]" "io_analog[6]" 57285.3
-cap "io_analog[6]" "io_clamp_low[2]" 525
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "m1_560230_657890#" "m2_560230_657890#" 693.45
cap "io_analog[7]" "io_analog[6]" 454.755
-cap "vssa1" "m3_560230_657890#" 480.9
+cap "gpio_noesd[15]" "gpio_analog[17]" 5801.25
+cap "gpio_analog[14]" "vssd1" 248
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "gpio_analog[14]" "gpio_analog[17]" 508.4
+cap "m3_60440_111096#" "m4_28900_141410#" 18845.9
cap "vdda1" "io_analog[5]" 10678
+cap "io_analog[7]" "vssa1" 6884.47
+cap "li_27474_203846#" "gpio_analog[17]" 688.8
+cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "io_analog[5]" "vdda1" 45782.9
cap "gpio_analog[13]" "gpio_analog[12]" 1228.81
+cap "vssd1" "m4_28900_141410#" 1117.2
+cap "gpio_analog[15]" "m3_60440_111096#" 5372.79
+cap "gpio_noesd[15]" "gpio_analog[16]" 9283.52
+cap "io_clamp_low[1]" "io_clamp_high[1]" 525
+cap "li_15258_203018#" "gpio_analog[14]" 3134.17
+cap "gpio_analog[14]" "gpio_analog[16]" 570.4
+cap "li_22752_203148#" "gpio_analog[14]" 627.84
+cap "li_27474_203846#" "gpio_analog[14]" 561.64
+cap "li_22752_203148#" "li_15258_203018#" 534.48
+cap "li_22752_203148#" "gpio_analog[16]" 772.8
+cap "li_27474_203846#" "li_15258_203018#" 485.58
+cap "io_clamp_high[2]" "io_analog[6]" 525
+cap "li_27474_203846#" "li_22752_203148#" 485.58
+cap "io_clamp_low[2]" "io_clamp_high[2]" 525
+cap "m2_560230_657890#" "m3_560230_657890#" 445.05
+cap "vdda1" "vssa1" 3126.6
+cap "gpio_noesd[15]" "gpio_analog[15]" 11274.7
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[6]" "io_clamp_low[2]" 525
+cap "li_44580_213200#" "io_analog[5]" 342.875
+cap "m3_31530_200540#" "vssd1" 336
+cap "gpio_analog[14]" "gpio_analog[15]" 678.9
+cap "vssa1" "vssd1" 598.6
+cap "io_analog[5]" "m4_115800_678290#" 1008.9
+cap "li_15258_203018#" "gpio_analog[15]" 919.8
+cap "io_analog[4]" "io_analog[4]" 56533.6
+cap "vssa1" "vdda1" 52732.6
+cap "m2_560230_657890#" "vssa1" 26.4
+cap "w_559560_661800#" "w_559500_660830#" 224.4
+cap "m1_560230_657890#" "vssa1" 19.8
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "io_analog[3]" "vdda1" 8331.27
+cap "gpio_analog[14]" "m3_31530_200540#" 283.6
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[0]" "io_analog[1]" 5625.78
+cap "m1_560230_657890#" "li_560230_657890#" 589.95
+cap "io_analog[2]" "vdda1" 2018.08
+cap "li_15258_203018#" "m3_31530_200540#" 280.2
+cap "li_22752_203148#" "m3_31530_200540#" 280.2
+cap "li_27474_203846#" "m3_31530_200540#" 235.7
+cap "io_analog[5]" "vssa1" 23110.9
+cap "vssa1" "m4_115800_678290#" 6516.2
+cap "w_559500_660830#" "vdda1" 11.8235
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "vssa1" "m3_560230_657890#" 480.9
+cap "io_analog[5]" "io_clamp_low[1]" 525
+cap "io_analog[4]" "io_analog[4]" 69835.6
+cap "io_analog[5]" "io_analog[5]" 26250
cap "filter_0/a_4216_n2998#" "filter_0/v" 60.1993
cap "filter_0/gnd" "gpio_noesd[15]" 186.856
-cap "gpio_noesd[15]" "filter_0/gnd" 383.726
+cap "filter_0/gnd" "gpio_noesd[15]" 383.726
+cap "ro_complete_1/cbank_2/switch_3/vin" "li_27474_203846#" 31.9579
cap "ro_complete_1/cbank_2/gnd!" "li_22752_203148#" 77.2083
cap "ro_complete_1/cbank_2/switch_2/vin" "li_27474_203846#" 32.2979
cap "ro_complete_1/cbank_2/gnd!" "li_27474_203846#" 299.327
-cap "ro_complete_1/cbank_2/switch_3/vin" "li_27474_203846#" 31.9579
+cap "ro_complete_1/cbank_2/switch_5/vin" "li_15258_203018#" 19.8431
cap "ro_complete_1/cbank_2/gnd!" "li_15258_203018#" 230.111
-cap "ro_complete_1/cbank_2/gnd!" "li_22752_203148#" 156.208
-cap "ro_complete_1/cbank_2/switch_5/vin" "li_15258_203018#" 19.8431
cap "ro_complete_1/cbank_2/switch_4/vin" "li_22752_203148#" 38.4304
-cap "ro_complete_1/cbank_2/switch_5/vin" "li_15258_203018#" 19.8431
+cap "ro_complete_1/cbank_2/gnd!" "li_22752_203148#" 156.208
cap "ro_complete_1/cbank_2/switch_5/vout" "gpio_analog[14]" 212.707
+cap "ro_complete_1/cbank_2/switch_5/vin" "li_15258_203018#" 19.8431
+cap "ro_complete_1/cbank_2/a2" "ro_complete_1/cbank_2/switch_2/vin" 90.5745
cap "ro_complete_1/cbank_2/a3" "ro_complete_1/cbank_2/switch_3/vout" 97.8621
cap "ro_complete_1/cbank_2/a2" "ro_complete_1/cbank_2/switch_3/vin" 89.6211
cap "ro_complete_1/cbank_2/a2" "ro_complete_1/cbank_2/switch_2/vout" 270.286
-cap "ro_complete_1/cbank_2/a2" "ro_complete_1/cbank_2/switch_2/vin" 90.5745
cap "ro_complete_1/cbank_2/a4" "ro_complete_1/cbank_2/switch_5/vin" 55.6471
cap "ro_complete_1/cbank_2/a4" "ro_complete_1/cbank_2/switch_4/vout" 175.546
cap "ro_complete_1/cbank_2/a3" "ro_complete_1/cbank_2/switch_4/vin" 107.772
@@ -1525,8 +1504,8 @@
cap "ro_complete_1/a0" "ro_complete_1/cbank_0/switch_0/vin" 8.6194
cap "ro_complete_1/a_7790_n10640#" "ro_complete_1/li_7140_1400#" 298.145
cap "divbuf_3/OUT" "divbuf_3/VDD" 17.3563
+cap "divbuf_3/GND" "divbuf_3/IN" 335.041
cap "divbuf_3/GND" "divbuf_3/OUT" 387.393
-cap "divbuf_3/IN" "divbuf_3/GND" 335.041
cap "gpio_analog[12]" "ro_complete_1/cbank_0/v" 94.5
cap "gpio_analog[12]" "ro_complete_1/cbank_0/gnd!" 134.583
cap "gpio_analog[13]" "ro_complete_1/cbank_0/v" 94.5
@@ -1546,136 +1525,29 @@
cap "ro_complete_1/a_7790_n10640#" "ro_complete_1/li_7140_1400#" 230.888
cap "ro_complete_1/ro_var_extend_0/gnd" "ro_complete_1/ro_var_extend_0/vdd" 260.125
cap "ro_complete_1/ro_var_extend_0/gnd" "ro_complete_1/ro_var_extend_0/vdd" 312.18
-cap "pll_full_0/divbuf_0/GND" "vdda1" 50.938
-cap "pll_full_0/divbuf_0/VDD" "pll_full_0/divbuf_0/IN" 74.1
-cap "pll_full_0/divbuf_0/GND" "pll_full_0/divbuf_0/VDD" 1.086
-cap "pll_full_0/divbuf_0/VDD" "pll_full_0/divbuf_0/OUT" 96.22
-cap "pll_full_0/li_n10340_n3220#" "vssa1" 411.85
-cap "pll_full_0/li_n10470_n4240#" "vssa1" 495.75
-cap "pll_full_0/filter_0/gnd" "vssa1" 177.576
-cap "pll_full_0/filter_0/gnd" "vssa1" 374.37
-cap "pll_full_0/filter_0/gnd" "vssa1" 179.56
-cap "pll_full_0/filter_0/gnd" "vssa1" 225.4
-cap "pll_full_0/filter_0/gnd" "vssa1" 321.45
-cap "pll_full_0/li_n10340_n3220#" "vssa1" 34.656
-cap "pll_full_0/li_n10470_n4240#" "vssa1" 50.72
-cap "pll_full_0/filter_0/gnd" "vssa1" 156.648
-cap "pll_full_0/filter_0/gnd" "vssa1" 327.33
-cap "pll_full_0/filter_0/gnd" "vssa1" 151.83
-cap "pll_full_0/filter_0/gnd" "vssa1" -44.39
-cap "pll_full_0/divider_0/a_n940_n20#" "vdda1" 34.12
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/m2_n10320_4830#" 109.6
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/li_n10470_n4240#" 148.6
-cap "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/divider_0/prescaler_0/tspc_2/Q" 77.975
-cap "pll_full_0/divider_0/a_n940_n20#" "pll_full_0/divider_0/w_n140_1520#" -645.86
-cap "pll_full_0/divider_0/mc2" "pll_full_0/m2_n10320_4830#" 269.9
-cap "pll_full_0/divider_0/mc2" "pll_full_0/li_n10470_n4240#" 87.58
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "pll_full_0/divider_0/mc2" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/m2_n10320_4830#" 220.66
-cap "pll_full_0/pd_0/a_n420_n1430#" "pll_full_0/divider_0/prescaler_0/GND" 229.752
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_1/VDD" 0.867876
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_1/VDD" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_1/VDD" 10.4145
-cap "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/pd_0/tspc_r_1/VDD" 10.4145
-cap "pll_full_0/m2_n10320_4830#" "vssa1" 130.96
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "vssa1" 9.54663
-cap "pll_full_0/m2_n10320_4830#" "vssa1" -20.79
-cap "pll_full_0/pd_0/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "vssa1" 0.867876
-cap "pll_full_0/pd_0/tspc_r_1/VDD" "vssa1" 10.4145
-cap "pll_full_0/pd_0/w_0_n1460#" "pll_full_0/pd_0/and_pd_0/GND" 9.54663
-cap "pll_full_0/pd_0/a_n420_n1430#" "pll_full_0/pd_0/and_pd_0/GND" 31.1864
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/REF" 14.96
-cap "pll_full_0/pd_0/a_n420_n1430#" "pll_full_0/pd_0/VDD" 39.696
-cap "pll_full_0/pd_0/a_n420_n1430#" "pll_full_0/pd_0/and_pd_0/GND" 106.318
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/REF" 45.28
-cap "pll_full_0/pd_0/VDD" "pll_full_0/pd_0/VDD" 1.77636e-15
-cap "pll_full_0/pd_0/a_n420_n1430#" "pll_full_0/pd_0/VDD" 89.248
-cap "pll_full_0/cp_0/vdd!" "pll_full_0/li_n9940_24670#" 45.7
-cap "pll_full_0/cp_0/vdd!" "pll_full_0/li_n9940_24670#" 350
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/li_n9940_24670#" 350
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 128.714
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/li_n9940_24670#" 37.41
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/divbuf_1/VDD" 2.92
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 12.4096
-cap "pll_full_0/divbuf_1/VDD" "pll_full_0/divbuf_1/GND" 106.269
-cap "pll_full_0/divbuf_1/GND" "pll_full_0/divbuf_1/VDD" 59.4592
-cap "divbuf_4/GND" "li_19434_665672#" 251.077
-cap "divbuf_4/GND" "divbuf_4/OUT" 12.0622
-cap "divbuf_4/GND" "divbuf_4/OUT" -702.284
-cap "divbuf_4/VDD" "divbuf_4/OUT" 13.2711
-cap "divbuf_4/GND" "li_32886_649070#" 439.888
-cap "divbuf_4/GND" "divbuf_4/VDD" 195.428
-cap "divbuf_4/GND" "divbuf_4/IN" -612.03
-cap "divbuf_5/GND" "divbuf_5/VDD" 94.7136
-cap "divbuf_5/GND" "li_32886_649070#" -78.925
-cap "divbuf_5/GND" "divbuf_5/OUT" 451.039
-cap "divbuf_5/OUT" "divbuf_5/VDD" 14.4404
-cap "divbuf_5/VDD" "divbuf_5/VDD" 2.84
-cap "divbuf_5/GND" "divbuf_5/VDD" 52.6144
-cap "divbuf_5/GND" "divbuf_5/OUT" 36.1464
-cap "pd_0/a_n420_n1430#" "pd_0/DIV" 161.782
-cap "divbuf_5/GND" "li_32886_649070#" 34.2391
-cap "divbuf_5/GND" "li_19434_665672#" 3.47965
-cap "divbuf_5/GND" "li_32770_653524#" -48.3526
-cap "divbuf_5/GND" "divbuf_5/IN" -8.51248
-cap "divbuf_5/GND" "divbuf_5/VDD" 93.2072
-cap "divbuf_5/GND" "li_19434_665672#" 19.7791
-cap "pd_0/a_n420_n1430#" "pd_0/REF" 177.334
-cap "pd_0/R" "pd_0/DOWN" 19.5152
-cap "pd_0/UP" "pd_0/DOWN" -4.1413
-cap "pd_0/a_n420_n1430#" "pd_0/DOWN" 239.102
-cap "pd_0/a_n420_n1430#" "pd_0/and_pd_0/GND" 140.1
-cap "pd_0/UP" "pd_0/R" 5.68421
-cap "pd_0/a_n420_n1430#" "pd_0/UP" 221.854
-cap "pd_0/VDD" "pd_0/UP" 7.87692
-cap "divbuf_5/GND" "li_32770_653524#" -113.201
-cap "divbuf_5/GND" "li_32770_653524#" 56.4574
-cap "divbuf_5/GND" "divbuf_5/VDD" 141.229
-cap "pd_0/VDD" "pd_0/tspc_r_0/D" 3.216
-cap "pd_0/a_n420_n1430#" "pd_0/tspc_r_0/D" 163.508
-cap "pd_0/VDD" "pd_0/UP" 7.87692
cap "cp_0/gnd!" "cp_0/gnd!" 6.1875
cap "cp_0/down" "cp_0/gnd!" 116.74
cap "cp_0/gnd!" "cp_0/down" 333.565
cap "cp_0/gnd!" "io_analog[1]" -98.8142
-cap "divbuf_1/GND" "li_19434_665672#" -52.89
-cap "divbuf_1/GND" "li_19160_659970#" -48.5248
-cap "divbuf_1/GND" "li_19434_665672#" -29.785
-cap "divbuf_1/GND" "divbuf_1/OUT" 66.3708
-cap "divbuf_1/OUT" "divbuf_1/VDD" 15
cap "cp_0/gnd!" "cp_0/gnd!" 1.98
-cap "divbuf_1/GND" "li_19160_659970#" -72.5769
-cap "divbuf_1/GND" "li_19158_660978#" -141.668
-cap "divbuf_1/GND" "divbuf_1/IN" -169.062
-cap "divbuf_1/GND" "divbuf_1/OUT" 118.833
-cap "divbuf_1/GND" "divbuf_1/OUT" 19.5108
-cap "cp_0/vdd!" "cp_0/vdd!" -8.2
cap "cp_0/vbias" "cp_0/gnd!" 70.4
-cap "cp_0/vdd!" "cp_0/vbias" 6.99153
cap "cp_0/vbias" "cp_0/vdd!" 70.1
-cap "cp_0/vbias" "cp_0/vdd!" 37.925
+cap "cp_0/vdd!" "cp_0/vdd!" -8.2
+cap "cp_0/vdd!" "cp_0/vbias" 6.99153
+cap "cp_0/vdd!" "cp_0/vbias" 37.925
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 8.33333
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 7.5
cap "cp_0/a_1710_n2840#" "w_559500_660830#" 5.5
cap "cp_0/a_1710_n2840#" "cp_0/a_1710_0#" 37.5
cap "cp_0/a_1710_n2840#" "cp_0/a_3060_0#" 14.96
cap "cp_0/a_1710_n2840#" "cp_0/a_3060_0#" 37.2505
-cap "divbuf_1/GND" "divbuf_1/VDD" 203.264
cap "cp_0/vdd!" "cp_0/vdd!" 95.0847
cap "cp_0/a_1710_n2840#" "cp_0/a_3060_0#" 988.637
cap "cp_0/a_3060_0#" "w_559500_660830#" 1004.68
cap "w_559560_661800#" "w_559500_660830#" -34.44
-cap "divbuf_0/GND" "divbuf_0/IN" 10.8621
-cap "divbuf_0/GND" "divbuf_0/OUT" 322.322
+cap "w_559560_661800#" "vdda1" -24.96
cap "cp_0/a_3060_0#" "vdda1" 134.64
cap "cp_0/a_3060_0#" "vdda1" 325.8
-cap "w_559560_661800#" "vdda1" -24.96
-cap "divbuf_0/GND" "divbuf_0/IN" 427.206
-cap "divbuf_0/GND" "divbuf_0/VDD" -52.192
-cap "divbuf_0/GND" "divbuf_0/VDD" -38.98
cap "ashish_1/a_150_n710#" "vssa1" 445.586
cap "ashish_1/a_150_0#" "vssa1" 334.233
cap "ashish_1/a_150_0#" "ashish_1/Gnd" 19.1739
@@ -1684,60 +1556,23 @@
cap "ashish_1/a_n2230_n1430#" "ashish_1/von" 238.75
cap "vssa1" "ashish_1/a_150_n710#" 141.75
cap "ashish_1/a_n2230_n1430#" "vssa1" 273.3
-merge "cp_0/a_1710_n2840#" "cp_0/vbias" -33703.9 0 0 0 0 -1481520 -6252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -46200 -600 58600 -2902 0 0 -47232000 -58080 -994420 -14592 0 0 0 0
+merge "cp_0/a_1710_n2840#" "ro_complete_1/ro_var_extend_0/vdd" -12846.5 0 0 0 0 -3161760 -16923 0 0 15200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -113196 -1592 3900 0 3900 0 -149360 -1220 402300 -10696 0 0 0 0
+merge "ro_complete_1/ro_var_extend_0/vdd" "vdda1"
+merge "vdda1" "cp_0/vbias"
merge "cp_0/vbias" "li_555470_660400#"
merge "li_555470_660400#" "cp_0/vdd!"
merge "cp_0/vdd!" "w_559500_660830#"
merge "w_559500_660830#" "w_559560_661800#"
-merge "w_559560_661800#" "pll_full_0/divbuf_1/VDD"
-merge "pll_full_0/divbuf_1/VDD" "pll_full_0/cp_0/vdd!"
-merge "pll_full_0/cp_0/vdd!" "m4_374062_561532#"
-merge "m4_374062_561532#" "pll_full_0/pd_0/VDD"
-merge "pll_full_0/pd_0/VDD" "pll_full_0/divider_0/w_n140_1520#"
-merge "pll_full_0/divider_0/w_n140_1520#" "pll_full_0/divbuf_0/VDD"
-merge "pll_full_0/divbuf_0/VDD" "ro_complete_1/ro_var_extend_0/vdd"
-merge "ro_complete_1/ro_var_extend_0/vdd" "vdda1"
merge "ro_complete_1/cbank_2/a5" "gpio_analog[14]" -108.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14000 -440 0 0 0 0 0 0 0 0 0 0 0 0
-merge "pd_0/DOWN" "divbuf_4/IN" -2715.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17808 -132 -1414191 -10725 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_4/IN" "li_32886_649070#"
-merge "ashish_1/Gnd" "li_133706_697044#" -23691.2 0 0 0 0 0 0 0 0 0 0 -47200 -1140 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110540 -3048 107822 -2294 72470 -1722 -25806016 -55135 2144270 -19159 -97696 -12732 0 0
+merge "ashish_1/Gnd" "li_133706_697044#" -17034.5 0 0 0 0 0 0 0 0 0 0 -47200 -1140 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -118772 -2308 -52000 -1060 -52000 -1060 -25198340 -44229 -60400 -3050 -92226 -3350 0 0
merge "li_133706_697044#" "ashish_1/a_n2230_n1430#"
-merge "ashish_1/a_n2230_n1430#" "divbuf_0/VDD"
-merge "divbuf_0/VDD" "divbuf_0/OUT"
-merge "divbuf_0/OUT" "divbuf_0/IN"
-merge "divbuf_0/IN" "divbuf_0/GND"
-merge "divbuf_0/GND" "divbuf_1/VDD"
-merge "divbuf_1/VDD" "divbuf_1/GND"
-merge "divbuf_1/GND" "cp_0/gnd!"
-merge "cp_0/gnd!" "pll_full_0/divbuf_1/GND"
-merge "pll_full_0/divbuf_1/GND" "pll_full_0/pd_0/and_pd_0/GND"
-merge "pll_full_0/pd_0/and_pd_0/GND" "pll_full_0/divider_0/prescaler_0/GND"
-merge "pll_full_0/divider_0/prescaler_0/GND" "pll_full_0/divider_0/prescaler_0/tspc_2/gnd!"
-merge "pll_full_0/divider_0/prescaler_0/tspc_2/gnd!" "pll_full_0/divider_0/mc2"
-merge "pll_full_0/divider_0/mc2" "pll_full_0/filter_0/gnd!"
-merge "pll_full_0/filter_0/gnd!" "pll_full_0/filter_0/gnd"
-merge "pll_full_0/filter_0/gnd" "pll_full_0/divbuf_0/GND"
-merge "pll_full_0/divbuf_0/GND" "vssa1"
+merge "ashish_1/a_n2230_n1430#" "cp_0/gnd!"
+merge "cp_0/gnd!" "vssa1"
merge "vssa1" "m3_560230_657890#"
merge "m3_560230_657890#" "m2_560230_657890#"
merge "m2_560230_657890#" "m1_560230_657890#"
merge "m1_560230_657890#" "li_560230_657890#"
-merge "li_560230_657890#" "pd_0/tspc_r_0/D"
-merge "pd_0/tspc_r_0/D" "pd_0/and_pd_0/GND"
-merge "pd_0/and_pd_0/GND" "pd_0/tspc_r_0/VDD"
-merge "pd_0/tspc_r_0/VDD" "pd_0/VDD"
-merge "pd_0/VDD" "pd_0/REF"
-merge "pd_0/REF" "divbuf_5/VDD"
-merge "divbuf_5/VDD" "divbuf_4/VDD"
-merge "divbuf_4/VDD" "m4_33166_649670#"
-merge "m4_33166_649670#" "divbuf_5/OUT"
-merge "divbuf_5/OUT" "pd_0/a_n420_n1430#"
-merge "pd_0/a_n420_n1430#" "divbuf_5/GND"
-merge "divbuf_5/GND" "divbuf_4/GND"
-merge "divbuf_4/GND" "divbuf_4/OUT"
-merge "divbuf_4/OUT" "li_19434_665672#"
-merge "li_19434_665672#" "pll_full_0/VSUBS"
-merge "pll_full_0/VSUBS" "divbuf_3/GND"
+merge "li_560230_657890#" "divbuf_3/GND"
merge "divbuf_3/GND" "ro_complete_1/a_7790_n10640#"
merge "ro_complete_1/a_7790_n10640#" "filter_0/gnd!"
merge "filter_0/gnd!" "filter_0/gnd"
@@ -1757,14 +1592,9 @@
merge "cp_0/out" "io_analog[0]" -6988.98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18960 -860 0 0 -12500000 -15000 0 0 0 0 0 0
merge "divbuf_3/OUT" "io_analog[5]" -28550.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4400 -140 0 0 0 0 -25038010 -30572 -25000000 -30000 -25000000 -30000 0 0
merge "cp_0/down" "io_analog[1]" -9862 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -202260 -3882 -2260 -1722 -1040633 -6232 -12500000 -15000 0 0 0 0 0 0
-merge "pd_0/UP" "divbuf_5/IN" -696.707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5280 -128 -246100 -2144 0 0 0 0 0 0 0 0 0 0
-merge "divbuf_5/IN" "li_32770_653524#"
merge "ashish_1/von" "io_analog[7]" -11658.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12500000 -15000 -1401036 -26026 0 0 0 0
-merge "divbuf_1/OUT" "pd_0/DIV" -129.762 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3120 -200 0 0 -69504 -176 0 0 0 0 0 0 0 0
-merge "pd_0/DIV" "li_19160_659970#"
merge "ashish_1/vop" "io_analog[6]" -28414.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25000000 -30000 -24995350 -30672 -25000000 -30000 0 0
merge "ro_complete_1/cbank_2/gnd!" "m3_31530_200540#" -1411.23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -576800 -3042 -293050 -4580 0 0 0 0
merge "divbuf_3/IN" "ro_complete_1/li_7140_1400#" -1007.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4200 -100 0 0 -207290 -3354 0 0 0 0 0 0 0 0
merge "ro_complete_1/li_7140_1400#" "li_44580_213200#"
merge "filter_0/v" "gpio_noesd[15]" -5579.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9196 -318 -37372 -1840 -2664918 -19524 0 0 0 0 0 0 0 0
-merge "divbuf_1/IN" "li_19158_660978#" 209.656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -395612 -152 422704 0 82482 -253 0 0 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper.gds b/mag/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..7816128
--- /dev/null
+++ b/mag/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 5cf9d1e..b85532d 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1641019647
+timestamp 1641020346
<< nwell >>
rect 279780 330900 279945 332600
rect 279750 330415 279970 330610
@@ -19,20 +19,13 @@
rect 281520 333200 281580 333430
rect 281800 333200 281855 333430
rect 281520 333140 281855 333200
-rect 8903 332725 9154 332959
rect 281520 332948 281645 333140
-rect 8919 332178 9170 332412
-rect 9579 330575 9679 330619
-rect 9579 330503 9586 330575
-rect 9662 330503 9679 330575
-rect 9579 330489 9679 330503
rect 277735 330250 277817 331057
rect 279795 330570 279930 330580
rect 279795 330460 279805 330570
rect 279920 330460 279930 330570
rect 279795 330455 279930 330460
rect 277735 330200 278230 330250
-rect 9682 329990 9691 330039
rect 280115 328945 280340 329175
rect 281520 328880 281630 329110
rect 281830 328885 282095 328910
@@ -41,24 +34,6 @@
rect 281830 328690 281855 328770
rect 282055 328690 282095 328885
rect 281830 328665 282095 328690
-rect 16385 326859 16490 326867
-rect 16385 326778 16393 326859
-rect 16483 326778 16490 326859
-rect 16385 326762 16490 326778
-rect 16374 326355 16508 326365
-rect 16374 326242 16386 326355
-rect 16499 326242 16508 326355
-rect 16374 326230 16508 326242
-rect 16443 324658 16569 324672
-rect 16443 324550 16455 324658
-rect 16560 324550 16569 324658
-rect 16443 324535 16569 324550
-rect 16447 324168 16581 324178
-rect 16447 324055 16459 324168
-rect 16572 324110 16581 324168
-rect 16572 324090 16586 324110
-rect 16572 324055 16581 324090
-rect 16447 324043 16581 324055
rect 12170 108770 12550 108815
rect 12170 108460 12215 108770
rect 12515 108460 12550 108770
@@ -134,16 +109,8 @@
rect 19475 100185 19640 100195
<< viali >>
rect 281580 333200 281800 333430
-rect 9717 332836 9772 332898
-rect 9728 332337 9777 332386
-rect 9586 330503 9662 330575
rect 279805 330460 279920 330570
-rect 9580 329985 9682 330088
rect 281855 328690 282055 328885
-rect 16393 326778 16483 326859
-rect 16386 326242 16499 326355
-rect 16455 324550 16560 324658
-rect 16459 324055 16572 324168
rect 12215 108460 12515 108770
rect 17285 108550 17365 108620
rect 13855 106900 14155 107210
@@ -159,39 +126,11 @@
rect 281530 333200 281580 333430
rect 281800 333200 281855 333430
rect 281530 333140 281855 333200
-rect 8903 332954 9154 332959
-rect 8903 332734 8914 332954
-rect 9144 332907 9154 332954
-rect 9144 332898 9776 332907
-rect 9144 332836 9717 332898
-rect 9772 332836 9776 332898
-rect 9144 332828 9776 332836
-rect 9144 332734 9154 332828
-rect 8903 332725 9154 332734
-rect 8919 332407 9170 332412
-rect 8919 332187 8930 332407
-rect 9160 332393 9170 332407
-rect 9160 332386 9785 332393
-rect 9160 332337 9728 332386
-rect 9777 332337 9785 332386
-rect 9160 332329 9785 332337
-rect 9160 332281 9198 332329
-rect 9160 332187 9170 332281
-rect 8919 332178 9170 332187
rect 287587 331330 288039 331387
rect 287587 331014 287648 331330
rect 287583 331010 287648 331014
rect 287972 331010 288039 331330
rect 287583 330922 288039 331010
-rect 9086 330630 9662 330641
-rect 9086 330518 9098 330630
-rect 9220 330619 9662 330630
-rect 9220 330575 9679 330619
-rect 9220 330518 9586 330575
-rect 9086 330503 9586 330518
-rect 9662 330503 9679 330575
-rect 9086 330498 9679 330503
-rect 9579 330489 9679 330498
rect 279795 330570 279930 330580
rect 279795 330460 279805 330570
rect 279920 330460 279930 330570
@@ -201,14 +140,7 @@
rect 282430 330330 283580 330450
rect 283485 330240 283580 330330
rect 283850 330240 283965 330465
-rect 9059 330088 9691 330114
rect 283485 330100 283965 330240
-rect 9059 330083 9580 330088
-rect 9059 329943 9075 330083
-rect 9220 329985 9580 330083
-rect 9682 329985 9691 330088
-rect 9220 329943 9691 329985
-rect 9059 329923 9691 329943
rect 287583 329371 288034 330922
rect 287582 329178 288034 329371
rect 280115 328945 280340 329175
@@ -220,47 +152,6 @@
rect 287582 328486 287634 328768
rect 287946 328486 288033 328768
rect 287582 328425 288033 328486
-rect 13950 327856 14985 327860
-rect 15950 327856 16488 327867
-rect 13675 327852 16488 327856
-rect 13675 327849 16493 327852
-rect 13522 327806 16493 327849
-rect 13288 327777 16493 327806
-rect 13522 327773 16493 327777
-rect 13522 327772 13699 327773
-rect 13950 327770 14985 327773
-rect 15950 327766 16493 327773
-rect 15953 327698 16151 327708
-rect 13655 327691 14035 327698
-rect 13275 327690 14035 327691
-rect 14845 327690 16151 327698
-rect 13275 327614 16151 327690
-rect 13655 327599 16151 327614
-rect 13920 327585 14950 327599
-rect 15953 324851 16151 327599
-rect 16384 326859 16493 327766
-rect 16384 326844 16393 326859
-rect 16385 326778 16393 326844
-rect 16483 326844 16493 326859
-rect 16483 326778 16490 326844
-rect 16385 326762 16490 326778
-rect 16374 326355 16508 326365
-rect 16374 326242 16386 326355
-rect 16499 326242 16508 326355
-rect 16374 326230 16508 326242
-rect 15953 324758 16154 324851
-rect 15954 324670 16154 324758
-rect 16443 324670 16569 324672
-rect 15954 324658 16569 324670
-rect 15954 324550 16455 324658
-rect 16560 324550 16569 324658
-rect 15954 324535 16569 324550
-rect 15954 324534 16558 324535
-rect 15954 324527 16154 324534
-rect 16447 324168 16581 324178
-rect 16447 324055 16459 324168
-rect 16572 324055 16581 324168
-rect 16447 324043 16581 324055
rect 17275 109280 17450 109305
rect 17275 109190 17315 109280
rect 17405 109190 17450 109280
@@ -308,17 +199,11 @@
rect 30741 65661 31026 65799
<< via1 >>
rect 281580 333200 281800 333430
-rect 8914 332734 9144 332954
-rect 8930 332187 9160 332407
rect 287648 331010 287972 331330
-rect 9098 330518 9220 330630
rect 279805 330460 279920 330570
rect 283580 330240 283850 330465
-rect 9075 329943 9220 330083
rect 281855 328690 282055 328885
rect 287634 328486 287946 328768
-rect 16386 326242 16499 326355
-rect 16459 324055 16572 324168
rect 17315 109190 17405 109280
rect 12215 108460 12515 108770
rect 13855 106900 14155 107210
@@ -368,52 +253,26 @@
rect 281420 333200 281580 333430
rect 281800 333200 282100 333430
rect 281420 333090 282100 333200
-rect 8903 332954 9154 332959
-rect 8903 332734 8914 332954
-rect 9144 332734 9154 332954
-rect 8903 332725 9154 332734
-rect 8919 332407 9170 332412
-rect 8919 332187 8930 332407
-rect 9160 332187 9170 332407
-rect 8919 332178 9170 332187
rect 287541 331330 288077 334512
rect 287541 331251 287648 331330
rect 287554 331010 287648 331251
rect 287972 331251 288077 331330
rect 287972 331010 288068 331251
rect 287554 330971 288068 331010
-rect 8110 330719 8410 330735
-rect 3062 330630 9279 330719
-rect 3062 330518 9098 330630
-rect 9220 330518 9279 330630
rect 283420 330647 284290 330675
rect 283420 330628 288707 330647
rect 288781 330628 289157 340399
-rect 3062 330480 9279 330518
-rect 3062 330467 8155 330480
-rect 8355 330467 9279 330480
rect 279795 330570 279930 330580
-rect 3075 329794 3531 330467
rect 279795 330460 279805 330570
rect 279920 330460 279930 330570
rect 279795 330455 279930 330460
rect 283420 330465 289157 330628
rect 283420 330240 283580 330465
rect 283850 330240 289157 330465
-rect 8050 330107 8440 330115
-rect 7484 330083 9249 330107
-rect 7484 329943 9075 330083
-rect 9220 329943 9249 330083
rect 283420 329950 289157 330240
-rect 7484 329853 9249 329943
rect 283657 329930 289157 329950
rect 288542 329919 289157 329930
rect 288781 329899 289157 329919
-rect 3078 314810 3513 329794
-rect 7488 329122 7805 329853
-rect 8050 329840 8440 329853
-rect 7483 329061 7805 329122
-rect 7483 327173 7799 329061
rect 280115 328945 280340 329175
rect 282219 328950 288079 328957
rect 281650 328885 288079 328950
@@ -424,38 +283,13 @@
rect 287946 328486 288079 328768
rect 281650 328320 288079 328486
rect 281650 328316 282320 328320
-rect 10817 327955 11059 327967
-rect 10817 327735 10840 327955
-rect 11043 327886 11059 327955
-rect 11043 327873 11576 327886
-rect 11043 327836 11736 327873
-rect 11043 327786 11576 327836
-rect 11043 327735 11059 327786
-rect 10817 327715 11059 327735
-rect 8915 327173 10280 327210
-rect 7483 327052 11393 327173
-rect 7483 327046 11577 327052
-rect 7483 326945 11747 327046
-rect 7483 326934 11577 326945
-rect 7483 326844 11393 326934
-rect 8915 326835 10280 326844
-rect 16374 326355 16508 326365
-rect 16374 326242 16386 326355
-rect 16499 326242 16508 326355
-rect 16374 326230 16508 326242
-rect 16447 324168 16581 324178
-rect 16447 324055 16459 324168
-rect 16572 324055 16581 324168
-rect 16447 324043 16581 324055
rect 934 255988 1537 255995
-rect 3078 255988 3513 311485
-rect 934 255984 3513 255988
-rect 365 255863 3513 255984
+rect 934 255984 2250 255988
+rect 365 255863 2250 255984
rect 365 255697 420 255863
-rect 591 255697 3513 255863
-rect 365 255610 3513 255697
+rect 591 255697 2250 255863
+rect 365 255610 2250 255697
rect 365 255608 968 255610
-rect 3078 255606 3513 255610
rect 17295 109280 17425 109295
rect 17295 109190 17315 109280
rect 17405 109190 17425 109280
@@ -1011,12 +845,7 @@
rect 233768 350323 234259 350794
rect 284173 350154 284687 350660
rect 290370 340501 290604 340740
-rect 8914 332734 9144 332954
-rect 8930 332187 9160 332407
rect 279805 330460 279920 330570
-rect 10840 327735 11043 327955
-rect 16386 326242 16499 326355
-rect 16459 324055 16572 324168
rect 420 255697 591 255863
rect 17315 109190 17405 109280
rect 12215 108460 12515 108770
@@ -1057,8 +886,7 @@
rect 65405 348720 67540 349020
rect 6445 347626 9402 348356
rect 6445 347110 7065 347626
-rect -400 341845 850 342621
-rect 6402 342590 7065 347110
+rect 6402 346960 7065 347110
rect 65405 346645 66050 348720
rect 67375 347885 67455 348720
rect 83010 348235 84260 351150
@@ -1068,136 +896,43 @@
rect 67345 347765 67470 347775
rect 109085 347260 109985 351150
rect 159822 350613 160787 351150
-rect 206750 351135 208230 351150
-rect 233320 350921 234785 351150
+rect 206750 351135 208840 351150
rect 159818 350464 160787 350613
-rect 233307 350794 234788 350921
rect 65360 345785 66050 346645
rect 108975 346705 110630 347260
rect 159818 346994 160786 350464
-rect 233307 350323 233768 350794
-rect 234259 350323 234788 350794
-rect 233307 350205 234788 350323
-rect 260738 350454 261891 351170
-rect 283297 351150 285797 352400
-rect 260738 349780 260950 350454
-rect 261694 349780 261891 350454
-rect 283705 350660 285250 351150
-rect 283705 350154 284173 350660
-rect 284687 350154 285250 350660
-rect 283705 349894 285250 350154
-rect 260738 349617 261891 349780
rect 159818 346862 160787 346994
rect 108975 346400 109335 346705
rect 109675 346400 110630 346705
-rect 50490 345110 54100 345220
-rect 48795 345094 54100 345110
-rect 8064 344205 54100 345094
-rect 8064 344200 52465 344205
+rect -400 341845 850 342621
rect -400 340357 1915 341845
rect -400 340121 850 340357
-rect 4571 338645 5203 339265
-rect 6402 339250 7065 339265
-rect 6390 338645 7065 339250
-rect 4600 337550 5185 338645
-rect 6390 337550 6975 338645
-rect 4571 325688 5203 337550
-rect 6390 337150 7065 337550
-rect 6402 325910 7065 337150
-rect 8785 336760 9200 344200
-rect 48795 344070 52465 344200
-rect 8785 336430 9230 336760
-rect 8795 335705 9230 336430
-rect 8785 335520 9230 335705
-rect 7356 332724 7928 333880
-rect 7356 332399 7452 332724
-rect 7784 332694 7928 332724
-rect 8785 332954 9200 335520
-rect 8785 332734 8914 332954
-rect 9144 332734 9200 332954
-rect 8785 332694 9200 332734
-rect 7784 332690 8155 332694
-rect 8355 332690 9592 332694
-rect 7784 332470 9592 332690
-rect 7784 332465 8155 332470
-rect 8355 332465 9592 332470
-rect 7784 332399 7928 332465
-rect 7356 330429 7928 332399
-rect 7356 330104 7499 330429
-rect 7831 330417 7928 330429
-rect 8523 332407 9198 332465
-rect 8523 332187 8930 332407
-rect 9160 332187 9198 332407
-rect 8523 332131 9198 332187
-rect 8523 332114 9090 332131
-rect 8523 330417 8903 332114
-rect 7831 330415 8155 330417
-rect 8355 330415 9526 330417
-rect 7831 330104 9526 330415
-rect 7356 329986 9526 330104
-rect 7356 325910 7928 329986
-rect 8020 329980 8395 329986
-rect 8523 328260 8903 329986
-rect 8523 328055 9130 328260
-rect 8523 327991 10320 328055
-rect 8523 327955 11257 327991
-rect 8523 327735 10840 327955
-rect 11043 327735 11257 327955
-rect 8523 327682 11257 327735
-rect 8955 327680 10320 327682
-rect 15513 326686 15774 326703
-rect 14845 326455 15203 326477
-rect 14790 326362 15203 326455
-rect 15513 326473 15536 326686
-rect 15752 326633 15774 326686
-rect 15752 326491 16381 326633
-rect 15752 326473 15774 326491
-rect 15513 326454 15774 326473
-rect 16374 326363 16508 326365
-rect 15532 326362 16508 326363
-rect 14790 326355 16508 326362
-rect 14790 326242 16386 326355
-rect 16499 326242 16508 326355
-rect 14790 326230 16508 326242
-rect 14790 326205 16492 326230
-rect 14790 326204 15916 326205
-rect 14790 326143 15203 326204
-rect 8925 325910 10290 325915
-rect 14790 325910 15170 326143
rect -400 321921 830 324321
-rect 4649 324224 5099 325688
-rect 6370 325565 15170 325910
-rect 6370 325543 15150 325565
-rect 4649 324213 5998 324224
-rect 7356 324213 7928 325543
-rect 8925 325540 10290 325543
-rect 13910 325530 15150 325543
-rect 15558 324520 15819 324537
-rect 15558 324307 15581 324520
-rect 15797 324467 15819 324520
-rect 15797 324466 15925 324467
-rect 16061 324466 16446 324467
-rect 15797 324325 16446 324466
-rect 15797 324307 15819 324325
-rect 16201 324324 16446 324325
-rect 15558 324288 15819 324307
-rect 13825 324213 15025 324245
-rect 4649 324177 15456 324213
-rect 16447 324177 16581 324178
-rect 4649 324168 16581 324177
-rect 4649 324055 16459 324168
-rect 16572 324055 16581 324168
-rect 4649 324043 16581 324055
-rect 4649 324018 16565 324043
-rect 4649 324003 16475 324018
-rect 4649 323988 15456 324003
-rect 4649 323954 5998 323988
-rect 7356 322125 7928 323988
-rect 13825 323980 15025 323988
rect 65360 322965 66010 345785
rect 108975 342720 110630 346400
rect 159822 345785 160787 346862
rect 108865 331960 110740 342720
+rect 65205 322855 66155 322965
+rect 65205 322180 65275 322855
+rect 66080 322180 66155 322855
+rect 65205 322080 66155 322180
+rect -400 316921 830 319321
+rect 108960 311925 109965 331960
+rect 207985 324315 208840 351135
+rect 233320 350921 234785 351150
+rect 233307 350794 234788 350921
+rect 233307 350323 233768 350794
+rect 234259 350323 234788 350794
+rect 233307 350205 234788 350323
+rect 260738 350249 261891 351170
+rect 283297 351150 285797 352400
+rect 260738 349575 260950 350249
+rect 261694 349575 261891 350249
+rect 283705 350660 285250 351150
+rect 283705 350154 284173 350660
+rect 284687 350154 285250 350660
+rect 283705 349894 285250 350154
+rect 260738 349412 261891 349575
rect 291150 341079 292400 341492
rect 290829 341063 292400 341079
rect 290310 340740 292400 341063
@@ -1206,12 +941,6 @@
rect 290310 340216 292400 340501
rect 290829 340215 292400 340216
rect 291150 338992 292400 340215
-rect 65205 322855 66155 322965
-rect 65205 322180 65275 322855
-rect 66080 322180 66155 322855
-rect 65205 322080 66155 322180
-rect -400 316921 830 319321
-rect 108960 311925 109965 331960
rect 279750 330570 279970 330610
rect 279750 330460 279805 330570
rect 279920 330460 279970 330570
@@ -1244,47 +973,16 @@
rect -400 252810 240 252866
rect 63260 242820 66880 287115
rect 91030 286895 110250 287115
-rect 184688 283237 184951 283260
-rect 184688 283036 184709 283237
-rect 184928 283200 184951 283237
-rect 184928 283064 186757 283200
-rect 184928 283036 184951 283064
-rect 184688 283020 184951 283036
rect 287030 277158 289600 277160
rect 291170 277158 292400 277681
rect 287030 276940 292400 277158
-rect 184716 276285 184979 276308
-rect 184716 276084 184737 276285
-rect 184956 276248 184979 276285
-rect 184956 276112 185006 276248
-rect 184956 276084 184979 276112
-rect 184716 276068 184979 276084
rect 287030 275760 287240 276940
rect 288470 275760 292400 276940
rect 287030 275538 292400 275760
rect 287030 275530 289600 275538
rect 287030 275515 287515 275530
rect 291170 275281 292400 275538
-rect 184758 275213 185021 275236
-rect 184758 275012 184779 275213
-rect 184998 275176 185021 275213
-rect 184998 275040 185048 275176
-rect 184998 275012 185021 275040
-rect 184758 274996 185021 275012
-rect 184751 270464 193650 270512
-rect 195391 270464 195815 271089
-rect 184751 270429 195834 270464
-rect 184751 270228 184785 270429
-rect 185004 270228 195834 270429
rect 291170 270281 292400 272681
-rect 184751 270175 195834 270228
-rect 193400 270166 195834 270175
-rect 184745 269276 185008 269299
-rect 184745 269243 184766 269276
-rect 184722 269075 184766 269243
-rect 184985 269243 185008 269276
-rect 184985 269075 186569 269243
-rect 184722 269025 186569 269075
rect 291760 250025 292400 250081
rect 291760 249434 292400 249490
rect 291760 248843 292400 248899
@@ -1556,23 +1254,11 @@
<< via3 >>
rect 60845 348965 61435 349520
rect 67355 347775 67465 347875
-rect 260950 349780 261694 350454
rect 109335 346400 109675 346705
-rect 7452 332399 7784 332724
-rect 8914 332734 9144 332954
-rect 7499 330104 7831 330429
-rect 8930 332187 9160 332407
-rect 10840 327735 11043 327955
-rect 15536 326473 15752 326686
-rect 15581 324307 15797 324520
rect 65275 322180 66080 322855
+rect 260950 349575 261694 350249
rect 279805 330460 279920 330570
-rect 184709 283036 184928 283237
-rect 184737 276084 184956 276285
rect 287240 275760 288470 276940
-rect 184779 275012 184998 275213
-rect 184785 270228 185004 270429
-rect 184766 269075 184985 269276
rect 21240 116470 21700 116840
rect 21375 112115 21835 112485
rect 15840 101990 16080 102210
@@ -1618,29 +1304,15 @@
rect 159822 350613 160787 351150
rect 159818 350464 160787 350613
rect 159818 346994 160786 350464
-rect 260905 350454 261730 350495
-rect 260905 349780 260950 350454
-rect 261694 349780 261730 350454
-rect 260905 349735 261730 349780
+rect 260905 350249 261730 350290
+rect 260905 349575 260950 350249
+rect 261694 349575 261730 350249
+rect 260905 349530 261730 349575
rect 159818 346862 160787 346994
rect 109085 346400 109335 346705
rect 109675 346400 109985 346705
rect 109085 346260 109985 346400
rect 159822 345785 160787 346862
-rect 50490 345110 54100 345220
-rect 48795 345094 54100 345110
-rect 8064 344205 54100 345094
-rect 8064 344200 52465 344205
-rect 8785 340140 9200 344200
-rect 48795 344070 52465 344200
-rect 49850 340150 52465 340220
-rect 49850 340140 54100 340150
-rect 8305 339255 54100 340140
-rect 8785 336760 9200 339255
-rect 8785 336430 9230 336760
-rect 11916 336695 12573 339255
-rect 42361 336960 43104 339255
-rect 49850 339140 54100 339255
rect 57900 340140 64035 340165
rect 81510 340140 86430 340205
rect 264440 340140 265420 349865
@@ -1650,65 +1322,6 @@
rect 110740 339255 281150 340140
rect 57900 339145 64035 339255
rect 81510 339245 86430 339255
-rect 50490 339135 54100 339140
-rect 8795 335705 9230 336430
-rect 8785 335520 9230 335705
-rect 7356 332727 7928 333880
-rect 7356 332724 7456 332727
-rect 7356 332399 7452 332724
-rect 7784 332399 7928 332727
-rect 8785 332954 9200 335520
-rect 11850 335480 12635 336695
-rect 11916 333580 12573 335480
-rect 42315 335420 43110 336960
-rect 12119 333111 12315 333580
-rect 8785 332734 8914 332954
-rect 9144 332734 9200 332954
-rect 8785 332670 9200 332734
-rect 8811 332487 9198 332489
-rect 8581 332481 9198 332487
-rect 7356 330432 7928 332399
-rect 7356 330429 7503 330432
-rect 7356 330104 7499 330429
-rect 7831 330104 7928 330432
-rect 7356 322125 7928 330104
-rect 8523 332407 9198 332481
-rect 8523 332187 8930 332407
-rect 9160 332187 9198 332407
-rect 8523 332131 9198 332187
-rect 8523 332114 9090 332131
-rect 8523 328260 8903 332114
-rect 42354 331535 43104 335420
-rect 28930 331186 43104 331535
-rect 29298 330763 29546 331186
-rect 42354 331116 43104 331186
-rect 42354 329056 43097 331116
-rect 11641 328640 43097 329056
-rect 8523 328055 9130 328260
-rect 11943 328097 12144 328640
-rect 8523 327991 10320 328055
-rect 8523 327955 11257 327991
-rect 8523 327735 10840 327955
-rect 11043 327735 11257 327955
-rect 8523 327682 11257 327735
-rect 8955 327680 10320 327682
-rect 13230 327280 13355 327570
-rect 13230 327215 13800 327280
-rect 13230 327105 13520 327215
-rect 13350 326970 13520 327105
-rect 13775 326970 13800 327215
-rect 16542 327028 16744 328640
-rect 42354 328596 43097 328640
-rect 13350 326955 13800 326970
-rect 15513 326686 15774 326703
-rect 15513 326473 15536 326686
-rect 15752 326473 15774 326686
-rect 15513 326454 15774 326473
-rect 16583 324835 16679 325959
-rect 15558 324520 15819 324537
-rect 15558 324307 15581 324520
-rect 15797 324307 15819 324520
-rect 15558 324288 15819 324307
rect 65205 322855 66155 322965
rect 65205 322180 65275 322855
rect 66080 322180 66155 322855
@@ -1723,61 +1336,20 @@
rect 280115 328995 280150 329145
rect 280295 328995 280340 329145
rect 280115 328945 280340 328995
-rect 5765 305475 278610 306360
+rect 52355 305475 278610 306360
rect 264440 286700 265420 305475
-rect 6535 285815 279380 286700
+rect 52355 285815 279380 286700
rect 119925 276675 121190 285815
-rect 183782 276856 184320 285815
-rect 187007 283601 187153 285815
-rect 184688 283237 184951 283260
-rect 184688 283036 184709 283237
-rect 184928 283036 184951 283237
-rect 184688 283020 184951 283036
-rect 187031 280766 187104 282515
+rect 183782 285655 184320 285815
+rect 187007 285655 187153 285815
rect 264440 277090 265420 285815
rect 264440 277085 278300 277090
rect 264440 276940 288920 277085
-rect 183782 276788 186966 276856
-rect 183782 274349 184320 276788
-rect 184716 276285 184979 276308
-rect 184716 276265 184737 276285
-rect 184714 276098 184737 276265
-rect 184716 276084 184737 276098
-rect 184956 276265 184979 276285
-rect 186170 276265 186258 276329
-rect 184956 276098 186258 276265
-rect 184956 276084 184979 276098
-rect 184716 276068 184979 276084
-rect 186170 275268 186258 276098
-rect 188431 275268 188519 276309
rect 264440 275760 287240 276940
rect 288470 275760 288920 276940
rect 264440 275575 288920 275760
rect 264440 275550 285870 275575
rect 264440 275450 278280 275550
-rect 184758 275213 185021 275236
-rect 184758 275012 184779 275213
-rect 184998 275012 185021 275213
-rect 186170 275202 188795 275268
-rect 186179 275191 188795 275202
-rect 184758 274996 185021 275012
-rect 187209 274879 187322 275191
-rect 188431 275182 188519 275191
-rect 183716 274285 184320 274349
-rect 183716 274270 187212 274285
-rect 183716 274139 187214 274270
-rect 183685 274095 187214 274139
-rect 183685 269646 184340 274095
-rect 184764 270429 185027 270452
-rect 184764 270228 184785 270429
-rect 185004 270228 185027 270429
-rect 184764 270212 185027 270228
-rect 183685 269553 186779 269646
-rect 183685 269340 184340 269553
-rect 184745 269276 185008 269299
-rect 184745 269075 184766 269276
-rect 184985 269075 185008 269276
-rect 184745 269059 185008 269075
rect 21075 116840 22005 116975
rect 21075 116470 21240 116840
rect 21700 116470 22005 116840
@@ -1799,25 +1371,10 @@
rect 264440 1585 265420 70705
<< via4 >>
rect 83250 348410 84065 349280
-rect 260950 349780 261694 350454
+rect 260950 349575 261694 350249
rect 109335 346400 109675 346705
-rect 7456 332724 7784 332727
-rect 7456 332402 7784 332724
-rect 8914 332734 9144 332954
-rect 7503 330429 7831 330432
-rect 7503 330107 7831 330429
-rect 8930 332187 9160 332407
-rect 10840 327735 11043 327955
-rect 13520 326970 13775 327215
-rect 15536 326473 15752 326686
-rect 15581 324307 15797 324520
rect 65275 322180 66080 322855
rect 280150 328995 280295 329145
-rect 184709 283036 184928 283237
-rect 184737 276084 184956 276285
-rect 184779 275012 184998 275213
-rect 184785 270228 185004 270429
-rect 184766 269075 184985 269276
rect 30312 55313 30585 55602
<< metal5 >>
rect 82797 351150 85297 352400
@@ -1834,74 +1391,17 @@
rect 159822 350613 160787 351150
rect 159818 350464 160787 350613
rect 159818 346994 160786 350464
-rect 260905 350454 261730 350495
-rect 260905 349780 260950 350454
-rect 261694 349780 261730 350454
-rect 260905 349735 261730 349780
+rect 260905 350249 261730 350290
+rect 260905 349575 260950 350249
+rect 261694 349575 261730 350249
+rect 260905 349530 261730 349575
rect 159818 346862 160787 346994
rect 109085 346400 109335 346705
rect 109675 346400 109985 346705
rect 109085 346260 109985 346400
rect 159822 345785 160787 346862
-rect 50490 345110 54100 345220
-rect 48795 345094 54100 345110
-rect 8064 344205 54100 345094
-rect 8064 344200 52465 344205
-rect 8785 336760 9200 344200
-rect 48795 344070 52465 344200
-rect 260945 343525 261675 349735
+rect 260945 343525 261675 349530
rect 260940 338325 261680 343525
-rect 8785 336430 9230 336760
-rect 8795 335705 9230 336430
-rect 8785 335520 9230 335705
-rect 7356 332727 7928 333880
-rect 7356 332402 7456 332727
-rect 7784 332402 7928 332727
-rect 8785 332954 9200 335520
-rect 8785 332734 8914 332954
-rect 9144 332734 9200 332954
-rect 8785 332670 9200 332734
-rect 8811 332487 9198 332489
-rect 8581 332481 9198 332487
-rect 7356 330432 7928 332402
-rect 7356 330107 7503 330432
-rect 7831 330107 7928 330432
-rect 7356 322960 7928 330107
-rect 8523 332407 9198 332481
-rect 8523 332187 8930 332407
-rect 9160 332187 9198 332407
-rect 8523 332131 9198 332187
-rect 8523 332114 9090 332131
-rect 8523 328260 8903 332114
-rect 8523 328055 9130 328260
-rect 8523 327991 10320 328055
-rect 8523 327955 11257 327991
-rect 8523 327735 10840 327955
-rect 11043 327735 11257 327955
-rect 8523 327682 11257 327735
-rect 8955 327680 10320 327682
-rect 13475 327215 13845 327300
-rect 13475 326970 13520 327215
-rect 13775 326970 13845 327215
-rect 13475 326395 13845 326970
-rect 12055 326085 13845 326395
-rect 12051 326050 13845 326085
-rect 15363 326686 15924 329096
-rect 15363 326473 15536 326686
-rect 15752 326473 15924 326686
-rect 12051 326040 13830 326050
-rect 12051 322967 12500 326040
-rect 15363 324618 15924 326473
-rect 15363 324520 15925 324618
-rect 15363 324307 15581 324520
-rect 15797 324307 15925 324520
-rect 15363 324195 15925 324307
-rect 15363 323565 15924 324195
-rect 15340 323395 15924 323565
-rect 15340 322990 15900 323395
-rect 49175 323065 52465 323135
-rect 15340 322967 15924 322990
-rect 49175 322967 54100 323065
rect 260945 322967 261675 338325
rect 280115 329145 280340 329175
rect 280115 328995 280150 329145
@@ -1909,8 +1409,6 @@
rect 280115 328945 280340 328995
rect 280145 322970 280310 328945
rect 280129 322967 280705 322970
-rect 8729 322960 54100 322967
-rect 7351 322091 54100 322960
rect 57900 322960 103850 322967
rect 115760 322965 263710 322967
rect 266950 322965 281562 322967
@@ -1919,42 +1417,24 @@
rect 57900 322180 65275 322855
rect 66080 322180 281562 322855
rect 57900 322091 281562 322180
-rect 7351 322044 9000 322091
-rect 49175 322055 54100 322091
rect 65205 322080 66155 322091
-rect 50885 322050 54100 322055
rect 260945 307590 261675 322091
rect 263640 322085 267055 322091
rect 260920 303700 261700 307590
rect 260945 292409 261675 303700
-rect 6100 292405 263710 292409
+rect 52355 292405 263710 292409
rect 266950 292405 289699 292409
-rect 6100 291076 289699 292405
+rect 52355 291076 289699 292405
rect 260945 288885 261675 291076
rect 262275 291020 269150 291076
rect 260935 288345 261675 288885
rect 260935 284665 261670 288345
-rect 184604 283237 185087 284436
rect 260935 284350 261675 284665
-rect 184604 283036 184709 283237
-rect 184928 283036 185087 283237
-rect 184604 276285 185087 283036
-rect 184604 276084 184737 276285
-rect 184956 276084 185087 276285
-rect 184604 275213 185087 276084
-rect 184604 275012 184779 275213
-rect 184998 275012 185087 275213
-rect 184604 270429 185087 275012
-rect 184604 270228 184785 270429
-rect 185004 270228 185087 270429
-rect 184604 269276 185087 270228
-rect 184604 269075 184766 269276
-rect 184985 269075 185087 269276
rect 106600 259409 107895 267480
-rect 184604 259409 185087 269075
+rect 184604 259409 185087 261460
rect 260945 259409 261675 284350
rect 262920 259409 269795 259455
-rect 4860 258076 288459 259409
+rect 52355 258076 288459 259409
rect 260945 92755 261675 258076
rect 262920 258070 269795 258076
rect 260945 71965 261675 91685
@@ -1988,30 +1468,6 @@
timestamp 1641018626
transform 1 0 15975 0 1 107450
box -57 -5330 4455 1440
-use pll_full pll_full_0
-timestamp 1641018938
-transform 1 0 191860 0 1 271011
-box -5415 -2690 26430 12835
-use pd pd_0
-timestamp 1641018908
-transform 1 0 11833 0 1 327448
-box -215 -855 1685 810
-use divbuf divbuf_0
-timestamp 1641017053
-transform 1 0 9942 0 1 332863
-box -460 -1085 31200 495
-use divbuf divbuf_1
-timestamp 1641017053
-transform 1 0 9851 0 1 330509
-box -460 -1085 31200 495
-use divbuf divbuf_5
-timestamp 1641017053
-transform 1 0 16668 0 1 326792
-box -460 -1085 31200 495
-use divbuf divbuf_4
-timestamp 1641017053
-transform 1 0 16746 0 1 324604
-box -460 -1085 31200 495
use ashish ashish_1
timestamp 1640990489
transform 1 0 67480 0 1 347875
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 2e8b1ed..fae58c5 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1481 +106,834 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-C0 divbuf_4/OUT4 io_analog[5] 1.11fF
-C1 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF
-C2 io_analog[6] io_clamp_low[2] 0.53fF
-C3 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C4 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
-C5 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF
-C6 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF
-C7 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF
-C8 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C9 ro_complete_0/cbank_1/switch_4/vin divbuf_4/IN 1.30fF
-C10 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF
-C11 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF
-C12 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C13 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C14 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C15 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF
-C16 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C17 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C18 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
-C19 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF
-C20 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/a3 0.15fF
-C21 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF
-C22 ro_complete_0/cbank_2/switch_3/vin gpio_analog[13] 0.14fF
-C23 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C24 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C25 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C26 gpio_noesd[15] gpio_analog[17] 5.80fF
-C27 filter_0/a_4216_n5230# gpio_noesd[15] 0.19fF
-C28 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C29 gpio_analog[14] ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C30 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C31 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF
-C32 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C33 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
-C34 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C35 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C36 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C37 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C38 gpio_analog[13] ro_complete_0/cbank_2/v 0.05fF
-C39 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C40 pd_0/R pd_0/and_pd_0/Out1 0.33fF
-C41 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
-C42 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C43 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/Out 0.11fF
-C44 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF
-C45 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C46 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C47 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z1 1.07fF
-C48 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C49 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF
-C50 ro_complete_0/a2 divbuf_4/IN 0.05fF
-C51 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C52 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF
-C53 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF
-C54 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
-C55 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
-C56 gpio_analog[14] gpio_analog[15] 0.68fF
-C57 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF
-C58 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF
-C59 ro_complete_0/cbank_1/switch_0/vin divbuf_4/IN 1.45fF
-C60 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C61 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C62 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF
-C63 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C64 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
-C65 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF
-C66 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C67 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C68 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C69 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C70 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF
-C71 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
-C72 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C73 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C74 divbuf_4/a_492_n240# io_analog[5] 0.00fF
-C75 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF
-C76 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF
-C77 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF
-C78 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C79 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF
-C80 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF
-C81 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C82 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C83 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C84 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF
-C85 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF
-C86 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C87 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF
-C88 ro_complete_0/a3 gpio_analog[16] 0.77fF
-C89 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C90 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C91 ro_complete_0/cbank_1/switch_5/vin divbuf_4/IN 1.30fF
-C92 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF
-C93 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C94 io_analog[5] io_clamp_low[1] 0.53fF
-C95 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C96 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF
-C97 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
-C98 ro_complete_0/a2 ro_complete_0/a3 0.49fF
-C99 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C100 divbuf_4/IN io_analog[5] 0.34fF
-C101 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF
-C102 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C103 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C104 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF
-C105 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF
-C106 pd_0/UP divbuf_1/a_492_n240# 0.13fF
-C107 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C108 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C109 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
-C110 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/A 0.23fF
-C111 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF
-C112 ro_complete_0/a2 gpio_analog[17] 0.69fF
-C113 gpio_analog[14] ro_complete_0/cbank_2/v 0.08fF
-C114 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF
-C115 cp_0/a_1710_0# io_analog[0] 0.84fF
-C116 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF
-C117 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF
-C118 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C119 divbuf_4/IN divbuf_4/a_492_n240# 0.13fF
-C120 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF
-C121 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C122 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C123 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C124 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF
-C125 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
-C126 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C127 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C128 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF
-C129 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF
-C130 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF
-C131 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C132 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C133 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C134 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF
-C135 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C136 gpio_analog[14] vssd1 0.25fF
-C137 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C138 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF
-C139 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C140 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF
-C141 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF
-C142 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C143 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C144 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
-C145 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C146 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C147 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF
-C148 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C149 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF
-C150 ashish_0/a_150_0# ashish_0/a_150_n710# 6.31fF
-C151 pd_0/DIV divbuf_2/OUT3 0.26fF
-C152 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF
-C153 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
-C154 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
-C155 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF
-C156 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C157 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF
-C158 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF
-C159 cp_0/a_1710_0# io_analog[1] 0.32fF
-C160 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
-C161 ro_complete_0/a2 ro_complete_0/a4 0.49fF
-C162 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF
-C163 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
-C164 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
-C165 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C166 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF
-C167 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF
-C168 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C169 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C170 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
-C171 ro_complete_0/a4 ro_complete_0/cbank_1/switch_0/vin 0.15fF
-C172 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C173 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C174 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
-C175 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF
-C176 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF
-C177 ro_complete_0/a3 divbuf_4/IN 0.05fF
-C178 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C179 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF
-C180 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF
-C181 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF
-C182 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C183 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF
-C184 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C185 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF
-C186 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF
-C187 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
-C188 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C189 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF
-C190 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C191 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C192 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C193 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C194 ashish_0/a_150_n710# io_analog[7] 4.33fF
-C195 ashish_0/a_150_0# io_analog[6] 4.44fF
-C196 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF
-C197 pd_0/DIV divbuf_2/OUT5 43.38fF
-C198 io_clamp_low[0] io_analog[4] 0.53fF
-C199 pd_0/DOWN pd_0/R 0.38fF
-C200 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
-C201 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
-C202 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
-C203 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C204 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF
-C205 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF
-C206 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF
-C207 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF
-C208 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
-C209 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
-C210 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
-C211 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C212 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF
-C213 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF
-C214 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C215 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF
-C216 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF
-C217 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C218 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF
-C219 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C220 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C221 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C222 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF
-C223 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
-C224 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
-C225 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C226 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C227 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C228 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C229 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF
-C230 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C231 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C232 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C233 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF
-C234 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
-C235 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C236 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C237 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF
-C238 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF
-C239 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF
-C240 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C241 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF
-C242 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C243 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF
-C244 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C245 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C246 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C247 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C248 io_analog[7] io_analog[6] 13.31fF
-C249 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C250 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF
-C251 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF
-C252 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF
-C253 ro_complete_0/a4 divbuf_4/IN 0.05fF
-C254 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C255 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C256 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C257 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C258 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
-C259 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
-C260 gpio_analog[14] gpio_analog[16] 0.57fF
-C261 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C262 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF
-C263 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF
-C264 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF
-C265 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF
-C266 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C267 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C268 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C269 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
-C270 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
-C271 ro_complete_0/a2 gpio_analog[14] 0.56fF
-C272 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF
-C273 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
-C274 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
-C275 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF
-C276 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C277 gpio_noesd[15] gpio_analog[15] 11.27fF
-C278 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C279 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C280 pd_0/UP divbuf_1/OUT5 0.00fF
-C281 gpio_analog[14] ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C282 divbuf_4/OUT3 io_analog[5] 0.26fF
-C283 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
-C284 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
-C285 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF
-C286 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF
-C287 gpio_analog[13] divbuf_4/IN 0.05fF
-C288 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C289 pd_0/R pd_0/UP 0.46fF
-C290 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF
-C291 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF
-C292 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C293 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C294 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.21fF
-C295 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C296 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C297 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF
-C298 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
-C299 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C300 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C301 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C302 ro_complete_0/a4 ro_complete_0/a3 0.53fF
-C303 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
-C304 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C305 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C306 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF
-C307 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C308 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF
-C309 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF
-C310 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF
-C311 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C312 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C313 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C314 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C315 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C316 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF
-C317 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF
-C318 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C319 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C320 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF
-C321 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C322 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
-C323 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C324 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C325 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF
-C326 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C327 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C328 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C329 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C330 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF
-C331 pd_0/DOWN divbuf_0/OUT5 0.00fF
-C332 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C333 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF
-C334 divbuf_4/OUT5 io_analog[5] 43.38fF
-C335 io_analog[6] io_clamp_high[2] 0.53fF
-C336 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C337 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
-C338 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C339 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C340 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF
-C341 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF
-C342 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
-C343 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C344 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF
-C345 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C346 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C347 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C348 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C349 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF
-C350 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
-C351 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C352 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
-C353 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF
-C354 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C355 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF
-C356 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF
-C357 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C358 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C359 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF
-C360 pd_0/DOWN divbuf_0/a_492_n240# 0.13fF
-C361 divbuf_2/OUT5 divbuf_2/IN 0.00fF
-C362 gpio_analog[14] divbuf_4/IN 0.10fF
-C363 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF
-C364 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C365 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF
-C366 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF
-C367 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF
-C368 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C369 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF
-C370 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C371 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF
-C372 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF
-C373 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C374 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
-C375 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
-C376 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C377 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.45fF
-C378 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C379 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C380 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF
-C381 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
-C382 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C383 divbuf_4/IN divbuf_4/OUT5 0.00fF
-C384 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C385 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF
-C386 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF
-C387 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C388 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF
-C389 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF
-C390 ro_complete_0/cbank_1/switch_3/vin divbuf_4/IN 1.30fF
-C391 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF
-C392 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
-C393 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
-C394 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C395 ro_complete_0/cbank_0/v divbuf_4/IN 1.27fF
-C396 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
-C397 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF
-C398 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF
-C399 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C400 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF
-C401 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C402 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C403 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C404 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF
-C405 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF
-C406 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
-C407 gpio_analog[14] ro_complete_0/a3 0.63fF
-C408 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
-C409 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
-C410 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF
-C411 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C412 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C413 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF
-C414 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C415 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C416 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C417 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C418 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF
-C419 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C420 gpio_analog[14] gpio_analog[17] 0.51fF
-C421 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C422 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C423 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF
-C424 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C425 io_analog[5] io_clamp_high[1] 0.53fF
-C426 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF
-C427 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C428 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C429 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF
-C430 cp_0/upbar io_analog[1] 0.02fF
-C431 pd_0/R pd_0/and_pd_0/Z1 0.02fF
-C432 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
-C433 ro_complete_0/a2 ro_complete_0/cbank_1/switch_2/vin 0.12fF
-C434 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF
-C435 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C436 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF
-C437 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C438 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF
-C439 pd_0/DIV divbuf_2/OUT2 0.06fF
-C440 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
-C441 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C442 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/A 0.38fF
-C443 pd_0/DIV pd_0/R 0.51fF
-C444 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF
-C445 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF
-C446 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF
-C447 m4_28900_141410# vssd1 1.12fF
-C448 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C449 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF
-C450 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C451 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF
-C452 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C453 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C454 ro_complete_0/cbank_0/switch_0/vin gpio_analog[14] 0.09fF
-C455 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF
-C456 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C457 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C458 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF
-C459 io_analog[0] io_analog[1] 5.63fF
-C460 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C461 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
-C462 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C463 io_analog[5] m4_115800_678290# 1.01fF
-C464 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C465 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C466 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF
-C467 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF
-C468 pd_0/DOWN pd_0/UP 2.16fF
-C469 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
-C470 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF
-C471 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF
-C472 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C473 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C474 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C475 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF
-C476 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF
-C477 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF
-C478 pd_0/DIV divbuf_2/a_492_n240# 0.00fF
-C479 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C480 ro_complete_0/a4 gpio_analog[14] 3.13fF
-C481 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF
-C482 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C483 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF
-C484 ashish_0/a_150_0# io_analog[7] 9.14fF
-C485 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF
-C486 gpio_noesd[15] gpio_analog[16] 9.28fF
-C487 pd_0/DIV divbuf_2/OUT4 1.11fF
-C488 filter_0/a_4216_n2998# gpio_noesd[15] 0.37fF
-C489 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
-C490 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
-C491 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
-C492 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF
-C493 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF
-C494 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C495 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C496 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
-C497 divbuf_4/IN ro_complete_0/cbank_2/v 1.36fF
-C498 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF
-C499 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF
-C500 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C501 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF
-C502 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C503 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF
-C504 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C505 ro_complete_0/cbank_1/switch_2/vin divbuf_4/IN 1.30fF
-C506 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF
-C507 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C508 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF
-C509 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C510 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF
-C511 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF
-C512 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF
-C513 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF
-C514 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C515 ashish_0/a_150_n710# io_analog[6] 9.14fF
-C516 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF
-C517 gpio_analog[13] ro_complete_0/cbank_0/v 0.16fF
-C518 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C519 io_clamp_high[0] io_analog[4] 0.53fF
-C520 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
-C521 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF
-C522 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C523 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF
-C524 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C525 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF
-C526 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C527 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
-C528 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF
-C529 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C530 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF
-C531 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C532 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C533 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C534 divbuf_4/OUT2 io_analog[5] 0.06fF
-C535 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
-C536 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C537 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
-C538 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF
-C539 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF
-C540 ro_complete_0/a4 gpio_analog[15] 0.92fF
-C541 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF
-C542 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
-C543 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C544 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C545 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C546 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C547 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
-C548 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
-C549 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF
-C550 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF
-C551 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF
-C552 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF
-C553 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C554 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF
-C555 ro_complete_0/cbank_0/switch_3/vin gpio_analog[13] 0.14fF
-C556 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C557 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C558 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
-C559 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF
-C560 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C561 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF
-C562 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF
-C563 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C564 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF
-C565 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF
-C566 ro_complete_0/cbank_1/switch_1/vin divbuf_4/IN 1.30fF
-C567 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C568 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF
-C569 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C570 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF
-C571 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF
-C572 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
-C573 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
-C574 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C575 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C576 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF
-C577 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF
-C578 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C579 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF
-C580 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C581 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
-C582 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF
-C583 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C584 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C585 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF
-C586 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C587 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF
-C588 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C589 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C590 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C0 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1 gpio_analog[14] ro_complete_0/cbank_2/v 0.08fF
+C2 gpio_analog[14] gpio_analog[17] 0.51fF
+C3 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF
+C4 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C5 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C6 cp_0/a_1710_0# io_analog[1] 0.32fF
+C7 io_analog[5] divbuf_0/OUT3 0.26fF
+C8 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C9 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C10 io_analog[5] m4_115800_678290# 1.01fF
+C11 ro_complete_0/a2 ro_complete_0/a4 0.49fF
+C12 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF
+C13 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
+C14 io_analog[5] divbuf_0/IN 0.34fF
+C15 ro_complete_0/a4 ro_complete_0/cbank_1/switch_0/vin 0.15fF
+C16 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C17 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C18 gpio_noesd[15] gpio_analog[16] 9.28fF
+C19 ro_complete_0/a3 divbuf_0/IN 0.05fF
+C20 io_analog[5] divbuf_0/OUT4 1.11fF
+C21 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C22 io_analog[5] io_clamp_high[1] 0.53fF
+C23 divbuf_0/OUT5 divbuf_0/IN 0.00fF
+C24 io_clamp_low[0] io_analog[4] 0.53fF
+C25 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF
+C26 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C27 io_analog[6] io_clamp_high[2] 0.53fF
+C28 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF
+C29 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C30 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C31 io_analog[5] divbuf_0/OUT5 43.38fF
+C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C33 ro_complete_0/a4 divbuf_0/IN 0.05fF
+C34 ro_complete_0/a4 gpio_analog[15] 0.92fF
+C35 ro_complete_0/a2 gpio_analog[14] 0.56fF
+C36 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
+C37 io_analog[5] divbuf_0/a_492_n240# 0.00fF
+C38 gpio_analog[14] ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C39 gpio_analog[13] divbuf_0/IN 0.05fF
+C40 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.21fF
+C41 ro_complete_0/a4 ro_complete_0/a3 0.53fF
+C42 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
+C43 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C44 io_analog[7] io_analog[6] 13.31fF
+C45 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C46 cp_0/upbar io_analog[1] 0.02fF
+C47 gpio_noesd[15] gpio_analog[17] 5.80fF
+C48 io_analog[5] divbuf_0/OUT2 0.06fF
+C49 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C50 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C51 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C52 gpio_analog[14] divbuf_0/IN 0.10fF
+C53 gpio_analog[14] gpio_analog[15] 0.68fF
+C54 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C55 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
+C56 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C57 ro_complete_0/cbank_1/switch_3/vin divbuf_0/IN 1.30fF
+C58 ro_complete_0/cbank_0/v divbuf_0/IN 1.27fF
+C59 ro_complete_0/a3 gpio_analog[16] 0.77fF
+C60 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C61 gpio_analog[14] ro_complete_0/a3 0.63fF
+C62 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF
+C63 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C64 ro_complete_0/a2 gpio_analog[17] 0.69fF
+C65 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C66 ashish_0/a_150_n710# io_analog[7] 4.33fF
+C67 ro_complete_0/a2 ro_complete_0/cbank_1/switch_2/vin 0.12fF
+C68 gpio_analog[14] vssd1 0.25fF
+C69 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C70 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C71 ro_complete_0/cbank_0/switch_0/vin gpio_analog[14] 0.09fF
+C72 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C73 ashish_0/a_150_n710# io_analog[6] 9.14fF
+C74 ro_complete_0/a4 gpio_analog[14] 3.13fF
+C75 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C76 io_analog[5] io_clamp_low[1] 0.53fF
+C77 divbuf_0/IN ro_complete_0/cbank_2/v 1.36fF
+C78 io_analog[6] io_clamp_low[2] 0.53fF
+C79 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C80 ro_complete_0/cbank_1/switch_2/vin divbuf_0/IN 1.30fF
+C81 gpio_analog[13] ro_complete_0/cbank_0/v 0.16fF
+C82 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C83 io_analog[7] ashish_0/a_150_0# 9.14fF
+C84 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C85 io_clamp_high[0] io_analog[4] 0.53fF
+C86 m4_28900_141410# vssd1 1.12fF
+C87 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C88 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C89 gpio_analog[14] gpio_analog[16] 0.57fF
+C90 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C91 ro_complete_0/cbank_0/switch_3/vin gpio_analog[13] 0.14fF
+C92 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C93 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C94 gpio_noesd[15] gpio_analog[15] 11.27fF
+C95 filter_0/a_4216_n2998# gpio_noesd[15] 0.37fF
+C96 ro_complete_0/cbank_1/switch_1/vin divbuf_0/IN 1.30fF
+C97 ashish_0/a_150_0# io_analog[6] 4.44fF
+C98 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C99 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C100 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF
+C101 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C102 ro_complete_0/cbank_1/switch_4/vin divbuf_0/IN 1.30fF
+C103 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C104 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/a3 0.15fF
+C105 ro_complete_0/cbank_2/switch_3/vin gpio_analog[13] 0.14fF
+C106 filter_0/a_4216_n5230# gpio_noesd[15] 0.19fF
+C107 gpio_analog[14] ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C108 gpio_analog[13] ro_complete_0/cbank_2/v 0.05fF
+C109 io_analog[0] io_analog[1] 5.63fF
+C110 ro_complete_0/a2 divbuf_0/IN 0.05fF
+C111 ro_complete_0/cbank_1/switch_0/vin divbuf_0/IN 1.45fF
+C112 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C113 cp_0/a_1710_0# io_analog[0] 0.84fF
+C114 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C115 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C116 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C117 ashish_0/a_150_n710# ashish_0/a_150_0# 6.31fF
+C118 ro_complete_0/cbank_1/switch_5/vin divbuf_0/IN 1.30fF
+C119 ro_complete_0/a2 ro_complete_0/a3 0.49fF
+C120 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
Xashish_0 io_analog[7] io_analog[6] gpio_analog[12] ashish
-Xpd_0 gpio_analog[12] gpio_analog[12] gpio_analog[12] pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R
-+ pd
Xcp_0 vdda1 vdda1 gpio_analog[12] io_analog[0] io_analog[1] cp_0/upbar cp
Xfilter_0 gpio_analog[12] gpio_noesd[15] filter
Xro_complete_0 gpio_analog[12] gpio_analog[13] gpio_analog[14] ro_complete_0/a4 ro_complete_0/a3
+ ro_complete_0/a2 ro_complete
-Xdivbuf_0 gpio_analog[12] pd_0/DOWN gpio_analog[12] divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4
-+ divbuf_0/OUT5 gpio_analog[12] divbuf
-Xdivbuf_1 gpio_analog[12] pd_0/UP gpio_analog[12] divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4
-+ divbuf_1/OUT5 gpio_analog[12] divbuf
-Xdivbuf_2 gpio_analog[12] divbuf_2/IN pd_0/DIV divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4
-+ divbuf_2/OUT5 gpio_analog[12] divbuf
-Xdivbuf_3 gpio_analog[12] gpio_analog[12] gpio_analog[12] divbuf_3/OUT2 divbuf_3/OUT3
-+ divbuf_3/OUT4 divbuf_3/OUT5 gpio_analog[12] divbuf
-Xdivbuf_4 VDD divbuf_4/IN io_analog[5] divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 divbuf_4/OUT5
+Xdivbuf_0 VDD divbuf_0/IN io_analog[5] divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 divbuf_0/OUT5
+ gpio_analog[12] divbuf
-Xpll_full_0 vdda1 pll_full
-C591 io_analog[4] vdda1 43.84fF
-C592 io_in_3v3[0] vdda1 0.61fF
-C593 io_oeb[26] vdda1 0.61fF
-C594 io_in[0] vdda1 0.61fF
-C595 io_out[26] vdda1 0.61fF
-C596 io_out[0] vdda1 0.61fF
-C597 io_in[26] vdda1 0.61fF
-C598 io_oeb[0] vdda1 0.61fF
-C599 io_in_3v3[26] vdda1 0.61fF
-C600 io_in_3v3[1] vdda1 0.61fF
-C601 io_oeb[25] vdda1 0.61fF
-C602 io_in[1] vdda1 0.61fF
-C603 io_out[25] vdda1 0.61fF
-C604 io_out[1] vdda1 0.61fF
-C605 io_in[25] vdda1 0.61fF
-C606 io_oeb[1] vdda1 0.61fF
-C607 io_in_3v3[25] vdda1 0.61fF
-C608 io_in_3v3[2] vdda1 0.61fF
-C609 io_oeb[24] vdda1 0.61fF
-C610 io_in[2] vdda1 0.61fF
-C611 io_out[24] vdda1 0.61fF
-C612 io_out[2] vdda1 0.61fF
-C613 io_in[24] vdda1 0.61fF
-C614 io_oeb[2] vdda1 0.61fF
-C615 io_in_3v3[24] vdda1 0.61fF
-C616 io_in_3v3[3] vdda1 0.61fF
-C617 gpio_noesd[17] vdda1 0.61fF
-C618 io_in[3] vdda1 0.61fF
-C619 io_out[3] vdda1 0.61fF
-C620 io_oeb[3] vdda1 0.61fF
-C621 io_in_3v3[4] vdda1 0.61fF
-C622 io_in[4] vdda1 0.61fF
-C623 io_out[4] vdda1 0.61fF
-C624 io_oeb[4] vdda1 0.61fF
-C625 io_in_3v3[5] vdda1 0.61fF
-C626 io_in[5] vdda1 0.61fF
-C627 io_out[5] vdda1 0.61fF
-C628 io_oeb[5] vdda1 0.61fF
-C629 io_in_3v3[6] vdda1 0.61fF
-C630 io_in[6] vdda1 0.61fF
-C631 io_out[6] vdda1 0.61fF
-C632 io_oeb[6] vdda1 0.61fF
-C633 vssd1 vdda1 604.65fF
-C634 gpio_analog[17] vdda1 187.27fF
-C635 io_oeb[23] vdda1 0.61fF
-C636 io_out[23] vdda1 0.61fF
-C637 io_in[23] vdda1 0.61fF
-C638 io_in_3v3[23] vdda1 0.61fF
-C639 gpio_noesd[16] vdda1 0.61fF
-C640 gpio_analog[16] vdda1 177.29fF
-C641 io_oeb[22] vdda1 0.61fF
-C642 io_out[22] vdda1 0.61fF
-C643 io_in[22] vdda1 0.61fF
-C644 io_in_3v3[22] vdda1 0.61fF
-C645 io_oeb[21] vdda1 0.61fF
-C646 io_out[21] vdda1 0.61fF
-C647 io_in[21] vdda1 0.61fF
-C648 gpio_analog[15] vdda1 145.89fF
-C649 io_in_3v3[21] vdda1 0.61fF
-C650 gpio_noesd[14] vdda1 0.61fF
-C651 vssd2 vdda1 13.04fF
-C652 vdda2 vdda1 13.04fF
-C653 gpio_analog[0] vdda1 0.61fF
-C654 gpio_noesd[0] vdda1 0.61fF
-C655 io_in_3v3[7] vdda1 0.61fF
-C656 io_in[7] vdda1 0.61fF
-C657 io_out[7] vdda1 0.61fF
-C658 io_oeb[7] vdda1 0.61fF
-C659 gpio_analog[1] vdda1 0.61fF
-C660 gpio_noesd[1] vdda1 0.61fF
-C661 io_in_3v3[8] vdda1 0.61fF
-C662 io_oeb[20] vdda1 0.61fF
-C663 io_out[20] vdda1 0.61fF
-C664 io_in[20] vdda1 0.61fF
-C665 io_in_3v3[20] vdda1 0.61fF
-C666 gpio_noesd[13] vdda1 0.61fF
-C667 io_oeb[19] vdda1 0.61fF
-C668 io_out[19] vdda1 0.61fF
-C669 io_in[19] vdda1 0.61fF
-C670 io_in_3v3[19] vdda1 0.61fF
-C671 gpio_noesd[12] vdda1 0.61fF
-C672 io_in[8] vdda1 0.61fF
-C673 io_out[8] vdda1 0.61fF
-C674 io_oeb[8] vdda1 0.61fF
-C675 gpio_analog[2] vdda1 0.61fF
-C676 gpio_noesd[2] vdda1 0.61fF
-C677 io_in_3v3[9] vdda1 0.61fF
-C678 io_in[9] vdda1 0.61fF
-C679 io_out[9] vdda1 0.61fF
-C680 io_oeb[9] vdda1 0.61fF
-C681 io_oeb[18] vdda1 0.61fF
-C682 io_out[18] vdda1 0.61fF
-C683 io_in[18] vdda1 0.61fF
-C684 io_in_3v3[18] vdda1 0.61fF
-C685 gpio_noesd[11] vdda1 0.61fF
-C686 gpio_analog[11] vdda1 0.61fF
-C687 io_oeb[17] vdda1 0.61fF
-C688 io_out[17] vdda1 0.61fF
-C689 io_in[17] vdda1 0.61fF
-C690 io_in_3v3[17] vdda1 0.61fF
-C691 gpio_noesd[10] vdda1 0.61fF
-C692 gpio_analog[10] vdda1 0.61fF
-C693 gpio_analog[3] vdda1 0.61fF
-C694 gpio_noesd[3] vdda1 0.61fF
-C695 io_in_3v3[10] vdda1 0.61fF
-C696 io_in[10] vdda1 0.61fF
-C697 io_out[10] vdda1 0.61fF
-C698 io_oeb[10] vdda1 0.61fF
-C699 io_oeb[16] vdda1 0.61fF
-C700 gpio_analog[4] vdda1 0.61fF
-C701 gpio_noesd[4] vdda1 0.61fF
-C702 io_in_3v3[11] vdda1 0.61fF
-C703 io_in[11] vdda1 0.61fF
-C704 io_out[11] vdda1 0.61fF
-C705 io_oeb[11] vdda1 0.61fF
-C706 io_out[16] vdda1 0.61fF
-C707 io_in[16] vdda1 0.61fF
-C708 io_in_3v3[16] vdda1 0.61fF
-C709 gpio_noesd[9] vdda1 0.61fF
-C710 gpio_analog[9] vdda1 0.61fF
-C711 io_oeb[15] vdda1 0.61fF
-C712 io_out[15] vdda1 0.61fF
-C713 io_in[15] vdda1 0.61fF
-C714 io_in_3v3[15] vdda1 0.61fF
-C715 gpio_noesd[8] vdda1 0.61fF
-C716 gpio_analog[8] vdda1 0.61fF
-C717 gpio_analog[5] vdda1 0.61fF
-C718 gpio_noesd[5] vdda1 0.61fF
-C719 io_in_3v3[12] vdda1 0.61fF
-C720 io_in[12] vdda1 0.61fF
-C721 io_out[12] vdda1 0.61fF
-C722 io_oeb[12] vdda1 0.61fF
-C723 io_oeb[14] vdda1 0.61fF
-C724 io_out[14] vdda1 0.61fF
-C725 io_in[14] vdda1 0.61fF
-C726 io_in_3v3[14] vdda1 0.61fF
-C727 gpio_noesd[7] vdda1 0.61fF
-C728 vssa2 vdda1 13.04fF
-C729 gpio_analog[6] vdda1 0.61fF
-C730 gpio_noesd[6] vdda1 0.61fF
-C731 io_in_3v3[13] vdda1 0.61fF
-C732 io_in[13] vdda1 0.61fF
-C733 io_out[13] vdda1 0.61fF
-C734 io_oeb[13] vdda1 0.61fF
-C735 vccd1 vdda1 13.04fF
-C736 vccd2 vdda1 13.04fF
-C737 io_analog[10] vdda1 9.60fF
-C738 io_analog[3] vdda1 6.86fF
-C739 io_clamp_high[0] vdda1 3.58fF
-C740 io_clamp_low[0] vdda1 3.58fF
-C741 io_clamp_high[1] vdda1 3.58fF
-C742 io_clamp_low[1] vdda1 3.58fF
-C743 io_clamp_high[2] vdda1 3.58fF
-C744 io_clamp_low[2] vdda1 3.58fF
-C745 io_analog[8] vdda1 6.83fF
-C746 io_analog[9] vdda1 25.11fF
-C747 user_irq[2] vdda1 0.63fF
-C748 user_irq[1] vdda1 0.63fF
-C749 user_irq[0] vdda1 0.63fF
-C750 user_clock2 vdda1 0.63fF
-C751 la_oenb[127] vdda1 0.63fF
-C752 la_data_out[127] vdda1 0.63fF
-C753 la_data_in[127] vdda1 0.63fF
-C754 la_oenb[126] vdda1 0.63fF
-C755 la_data_out[126] vdda1 0.63fF
-C756 la_data_in[126] vdda1 0.63fF
-C757 la_oenb[125] vdda1 0.63fF
-C758 la_data_out[125] vdda1 0.63fF
-C759 la_data_in[125] vdda1 0.63fF
-C760 la_oenb[124] vdda1 0.63fF
-C761 la_data_out[124] vdda1 0.63fF
-C762 la_data_in[124] vdda1 0.63fF
-C763 la_oenb[123] vdda1 0.63fF
-C764 la_data_out[123] vdda1 0.63fF
-C765 la_data_in[123] vdda1 0.63fF
-C766 la_oenb[122] vdda1 0.63fF
-C767 la_data_out[122] vdda1 0.63fF
-C768 la_data_in[122] vdda1 0.63fF
-C769 la_oenb[121] vdda1 0.63fF
-C770 la_data_out[121] vdda1 0.63fF
-C771 la_data_in[121] vdda1 0.63fF
-C772 la_oenb[120] vdda1 0.63fF
-C773 la_data_out[120] vdda1 0.63fF
-C774 la_data_in[120] vdda1 0.63fF
-C775 la_oenb[119] vdda1 0.63fF
-C776 la_data_out[119] vdda1 0.63fF
-C777 la_data_in[119] vdda1 0.63fF
-C778 la_oenb[118] vdda1 0.63fF
-C779 la_data_out[118] vdda1 0.63fF
-C780 la_data_in[118] vdda1 0.63fF
-C781 la_oenb[117] vdda1 0.63fF
-C782 la_data_out[117] vdda1 0.63fF
-C783 la_data_in[117] vdda1 0.63fF
-C784 la_oenb[116] vdda1 0.63fF
-C785 la_data_out[116] vdda1 0.63fF
-C786 la_data_in[116] vdda1 0.63fF
-C787 la_oenb[115] vdda1 0.63fF
-C788 la_data_out[115] vdda1 0.63fF
-C789 la_data_in[115] vdda1 0.63fF
-C790 la_oenb[114] vdda1 0.63fF
-C791 la_data_out[114] vdda1 0.63fF
-C792 la_data_in[114] vdda1 0.63fF
-C793 la_oenb[113] vdda1 0.63fF
-C794 la_data_out[113] vdda1 0.63fF
-C795 la_data_in[113] vdda1 0.63fF
-C796 la_oenb[112] vdda1 0.63fF
-C797 la_data_out[112] vdda1 0.63fF
-C798 la_data_in[112] vdda1 0.63fF
-C799 la_oenb[111] vdda1 0.63fF
-C800 la_data_out[111] vdda1 0.63fF
-C801 la_data_in[111] vdda1 0.63fF
-C802 la_oenb[110] vdda1 0.63fF
-C803 la_data_out[110] vdda1 0.63fF
-C804 la_data_in[110] vdda1 0.63fF
-C805 la_oenb[109] vdda1 0.63fF
-C806 la_data_out[109] vdda1 0.63fF
-C807 la_data_in[109] vdda1 0.63fF
-C808 la_oenb[108] vdda1 0.63fF
-C809 la_data_out[108] vdda1 0.63fF
-C810 la_data_in[108] vdda1 0.63fF
-C811 la_oenb[107] vdda1 0.63fF
-C812 la_data_out[107] vdda1 0.63fF
-C813 la_data_in[107] vdda1 0.63fF
-C814 la_oenb[106] vdda1 0.63fF
-C815 la_data_out[106] vdda1 0.63fF
-C816 la_data_in[106] vdda1 0.63fF
-C817 la_oenb[105] vdda1 0.63fF
-C818 la_data_out[105] vdda1 0.63fF
-C819 la_data_in[105] vdda1 0.63fF
-C820 la_oenb[104] vdda1 0.63fF
-C821 la_data_out[104] vdda1 0.63fF
-C822 la_data_in[104] vdda1 0.63fF
-C823 la_oenb[103] vdda1 0.63fF
-C824 la_data_out[103] vdda1 0.63fF
-C825 la_data_in[103] vdda1 0.63fF
-C826 la_oenb[102] vdda1 0.63fF
-C827 la_data_out[102] vdda1 0.63fF
-C828 la_data_in[102] vdda1 0.63fF
-C829 la_oenb[101] vdda1 0.63fF
-C830 la_data_out[101] vdda1 0.63fF
-C831 la_data_in[101] vdda1 0.63fF
-C832 la_oenb[100] vdda1 0.63fF
-C833 la_data_out[100] vdda1 0.63fF
-C834 la_data_in[100] vdda1 0.63fF
-C835 la_oenb[99] vdda1 0.63fF
-C836 la_data_out[99] vdda1 0.63fF
-C837 la_data_in[99] vdda1 0.63fF
-C838 la_oenb[98] vdda1 0.63fF
-C839 la_data_out[98] vdda1 0.63fF
-C840 la_data_in[98] vdda1 0.63fF
-C841 la_oenb[97] vdda1 0.63fF
-C842 la_data_out[97] vdda1 0.63fF
-C843 la_data_in[97] vdda1 0.63fF
-C844 la_oenb[96] vdda1 0.63fF
-C845 la_data_out[96] vdda1 0.63fF
-C846 la_data_in[96] vdda1 0.63fF
-C847 la_oenb[95] vdda1 0.63fF
-C848 la_data_out[95] vdda1 0.63fF
-C849 la_data_in[95] vdda1 0.63fF
-C850 la_oenb[94] vdda1 0.63fF
-C851 la_data_out[94] vdda1 0.63fF
-C852 la_data_in[94] vdda1 0.63fF
-C853 la_oenb[93] vdda1 0.63fF
-C854 la_data_out[93] vdda1 0.63fF
-C855 la_data_in[93] vdda1 0.63fF
-C856 la_oenb[92] vdda1 0.63fF
-C857 la_data_out[92] vdda1 0.63fF
-C858 la_data_in[92] vdda1 0.63fF
-C859 la_oenb[91] vdda1 0.63fF
-C860 la_data_out[91] vdda1 0.63fF
-C861 la_data_in[91] vdda1 0.63fF
-C862 la_oenb[90] vdda1 0.63fF
-C863 la_data_out[90] vdda1 0.63fF
-C864 la_data_in[90] vdda1 0.63fF
-C865 la_oenb[89] vdda1 0.63fF
-C866 la_data_out[89] vdda1 0.63fF
-C867 la_data_in[89] vdda1 0.63fF
-C868 la_oenb[88] vdda1 0.63fF
-C869 la_data_out[88] vdda1 0.63fF
-C870 la_data_in[88] vdda1 0.63fF
-C871 la_oenb[87] vdda1 0.63fF
-C872 la_data_out[87] vdda1 0.63fF
-C873 la_data_in[87] vdda1 0.63fF
-C874 la_oenb[86] vdda1 0.63fF
-C875 la_data_out[86] vdda1 0.63fF
-C876 la_data_in[86] vdda1 0.63fF
-C877 la_oenb[85] vdda1 0.63fF
-C878 la_data_out[85] vdda1 0.63fF
-C879 la_data_in[85] vdda1 0.63fF
-C880 la_oenb[84] vdda1 0.63fF
-C881 la_data_out[84] vdda1 0.63fF
-C882 la_data_in[84] vdda1 0.63fF
-C883 la_oenb[83] vdda1 0.63fF
-C884 la_data_out[83] vdda1 0.63fF
-C885 la_data_in[83] vdda1 0.63fF
-C886 la_oenb[82] vdda1 0.63fF
-C887 la_data_out[82] vdda1 0.63fF
-C888 la_data_in[82] vdda1 0.63fF
-C889 la_oenb[81] vdda1 0.63fF
-C890 la_data_out[81] vdda1 0.63fF
-C891 la_data_in[81] vdda1 0.63fF
-C892 la_oenb[80] vdda1 0.63fF
-C893 la_data_out[80] vdda1 0.63fF
-C894 la_data_in[80] vdda1 0.63fF
-C895 la_oenb[79] vdda1 0.63fF
-C896 la_data_out[79] vdda1 0.63fF
-C897 la_data_in[79] vdda1 0.63fF
-C898 la_oenb[78] vdda1 0.63fF
-C899 la_data_out[78] vdda1 0.63fF
-C900 la_data_in[78] vdda1 0.63fF
-C901 la_oenb[77] vdda1 0.63fF
-C902 la_data_out[77] vdda1 0.63fF
-C903 la_data_in[77] vdda1 0.63fF
-C904 la_oenb[76] vdda1 0.63fF
-C905 la_data_out[76] vdda1 0.63fF
-C906 la_data_in[76] vdda1 0.63fF
-C907 la_oenb[75] vdda1 0.63fF
-C908 la_data_out[75] vdda1 0.63fF
-C909 la_data_in[75] vdda1 0.63fF
-C910 la_oenb[74] vdda1 0.63fF
-C911 la_data_out[74] vdda1 0.63fF
-C912 la_data_in[74] vdda1 0.63fF
-C913 la_oenb[73] vdda1 0.63fF
-C914 la_data_out[73] vdda1 0.63fF
-C915 la_data_in[73] vdda1 0.63fF
-C916 la_oenb[72] vdda1 0.63fF
-C917 la_data_out[72] vdda1 0.63fF
-C918 la_data_in[72] vdda1 0.63fF
-C919 la_oenb[71] vdda1 0.63fF
-C920 la_data_out[71] vdda1 0.63fF
-C921 la_data_in[71] vdda1 0.63fF
-C922 la_oenb[70] vdda1 0.63fF
-C923 la_data_out[70] vdda1 0.63fF
-C924 la_data_in[70] vdda1 0.63fF
-C925 la_oenb[69] vdda1 0.63fF
-C926 la_data_out[69] vdda1 0.63fF
-C927 la_data_in[69] vdda1 0.63fF
-C928 la_oenb[68] vdda1 0.63fF
-C929 la_data_out[68] vdda1 0.63fF
-C930 la_data_in[68] vdda1 0.63fF
-C931 la_oenb[67] vdda1 0.63fF
-C932 la_data_out[67] vdda1 0.63fF
-C933 la_data_in[67] vdda1 0.63fF
-C934 la_oenb[66] vdda1 0.63fF
-C935 la_data_out[66] vdda1 0.63fF
-C936 la_data_in[66] vdda1 0.63fF
-C937 la_oenb[65] vdda1 0.63fF
-C938 la_data_out[65] vdda1 0.63fF
-C939 la_data_in[65] vdda1 0.63fF
-C940 la_oenb[64] vdda1 0.63fF
-C941 la_data_out[64] vdda1 0.63fF
-C942 la_data_in[64] vdda1 0.63fF
-C943 la_oenb[63] vdda1 0.63fF
-C944 la_data_out[63] vdda1 0.63fF
-C945 la_data_in[63] vdda1 0.63fF
-C946 la_oenb[62] vdda1 0.63fF
-C947 la_data_out[62] vdda1 0.63fF
-C948 la_data_in[62] vdda1 0.63fF
-C949 la_oenb[61] vdda1 0.63fF
-C950 la_data_out[61] vdda1 0.63fF
-C951 la_data_in[61] vdda1 0.63fF
-C952 la_oenb[60] vdda1 0.63fF
-C953 la_data_out[60] vdda1 0.63fF
-C954 la_data_in[60] vdda1 0.63fF
-C955 la_oenb[59] vdda1 0.63fF
-C956 la_data_out[59] vdda1 0.63fF
-C957 la_data_in[59] vdda1 0.63fF
-C958 la_oenb[58] vdda1 0.63fF
-C959 la_data_out[58] vdda1 0.63fF
-C960 la_data_in[58] vdda1 0.63fF
-C961 la_oenb[57] vdda1 0.63fF
-C962 la_data_out[57] vdda1 0.63fF
-C963 la_data_in[57] vdda1 0.63fF
-C964 la_oenb[56] vdda1 0.63fF
-C965 la_data_out[56] vdda1 0.63fF
-C966 la_data_in[56] vdda1 0.63fF
-C967 la_oenb[55] vdda1 0.63fF
-C968 la_data_out[55] vdda1 0.63fF
-C969 la_data_in[55] vdda1 0.63fF
-C970 la_oenb[54] vdda1 0.63fF
-C971 la_data_out[54] vdda1 0.63fF
-C972 la_data_in[54] vdda1 0.63fF
-C973 la_oenb[53] vdda1 0.63fF
-C974 la_data_out[53] vdda1 0.63fF
-C975 la_data_in[53] vdda1 0.63fF
-C976 la_oenb[52] vdda1 0.63fF
-C977 la_data_out[52] vdda1 0.63fF
-C978 la_data_in[52] vdda1 0.63fF
-C979 la_oenb[51] vdda1 0.63fF
-C980 la_data_out[51] vdda1 0.63fF
-C981 la_data_in[51] vdda1 0.63fF
-C982 la_oenb[50] vdda1 0.63fF
-C983 la_data_out[50] vdda1 0.63fF
-C984 la_data_in[50] vdda1 0.63fF
-C985 la_oenb[49] vdda1 0.63fF
-C986 la_data_out[49] vdda1 0.63fF
-C987 la_data_in[49] vdda1 0.63fF
-C988 la_oenb[48] vdda1 0.63fF
-C989 la_data_out[48] vdda1 0.63fF
-C990 la_data_in[48] vdda1 0.63fF
-C991 la_oenb[47] vdda1 0.63fF
-C992 la_data_out[47] vdda1 0.63fF
-C993 la_data_in[47] vdda1 0.63fF
-C994 la_oenb[46] vdda1 0.63fF
-C995 la_data_out[46] vdda1 0.63fF
-C996 la_data_in[46] vdda1 0.63fF
-C997 la_oenb[45] vdda1 0.63fF
-C998 la_data_out[45] vdda1 0.63fF
-C999 la_data_in[45] vdda1 0.63fF
-C1000 la_oenb[44] vdda1 0.63fF
-C1001 la_data_out[44] vdda1 0.63fF
-C1002 la_data_in[44] vdda1 0.63fF
-C1003 la_oenb[43] vdda1 0.63fF
-C1004 la_data_out[43] vdda1 0.63fF
-C1005 la_data_in[43] vdda1 0.63fF
-C1006 la_oenb[42] vdda1 0.63fF
-C1007 la_data_out[42] vdda1 0.63fF
-C1008 la_data_in[42] vdda1 0.63fF
-C1009 la_oenb[41] vdda1 0.63fF
-C1010 la_data_out[41] vdda1 0.63fF
-C1011 la_data_in[41] vdda1 0.63fF
-C1012 la_oenb[40] vdda1 0.63fF
-C1013 la_data_out[40] vdda1 0.63fF
-C1014 la_data_in[40] vdda1 0.63fF
-C1015 la_oenb[39] vdda1 0.63fF
-C1016 la_data_out[39] vdda1 0.63fF
-C1017 la_data_in[39] vdda1 0.63fF
-C1018 la_oenb[38] vdda1 0.63fF
-C1019 la_data_out[38] vdda1 0.63fF
-C1020 la_data_in[38] vdda1 0.63fF
-C1021 la_oenb[37] vdda1 0.63fF
-C1022 la_data_out[37] vdda1 0.63fF
-C1023 la_data_in[37] vdda1 0.63fF
-C1024 la_oenb[36] vdda1 0.63fF
-C1025 la_data_out[36] vdda1 0.63fF
-C1026 la_data_in[36] vdda1 0.63fF
-C1027 la_oenb[35] vdda1 0.63fF
-C1028 la_data_out[35] vdda1 0.63fF
-C1029 la_data_in[35] vdda1 0.63fF
-C1030 la_oenb[34] vdda1 0.63fF
-C1031 la_data_out[34] vdda1 0.63fF
-C1032 la_data_in[34] vdda1 0.63fF
-C1033 la_oenb[33] vdda1 0.63fF
-C1034 la_data_out[33] vdda1 0.63fF
-C1035 la_data_in[33] vdda1 0.63fF
-C1036 la_oenb[32] vdda1 0.63fF
-C1037 la_data_out[32] vdda1 0.63fF
-C1038 la_data_in[32] vdda1 0.63fF
-C1039 la_oenb[31] vdda1 0.63fF
-C1040 la_data_out[31] vdda1 0.63fF
-C1041 la_data_in[31] vdda1 0.63fF
-C1042 la_oenb[30] vdda1 0.63fF
-C1043 la_data_out[30] vdda1 0.63fF
-C1044 la_data_in[30] vdda1 0.63fF
-C1045 la_oenb[29] vdda1 0.63fF
-C1046 la_data_out[29] vdda1 0.63fF
-C1047 la_data_in[29] vdda1 0.63fF
-C1048 la_oenb[28] vdda1 0.63fF
-C1049 la_data_out[28] vdda1 0.63fF
-C1050 la_data_in[28] vdda1 0.63fF
-C1051 la_oenb[27] vdda1 0.63fF
-C1052 la_data_out[27] vdda1 0.63fF
-C1053 la_data_in[27] vdda1 0.63fF
-C1054 la_oenb[26] vdda1 0.63fF
-C1055 la_data_out[26] vdda1 0.63fF
-C1056 la_data_in[26] vdda1 0.63fF
-C1057 la_oenb[25] vdda1 0.63fF
-C1058 la_data_out[25] vdda1 0.63fF
-C1059 la_data_in[25] vdda1 0.63fF
-C1060 la_oenb[24] vdda1 0.63fF
-C1061 la_data_out[24] vdda1 0.63fF
-C1062 la_data_in[24] vdda1 0.63fF
-C1063 la_oenb[23] vdda1 0.63fF
-C1064 la_data_out[23] vdda1 0.63fF
-C1065 la_data_in[23] vdda1 0.63fF
-C1066 la_oenb[22] vdda1 0.63fF
-C1067 la_data_out[22] vdda1 0.63fF
-C1068 la_data_in[22] vdda1 0.63fF
-C1069 la_oenb[21] vdda1 0.63fF
-C1070 la_data_out[21] vdda1 0.63fF
-C1071 la_data_in[21] vdda1 0.63fF
-C1072 la_oenb[20] vdda1 0.63fF
-C1073 la_data_out[20] vdda1 0.63fF
-C1074 la_data_in[20] vdda1 0.63fF
-C1075 la_oenb[19] vdda1 0.63fF
-C1076 la_data_out[19] vdda1 0.63fF
-C1077 la_data_in[19] vdda1 0.63fF
-C1078 la_oenb[18] vdda1 0.63fF
-C1079 la_data_out[18] vdda1 0.63fF
-C1080 la_data_in[18] vdda1 0.63fF
-C1081 la_oenb[17] vdda1 0.63fF
-C1082 la_data_out[17] vdda1 0.63fF
-C1083 la_data_in[17] vdda1 0.63fF
-C1084 la_oenb[16] vdda1 0.63fF
-C1085 la_data_out[16] vdda1 0.63fF
-C1086 la_data_in[16] vdda1 0.63fF
-C1087 la_oenb[15] vdda1 0.63fF
-C1088 la_data_out[15] vdda1 0.63fF
-C1089 la_data_in[15] vdda1 0.63fF
-C1090 la_oenb[14] vdda1 0.63fF
-C1091 la_data_out[14] vdda1 0.63fF
-C1092 la_data_in[14] vdda1 0.63fF
-C1093 la_oenb[13] vdda1 0.63fF
-C1094 la_data_out[13] vdda1 0.63fF
-C1095 la_data_in[13] vdda1 0.63fF
-C1096 la_oenb[12] vdda1 0.63fF
-C1097 la_data_out[12] vdda1 0.63fF
-C1098 la_data_in[12] vdda1 0.63fF
-C1099 la_oenb[11] vdda1 0.63fF
-C1100 la_data_out[11] vdda1 0.63fF
-C1101 la_data_in[11] vdda1 0.63fF
-C1102 la_oenb[10] vdda1 0.63fF
-C1103 la_data_out[10] vdda1 0.63fF
-C1104 la_data_in[10] vdda1 0.63fF
-C1105 la_oenb[9] vdda1 0.63fF
-C1106 la_data_out[9] vdda1 0.63fF
-C1107 la_data_in[9] vdda1 0.63fF
-C1108 la_oenb[8] vdda1 0.63fF
-C1109 la_data_out[8] vdda1 0.63fF
-C1110 la_data_in[8] vdda1 0.63fF
-C1111 la_oenb[7] vdda1 0.63fF
-C1112 la_data_out[7] vdda1 0.63fF
-C1113 la_data_in[7] vdda1 0.63fF
-C1114 la_oenb[6] vdda1 0.63fF
-C1115 la_data_out[6] vdda1 0.63fF
-C1116 la_data_in[6] vdda1 0.63fF
-C1117 la_oenb[5] vdda1 0.63fF
-C1118 la_data_out[5] vdda1 0.63fF
-C1119 la_data_in[5] vdda1 0.63fF
-C1120 la_oenb[4] vdda1 0.63fF
-C1121 la_data_out[4] vdda1 0.63fF
-C1122 la_data_in[4] vdda1 0.63fF
-C1123 la_oenb[3] vdda1 0.63fF
-C1124 la_data_out[3] vdda1 0.63fF
-C1125 la_data_in[3] vdda1 0.63fF
-C1126 la_oenb[2] vdda1 0.63fF
-C1127 la_data_out[2] vdda1 0.63fF
-C1128 la_data_in[2] vdda1 0.63fF
-C1129 la_oenb[1] vdda1 0.63fF
-C1130 la_data_out[1] vdda1 0.63fF
-C1131 la_data_in[1] vdda1 0.63fF
-C1132 la_oenb[0] vdda1 0.63fF
-C1133 la_data_out[0] vdda1 0.63fF
-C1134 la_data_in[0] vdda1 0.63fF
-C1135 wbs_dat_o[31] vdda1 0.63fF
-C1136 wbs_dat_i[31] vdda1 0.63fF
-C1137 wbs_adr_i[31] vdda1 0.63fF
-C1138 wbs_dat_o[30] vdda1 0.63fF
-C1139 wbs_dat_i[30] vdda1 0.63fF
-C1140 wbs_adr_i[30] vdda1 0.63fF
-C1141 wbs_dat_o[29] vdda1 0.63fF
-C1142 wbs_dat_i[29] vdda1 0.63fF
-C1143 wbs_adr_i[29] vdda1 0.63fF
-C1144 wbs_dat_o[28] vdda1 0.63fF
-C1145 wbs_dat_i[28] vdda1 0.63fF
-C1146 wbs_adr_i[28] vdda1 0.63fF
-C1147 wbs_dat_o[27] vdda1 0.63fF
-C1148 wbs_dat_i[27] vdda1 0.63fF
-C1149 wbs_adr_i[27] vdda1 0.63fF
-C1150 wbs_dat_o[26] vdda1 0.63fF
-C1151 wbs_dat_i[26] vdda1 0.63fF
-C1152 wbs_adr_i[26] vdda1 0.63fF
-C1153 wbs_dat_o[25] vdda1 0.63fF
-C1154 wbs_dat_i[25] vdda1 0.63fF
-C1155 wbs_adr_i[25] vdda1 0.63fF
-C1156 wbs_dat_o[24] vdda1 0.63fF
-C1157 wbs_dat_i[24] vdda1 0.63fF
-C1158 wbs_adr_i[24] vdda1 0.63fF
-C1159 wbs_dat_o[23] vdda1 0.63fF
-C1160 wbs_dat_i[23] vdda1 0.63fF
-C1161 wbs_adr_i[23] vdda1 0.63fF
-C1162 wbs_dat_o[22] vdda1 0.63fF
-C1163 wbs_dat_i[22] vdda1 0.63fF
-C1164 wbs_adr_i[22] vdda1 0.63fF
-C1165 wbs_dat_o[21] vdda1 0.63fF
-C1166 wbs_dat_i[21] vdda1 0.63fF
-C1167 wbs_adr_i[21] vdda1 0.63fF
-C1168 wbs_dat_o[20] vdda1 0.63fF
-C1169 wbs_dat_i[20] vdda1 0.63fF
-C1170 wbs_adr_i[20] vdda1 0.63fF
-C1171 wbs_dat_o[19] vdda1 0.63fF
-C1172 wbs_dat_i[19] vdda1 0.63fF
-C1173 wbs_adr_i[19] vdda1 0.63fF
-C1174 wbs_dat_o[18] vdda1 0.63fF
-C1175 wbs_dat_i[18] vdda1 0.63fF
-C1176 wbs_adr_i[18] vdda1 0.63fF
-C1177 wbs_dat_o[17] vdda1 0.63fF
-C1178 wbs_dat_i[17] vdda1 0.63fF
-C1179 wbs_adr_i[17] vdda1 0.63fF
-C1180 wbs_dat_o[16] vdda1 0.63fF
-C1181 wbs_dat_i[16] vdda1 0.63fF
-C1182 wbs_adr_i[16] vdda1 0.63fF
-C1183 wbs_dat_o[15] vdda1 0.63fF
-C1184 wbs_dat_i[15] vdda1 0.63fF
-C1185 wbs_adr_i[15] vdda1 0.63fF
-C1186 wbs_dat_o[14] vdda1 0.63fF
-C1187 wbs_dat_i[14] vdda1 0.63fF
-C1188 wbs_adr_i[14] vdda1 0.63fF
-C1189 wbs_dat_o[13] vdda1 0.63fF
-C1190 wbs_dat_i[13] vdda1 0.63fF
-C1191 wbs_adr_i[13] vdda1 0.63fF
-C1192 wbs_dat_o[12] vdda1 0.63fF
-C1193 wbs_dat_i[12] vdda1 0.63fF
-C1194 wbs_adr_i[12] vdda1 0.63fF
-C1195 wbs_dat_o[11] vdda1 0.63fF
-C1196 wbs_dat_i[11] vdda1 0.63fF
-C1197 wbs_adr_i[11] vdda1 0.63fF
-C1198 wbs_dat_o[10] vdda1 0.63fF
-C1199 wbs_dat_i[10] vdda1 0.63fF
-C1200 wbs_adr_i[10] vdda1 0.63fF
-C1201 wbs_dat_o[9] vdda1 0.63fF
-C1202 wbs_dat_i[9] vdda1 0.63fF
-C1203 wbs_adr_i[9] vdda1 0.63fF
-C1204 wbs_dat_o[8] vdda1 0.63fF
-C1205 wbs_dat_i[8] vdda1 0.63fF
-C1206 wbs_adr_i[8] vdda1 0.63fF
-C1207 wbs_dat_o[7] vdda1 0.63fF
-C1208 wbs_dat_i[7] vdda1 0.63fF
-C1209 wbs_adr_i[7] vdda1 0.63fF
-C1210 wbs_dat_o[6] vdda1 0.63fF
-C1211 wbs_dat_i[6] vdda1 0.63fF
-C1212 wbs_adr_i[6] vdda1 0.63fF
-C1213 wbs_dat_o[5] vdda1 0.63fF
-C1214 wbs_dat_i[5] vdda1 0.63fF
-C1215 wbs_adr_i[5] vdda1 0.63fF
-C1216 wbs_dat_o[4] vdda1 0.63fF
-C1217 wbs_dat_i[4] vdda1 0.63fF
-C1218 wbs_adr_i[4] vdda1 0.63fF
-C1219 wbs_sel_i[3] vdda1 0.63fF
-C1220 wbs_dat_o[3] vdda1 0.63fF
-C1221 wbs_dat_i[3] vdda1 0.63fF
-C1222 wbs_adr_i[3] vdda1 0.63fF
-C1223 wbs_sel_i[2] vdda1 0.63fF
-C1224 wbs_dat_o[2] vdda1 0.63fF
-C1225 wbs_dat_i[2] vdda1 0.63fF
-C1226 wbs_adr_i[2] vdda1 0.63fF
-C1227 wbs_sel_i[1] vdda1 0.63fF
-C1228 wbs_dat_o[1] vdda1 0.63fF
-C1229 wbs_dat_i[1] vdda1 0.63fF
-C1230 wbs_adr_i[1] vdda1 0.63fF
-C1231 wbs_sel_i[0] vdda1 0.63fF
-C1232 wbs_dat_o[0] vdda1 0.63fF
-C1233 wbs_dat_i[0] vdda1 0.63fF
-C1234 wbs_adr_i[0] vdda1 0.63fF
-C1235 wbs_we_i vdda1 0.63fF
-C1236 wbs_stb_i vdda1 0.63fF
-C1237 wbs_cyc_i vdda1 0.63fF
-C1238 wbs_ack_o vdda1 0.63fF
-C1239 wb_rst_i vdda1 0.63fF
-C1240 wb_clk_i vdda1 0.63fF
-C1241 gpio_analog[7] vdda1 92.33fF
-C1242 io_analog[2] vdda1 133.63fF
-C1243 m4_28900_141410# vdda1 540.96fF **FLOATING
-C1244 m4_115800_678290# vdda1 80.80fF **FLOATING
-C1245 li_17838_664356# vdda1 1.78fF **FLOATING
-C1246 li_17806_665450# vdda1 1.77fF **FLOATING
-C1247 pll_full_0/divider_0/and_0/Z1 vdda1 0.65fF
-C1248 pll_full_0/divider_0/and_0/B vdda1 2.45fF
-C1249 pll_full_0/divider_0/and_0/A vdda1 2.35fF
-C1250 pll_full_0/divider_0/and_0/out1 vdda1 2.99fF
-C1251 pll_full_0/divider_0/tspc_2/Z4 vdda1 0.86fF
-C1252 pll_full_0/divbuf_0/IN vdda1 10.47fF
-C1253 pll_full_0/divider_0/tspc_2/Z3 vdda1 2.26fF
-C1254 pll_full_0/divider_0/tspc_2/Z2 vdda1 1.46fF
-C1255 pll_full_0/divider_0/tspc_2/Z1 vdda1 0.99fF
-C1256 pll_full_0/divider_0/nor_0/B vdda1 6.48fF
-C1257 pll_full_0/divider_0/tspc_2/a_630_n680# vdda1 1.14fF **FLOATING
-C1258 pll_full_0/divider_0/tspc_1/Z4 vdda1 0.86fF
-C1259 pll_full_0/divider_0/tspc_1/Q vdda1 3.12fF
-C1260 pll_full_0/divider_0/tspc_1/Z3 vdda1 2.26fF
-C1261 pll_full_0/divider_0/tspc_1/Z2 vdda1 1.46fF
-C1262 pll_full_0/divider_0/tspc_1/Z1 vdda1 0.99fF
-C1263 pll_full_0/divider_0/nor_1/B vdda1 7.12fF
-C1264 pll_full_0/divider_0/tspc_1/a_630_n680# vdda1 1.15fF **FLOATING
-C1265 pll_full_0/divider_0/tspc_0/Z4 vdda1 0.86fF
-C1266 pll_full_0/divider_0/tspc_0/Q vdda1 3.14fF
-C1267 pll_full_0/divider_0/tspc_0/Z3 vdda1 2.26fF
-C1268 pll_full_0/divider_0/tspc_0/Z2 vdda1 1.46fF
-C1269 pll_full_0/divider_0/tspc_0/Z1 vdda1 0.99fF
-C1270 pll_full_0/divider_0/nor_1/A vdda1 7.08fF
-C1271 pll_full_0/divider_0/tspc_0/a_630_n680# vdda1 1.15fF **FLOATING
-C1272 pll_full_0/divider_0/clk vdda1 32.57fF
-C1273 pll_full_0/divider_0/prescaler_0/Out vdda1 4.59fF
-C1274 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdda1 0.36fF
-C1275 pll_full_0/divider_0/prescaler_0/tspc_2/D vdda1 2.64fF
-C1276 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdda1 3.72fF
-C1277 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdda1 3.61fF
-C1278 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdda1 0.36fF
-C1279 pll_full_0/divider_0/prescaler_0/tspc_0/D vdda1 3.12fF
-C1280 pll_full_0/divider_0/and_0/OUT vdda1 5.67fF
-C1281 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdda1 0.86fF
-C1282 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdda1 2.26fF
-C1283 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdda1 1.46fF
-C1284 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdda1 0.99fF
-C1285 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdda1 1.16fF **FLOATING
-C1286 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdda1 2.11fF **FLOATING
-C1287 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdda1 0.86fF
-C1288 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdda1 2.26fF
-C1289 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdda1 1.48fF
-C1290 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdda1 0.99fF
-C1291 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdda1 1.14fF **FLOATING
-C1292 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdda1 4.22fF **FLOATING
-C1293 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdda1 0.86fF
-C1294 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdda1 2.26fF
-C1295 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdda1 1.19fF
-C1296 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdda1 0.99fF
-C1297 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdda1 1.47fF **FLOATING
-C1298 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdda1 2.11fF **FLOATING
-C1299 pll_full_0/divider_0/nor_1/Z1 vdda1 1.34fF
-C1300 pll_full_0/divider_0/nor_0/Z1 vdda1 1.34fF
-C1301 pll_full_0/divbuf_1/OUT vdda1 363.82fF
-C1302 pll_full_0/divbuf_1/OUT5 vdda1 350.37fF
-C1303 pll_full_0/divbuf_1/OUT4 vdda1 133.72fF
-C1304 pll_full_0/divbuf_1/OUT3 vdda1 34.03fF
-C1305 pll_full_0/divbuf_1/OUT2 vdda1 8.71fF
-C1306 pll_full_0/divbuf_1/a_492_n240# vdda1 2.46fF **FLOATING
-C1307 pll_full_0/divbuf_0/OUT5 vdda1 350.37fF
-C1308 pll_full_0/divbuf_0/OUT4 vdda1 133.72fF
-C1309 pll_full_0/divbuf_0/OUT3 vdda1 34.03fF
-C1310 pll_full_0/divbuf_0/OUT2 vdda1 8.71fF
-C1311 pll_full_0/divbuf_0/a_492_n240# vdda1 2.46fF **FLOATING
-C1312 pll_full_0/ro_complete_0/cbank_2/v vdda1 17.88fF
-C1313 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdda1 0.78fF
-C1314 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdda1 1.50fF
-C1315 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF
-C1316 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF
-C1317 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF
-C1318 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF
-C1319 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdda1 0.78fF
-C1320 pll_full_0/ro_complete_0/a0 vdda1 7.88fF
-C1321 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF
-C1322 pll_full_0/ro_complete_0/a1 vdda1 5.39fF
-C1323 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF
-C1324 pll_full_0/ro_complete_0/a3 vdda1 6.85fF
-C1325 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF
-C1326 pll_full_0/ro_complete_0/a2 vdda1 5.48fF
-C1327 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF
-C1328 pll_full_0/ro_complete_0/a4 vdda1 5.36fF
-C1329 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF
-C1330 pll_full_0/ro_complete_0/a5 vdda1 5.19fF
-C1331 pll_full_0/ro_complete_0/cbank_0/v vdda1 15.02fF
-C1332 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdda1 0.78fF
-C1333 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdda1 1.50fF
-C1334 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF
-C1335 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdda1 0.56fF
-C1336 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
-C1337 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
-C1338 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdda1 0.27fF
-C1339 pll_full_0/filter_0/a_4216_n5230# vdda1 419.25fF **FLOATING
-C1340 pll_full_0/filter_0/a_4216_n2998# vdda1 1.39fF **FLOATING
-C1341 pll_full_0/cp_0/down vdda1 1.54fF
-C1342 pll_full_0/cp_0/upbar vdda1 1.79fF
-C1343 pll_full_0/cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1344 pll_full_0/cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1345 pll_full_0/cp_0/a_7110_0# vdda1 0.17fF **FLOATING
-C1346 pll_full_0/cp_0/a_6370_0# vdda1 0.40fF **FLOATING
-C1347 pll_full_0/cp_0/a_3060_0# vdda1 2.49fF **FLOATING
-C1348 pll_full_0/cp_0/a_1710_0# vdda1 7.47fF **FLOATING
-C1349 pll_full_0/pd_0/and_pd_0/Z1 vdda1 0.39fF
-C1350 pll_full_0/pd_0/and_pd_0/Out1 vdda1 2.22fF
-C1351 pll_full_0/pd_0/tspc_r_1/z5 vdda1 1.10fF
-C1352 pll_full_0/pd_0/tspc_r_1/Z4 vdda1 1.07fF
-C1353 pll_full_0/pd_0/tspc_r_1/Qbar vdda1 0.88fF
-C1354 pll_full_0/pd_0/tspc_r_1/Z2 vdda1 1.22fF
-C1355 pll_full_0/pd_0/tspc_r_1/Z1 vdda1 0.67fF
-C1356 pll_full_0/pd_0/UP vdda1 6.61fF
-C1357 pll_full_0/pd_0/tspc_r_1/Qbar1 vdda1 1.34fF
-C1358 pll_full_0/pd_0/tspc_r_1/Z3 vdda1 2.12fF
-C1359 pll_full_0/pd_0/REF vdda1 7.29fF
-C1360 pll_full_0/pd_0/tspc_r_0/z5 vdda1 1.10fF
-C1361 pll_full_0/pd_0/tspc_r_0/Z4 vdda1 1.07fF
-C1362 pll_full_0/pd_0/R vdda1 3.05fF
-C1363 pll_full_0/pd_0/tspc_r_0/Qbar vdda1 0.79fF
-C1364 pll_full_0/pd_0/tspc_r_0/Z2 vdda1 1.22fF
-C1365 pll_full_0/pd_0/tspc_r_0/Z1 vdda1 0.67fF
-C1366 pll_full_0/pd_0/DOWN vdda1 7.24fF
-C1367 pll_full_0/pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
-C1368 pll_full_0/pd_0/tspc_r_0/Z3 vdda1 2.12fF
-C1369 pll_full_0/pd_0/DIV vdda1 372.75fF
-C1370 io_analog[5] vdda1 1865.75fF
-C1371 divbuf_4/OUT5 vdda1 350.37fF
-C1372 divbuf_4/OUT4 vdda1 133.72fF
-C1373 divbuf_4/OUT3 vdda1 34.03fF
-C1374 divbuf_4/OUT2 vdda1 8.71fF
-C1375 divbuf_4/a_492_n240# vdda1 2.46fF **FLOATING
-C1376 divbuf_3/OUT5 vdda1 393.75fF
-C1377 divbuf_3/OUT4 vdda1 134.83fF
-C1378 divbuf_3/OUT3 vdda1 34.29fF
-C1379 divbuf_3/OUT2 vdda1 8.77fF
-C1380 divbuf_3/a_492_n240# vdda1 2.59fF **FLOATING
-C1381 divbuf_2/OUT5 vdda1 350.37fF
-C1382 divbuf_2/OUT4 vdda1 133.72fF
-C1383 divbuf_2/OUT3 vdda1 34.03fF
-C1384 divbuf_2/OUT2 vdda1 8.71fF
-C1385 divbuf_2/IN vdda1 43.96fF
-C1386 divbuf_2/a_492_n240# vdda1 2.46fF **FLOATING
-C1387 divbuf_1/OUT5 vdda1 393.75fF
-C1388 divbuf_1/OUT4 vdda1 134.83fF
-C1389 divbuf_1/OUT3 vdda1 34.29fF
-C1390 divbuf_1/OUT2 vdda1 8.77fF
-C1391 divbuf_1/a_492_n240# vdda1 2.46fF **FLOATING
-C1392 divbuf_0/OUT5 vdda1 393.75fF
-C1393 divbuf_0/OUT4 vdda1 134.83fF
-C1394 divbuf_0/OUT3 vdda1 34.29fF
-C1395 divbuf_0/OUT2 vdda1 8.77fF
-C1396 divbuf_0/a_492_n240# vdda1 2.46fF **FLOATING
-C1397 ro_complete_0/cbank_2/v vdda1 17.89fF
-C1398 ro_complete_0/cbank_2/switch_5/vin vdda1 0.87fF
-C1399 ro_complete_0/cbank_2/switch_4/vin vdda1 1.63fF
-C1400 ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF
-C1401 ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF
-C1402 ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF
-C1403 ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF
-C1404 divbuf_4/IN vdda1 19.88fF
-C1405 ro_complete_0/cbank_1/switch_5/vin vdda1 0.87fF
-C1406 ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF
-C1407 gpio_analog[13] vdda1 69.60fF
-C1408 ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF
-C1409 ro_complete_0/a3 vdda1 26.74fF
-C1410 ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF
-C1411 ro_complete_0/a2 vdda1 20.30fF
-C1412 ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF
-C1413 ro_complete_0/a4 vdda1 33.91fF
-C1414 ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF
-C1415 gpio_analog[14] vdda1 127.21fF
-C1416 ro_complete_0/cbank_0/v vdda1 17.14fF
-C1417 ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF
-C1418 ro_complete_0/cbank_0/switch_3/vin vdda1 0.76fF
-C1419 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
-C1420 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
-C1421 ro_complete_0/ro_var_extend_0/vcont vdda1 0.27fF
-C1422 gpio_noesd[15] vdda1 179.74fF
-C1423 filter_0/a_4216_n5230# vdda1 418.47fF **FLOATING
-C1424 filter_0/a_4216_n2998# vdda1 1.03fF **FLOATING
-C1425 io_analog[1] vdda1 61.29fF
-C1426 io_analog[0] vdda1 37.70fF
-C1427 cp_0/upbar vdda1 1.79fF
-C1428 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1429 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1430 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
-C1431 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
-C1432 cp_0/a_3060_0# vdda1 4.16fF **FLOATING
-C1433 cp_0/a_1710_0# vdda1 6.63fF **FLOATING
-C1434 cp_0/a_10_n50# vdda1 3.15fF **FLOATING
-C1435 pd_0/and_pd_0/Z1 vdda1 0.39fF
-C1436 pd_0/and_pd_0/Out1 vdda1 2.22fF
-C1437 pd_0/tspc_r_1/z5 vdda1 1.14fF
-C1438 pd_0/tspc_r_1/Z4 vdda1 1.09fF
-C1439 pd_0/tspc_r_1/Qbar vdda1 0.88fF
-C1440 pd_0/tspc_r_1/Z2 vdda1 1.41fF
-C1441 pd_0/tspc_r_1/Z1 vdda1 0.84fF
-C1442 pd_0/UP vdda1 7.59fF
-C1443 pd_0/tspc_r_1/Qbar1 vdda1 1.46fF
-C1444 pd_0/tspc_r_1/Z3 vdda1 2.78fF
-C1445 pd_0/tspc_r_0/z5 vdda1 1.10fF
-C1446 pd_0/tspc_r_0/Z4 vdda1 1.07fF
-C1447 pd_0/R vdda1 3.66fF
-C1448 pd_0/tspc_r_0/Qbar vdda1 0.79fF
-C1449 pd_0/tspc_r_0/Z2 vdda1 1.22fF
-C1450 pd_0/tspc_r_0/Z1 vdda1 0.67fF
-C1451 pd_0/DOWN vdda1 10.38fF
-C1452 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
-C1453 pd_0/tspc_r_0/Z3 vdda1 2.12fF
-C1454 pd_0/DIV vdda1 399.71fF
-C1455 io_analog[6] vdda1 39.54fF
-C1456 io_analog[7] vdda1 31.85fF
-C1457 ashish_0/a_150_n710# vdda1 3.84fF **FLOATING
-C1458 ashish_0/a_150_0# vdda1 1.41fF **FLOATING
+C121 io_analog[4] vdda1 43.84fF
+C122 io_in_3v3[0] vdda1 0.61fF
+C123 io_oeb[26] vdda1 0.61fF
+C124 io_in[0] vdda1 0.61fF
+C125 io_out[26] vdda1 0.61fF
+C126 io_out[0] vdda1 0.61fF
+C127 io_in[26] vdda1 0.61fF
+C128 io_oeb[0] vdda1 0.61fF
+C129 io_in_3v3[26] vdda1 0.61fF
+C130 io_in_3v3[1] vdda1 0.61fF
+C131 io_oeb[25] vdda1 0.61fF
+C132 io_in[1] vdda1 0.61fF
+C133 io_out[25] vdda1 0.61fF
+C134 io_out[1] vdda1 0.61fF
+C135 io_in[25] vdda1 0.61fF
+C136 io_oeb[1] vdda1 0.61fF
+C137 io_in_3v3[25] vdda1 0.61fF
+C138 io_in_3v3[2] vdda1 0.61fF
+C139 io_oeb[24] vdda1 0.61fF
+C140 io_in[2] vdda1 0.61fF
+C141 io_out[24] vdda1 0.61fF
+C142 io_out[2] vdda1 0.61fF
+C143 io_in[24] vdda1 0.61fF
+C144 io_oeb[2] vdda1 0.61fF
+C145 io_in_3v3[24] vdda1 0.61fF
+C146 io_in_3v3[3] vdda1 0.61fF
+C147 gpio_noesd[17] vdda1 0.61fF
+C148 io_in[3] vdda1 0.61fF
+C149 io_out[3] vdda1 0.61fF
+C150 io_oeb[3] vdda1 0.61fF
+C151 io_in_3v3[4] vdda1 0.61fF
+C152 io_in[4] vdda1 0.61fF
+C153 io_out[4] vdda1 0.61fF
+C154 io_oeb[4] vdda1 0.61fF
+C155 io_in_3v3[5] vdda1 0.61fF
+C156 io_in[5] vdda1 0.61fF
+C157 io_out[5] vdda1 0.61fF
+C158 io_oeb[5] vdda1 0.61fF
+C159 io_in_3v3[6] vdda1 0.61fF
+C160 io_in[6] vdda1 0.61fF
+C161 io_out[6] vdda1 0.61fF
+C162 io_oeb[6] vdda1 0.61fF
+C163 vssd1 vdda1 604.65fF
+C164 gpio_analog[17] vdda1 187.27fF
+C165 io_oeb[23] vdda1 0.61fF
+C166 io_out[23] vdda1 0.61fF
+C167 io_in[23] vdda1 0.61fF
+C168 io_in_3v3[23] vdda1 0.61fF
+C169 gpio_noesd[16] vdda1 0.61fF
+C170 gpio_analog[16] vdda1 177.29fF
+C171 io_oeb[22] vdda1 0.61fF
+C172 io_out[22] vdda1 0.61fF
+C173 io_in[22] vdda1 0.61fF
+C174 io_in_3v3[22] vdda1 0.61fF
+C175 io_oeb[21] vdda1 0.61fF
+C176 io_out[21] vdda1 0.61fF
+C177 io_in[21] vdda1 0.61fF
+C178 gpio_analog[15] vdda1 145.89fF
+C179 io_in_3v3[21] vdda1 0.61fF
+C180 gpio_noesd[14] vdda1 0.61fF
+C181 vssd2 vdda1 13.04fF
+C182 vdda2 vdda1 13.04fF
+C183 gpio_analog[0] vdda1 0.61fF
+C184 gpio_noesd[0] vdda1 0.61fF
+C185 io_in_3v3[7] vdda1 0.61fF
+C186 io_in[7] vdda1 0.61fF
+C187 io_out[7] vdda1 0.61fF
+C188 io_oeb[7] vdda1 0.61fF
+C189 gpio_analog[1] vdda1 0.61fF
+C190 gpio_noesd[1] vdda1 0.61fF
+C191 io_in_3v3[8] vdda1 0.61fF
+C192 io_oeb[20] vdda1 0.61fF
+C193 io_out[20] vdda1 0.61fF
+C194 io_in[20] vdda1 0.61fF
+C195 io_in_3v3[20] vdda1 0.61fF
+C196 gpio_noesd[13] vdda1 0.61fF
+C197 io_oeb[19] vdda1 0.61fF
+C198 io_out[19] vdda1 0.61fF
+C199 io_in[19] vdda1 0.61fF
+C200 io_in_3v3[19] vdda1 0.61fF
+C201 gpio_noesd[12] vdda1 0.61fF
+C202 io_in[8] vdda1 0.61fF
+C203 io_out[8] vdda1 0.61fF
+C204 io_oeb[8] vdda1 0.61fF
+C205 gpio_analog[2] vdda1 0.61fF
+C206 gpio_noesd[2] vdda1 0.61fF
+C207 io_in_3v3[9] vdda1 0.61fF
+C208 io_in[9] vdda1 0.61fF
+C209 io_out[9] vdda1 0.61fF
+C210 io_oeb[9] vdda1 0.61fF
+C211 io_oeb[18] vdda1 0.61fF
+C212 io_out[18] vdda1 0.61fF
+C213 io_in[18] vdda1 0.61fF
+C214 io_in_3v3[18] vdda1 0.61fF
+C215 gpio_noesd[11] vdda1 0.61fF
+C216 gpio_analog[11] vdda1 0.61fF
+C217 io_oeb[17] vdda1 0.61fF
+C218 io_out[17] vdda1 0.61fF
+C219 io_in[17] vdda1 0.61fF
+C220 io_in_3v3[17] vdda1 0.61fF
+C221 gpio_noesd[10] vdda1 0.61fF
+C222 gpio_analog[10] vdda1 0.61fF
+C223 gpio_analog[3] vdda1 0.61fF
+C224 gpio_noesd[3] vdda1 0.61fF
+C225 io_in_3v3[10] vdda1 0.61fF
+C226 io_in[10] vdda1 0.61fF
+C227 io_out[10] vdda1 0.61fF
+C228 io_oeb[10] vdda1 0.61fF
+C229 io_oeb[16] vdda1 0.61fF
+C230 gpio_analog[4] vdda1 0.61fF
+C231 gpio_noesd[4] vdda1 0.61fF
+C232 io_in_3v3[11] vdda1 0.61fF
+C233 io_in[11] vdda1 0.61fF
+C234 io_out[11] vdda1 0.61fF
+C235 io_oeb[11] vdda1 0.61fF
+C236 io_out[16] vdda1 0.61fF
+C237 io_in[16] vdda1 0.61fF
+C238 io_in_3v3[16] vdda1 0.61fF
+C239 gpio_noesd[9] vdda1 0.61fF
+C240 gpio_analog[9] vdda1 0.61fF
+C241 io_oeb[15] vdda1 0.61fF
+C242 io_out[15] vdda1 0.61fF
+C243 io_in[15] vdda1 0.61fF
+C244 io_in_3v3[15] vdda1 0.61fF
+C245 gpio_noesd[8] vdda1 0.61fF
+C246 gpio_analog[8] vdda1 0.61fF
+C247 gpio_analog[5] vdda1 0.61fF
+C248 gpio_noesd[5] vdda1 0.61fF
+C249 io_in_3v3[12] vdda1 0.61fF
+C250 io_in[12] vdda1 0.61fF
+C251 io_out[12] vdda1 0.61fF
+C252 io_oeb[12] vdda1 0.61fF
+C253 io_oeb[14] vdda1 0.61fF
+C254 io_out[14] vdda1 0.61fF
+C255 io_in[14] vdda1 0.61fF
+C256 io_in_3v3[14] vdda1 0.61fF
+C257 gpio_noesd[7] vdda1 0.61fF
+C258 vssa2 vdda1 13.04fF
+C259 gpio_analog[6] vdda1 0.61fF
+C260 gpio_noesd[6] vdda1 0.61fF
+C261 io_in_3v3[13] vdda1 0.61fF
+C262 io_in[13] vdda1 0.61fF
+C263 io_out[13] vdda1 0.61fF
+C264 io_oeb[13] vdda1 0.61fF
+C265 vccd1 vdda1 13.04fF
+C266 vccd2 vdda1 13.04fF
+C267 io_analog[10] vdda1 9.60fF
+C268 io_analog[3] vdda1 64.72fF
+C269 io_clamp_high[0] vdda1 3.58fF
+C270 io_clamp_low[0] vdda1 3.58fF
+C271 io_clamp_high[1] vdda1 3.58fF
+C272 io_clamp_low[1] vdda1 3.58fF
+C273 io_clamp_high[2] vdda1 3.58fF
+C274 io_clamp_low[2] vdda1 3.58fF
+C275 io_analog[8] vdda1 6.83fF
+C276 io_analog[9] vdda1 18.05fF
+C277 user_irq[2] vdda1 0.63fF
+C278 user_irq[1] vdda1 0.63fF
+C279 user_irq[0] vdda1 0.63fF
+C280 user_clock2 vdda1 0.63fF
+C281 la_oenb[127] vdda1 0.63fF
+C282 la_data_out[127] vdda1 0.63fF
+C283 la_data_in[127] vdda1 0.63fF
+C284 la_oenb[126] vdda1 0.63fF
+C285 la_data_out[126] vdda1 0.63fF
+C286 la_data_in[126] vdda1 0.63fF
+C287 la_oenb[125] vdda1 0.63fF
+C288 la_data_out[125] vdda1 0.63fF
+C289 la_data_in[125] vdda1 0.63fF
+C290 la_oenb[124] vdda1 0.63fF
+C291 la_data_out[124] vdda1 0.63fF
+C292 la_data_in[124] vdda1 0.63fF
+C293 la_oenb[123] vdda1 0.63fF
+C294 la_data_out[123] vdda1 0.63fF
+C295 la_data_in[123] vdda1 0.63fF
+C296 la_oenb[122] vdda1 0.63fF
+C297 la_data_out[122] vdda1 0.63fF
+C298 la_data_in[122] vdda1 0.63fF
+C299 la_oenb[121] vdda1 0.63fF
+C300 la_data_out[121] vdda1 0.63fF
+C301 la_data_in[121] vdda1 0.63fF
+C302 la_oenb[120] vdda1 0.63fF
+C303 la_data_out[120] vdda1 0.63fF
+C304 la_data_in[120] vdda1 0.63fF
+C305 la_oenb[119] vdda1 0.63fF
+C306 la_data_out[119] vdda1 0.63fF
+C307 la_data_in[119] vdda1 0.63fF
+C308 la_oenb[118] vdda1 0.63fF
+C309 la_data_out[118] vdda1 0.63fF
+C310 la_data_in[118] vdda1 0.63fF
+C311 la_oenb[117] vdda1 0.63fF
+C312 la_data_out[117] vdda1 0.63fF
+C313 la_data_in[117] vdda1 0.63fF
+C314 la_oenb[116] vdda1 0.63fF
+C315 la_data_out[116] vdda1 0.63fF
+C316 la_data_in[116] vdda1 0.63fF
+C317 la_oenb[115] vdda1 0.63fF
+C318 la_data_out[115] vdda1 0.63fF
+C319 la_data_in[115] vdda1 0.63fF
+C320 la_oenb[114] vdda1 0.63fF
+C321 la_data_out[114] vdda1 0.63fF
+C322 la_data_in[114] vdda1 0.63fF
+C323 la_oenb[113] vdda1 0.63fF
+C324 la_data_out[113] vdda1 0.63fF
+C325 la_data_in[113] vdda1 0.63fF
+C326 la_oenb[112] vdda1 0.63fF
+C327 la_data_out[112] vdda1 0.63fF
+C328 la_data_in[112] vdda1 0.63fF
+C329 la_oenb[111] vdda1 0.63fF
+C330 la_data_out[111] vdda1 0.63fF
+C331 la_data_in[111] vdda1 0.63fF
+C332 la_oenb[110] vdda1 0.63fF
+C333 la_data_out[110] vdda1 0.63fF
+C334 la_data_in[110] vdda1 0.63fF
+C335 la_oenb[109] vdda1 0.63fF
+C336 la_data_out[109] vdda1 0.63fF
+C337 la_data_in[109] vdda1 0.63fF
+C338 la_oenb[108] vdda1 0.63fF
+C339 la_data_out[108] vdda1 0.63fF
+C340 la_data_in[108] vdda1 0.63fF
+C341 la_oenb[107] vdda1 0.63fF
+C342 la_data_out[107] vdda1 0.63fF
+C343 la_data_in[107] vdda1 0.63fF
+C344 la_oenb[106] vdda1 0.63fF
+C345 la_data_out[106] vdda1 0.63fF
+C346 la_data_in[106] vdda1 0.63fF
+C347 la_oenb[105] vdda1 0.63fF
+C348 la_data_out[105] vdda1 0.63fF
+C349 la_data_in[105] vdda1 0.63fF
+C350 la_oenb[104] vdda1 0.63fF
+C351 la_data_out[104] vdda1 0.63fF
+C352 la_data_in[104] vdda1 0.63fF
+C353 la_oenb[103] vdda1 0.63fF
+C354 la_data_out[103] vdda1 0.63fF
+C355 la_data_in[103] vdda1 0.63fF
+C356 la_oenb[102] vdda1 0.63fF
+C357 la_data_out[102] vdda1 0.63fF
+C358 la_data_in[102] vdda1 0.63fF
+C359 la_oenb[101] vdda1 0.63fF
+C360 la_data_out[101] vdda1 0.63fF
+C361 la_data_in[101] vdda1 0.63fF
+C362 la_oenb[100] vdda1 0.63fF
+C363 la_data_out[100] vdda1 0.63fF
+C364 la_data_in[100] vdda1 0.63fF
+C365 la_oenb[99] vdda1 0.63fF
+C366 la_data_out[99] vdda1 0.63fF
+C367 la_data_in[99] vdda1 0.63fF
+C368 la_oenb[98] vdda1 0.63fF
+C369 la_data_out[98] vdda1 0.63fF
+C370 la_data_in[98] vdda1 0.63fF
+C371 la_oenb[97] vdda1 0.63fF
+C372 la_data_out[97] vdda1 0.63fF
+C373 la_data_in[97] vdda1 0.63fF
+C374 la_oenb[96] vdda1 0.63fF
+C375 la_data_out[96] vdda1 0.63fF
+C376 la_data_in[96] vdda1 0.63fF
+C377 la_oenb[95] vdda1 0.63fF
+C378 la_data_out[95] vdda1 0.63fF
+C379 la_data_in[95] vdda1 0.63fF
+C380 la_oenb[94] vdda1 0.63fF
+C381 la_data_out[94] vdda1 0.63fF
+C382 la_data_in[94] vdda1 0.63fF
+C383 la_oenb[93] vdda1 0.63fF
+C384 la_data_out[93] vdda1 0.63fF
+C385 la_data_in[93] vdda1 0.63fF
+C386 la_oenb[92] vdda1 0.63fF
+C387 la_data_out[92] vdda1 0.63fF
+C388 la_data_in[92] vdda1 0.63fF
+C389 la_oenb[91] vdda1 0.63fF
+C390 la_data_out[91] vdda1 0.63fF
+C391 la_data_in[91] vdda1 0.63fF
+C392 la_oenb[90] vdda1 0.63fF
+C393 la_data_out[90] vdda1 0.63fF
+C394 la_data_in[90] vdda1 0.63fF
+C395 la_oenb[89] vdda1 0.63fF
+C396 la_data_out[89] vdda1 0.63fF
+C397 la_data_in[89] vdda1 0.63fF
+C398 la_oenb[88] vdda1 0.63fF
+C399 la_data_out[88] vdda1 0.63fF
+C400 la_data_in[88] vdda1 0.63fF
+C401 la_oenb[87] vdda1 0.63fF
+C402 la_data_out[87] vdda1 0.63fF
+C403 la_data_in[87] vdda1 0.63fF
+C404 la_oenb[86] vdda1 0.63fF
+C405 la_data_out[86] vdda1 0.63fF
+C406 la_data_in[86] vdda1 0.63fF
+C407 la_oenb[85] vdda1 0.63fF
+C408 la_data_out[85] vdda1 0.63fF
+C409 la_data_in[85] vdda1 0.63fF
+C410 la_oenb[84] vdda1 0.63fF
+C411 la_data_out[84] vdda1 0.63fF
+C412 la_data_in[84] vdda1 0.63fF
+C413 la_oenb[83] vdda1 0.63fF
+C414 la_data_out[83] vdda1 0.63fF
+C415 la_data_in[83] vdda1 0.63fF
+C416 la_oenb[82] vdda1 0.63fF
+C417 la_data_out[82] vdda1 0.63fF
+C418 la_data_in[82] vdda1 0.63fF
+C419 la_oenb[81] vdda1 0.63fF
+C420 la_data_out[81] vdda1 0.63fF
+C421 la_data_in[81] vdda1 0.63fF
+C422 la_oenb[80] vdda1 0.63fF
+C423 la_data_out[80] vdda1 0.63fF
+C424 la_data_in[80] vdda1 0.63fF
+C425 la_oenb[79] vdda1 0.63fF
+C426 la_data_out[79] vdda1 0.63fF
+C427 la_data_in[79] vdda1 0.63fF
+C428 la_oenb[78] vdda1 0.63fF
+C429 la_data_out[78] vdda1 0.63fF
+C430 la_data_in[78] vdda1 0.63fF
+C431 la_oenb[77] vdda1 0.63fF
+C432 la_data_out[77] vdda1 0.63fF
+C433 la_data_in[77] vdda1 0.63fF
+C434 la_oenb[76] vdda1 0.63fF
+C435 la_data_out[76] vdda1 0.63fF
+C436 la_data_in[76] vdda1 0.63fF
+C437 la_oenb[75] vdda1 0.63fF
+C438 la_data_out[75] vdda1 0.63fF
+C439 la_data_in[75] vdda1 0.63fF
+C440 la_oenb[74] vdda1 0.63fF
+C441 la_data_out[74] vdda1 0.63fF
+C442 la_data_in[74] vdda1 0.63fF
+C443 la_oenb[73] vdda1 0.63fF
+C444 la_data_out[73] vdda1 0.63fF
+C445 la_data_in[73] vdda1 0.63fF
+C446 la_oenb[72] vdda1 0.63fF
+C447 la_data_out[72] vdda1 0.63fF
+C448 la_data_in[72] vdda1 0.63fF
+C449 la_oenb[71] vdda1 0.63fF
+C450 la_data_out[71] vdda1 0.63fF
+C451 la_data_in[71] vdda1 0.63fF
+C452 la_oenb[70] vdda1 0.63fF
+C453 la_data_out[70] vdda1 0.63fF
+C454 la_data_in[70] vdda1 0.63fF
+C455 la_oenb[69] vdda1 0.63fF
+C456 la_data_out[69] vdda1 0.63fF
+C457 la_data_in[69] vdda1 0.63fF
+C458 la_oenb[68] vdda1 0.63fF
+C459 la_data_out[68] vdda1 0.63fF
+C460 la_data_in[68] vdda1 0.63fF
+C461 la_oenb[67] vdda1 0.63fF
+C462 la_data_out[67] vdda1 0.63fF
+C463 la_data_in[67] vdda1 0.63fF
+C464 la_oenb[66] vdda1 0.63fF
+C465 la_data_out[66] vdda1 0.63fF
+C466 la_data_in[66] vdda1 0.63fF
+C467 la_oenb[65] vdda1 0.63fF
+C468 la_data_out[65] vdda1 0.63fF
+C469 la_data_in[65] vdda1 0.63fF
+C470 la_oenb[64] vdda1 0.63fF
+C471 la_data_out[64] vdda1 0.63fF
+C472 la_data_in[64] vdda1 0.63fF
+C473 la_oenb[63] vdda1 0.63fF
+C474 la_data_out[63] vdda1 0.63fF
+C475 la_data_in[63] vdda1 0.63fF
+C476 la_oenb[62] vdda1 0.63fF
+C477 la_data_out[62] vdda1 0.63fF
+C478 la_data_in[62] vdda1 0.63fF
+C479 la_oenb[61] vdda1 0.63fF
+C480 la_data_out[61] vdda1 0.63fF
+C481 la_data_in[61] vdda1 0.63fF
+C482 la_oenb[60] vdda1 0.63fF
+C483 la_data_out[60] vdda1 0.63fF
+C484 la_data_in[60] vdda1 0.63fF
+C485 la_oenb[59] vdda1 0.63fF
+C486 la_data_out[59] vdda1 0.63fF
+C487 la_data_in[59] vdda1 0.63fF
+C488 la_oenb[58] vdda1 0.63fF
+C489 la_data_out[58] vdda1 0.63fF
+C490 la_data_in[58] vdda1 0.63fF
+C491 la_oenb[57] vdda1 0.63fF
+C492 la_data_out[57] vdda1 0.63fF
+C493 la_data_in[57] vdda1 0.63fF
+C494 la_oenb[56] vdda1 0.63fF
+C495 la_data_out[56] vdda1 0.63fF
+C496 la_data_in[56] vdda1 0.63fF
+C497 la_oenb[55] vdda1 0.63fF
+C498 la_data_out[55] vdda1 0.63fF
+C499 la_data_in[55] vdda1 0.63fF
+C500 la_oenb[54] vdda1 0.63fF
+C501 la_data_out[54] vdda1 0.63fF
+C502 la_data_in[54] vdda1 0.63fF
+C503 la_oenb[53] vdda1 0.63fF
+C504 la_data_out[53] vdda1 0.63fF
+C505 la_data_in[53] vdda1 0.63fF
+C506 la_oenb[52] vdda1 0.63fF
+C507 la_data_out[52] vdda1 0.63fF
+C508 la_data_in[52] vdda1 0.63fF
+C509 la_oenb[51] vdda1 0.63fF
+C510 la_data_out[51] vdda1 0.63fF
+C511 la_data_in[51] vdda1 0.63fF
+C512 la_oenb[50] vdda1 0.63fF
+C513 la_data_out[50] vdda1 0.63fF
+C514 la_data_in[50] vdda1 0.63fF
+C515 la_oenb[49] vdda1 0.63fF
+C516 la_data_out[49] vdda1 0.63fF
+C517 la_data_in[49] vdda1 0.63fF
+C518 la_oenb[48] vdda1 0.63fF
+C519 la_data_out[48] vdda1 0.63fF
+C520 la_data_in[48] vdda1 0.63fF
+C521 la_oenb[47] vdda1 0.63fF
+C522 la_data_out[47] vdda1 0.63fF
+C523 la_data_in[47] vdda1 0.63fF
+C524 la_oenb[46] vdda1 0.63fF
+C525 la_data_out[46] vdda1 0.63fF
+C526 la_data_in[46] vdda1 0.63fF
+C527 la_oenb[45] vdda1 0.63fF
+C528 la_data_out[45] vdda1 0.63fF
+C529 la_data_in[45] vdda1 0.63fF
+C530 la_oenb[44] vdda1 0.63fF
+C531 la_data_out[44] vdda1 0.63fF
+C532 la_data_in[44] vdda1 0.63fF
+C533 la_oenb[43] vdda1 0.63fF
+C534 la_data_out[43] vdda1 0.63fF
+C535 la_data_in[43] vdda1 0.63fF
+C536 la_oenb[42] vdda1 0.63fF
+C537 la_data_out[42] vdda1 0.63fF
+C538 la_data_in[42] vdda1 0.63fF
+C539 la_oenb[41] vdda1 0.63fF
+C540 la_data_out[41] vdda1 0.63fF
+C541 la_data_in[41] vdda1 0.63fF
+C542 la_oenb[40] vdda1 0.63fF
+C543 la_data_out[40] vdda1 0.63fF
+C544 la_data_in[40] vdda1 0.63fF
+C545 la_oenb[39] vdda1 0.63fF
+C546 la_data_out[39] vdda1 0.63fF
+C547 la_data_in[39] vdda1 0.63fF
+C548 la_oenb[38] vdda1 0.63fF
+C549 la_data_out[38] vdda1 0.63fF
+C550 la_data_in[38] vdda1 0.63fF
+C551 la_oenb[37] vdda1 0.63fF
+C552 la_data_out[37] vdda1 0.63fF
+C553 la_data_in[37] vdda1 0.63fF
+C554 la_oenb[36] vdda1 0.63fF
+C555 la_data_out[36] vdda1 0.63fF
+C556 la_data_in[36] vdda1 0.63fF
+C557 la_oenb[35] vdda1 0.63fF
+C558 la_data_out[35] vdda1 0.63fF
+C559 la_data_in[35] vdda1 0.63fF
+C560 la_oenb[34] vdda1 0.63fF
+C561 la_data_out[34] vdda1 0.63fF
+C562 la_data_in[34] vdda1 0.63fF
+C563 la_oenb[33] vdda1 0.63fF
+C564 la_data_out[33] vdda1 0.63fF
+C565 la_data_in[33] vdda1 0.63fF
+C566 la_oenb[32] vdda1 0.63fF
+C567 la_data_out[32] vdda1 0.63fF
+C568 la_data_in[32] vdda1 0.63fF
+C569 la_oenb[31] vdda1 0.63fF
+C570 la_data_out[31] vdda1 0.63fF
+C571 la_data_in[31] vdda1 0.63fF
+C572 la_oenb[30] vdda1 0.63fF
+C573 la_data_out[30] vdda1 0.63fF
+C574 la_data_in[30] vdda1 0.63fF
+C575 la_oenb[29] vdda1 0.63fF
+C576 la_data_out[29] vdda1 0.63fF
+C577 la_data_in[29] vdda1 0.63fF
+C578 la_oenb[28] vdda1 0.63fF
+C579 la_data_out[28] vdda1 0.63fF
+C580 la_data_in[28] vdda1 0.63fF
+C581 la_oenb[27] vdda1 0.63fF
+C582 la_data_out[27] vdda1 0.63fF
+C583 la_data_in[27] vdda1 0.63fF
+C584 la_oenb[26] vdda1 0.63fF
+C585 la_data_out[26] vdda1 0.63fF
+C586 la_data_in[26] vdda1 0.63fF
+C587 la_oenb[25] vdda1 0.63fF
+C588 la_data_out[25] vdda1 0.63fF
+C589 la_data_in[25] vdda1 0.63fF
+C590 la_oenb[24] vdda1 0.63fF
+C591 la_data_out[24] vdda1 0.63fF
+C592 la_data_in[24] vdda1 0.63fF
+C593 la_oenb[23] vdda1 0.63fF
+C594 la_data_out[23] vdda1 0.63fF
+C595 la_data_in[23] vdda1 0.63fF
+C596 la_oenb[22] vdda1 0.63fF
+C597 la_data_out[22] vdda1 0.63fF
+C598 la_data_in[22] vdda1 0.63fF
+C599 la_oenb[21] vdda1 0.63fF
+C600 la_data_out[21] vdda1 0.63fF
+C601 la_data_in[21] vdda1 0.63fF
+C602 la_oenb[20] vdda1 0.63fF
+C603 la_data_out[20] vdda1 0.63fF
+C604 la_data_in[20] vdda1 0.63fF
+C605 la_oenb[19] vdda1 0.63fF
+C606 la_data_out[19] vdda1 0.63fF
+C607 la_data_in[19] vdda1 0.63fF
+C608 la_oenb[18] vdda1 0.63fF
+C609 la_data_out[18] vdda1 0.63fF
+C610 la_data_in[18] vdda1 0.63fF
+C611 la_oenb[17] vdda1 0.63fF
+C612 la_data_out[17] vdda1 0.63fF
+C613 la_data_in[17] vdda1 0.63fF
+C614 la_oenb[16] vdda1 0.63fF
+C615 la_data_out[16] vdda1 0.63fF
+C616 la_data_in[16] vdda1 0.63fF
+C617 la_oenb[15] vdda1 0.63fF
+C618 la_data_out[15] vdda1 0.63fF
+C619 la_data_in[15] vdda1 0.63fF
+C620 la_oenb[14] vdda1 0.63fF
+C621 la_data_out[14] vdda1 0.63fF
+C622 la_data_in[14] vdda1 0.63fF
+C623 la_oenb[13] vdda1 0.63fF
+C624 la_data_out[13] vdda1 0.63fF
+C625 la_data_in[13] vdda1 0.63fF
+C626 la_oenb[12] vdda1 0.63fF
+C627 la_data_out[12] vdda1 0.63fF
+C628 la_data_in[12] vdda1 0.63fF
+C629 la_oenb[11] vdda1 0.63fF
+C630 la_data_out[11] vdda1 0.63fF
+C631 la_data_in[11] vdda1 0.63fF
+C632 la_oenb[10] vdda1 0.63fF
+C633 la_data_out[10] vdda1 0.63fF
+C634 la_data_in[10] vdda1 0.63fF
+C635 la_oenb[9] vdda1 0.63fF
+C636 la_data_out[9] vdda1 0.63fF
+C637 la_data_in[9] vdda1 0.63fF
+C638 la_oenb[8] vdda1 0.63fF
+C639 la_data_out[8] vdda1 0.63fF
+C640 la_data_in[8] vdda1 0.63fF
+C641 la_oenb[7] vdda1 0.63fF
+C642 la_data_out[7] vdda1 0.63fF
+C643 la_data_in[7] vdda1 0.63fF
+C644 la_oenb[6] vdda1 0.63fF
+C645 la_data_out[6] vdda1 0.63fF
+C646 la_data_in[6] vdda1 0.63fF
+C647 la_oenb[5] vdda1 0.63fF
+C648 la_data_out[5] vdda1 0.63fF
+C649 la_data_in[5] vdda1 0.63fF
+C650 la_oenb[4] vdda1 0.63fF
+C651 la_data_out[4] vdda1 0.63fF
+C652 la_data_in[4] vdda1 0.63fF
+C653 la_oenb[3] vdda1 0.63fF
+C654 la_data_out[3] vdda1 0.63fF
+C655 la_data_in[3] vdda1 0.63fF
+C656 la_oenb[2] vdda1 0.63fF
+C657 la_data_out[2] vdda1 0.63fF
+C658 la_data_in[2] vdda1 0.63fF
+C659 la_oenb[1] vdda1 0.63fF
+C660 la_data_out[1] vdda1 0.63fF
+C661 la_data_in[1] vdda1 0.63fF
+C662 la_oenb[0] vdda1 0.63fF
+C663 la_data_out[0] vdda1 0.63fF
+C664 la_data_in[0] vdda1 0.63fF
+C665 wbs_dat_o[31] vdda1 0.63fF
+C666 wbs_dat_i[31] vdda1 0.63fF
+C667 wbs_adr_i[31] vdda1 0.63fF
+C668 wbs_dat_o[30] vdda1 0.63fF
+C669 wbs_dat_i[30] vdda1 0.63fF
+C670 wbs_adr_i[30] vdda1 0.63fF
+C671 wbs_dat_o[29] vdda1 0.63fF
+C672 wbs_dat_i[29] vdda1 0.63fF
+C673 wbs_adr_i[29] vdda1 0.63fF
+C674 wbs_dat_o[28] vdda1 0.63fF
+C675 wbs_dat_i[28] vdda1 0.63fF
+C676 wbs_adr_i[28] vdda1 0.63fF
+C677 wbs_dat_o[27] vdda1 0.63fF
+C678 wbs_dat_i[27] vdda1 0.63fF
+C679 wbs_adr_i[27] vdda1 0.63fF
+C680 wbs_dat_o[26] vdda1 0.63fF
+C681 wbs_dat_i[26] vdda1 0.63fF
+C682 wbs_adr_i[26] vdda1 0.63fF
+C683 wbs_dat_o[25] vdda1 0.63fF
+C684 wbs_dat_i[25] vdda1 0.63fF
+C685 wbs_adr_i[25] vdda1 0.63fF
+C686 wbs_dat_o[24] vdda1 0.63fF
+C687 wbs_dat_i[24] vdda1 0.63fF
+C688 wbs_adr_i[24] vdda1 0.63fF
+C689 wbs_dat_o[23] vdda1 0.63fF
+C690 wbs_dat_i[23] vdda1 0.63fF
+C691 wbs_adr_i[23] vdda1 0.63fF
+C692 wbs_dat_o[22] vdda1 0.63fF
+C693 wbs_dat_i[22] vdda1 0.63fF
+C694 wbs_adr_i[22] vdda1 0.63fF
+C695 wbs_dat_o[21] vdda1 0.63fF
+C696 wbs_dat_i[21] vdda1 0.63fF
+C697 wbs_adr_i[21] vdda1 0.63fF
+C698 wbs_dat_o[20] vdda1 0.63fF
+C699 wbs_dat_i[20] vdda1 0.63fF
+C700 wbs_adr_i[20] vdda1 0.63fF
+C701 wbs_dat_o[19] vdda1 0.63fF
+C702 wbs_dat_i[19] vdda1 0.63fF
+C703 wbs_adr_i[19] vdda1 0.63fF
+C704 wbs_dat_o[18] vdda1 0.63fF
+C705 wbs_dat_i[18] vdda1 0.63fF
+C706 wbs_adr_i[18] vdda1 0.63fF
+C707 wbs_dat_o[17] vdda1 0.63fF
+C708 wbs_dat_i[17] vdda1 0.63fF
+C709 wbs_adr_i[17] vdda1 0.63fF
+C710 wbs_dat_o[16] vdda1 0.63fF
+C711 wbs_dat_i[16] vdda1 0.63fF
+C712 wbs_adr_i[16] vdda1 0.63fF
+C713 wbs_dat_o[15] vdda1 0.63fF
+C714 wbs_dat_i[15] vdda1 0.63fF
+C715 wbs_adr_i[15] vdda1 0.63fF
+C716 wbs_dat_o[14] vdda1 0.63fF
+C717 wbs_dat_i[14] vdda1 0.63fF
+C718 wbs_adr_i[14] vdda1 0.63fF
+C719 wbs_dat_o[13] vdda1 0.63fF
+C720 wbs_dat_i[13] vdda1 0.63fF
+C721 wbs_adr_i[13] vdda1 0.63fF
+C722 wbs_dat_o[12] vdda1 0.63fF
+C723 wbs_dat_i[12] vdda1 0.63fF
+C724 wbs_adr_i[12] vdda1 0.63fF
+C725 wbs_dat_o[11] vdda1 0.63fF
+C726 wbs_dat_i[11] vdda1 0.63fF
+C727 wbs_adr_i[11] vdda1 0.63fF
+C728 wbs_dat_o[10] vdda1 0.63fF
+C729 wbs_dat_i[10] vdda1 0.63fF
+C730 wbs_adr_i[10] vdda1 0.63fF
+C731 wbs_dat_o[9] vdda1 0.63fF
+C732 wbs_dat_i[9] vdda1 0.63fF
+C733 wbs_adr_i[9] vdda1 0.63fF
+C734 wbs_dat_o[8] vdda1 0.63fF
+C735 wbs_dat_i[8] vdda1 0.63fF
+C736 wbs_adr_i[8] vdda1 0.63fF
+C737 wbs_dat_o[7] vdda1 0.63fF
+C738 wbs_dat_i[7] vdda1 0.63fF
+C739 wbs_adr_i[7] vdda1 0.63fF
+C740 wbs_dat_o[6] vdda1 0.63fF
+C741 wbs_dat_i[6] vdda1 0.63fF
+C742 wbs_adr_i[6] vdda1 0.63fF
+C743 wbs_dat_o[5] vdda1 0.63fF
+C744 wbs_dat_i[5] vdda1 0.63fF
+C745 wbs_adr_i[5] vdda1 0.63fF
+C746 wbs_dat_o[4] vdda1 0.63fF
+C747 wbs_dat_i[4] vdda1 0.63fF
+C748 wbs_adr_i[4] vdda1 0.63fF
+C749 wbs_sel_i[3] vdda1 0.63fF
+C750 wbs_dat_o[3] vdda1 0.63fF
+C751 wbs_dat_i[3] vdda1 0.63fF
+C752 wbs_adr_i[3] vdda1 0.63fF
+C753 wbs_sel_i[2] vdda1 0.63fF
+C754 wbs_dat_o[2] vdda1 0.63fF
+C755 wbs_dat_i[2] vdda1 0.63fF
+C756 wbs_adr_i[2] vdda1 0.63fF
+C757 wbs_sel_i[1] vdda1 0.63fF
+C758 wbs_dat_o[1] vdda1 0.63fF
+C759 wbs_dat_i[1] vdda1 0.63fF
+C760 wbs_adr_i[1] vdda1 0.63fF
+C761 wbs_sel_i[0] vdda1 0.63fF
+C762 wbs_dat_o[0] vdda1 0.63fF
+C763 wbs_dat_i[0] vdda1 0.63fF
+C764 wbs_adr_i[0] vdda1 0.63fF
+C765 wbs_we_i vdda1 0.63fF
+C766 wbs_stb_i vdda1 0.63fF
+C767 wbs_cyc_i vdda1 0.63fF
+C768 wbs_ack_o vdda1 0.63fF
+C769 wb_rst_i vdda1 0.63fF
+C770 wb_clk_i vdda1 0.63fF
+C771 gpio_analog[7] vdda1 3.92fF
+C772 io_analog[2] vdda1 133.63fF
+C773 m4_28900_141410# vdda1 540.96fF **FLOATING
+C774 m4_115800_678290# vdda1 80.80fF **FLOATING
+C775 io_analog[5] vdda1 1865.75fF
+C776 divbuf_0/OUT5 vdda1 350.37fF
+C777 divbuf_0/OUT4 vdda1 133.72fF
+C778 divbuf_0/OUT3 vdda1 34.03fF
+C779 divbuf_0/OUT2 vdda1 8.71fF
+C780 divbuf_0/a_492_n240# vdda1 2.46fF **FLOATING
+C781 ro_complete_0/cbank_2/v vdda1 17.89fF
+C782 ro_complete_0/cbank_2/switch_5/vin vdda1 0.87fF
+C783 ro_complete_0/cbank_2/switch_4/vin vdda1 1.63fF
+C784 ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF
+C785 ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF
+C786 ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF
+C787 ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF
+C788 divbuf_0/IN vdda1 19.88fF
+C789 ro_complete_0/cbank_1/switch_5/vin vdda1 0.87fF
+C790 ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF
+C791 gpio_analog[13] vdda1 69.60fF
+C792 ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF
+C793 ro_complete_0/a3 vdda1 26.74fF
+C794 ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF
+C795 ro_complete_0/a2 vdda1 20.30fF
+C796 ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF
+C797 ro_complete_0/a4 vdda1 33.91fF
+C798 ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF
+C799 gpio_analog[14] vdda1 127.21fF
+C800 ro_complete_0/cbank_0/v vdda1 17.14fF
+C801 ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF
+C802 ro_complete_0/cbank_0/switch_3/vin vdda1 0.76fF
+C803 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
+C804 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
+C805 ro_complete_0/ro_var_extend_0/vcont vdda1 0.27fF
+C806 gpio_noesd[15] vdda1 179.74fF
+C807 filter_0/a_4216_n5230# vdda1 418.47fF **FLOATING
+C808 filter_0/a_4216_n2998# vdda1 1.03fF **FLOATING
+C809 io_analog[1] vdda1 61.29fF
+C810 io_analog[0] vdda1 37.70fF
+C811 cp_0/upbar vdda1 1.79fF
+C812 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
+C813 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
+C814 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
+C815 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
+C816 cp_0/a_3060_0# vdda1 4.16fF **FLOATING
+C817 cp_0/a_1710_0# vdda1 6.63fF **FLOATING
+C818 cp_0/a_10_n50# vdda1 3.15fF **FLOATING
+C819 io_analog[6] vdda1 39.54fF
+C820 io_analog[7] vdda1 31.85fF
+C821 ashish_0/a_150_n710# vdda1 3.84fF **FLOATING
+C822 ashish_0/a_150_0# vdda1 1.41fF **FLOATING
.ends
