commit d5adcee77b469f5bb96a3ad22d03c5d41ef8443c
author asdhi <63298985+srestha-avadhani@users.noreply.github.com> Sat Jan 01 13:02:40 2022 +0530
committer GitHub <noreply@github.com> Sat Jan 01 13:02:40 2022 +0530
tree dfd4ab3381593c23fc6bf3a76d33b378f8ff6021
parent f63f1c6cc8c7bb10f1328cd3decc4fc33ee4c219

Update

Readme.md

diff --git a/Readme.md b/Readme.md
index 1c375ab..9a24a00 100644
--- a/Readme.md
+++ b/Readme.md
@@ -10,10 +10,11 @@
 ### Simulation results
 To validate our circuit, we have tested it in 180 nm technology and the results for the same are shown in the figure below.
 #### Phase Frequency Detector
-![](pfd.png) 
+![](Images/pfd.png) 
 #### Voltage controlled Oscillator
-![](ro_cbank_var_post.png)
-
+![](Images/ro_cbank_var_post.png)
+#### Fractional-N divider
+![](Images/div.png)
 ### Sources
 This repository mainly contains all the required building blocks for the implementation of the PLL(gds/mag/netlists). We have the complete fractional-N PLL loop, individual blocks - PFD, fresctional-N divider, VCO, charge pump and loop filter. In addition to these we have combinations of phase dectector - divider and VCO - divider.