retry
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index bde1799..4b7eff7 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/cbank.ext b/mag/cbank.ext
index 0a248a3..cd40627 100644
--- a/mag/cbank.ext
+++ b/mag/cbank.ext
@@ -26,6 +26,9 @@
node "a_2720_n30#" 133 1402.86 2720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
node "a_1840_n30#" 120 0 1840 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd!" 0 0 4650 -1660 ppd 0 0 0 0 0 0 0 0 0 0 67600 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 482200 8300 403200 6720 403200 6720 1919200 11580 2616000 18040 0 0 0 0
+cap "a_1840_n30#" "li_1840_n30#" 18.13
+cap "v" "li_1840_n30#" 1301.39
+cap "a_2720_n30#" "li_1840_n30#" 435.273
cap "a_6220_n30#" "v" 1301.39
cap "a_5320_n30#" "v" 1301.39
cap "a_5320_n30#" "a_6220_n30#" 368.308
@@ -35,9 +38,6 @@
cap "a_2720_n30#" "v" 1301.39
cap "a_3600_n30#" "a_4460_n30#" 399
cap "a_2720_n30#" "a_3600_n30#" 281.647
-cap "v" "li_1840_n30#" 1301.39
-cap "a_2720_n30#" "li_1840_n30#" 435.273
-cap "a_1840_n30#" "li_1840_n30#" 18.13
device csubckt sky130_fd_pr__cap_mim_m3_1 6070 590 6071 591 w=560 l=560 "None" "v" 1920 0 "a_6220_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 5190 590 5191 591 w=560 l=560 "None" "v" 1920 0 "a_5320_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 4320 590 4321 591 w=560 l=560 "None" "v" 1920 0 "a_4460_n30#" 1440 0
@@ -45,18 +45,18 @@
device csubckt sky130_fd_pr__cap_mim_m3_1 2530 590 2531 591 w=560 l=560 "None" "v" 1920 0 "a_2720_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 1670 590 1671 591 w=560 l=560 "None" "v" 1920 0 "li_1840_n30#" 1440 0
device csubckt sky130_fd_pr__cap_mim_m3_1 330 130 331 131 w=1040 l=1000 "None" "v" 3760 0 "gnd!" 1440 0
-cap "switch_0/vcont" "switch_0/vin" 83.635
cap "switch_1/vcont" "switch_1/vout" 4.23077
cap "switch_1/vcont" "switch_1/vin" 83.635
cap "switch_0/vcont" "switch_0/vout" 4.23077
-cap "switch_2/vcont" "switch_2/vout" 4.23077
-cap "switch_2/vcont" "switch_2/vin" 83.635
-cap "switch_4/vcont" "switch_4/vout" 4.23077
-cap "switch_4/vcont" "switch_4/vin" 83.635
-cap "switch_3/vcont" "switch_3/vout" 4.23077
+cap "switch_0/vcont" "switch_0/vin" 83.635
+cap "switch_2/vout" "switch_2/vcont" 4.23077
+cap "switch_2/vin" "switch_2/vcont" 83.635
+cap "switch_4/vout" "switch_4/vcont" 4.23077
+cap "switch_4/vin" "switch_4/vcont" 83.635
+cap "switch_3/vout" "switch_3/vcont" 4.23077
cap "switch_3/vcont" "switch_3/vin" 83.635
-cap "switch_5/vcont" "switch_5/vout" 4.23077
-cap "switch_5/vcont" "switch_5/vin" 83.635
+cap "switch_5/vout" "switch_5/vcont" 4.23077
+cap "switch_5/vin" "switch_5/vcont" 83.635
merge "switch_5/vout" "switch_4/VSUBS" -915.086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91320 -1316 93600 0 93600 0 139137 -1408 -72040 -3202 0 0 0 0
merge "switch_4/VSUBS" "switch_4/vout"
merge "switch_4/vout" "switch_5/VSUBS"
diff --git a/mag/cp.ext b/mag/cp.ext
index 351a931..64ee0bf 100644
--- a/mag/cp.ext
+++ b/mag/cp.ext
@@ -19,21 +19,21 @@
node "a_10_n50#" 3989 2430.18 10 -50 p 0 0 0 0 0 0 0 0 684000 4360 1368000 7960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2779200 17200 0 0 1936200 15780 239200 4200 0 0 0 0 0 0 0 0 0 0
node "vdd!" 16208 127784 -490 -160 nw 0 0 0 0 40009000 27420 0 0 78300 1120 6840000 39800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 6275100 44200 960700 13000 348300 5280 348300 5280 3226600 19660 0 0 0 0
substrate "gnd!" 0 0 -370 -2840 ndif 0 0 0 0 0 0 0 0 3419400 21800 81200 1140 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3576600 28780 732600 8960 351000 5300 351000 5300 4550400 19920 0 0 0 0
-cap "a_7110_0#" "vdd!" 42.55
-cap "a_1710_0#" "down" 320.4
-cap "a_3060_0#" "vdd!" 1788.27
-cap "upbar" "down" 20.625
-cap "a_1710_0#" "vdd!" 707.2
-cap "out" "vdd!" 281.2
-cap "a_1710_n2840#" "vdd!" 254.08
-cap "a_10_n50#" "vbias" 192.9
-cap "a_10_n50#" "a_1710_0#" 41.6842
+cap "a_1710_n2840#" "out" 606.81
+cap "vdd!" "out" 281.2
+cap "vdd!" "a_1710_n2840#" 254.08
+cap "vdd!" "a_10_n50#" 530.297
cap "vdd!" "a_3060_n2840#" 320.4
-cap "a_10_n50#" "vdd!" 530.297
+cap "a_10_n50#" "vbias" 192.9
cap "out" "a_1710_0#" 841.733
cap "a_1710_n2840#" "a_1710_0#" 828.847
+cap "vdd!" "a_7110_0#" 42.55
+cap "a_10_n50#" "a_1710_0#" 41.6842
+cap "vdd!" "a_3060_0#" 1788.27
cap "a_1710_n2840#" "upbar" 291.6
-cap "a_1710_n2840#" "out" 606.81
+cap "vdd!" "a_1710_0#" 707.2
+cap "a_1710_0#" "down" 320.4
+cap "upbar" "down" 20.625
device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/mag/ro_complete.ext b/mag/ro_complete.ext
index 5aedf82..0232523 100644
--- a/mag/ro_complete.ext
+++ b/mag/ro_complete.ext
@@ -20,45 +20,45 @@
substrate "a_7790_n10640#" 0 0 7790 -10640 ppd 0 0 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1036800 17280 1349800 21100 1085200 18160 1085200 18160 3951000 27540 0 0 0 0
cap "li_4080_1390#" "a5" 77.72
cap "li_7140_1400#" "a5" 100.96
+cap "cbank_2/a1" "cbank_2/switch_1/vout" 10.1538
+cap "cbank_2/a0" "cbank_2/switch_1/vin" 243.345
+cap "cbank_2/a0" "cbank_2/switch_0/vout" 46.5385
cap "cbank_2/a0" "cbank_2/a1" 9.35
-cap "cbank_2/switch_1/vout" "cbank_2/a1" 10.1538
-cap "cbank_2/switch_0/vout" "cbank_2/a0" 46.5385
-cap "cbank_2/switch_1/vin" "cbank_2/a0" 243.345
-cap "cbank_2/a2" "cbank_2/switch_3/vin" 219.322
-cap "cbank_2/a2" "cbank_2/switch_2/vout" 46.5385
+cap "cbank_2/switch_3/vin" "cbank_2/a2" 219.322
+cap "cbank_2/switch_2/vout" "cbank_2/a2" 46.5385
+cap "cbank_2/switch_1/vout" "cbank_2/a1" 36.3846
cap "cbank_2/a2" "cbank_2/a3" 4.95
-cap "cbank_2/a1" "cbank_2/switch_1/vout" 36.3846
cap "cbank_2/a1" "cbank_2/a2" 8.63077
-cap "cbank_2/a4" "cbank_2/switch_4/vout" 46.5385
+cap "cbank_2/switch_4/vout" "cbank_2/a4" 46.5385
+cap "a2" "cbank_2/a3" 4.95
cap "cbank_2/a3" "cbank_2/switch_4/vin" 203.307
cap "cbank_2/a3" "cbank_2/switch_3/vout" 46.5385
cap "cbank_2/a3" "cbank_2/a4" 9.61714
-cap "cbank_2/a3" "a2" 4.95
-cap "cbank_2/a4" "cbank_2/a5" 8.63077
cap "cbank_2/switch_5/vin" "li_7140_1400#" 24
-cap "cbank_2/a5" "cbank_2/switch_5/vout" 46.5385
-cap "cbank_2/v" "cbank_1/gnd!" 85.5235
+cap "cbank_2/switch_5/vout" "cbank_2/a5" 46.5385
+cap "cbank_2/a4" "cbank_2/a5" 8.63077
+cap "cbank_1/gnd!" "cbank_2/v" 85.5235
+cap "cbank_1/switch_0/vout" "cbank_2/v" 275.882
cap "cbank_1/switch_0/vout" "a1" 19.5854
cap "cbank_1/switch_1/vin" "a0" 34.1478
cap "cbank_1/switch_0/vout" "a0" 181.38
cap "a0" "cbank_2/v" 53.41
-cap "cbank_1/switch_0/vout" "cbank_2/v" 275.882
cap "a0" "cbank_2/a_2720_n30#" 58.495
cap "cbank_1/switch_3/vin" "a2" 18.7
+cap "a2" "cbank_2/v" 53.41
+cap "a2" "cbank_2/a_4460_n30#" 49.3975
+cap "a1" "cbank_2/v" 53.41
cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/switch_2/vin" "a1" 30.2077
cap "cbank_1/gnd!" "a2" 181.38
cap "cbank_1/gnd!" "a1" 207.754
-cap "a2" "cbank_2/a_4460_n30#" 49.3975
-cap "a2" "cbank_2/v" 53.41
-cap "a1" "cbank_2/v" 53.41
cap "a3" "cbank_2/v" 53.41
cap "a3" "cbank_2/a_5320_n30#" 43.3325
-cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/switch_4/vin" "a3" 35.7
+cap "cbank_1/switch_3/vin" "a2" 18.7
+cap "cbank_1/gnd!" "cbank_2/v" 275.882
cap "cbank_1/gnd!" "a4" 62.3432
cap "cbank_1/gnd!" "a3" 188.986
-cap "cbank_1/switch_3/vin" "a2" 18.7
cap "li_7140_1400#" "cbank_2/a_6220_n30#" 126
cap "a4" "li_7140_1400#" 53.41
cap "cbank_1/switch_4/vout" "li_7140_1400#" 230.8
@@ -70,26 +70,26 @@
cap "cbank_1/a0" "cbank_1/switch_1/vin" 166.722
cap "cbank_1/a0" "cbank_1/switch_0/vout" 248.36
cap "cbank_1/a0" "cbank_1/a1" 12.8333
+cap "cbank_1/a2" "cbank_1/a3" 6.79412
cap "cbank_1/a1" "cbank_1/a2" 11.8462
cap "cbank_1/gnd!" "cbank_1/a2" 248.36
-cap "cbank_1/switch_2/vin" "cbank_1/a1" 147.485
cap "cbank_1/gnd!" "cbank_1/a1" 276.047
-cap "cbank_1/a3" "cbank_1/a2" 6.79412
-cap "cbank_1/switch_3/vin" "cbank_1/a2" 91.3
+cap "cbank_1/a2" "cbank_1/switch_3/vin" 91.3
+cap "cbank_1/a1" "cbank_1/switch_2/vin" 147.485
+cap "cbank_1/gnd!" "cbank_1/a3" 259.572
cap "cbank_1/switch_3/vin" "a2" 91.3
-cap "cbank_1/a3" "a2" 6.79412
cap "cbank_1/a3" "cbank_1/switch_4/vin" 174.3
cap "cbank_1/gnd!" "cbank_1/a4" 153.055
cap "cbank_1/a3" "cbank_1/a4" 13.2
-cap "cbank_1/gnd!" "cbank_1/a3" 259.572
+cap "cbank_1/a3" "a2" 6.79412
cap "cbank_1/a5" "cbank_1/switch_5/vout" 156.098
cap "cbank_1/a4" "cbank_1/switch_5/vin" 147.485
cap "cbank_1/a4" "cbank_1/switch_5/vout" 106.517
cap "cbank_1/a4" "cbank_1/a5" 11.8462
cap "cbank_1/v" "cbank_0/gnd!" 46.9
-cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_1/v" "cbank_1/a0" 53.41
-cap "cbank_1/a0" "cbank_1/switch_1/vin" 287.74
+cap "cbank_1/switch_1/vin" "cbank_1/a0" 287.74
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_1/a2" "cbank_1/v" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_1/a2" "cbank_1/switch_3/vin" 261.67
@@ -97,62 +97,62 @@
cap "cbank_1/a3" "cbank_1/switch_4/vin" 244.29
cap "cbank_1/a3" "cbank_1/v" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 151.29
+cap "cbank_1/a4" "li_4080_1390#" 53.41
cap "cbank_0/gnd!" "li_4080_1390#" 117.991
cap "cbank_1/switch_5/vin" "li_4080_1390#" 133.875
-cap "cbank_1/a4" "li_4080_1390#" 53.41
cap "cbank_0/gnd!" "cbank_1/v" 46.9
cap "cbank_0/switch_0/vout" "cbank_1/v" 151.29
cap "cbank_0/switch_0/vout" "a1" 41.7195
cap "cbank_0/switch_1/vin" "a0" 128.843
cap "cbank_0/switch_0/vout" "a0" 296.011
-cap "cbank_0/switch_3/vin" "a2" 70.5571
-cap "cbank_0/switch_2/vin" "a1" 113.977
cap "cbank_0/gnd!" "cbank_1/v" 151.29
cap "cbank_0/gnd!" "a2" 296.011
+cap "cbank_0/switch_3/vin" "a2" 70.5571
cap "cbank_0/gnd!" "a1" 343.879
-cap "a4" "cbank_0/gnd!" 122.843
+cap "cbank_0/switch_2/vin" "a1" 113.977
+cap "cbank_1/v" "cbank_0/gnd!" 151.29
cap "cbank_0/switch_4/vin" "a3" 134.7
+cap "cbank_0/gnd!" "a4" 122.843
cap "cbank_0/gnd!" "a3" 309.986
cap "cbank_0/switch_3/vin" "a2" 70.5571
-cap "cbank_1/v" "cbank_0/gnd!" 151.29
-cap "cbank_0/switch_5/vin" "a4" 113.977
cap "li_4080_1390#" "cbank_0/switch_4/vout" 339.331
-cap "a5" "cbank_0/switch_4/vout" 187.16
-cap "a4" "cbank_0/switch_4/vout" 187.143
+cap "cbank_0/switch_4/vout" "a5" 187.16
+cap "cbank_0/switch_5/vin" "a4" 113.977
+cap "cbank_0/switch_4/vout" "a4" 187.143
cap "li_4080_1390#" "a_7790_n10640#" -33.775
cap "li_7140_1400#" "a_7790_n10640#" 67.7
-cap "cbank_0/a1" "cbank_0/switch_1/vout" 26.2514
-cap "cbank_0/switch_1/vin" "cbank_0/a0" 72.0261
-cap "cbank_0/switch_0/vout" "cbank_0/a0" 133.728
-cap "cbank_0/a1" "cbank_0/a0" 9.9
-cap "cbank_0/a2" "cbank_0/switch_3/vin" 39.4429
-cap "cbank_0/a2" "cbank_0/switch_2/vout" 133.728
-cap "cbank_0/a1" "cbank_0/switch_2/vin" 63.7154
-cap "cbank_0/a1" "cbank_0/switch_1/vout" 139.922
+cap "cbank_0/switch_1/vout" "cbank_0/a1" 26.2514
+cap "cbank_0/a0" "cbank_0/switch_1/vin" 72.0261
+cap "cbank_0/a0" "cbank_0/switch_0/vout" 133.728
+cap "cbank_0/a0" "cbank_0/a1" 9.9
+cap "cbank_0/switch_2/vin" "cbank_0/a1" 63.7154
+cap "cbank_0/switch_1/vout" "cbank_0/a1" 139.922
cap "cbank_0/a2" "cbank_0/a3" 5.24118
cap "cbank_0/a1" "cbank_0/a2" 9.13846
-cap "cbank_0/a3" "cbank_0/switch_3/vout" 138.572
-cap "cbank_0/a3" "cbank_0/a4" 10.1829
+cap "cbank_0/switch_3/vin" "cbank_0/a2" 39.4429
+cap "cbank_0/switch_2/vout" "cbank_0/a2" 133.728
cap "a2" "cbank_0/switch_3/vin" 39.4429
cap "a2" "cbank_0/a3" 5.24118
cap "cbank_0/switch_4/vout" "cbank_0/a4" 92.5551
cap "cbank_0/switch_4/vin" "cbank_0/a3" 75.3
+cap "cbank_0/switch_3/vout" "cbank_0/a3" 138.572
+cap "cbank_0/a3" "cbank_0/a4" 10.1829
+cap "li_4080_1390#" "cbank_0/switch_5/vin" 91
+cap "cbank_0/a5" "cbank_0/switch_5/vout" 93.8699
+cap "cbank_0/a4" "cbank_0/switch_5/vin" 63.7154
+cap "cbank_0/a4" "cbank_0/switch_4/vout" 46.0167
cap "cbank_0/a4" "cbank_0/a5" 9.13846
-cap "cbank_0/switch_5/vin" "li_4080_1390#" 91
-cap "cbank_0/switch_5/vout" "cbank_0/a5" 93.8699
-cap "cbank_0/switch_5/vin" "cbank_0/a4" 63.7154
-cap "cbank_0/switch_4/vout" "cbank_0/a4" 46.0167
-cap "cbank_0/a_6220_n30#" "li_4080_1390#" 42
-cap "ro_var_extend_0/w_n116_n750#" "ro_var_extend_0/out1" 100.15
+cap "li_4080_1390#" "cbank_0/a_6220_n30#" 42
cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
cap "ro_var_extend_0/out3" "ro_var_extend_0/out1" 116.667
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 198.749
+cap "ro_var_extend_0/w_n116_n750#" "ro_var_extend_0/out1" 100.15
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 198.749
cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
-cap "ro_var_extend_0/out2" "ro_var_extend_0/w_n116_n750#" 184.5
-cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55
-cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 12.1846
+cap "ro_var_extend_0/w_n116_n750#" "ro_var_extend_0/out2" 184.5
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
cap "ro_var_extend_0/w_n116_n750#" "ro_var_extend_0/vcont" -11.167
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 12.1846
merge "cbank_0/a4" "cbank_1/a4" -1641 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15680 -6020 0 0 0 0 0 0 0 0 0 0 0 0
merge "cbank_1/a4" "cbank_2/a4"
merge "cbank_2/a4" "a4"
diff --git a/mag/ro_var_extend.ext b/mag/ro_var_extend.ext
index b53fa11..8a57314 100644
--- a/mag/ro_var_extend.ext
+++ b/mag/ro_var_extend.ext
@@ -14,14 +14,14 @@
node "w_n116_n750#" 20519 4163.15 -116 -750 nw 0 0 0 0 319818 3930 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
node "vdd" 20170 17140.2 -250 320 nw 0 0 0 0 4464300 14320 0 0 35200 860 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
substrate "gnd" 0 0 -210 -20 ndif 0 0 0 0 0 0 0 0 60000 1800 117400 3220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1050720 15848 0 0 0 0 0 0 0 0 0 0 0 0
-cap "w_n116_n750#" "vcont" 140.194
-cap "out1" "out2" 40.8506
-cap "out3" "out2" 1263.05
-cap "w_n116_n750#" "out2" 786.728
+cap "vdd" "out2" 235.622
cap "out3" "out1" 1156.32
cap "w_n116_n750#" "out1" 566.63
-cap "vdd" "out2" 235.622
cap "w_n116_n750#" "out3" 213.319
+cap "out1" "out2" 40.8506
+cap "w_n116_n750#" "vcont" 140.194
+cap "out3" "out2" 1263.05
+cap "w_n116_n750#" "out2" 786.728
cap "vdd" "out1" 230.66
cap "vdd" "out3" 230.554
device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n116_n750#" "out3" 72 0 "w_n116_n750#" 400 0
diff --git a/mag/switch.ext b/mag/switch.ext
index b5399a5..9a3126c 100644
--- a/mag/switch.ext
+++ b/mag/switch.ext
@@ -9,7 +9,7 @@
node "vin" 1082 0 -190 0 ndif 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0
node "vcont" 1139 384.82 -40 1460 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vcont" "vout" 16.5
-cap "vcont" "vin" 8.25
+cap "vin" "vcont" 8.25
cap "vin" "vout" 420
+cap "vout" "vcont" 16.5
device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "VSUBS" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
index bc71ffb..97cd20a 100644
--- a/mag/user_analog_project_wrapper.ext
+++ b/mag/user_analog_project_wrapper.ext
@@ -1,10 +1,10 @@
-timestamp 1640881500
+timestamp 1640886908
version 8.3
tech sky130A
style ngspice()
scale 1000 1 500000
resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use ro_complete ro_complete_0 1 0 19988 0 1 655326
+use cp cp_0 1 0 66630 0 1 683860
port "io_analog[4]" 41 329294 702300 334294 704800 m5
port "io_analog[4]" 47 318994 702300 323994 704800 m5
port "io_analog[5]" 42 227594 702300 232594 704800 m5
@@ -1387,24 +1387,24 @@
node "wb_clk_i" 1 631.648 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_clamp_high[0]" "io_analog[4]" 525
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "io_analog[4]" "io_clamp_low[0]" 525
cap "io_clamp_high[1]" "io_analog[5]" 525
cap "io_clamp_low[1]" "io_clamp_high[1]" 525
-cap "io_analog[5]" "io_analog[5]" 26250
cap "io_analog[5]" "io_clamp_low[1]" 525
-cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[4]" "io_analog[4]" 26250
cap "io_clamp_high[2]" "io_analog[6]" 525
-cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[4]" "io_analog[4]" 26250
cap "io_clamp_low[2]" "io_clamp_high[2]" 525
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[4]" "io_analog[4]" 21250
cap "io_analog[6]" "io_clamp_low[2]" 525
cap "io_analog[4]" "io_analog[4]" 21250
-cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[5]" "io_analog[5]" 26250
cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_clamp_high[0]" "io_analog[4]" 525
-cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_analog[6]" "io_analog[6]" 26250
cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_clamp_low[0]" "io_clamp_high[0]" 525
cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "io_analog[4]" "io_analog[4]" 26250
-merge "ro_complete_0/a_7790_n10640#" "VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "io_analog[6]" "io_analog[6]" 26250
+merge "cp_0/gnd!" "VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper.gds b/mag/user_analog_project_wrapper.gds
index bde1799..4b7eff7 100644
--- a/mag/user_analog_project_wrapper.gds
+++ b/mag/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 9b70f3b..314a325 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1640881500
+timestamp 1640886908
<< metal2 >>
rect 262 -400 318 240
rect 853 -400 909 240
@@ -700,10 +700,10 @@
rect -50 0 0 352000
rect 292000 0 292050 352000
rect -50 -50 292050 0
-use ro_complete ro_complete_0
-timestamp 1640809734
-transform 1 0 9994 0 1 327663
-box 362 -5330 4455 1180
+use cp cp_0
+timestamp 1640602475
+transform 1 0 33315 0 1 341930
+box -245 -1715 4500 2030
<< labels >>
flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..23e885f
--- /dev/null
+++ b/mag/user_analog_project_wrapper.spice
@@ -0,0 +1,942 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+X0 ro_complete_0/cbank_0/v gnd gnd sky130_fd_pr__cap_var_lvt pd=0u ps=0u ad=0p as=0p w=1e+06u l=180000u
+X1 ro_complete_0/cbank_2/v gnd gnd sky130_fd_pr__cap_var_lvt pd=0u ps=0u ad=0p as=0p w=1e+06u l=180000u
+X2 ro_complete_0/cbank_1/v ro_complete_0/cbank_0/v ro_complete_0/ro_var_extend_0/vdd ro_complete_0/ro_var_extend_0/vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=300000u
+X3 ro_complete_0/cbank_2/v ro_complete_0/cbank_1/v ro_complete_0/ro_var_extend_0/vdd ro_complete_0/ro_var_extend_0/vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=300000u
+X4 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v ro_complete_0/ro_var_extend_0/vdd ro_complete_0/ro_var_extend_0/vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2e+06u l=300000u
+X5 ro_complete_0/cbank_1/v gnd gnd sky130_fd_pr__cap_var_lvt pd=0u ps=0u ad=0p as=0p w=1e+06u l=180000u
+X6 ro_complete_0/cbank_1/v ro_complete_0/cbank_0/v gnd gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X7 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v gnd gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X8 ro_complete_0/cbank_2/v ro_complete_0/cbank_1/v gnd gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X9 gnd ro_complete_0/a0 ro_complete_0/cbank_0/switch_0/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X10 gnd ro_complete_0/a1 ro_complete_0/cbank_0/switch_1/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X11 gnd ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X12 gnd ro_complete_0/a3 ro_complete_0/cbank_0/switch_3/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X13 gnd ro_complete_0/a4 ro_complete_0/cbank_0/switch_4/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X14 gnd ro_complete_0/a5 ro_complete_0/cbank_0/switch_5/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X15 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_2/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X16 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_3/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X17 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_0/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X18 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_5/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X19 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_4/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X20 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_1/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X21 ro_complete_0/cbank_0/v gnd sky130_fd_pr__cap_mim_m3_1 l=5e+06u w=5.2e+06u
+X22 gnd ro_complete_0/a0 ro_complete_0/cbank_1/switch_0/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X23 gnd ro_complete_0/a1 ro_complete_0/cbank_1/switch_1/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X24 gnd ro_complete_0/a2 ro_complete_0/cbank_1/switch_2/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X25 gnd ro_complete_0/a3 ro_complete_0/cbank_1/switch_3/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X26 gnd ro_complete_0/a4 ro_complete_0/cbank_1/switch_4/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X27 gnd ro_complete_0/a5 ro_complete_0/cbank_1/switch_5/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X28 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_2/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X29 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_3/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X30 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_0/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X31 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_5/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X32 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_4/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X33 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_1/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X34 ro_complete_0/cbank_1/v gnd sky130_fd_pr__cap_mim_m3_1 l=5e+06u w=5.2e+06u
+X35 gnd ro_complete_0/a0 ro_complete_0/cbank_2/switch_0/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X36 gnd ro_complete_0/a1 ro_complete_0/cbank_2/switch_1/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X37 gnd ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X38 gnd ro_complete_0/a3 ro_complete_0/cbank_2/switch_3/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X39 gnd ro_complete_0/a4 ro_complete_0/cbank_2/switch_4/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X40 gnd ro_complete_0/a5 ro_complete_0/cbank_2/switch_5/vin gnd sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=7.2e+06u l=350000u
+X41 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_2/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X42 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_3/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X43 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_0/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X44 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_5/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X45 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_4/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X46 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_1/vin sky130_fd_pr__cap_mim_m3_1 l=2.8e+06u w=2.8e+06u
+X47 ro_complete_0/cbank_2/v gnd sky130_fd_pr__cap_mim_m3_1 l=5e+06u w=5.2e+06u
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+C1 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.44fF
+C2 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
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+C4 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C5 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/switch_1/vin 0.28fF
+C6 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 0.04fF
+C7 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C8 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a4 0.18fF
+C9 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.37fF
+C10 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/a3 0.09fF
+C11 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/switch_3/vin 0.40fF
+C12 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/a4 0.18fF
+C13 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C14 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_1/v 0.13fF
+C15 ro_complete_0/a4 ro_complete_0/a5 0.03fF
+C16 io_clamp_low[2] io_analog[6] 0.53fF
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+C18 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.40fF
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+C20 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.44fF
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+C22 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C23 ro_complete_0/a0 ro_complete_0/cbank_0/switch_0/vin 0.09fF
+C24 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/a3 0.45fF
+C25 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_0/vin 1.30fF
+C26 ro_complete_0/cbank_1/v ro_complete_0/a5 0.08fF
+C27 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.37fF
+C28 ro_complete_0/a0 ro_complete_0/a1 0.03fF
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+C31 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C33 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C34 io_clamp_high[1] io_analog[5] 0.53fF
+C35 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C36 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.40fF
+C37 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.45fF
+C38 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.48fF
+C39 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C40 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C41 ro_complete_0/a0 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C42 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/a4 0.09fF
+C43 ro_complete_0/a5 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C44 ro_complete_0/cbank_1/v ro_complete_0/cbank_1/switch_0/vin 1.30fF
+C45 io_clamp_low[0] io_analog[4] 0.53fF
+C46 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/a1 0.09fF
+C47 ro_complete_0/a2 ro_complete_0/a3 0.03fF
+C48 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C49 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/a2 0.09fF
+C50 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C51 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.28fF
+C52 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C53 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C54 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.37fF
+C55 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/switch_3/vin 0.40fF
+C56 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C57 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C58 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a3 0.09fF
+C59 ro_complete_0/a0 ro_complete_0/cbank_1/switch_1/vin 0.49fF
+C60 ro_complete_0/cbank_2/v ro_complete_0/cbank_2/switch_0/vin 1.30fF
+C61 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C62 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 1.27fF
+C63 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/a1 0.18fF
+C64 ro_complete_0/a1 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C65 ro_complete_0/a3 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C66 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C67 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C68 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_0/vin 0.44fF
+C69 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C70 io_clamp_high[2] io_analog[6] 0.53fF
+C71 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a2 0.09fF
+C72 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a1 0.09fF
+C73 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a3 0.21fF
+C74 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a5 0.09fF
+C75 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.44fF
+C76 io_clamp_low[1] io_analog[5] 0.53fF
+C77 ro_complete_0/a0 ro_complete_0/cbank_2/switch_1/vin 0.30fF
+C78 ro_complete_0/a0 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C79 ro_complete_0/a3 ro_complete_0/cbank_2/switch_4/vin 0.25fF
+C80 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C81 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/a5 0.09fF
+C82 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/switch_3/vin 0.40fF
+C83 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.10fF
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+C85 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a0 0.20fF
+C86 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a1 0.18fF
+C87 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.22fF
+C88 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C89 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a4 0.09fF
+C90 ro_complete_0/a2 ro_complete_0/a1 0.03fF
+C91 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/switch_1/vin 0.28fF
+C92 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C93 io_clamp_high[0] io_analog[4] 0.53fF
+C94 io_analog[4] gnd 25.05fF
+C95 io_analog[5] gnd 25.05fF
+C96 io_analog[6] gnd 25.05fF
+C97 io_in_3v3[0] gnd 0.61fF
+C98 io_oeb[26] gnd 0.61fF
+C99 io_in[0] gnd 0.61fF
+C100 io_out[26] gnd 0.61fF
+C101 io_out[0] gnd 0.61fF
+C102 io_in[26] gnd 0.61fF
+C103 io_oeb[0] gnd 0.61fF
+C104 io_in_3v3[26] gnd 0.61fF
+C105 io_in_3v3[1] gnd 0.61fF
+C106 io_oeb[25] gnd 0.61fF
+C107 io_in[1] gnd 0.61fF
+C108 io_out[25] gnd 0.61fF
+C109 io_out[1] gnd 0.61fF
+C110 io_in[25] gnd 0.61fF
+C111 io_oeb[1] gnd 0.61fF
+C112 io_in_3v3[25] gnd 0.61fF
+C113 io_in_3v3[2] gnd 0.61fF
+C114 io_oeb[24] gnd 0.61fF
+C115 io_in[2] gnd 0.61fF
+C116 io_out[24] gnd 0.61fF
+C117 io_out[2] gnd 0.61fF
+C118 io_in[24] gnd 0.61fF
+C119 io_oeb[2] gnd 0.61fF
+C120 io_in_3v3[24] gnd 0.61fF
+C121 io_in_3v3[3] gnd 0.61fF
+C122 gpio_noesd[17] gnd 0.61fF
+C123 io_in[3] gnd 0.61fF
+C124 gpio_analog[17] gnd 0.61fF
+C125 io_out[3] gnd 0.61fF
+C126 io_oeb[3] gnd 0.61fF
+C127 io_in_3v3[4] gnd 0.61fF
+C128 io_in[4] gnd 0.61fF
+C129 io_out[4] gnd 0.61fF
+C130 io_oeb[4] gnd 0.61fF
+C131 io_oeb[23] gnd 0.61fF
+C132 io_out[23] gnd 0.61fF
+C133 io_in[23] gnd 0.61fF
+C134 io_in_3v3[23] gnd 0.61fF
+C135 gpio_noesd[16] gnd 0.61fF
+C136 gpio_analog[16] gnd 0.61fF
+C137 io_in_3v3[5] gnd 0.61fF
+C138 io_in[5] gnd 0.61fF
+C139 io_out[5] gnd 0.61fF
+C140 io_oeb[5] gnd 0.61fF
+C141 io_oeb[22] gnd 0.61fF
+C142 io_out[22] gnd 0.61fF
+C143 io_in[22] gnd 0.61fF
+C144 io_in_3v3[22] gnd 0.61fF
+C145 gpio_noesd[15] gnd 0.61fF
+C146 gpio_analog[15] gnd 0.61fF
+C147 io_in_3v3[6] gnd 0.61fF
+C148 io_in[6] gnd 0.61fF
+C149 io_out[6] gnd 0.61fF
+C150 io_oeb[6] gnd 0.61fF
+C151 io_oeb[21] gnd 0.61fF
+C152 io_out[21] gnd 0.61fF
+C153 io_in[21] gnd 0.61fF
+C154 io_in_3v3[21] gnd 0.61fF
+C155 gpio_noesd[14] gnd 0.61fF
+C156 gpio_analog[14] gnd 0.61fF
+C157 vssa1 gnd 26.08fF
+C158 vssd2 gnd 13.04fF
+C159 vssd1 gnd 13.04fF
+C160 vdda2 gnd 13.04fF
+C161 vdda1 gnd 26.08fF
+C162 io_oeb[20] gnd 0.61fF
+C163 io_out[20] gnd 0.61fF
+C164 io_in[20] gnd 0.61fF
+C165 io_in_3v3[20] gnd 0.61fF
+C166 gpio_noesd[13] gnd 0.61fF
+C167 gpio_analog[13] gnd 0.61fF
+C168 gpio_analog[0] gnd 0.61fF
+C169 gpio_noesd[0] gnd 0.61fF
+C170 io_in_3v3[7] gnd 0.61fF
+C171 io_in[7] gnd 0.61fF
+C172 io_out[7] gnd 0.61fF
+C173 io_oeb[7] gnd 0.61fF
+C174 io_oeb[19] gnd 0.61fF
+C175 io_out[19] gnd 0.61fF
+C176 io_in[19] gnd 0.61fF
+C177 io_in_3v3[19] gnd 0.61fF
+C178 gpio_noesd[12] gnd 0.61fF
+C179 gpio_analog[12] gnd 0.61fF
+C180 gpio_analog[1] gnd 0.61fF
+C181 gpio_noesd[1] gnd 0.61fF
+C182 io_in_3v3[8] gnd 0.61fF
+C183 io_in[8] gnd 0.61fF
+C184 io_out[8] gnd 0.61fF
+C185 io_oeb[8] gnd 0.61fF
+C186 io_oeb[18] gnd 0.61fF
+C187 io_out[18] gnd 0.61fF
+C188 io_in[18] gnd 0.61fF
+C189 io_in_3v3[18] gnd 0.61fF
+C190 gpio_noesd[11] gnd 0.61fF
+C191 gpio_analog[11] gnd 0.61fF
+C192 gpio_analog[2] gnd 0.61fF
+C193 gpio_noesd[2] gnd 0.61fF
+C194 io_in_3v3[9] gnd 0.61fF
+C195 io_in[9] gnd 0.61fF
+C196 io_out[9] gnd 0.61fF
+C197 io_oeb[9] gnd 0.61fF
+C198 io_oeb[17] gnd 0.61fF
+C199 io_out[17] gnd 0.61fF
+C200 io_in[17] gnd 0.61fF
+C201 io_in_3v3[17] gnd 0.61fF
+C202 gpio_noesd[10] gnd 0.61fF
+C203 gpio_analog[10] gnd 0.61fF
+C204 gpio_analog[3] gnd 0.61fF
+C205 gpio_noesd[3] gnd 0.61fF
+C206 io_in_3v3[10] gnd 0.61fF
+C207 io_in[10] gnd 0.61fF
+C208 io_out[10] gnd 0.61fF
+C209 io_oeb[10] gnd 0.61fF
+C210 io_oeb[16] gnd 0.61fF
+C211 io_out[16] gnd 0.61fF
+C212 io_in[16] gnd 0.61fF
+C213 io_in_3v3[16] gnd 0.61fF
+C214 gpio_noesd[9] gnd 0.61fF
+C215 gpio_analog[9] gnd 0.61fF
+C216 gpio_analog[4] gnd 0.61fF
+C217 gpio_noesd[4] gnd 0.61fF
+C218 io_in_3v3[11] gnd 0.61fF
+C219 io_in[11] gnd 0.61fF
+C220 io_out[11] gnd 0.61fF
+C221 io_oeb[11] gnd 0.61fF
+C222 io_oeb[15] gnd 0.61fF
+C223 io_out[15] gnd 0.61fF
+C224 io_in[15] gnd 0.61fF
+C225 io_in_3v3[15] gnd 0.61fF
+C226 gpio_noesd[8] gnd 0.61fF
+C227 gpio_analog[8] gnd 0.61fF
+C228 gpio_analog[5] gnd 0.61fF
+C229 gpio_noesd[5] gnd 0.61fF
+C230 io_in_3v3[12] gnd 0.61fF
+C231 io_in[12] gnd 0.61fF
+C232 io_out[12] gnd 0.61fF
+C233 io_oeb[12] gnd 0.61fF
+C234 io_oeb[14] gnd 0.61fF
+C235 io_out[14] gnd 0.61fF
+C236 io_in[14] gnd 0.61fF
+C237 io_in_3v3[14] gnd 0.61fF
+C238 gpio_noesd[7] gnd 0.61fF
+C239 gpio_analog[7] gnd 0.61fF
+C240 vssa2 gnd 13.04fF
+C241 gpio_analog[6] gnd 0.61fF
+C242 gpio_noesd[6] gnd 0.61fF
+C243 io_in_3v3[13] gnd 0.61fF
+C244 io_in[13] gnd 0.61fF
+C245 io_out[13] gnd 0.61fF
+C246 io_oeb[13] gnd 0.61fF
+C247 vccd1 gnd 13.04fF
+C248 vccd2 gnd 13.04fF
+C249 io_analog[0] gnd 6.83fF
+C250 io_analog[10] gnd 6.83fF
+C251 io_analog[1] gnd 6.83fF
+C252 io_analog[2] gnd 6.83fF
+C253 io_analog[3] gnd 6.83fF
+C254 io_clamp_high[0] gnd 3.58fF
+C255 io_clamp_low[0] gnd 3.58fF
+C256 io_clamp_high[1] gnd 3.58fF
+C257 io_clamp_low[1] gnd 3.58fF
+C258 io_clamp_high[2] gnd 3.58fF
+C259 io_clamp_low[2] gnd 3.58fF
+C260 io_analog[7] gnd 6.83fF
+C261 io_analog[8] gnd 6.83fF
+C262 io_analog[9] gnd 6.83fF
+C263 user_irq[2] gnd 0.63fF
+C264 user_irq[1] gnd 0.63fF
+C265 user_irq[0] gnd 0.63fF
+C266 user_clock2 gnd 0.63fF
+C267 la_oenb[127] gnd 0.63fF
+C268 la_data_out[127] gnd 0.63fF
+C269 la_data_in[127] gnd 0.63fF
+C270 la_oenb[126] gnd 0.63fF
+C271 la_data_out[126] gnd 0.63fF
+C272 la_data_in[126] gnd 0.63fF
+C273 la_oenb[125] gnd 0.63fF
+C274 la_data_out[125] gnd 0.63fF
+C275 la_data_in[125] gnd 0.63fF
+C276 la_oenb[124] gnd 0.63fF
+C277 la_data_out[124] gnd 0.63fF
+C278 la_data_in[124] gnd 0.63fF
+C279 la_oenb[123] gnd 0.63fF
+C280 la_data_out[123] gnd 0.63fF
+C281 la_data_in[123] gnd 0.63fF
+C282 la_oenb[122] gnd 0.63fF
+C283 la_data_out[122] gnd 0.63fF
+C284 la_data_in[122] gnd 0.63fF
+C285 la_oenb[121] gnd 0.63fF
+C286 la_data_out[121] gnd 0.63fF
+C287 la_data_in[121] gnd 0.63fF
+C288 la_oenb[120] gnd 0.63fF
+C289 la_data_out[120] gnd 0.63fF
+C290 la_data_in[120] gnd 0.63fF
+C291 la_oenb[119] gnd 0.63fF
+C292 la_data_out[119] gnd 0.63fF
+C293 la_data_in[119] gnd 0.63fF
+C294 la_oenb[118] gnd 0.63fF
+C295 la_data_out[118] gnd 0.63fF
+C296 la_data_in[118] gnd 0.63fF
+C297 la_oenb[117] gnd 0.63fF
+C298 la_data_out[117] gnd 0.63fF
+C299 la_data_in[117] gnd 0.63fF
+C300 la_oenb[116] gnd 0.63fF
+C301 la_data_out[116] gnd 0.63fF
+C302 la_data_in[116] gnd 0.63fF
+C303 la_oenb[115] gnd 0.63fF
+C304 la_data_out[115] gnd 0.63fF
+C305 la_data_in[115] gnd 0.63fF
+C306 la_oenb[114] gnd 0.63fF
+C307 la_data_out[114] gnd 0.63fF
+C308 la_data_in[114] gnd 0.63fF
+C309 la_oenb[113] gnd 0.63fF
+C310 la_data_out[113] gnd 0.63fF
+C311 la_data_in[113] gnd 0.63fF
+C312 la_oenb[112] gnd 0.63fF
+C313 la_data_out[112] gnd 0.63fF
+C314 la_data_in[112] gnd 0.63fF
+C315 la_oenb[111] gnd 0.63fF
+C316 la_data_out[111] gnd 0.63fF
+C317 la_data_in[111] gnd 0.63fF
+C318 la_oenb[110] gnd 0.63fF
+C319 la_data_out[110] gnd 0.63fF
+C320 la_data_in[110] gnd 0.63fF
+C321 la_oenb[109] gnd 0.63fF
+C322 la_data_out[109] gnd 0.63fF
+C323 la_data_in[109] gnd 0.63fF
+C324 la_oenb[108] gnd 0.63fF
+C325 la_data_out[108] gnd 0.63fF
+C326 la_data_in[108] gnd 0.63fF
+C327 la_oenb[107] gnd 0.63fF
+C328 la_data_out[107] gnd 0.63fF
+C329 la_data_in[107] gnd 0.63fF
+C330 la_oenb[106] gnd 0.63fF
+C331 la_data_out[106] gnd 0.63fF
+C332 la_data_in[106] gnd 0.63fF
+C333 la_oenb[105] gnd 0.63fF
+C334 la_data_out[105] gnd 0.63fF
+C335 la_data_in[105] gnd 0.63fF
+C336 la_oenb[104] gnd 0.63fF
+C337 la_data_out[104] gnd 0.63fF
+C338 la_data_in[104] gnd 0.63fF
+C339 la_oenb[103] gnd 0.63fF
+C340 la_data_out[103] gnd 0.63fF
+C341 la_data_in[103] gnd 0.63fF
+C342 la_oenb[102] gnd 0.63fF
+C343 la_data_out[102] gnd 0.63fF
+C344 la_data_in[102] gnd 0.63fF
+C345 la_oenb[101] gnd 0.63fF
+C346 la_data_out[101] gnd 0.63fF
+C347 la_data_in[101] gnd 0.63fF
+C348 la_oenb[100] gnd 0.63fF
+C349 la_data_out[100] gnd 0.63fF
+C350 la_data_in[100] gnd 0.63fF
+C351 la_oenb[99] gnd 0.63fF
+C352 la_data_out[99] gnd 0.63fF
+C353 la_data_in[99] gnd 0.63fF
+C354 la_oenb[98] gnd 0.63fF
+C355 la_data_out[98] gnd 0.63fF
+C356 la_data_in[98] gnd 0.63fF
+C357 la_oenb[97] gnd 0.63fF
+C358 la_data_out[97] gnd 0.63fF
+C359 la_data_in[97] gnd 0.63fF
+C360 la_oenb[96] gnd 0.63fF
+C361 la_data_out[96] gnd 0.63fF
+C362 la_data_in[96] gnd 0.63fF
+C363 la_oenb[95] gnd 0.63fF
+C364 la_data_out[95] gnd 0.63fF
+C365 la_data_in[95] gnd 0.63fF
+C366 la_oenb[94] gnd 0.63fF
+C367 la_data_out[94] gnd 0.63fF
+C368 la_data_in[94] gnd 0.63fF
+C369 la_oenb[93] gnd 0.63fF
+C370 la_data_out[93] gnd 0.63fF
+C371 la_data_in[93] gnd 0.63fF
+C372 la_oenb[92] gnd 0.63fF
+C373 la_data_out[92] gnd 0.63fF
+C374 la_data_in[92] gnd 0.63fF
+C375 la_oenb[91] gnd 0.63fF
+C376 la_data_out[91] gnd 0.63fF
+C377 la_data_in[91] gnd 0.63fF
+C378 la_oenb[90] gnd 0.63fF
+C379 la_data_out[90] gnd 0.63fF
+C380 la_data_in[90] gnd 0.63fF
+C381 la_oenb[89] gnd 0.63fF
+C382 la_data_out[89] gnd 0.63fF
+C383 la_data_in[89] gnd 0.63fF
+C384 la_oenb[88] gnd 0.63fF
+C385 la_data_out[88] gnd 0.63fF
+C386 la_data_in[88] gnd 0.63fF
+C387 la_oenb[87] gnd 0.63fF
+C388 la_data_out[87] gnd 0.63fF
+C389 la_data_in[87] gnd 0.63fF
+C390 la_oenb[86] gnd 0.63fF
+C391 la_data_out[86] gnd 0.63fF
+C392 la_data_in[86] gnd 0.63fF
+C393 la_oenb[85] gnd 0.63fF
+C394 la_data_out[85] gnd 0.63fF
+C395 la_data_in[85] gnd 0.63fF
+C396 la_oenb[84] gnd 0.63fF
+C397 la_data_out[84] gnd 0.63fF
+C398 la_data_in[84] gnd 0.63fF
+C399 la_oenb[83] gnd 0.63fF
+C400 la_data_out[83] gnd 0.63fF
+C401 la_data_in[83] gnd 0.63fF
+C402 la_oenb[82] gnd 0.63fF
+C403 la_data_out[82] gnd 0.63fF
+C404 la_data_in[82] gnd 0.63fF
+C405 la_oenb[81] gnd 0.63fF
+C406 la_data_out[81] gnd 0.63fF
+C407 la_data_in[81] gnd 0.63fF
+C408 la_oenb[80] gnd 0.63fF
+C409 la_data_out[80] gnd 0.63fF
+C410 la_data_in[80] gnd 0.63fF
+C411 la_oenb[79] gnd 0.63fF
+C412 la_data_out[79] gnd 0.63fF
+C413 la_data_in[79] gnd 0.63fF
+C414 la_oenb[78] gnd 0.63fF
+C415 la_data_out[78] gnd 0.63fF
+C416 la_data_in[78] gnd 0.63fF
+C417 la_oenb[77] gnd 0.63fF
+C418 la_data_out[77] gnd 0.63fF
+C419 la_data_in[77] gnd 0.63fF
+C420 la_oenb[76] gnd 0.63fF
+C421 la_data_out[76] gnd 0.63fF
+C422 la_data_in[76] gnd 0.63fF
+C423 la_oenb[75] gnd 0.63fF
+C424 la_data_out[75] gnd 0.63fF
+C425 la_data_in[75] gnd 0.63fF
+C426 la_oenb[74] gnd 0.63fF
+C427 la_data_out[74] gnd 0.63fF
+C428 la_data_in[74] gnd 0.63fF
+C429 la_oenb[73] gnd 0.63fF
+C430 la_data_out[73] gnd 0.63fF
+C431 la_data_in[73] gnd 0.63fF
+C432 la_oenb[72] gnd 0.63fF
+C433 la_data_out[72] gnd 0.63fF
+C434 la_data_in[72] gnd 0.63fF
+C435 la_oenb[71] gnd 0.63fF
+C436 la_data_out[71] gnd 0.63fF
+C437 la_data_in[71] gnd 0.63fF
+C438 la_oenb[70] gnd 0.63fF
+C439 la_data_out[70] gnd 0.63fF
+C440 la_data_in[70] gnd 0.63fF
+C441 la_oenb[69] gnd 0.63fF
+C442 la_data_out[69] gnd 0.63fF
+C443 la_data_in[69] gnd 0.63fF
+C444 la_oenb[68] gnd 0.63fF
+C445 la_data_out[68] gnd 0.63fF
+C446 la_data_in[68] gnd 0.63fF
+C447 la_oenb[67] gnd 0.63fF
+C448 la_data_out[67] gnd 0.63fF
+C449 la_data_in[67] gnd 0.63fF
+C450 la_oenb[66] gnd 0.63fF
+C451 la_data_out[66] gnd 0.63fF
+C452 la_data_in[66] gnd 0.63fF
+C453 la_oenb[65] gnd 0.63fF
+C454 la_data_out[65] gnd 0.63fF
+C455 la_data_in[65] gnd 0.63fF
+C456 la_oenb[64] gnd 0.63fF
+C457 la_data_out[64] gnd 0.63fF
+C458 la_data_in[64] gnd 0.63fF
+C459 la_oenb[63] gnd 0.63fF
+C460 la_data_out[63] gnd 0.63fF
+C461 la_data_in[63] gnd 0.63fF
+C462 la_oenb[62] gnd 0.63fF
+C463 la_data_out[62] gnd 0.63fF
+C464 la_data_in[62] gnd 0.63fF
+C465 la_oenb[61] gnd 0.63fF
+C466 la_data_out[61] gnd 0.63fF
+C467 la_data_in[61] gnd 0.63fF
+C468 la_oenb[60] gnd 0.63fF
+C469 la_data_out[60] gnd 0.63fF
+C470 la_data_in[60] gnd 0.63fF
+C471 la_oenb[59] gnd 0.63fF
+C472 la_data_out[59] gnd 0.63fF
+C473 la_data_in[59] gnd 0.63fF
+C474 la_oenb[58] gnd 0.63fF
+C475 la_data_out[58] gnd 0.63fF
+C476 la_data_in[58] gnd 0.63fF
+C477 la_oenb[57] gnd 0.63fF
+C478 la_data_out[57] gnd 0.63fF
+C479 la_data_in[57] gnd 0.63fF
+C480 la_oenb[56] gnd 0.63fF
+C481 la_data_out[56] gnd 0.63fF
+C482 la_data_in[56] gnd 0.63fF
+C483 la_oenb[55] gnd 0.63fF
+C484 la_data_out[55] gnd 0.63fF
+C485 la_data_in[55] gnd 0.63fF
+C486 la_oenb[54] gnd 0.63fF
+C487 la_data_out[54] gnd 0.63fF
+C488 la_data_in[54] gnd 0.63fF
+C489 la_oenb[53] gnd 0.63fF
+C490 la_data_out[53] gnd 0.63fF
+C491 la_data_in[53] gnd 0.63fF
+C492 la_oenb[52] gnd 0.63fF
+C493 la_data_out[52] gnd 0.63fF
+C494 la_data_in[52] gnd 0.63fF
+C495 la_oenb[51] gnd 0.63fF
+C496 la_data_out[51] gnd 0.63fF
+C497 la_data_in[51] gnd 0.63fF
+C498 la_oenb[50] gnd 0.63fF
+C499 la_data_out[50] gnd 0.63fF
+C500 la_data_in[50] gnd 0.63fF
+C501 la_oenb[49] gnd 0.63fF
+C502 la_data_out[49] gnd 0.63fF
+C503 la_data_in[49] gnd 0.63fF
+C504 la_oenb[48] gnd 0.63fF
+C505 la_data_out[48] gnd 0.63fF
+C506 la_data_in[48] gnd 0.63fF
+C507 la_oenb[47] gnd 0.63fF
+C508 la_data_out[47] gnd 0.63fF
+C509 la_data_in[47] gnd 0.63fF
+C510 la_oenb[46] gnd 0.63fF
+C511 la_data_out[46] gnd 0.63fF
+C512 la_data_in[46] gnd 0.63fF
+C513 la_oenb[45] gnd 0.63fF
+C514 la_data_out[45] gnd 0.63fF
+C515 la_data_in[45] gnd 0.63fF
+C516 la_oenb[44] gnd 0.63fF
+C517 la_data_out[44] gnd 0.63fF
+C518 la_data_in[44] gnd 0.63fF
+C519 la_oenb[43] gnd 0.63fF
+C520 la_data_out[43] gnd 0.63fF
+C521 la_data_in[43] gnd 0.63fF
+C522 la_oenb[42] gnd 0.63fF
+C523 la_data_out[42] gnd 0.63fF
+C524 la_data_in[42] gnd 0.63fF
+C525 la_oenb[41] gnd 0.63fF
+C526 la_data_out[41] gnd 0.63fF
+C527 la_data_in[41] gnd 0.63fF
+C528 la_oenb[40] gnd 0.63fF
+C529 la_data_out[40] gnd 0.63fF
+C530 la_data_in[40] gnd 0.63fF
+C531 la_oenb[39] gnd 0.63fF
+C532 la_data_out[39] gnd 0.63fF
+C533 la_data_in[39] gnd 0.63fF
+C534 la_oenb[38] gnd 0.63fF
+C535 la_data_out[38] gnd 0.63fF
+C536 la_data_in[38] gnd 0.63fF
+C537 la_oenb[37] gnd 0.63fF
+C538 la_data_out[37] gnd 0.63fF
+C539 la_data_in[37] gnd 0.63fF
+C540 la_oenb[36] gnd 0.63fF
+C541 la_data_out[36] gnd 0.63fF
+C542 la_data_in[36] gnd 0.63fF
+C543 la_oenb[35] gnd 0.63fF
+C544 la_data_out[35] gnd 0.63fF
+C545 la_data_in[35] gnd 0.63fF
+C546 la_oenb[34] gnd 0.63fF
+C547 la_data_out[34] gnd 0.63fF
+C548 la_data_in[34] gnd 0.63fF
+C549 la_oenb[33] gnd 0.63fF
+C550 la_data_out[33] gnd 0.63fF
+C551 la_data_in[33] gnd 0.63fF
+C552 la_oenb[32] gnd 0.63fF
+C553 la_data_out[32] gnd 0.63fF
+C554 la_data_in[32] gnd 0.63fF
+C555 la_oenb[31] gnd 0.63fF
+C556 la_data_out[31] gnd 0.63fF
+C557 la_data_in[31] gnd 0.63fF
+C558 la_oenb[30] gnd 0.63fF
+C559 la_data_out[30] gnd 0.63fF
+C560 la_data_in[30] gnd 0.63fF
+C561 la_oenb[29] gnd 0.63fF
+C562 la_data_out[29] gnd 0.63fF
+C563 la_data_in[29] gnd 0.63fF
+C564 la_oenb[28] gnd 0.63fF
+C565 la_data_out[28] gnd 0.63fF
+C566 la_data_in[28] gnd 0.63fF
+C567 la_oenb[27] gnd 0.63fF
+C568 la_data_out[27] gnd 0.63fF
+C569 la_data_in[27] gnd 0.63fF
+C570 la_oenb[26] gnd 0.63fF
+C571 la_data_out[26] gnd 0.63fF
+C572 la_data_in[26] gnd 0.63fF
+C573 la_oenb[25] gnd 0.63fF
+C574 la_data_out[25] gnd 0.63fF
+C575 la_data_in[25] gnd 0.63fF
+C576 la_oenb[24] gnd 0.63fF
+C577 la_data_out[24] gnd 0.63fF
+C578 la_data_in[24] gnd 0.63fF
+C579 la_oenb[23] gnd 0.63fF
+C580 la_data_out[23] gnd 0.63fF
+C581 la_data_in[23] gnd 0.63fF
+C582 la_oenb[22] gnd 0.63fF
+C583 la_data_out[22] gnd 0.63fF
+C584 la_data_in[22] gnd 0.63fF
+C585 la_oenb[21] gnd 0.63fF
+C586 la_data_out[21] gnd 0.63fF
+C587 la_data_in[21] gnd 0.63fF
+C588 la_oenb[20] gnd 0.63fF
+C589 la_data_out[20] gnd 0.63fF
+C590 la_data_in[20] gnd 0.63fF
+C591 la_oenb[19] gnd 0.63fF
+C592 la_data_out[19] gnd 0.63fF
+C593 la_data_in[19] gnd 0.63fF
+C594 la_oenb[18] gnd 0.63fF
+C595 la_data_out[18] gnd 0.63fF
+C596 la_data_in[18] gnd 0.63fF
+C597 la_oenb[17] gnd 0.63fF
+C598 la_data_out[17] gnd 0.63fF
+C599 la_data_in[17] gnd 0.63fF
+C600 la_oenb[16] gnd 0.63fF
+C601 la_data_out[16] gnd 0.63fF
+C602 la_data_in[16] gnd 0.63fF
+C603 la_oenb[15] gnd 0.63fF
+C604 la_data_out[15] gnd 0.63fF
+C605 la_data_in[15] gnd 0.63fF
+C606 la_oenb[14] gnd 0.63fF
+C607 la_data_out[14] gnd 0.63fF
+C608 la_data_in[14] gnd 0.63fF
+C609 la_oenb[13] gnd 0.63fF
+C610 la_data_out[13] gnd 0.63fF
+C611 la_data_in[13] gnd 0.63fF
+C612 la_oenb[12] gnd 0.63fF
+C613 la_data_out[12] gnd 0.63fF
+C614 la_data_in[12] gnd 0.63fF
+C615 la_oenb[11] gnd 0.63fF
+C616 la_data_out[11] gnd 0.63fF
+C617 la_data_in[11] gnd 0.63fF
+C618 la_oenb[10] gnd 0.63fF
+C619 la_data_out[10] gnd 0.63fF
+C620 la_data_in[10] gnd 0.63fF
+C621 la_oenb[9] gnd 0.63fF
+C622 la_data_out[9] gnd 0.63fF
+C623 la_data_in[9] gnd 0.63fF
+C624 la_oenb[8] gnd 0.63fF
+C625 la_data_out[8] gnd 0.63fF
+C626 la_data_in[8] gnd 0.63fF
+C627 la_oenb[7] gnd 0.63fF
+C628 la_data_out[7] gnd 0.63fF
+C629 la_data_in[7] gnd 0.63fF
+C630 la_oenb[6] gnd 0.63fF
+C631 la_data_out[6] gnd 0.63fF
+C632 la_data_in[6] gnd 0.63fF
+C633 la_oenb[5] gnd 0.63fF
+C634 la_data_out[5] gnd 0.63fF
+C635 la_data_in[5] gnd 0.63fF
+C636 la_oenb[4] gnd 0.63fF
+C637 la_data_out[4] gnd 0.63fF
+C638 la_data_in[4] gnd 0.63fF
+C639 la_oenb[3] gnd 0.63fF
+C640 la_data_out[3] gnd 0.63fF
+C641 la_data_in[3] gnd 0.63fF
+C642 la_oenb[2] gnd 0.63fF
+C643 la_data_out[2] gnd 0.63fF
+C644 la_data_in[2] gnd 0.63fF
+C645 la_oenb[1] gnd 0.63fF
+C646 la_data_out[1] gnd 0.63fF
+C647 la_data_in[1] gnd 0.63fF
+C648 la_oenb[0] gnd 0.63fF
+C649 la_data_out[0] gnd 0.63fF
+C650 la_data_in[0] gnd 0.63fF
+C651 wbs_dat_o[31] gnd 0.63fF
+C652 wbs_dat_i[31] gnd 0.63fF
+C653 wbs_adr_i[31] gnd 0.63fF
+C654 wbs_dat_o[30] gnd 0.63fF
+C655 wbs_dat_i[30] gnd 0.63fF
+C656 wbs_adr_i[30] gnd 0.63fF
+C657 wbs_dat_o[29] gnd 0.63fF
+C658 wbs_dat_i[29] gnd 0.63fF
+C659 wbs_adr_i[29] gnd 0.63fF
+C660 wbs_dat_o[28] gnd 0.63fF
+C661 wbs_dat_i[28] gnd 0.63fF
+C662 wbs_adr_i[28] gnd 0.63fF
+C663 wbs_dat_o[27] gnd 0.63fF
+C664 wbs_dat_i[27] gnd 0.63fF
+C665 wbs_adr_i[27] gnd 0.63fF
+C666 wbs_dat_o[26] gnd 0.63fF
+C667 wbs_dat_i[26] gnd 0.63fF
+C668 wbs_adr_i[26] gnd 0.63fF
+C669 wbs_dat_o[25] gnd 0.63fF
+C670 wbs_dat_i[25] gnd 0.63fF
+C671 wbs_adr_i[25] gnd 0.63fF
+C672 wbs_dat_o[24] gnd 0.63fF
+C673 wbs_dat_i[24] gnd 0.63fF
+C674 wbs_adr_i[24] gnd 0.63fF
+C675 wbs_dat_o[23] gnd 0.63fF
+C676 wbs_dat_i[23] gnd 0.63fF
+C677 wbs_adr_i[23] gnd 0.63fF
+C678 wbs_dat_o[22] gnd 0.63fF
+C679 wbs_dat_i[22] gnd 0.63fF
+C680 wbs_adr_i[22] gnd 0.63fF
+C681 wbs_dat_o[21] gnd 0.63fF
+C682 wbs_dat_i[21] gnd 0.63fF
+C683 wbs_adr_i[21] gnd 0.63fF
+C684 wbs_dat_o[20] gnd 0.63fF
+C685 wbs_dat_i[20] gnd 0.63fF
+C686 wbs_adr_i[20] gnd 0.63fF
+C687 wbs_dat_o[19] gnd 0.63fF
+C688 wbs_dat_i[19] gnd 0.63fF
+C689 wbs_adr_i[19] gnd 0.63fF
+C690 wbs_dat_o[18] gnd 0.63fF
+C691 wbs_dat_i[18] gnd 0.63fF
+C692 wbs_adr_i[18] gnd 0.63fF
+C693 wbs_dat_o[17] gnd 0.63fF
+C694 wbs_dat_i[17] gnd 0.63fF
+C695 wbs_adr_i[17] gnd 0.63fF
+C696 wbs_dat_o[16] gnd 0.63fF
+C697 wbs_dat_i[16] gnd 0.63fF
+C698 wbs_adr_i[16] gnd 0.63fF
+C699 wbs_dat_o[15] gnd 0.63fF
+C700 wbs_dat_i[15] gnd 0.63fF
+C701 wbs_adr_i[15] gnd 0.63fF
+C702 wbs_dat_o[14] gnd 0.63fF
+C703 wbs_dat_i[14] gnd 0.63fF
+C704 wbs_adr_i[14] gnd 0.63fF
+C705 wbs_dat_o[13] gnd 0.63fF
+C706 wbs_dat_i[13] gnd 0.63fF
+C707 wbs_adr_i[13] gnd 0.63fF
+C708 wbs_dat_o[12] gnd 0.63fF
+C709 wbs_dat_i[12] gnd 0.63fF
+C710 wbs_adr_i[12] gnd 0.63fF
+C711 wbs_dat_o[11] gnd 0.63fF
+C712 wbs_dat_i[11] gnd 0.63fF
+C713 wbs_adr_i[11] gnd 0.63fF
+C714 wbs_dat_o[10] gnd 0.63fF
+C715 wbs_dat_i[10] gnd 0.63fF
+C716 wbs_adr_i[10] gnd 0.63fF
+C717 wbs_dat_o[9] gnd 0.63fF
+C718 wbs_dat_i[9] gnd 0.63fF
+C719 wbs_adr_i[9] gnd 0.63fF
+C720 wbs_dat_o[8] gnd 0.63fF
+C721 wbs_dat_i[8] gnd 0.63fF
+C722 wbs_adr_i[8] gnd 0.63fF
+C723 wbs_dat_o[7] gnd 0.63fF
+C724 wbs_dat_i[7] gnd 0.63fF
+C725 wbs_adr_i[7] gnd 0.63fF
+C726 wbs_dat_o[6] gnd 0.63fF
+C727 wbs_dat_i[6] gnd 0.63fF
+C728 wbs_adr_i[6] gnd 0.63fF
+C729 wbs_dat_o[5] gnd 0.63fF
+C730 wbs_dat_i[5] gnd 0.63fF
+C731 wbs_adr_i[5] gnd 0.63fF
+C732 wbs_dat_o[4] gnd 0.63fF
+C733 wbs_dat_i[4] gnd 0.63fF
+C734 wbs_adr_i[4] gnd 0.63fF
+C735 wbs_sel_i[3] gnd 0.63fF
+C736 wbs_dat_o[3] gnd 0.63fF
+C737 wbs_dat_i[3] gnd 0.63fF
+C738 wbs_adr_i[3] gnd 0.63fF
+C739 wbs_sel_i[2] gnd 0.63fF
+C740 wbs_dat_o[2] gnd 0.63fF
+C741 wbs_dat_i[2] gnd 0.63fF
+C742 wbs_adr_i[2] gnd 0.63fF
+C743 wbs_sel_i[1] gnd 0.63fF
+C744 wbs_dat_o[1] gnd 0.63fF
+C745 wbs_dat_i[1] gnd 0.63fF
+C746 wbs_adr_i[1] gnd 0.63fF
+C747 wbs_sel_i[0] gnd 0.63fF
+C748 wbs_dat_o[0] gnd 0.63fF
+C749 wbs_dat_i[0] gnd 0.63fF
+C750 wbs_adr_i[0] gnd 0.63fF
+C751 wbs_we_i gnd 0.63fF
+C752 wbs_stb_i gnd 0.63fF
+C753 wbs_cyc_i gnd 0.63fF
+C754 wbs_ack_o gnd 0.63fF
+C755 wb_rst_i gnd 0.63fF
+C756 wb_clk_i gnd 0.63fF
+C757 ro_complete_0/cbank_2/switch_0/vin gnd 1.60fF
+C758 ro_complete_0/cbank_2/v gnd 16.05fF
+C759 ro_complete_0/cbank_2/switch_5/vin gnd 1.72fF
+C760 ro_complete_0/a5 gnd 6.55fF
+C761 ro_complete_0/cbank_2/switch_4/vin gnd 0.94fF
+C762 ro_complete_0/a4 gnd 5.57fF
+C763 ro_complete_0/cbank_2/switch_3/vin gnd 1.20fF
+C764 ro_complete_0/a3 gnd 5.42fF
+C765 ro_complete_0/cbank_2/switch_2/vin gnd 1.30fF
+C766 ro_complete_0/a2 gnd 6.43fF
+C767 ro_complete_0/cbank_2/switch_1/vin gnd 1.06fF
+C768 ro_complete_0/a1 gnd 6.15fF
+C769 ro_complete_0/a0 gnd 5.31fF
+C770 ro_complete_0/cbank_1/switch_0/vin gnd 1.60fF
+C771 ro_complete_0/cbank_1/v gnd 15.97fF
+C772 ro_complete_0/cbank_1/switch_5/vin gnd 1.72fF
+C773 ro_complete_0/cbank_1/switch_4/vin gnd 0.94fF
+C774 ro_complete_0/cbank_1/switch_3/vin gnd 1.20fF
+C775 ro_complete_0/cbank_1/switch_2/vin gnd 1.30fF
+C776 ro_complete_0/cbank_1/switch_1/vin gnd 1.06fF
+C777 ro_complete_0/cbank_0/switch_0/vin gnd 1.60fF
+C778 ro_complete_0/cbank_0/v gnd 14.97fF
+C779 ro_complete_0/cbank_0/switch_5/vin gnd 1.72fF
+C780 ro_complete_0/cbank_0/switch_4/vin gnd 0.94fF
+C781 ro_complete_0/cbank_0/switch_3/vin gnd 1.20fF
+C782 ro_complete_0/cbank_0/switch_2/vin gnd 1.30fF
+C783 ro_complete_0/cbank_0/switch_1/vin gnd 1.06fF
+C784 ro_complete_0/ro_var_extend_0/vcont gnd 0.25fF **FLOATING
+.ends
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
index 2264f78..f843d71 100644
--- a/mag/user_analog_project_wrapper_empty.mag
+++ b/mag/user_analog_project_wrapper_empty.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1640880731
+timestamp 1640863034
<< metal2 >>
rect 262 -400 318 240
rect 853 -400 909 240
@@ -700,6 +700,22 @@
rect -50 0 0 352000
rect 292000 0 292050 352000
rect -50 -50 292050 0
+use pd pd_0 ../avadhani
+timestamp 1640777101
+transform 1 0 46233 0 1 340608
+box -115 -730 1470 690
+use divider divider_0 ../avadhani
+timestamp 1640857911
+transform 1 0 58605 0 1 340399
+box -185 -70 4395 1990
+use ro_complete ro_complete_0
+timestamp 1640809734
+transform 1 0 7163 0 1 344610
+box 362 -5330 4455 1180
+use cp cp_0
+timestamp 1640602475
+transform 1 0 33315 0 1 341930
+box -245 -1715 4500 2030
<< labels >>
flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
