commit 7fb10a7941b513e08105d4b2faa2192221031096
author asdhi <63298985+srestha-avadhani@users.noreply.github.com> Sat Jan 01 13:03:32 2022 +0530
committer GitHub <noreply@github.com> Sat Jan 01 13:03:32 2022 +0530
tree 49f5c01ea8a202d9ac3fdb344ae259f664d40b85
parent d5adcee77b469f5bb96a3ad22d03c5d41ef8443c

Update

Images/PLL.png

diff --git a/Images/PLL.png b/Images/PLL.png
new file mode 100644
index 0000000..52a8b19
--- /dev/null
+++ b/Images/PLL.png
Binary files differ

Readme.md

diff --git a/Readme.md b/Readme.md
index 9a24a00..7d33d21 100644
--- a/Readme.md
+++ b/Readme.md
@@ -4,7 +4,7 @@
 
 ## Project implementation
 The figure below shows the block diagram for the 2.87 GHz fractional-N sythesizer implemented in skywater 130nm tecnology.  
-![PLL loop](PLL.png "Fractional -N synthesiszer PLL")
+![PLL loop](Images/PLL.png "Fractional -N synthesiszer PLL")
 
 
 ### Simulation results