- 665a2af drc clean project ver1.0 by dineshannayya · 3 years, 3 months ago
- 6d8d774 test bench clean-up by dineshannayya · 3 years, 3 months ago
- 39fb862 first version of riscduino with sdram removed, pinmux and sar_adc added by dineshannayya · 3 years, 3 months ago
- 2223fbd pdk file are copied /opt/pdk inside the docker by dineshannayya · 3 years, 4 months ago
- 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 4 months ago
- c6a2a5d antenna fix by dineshannayya · 3 years, 4 months ago
- c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 3 years, 4 months ago
- fbc351b SPDX Non compliant text fix by dineshannayya · 3 years, 5 months ago
- 3ae1a2b usb1 host is integrated by dineshannayya · 3 years, 5 months ago
- 4f74e2f i2cm integrated and share same uart io by dineshannayya · 3 years, 5 months ago
- 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 5 months ago
- 9fdcbca syntacore timing fix by dineshannayya · 3 years, 5 months ago
- 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 3 years, 5 months ago
- 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years, 5 months ago
- 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 5 months ago
- a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years, 5 months ago
- 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 5 months ago
- 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 5 months ago
- 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years, 5 months ago
- daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 3 years, 5 months ago
- 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years, 5 months ago
- ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 6 months ago
- 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 6 months ago
- a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years, 6 months ago
- 311a4e0 precheck cleanup by dineshannayya · 3 years, 6 months ago
- 76d58fb DRC clean user_project_wrapper by dineshannayya · 3 years, 6 months ago
- a908000 updated database by dineshannayya · 3 years, 6 months ago
- 81d24ed wb_host rtl and openlane setup added by dineshannayya · 3 years, 6 months ago
- feb1877 backand cleanup by dineshannayya · 3 years, 6 months ago
- 9112eeb user project def,lef,gds added by dineshannayya · 3 years, 6 months ago
- ed94965 database update by dineshannayya · 3 years, 6 months ago
- 3f698f9 script update by dineshannayya · 3 years, 6 months ago
- 1431d7b def,gds,lef addition by dineshannayya · 3 years, 6 months ago
- 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 3 years, 6 months ago
- ea1e6f3 floor planning cleanup by dineshannayya · 3 years, 6 months ago
- 44e67e1 first user project lvs clean database by dineshannayya · 3 years, 6 months ago
- 9ca8009 pin order update for sdram & syntacore by dineshannayya · 3 years, 6 months ago
- 2e2fad8 sdram added by dinesha · 3 years, 6 months ago
- 25e2d74 spi master added by dinesha · 3 years, 6 months ago
- fc4b9c4 syntacore added by dinesha · 3 years, 7 months ago
- 9e5d826 Initial version of efabless caravel user project by dinesha · 3 years, 7 months ago