- 05393e8 Basic Verification and Physical design cleanup by dineshannayya · 3 years, 5 months ago
- 6d8d774 test bench clean-up by dineshannayya · 3 years, 6 months ago
- a752b44 riscv regression with coremark test passing by dineshannayya · 3 years, 7 months ago
- 0081f48 timer_irq connectivity bug fix by dineshannayya · 3 years, 7 months ago
- 66179f7 riscv_regress simulation works through docker by dineshannayya · 3 years, 7 months ago
- f83393a riscv regression suite, riscv_isa and riscv_compliance test integrated by dineshannayya · 3 years, 7 months ago
- 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 8 months ago
- c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 8 months ago
- fbc351b SPDX Non compliant text fix by dineshannayya · 3 years, 8 months ago
- 3ae1a2b usb1 host is integrated by dineshannayya · 3 years, 8 months ago
- 4f74e2f i2cm integrated and share same uart io by dineshannayya · 3 years, 8 months ago
- 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 8 months ago
- 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 3 years, 8 months ago
- 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years, 8 months ago
- 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 9 months ago
- 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 9 months ago
- 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 9 months ago
- 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years, 9 months ago
- ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 9 months ago
- 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 9 months ago
- a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years, 9 months ago
- 311a4e0 precheck cleanup by dineshannayya · 3 years, 9 months ago
- a908000 updated database by dineshannayya · 3 years, 9 months ago
- feb1877 backand cleanup by dineshannayya · 3 years, 9 months ago
- 3f698f9 script update by dineshannayya · 3 years, 9 months ago
- 1431d7b def,gds,lef addition by dineshannayya · 3 years, 9 months ago
- e08e2a5 uart test case integration by dineshannayya · 3 years, 9 months ago
- b547314 uart test case integration by dineshannayya · 3 years, 9 months ago
- 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 3 years, 9 months ago
- 44e67e1 first user project lvs clean database by dineshannayya · 3 years, 9 months ago
- 21e5ba9 test bench update by dinesha · 3 years, 10 months ago
- 9e5d826 Initial version of efabless caravel user project by dinesha · 3 years, 10 months ago
