- 665a2af drc clean project ver1.0 by dineshannayya · 3 years, 5 months ago
- 6d8d774 test bench clean-up by dineshannayya · 3 years, 6 months ago
- 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 7 months ago
- c6a2a5d antenna fix by dineshannayya · 3 years, 7 months ago
- 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 8 months ago
- 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 8 months ago
- a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years, 8 months ago
- 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 8 months ago
- 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 8 months ago
- 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years, 8 months ago
- ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 8 months ago
- 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 9 months ago
- 76d58fb DRC clean user_project_wrapper by dineshannayya · 3 years, 9 months ago
- a908000 updated database by dineshannayya · 3 years, 9 months ago
- feb1877 backand cleanup by dineshannayya · 3 years, 9 months ago
- 3f698f9 script update by dineshannayya · 3 years, 9 months ago
- e08e2a5 uart test case integration by dineshannayya · 3 years, 9 months ago
- 44e67e1 first user project lvs clean database by dineshannayya · 3 years, 9 months ago
