commit 26743b220f2d184cba74d212eccbaec4fc76ecc8
author dineshannayya <dinesh.annayya@gmail.com> Mon Aug 16 19:18:49 2021 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Mon Aug 16 19:18:49 2021 +0530
tree 685bf7b4ff5c7bb53ad1ce160d78aa5a390b62fc
parent 337d9f86bef06f4583bf3a8327cb8efc597878ad

modelsim compile cleanup

verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv

diff --git a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
index eabaf49..d42adf4 100644
--- a/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
+++ b/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
@@ -188,7 +188,7 @@
     if (~rst_n) begin
 	exu2ialu_main_op1_ff <= '0;
         exu2ialu_main_op2_ff <= '0;
-        exu2ialu_cmd_ff      <= '0;
+        exu2ialu_cmd_ff      <= SCR1_IALU_CMD_NONE;
 	exu2ialu_rvm_cmd_vd_ff <= '0;
     end else begin
 	exu2ialu_main_op1_ff <= exu2ialu_main_op1_i;