|author||dineshannayya <firstname.lastname@example.org>||Tue Dec 21 21:29:29 2021 +0530|
|committer||dineshannayya <email@example.com>||Tue Dec 21 21:29:29 2021 +0530|
Read Me update
LOGIC BIST Controller Permission to use, copy, modify, and/or distribute this soc for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.
Logic built-in self-test (or LBIST) is a form of built-in self-test (BIST) in which hardware and/or software is built into integrated circuits allowing them to test their own operation.
Scan chains are traditionally controlled by expensive external test equipment (ATE) * requires large ram for test vectors for high coverage * requires high speed electronics for at-speed test * expensive
The main advantage of LBIST is the ability to test internal circuits having no direct connections to external pins.
LBIST that requires additional circuitry increases the cost of the integrated circuit. Another disadvantage of LBIST is the possibility that the on-chip testing hardware itself can fail; external automated test equipment tests the integrated circuit with known-good test circuitry.
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed. * Mbist controller with memory repair supported * LOGIC BIST with 8 Scan-in/Scan-out chain * Wishbone compatible design * Written in System Verilog * Open-source tool set * simulation - iverilog * synthesis - yosys * backend/sta - openlane tool set * Verification suite provided.
There are hacks are done in openlane script/tool to integrated the scan chain. The tool and scripts are updated in dineshannayya:mpw4 docker. Here are details on hacks:
Directory: OpenSTA (hacks/src/OpenSTA) Source Files: hacks/src/OpenSTA/network/ConcreteNetwork.cc hacks/src/OpenSTA/tcl/NetworkEdit.tcl hacks/src/OpenSTA/tcl/Sta.tcl Patch File: for OpenRoad docker hacks/patch/scan_swap.patch
Directory: OpenROAD Source Files: hacks/src/OpenROAD/Resizer.cc Patch File: for OpenRoad docker hacks/patch/resizer.patch
Directory: Openlane Source Files: hacks/src/openlane/io_place.py
Directory: Openlane Source Files: hacks/src/openlane/synth.tcl hacks/src/openlane/synth_top.tcl
all these hacks/patches are implemented inside dineshannayya:mpw4 docker
for logic bist to work properly, design should met these crieria.
Clock Doman: All the Sub block should be synchronous and use single clock
Reset: Scan Reset Bypass logic need to implemented
SRAM: SRAM input towards digital logic should have scan bypass
Register: All the Register should be able to re-initialize with reset, even the two dimensional FIFO.
Input: All the Input should be in known state, else add scan bypass logic
The simulation package includes the following tests:
make verify-wb_port make verify-user_basic make verify-user_mbist_test1 make verify-user_lbist make verify-wb_port SIM=RTL DUMP=OFF make verify-wb_port SIM=RTL DUMP=ON make verify-user_mbist_test1 SIM=RTL DUMP=OFF make verify-user_mbist_test1 SIM=RTL DUMP=ON make verify-user_lbist SIM=RTL DUMP=ON
Mbist Controller flow uses Openlane tool sets.
yosys- Performs RTL synthesis
abc- Performs technology mapping
OpenSTA- Pefroms static timing analysis on the resulting netlist to generate timing reports
init_fp- Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
ioplacer- Places the macro input and output ports
pdn- Generates the power distribution network
tapcell- Inserts welltap and decap cells in the floorplan
RePLace- Performs global placement
Resizer- Performs optional optimizations on the design
OpenPhySyn- Performs timing optimizations on the design
OpenDP- Perfroms detailed placement to legalize the globally placed components
TritonCTS- Synthesizes the clock distribution network (the clock tree)
FastRoute- Performs global routing to generate a guide file for the detailed router
CU-GR- Another option for performing global routing.
TritonRoute- Performs detailed routing
SPEF-Extractor- Performs SPEF extraction
Magic- Streams out the final GDSII layout file from the routed def
Klayout- Streams out the final GDSII layout file from the routed def as a back-up
Magic- Performs DRC Checks & Antenna Checks
Klayout- Performs DRC Checks
Netgen- Performs LVS Checks
CVC- Performs Circuit Validity Checks
Report an issue: https://github.com/dineshannayya/logic_bist/issues