commit	913410a7f65ff1418fead5874e5fa61bf7b7ceee	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Wed Oct 13 22:29:46 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Wed Oct 13 22:29:46 2021 +0530
tree	3f3bcb6e6a1a3be4a604372150168b4cb3390f54
parent	fc583ec64d0e153d10e4e28146342af0d0fecd6e [diff]

initial version of mbist

gds/user_proj_example.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
mag/user_proj_example.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
openlane/mbist/config.tcl[Added - diff]
openlane/mbist/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/interactive.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pdn.tcl[Added - diff]
openlane/wb_host/base.sdc[Added - diff]
openlane/wb_host/config.tcl[Added - diff]
openlane/wb_host/pin_order.cfg[Added - diff]
signoff/mbist/OPENLANE_VERSION[Added - diff]
signoff/mbist/PDK_SOURCES[Renamed from signoff/user_proj_example/PDK_SOURCES - diff]
signoff/mbist/final_summary_report.csv[Renamed from signoff/user_proj_example/final_summary_report.csv - diff]
signoff/user_proj_example/OPENLANE_VERSION[Deleted - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
signoff/wb_host/OPENLANE_VERSION[Added - diff]
signoff/wb_host/PDK_SOURCES[Copied from signoff/user_proj_example/PDK_SOURCES - diff]
signoff/wb_host/final_summary_report.csv[Copied from signoff/user_proj_example/final_summary_report.csv - diff]
verilog/gl/mbist.v[Added - diff]
verilog/gl/wb_host.v[Added - diff]
verilog/rtl/lib/async_fifo.sv[Added - diff]
verilog/rtl/lib/async_fifo_th.sv[Added - diff]
verilog/rtl/lib/async_wb.sv[Added - diff]
verilog/rtl/lib/clk_buf.v[Added - diff]
verilog/rtl/lib/clk_ctl.v[Added - diff]
verilog/rtl/lib/double_sync_high.v[Added - diff]
verilog/rtl/lib/double_sync_low.v[Added - diff]
verilog/rtl/lib/pulse_gen_type1.sv[Added - diff]
verilog/rtl/lib/pulse_gen_type2.sv[Added - diff]
verilog/rtl/lib/registers.v[Added - diff]
verilog/rtl/lib/reset_sync.sv[Added - diff]
verilog/rtl/lib/sync_fifo.sv[Added - diff]
verilog/rtl/lib/wb_interface.v[Added - diff]
verilog/rtl/lib/wb_stagging.sv[Added - diff]
verilog/rtl/mbist/include/mbist_def.svh[Added - diff]
verilog/rtl/mbist/src/mbist_addr_gen.sv[Added - diff]
verilog/rtl/mbist/src/mbist_data_cmp.sv[Added - diff]
verilog/rtl/mbist/src/mbist_fsm.sv[Added - diff]
verilog/rtl/mbist/src/mbist_mux.sv[Added - diff]
verilog/rtl/mbist/src/mbist_op_sel.sv[Added - diff]
verilog/rtl/mbist/src/mbist_pat_sel.sv[Added - diff]
verilog/rtl/mbist/src/mbist_repair_addr.sv[Added - diff]
verilog/rtl/mbist/src/mbist_sti_sel.sv[Added - diff]
verilog/rtl/mbist/src/mbist_top.sv[Added - diff]
verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wb_host/src/wb_host.sv[Added - diff]

53 files changed

tree: 3f3bcb6e6a1a3be4a604372150168b4cb3390f54

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.