commit 10d5277f24b5558f0349973e1261edcaca495817
author Manar <manarabdelatty@aucegypt.edu> Sat Apr 17 03:07:07 2021 +0200
committer GitHub <noreply@github.com> Sat Apr 17 03:07:07 2021 +0200
tree 0c3019c1b84c5e9f3032f1c88d781bf43a91354f
parent d868235d8ea8bf6cb2359b038fcef164ecfd331a

Update README.md

README.md

diff --git a/README.md b/README.md
index d597451..5df0dd1 100644
--- a/README.md
+++ b/README.md
@@ -19,13 +19,22 @@
 # Caravel User Project
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![CI](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_example_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_example_ci.yml)
 
+# Table of contents
+- [Overview](#overview)
+- [Caravel Integration](#caravel-integration)
+    - [Repo Integration](#repo-integration)
+    - [Verilog Integration](#verilog-integration)
+- [Running Full Chip Simulation](#running-full-chip-simulation)
+- [Hardening the User Project Macro using Openlane](#hardening-the-user-project-macro-using-openlane)
+- [Checklist for Open-MPW Submission](#checklist-for-open-mpw-submission)
+  
 # Overview
 
 This repo contains a sample user project that utilizes the [caravel](https://github.com/efabless/caravel.git) chip user space. The user project is a simple counter that showcases how to make use of [caravel's](https://github.com/efabless/caravel.git) user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw shuttle projects. 
 
 # Caravel Integration
 
-## Files Integration
+## Repo Integration
 
 Caravel files are kept separate from the user project by having caravel as submodule. The submodule commit should point to the latest of caravel master. The following files should have a symbolic link to [caravel's](https://github.com/efabless/caravel.git) corresponding files: 
 
@@ -66,7 +75,7 @@
 
 # Running Full Chip Simulation
 
-The verilog test-benches are under this [verilog/dv](verilog/dv). For more information on setting up the simulation environment and the available testbenches for this sample project, refer to [README] (verilog/dv/README.md).
+The verilog test-benches are under this [verilog/dv](verilog/dv). For more information on setting up the simulation environment and the available testbenches for this sample project, refer to [README](verilog/dv/README.md).
 
 # Hardening the User Project Macro using Openlane