commit: fe4778a90a6bf9680b95e6621ee9480ba7d89406
[log]
author: nguyendao-uom <nguyen.dao@manchester.ac.uk>
Tue Dec 28 11:07:32 2021 +0000
committer: nguyendao-uom <nguyen.dao@manchester.ac.uk>
Tue Dec 28 11:07:32 2021 +0000
tree: 6f1d7ed6845c9f4a87b5662feccf830f697dc164
parent: 2a3c94373ffc0e53a287be94a569a2139b1cb496 [diff]

update icesoc

caravel[diff]
def/user_project_wrapper.def[diff]
gds/user_project_wrapper.gds.gz[Added - diff]
info.yaml[Added - diff]
lef/eFPGA_CPU_top.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
verilog/dv/wb_test_icesoc/Makefile[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/Makefile[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/aes_common.h[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/crt.s[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/gen_program.py[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/link.ld[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/rv32zk.S[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/test.c[Added - diff]
verilog/dv/wb_test_icesoc/ibex_prog/zkn.h[Added - diff]
verilog/dv/wb_test_icesoc/wb_test_icesoc.c[Added - diff]
verilog/dv/wb_test_icesoc/wb_test_icesoc_tb.v[Added - diff]
verilog/dv/wb_to_sram/Makefile[Added - diff]
verilog/dv/wb_to_sram/wb_to_sram.c[Added - diff]
verilog/dv/wb_to_sram/wb_to_sram.hex[Added - diff]
verilog/dv/wb_to_sram/wb_to_sram_tb.v[Added - diff]
verilog/rtl/eFPGA_CPU_top.v[Added - diff]
verilog/rtl/eFPGA_conf/Config.v[Added - diff]
verilog/rtl/eFPGA_conf/ConfigFSM.v[Added - diff]
verilog/rtl/eFPGA_conf/Config_access.v[Added - diff]
verilog/rtl/eFPGA_conf/Frame_Data_Reg_Pack.v[Added - diff]
verilog/rtl/eFPGA_conf/Frame_Select_Pack.v[Added - diff]
verilog/rtl/eFPGA_conf/bitbang.v[Added - diff]
verilog/rtl/eFPGA_conf/config_UART.v[Added - diff]
verilog/rtl/eFPGA_conf/eFPGAconf_netlists.vh[Added - diff]
verilog/rtl/eFPGA_conf/fabric_DSP_tile.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_bot_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_bot_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_bot_tile.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_tile.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_top_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_top_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/DSP_top_tile.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_bot_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_bot_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_bot_tile.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/E_CPU_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/IO_1_bidirectional_frame_config_pass.v[Added - diff]
verilog/rtl/eFPGA_core/InPass4_frame_config_mux.v[Added - diff]
verilog/rtl/eFPGA_core/LUT4AB_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/LUT4AB_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/LUT4AB_tile.v[Added - diff]
verilog/rtl/eFPGA_core/LUT4c_frame_config_dffesr.v[Added - diff]
verilog/rtl/eFPGA_core/MULADD.v[Added - diff]
verilog/rtl/eFPGA_core/MUX8LUT_frame_config_mux.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_DSP_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_DSP_tile.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_RAM_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_single2_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_single2_tile.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_single_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/N_term_single_tile.v[Added - diff]
verilog/rtl/eFPGA_core/OutPass4_frame_config_mux.v[Added - diff]
verilog/rtl/eFPGA_core/RAM_IO_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/RAM_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/RegFile_32x4.v[Added - diff]
verilog/rtl/eFPGA_core/RegFile_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/RegFile_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/RegFile_tile.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_DSP_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_DSP_tile.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_RAM_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_RAM_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_single2_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_single2_tile.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_single_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/S_term_single_tile.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_bot_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_bot_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_bot_tile.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/W_CPU_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/W_IO_ConfigMem.v[Added - diff]
verilog/rtl/eFPGA_core/W_IO_switch_matrix.v[Added - diff]
verilog/rtl/eFPGA_core/W_IO_tile.v[Added - diff]
verilog/rtl/eFPGA_core/eFPGAcore_netlists.vh[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_alu.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_compressed_decoder.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_controller.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_core.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_cs_registers.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_decoder.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_defines.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_eFPGA.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_ex_block.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_fetch_fifo.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_id_stage.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_if_stage.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_int_controller.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_load_store_unit.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_multdiv_fast.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_prefetch_buffer.v[Added - diff]
verilog/rtl/ibex_core/flexbex_ibex_register_file.v[Added - diff]
verilog/rtl/ibex_core/flexbex_prim_clock_gating.v[Added - diff]
verilog/rtl/ibex_core/ibex_aes_sbox.v[Added - diff]
verilog/rtl/ibex_core/ibex_alu.v[Added - diff]
verilog/rtl/ibex_core/ibex_branch_predict.v[Added - diff]
verilog/rtl/ibex_core/ibex_compressed_decoder.v[Added - diff]
verilog/rtl/ibex_core/ibex_controller.v[Added - diff]
verilog/rtl/ibex_core/ibex_core.v[Added - diff]
verilog/rtl/ibex_core/ibex_counter.v[Added - diff]
verilog/rtl/ibex_core/ibex_cs_registers.v[Added - diff]
verilog/rtl/ibex_core/ibex_csr.v[Added - diff]
verilog/rtl/ibex_core/ibex_decoder.v[Added - diff]
verilog/rtl/ibex_core/ibex_eFPGA.v[Added - diff]
verilog/rtl/ibex_core/ibex_ex_block.v[Added - diff]
verilog/rtl/ibex_core/ibex_fetch_fifo.v[Added - diff]
verilog/rtl/ibex_core/ibex_icache.v[Added - diff]
verilog/rtl/ibex_core/ibex_id_stage.v[Added - diff]
verilog/rtl/ibex_core/ibex_if_stage.v[Added - diff]
verilog/rtl/ibex_core/ibex_load_store_unit.v[Added - diff]
verilog/rtl/ibex_core/ibex_multdiv_fast.v[Added - diff]
verilog/rtl/ibex_core/ibex_multdiv_slow.v[Added - diff]
verilog/rtl/ibex_core/ibex_poly16_mul.v[Added - diff]
verilog/rtl/ibex_core/ibex_prefetch_buffer.v[Added - diff]
verilog/rtl/ibex_core/ibex_register_file_ff.v[Added - diff]
verilog/rtl/ibex_core/ibex_register_file_fpga.v[Added - diff]
verilog/rtl/ibex_core/ibex_register_file_latch.v[Added - diff]
verilog/rtl/ibex_core/ibex_sm4_sbox.v[Added - diff]
verilog/rtl/ibex_core/ibex_top.v[Added - diff]
verilog/rtl/ibex_core/ibex_wb_stage.v[Added - diff]
verilog/rtl/ibex_core/ibex_zk.v[Added - diff]
verilog/rtl/ibex_core/ibexcore_netlists.vh[Added - diff]
verilog/rtl/ibex_core/prim_clock_gating.v[Added - diff]
verilog/rtl/icesoc/axi_uart.v[Added - diff]
verilog/rtl/icesoc/icesoc_netlists.vh[Added - diff]
verilog/rtl/icesoc/icesoc_top.v[Added - diff]
verilog/rtl/icesoc/inter.v[Added - diff]
verilog/rtl/icesoc/inter_read.v[Added - diff]
verilog/rtl/icesoc/peripheral.v[Added - diff]
verilog/rtl/icesoc/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/icesoc/uart.v[Added - diff]
verilog/rtl/icesoc/uart_rx.v[Added - diff]
verilog/rtl/icesoc/uart_to_mem.v[Added - diff]
verilog/rtl/icesoc/uart_tx.v[Added - diff]
verilog/rtl/models_pack.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

151 files changed

tree: 6f1d7ed6845c9f4a87b5662feccf830f697dc164

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.