commit 502bdfc268f3b56b091c1df3f1597a66bf802b1e
author Harrison Pham <harrison@harrisonpham.com> Sun Oct 24 20:19:29 2021 -0700
committer Harrison Pham <harrison@harrisonpham.com> Sun Oct 24 20:19:29 2021 -0700
tree f9dc7d8e34a9897b852eb47b78c25837cef381e9
parent 056af9a3708f139a79e6138eaada8d0971bf51b3

Passes GL sim

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 070ccac..af69d30 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -71,7 +71,8 @@
 set ::env(GLB_RT_OBS)  "li1 0 0 2920 3520"
 
 set ::env(GLB_RT_ALLOW_CONGESTION) 1
-set ::env(GLB_RT_ADJUSTMENT) 0.70
+set ::env(GLB_RT_ADJUSTMENT) 0.60
+# set ::env(ROUTING_OPT_ITERS) 128
 
 # disable pdn check nodes becuase it hangs with multiple power domains.
 # any issue with pdn connections will be flagged with LVS so it is not a critical check.

verilog/dv/randsack_netlists.v

diff --git a/verilog/dv/randsack_netlists.v b/verilog/dv/randsack_netlists.v
index 68f604b..e61d22a 100644
--- a/verilog/dv/randsack_netlists.v
+++ b/verilog/dv/randsack_netlists.v
@@ -21,6 +21,12 @@
     // Assume default net type to be wire because GL netlists don't have the wire definitions
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
+    `include "gl/digitalcore_macro.v"
+    // TODO(hdpham): Add better collapsering sim model.
+    `include "collapsering_macro.v"
+    `include "ringosc_macro.v"
+    `include "collapsering.v"
+    `include "ring_osc2x13.v"
 `else
     `include "user_project_wrapper.v"
     `include "digitalcore_macro.v"

verilog/dv/randsack_regrw_directed/Makefile

diff --git a/verilog/dv/randsack_regrw_directed/Makefile b/verilog/dv/randsack_regrw_directed/Makefile
index 07e13f7..a194e15 100644
--- a/verilog/dv/randsack_regrw_directed/Makefile
+++ b/verilog/dv/randsack_regrw_directed/Makefile
@@ -45,7 +45,7 @@
 
 PATTERN = randsack_regrw_directed
 
-all:  ${PATTERN:=.vcd}
+all:  ${PATTERN:=.fst}
 
 hex:  ${PATTERN:=.hex}
 
@@ -63,8 +63,8 @@
 	$< -o $@ 
 endif
 
-%.vcd: %.vvp
-	vvp $<
+%.fst: %.vvp
+	vvp $< -fst
 
 %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
 	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
@@ -95,6 +95,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	rm -f *.elf *.hex *.bin *.vvp *.fst *.log
 
 .PHONY: clean hex all

verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v

diff --git a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
index ca9b157..715ef5c 100644
--- a/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
+++ b/verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v
@@ -48,7 +48,7 @@
   end
 
   initial begin
-    $dumpfile("randsack_regrw_directed_tb.vcd");
+    $dumpfile("randsack_regrw_directed_tb.fst");
     $dumpvars(0, randsack_regrw_directed_tb);
 
     // Repeat cycles of 1000 clock edges as needed to complete testbench