| commit | fadaa871cde9548346a840cf8282a3ad64cb2042 | [log] [tgz] |
|---|---|---|
| author | hamzashabbir517 <shabbirhamza517@gmail.com> | Wed Jun 23 22:43:20 2021 +0500 |
| committer | hamzashabbir517 <shabbirhamza517@gmail.com> | Wed Jun 23 22:43:20 2021 +0500 |
| tree | 41965f45bfa722083f4aff8517a9b27bdfcdbe30 | |
| parent | c44fecda603012b8c2fb0878a0d27b98054c1b64 [diff] |
Update
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index b8ae917..b03a01f 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -144,8 +144,8 @@ //=========================================================================- eb1_brqrv_wrapper brqrv_top ( `ifdef USE_POWER_PINS - .VPWR ( vccd1 ), - .VGND ( vssd1 ), + .vccd1 ( vccd1 ), + .vssd1 ( vssd1 ), `endif .rst_l ( rst ), .dbg_rst_l ( ~wb_rst_i ),