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foss-eda-tools / third_party / shuttle / sky130 / mpw-004 / slot-005 / c395e2840b7cd25ef94b362a29a1b675c9a3ec35
commitc395e2840b7cd25ef94b362a29a1b675c9a3ec35[log] [tgz]
authorhamzashabbir517 <shabbirhamza517@gmail.com>Tue Jun 29 19:43:30 2021 +0100
committerhamzashabbir517 <shabbirhamza517@gmail.com>Tue Jun 29 19:43:30 2021 +0100
tree1249b922a70330bc22b4a7363b39065560e5cb55
parentc8b64810a93b45d634b272bf11d4b1100ee3ead6 [diff]
Update
9 files changed
tree: 1249b922a70330bc22b4a7363b39065560e5cb55
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

License UPRJ_CI Caravel Build

BrqRV EB1 RISC-V Core 1.0 from MERL

This repository contains the BrqRV EB1 Core design RTL. BrqRV EB1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline

Block Diagram

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The BrqRV_EB1 Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── user_project_wrapper.v       #   User Project Wrapper source file
|       ├── user_proj_example.v          #   User Project Example source file
|       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
|           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
|           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex files folder
│       ├── asm                          #   Assmebly files folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── user_project_wrapper.v       #   User Project Wrapper Netlist
│       ├── user_proj_example.v          #   User Project Example Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── user_project_wrapper.def        #    User Project Wrapper def file

├── lef                                 #    lef Directory
│   ├── user_project_wrapper.lef        #    User Project Wrapper lef file
│   ├── user_proj_example.lef           #    User Project Example lef file

├── gds                                 #    gds Directory
│   ├── user_project_wrapper.gdz.gz     #    User Project Wrapper gds
│   ├── user_proj_example.gdz.gz        #    User Project Example gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

  1. Set the GCC_PATH environment variable.
  2. Set the PDK_PATH environment variable.
  3. Copy the given program hex file into uart.hex.
  4. run the make commad for RTL simulation
  5. run the SIM=GL make command for netlist simulation

Note: Dont forget to add 00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.