Integration Completed
diff --git a/verilog/rtl/BrqRV_EB1/design/soc_files/tb_prog.v b/verilog/rtl/BrqRV_EB1/design/soc_files/tb_prog.v
index 3125b2e..0416bbf 100644
--- a/verilog/rtl/BrqRV_EB1/design/soc_files/tb_prog.v
+++ b/verilog/rtl/BrqRV_EB1/design/soc_files/tb_prog.v
@@ -44,7 +44,7 @@
end
always @(count) begin
- if(count > 50) begin
+ if(count > 1740) begin
r_Clock = ~r_Clock;
count = 0;
end
@@ -83,21 +83,21 @@
START_TX : begin
// $display("Sending Start Bit");
r_Rx_Serial <= 1'b0;
- next_state = (state_count == 32'd20) ? DATA_TX : START_TX;
- state_count = (state_count == 32'd20) ? 32'd0 : state_count;
+ next_state = (state_count == 32'd696) ? DATA_TX : START_TX;
+ state_count = (state_count == 32'd696) ? 32'd0 : state_count;
end
DATA_TX : begin
// $display("Sending Data Bit");
r_Rx_Serial <= data[tx_count];
- tx_count = (state_count == 32'd20) ? (tx_count + 32'd1) : tx_count;
+ tx_count = (state_count == 32'd696) ? (tx_count + 32'd1) : tx_count;
next_state = (tx_count == 32'd8) ? STOP_TX : DATA_TX;
- state_count = (state_count == 32'd20) ? 32'd0 : state_count;
+ state_count = (state_count == 32'd696) ? 32'd0 : state_count;
end
STOP_TX : begin
// $display("Sending End Bit");
r_Rx_Serial <= 1'b1;
- next_state = (state_count == 32'd20) ? IDLE : STOP_TX;
- state_count = (state_count == 32'd20) ? 32'd0 : state_count;
+ next_state = (state_count == 32'd696) ? IDLE : STOP_TX;
+ state_count = (state_count == 32'd696) ? 32'd0 : state_count;
tx_count = 32'd0;
valid = 1'b0;//(state_count == 32'd20) ? 1'b0 : valid;
end
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 1c4e08b..2d4dd04 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -101,6 +101,8 @@
assign io_out[35:8] = (| lsu_axi_wstrb[3:0]) ? lsu_axi_wdata[27:0] : (| lsu_axi_wstrb[7:4]) ? lsu_axi_wdata[59:32] : {28{1'b0}};
assign io_oeb[35:8] = {28{lsu_axi_wvalid}};
+ assign io_oeb[7:0] = {8{~rst}};
+ assign io_oeb[37:36] = {2{~rst}};
assign lsu_axi_bvalid = (wb_rst_i) ? 1'b0 : (lsu_axi_wvalid) ? 1'b1 : 1'b0;
// IRQ
