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foss-eda-tools / third_party / shuttle / sky130 / mpw-004 / slot-005 / 6ebbe230d00ec539403d30d68d21912eea7e98bd
commit6ebbe230d00ec539403d30d68d21912eea7e98bd[log] [tgz]
authorwajehulhasan <whassan@uit.edu>Thu Dec 30 19:36:20 2021 +0100
committerwajehulhasan <whassan@uit.edu>Thu Dec 30 19:36:20 2021 +0100
tree4a8dc5cd91c409b3963cbe4e0644dbfcde8147a0
parent53c0783e00926214d045e64b9450822b5f88892f [diff]
user wrapper hardened
4 files changed
tree: 4a8dc5cd91c409b3963cbe4e0644dbfcde8147a0
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. info.yaml
  14. LICENSE
  15. Makefile
  16. README.md
README.md

License UPRJ_CI Caravel Build

SPDX-FileCopyrightText: 2020 Efabless Corporation Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. SPDX-License-Identifier: Apache-2.0

RAM Generator from MERL

This repository contains the memories generated by our RAM Generator using sky130 sram as a base model for testing purpose.

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The Memories Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── user_project_wrapper.v       #   User Project Wrapper source file
|       ├── user_proj_example.v          #   User Project Example source file
|       ├── rams                         #   Rams folder
|           ├── ram_256x32_2r1w          #   Ram 256x32 2r1w folder
|               ├── ram_generated_256x32_2r1w.v             #   RAM 2r1w source file
|               ├── ram_generated_256x32_1rw.v              #   RAM 1rw source file
|               ├── sky130_sram_1kbyte_1rw1r_32x256_8.v     #   1KB sram
|               ├── utils.vh     				 #   utils header file

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex files folder
│       ├── asm                          #   Assmebly files folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── user_project_wrapper.v       #   User Project Wrapper Netlist
│       ├── user_proj_example.v          #   User Project Example Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── user_project_wrapper.def        #    User Project Wrapper def file

├── lef                                 #    lef Directory
│   ├── user_project_wrapper.lef        #    User Project Wrapper lef file
│   ├── user_proj_example.lef           #    User Project Example lef file

├── gds                                 #    gds Directory
│   ├── user_project_wrapper.gdz.gz     #    User Project Wrapper gds
│   ├── user_proj_example.gdz.gz        #    User Project Example gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

  1. Set the GCC_PATH environment variable.
  2. Set the PDK_PATH environment variable.
  3. run the make commad for RTL simulation
  4. run the SIM=GL make command for netlist simulation