user_proj_example verilog
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 6101828..97bef5e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,8 +39,14 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
+ //inout vdda1, // User area 1 3.3V supply
+ //inout vdda2, // User area 2 3.3V supply
+ //inout vssa1, // User area 1 analog ground
+ //inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
+ //inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
+ //inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
