Merge branch 'efabless:main' into main

README.md

diff --git a/README.md b/README.md
index 3706438..20f083b 100644
--- a/README.md
+++ b/README.md
@@ -1,11 +1,78 @@
-# Caravel User Project
-
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
-| :exclamation: Important Note            |
-|-----------------------------------------|
+SPDX-FileCopyrightText: 2020 Efabless Corporation
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+SPDX-License-Identifier: Apache-2.0
 
-## Please fill in your project documentation in this README.md file 
+# BrqRV EB1 RISC-V Core 1.0 from MERL
+
+This repository contains the BrqRV EB1 Core design RTL. BrqRV EB1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline
+
+## Block Diagram
+![](docs/BrqRV_EB1.png)
+
+## Directory Structure
+
+    ├── verlog                          #   User verilog Directory
+    │   ├── rtl                         #   RTL
+    │   ├── dv                          #   Design Verification
+    │   ├── gl                          #   Gate Level Netlis
+    
+   #  The BrqRV_EB1 Source Code is avaialable here
+    
+    ├── verlog                               #   User verilog Directory
+    │   ├── rtl                              #   RTL
+    |       ├── user_project_wrapper.v       #   User Project Wrapper source file
+    |       ├── user_proj_example.v          #   User Project Example source file
+    |       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
+    |           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
+    |           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram
+    
+    
+   # The Design Verification Testbench is available here 
+    ├── verlog                               #   User verilog Directory
+    │   ├── dv                               #   Design Verification
+    │       ├── BrqRV_EB1                    #   Design Test Directory
+    │       ├── hex                          #   Hex files folder
+    │       ├── asm                          #   Assmebly files folder
+     
+  # The synthesized netlist is present here:
+  
+    ├── verlog                               #   User verilog Directory
+    │   ├── gl                               #   Gate Level Netlis
+    │       ├── user_project_wrapper.v       #   User Project Wrapper Netlist
+    │       ├── user_proj_example.v          #   User Project Example Netlist
+    
+ # The hardened macros are placed here:
+
+    ├── def                                 #    def Directory
+    │   ├── user_project_wrapper.def        #    User Project Wrapper def file
+    
+    ├── lef                                 #    lef Directory
+    │   ├── user_project_wrapper.lef        #    User Project Wrapper lef file
+    │   ├── user_proj_example.lef           #    User Project Example lef file
+    
+    ├── gds                                 #    gds Directory
+    │   ├── user_project_wrapper.gdz.gz     #    User Project Wrapper gds
+    │   ├── user_proj_example.gdz.gz        #    User Project Example gds
 
 
-Refer to [README](docs/source/index.rst) for this sample project documentation. 
+### Testing of Design
+
+Go to verilog/dv/BrqRV_EB1/ directory
+
+1. Set the GCC_PATH environment variable.
+2. Set the PDK_PATH environment variable.
+3. Copy the given program hex file into uart.hex. 
+4. run the make commad for RTL simulation
+5. run the SIM=GL make command for netlist simulation
+
+Note: Dont forget to add 00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.

def/user_proj_example.def.gz

diff --git a/def/user_proj_example.def.gz b/def/user_proj_example.def.gz
new file mode 100644
index 0000000..ff7816f
--- /dev/null
+++ b/def/user_proj_example.def.gz
Binary files differ

docs/BrqRV_EB1.png

diff --git a/docs/BrqRV_EB1.png b/docs/BrqRV_EB1.png
new file mode 100644
index 0000000..e0cf288
--- /dev/null
+++ b/docs/BrqRV_EB1.png
Binary files differ

gds/user_proj_example.gds.gz

diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..1fcf2ff
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ

gds/user_project_wrapper.gds.gz

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..bef17f4
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

info.yaml

diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..87a7136
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+  description: "A Small SoC for Google sponsored Open MPW shuttles for SKY130."
+  foundry: "SkyWater"
+  git_url: "https://github.com/HamzaShabbir517/caravel_BrqRV_EB1.git"
+  organization: "Micro Electronics Research Lab (MERL)"
+  organization_url: "https://merledupk.org/"
+  owner: "Micro Electronics Research Lab (MERL)"
+  process: "SKY130"
+  project_name: "BrqRV EB1"
+  project_id: "00000001"
+  tags:
+    - "Open MPW"
+    - "BrqRV EB1"
+  category: "Processor"
+  top_level_netlist: "caravel/verilog/gl/caravel.v"
+  user_level_netlist: "verilog/gl/user_project_wrapper.v"
+  version: "1.00"
+  cover_image: "docs/BrqRV_EB1.png"

lef/user_proj_example.lef

diff --git a/lef/user_proj_example.lef b/lef/user_proj_example.lef
index 0297dcc..7163117 100644
--- a/lef/user_proj_example.lef
+++ b/lef/user_proj_example.lef
@@ -1,934 +1,941 @@
-VERSION 5.7 ;
-  NOWIREEXTENSIONATPIN ON ;
-  DIVIDERCHAR "/" ;
-  BUSBITCHARS "[]" ;
+##
+## LEF for PtnCells ;
+## created by Innovus v20.10-p004_1 on Sun Jul 11 21:10:59 2021
+##
+
+VERSION 5.8 ;
+
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
 MACRO user_proj_example
   CLASS BLOCK ;
-  FOREIGN user_proj_example ;
-  ORIGIN 0.000 0.000 ;
-  SIZE 900.000 BY 600.000 ;
-  PIN io_in[0]
+  SIZE 2239.740000 BY 2960.040000 ;
+  FOREIGN user_proj_example 0.000000 0.000000 ;
+  ORIGIN 0 0 ;
+  SYMMETRY X Y R90 ;
+  PIN wb_clk_i
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 3.770 596.000 4.050 600.000 ;
+        RECT 4.760000 0.000000 4.900000 0.490000 ;
     END
-  END io_in[0]
-  PIN io_in[10]
+  END wb_clk_i
+  PIN wb_rst_i
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 240.670 596.000 240.950 600.000 ;
+        RECT 4.300000 0.000000 4.440000 0.490000 ;
     END
-  END io_in[10]
-  PIN io_in[11]
+  END wb_rst_i
+  PIN wbs_stb_i
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 264.130 596.000 264.410 600.000 ;
+        RECT 472.120000 0.000000 472.260000 0.490000 ;
     END
-  END io_in[11]
-  PIN io_in[12]
+  END wbs_stb_i
+  PIN wbs_cyc_i
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 288.050 596.000 288.330 600.000 ;
+        RECT 158.860000 0.000000 159.000000 0.490000 ;
     END
-  END io_in[12]
-  PIN io_in[13]
+  END wbs_cyc_i
+  PIN wbs_we_i
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 311.510 596.000 311.790 600.000 ;
+        RECT 476.720000 0.000000 476.860000 0.490000 ;
     END
-  END io_in[13]
-  PIN io_in[14]
+  END wbs_we_i
+  PIN wbs_sel_i[3]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 335.430 596.000 335.710 600.000 ;
+        RECT 467.520000 0.000000 467.660000 0.490000 ;
     END
-  END io_in[14]
-  PIN io_in[15]
+  END wbs_sel_i[3]
+  PIN wbs_sel_i[2]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 358.890 596.000 359.170 600.000 ;
+        RECT 462.920000 0.000000 463.060000 0.490000 ;
     END
-  END io_in[15]
-  PIN io_in[16]
+  END wbs_sel_i[2]
+  PIN wbs_sel_i[1]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 382.810 596.000 383.090 600.000 ;
+        RECT 458.320000 0.000000 458.460000 0.490000 ;
     END
-  END io_in[16]
-  PIN io_in[17]
+  END wbs_sel_i[1]
+  PIN wbs_sel_i[0]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 406.270 596.000 406.550 600.000 ;
+        RECT 454.180000 0.000000 454.320000 0.490000 ;
     END
-  END io_in[17]
-  PIN io_in[18]
+  END wbs_sel_i[0]
+  PIN wbs_dat_i[31]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 430.190 596.000 430.470 600.000 ;
+        RECT 304.220000 0.000000 304.360000 0.490000 ;
     END
-  END io_in[18]
-  PIN io_in[19]
+  END wbs_dat_i[31]
+  PIN wbs_dat_i[30]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 453.650 596.000 453.930 600.000 ;
+        RECT 299.620000 0.000000 299.760000 0.490000 ;
     END
-  END io_in[19]
-  PIN io_in[1]
+  END wbs_dat_i[30]
+  PIN wbs_dat_i[29]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 27.230 596.000 27.510 600.000 ;
+        RECT 295.020000 0.000000 295.160000 0.490000 ;
     END
-  END io_in[1]
-  PIN io_in[20]
+  END wbs_dat_i[29]
+  PIN wbs_dat_i[28]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 477.570 596.000 477.850 600.000 ;
+        RECT 290.420000 0.000000 290.560000 0.490000 ;
     END
-  END io_in[20]
-  PIN io_in[21]
+  END wbs_dat_i[28]
+  PIN wbs_dat_i[27]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 501.030 596.000 501.310 600.000 ;
+        RECT 285.820000 0.000000 285.960000 0.490000 ;
     END
-  END io_in[21]
-  PIN io_in[22]
+  END wbs_dat_i[27]
+  PIN wbs_dat_i[26]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 524.950 596.000 525.230 600.000 ;
+        RECT 281.220000 0.000000 281.360000 0.490000 ;
     END
-  END io_in[22]
-  PIN io_in[23]
+  END wbs_dat_i[26]
+  PIN wbs_dat_i[25]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 548.410 596.000 548.690 600.000 ;
+        RECT 276.620000 0.000000 276.760000 0.490000 ;
     END
-  END io_in[23]
-  PIN io_in[24]
+  END wbs_dat_i[25]
+  PIN wbs_dat_i[24]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 572.330 596.000 572.610 600.000 ;
+        RECT 272.480000 0.000000 272.620000 0.490000 ;
     END
-  END io_in[24]
-  PIN io_in[25]
+  END wbs_dat_i[24]
+  PIN wbs_dat_i[23]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 595.790 596.000 596.070 600.000 ;
+        RECT 267.880000 0.000000 268.020000 0.490000 ;
     END
-  END io_in[25]
-  PIN io_in[26]
+  END wbs_dat_i[23]
+  PIN wbs_dat_i[22]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 619.710 596.000 619.990 600.000 ;
+        RECT 263.280000 0.000000 263.420000 0.490000 ;
     END
-  END io_in[26]
-  PIN io_in[27]
+  END wbs_dat_i[22]
+  PIN wbs_dat_i[21]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 643.170 596.000 643.450 600.000 ;
+        RECT 258.680000 0.000000 258.820000 0.490000 ;
     END
-  END io_in[27]
-  PIN io_in[28]
+  END wbs_dat_i[21]
+  PIN wbs_dat_i[20]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 667.090 596.000 667.370 600.000 ;
+        RECT 254.080000 0.000000 254.220000 0.490000 ;
     END
-  END io_in[28]
-  PIN io_in[29]
+  END wbs_dat_i[20]
+  PIN wbs_dat_i[19]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 690.550 596.000 690.830 600.000 ;
+        RECT 249.480000 0.000000 249.620000 0.490000 ;
     END
-  END io_in[29]
-  PIN io_in[2]
+  END wbs_dat_i[19]
+  PIN wbs_dat_i[18]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 51.150 596.000 51.430 600.000 ;
+        RECT 244.880000 0.000000 245.020000 0.490000 ;
     END
-  END io_in[2]
-  PIN io_in[30]
+  END wbs_dat_i[18]
+  PIN wbs_dat_i[17]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 714.470 596.000 714.750 600.000 ;
+        RECT 240.280000 0.000000 240.420000 0.490000 ;
     END
-  END io_in[30]
-  PIN io_in[31]
+  END wbs_dat_i[17]
+  PIN wbs_dat_i[16]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 737.930 596.000 738.210 600.000 ;
+        RECT 236.140000 0.000000 236.280000 0.490000 ;
     END
-  END io_in[31]
-  PIN io_in[32]
+  END wbs_dat_i[16]
+  PIN wbs_dat_i[15]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 761.850 596.000 762.130 600.000 ;
+        RECT 231.540000 0.000000 231.680000 0.490000 ;
     END
-  END io_in[32]
-  PIN io_in[33]
+  END wbs_dat_i[15]
+  PIN wbs_dat_i[14]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 785.310 596.000 785.590 600.000 ;
+        RECT 226.940000 0.000000 227.080000 0.490000 ;
     END
-  END io_in[33]
-  PIN io_in[34]
+  END wbs_dat_i[14]
+  PIN wbs_dat_i[13]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 809.230 596.000 809.510 600.000 ;
+        RECT 222.340000 0.000000 222.480000 0.490000 ;
     END
-  END io_in[34]
-  PIN io_in[35]
+  END wbs_dat_i[13]
+  PIN wbs_dat_i[12]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 832.690 596.000 832.970 600.000 ;
+        RECT 217.740000 0.000000 217.880000 0.490000 ;
     END
-  END io_in[35]
-  PIN io_in[36]
+  END wbs_dat_i[12]
+  PIN wbs_dat_i[11]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 856.610 596.000 856.890 600.000 ;
+        RECT 213.140000 0.000000 213.280000 0.490000 ;
     END
-  END io_in[36]
-  PIN io_in[37]
+  END wbs_dat_i[11]
+  PIN wbs_dat_i[10]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 880.070 596.000 880.350 600.000 ;
+        RECT 208.540000 0.000000 208.680000 0.490000 ;
     END
-  END io_in[37]
-  PIN io_in[3]
+  END wbs_dat_i[10]
+  PIN wbs_dat_i[9]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 74.610 596.000 74.890 600.000 ;
+        RECT 203.940000 0.000000 204.080000 0.490000 ;
     END
-  END io_in[3]
-  PIN io_in[4]
+  END wbs_dat_i[9]
+  PIN wbs_dat_i[8]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 98.530 596.000 98.810 600.000 ;
+        RECT 199.800000 0.000000 199.940000 0.490000 ;
     END
-  END io_in[4]
-  PIN io_in[5]
+  END wbs_dat_i[8]
+  PIN wbs_dat_i[7]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 121.990 596.000 122.270 600.000 ;
+        RECT 195.200000 0.000000 195.340000 0.490000 ;
     END
-  END io_in[5]
-  PIN io_in[6]
+  END wbs_dat_i[7]
+  PIN wbs_dat_i[6]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 145.910 596.000 146.190 600.000 ;
+        RECT 190.600000 0.000000 190.740000 0.490000 ;
     END
-  END io_in[6]
-  PIN io_in[7]
+  END wbs_dat_i[6]
+  PIN wbs_dat_i[5]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 169.370 596.000 169.650 600.000 ;
+        RECT 186.000000 0.000000 186.140000 0.490000 ;
     END
-  END io_in[7]
-  PIN io_in[8]
+  END wbs_dat_i[5]
+  PIN wbs_dat_i[4]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 193.290 596.000 193.570 600.000 ;
+        RECT 181.400000 0.000000 181.540000 0.490000 ;
     END
-  END io_in[8]
-  PIN io_in[9]
+  END wbs_dat_i[4]
+  PIN wbs_dat_i[3]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 216.750 596.000 217.030 600.000 ;
+        RECT 176.800000 0.000000 176.940000 0.490000 ;
     END
-  END io_in[9]
-  PIN io_oeb[0]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_i[3]
+  PIN wbs_dat_i[2]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 11.590 596.000 11.870 600.000 ;
+        RECT 172.200000 0.000000 172.340000 0.490000 ;
     END
-  END io_oeb[0]
-  PIN io_oeb[10]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_i[2]
+  PIN wbs_dat_i[1]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 248.490 596.000 248.770 600.000 ;
+        RECT 167.600000 0.000000 167.740000 0.490000 ;
     END
-  END io_oeb[10]
-  PIN io_oeb[11]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_i[1]
+  PIN wbs_dat_i[0]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 271.950 596.000 272.230 600.000 ;
+        RECT 163.460000 0.000000 163.600000 0.490000 ;
     END
-  END io_oeb[11]
-  PIN io_oeb[12]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_i[0]
+  PIN wbs_adr_i[31]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 295.870 596.000 296.150 600.000 ;
+        RECT 154.260000 0.000000 154.400000 0.490000 ;
     END
-  END io_oeb[12]
-  PIN io_oeb[13]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[31]
+  PIN wbs_adr_i[30]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 319.330 596.000 319.610 600.000 ;
+        RECT 149.660000 0.000000 149.800000 0.490000 ;
     END
-  END io_oeb[13]
-  PIN io_oeb[14]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[30]
+  PIN wbs_adr_i[29]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 343.250 596.000 343.530 600.000 ;
+        RECT 145.060000 0.000000 145.200000 0.490000 ;
     END
-  END io_oeb[14]
-  PIN io_oeb[15]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[29]
+  PIN wbs_adr_i[28]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 366.710 596.000 366.990 600.000 ;
+        RECT 140.460000 0.000000 140.600000 0.490000 ;
     END
-  END io_oeb[15]
-  PIN io_oeb[16]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[28]
+  PIN wbs_adr_i[27]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 390.630 596.000 390.910 600.000 ;
+        RECT 135.860000 0.000000 136.000000 0.490000 ;
     END
-  END io_oeb[16]
-  PIN io_oeb[17]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[27]
+  PIN wbs_adr_i[26]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 414.090 596.000 414.370 600.000 ;
+        RECT 131.260000 0.000000 131.400000 0.490000 ;
     END
-  END io_oeb[17]
-  PIN io_oeb[18]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[26]
+  PIN wbs_adr_i[25]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 438.010 596.000 438.290 600.000 ;
+        RECT 127.120000 0.000000 127.260000 0.490000 ;
     END
-  END io_oeb[18]
-  PIN io_oeb[19]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[25]
+  PIN wbs_adr_i[24]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 461.470 596.000 461.750 600.000 ;
+        RECT 122.520000 0.000000 122.660000 0.490000 ;
     END
-  END io_oeb[19]
-  PIN io_oeb[1]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[24]
+  PIN wbs_adr_i[23]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 35.050 596.000 35.330 600.000 ;
+        RECT 117.920000 0.000000 118.060000 0.490000 ;
     END
-  END io_oeb[1]
-  PIN io_oeb[20]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[23]
+  PIN wbs_adr_i[22]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 485.390 596.000 485.670 600.000 ;
+        RECT 113.320000 0.000000 113.460000 0.490000 ;
     END
-  END io_oeb[20]
-  PIN io_oeb[21]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[22]
+  PIN wbs_adr_i[21]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 508.850 596.000 509.130 600.000 ;
+        RECT 108.720000 0.000000 108.860000 0.490000 ;
     END
-  END io_oeb[21]
-  PIN io_oeb[22]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[21]
+  PIN wbs_adr_i[20]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 532.770 596.000 533.050 600.000 ;
+        RECT 104.120000 0.000000 104.260000 0.490000 ;
     END
-  END io_oeb[22]
-  PIN io_oeb[23]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[20]
+  PIN wbs_adr_i[19]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 556.230 596.000 556.510 600.000 ;
+        RECT 99.520000 0.000000 99.660000 0.490000 ;
     END
-  END io_oeb[23]
-  PIN io_oeb[24]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[19]
+  PIN wbs_adr_i[18]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 580.150 596.000 580.430 600.000 ;
+        RECT 94.920000 0.000000 95.060000 0.490000 ;
     END
-  END io_oeb[24]
-  PIN io_oeb[25]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[18]
+  PIN wbs_adr_i[17]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 603.610 596.000 603.890 600.000 ;
+        RECT 90.780000 0.000000 90.920000 0.490000 ;
     END
-  END io_oeb[25]
-  PIN io_oeb[26]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[17]
+  PIN wbs_adr_i[16]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 627.530 596.000 627.810 600.000 ;
+        RECT 86.180000 0.000000 86.320000 0.490000 ;
     END
-  END io_oeb[26]
-  PIN io_oeb[27]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[16]
+  PIN wbs_adr_i[15]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 650.990 596.000 651.270 600.000 ;
+        RECT 81.580000 0.000000 81.720000 0.490000 ;
     END
-  END io_oeb[27]
-  PIN io_oeb[28]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[15]
+  PIN wbs_adr_i[14]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 674.910 596.000 675.190 600.000 ;
+        RECT 76.980000 0.000000 77.120000 0.490000 ;
     END
-  END io_oeb[28]
-  PIN io_oeb[29]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[14]
+  PIN wbs_adr_i[13]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 698.370 596.000 698.650 600.000 ;
+        RECT 72.380000 0.000000 72.520000 0.490000 ;
     END
-  END io_oeb[29]
-  PIN io_oeb[2]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[13]
+  PIN wbs_adr_i[12]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 58.970 596.000 59.250 600.000 ;
+        RECT 67.780000 0.000000 67.920000 0.490000 ;
     END
-  END io_oeb[2]
-  PIN io_oeb[30]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[12]
+  PIN wbs_adr_i[11]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 722.290 596.000 722.570 600.000 ;
+        RECT 63.180000 0.000000 63.320000 0.490000 ;
     END
-  END io_oeb[30]
-  PIN io_oeb[31]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[11]
+  PIN wbs_adr_i[10]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 745.750 596.000 746.030 600.000 ;
+        RECT 58.580000 0.000000 58.720000 0.490000 ;
     END
-  END io_oeb[31]
-  PIN io_oeb[32]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[10]
+  PIN wbs_adr_i[9]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 769.670 596.000 769.950 600.000 ;
+        RECT 54.440000 0.000000 54.580000 0.490000 ;
     END
-  END io_oeb[32]
-  PIN io_oeb[33]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[9]
+  PIN wbs_adr_i[8]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 793.130 596.000 793.410 600.000 ;
+        RECT 49.840000 0.000000 49.980000 0.490000 ;
     END
-  END io_oeb[33]
-  PIN io_oeb[34]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[8]
+  PIN wbs_adr_i[7]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 817.050 596.000 817.330 600.000 ;
+        RECT 45.240000 0.000000 45.380000 0.490000 ;
     END
-  END io_oeb[34]
-  PIN io_oeb[35]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[7]
+  PIN wbs_adr_i[6]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 840.510 596.000 840.790 600.000 ;
+        RECT 40.640000 0.000000 40.780000 0.490000 ;
     END
-  END io_oeb[35]
-  PIN io_oeb[36]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[6]
+  PIN wbs_adr_i[5]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 864.430 596.000 864.710 600.000 ;
+        RECT 36.040000 0.000000 36.180000 0.490000 ;
     END
-  END io_oeb[36]
-  PIN io_oeb[37]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[5]
+  PIN wbs_adr_i[4]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 887.890 596.000 888.170 600.000 ;
+        RECT 31.440000 0.000000 31.580000 0.490000 ;
     END
-  END io_oeb[37]
-  PIN io_oeb[3]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[4]
+  PIN wbs_adr_i[3]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 82.430 596.000 82.710 600.000 ;
+        RECT 26.840000 0.000000 26.980000 0.490000 ;
     END
-  END io_oeb[3]
-  PIN io_oeb[4]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[3]
+  PIN wbs_adr_i[2]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 106.350 596.000 106.630 600.000 ;
+        RECT 22.240000 0.000000 22.380000 0.490000 ;
     END
-  END io_oeb[4]
-  PIN io_oeb[5]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[2]
+  PIN wbs_adr_i[1]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 129.810 596.000 130.090 600.000 ;
+        RECT 18.100000 0.000000 18.240000 0.490000 ;
     END
-  END io_oeb[5]
-  PIN io_oeb[6]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[1]
+  PIN wbs_adr_i[0]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 153.730 596.000 154.010 600.000 ;
+        RECT 13.500000 0.000000 13.640000 0.490000 ;
     END
-  END io_oeb[6]
-  PIN io_oeb[7]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_adr_i[0]
+  PIN wbs_ack_o
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 177.190 596.000 177.470 600.000 ;
+        RECT 8.900000 0.000000 9.040000 0.490000 ;
     END
-  END io_oeb[7]
-  PIN io_oeb[8]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_ack_o
+  PIN wbs_dat_o[31]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 201.110 596.000 201.390 600.000 ;
+        RECT 449.580000 0.000000 449.720000 0.490000 ;
     END
-  END io_oeb[8]
-  PIN io_oeb[9]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[31]
+  PIN wbs_dat_o[30]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 224.570 596.000 224.850 600.000 ;
+        RECT 444.980000 0.000000 445.120000 0.490000 ;
     END
-  END io_oeb[9]
-  PIN io_out[0]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[30]
+  PIN wbs_dat_o[29]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 19.410 596.000 19.690 600.000 ;
+        RECT 440.380000 0.000000 440.520000 0.490000 ;
     END
-  END io_out[0]
-  PIN io_out[10]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[29]
+  PIN wbs_dat_o[28]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 256.310 596.000 256.590 600.000 ;
+        RECT 435.780000 0.000000 435.920000 0.490000 ;
     END
-  END io_out[10]
-  PIN io_out[11]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[28]
+  PIN wbs_dat_o[27]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 279.770 596.000 280.050 600.000 ;
+        RECT 431.180000 0.000000 431.320000 0.490000 ;
     END
-  END io_out[11]
-  PIN io_out[12]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[27]
+  PIN wbs_dat_o[26]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 303.690 596.000 303.970 600.000 ;
+        RECT 426.580000 0.000000 426.720000 0.490000 ;
     END
-  END io_out[12]
-  PIN io_out[13]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[26]
+  PIN wbs_dat_o[25]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 327.150 596.000 327.430 600.000 ;
+        RECT 421.980000 0.000000 422.120000 0.490000 ;
     END
-  END io_out[13]
-  PIN io_out[14]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[25]
+  PIN wbs_dat_o[24]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 351.070 596.000 351.350 600.000 ;
+        RECT 417.840000 0.000000 417.980000 0.490000 ;
     END
-  END io_out[14]
-  PIN io_out[15]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[24]
+  PIN wbs_dat_o[23]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 374.530 596.000 374.810 600.000 ;
+        RECT 413.240000 0.000000 413.380000 0.490000 ;
     END
-  END io_out[15]
-  PIN io_out[16]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[23]
+  PIN wbs_dat_o[22]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 398.450 596.000 398.730 600.000 ;
+        RECT 408.640000 0.000000 408.780000 0.490000 ;
     END
-  END io_out[16]
-  PIN io_out[17]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[22]
+  PIN wbs_dat_o[21]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 421.910 596.000 422.190 600.000 ;
+        RECT 404.040000 0.000000 404.180000 0.490000 ;
     END
-  END io_out[17]
-  PIN io_out[18]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[21]
+  PIN wbs_dat_o[20]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 445.830 596.000 446.110 600.000 ;
+        RECT 399.440000 0.000000 399.580000 0.490000 ;
     END
-  END io_out[18]
-  PIN io_out[19]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[20]
+  PIN wbs_dat_o[19]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 469.290 596.000 469.570 600.000 ;
+        RECT 394.840000 0.000000 394.980000 0.490000 ;
     END
-  END io_out[19]
-  PIN io_out[1]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[19]
+  PIN wbs_dat_o[18]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 42.870 596.000 43.150 600.000 ;
+        RECT 390.240000 0.000000 390.380000 0.490000 ;
     END
-  END io_out[1]
-  PIN io_out[20]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[18]
+  PIN wbs_dat_o[17]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 493.210 596.000 493.490 600.000 ;
+        RECT 385.640000 0.000000 385.780000 0.490000 ;
     END
-  END io_out[20]
-  PIN io_out[21]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[17]
+  PIN wbs_dat_o[16]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 516.670 596.000 516.950 600.000 ;
+        RECT 381.500000 0.000000 381.640000 0.490000 ;
     END
-  END io_out[21]
-  PIN io_out[22]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[16]
+  PIN wbs_dat_o[15]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 540.590 596.000 540.870 600.000 ;
+        RECT 376.900000 0.000000 377.040000 0.490000 ;
     END
-  END io_out[22]
-  PIN io_out[23]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[15]
+  PIN wbs_dat_o[14]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 564.050 596.000 564.330 600.000 ;
+        RECT 372.300000 0.000000 372.440000 0.490000 ;
     END
-  END io_out[23]
-  PIN io_out[24]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[14]
+  PIN wbs_dat_o[13]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 587.970 596.000 588.250 600.000 ;
+        RECT 367.700000 0.000000 367.840000 0.490000 ;
     END
-  END io_out[24]
-  PIN io_out[25]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[13]
+  PIN wbs_dat_o[12]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 611.430 596.000 611.710 600.000 ;
+        RECT 363.100000 0.000000 363.240000 0.490000 ;
     END
-  END io_out[25]
-  PIN io_out[26]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[12]
+  PIN wbs_dat_o[11]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 635.350 596.000 635.630 600.000 ;
+        RECT 358.500000 0.000000 358.640000 0.490000 ;
     END
-  END io_out[26]
-  PIN io_out[27]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[11]
+  PIN wbs_dat_o[10]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 658.810 596.000 659.090 600.000 ;
+        RECT 353.900000 0.000000 354.040000 0.490000 ;
     END
-  END io_out[27]
-  PIN io_out[28]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[10]
+  PIN wbs_dat_o[9]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 682.730 596.000 683.010 600.000 ;
+        RECT 349.300000 0.000000 349.440000 0.490000 ;
     END
-  END io_out[28]
-  PIN io_out[29]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[9]
+  PIN wbs_dat_o[8]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 706.190 596.000 706.470 600.000 ;
+        RECT 345.160000 0.000000 345.300000 0.490000 ;
     END
-  END io_out[29]
-  PIN io_out[2]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[8]
+  PIN wbs_dat_o[7]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 66.790 596.000 67.070 600.000 ;
+        RECT 340.560000 0.000000 340.700000 0.490000 ;
     END
-  END io_out[2]
-  PIN io_out[30]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[7]
+  PIN wbs_dat_o[6]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 730.110 596.000 730.390 600.000 ;
+        RECT 335.960000 0.000000 336.100000 0.490000 ;
     END
-  END io_out[30]
-  PIN io_out[31]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[6]
+  PIN wbs_dat_o[5]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 753.570 596.000 753.850 600.000 ;
+        RECT 331.360000 0.000000 331.500000 0.490000 ;
     END
-  END io_out[31]
-  PIN io_out[32]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[5]
+  PIN wbs_dat_o[4]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 777.490 596.000 777.770 600.000 ;
+        RECT 326.760000 0.000000 326.900000 0.490000 ;
     END
-  END io_out[32]
-  PIN io_out[33]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[4]
+  PIN wbs_dat_o[3]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 800.950 596.000 801.230 600.000 ;
+        RECT 322.160000 0.000000 322.300000 0.490000 ;
     END
-  END io_out[33]
-  PIN io_out[34]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[3]
+  PIN wbs_dat_o[2]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 824.870 596.000 825.150 600.000 ;
+        RECT 317.560000 0.000000 317.700000 0.490000 ;
     END
-  END io_out[34]
-  PIN io_out[35]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[2]
+  PIN wbs_dat_o[1]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 848.330 596.000 848.610 600.000 ;
+        RECT 312.960000 0.000000 313.100000 0.490000 ;
     END
-  END io_out[35]
-  PIN io_out[36]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[1]
+  PIN wbs_dat_o[0]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 872.250 596.000 872.530 600.000 ;
+        RECT 308.820000 0.000000 308.960000 0.490000 ;
     END
-  END io_out[36]
-  PIN io_out[37]
-    DIRECTION OUTPUT TRISTATE ;
+  END wbs_dat_o[0]
+  PIN la_data_in[127]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 895.710 596.000 895.990 600.000 ;
+        RECT 1058.160000 0.000000 1058.300000 0.490000 ;
     END
-  END io_out[37]
-  PIN io_out[3]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[127]
+  PIN la_data_in[126]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 90.250 596.000 90.530 600.000 ;
+        RECT 1053.560000 0.000000 1053.700000 0.490000 ;
     END
-  END io_out[3]
-  PIN io_out[4]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[126]
+  PIN la_data_in[125]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 114.170 596.000 114.450 600.000 ;
+        RECT 1048.960000 0.000000 1049.100000 0.490000 ;
     END
-  END io_out[4]
-  PIN io_out[5]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[125]
+  PIN la_data_in[124]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 137.630 596.000 137.910 600.000 ;
+        RECT 1044.820000 0.000000 1044.960000 0.490000 ;
     END
-  END io_out[5]
-  PIN io_out[6]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[124]
+  PIN la_data_in[123]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 161.550 596.000 161.830 600.000 ;
+        RECT 1040.220000 0.000000 1040.360000 0.490000 ;
     END
-  END io_out[6]
-  PIN io_out[7]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[123]
+  PIN la_data_in[122]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 185.010 596.000 185.290 600.000 ;
+        RECT 1035.620000 0.000000 1035.760000 0.490000 ;
     END
-  END io_out[7]
-  PIN io_out[8]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[122]
+  PIN la_data_in[121]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 208.930 596.000 209.210 600.000 ;
+        RECT 1031.020000 0.000000 1031.160000 0.490000 ;
     END
-  END io_out[8]
-  PIN io_out[9]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[121]
+  PIN la_data_in[120]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 232.390 596.000 232.670 600.000 ;
+        RECT 1026.420000 0.000000 1026.560000 0.490000 ;
     END
-  END io_out[9]
-  PIN irq[0]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[120]
+  PIN la_data_in[119]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 895.250 0.000 895.530 4.000 ;
     END
-  END irq[0]
-  PIN irq[1]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_in[119]
+  PIN la_data_in[118]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
@@ -942,79 +949,79 @@
       LAYER met2 ;
         RECT 898.930 0.000 899.210 4.000 ;
     END
-  END irq[2]
-  PIN la_data_in[0]
+  END la_data_in[118]
+  PIN la_data_in[117]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 193.750 0.000 194.030 4.000 ;
     END
-  END la_data_in[0]
-  PIN la_data_in[100]
+  END la_data_in[117]
+  PIN la_data_in[116]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 741.610 0.000 741.890 4.000 ;
     END
-  END la_data_in[100]
-  PIN la_data_in[101]
+  END la_data_in[116]
+  PIN la_data_in[115]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 747.130 0.000 747.410 4.000 ;
     END
-  END la_data_in[101]
-  PIN la_data_in[102]
+  END la_data_in[115]
+  PIN la_data_in[114]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 752.650 0.000 752.930 4.000 ;
     END
-  END la_data_in[102]
-  PIN la_data_in[103]
+  END la_data_in[114]
+  PIN la_data_in[113]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 758.170 0.000 758.450 4.000 ;
     END
-  END la_data_in[103]
-  PIN la_data_in[104]
+  END la_data_in[113]
+  PIN la_data_in[112]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 763.690 0.000 763.970 4.000 ;
     END
-  END la_data_in[104]
-  PIN la_data_in[105]
+  END la_data_in[112]
+  PIN la_data_in[111]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 769.210 0.000 769.490 4.000 ;
     END
-  END la_data_in[105]
-  PIN la_data_in[106]
+  END la_data_in[111]
+  PIN la_data_in[110]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 774.730 0.000 775.010 4.000 ;
     END
-  END la_data_in[106]
-  PIN la_data_in[107]
+  END la_data_in[110]
+  PIN la_data_in[109]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 780.250 0.000 780.530 4.000 ;
     END
-  END la_data_in[107]
+  END la_data_in[109]
   PIN la_data_in[108]
     DIRECTION INPUT ;
     USE SIGNAL ;
@@ -1023,1440 +1030,1440 @@
         RECT 785.310 0.000 785.590 4.000 ;
     END
   END la_data_in[108]
-  PIN la_data_in[109]
+  PIN la_data_in[107]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 790.830 0.000 791.110 4.000 ;
     END
-  END la_data_in[109]
-  PIN la_data_in[10]
+  END la_data_in[107]
+  PIN la_data_in[106]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 248.490 0.000 248.770 4.000 ;
     END
-  END la_data_in[10]
-  PIN la_data_in[110]
+  END la_data_in[106]
+  PIN la_data_in[105]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 796.350 0.000 796.630 4.000 ;
     END
-  END la_data_in[110]
-  PIN la_data_in[111]
+  END la_data_in[105]
+  PIN la_data_in[104]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 801.870 0.000 802.150 4.000 ;
     END
-  END la_data_in[111]
-  PIN la_data_in[112]
+  END la_data_in[104]
+  PIN la_data_in[103]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 807.390 0.000 807.670 4.000 ;
     END
-  END la_data_in[112]
-  PIN la_data_in[113]
+  END la_data_in[103]
+  PIN la_data_in[102]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 812.910 0.000 813.190 4.000 ;
     END
-  END la_data_in[113]
-  PIN la_data_in[114]
+  END la_data_in[102]
+  PIN la_data_in[101]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 818.430 0.000 818.710 4.000 ;
     END
-  END la_data_in[114]
-  PIN la_data_in[115]
+  END la_data_in[101]
+  PIN la_data_in[100]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 823.950 0.000 824.230 4.000 ;
     END
-  END la_data_in[115]
-  PIN la_data_in[116]
+  END la_data_in[100]
+  PIN la_data_in[99]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 829.470 0.000 829.750 4.000 ;
     END
-  END la_data_in[116]
-  PIN la_data_in[117]
+  END la_data_in[99]
+  PIN la_data_in[98]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 834.990 0.000 835.270 4.000 ;
     END
-  END la_data_in[117]
-  PIN la_data_in[118]
+  END la_data_in[98]
+  PIN la_data_in[97]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 840.510 0.000 840.790 4.000 ;
     END
-  END la_data_in[118]
-  PIN la_data_in[119]
+  END la_data_in[97]
+  PIN la_data_in[96]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 845.570 0.000 845.850 4.000 ;
     END
-  END la_data_in[119]
-  PIN la_data_in[11]
+  END la_data_in[96]
+  PIN la_data_in[95]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 254.010 0.000 254.290 4.000 ;
     END
-  END la_data_in[11]
-  PIN la_data_in[120]
+  END la_data_in[95]
+  PIN la_data_in[94]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 851.090 0.000 851.370 4.000 ;
     END
-  END la_data_in[120]
-  PIN la_data_in[121]
+  END la_data_in[94]
+  PIN la_data_in[93]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 856.610 0.000 856.890 4.000 ;
     END
-  END la_data_in[121]
-  PIN la_data_in[122]
+  END la_data_in[93]
+  PIN la_data_in[92]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 862.130 0.000 862.410 4.000 ;
     END
-  END la_data_in[122]
-  PIN la_data_in[123]
+  END la_data_in[92]
+  PIN la_data_in[91]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 867.650 0.000 867.930 4.000 ;
     END
-  END la_data_in[123]
-  PIN la_data_in[124]
+  END la_data_in[91]
+  PIN la_data_in[90]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 873.170 0.000 873.450 4.000 ;
     END
-  END la_data_in[124]
-  PIN la_data_in[125]
+  END la_data_in[90]
+  PIN la_data_in[89]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 878.690 0.000 878.970 4.000 ;
     END
-  END la_data_in[125]
-  PIN la_data_in[126]
+  END la_data_in[89]
+  PIN la_data_in[88]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 884.210 0.000 884.490 4.000 ;
     END
-  END la_data_in[126]
-  PIN la_data_in[127]
+  END la_data_in[88]
+  PIN la_data_in[87]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 889.730 0.000 890.010 4.000 ;
     END
-  END la_data_in[127]
-  PIN la_data_in[12]
+  END la_data_in[87]
+  PIN la_data_in[86]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 259.530 0.000 259.810 4.000 ;
     END
-  END la_data_in[12]
-  PIN la_data_in[13]
+  END la_data_in[86]
+  PIN la_data_in[85]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 265.050 0.000 265.330 4.000 ;
     END
-  END la_data_in[13]
-  PIN la_data_in[14]
+  END la_data_in[85]
+  PIN la_data_in[84]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 270.570 0.000 270.850 4.000 ;
     END
-  END la_data_in[14]
-  PIN la_data_in[15]
+  END la_data_in[84]
+  PIN la_data_in[83]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 276.090 0.000 276.370 4.000 ;
     END
-  END la_data_in[15]
-  PIN la_data_in[16]
+  END la_data_in[83]
+  PIN la_data_in[82]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 281.610 0.000 281.890 4.000 ;
     END
-  END la_data_in[16]
-  PIN la_data_in[17]
+  END la_data_in[82]
+  PIN la_data_in[81]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 287.130 0.000 287.410 4.000 ;
     END
-  END la_data_in[17]
-  PIN la_data_in[18]
+  END la_data_in[81]
+  PIN la_data_in[80]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 292.650 0.000 292.930 4.000 ;
     END
-  END la_data_in[18]
-  PIN la_data_in[19]
+  END la_data_in[80]
+  PIN la_data_in[79]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 298.170 0.000 298.450 4.000 ;
     END
-  END la_data_in[19]
-  PIN la_data_in[1]
+  END la_data_in[79]
+  PIN la_data_in[78]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 199.270 0.000 199.550 4.000 ;
     END
-  END la_data_in[1]
-  PIN la_data_in[20]
+  END la_data_in[78]
+  PIN la_data_in[77]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 303.230 0.000 303.510 4.000 ;
     END
-  END la_data_in[20]
-  PIN la_data_in[21]
+  END la_data_in[77]
+  PIN la_data_in[76]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 308.750 0.000 309.030 4.000 ;
     END
-  END la_data_in[21]
-  PIN la_data_in[22]
+  END la_data_in[76]
+  PIN la_data_in[75]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 314.270 0.000 314.550 4.000 ;
     END
-  END la_data_in[22]
-  PIN la_data_in[23]
+  END la_data_in[75]
+  PIN la_data_in[74]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 319.790 0.000 320.070 4.000 ;
     END
-  END la_data_in[23]
-  PIN la_data_in[24]
+  END la_data_in[74]
+  PIN la_data_in[73]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 325.310 0.000 325.590 4.000 ;
     END
-  END la_data_in[24]
-  PIN la_data_in[25]
+  END la_data_in[73]
+  PIN la_data_in[72]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 330.830 0.000 331.110 4.000 ;
     END
-  END la_data_in[25]
-  PIN la_data_in[26]
+  END la_data_in[72]
+  PIN la_data_in[71]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 336.350 0.000 336.630 4.000 ;
     END
-  END la_data_in[26]
-  PIN la_data_in[27]
+  END la_data_in[71]
+  PIN la_data_in[70]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 341.870 0.000 342.150 4.000 ;
     END
-  END la_data_in[27]
-  PIN la_data_in[28]
+  END la_data_in[70]
+  PIN la_data_in[69]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 347.390 0.000 347.670 4.000 ;
     END
-  END la_data_in[28]
-  PIN la_data_in[29]
+  END la_data_in[69]
+  PIN la_data_in[68]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 352.910 0.000 353.190 4.000 ;
     END
-  END la_data_in[29]
-  PIN la_data_in[2]
+  END la_data_in[68]
+  PIN la_data_in[67]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 204.790 0.000 205.070 4.000 ;
     END
-  END la_data_in[2]
-  PIN la_data_in[30]
+  END la_data_in[67]
+  PIN la_data_in[66]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 358.430 0.000 358.710 4.000 ;
     END
-  END la_data_in[30]
-  PIN la_data_in[31]
+  END la_data_in[66]
+  PIN la_data_in[65]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 363.490 0.000 363.770 4.000 ;
     END
-  END la_data_in[31]
-  PIN la_data_in[32]
+  END la_data_in[65]
+  PIN la_data_in[64]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 369.010 0.000 369.290 4.000 ;
     END
-  END la_data_in[32]
-  PIN la_data_in[33]
+  END la_data_in[64]
+  PIN la_data_in[63]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 374.530 0.000 374.810 4.000 ;
     END
-  END la_data_in[33]
-  PIN la_data_in[34]
+  END la_data_in[63]
+  PIN la_data_in[62]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 380.050 0.000 380.330 4.000 ;
     END
-  END la_data_in[34]
-  PIN la_data_in[35]
+  END la_data_in[62]
+  PIN la_data_in[61]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 385.570 0.000 385.850 4.000 ;
     END
-  END la_data_in[35]
-  PIN la_data_in[36]
+  END la_data_in[61]
+  PIN la_data_in[60]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 391.090 0.000 391.370 4.000 ;
     END
-  END la_data_in[36]
-  PIN la_data_in[37]
+  END la_data_in[60]
+  PIN la_data_in[59]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 396.610 0.000 396.890 4.000 ;
     END
-  END la_data_in[37]
-  PIN la_data_in[38]
+  END la_data_in[59]
+  PIN la_data_in[58]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 402.130 0.000 402.410 4.000 ;
     END
-  END la_data_in[38]
-  PIN la_data_in[39]
+  END la_data_in[58]
+  PIN la_data_in[57]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 407.650 0.000 407.930 4.000 ;
     END
-  END la_data_in[39]
-  PIN la_data_in[3]
+  END la_data_in[57]
+  PIN la_data_in[56]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 210.310 0.000 210.590 4.000 ;
     END
-  END la_data_in[3]
-  PIN la_data_in[40]
+  END la_data_in[56]
+  PIN la_data_in[55]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 413.170 0.000 413.450 4.000 ;
     END
-  END la_data_in[40]
-  PIN la_data_in[41]
+  END la_data_in[55]
+  PIN la_data_in[54]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 418.690 0.000 418.970 4.000 ;
     END
-  END la_data_in[41]
-  PIN la_data_in[42]
+  END la_data_in[54]
+  PIN la_data_in[53]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 423.750 0.000 424.030 4.000 ;
     END
-  END la_data_in[42]
-  PIN la_data_in[43]
+  END la_data_in[53]
+  PIN la_data_in[52]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 429.270 0.000 429.550 4.000 ;
     END
-  END la_data_in[43]
-  PIN la_data_in[44]
+  END la_data_in[52]
+  PIN la_data_in[51]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 434.790 0.000 435.070 4.000 ;
     END
-  END la_data_in[44]
-  PIN la_data_in[45]
+  END la_data_in[51]
+  PIN la_data_in[50]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 440.310 0.000 440.590 4.000 ;
     END
-  END la_data_in[45]
-  PIN la_data_in[46]
+  END la_data_in[50]
+  PIN la_data_in[49]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 445.830 0.000 446.110 4.000 ;
     END
-  END la_data_in[46]
-  PIN la_data_in[47]
+  END la_data_in[49]
+  PIN la_data_in[48]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 451.350 0.000 451.630 4.000 ;
     END
-  END la_data_in[47]
-  PIN la_data_in[48]
+  END la_data_in[48]
+  PIN la_data_in[47]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 456.870 0.000 457.150 4.000 ;
     END
-  END la_data_in[48]
-  PIN la_data_in[49]
+  END la_data_in[47]
+  PIN la_data_in[46]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 462.390 0.000 462.670 4.000 ;
     END
-  END la_data_in[49]
-  PIN la_data_in[4]
+  END la_data_in[46]
+  PIN la_data_in[45]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 215.830 0.000 216.110 4.000 ;
     END
-  END la_data_in[4]
-  PIN la_data_in[50]
+  END la_data_in[45]
+  PIN la_data_in[44]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 467.910 0.000 468.190 4.000 ;
     END
-  END la_data_in[50]
-  PIN la_data_in[51]
+  END la_data_in[44]
+  PIN la_data_in[43]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 473.430 0.000 473.710 4.000 ;
     END
-  END la_data_in[51]
-  PIN la_data_in[52]
+  END la_data_in[43]
+  PIN la_data_in[42]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 478.950 0.000 479.230 4.000 ;
     END
-  END la_data_in[52]
-  PIN la_data_in[53]
+  END la_data_in[42]
+  PIN la_data_in[41]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 484.010 0.000 484.290 4.000 ;
     END
-  END la_data_in[53]
-  PIN la_data_in[54]
+  END la_data_in[41]
+  PIN la_data_in[40]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 489.530 0.000 489.810 4.000 ;
     END
-  END la_data_in[54]
-  PIN la_data_in[55]
+  END la_data_in[40]
+  PIN la_data_in[39]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 495.050 0.000 495.330 4.000 ;
     END
-  END la_data_in[55]
-  PIN la_data_in[56]
+  END la_data_in[39]
+  PIN la_data_in[38]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 500.570 0.000 500.850 4.000 ;
     END
-  END la_data_in[56]
-  PIN la_data_in[57]
+  END la_data_in[38]
+  PIN la_data_in[37]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 506.090 0.000 506.370 4.000 ;
     END
-  END la_data_in[57]
-  PIN la_data_in[58]
+  END la_data_in[37]
+  PIN la_data_in[36]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 511.610 0.000 511.890 4.000 ;
     END
-  END la_data_in[58]
-  PIN la_data_in[59]
+  END la_data_in[36]
+  PIN la_data_in[35]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 517.130 0.000 517.410 4.000 ;
     END
-  END la_data_in[59]
-  PIN la_data_in[5]
+  END la_data_in[35]
+  PIN la_data_in[34]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 221.350 0.000 221.630 4.000 ;
     END
-  END la_data_in[5]
-  PIN la_data_in[60]
+  END la_data_in[34]
+  PIN la_data_in[33]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 522.650 0.000 522.930 4.000 ;
     END
-  END la_data_in[60]
-  PIN la_data_in[61]
+  END la_data_in[33]
+  PIN la_data_in[32]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 528.170 0.000 528.450 4.000 ;
     END
-  END la_data_in[61]
-  PIN la_data_in[62]
+  END la_data_in[32]
+  PIN la_data_in[31]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 533.690 0.000 533.970 4.000 ;
     END
-  END la_data_in[62]
-  PIN la_data_in[63]
+  END la_data_in[31]
+  PIN la_data_in[30]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 539.210 0.000 539.490 4.000 ;
     END
-  END la_data_in[63]
-  PIN la_data_in[64]
+  END la_data_in[30]
+  PIN la_data_in[29]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 544.270 0.000 544.550 4.000 ;
     END
-  END la_data_in[64]
-  PIN la_data_in[65]
+  END la_data_in[29]
+  PIN la_data_in[28]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 549.790 0.000 550.070 4.000 ;
     END
-  END la_data_in[65]
-  PIN la_data_in[66]
+  END la_data_in[28]
+  PIN la_data_in[27]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 555.310 0.000 555.590 4.000 ;
     END
-  END la_data_in[66]
-  PIN la_data_in[67]
+  END la_data_in[27]
+  PIN la_data_in[26]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 560.830 0.000 561.110 4.000 ;
     END
-  END la_data_in[67]
-  PIN la_data_in[68]
+  END la_data_in[26]
+  PIN la_data_in[25]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 566.350 0.000 566.630 4.000 ;
     END
-  END la_data_in[68]
-  PIN la_data_in[69]
+  END la_data_in[25]
+  PIN la_data_in[24]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 571.870 0.000 572.150 4.000 ;
     END
-  END la_data_in[69]
-  PIN la_data_in[6]
+  END la_data_in[24]
+  PIN la_data_in[23]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 226.870 0.000 227.150 4.000 ;
     END
-  END la_data_in[6]
-  PIN la_data_in[70]
+  END la_data_in[23]
+  PIN la_data_in[22]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 577.390 0.000 577.670 4.000 ;
     END
-  END la_data_in[70]
-  PIN la_data_in[71]
+  END la_data_in[22]
+  PIN la_data_in[21]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 582.910 0.000 583.190 4.000 ;
     END
-  END la_data_in[71]
-  PIN la_data_in[72]
+  END la_data_in[21]
+  PIN la_data_in[20]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 588.430 0.000 588.710 4.000 ;
     END
-  END la_data_in[72]
-  PIN la_data_in[73]
+  END la_data_in[20]
+  PIN la_data_in[19]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 593.950 0.000 594.230 4.000 ;
     END
-  END la_data_in[73]
-  PIN la_data_in[74]
+  END la_data_in[19]
+  PIN la_data_in[18]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 599.470 0.000 599.750 4.000 ;
     END
-  END la_data_in[74]
-  PIN la_data_in[75]
+  END la_data_in[18]
+  PIN la_data_in[17]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 604.530 0.000 604.810 4.000 ;
     END
-  END la_data_in[75]
-  PIN la_data_in[76]
+  END la_data_in[17]
+  PIN la_data_in[16]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 610.050 0.000 610.330 4.000 ;
     END
-  END la_data_in[76]
-  PIN la_data_in[77]
+  END la_data_in[16]
+  PIN la_data_in[15]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 615.570 0.000 615.850 4.000 ;
     END
-  END la_data_in[77]
-  PIN la_data_in[78]
+  END la_data_in[15]
+  PIN la_data_in[14]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 621.090 0.000 621.370 4.000 ;
     END
-  END la_data_in[78]
-  PIN la_data_in[79]
+  END la_data_in[14]
+  PIN la_data_in[13]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 626.610 0.000 626.890 4.000 ;
     END
-  END la_data_in[79]
-  PIN la_data_in[7]
+  END la_data_in[13]
+  PIN la_data_in[12]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 232.390 0.000 232.670 4.000 ;
     END
-  END la_data_in[7]
-  PIN la_data_in[80]
+  END la_data_in[12]
+  PIN la_data_in[11]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 632.130 0.000 632.410 4.000 ;
     END
-  END la_data_in[80]
-  PIN la_data_in[81]
+  END la_data_in[11]
+  PIN la_data_in[10]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 637.650 0.000 637.930 4.000 ;
     END
-  END la_data_in[81]
-  PIN la_data_in[82]
+  END la_data_in[10]
+  PIN la_data_in[9]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 643.170 0.000 643.450 4.000 ;
     END
-  END la_data_in[82]
-  PIN la_data_in[83]
+  END la_data_in[9]
+  PIN la_data_in[8]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 648.690 0.000 648.970 4.000 ;
     END
-  END la_data_in[83]
-  PIN la_data_in[84]
+  END la_data_in[8]
+  PIN la_data_in[7]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 654.210 0.000 654.490 4.000 ;
     END
-  END la_data_in[84]
-  PIN la_data_in[85]
+  END la_data_in[7]
+  PIN la_data_in[6]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 659.730 0.000 660.010 4.000 ;
     END
-  END la_data_in[85]
-  PIN la_data_in[86]
+  END la_data_in[6]
+  PIN la_data_in[5]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 664.790 0.000 665.070 4.000 ;
     END
-  END la_data_in[86]
-  PIN la_data_in[87]
+  END la_data_in[5]
+  PIN la_data_in[4]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 670.310 0.000 670.590 4.000 ;
     END
-  END la_data_in[87]
-  PIN la_data_in[88]
+  END la_data_in[4]
+  PIN la_data_in[3]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 675.830 0.000 676.110 4.000 ;
     END
-  END la_data_in[88]
-  PIN la_data_in[89]
+  END la_data_in[3]
+  PIN la_data_in[2]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 681.350 0.000 681.630 4.000 ;
     END
-  END la_data_in[89]
-  PIN la_data_in[8]
+  END la_data_in[2]
+  PIN la_data_in[1]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 237.910 0.000 238.190 4.000 ;
     END
-  END la_data_in[8]
-  PIN la_data_in[90]
+  END la_data_in[1]
+  PIN la_data_in[0]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 686.870 0.000 687.150 4.000 ;
     END
-  END la_data_in[90]
-  PIN la_data_in[91]
-    DIRECTION INPUT ;
+  END la_data_in[0]
+  PIN la_data_out[127]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 692.390 0.000 692.670 4.000 ;
     END
-  END la_data_in[91]
-  PIN la_data_in[92]
-    DIRECTION INPUT ;
+  END la_data_out[127]
+  PIN la_data_out[126]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 697.910 0.000 698.190 4.000 ;
     END
-  END la_data_in[92]
-  PIN la_data_in[93]
-    DIRECTION INPUT ;
+  END la_data_out[126]
+  PIN la_data_out[125]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 703.430 0.000 703.710 4.000 ;
     END
-  END la_data_in[93]
-  PIN la_data_in[94]
-    DIRECTION INPUT ;
+  END la_data_out[125]
+  PIN la_data_out[124]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 708.950 0.000 709.230 4.000 ;
     END
-  END la_data_in[94]
-  PIN la_data_in[95]
-    DIRECTION INPUT ;
+  END la_data_out[124]
+  PIN la_data_out[123]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 714.470 0.000 714.750 4.000 ;
     END
-  END la_data_in[95]
-  PIN la_data_in[96]
-    DIRECTION INPUT ;
+  END la_data_out[123]
+  PIN la_data_out[122]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 719.990 0.000 720.270 4.000 ;
     END
-  END la_data_in[96]
-  PIN la_data_in[97]
-    DIRECTION INPUT ;
+  END la_data_out[122]
+  PIN la_data_out[121]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 725.050 0.000 725.330 4.000 ;
     END
-  END la_data_in[97]
-  PIN la_data_in[98]
-    DIRECTION INPUT ;
+  END la_data_out[121]
+  PIN la_data_out[120]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 730.570 0.000 730.850 4.000 ;
     END
-  END la_data_in[98]
-  PIN la_data_in[99]
-    DIRECTION INPUT ;
+  END la_data_out[120]
+  PIN la_data_out[119]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 736.090 0.000 736.370 4.000 ;
     END
-  END la_data_in[99]
-  PIN la_data_in[9]
-    DIRECTION INPUT ;
+  END la_data_out[119]
+  PIN la_data_out[118]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 242.970 0.000 243.250 4.000 ;
     END
-  END la_data_in[9]
-  PIN la_data_out[0]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[118]
+  PIN la_data_out[117]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 195.590 0.000 195.870 4.000 ;
     END
-  END la_data_out[0]
-  PIN la_data_out[100]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[117]
+  PIN la_data_out[116]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 743.450 0.000 743.730 4.000 ;
     END
-  END la_data_out[100]
-  PIN la_data_out[101]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[116]
+  PIN la_data_out[115]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 748.970 0.000 749.250 4.000 ;
     END
-  END la_data_out[101]
-  PIN la_data_out[102]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[115]
+  PIN la_data_out[114]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 754.490 0.000 754.770 4.000 ;
     END
-  END la_data_out[102]
-  PIN la_data_out[103]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[114]
+  PIN la_data_out[113]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 760.010 0.000 760.290 4.000 ;
     END
-  END la_data_out[103]
-  PIN la_data_out[104]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[113]
+  PIN la_data_out[112]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 765.530 0.000 765.810 4.000 ;
     END
-  END la_data_out[104]
-  PIN la_data_out[105]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[112]
+  PIN la_data_out[111]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 771.050 0.000 771.330 4.000 ;
     END
-  END la_data_out[105]
-  PIN la_data_out[106]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[111]
+  PIN la_data_out[110]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 776.570 0.000 776.850 4.000 ;
     END
-  END la_data_out[106]
-  PIN la_data_out[107]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[110]
+  PIN la_data_out[109]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 781.630 0.000 781.910 4.000 ;
     END
-  END la_data_out[107]
+  END la_data_out[109]
   PIN la_data_out[108]
-    DIRECTION OUTPUT TRISTATE ;
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 787.150 0.000 787.430 4.000 ;
     END
   END la_data_out[108]
-  PIN la_data_out[109]
-    DIRECTION OUTPUT TRISTATE ;
+  PIN la_data_out[107]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 792.670 0.000 792.950 4.000 ;
     END
-  END la_data_out[109]
-  PIN la_data_out[10]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[107]
+  PIN la_data_out[106]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 250.330 0.000 250.610 4.000 ;
     END
-  END la_data_out[10]
-  PIN la_data_out[110]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[106]
+  PIN la_data_out[105]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 798.190 0.000 798.470 4.000 ;
     END
-  END la_data_out[110]
-  PIN la_data_out[111]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[105]
+  PIN la_data_out[104]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 803.710 0.000 803.990 4.000 ;
     END
-  END la_data_out[111]
-  PIN la_data_out[112]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[104]
+  PIN la_data_out[103]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 809.230 0.000 809.510 4.000 ;
     END
-  END la_data_out[112]
-  PIN la_data_out[113]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[103]
+  PIN la_data_out[102]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 814.750 0.000 815.030 4.000 ;
     END
-  END la_data_out[113]
-  PIN la_data_out[114]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[102]
+  PIN la_data_out[101]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 820.270 0.000 820.550 4.000 ;
     END
-  END la_data_out[114]
-  PIN la_data_out[115]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[101]
+  PIN la_data_out[100]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 825.790 0.000 826.070 4.000 ;
     END
-  END la_data_out[115]
-  PIN la_data_out[116]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[100]
+  PIN la_data_out[99]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 831.310 0.000 831.590 4.000 ;
     END
-  END la_data_out[116]
-  PIN la_data_out[117]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[99]
+  PIN la_data_out[98]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 836.830 0.000 837.110 4.000 ;
     END
-  END la_data_out[117]
-  PIN la_data_out[118]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[98]
+  PIN la_data_out[97]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 841.890 0.000 842.170 4.000 ;
     END
-  END la_data_out[118]
-  PIN la_data_out[119]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[97]
+  PIN la_data_out[96]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 847.410 0.000 847.690 4.000 ;
     END
-  END la_data_out[119]
-  PIN la_data_out[11]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[96]
+  PIN la_data_out[95]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 255.850 0.000 256.130 4.000 ;
     END
-  END la_data_out[11]
-  PIN la_data_out[120]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[95]
+  PIN la_data_out[94]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 852.930 0.000 853.210 4.000 ;
     END
-  END la_data_out[120]
-  PIN la_data_out[121]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[94]
+  PIN la_data_out[93]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 858.450 0.000 858.730 4.000 ;
     END
-  END la_data_out[121]
-  PIN la_data_out[122]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[93]
+  PIN la_data_out[92]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 863.970 0.000 864.250 4.000 ;
     END
-  END la_data_out[122]
-  PIN la_data_out[123]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[92]
+  PIN la_data_out[91]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 869.490 0.000 869.770 4.000 ;
     END
-  END la_data_out[123]
-  PIN la_data_out[124]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[91]
+  PIN la_data_out[90]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 875.010 0.000 875.290 4.000 ;
     END
-  END la_data_out[124]
-  PIN la_data_out[125]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[90]
+  PIN la_data_out[89]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 880.530 0.000 880.810 4.000 ;
     END
-  END la_data_out[125]
-  PIN la_data_out[126]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[89]
+  PIN la_data_out[88]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 886.050 0.000 886.330 4.000 ;
     END
-  END la_data_out[126]
-  PIN la_data_out[127]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[88]
+  PIN la_data_out[87]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 891.570 0.000 891.850 4.000 ;
     END
-  END la_data_out[127]
-  PIN la_data_out[12]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[87]
+  PIN la_data_out[86]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 261.370 0.000 261.650 4.000 ;
     END
-  END la_data_out[12]
-  PIN la_data_out[13]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[86]
+  PIN la_data_out[85]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 266.890 0.000 267.170 4.000 ;
     END
-  END la_data_out[13]
-  PIN la_data_out[14]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[85]
+  PIN la_data_out[84]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 272.410 0.000 272.690 4.000 ;
     END
-  END la_data_out[14]
-  PIN la_data_out[15]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[84]
+  PIN la_data_out[83]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 277.930 0.000 278.210 4.000 ;
     END
-  END la_data_out[15]
-  PIN la_data_out[16]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[83]
+  PIN la_data_out[82]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 283.450 0.000 283.730 4.000 ;
     END
-  END la_data_out[16]
-  PIN la_data_out[17]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[82]
+  PIN la_data_out[81]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 288.970 0.000 289.250 4.000 ;
     END
-  END la_data_out[17]
-  PIN la_data_out[18]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[81]
+  PIN la_data_out[80]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 294.490 0.000 294.770 4.000 ;
     END
-  END la_data_out[18]
-  PIN la_data_out[19]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[80]
+  PIN la_data_out[79]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 300.010 0.000 300.290 4.000 ;
     END
-  END la_data_out[19]
-  PIN la_data_out[1]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[79]
+  PIN la_data_out[78]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 201.110 0.000 201.390 4.000 ;
     END
-  END la_data_out[1]
-  PIN la_data_out[20]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[78]
+  PIN la_data_out[77]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 305.070 0.000 305.350 4.000 ;
     END
-  END la_data_out[20]
-  PIN la_data_out[21]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[77]
+  PIN la_data_out[76]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 310.590 0.000 310.870 4.000 ;
     END
-  END la_data_out[21]
-  PIN la_data_out[22]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[76]
+  PIN la_data_out[75]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 316.110 0.000 316.390 4.000 ;
     END
-  END la_data_out[22]
-  PIN la_data_out[23]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[75]
+  PIN la_data_out[74]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 321.630 0.000 321.910 4.000 ;
     END
-  END la_data_out[23]
-  PIN la_data_out[24]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[74]
+  PIN la_data_out[73]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 327.150 0.000 327.430 4.000 ;
     END
-  END la_data_out[24]
-  PIN la_data_out[25]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[73]
+  PIN la_data_out[72]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 332.670 0.000 332.950 4.000 ;
     END
-  END la_data_out[25]
-  PIN la_data_out[26]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[72]
+  PIN la_data_out[71]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 338.190 0.000 338.470 4.000 ;
     END
-  END la_data_out[26]
-  PIN la_data_out[27]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[71]
+  PIN la_data_out[70]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 343.710 0.000 343.990 4.000 ;
     END
-  END la_data_out[27]
-  PIN la_data_out[28]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[70]
+  PIN la_data_out[69]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 349.230 0.000 349.510 4.000 ;
     END
-  END la_data_out[28]
-  PIN la_data_out[29]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[69]
+  PIN la_data_out[68]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 354.750 0.000 355.030 4.000 ;
     END
-  END la_data_out[29]
-  PIN la_data_out[2]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[68]
+  PIN la_data_out[67]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 206.630 0.000 206.910 4.000 ;
     END
-  END la_data_out[2]
-  PIN la_data_out[30]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[67]
+  PIN la_data_out[66]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 360.270 0.000 360.550 4.000 ;
     END
-  END la_data_out[30]
-  PIN la_data_out[31]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[66]
+  PIN la_data_out[65]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 365.330 0.000 365.610 4.000 ;
     END
-  END la_data_out[31]
-  PIN la_data_out[32]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[65]
+  PIN la_data_out[64]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 370.850 0.000 371.130 4.000 ;
     END
-  END la_data_out[32]
-  PIN la_data_out[33]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[64]
+  PIN la_data_out[63]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 376.370 0.000 376.650 4.000 ;
     END
-  END la_data_out[33]
-  PIN la_data_out[34]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[63]
+  PIN la_data_out[62]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 381.890 0.000 382.170 4.000 ;
     END
-  END la_data_out[34]
-  PIN la_data_out[35]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[62]
+  PIN la_data_out[61]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 387.410 0.000 387.690 4.000 ;
     END
-  END la_data_out[35]
-  PIN la_data_out[36]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[61]
+  PIN la_data_out[60]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 392.930 0.000 393.210 4.000 ;
     END
-  END la_data_out[36]
-  PIN la_data_out[37]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[60]
+  PIN la_data_out[59]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 398.450 0.000 398.730 4.000 ;
     END
-  END la_data_out[37]
-  PIN la_data_out[38]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[59]
+  PIN la_data_out[58]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 403.970 0.000 404.250 4.000 ;
     END
-  END la_data_out[38]
-  PIN la_data_out[39]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[58]
+  PIN la_data_out[57]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 409.490 0.000 409.770 4.000 ;
     END
-  END la_data_out[39]
-  PIN la_data_out[3]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[57]
+  PIN la_data_out[56]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
@@ -2478,489 +2485,489 @@
       LAYER met2 ;
         RECT 420.530 0.000 420.810 4.000 ;
     END
-  END la_data_out[41]
-  PIN la_data_out[42]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[55]
+  PIN la_data_out[54]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 425.590 0.000 425.870 4.000 ;
     END
-  END la_data_out[42]
-  PIN la_data_out[43]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[54]
+  PIN la_data_out[53]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 431.110 0.000 431.390 4.000 ;
     END
-  END la_data_out[43]
-  PIN la_data_out[44]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[53]
+  PIN la_data_out[52]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 436.630 0.000 436.910 4.000 ;
     END
-  END la_data_out[44]
-  PIN la_data_out[45]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[52]
+  PIN la_data_out[51]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 442.150 0.000 442.430 4.000 ;
     END
-  END la_data_out[45]
-  PIN la_data_out[46]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[51]
+  PIN la_data_out[50]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 447.670 0.000 447.950 4.000 ;
     END
-  END la_data_out[46]
-  PIN la_data_out[47]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[50]
+  PIN la_data_out[49]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 453.190 0.000 453.470 4.000 ;
     END
-  END la_data_out[47]
+  END la_data_out[49]
   PIN la_data_out[48]
-    DIRECTION OUTPUT TRISTATE ;
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 458.710 0.000 458.990 4.000 ;
     END
   END la_data_out[48]
-  PIN la_data_out[49]
-    DIRECTION OUTPUT TRISTATE ;
+  PIN la_data_out[47]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 464.230 0.000 464.510 4.000 ;
     END
-  END la_data_out[49]
-  PIN la_data_out[4]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[47]
+  PIN la_data_out[46]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 217.670 0.000 217.950 4.000 ;
     END
-  END la_data_out[4]
-  PIN la_data_out[50]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[46]
+  PIN la_data_out[45]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 469.750 0.000 470.030 4.000 ;
     END
-  END la_data_out[50]
-  PIN la_data_out[51]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[45]
+  PIN la_data_out[44]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 475.270 0.000 475.550 4.000 ;
     END
-  END la_data_out[51]
-  PIN la_data_out[52]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[44]
+  PIN la_data_out[43]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 480.330 0.000 480.610 4.000 ;
     END
-  END la_data_out[52]
-  PIN la_data_out[53]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[43]
+  PIN la_data_out[42]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 485.850 0.000 486.130 4.000 ;
     END
-  END la_data_out[53]
-  PIN la_data_out[54]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[42]
+  PIN la_data_out[41]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 491.370 0.000 491.650 4.000 ;
     END
-  END la_data_out[54]
-  PIN la_data_out[55]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[41]
+  PIN la_data_out[40]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 496.890 0.000 497.170 4.000 ;
     END
-  END la_data_out[55]
-  PIN la_data_out[56]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[40]
+  PIN la_data_out[39]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 502.410 0.000 502.690 4.000 ;
     END
-  END la_data_out[56]
-  PIN la_data_out[57]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[39]
+  PIN la_data_out[38]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 507.930 0.000 508.210 4.000 ;
     END
-  END la_data_out[57]
-  PIN la_data_out[58]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[38]
+  PIN la_data_out[37]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 513.450 0.000 513.730 4.000 ;
     END
-  END la_data_out[58]
-  PIN la_data_out[59]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[37]
+  PIN la_data_out[36]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 518.970 0.000 519.250 4.000 ;
     END
-  END la_data_out[59]
-  PIN la_data_out[5]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[36]
+  PIN la_data_out[35]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 223.190 0.000 223.470 4.000 ;
     END
-  END la_data_out[5]
-  PIN la_data_out[60]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[35]
+  PIN la_data_out[34]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 524.490 0.000 524.770 4.000 ;
     END
-  END la_data_out[60]
-  PIN la_data_out[61]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[34]
+  PIN la_data_out[33]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 530.010 0.000 530.290 4.000 ;
     END
-  END la_data_out[61]
-  PIN la_data_out[62]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[33]
+  PIN la_data_out[32]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 535.530 0.000 535.810 4.000 ;
     END
-  END la_data_out[62]
-  PIN la_data_out[63]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[32]
+  PIN la_data_out[31]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 540.590 0.000 540.870 4.000 ;
     END
-  END la_data_out[63]
-  PIN la_data_out[64]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[31]
+  PIN la_data_out[30]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 546.110 0.000 546.390 4.000 ;
     END
-  END la_data_out[64]
-  PIN la_data_out[65]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[30]
+  PIN la_data_out[29]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 551.630 0.000 551.910 4.000 ;
     END
-  END la_data_out[65]
-  PIN la_data_out[66]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[29]
+  PIN la_data_out[28]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 557.150 0.000 557.430 4.000 ;
     END
-  END la_data_out[66]
-  PIN la_data_out[67]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[28]
+  PIN la_data_out[27]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 562.670 0.000 562.950 4.000 ;
     END
-  END la_data_out[67]
-  PIN la_data_out[68]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[27]
+  PIN la_data_out[26]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 568.190 0.000 568.470 4.000 ;
     END
-  END la_data_out[68]
-  PIN la_data_out[69]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[26]
+  PIN la_data_out[25]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 573.710 0.000 573.990 4.000 ;
     END
-  END la_data_out[69]
-  PIN la_data_out[6]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[25]
+  PIN la_data_out[24]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 228.710 0.000 228.990 4.000 ;
     END
-  END la_data_out[6]
-  PIN la_data_out[70]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[24]
+  PIN la_data_out[23]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 579.230 0.000 579.510 4.000 ;
     END
-  END la_data_out[70]
-  PIN la_data_out[71]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[23]
+  PIN la_data_out[22]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 584.750 0.000 585.030 4.000 ;
     END
-  END la_data_out[71]
-  PIN la_data_out[72]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[22]
+  PIN la_data_out[21]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 590.270 0.000 590.550 4.000 ;
     END
-  END la_data_out[72]
-  PIN la_data_out[73]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[21]
+  PIN la_data_out[20]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 595.790 0.000 596.070 4.000 ;
     END
-  END la_data_out[73]
-  PIN la_data_out[74]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[20]
+  PIN la_data_out[19]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 600.850 0.000 601.130 4.000 ;
     END
-  END la_data_out[74]
-  PIN la_data_out[75]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[19]
+  PIN la_data_out[18]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 606.370 0.000 606.650 4.000 ;
     END
-  END la_data_out[75]
-  PIN la_data_out[76]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[18]
+  PIN la_data_out[17]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 611.890 0.000 612.170 4.000 ;
     END
-  END la_data_out[76]
-  PIN la_data_out[77]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[17]
+  PIN la_data_out[16]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 617.410 0.000 617.690 4.000 ;
     END
-  END la_data_out[77]
-  PIN la_data_out[78]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[16]
+  PIN la_data_out[15]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 622.930 0.000 623.210 4.000 ;
     END
-  END la_data_out[78]
-  PIN la_data_out[79]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[15]
+  PIN la_data_out[14]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 628.450 0.000 628.730 4.000 ;
     END
-  END la_data_out[79]
-  PIN la_data_out[7]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[14]
+  PIN la_data_out[13]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 234.230 0.000 234.510 4.000 ;
     END
-  END la_data_out[7]
-  PIN la_data_out[80]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[13]
+  PIN la_data_out[12]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 633.970 0.000 634.250 4.000 ;
     END
-  END la_data_out[80]
-  PIN la_data_out[81]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[12]
+  PIN la_data_out[11]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 639.490 0.000 639.770 4.000 ;
     END
-  END la_data_out[81]
-  PIN la_data_out[82]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[11]
+  PIN la_data_out[10]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 645.010 0.000 645.290 4.000 ;
     END
-  END la_data_out[82]
-  PIN la_data_out[83]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[10]
+  PIN la_data_out[9]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 650.530 0.000 650.810 4.000 ;
     END
-  END la_data_out[83]
-  PIN la_data_out[84]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[9]
+  PIN la_data_out[8]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 656.050 0.000 656.330 4.000 ;
     END
-  END la_data_out[84]
-  PIN la_data_out[85]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[8]
+  PIN la_data_out[7]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 661.110 0.000 661.390 4.000 ;
     END
-  END la_data_out[85]
-  PIN la_data_out[86]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[7]
+  PIN la_data_out[6]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 666.630 0.000 666.910 4.000 ;
     END
-  END la_data_out[86]
-  PIN la_data_out[87]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[6]
+  PIN la_data_out[5]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 672.150 0.000 672.430 4.000 ;
     END
-  END la_data_out[87]
-  PIN la_data_out[88]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[5]
+  PIN la_data_out[4]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 677.670 0.000 677.950 4.000 ;
     END
-  END la_data_out[88]
-  PIN la_data_out[89]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[4]
+  PIN la_data_out[3]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 683.190 0.000 683.470 4.000 ;
     END
-  END la_data_out[89]
-  PIN la_data_out[8]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[3]
+  PIN la_data_out[2]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 239.750 0.000 240.030 4.000 ;
     END
-  END la_data_out[8]
-  PIN la_data_out[90]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[2]
+  PIN la_data_out[1]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 688.710 0.000 688.990 4.000 ;
     END
-  END la_data_out[90]
-  PIN la_data_out[91]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[1]
+  PIN la_data_out[0]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 694.230 0.000 694.510 4.000 ;
     END
-  END la_data_out[91]
-  PIN la_data_out[92]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_data_out[0]
+  PIN la_oenb[127]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 699.750 0.000 700.030 4.000 ;
     END
-  END la_data_out[92]
-  PIN la_data_out[93]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[127]
+  PIN la_oenb[126]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 705.270 0.000 705.550 4.000 ;
     END
-  END la_data_out[93]
-  PIN la_data_out[94]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[126]
+  PIN la_oenb[125]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 710.790 0.000 711.070 4.000 ;
     END
-  END la_data_out[94]
-  PIN la_data_out[95]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[125]
+  PIN la_oenb[124]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 716.310 0.000 716.590 4.000 ;
     END
-  END la_data_out[95]
-  PIN la_data_out[96]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[124]
+  PIN la_oenb[123]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 721.370 0.000 721.650 4.000 ;
     END
-  END la_data_out[96]
-  PIN la_data_out[97]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[123]
+  PIN la_oenb[122]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
@@ -2982,95 +2989,95 @@
       LAYER met2 ;
         RECT 737.930 0.000 738.210 4.000 ;
     END
-  END la_data_out[99]
-  PIN la_data_out[9]
-    DIRECTION OUTPUT TRISTATE ;
+  END la_oenb[121]
+  PIN la_oenb[120]
+    DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 244.810 0.000 245.090 4.000 ;
     END
-  END la_data_out[9]
-  PIN la_oenb[0]
+  END la_oenb[120]
+  PIN la_oenb[119]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 197.430 0.000 197.710 4.000 ;
     END
-  END la_oenb[0]
-  PIN la_oenb[100]
+  END la_oenb[119]
+  PIN la_oenb[118]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 745.290 0.000 745.570 4.000 ;
     END
-  END la_oenb[100]
-  PIN la_oenb[101]
+  END la_oenb[118]
+  PIN la_oenb[117]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 750.810 0.000 751.090 4.000 ;
     END
-  END la_oenb[101]
-  PIN la_oenb[102]
+  END la_oenb[117]
+  PIN la_oenb[116]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 756.330 0.000 756.610 4.000 ;
     END
-  END la_oenb[102]
-  PIN la_oenb[103]
+  END la_oenb[116]
+  PIN la_oenb[115]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 761.850 0.000 762.130 4.000 ;
     END
-  END la_oenb[103]
-  PIN la_oenb[104]
+  END la_oenb[115]
+  PIN la_oenb[114]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 767.370 0.000 767.650 4.000 ;
     END
-  END la_oenb[104]
-  PIN la_oenb[105]
+  END la_oenb[114]
+  PIN la_oenb[113]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 772.890 0.000 773.170 4.000 ;
     END
-  END la_oenb[105]
-  PIN la_oenb[106]
+  END la_oenb[113]
+  PIN la_oenb[112]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 778.410 0.000 778.690 4.000 ;
     END
-  END la_oenb[106]
-  PIN la_oenb[107]
+  END la_oenb[112]
+  PIN la_oenb[111]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 783.470 0.000 783.750 4.000 ;
     END
-  END la_oenb[107]
-  PIN la_oenb[108]
+  END la_oenb[111]
+  PIN la_oenb[110]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 788.990 0.000 789.270 4.000 ;
     END
-  END la_oenb[108]
+  END la_oenb[110]
   PIN la_oenb[109]
     DIRECTION INPUT ;
     USE SIGNAL ;
@@ -3079,935 +3086,935 @@
         RECT 794.510 0.000 794.790 4.000 ;
     END
   END la_oenb[109]
-  PIN la_oenb[10]
+  PIN la_oenb[108]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 252.170 0.000 252.450 4.000 ;
     END
-  END la_oenb[10]
-  PIN la_oenb[110]
+  END la_oenb[108]
+  PIN la_oenb[107]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 800.030 0.000 800.310 4.000 ;
     END
-  END la_oenb[110]
-  PIN la_oenb[111]
+  END la_oenb[107]
+  PIN la_oenb[106]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 805.550 0.000 805.830 4.000 ;
     END
-  END la_oenb[111]
-  PIN la_oenb[112]
+  END la_oenb[106]
+  PIN la_oenb[105]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 811.070 0.000 811.350 4.000 ;
     END
-  END la_oenb[112]
-  PIN la_oenb[113]
+  END la_oenb[105]
+  PIN la_oenb[104]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 816.590 0.000 816.870 4.000 ;
     END
-  END la_oenb[113]
-  PIN la_oenb[114]
+  END la_oenb[104]
+  PIN la_oenb[103]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 822.110 0.000 822.390 4.000 ;
     END
-  END la_oenb[114]
-  PIN la_oenb[115]
+  END la_oenb[103]
+  PIN la_oenb[102]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 827.630 0.000 827.910 4.000 ;
     END
-  END la_oenb[115]
-  PIN la_oenb[116]
+  END la_oenb[102]
+  PIN la_oenb[101]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 833.150 0.000 833.430 4.000 ;
     END
-  END la_oenb[116]
-  PIN la_oenb[117]
+  END la_oenb[101]
+  PIN la_oenb[100]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 838.670 0.000 838.950 4.000 ;
     END
-  END la_oenb[117]
-  PIN la_oenb[118]
+  END la_oenb[100]
+  PIN la_oenb[99]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 843.730 0.000 844.010 4.000 ;
     END
-  END la_oenb[118]
-  PIN la_oenb[119]
+  END la_oenb[99]
+  PIN la_oenb[98]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 849.250 0.000 849.530 4.000 ;
     END
-  END la_oenb[119]
-  PIN la_oenb[11]
+  END la_oenb[98]
+  PIN la_oenb[97]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 257.690 0.000 257.970 4.000 ;
     END
-  END la_oenb[11]
-  PIN la_oenb[120]
+  END la_oenb[97]
+  PIN la_oenb[96]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 854.770 0.000 855.050 4.000 ;
     END
-  END la_oenb[120]
-  PIN la_oenb[121]
+  END la_oenb[96]
+  PIN la_oenb[95]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 860.290 0.000 860.570 4.000 ;
     END
-  END la_oenb[121]
-  PIN la_oenb[122]
+  END la_oenb[95]
+  PIN la_oenb[94]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 865.810 0.000 866.090 4.000 ;
     END
-  END la_oenb[122]
-  PIN la_oenb[123]
+  END la_oenb[94]
+  PIN la_oenb[93]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 871.330 0.000 871.610 4.000 ;
     END
-  END la_oenb[123]
-  PIN la_oenb[124]
+  END la_oenb[93]
+  PIN la_oenb[92]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 876.850 0.000 877.130 4.000 ;
     END
-  END la_oenb[124]
-  PIN la_oenb[125]
+  END la_oenb[92]
+  PIN la_oenb[91]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 882.370 0.000 882.650 4.000 ;
     END
-  END la_oenb[125]
-  PIN la_oenb[126]
+  END la_oenb[91]
+  PIN la_oenb[90]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 887.890 0.000 888.170 4.000 ;
     END
-  END la_oenb[126]
-  PIN la_oenb[127]
+  END la_oenb[90]
+  PIN la_oenb[89]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 893.410 0.000 893.690 4.000 ;
     END
-  END la_oenb[127]
-  PIN la_oenb[12]
+  END la_oenb[89]
+  PIN la_oenb[88]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 263.210 0.000 263.490 4.000 ;
     END
-  END la_oenb[12]
-  PIN la_oenb[13]
+  END la_oenb[88]
+  PIN la_oenb[87]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 268.730 0.000 269.010 4.000 ;
     END
-  END la_oenb[13]
-  PIN la_oenb[14]
+  END la_oenb[87]
+  PIN la_oenb[86]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 274.250 0.000 274.530 4.000 ;
     END
-  END la_oenb[14]
-  PIN la_oenb[15]
+  END la_oenb[86]
+  PIN la_oenb[85]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 279.770 0.000 280.050 4.000 ;
     END
-  END la_oenb[15]
-  PIN la_oenb[16]
+  END la_oenb[85]
+  PIN la_oenb[84]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 285.290 0.000 285.570 4.000 ;
     END
-  END la_oenb[16]
-  PIN la_oenb[17]
+  END la_oenb[84]
+  PIN la_oenb[83]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 290.810 0.000 291.090 4.000 ;
     END
-  END la_oenb[17]
-  PIN la_oenb[18]
+  END la_oenb[83]
+  PIN la_oenb[82]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 296.330 0.000 296.610 4.000 ;
     END
-  END la_oenb[18]
-  PIN la_oenb[19]
+  END la_oenb[82]
+  PIN la_oenb[81]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 301.390 0.000 301.670 4.000 ;
     END
-  END la_oenb[19]
-  PIN la_oenb[1]
+  END la_oenb[81]
+  PIN la_oenb[80]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 202.950 0.000 203.230 4.000 ;
     END
-  END la_oenb[1]
-  PIN la_oenb[20]
+  END la_oenb[80]
+  PIN la_oenb[79]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 306.910 0.000 307.190 4.000 ;
     END
-  END la_oenb[20]
-  PIN la_oenb[21]
+  END la_oenb[79]
+  PIN la_oenb[78]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 312.430 0.000 312.710 4.000 ;
     END
-  END la_oenb[21]
-  PIN la_oenb[22]
+  END la_oenb[78]
+  PIN la_oenb[77]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 317.950 0.000 318.230 4.000 ;
     END
-  END la_oenb[22]
-  PIN la_oenb[23]
+  END la_oenb[77]
+  PIN la_oenb[76]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 323.470 0.000 323.750 4.000 ;
     END
-  END la_oenb[23]
-  PIN la_oenb[24]
+  END la_oenb[76]
+  PIN la_oenb[75]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 328.990 0.000 329.270 4.000 ;
     END
-  END la_oenb[24]
-  PIN la_oenb[25]
+  END la_oenb[75]
+  PIN la_oenb[74]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 334.510 0.000 334.790 4.000 ;
     END
-  END la_oenb[25]
-  PIN la_oenb[26]
+  END la_oenb[74]
+  PIN la_oenb[73]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 340.030 0.000 340.310 4.000 ;
     END
-  END la_oenb[26]
-  PIN la_oenb[27]
+  END la_oenb[73]
+  PIN la_oenb[72]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 345.550 0.000 345.830 4.000 ;
     END
-  END la_oenb[27]
-  PIN la_oenb[28]
+  END la_oenb[72]
+  PIN la_oenb[71]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 351.070 0.000 351.350 4.000 ;
     END
-  END la_oenb[28]
-  PIN la_oenb[29]
+  END la_oenb[71]
+  PIN la_oenb[70]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 356.590 0.000 356.870 4.000 ;
     END
-  END la_oenb[29]
-  PIN la_oenb[2]
+  END la_oenb[70]
+  PIN la_oenb[69]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 208.470 0.000 208.750 4.000 ;
     END
-  END la_oenb[2]
-  PIN la_oenb[30]
+  END la_oenb[69]
+  PIN la_oenb[68]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 361.650 0.000 361.930 4.000 ;
     END
-  END la_oenb[30]
-  PIN la_oenb[31]
+  END la_oenb[68]
+  PIN la_oenb[67]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 367.170 0.000 367.450 4.000 ;
     END
-  END la_oenb[31]
-  PIN la_oenb[32]
+  END la_oenb[67]
+  PIN la_oenb[66]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 372.690 0.000 372.970 4.000 ;
     END
-  END la_oenb[32]
-  PIN la_oenb[33]
+  END la_oenb[66]
+  PIN la_oenb[65]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 378.210 0.000 378.490 4.000 ;
     END
-  END la_oenb[33]
-  PIN la_oenb[34]
+  END la_oenb[65]
+  PIN la_oenb[64]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 383.730 0.000 384.010 4.000 ;
     END
-  END la_oenb[34]
-  PIN la_oenb[35]
+  END la_oenb[64]
+  PIN la_oenb[63]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 389.250 0.000 389.530 4.000 ;
     END
-  END la_oenb[35]
-  PIN la_oenb[36]
+  END la_oenb[63]
+  PIN la_oenb[62]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 394.770 0.000 395.050 4.000 ;
     END
-  END la_oenb[36]
-  PIN la_oenb[37]
+  END la_oenb[62]
+  PIN la_oenb[61]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 400.290 0.000 400.570 4.000 ;
     END
-  END la_oenb[37]
-  PIN la_oenb[38]
+  END la_oenb[61]
+  PIN la_oenb[60]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 405.810 0.000 406.090 4.000 ;
     END
-  END la_oenb[38]
-  PIN la_oenb[39]
+  END la_oenb[60]
+  PIN la_oenb[59]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 411.330 0.000 411.610 4.000 ;
     END
-  END la_oenb[39]
-  PIN la_oenb[3]
+  END la_oenb[59]
+  PIN la_oenb[58]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 213.990 0.000 214.270 4.000 ;
     END
-  END la_oenb[3]
-  PIN la_oenb[40]
+  END la_oenb[58]
+  PIN la_oenb[57]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 416.850 0.000 417.130 4.000 ;
     END
-  END la_oenb[40]
-  PIN la_oenb[41]
+  END la_oenb[57]
+  PIN la_oenb[56]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 421.910 0.000 422.190 4.000 ;
     END
-  END la_oenb[41]
-  PIN la_oenb[42]
+  END la_oenb[56]
+  PIN la_oenb[55]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 427.430 0.000 427.710 4.000 ;
     END
-  END la_oenb[42]
-  PIN la_oenb[43]
+  END la_oenb[55]
+  PIN la_oenb[54]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 432.950 0.000 433.230 4.000 ;
     END
-  END la_oenb[43]
-  PIN la_oenb[44]
+  END la_oenb[54]
+  PIN la_oenb[53]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 438.470 0.000 438.750 4.000 ;
     END
-  END la_oenb[44]
-  PIN la_oenb[45]
+  END la_oenb[53]
+  PIN la_oenb[52]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 443.990 0.000 444.270 4.000 ;
     END
-  END la_oenb[45]
-  PIN la_oenb[46]
+  END la_oenb[52]
+  PIN la_oenb[51]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 449.510 0.000 449.790 4.000 ;
     END
-  END la_oenb[46]
-  PIN la_oenb[47]
+  END la_oenb[51]
+  PIN la_oenb[50]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 455.030 0.000 455.310 4.000 ;
     END
-  END la_oenb[47]
-  PIN la_oenb[48]
+  END la_oenb[50]
+  PIN la_oenb[49]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 460.550 0.000 460.830 4.000 ;
     END
-  END la_oenb[48]
-  PIN la_oenb[49]
+  END la_oenb[49]
+  PIN la_oenb[48]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 466.070 0.000 466.350 4.000 ;
     END
-  END la_oenb[49]
-  PIN la_oenb[4]
+  END la_oenb[48]
+  PIN la_oenb[47]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 219.510 0.000 219.790 4.000 ;
     END
-  END la_oenb[4]
-  PIN la_oenb[50]
+  END la_oenb[47]
+  PIN la_oenb[46]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 471.590 0.000 471.870 4.000 ;
     END
-  END la_oenb[50]
-  PIN la_oenb[51]
+  END la_oenb[46]
+  PIN la_oenb[45]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 477.110 0.000 477.390 4.000 ;
     END
-  END la_oenb[51]
-  PIN la_oenb[52]
+  END la_oenb[45]
+  PIN la_oenb[44]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 482.170 0.000 482.450 4.000 ;
     END
-  END la_oenb[52]
-  PIN la_oenb[53]
+  END la_oenb[44]
+  PIN la_oenb[43]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 487.690 0.000 487.970 4.000 ;
     END
-  END la_oenb[53]
-  PIN la_oenb[54]
+  END la_oenb[43]
+  PIN la_oenb[42]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 493.210 0.000 493.490 4.000 ;
     END
-  END la_oenb[54]
-  PIN la_oenb[55]
+  END la_oenb[42]
+  PIN la_oenb[41]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 498.730 0.000 499.010 4.000 ;
     END
-  END la_oenb[55]
-  PIN la_oenb[56]
+  END la_oenb[41]
+  PIN la_oenb[40]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 504.250 0.000 504.530 4.000 ;
     END
-  END la_oenb[56]
-  PIN la_oenb[57]
+  END la_oenb[40]
+  PIN la_oenb[39]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 509.770 0.000 510.050 4.000 ;
     END
-  END la_oenb[57]
-  PIN la_oenb[58]
+  END la_oenb[39]
+  PIN la_oenb[38]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 515.290 0.000 515.570 4.000 ;
     END
-  END la_oenb[58]
-  PIN la_oenb[59]
+  END la_oenb[38]
+  PIN la_oenb[37]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 520.810 0.000 521.090 4.000 ;
     END
-  END la_oenb[59]
-  PIN la_oenb[5]
+  END la_oenb[37]
+  PIN la_oenb[36]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 225.030 0.000 225.310 4.000 ;
     END
-  END la_oenb[5]
-  PIN la_oenb[60]
+  END la_oenb[36]
+  PIN la_oenb[35]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 526.330 0.000 526.610 4.000 ;
     END
-  END la_oenb[60]
-  PIN la_oenb[61]
+  END la_oenb[35]
+  PIN la_oenb[34]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 531.850 0.000 532.130 4.000 ;
     END
-  END la_oenb[61]
-  PIN la_oenb[62]
+  END la_oenb[34]
+  PIN la_oenb[33]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 537.370 0.000 537.650 4.000 ;
     END
-  END la_oenb[62]
-  PIN la_oenb[63]
+  END la_oenb[33]
+  PIN la_oenb[32]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 542.430 0.000 542.710 4.000 ;
     END
-  END la_oenb[63]
-  PIN la_oenb[64]
+  END la_oenb[32]
+  PIN la_oenb[31]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 547.950 0.000 548.230 4.000 ;
     END
-  END la_oenb[64]
-  PIN la_oenb[65]
+  END la_oenb[31]
+  PIN la_oenb[30]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 553.470 0.000 553.750 4.000 ;
     END
-  END la_oenb[65]
-  PIN la_oenb[66]
+  END la_oenb[30]
+  PIN la_oenb[29]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 558.990 0.000 559.270 4.000 ;
     END
-  END la_oenb[66]
-  PIN la_oenb[67]
+  END la_oenb[29]
+  PIN la_oenb[28]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 564.510 0.000 564.790 4.000 ;
     END
-  END la_oenb[67]
-  PIN la_oenb[68]
+  END la_oenb[28]
+  PIN la_oenb[27]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 570.030 0.000 570.310 4.000 ;
     END
-  END la_oenb[68]
-  PIN la_oenb[69]
+  END la_oenb[27]
+  PIN la_oenb[26]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 575.550 0.000 575.830 4.000 ;
     END
-  END la_oenb[69]
-  PIN la_oenb[6]
+  END la_oenb[26]
+  PIN la_oenb[25]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 230.550 0.000 230.830 4.000 ;
     END
-  END la_oenb[6]
-  PIN la_oenb[70]
+  END la_oenb[25]
+  PIN la_oenb[24]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 581.070 0.000 581.350 4.000 ;
     END
-  END la_oenb[70]
-  PIN la_oenb[71]
+  END la_oenb[24]
+  PIN la_oenb[23]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 586.590 0.000 586.870 4.000 ;
     END
-  END la_oenb[71]
-  PIN la_oenb[72]
+  END la_oenb[23]
+  PIN la_oenb[22]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 592.110 0.000 592.390 4.000 ;
     END
-  END la_oenb[72]
-  PIN la_oenb[73]
+  END la_oenb[22]
+  PIN la_oenb[21]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 597.630 0.000 597.910 4.000 ;
     END
-  END la_oenb[73]
-  PIN la_oenb[74]
+  END la_oenb[21]
+  PIN la_oenb[20]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 602.690 0.000 602.970 4.000 ;
     END
-  END la_oenb[74]
-  PIN la_oenb[75]
+  END la_oenb[20]
+  PIN la_oenb[19]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 608.210 0.000 608.490 4.000 ;
     END
-  END la_oenb[75]
-  PIN la_oenb[76]
+  END la_oenb[19]
+  PIN la_oenb[18]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 613.730 0.000 614.010 4.000 ;
     END
-  END la_oenb[76]
-  PIN la_oenb[77]
+  END la_oenb[18]
+  PIN la_oenb[17]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 619.250 0.000 619.530 4.000 ;
     END
-  END la_oenb[77]
-  PIN la_oenb[78]
+  END la_oenb[17]
+  PIN la_oenb[16]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 624.770 0.000 625.050 4.000 ;
     END
-  END la_oenb[78]
-  PIN la_oenb[79]
+  END la_oenb[16]
+  PIN la_oenb[15]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 630.290 0.000 630.570 4.000 ;
     END
-  END la_oenb[79]
-  PIN la_oenb[7]
+  END la_oenb[15]
+  PIN la_oenb[14]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 236.070 0.000 236.350 4.000 ;
     END
-  END la_oenb[7]
-  PIN la_oenb[80]
+  END la_oenb[14]
+  PIN la_oenb[13]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 635.810 0.000 636.090 4.000 ;
     END
-  END la_oenb[80]
-  PIN la_oenb[81]
+  END la_oenb[13]
+  PIN la_oenb[12]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 641.330 0.000 641.610 4.000 ;
     END
-  END la_oenb[81]
-  PIN la_oenb[82]
+  END la_oenb[12]
+  PIN la_oenb[11]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 646.850 0.000 647.130 4.000 ;
     END
-  END la_oenb[82]
-  PIN la_oenb[83]
+  END la_oenb[11]
+  PIN la_oenb[10]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 652.370 0.000 652.650 4.000 ;
     END
-  END la_oenb[83]
-  PIN la_oenb[84]
+  END la_oenb[10]
+  PIN la_oenb[9]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 657.890 0.000 658.170 4.000 ;
     END
-  END la_oenb[84]
-  PIN la_oenb[85]
+  END la_oenb[9]
+  PIN la_oenb[8]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 662.950 0.000 663.230 4.000 ;
     END
-  END la_oenb[85]
-  PIN la_oenb[86]
+  END la_oenb[8]
+  PIN la_oenb[7]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 668.470 0.000 668.750 4.000 ;
     END
-  END la_oenb[86]
-  PIN la_oenb[87]
+  END la_oenb[7]
+  PIN la_oenb[6]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 673.990 0.000 674.270 4.000 ;
     END
-  END la_oenb[87]
-  PIN la_oenb[88]
+  END la_oenb[6]
+  PIN la_oenb[5]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 679.510 0.000 679.790 4.000 ;
     END
-  END la_oenb[88]
-  PIN la_oenb[89]
+  END la_oenb[5]
+  PIN la_oenb[4]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 685.030 0.000 685.310 4.000 ;
     END
-  END la_oenb[89]
-  PIN la_oenb[8]
+  END la_oenb[4]
+  PIN la_oenb[3]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 241.130 0.000 241.410 4.000 ;
     END
-  END la_oenb[8]
-  PIN la_oenb[90]
+  END la_oenb[3]
+  PIN la_oenb[2]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 690.550 0.000 690.830 4.000 ;
     END
-  END la_oenb[90]
-  PIN la_oenb[91]
+  END la_oenb[2]
+  PIN la_oenb[1]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 696.070 0.000 696.350 4.000 ;
     END
-  END la_oenb[91]
-  PIN la_oenb[92]
+  END la_oenb[1]
+  PIN la_oenb[0]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 701.590 0.000 701.870 4.000 ;
     END
-  END la_oenb[92]
-  PIN la_oenb[93]
+  END la_oenb[0]
+  PIN io_in[37]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 707.110 0.000 707.390 4.000 ;
     END
-  END la_oenb[93]
-  PIN la_oenb[94]
+  END io_in[37]
+  PIN io_in[36]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 712.630 0.000 712.910 4.000 ;
     END
-  END la_oenb[94]
-  PIN la_oenb[95]
+  END io_in[36]
+  PIN io_in[35]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 718.150 0.000 718.430 4.000 ;
     END
-  END la_oenb[95]
-  PIN la_oenb[96]
+  END io_in[35]
+  PIN io_in[34]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 723.210 0.000 723.490 4.000 ;
     END
-  END la_oenb[96]
-  PIN la_oenb[97]
+  END io_in[34]
+  PIN io_in[33]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 728.730 0.000 729.010 4.000 ;
     END
-  END la_oenb[97]
-  PIN la_oenb[98]
+  END io_in[33]
+  PIN io_in[32]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 734.250 0.000 734.530 4.000 ;
     END
-  END la_oenb[98]
-  PIN la_oenb[99]
+  END io_in[32]
+  PIN io_in[31]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 739.770 0.000 740.050 4.000 ;
     END
-  END la_oenb[99]
-  PIN la_oenb[9]
+  END io_in[31]
+  PIN io_in[30]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
@@ -4035,316 +4042,308 @@
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 0.550 0.000 0.830 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 1787.250000 0.800000 1787.550000 ;
     END
-  END wb_clk_i
-  PIN wb_rst_i
+  END io_in[29]
+  PIN io_in[28]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 1.930 0.000 2.210 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 2010.510000 0.800000 2010.810000 ;
     END
-  END wb_rst_i
-  PIN wbs_ack_o
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 3.770 0.000 4.050 4.000 ;
-    END
-  END wbs_ack_o
-  PIN wbs_adr_i[0]
+  END io_in[28]
+  PIN io_in[27]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 11.130 0.000 11.410 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 2234.380000 0.800000 2234.680000 ;
     END
-  END wbs_adr_i[0]
-  PIN wbs_adr_i[10]
+  END io_in[27]
+  PIN io_in[26]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 73.230 0.000 73.510 4.000 ;
     END
-  END wbs_adr_i[10]
-  PIN wbs_adr_i[11]
+  END io_in[26]
+  PIN io_in[25]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 78.750 0.000 79.030 4.000 ;
     END
-  END wbs_adr_i[11]
-  PIN wbs_adr_i[12]
+  END io_in[25]
+  PIN io_in[24]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 84.270 0.000 84.550 4.000 ;
     END
-  END wbs_adr_i[12]
-  PIN wbs_adr_i[13]
+  END io_in[24]
+  PIN io_in[23]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 89.790 0.000 90.070 4.000 ;
     END
-  END wbs_adr_i[13]
-  PIN wbs_adr_i[14]
+  END io_in[23]
+  PIN io_in[22]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 95.310 0.000 95.590 4.000 ;
     END
-  END wbs_adr_i[14]
-  PIN wbs_adr_i[15]
+  END io_in[22]
+  PIN io_in[21]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 100.830 0.000 101.110 4.000 ;
     END
-  END wbs_adr_i[15]
-  PIN wbs_adr_i[16]
+  END io_in[21]
+  PIN io_in[20]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 106.350 0.000 106.630 4.000 ;
     END
-  END wbs_adr_i[16]
-  PIN wbs_adr_i[17]
+  END io_in[20]
+  PIN io_in[19]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 111.870 0.000 112.150 4.000 ;
     END
-  END wbs_adr_i[17]
-  PIN wbs_adr_i[18]
+  END io_in[19]
+  PIN io_in[18]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 117.390 0.000 117.670 4.000 ;
     END
-  END wbs_adr_i[18]
-  PIN wbs_adr_i[19]
+  END io_in[18]
+  PIN io_in[17]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 122.450 0.000 122.730 4.000 ;
     END
-  END wbs_adr_i[19]
-  PIN wbs_adr_i[1]
+  END io_in[17]
+  PIN io_in[16]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 18.490 0.000 18.770 4.000 ;
+        RECT 1919.740000 2959.550000 1919.880000 2960.040000 ;
     END
-  END wbs_adr_i[1]
-  PIN wbs_adr_i[20]
+  END io_in[16]
+  PIN io_in[15]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 127.970 0.000 128.250 4.000 ;
     END
-  END wbs_adr_i[20]
-  PIN wbs_adr_i[21]
+  END io_in[15]
+  PIN io_in[14]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 133.490 0.000 133.770 4.000 ;
     END
-  END wbs_adr_i[21]
-  PIN wbs_adr_i[22]
+  END io_in[14]
+  PIN io_in[13]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 139.010 0.000 139.290 4.000 ;
     END
-  END wbs_adr_i[22]
-  PIN wbs_adr_i[23]
+  END io_in[13]
+  PIN io_in[12]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 144.530 0.000 144.810 4.000 ;
     END
-  END wbs_adr_i[23]
-  PIN wbs_adr_i[24]
+  END io_in[12]
+  PIN io_in[11]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 150.050 0.000 150.330 4.000 ;
     END
-  END wbs_adr_i[24]
-  PIN wbs_adr_i[25]
+  END io_in[11]
+  PIN io_in[10]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 155.570 0.000 155.850 4.000 ;
     END
-  END wbs_adr_i[25]
-  PIN wbs_adr_i[26]
+  END io_in[10]
+  PIN io_in[9]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 161.090 0.000 161.370 4.000 ;
     END
-  END wbs_adr_i[26]
-  PIN wbs_adr_i[27]
+  END io_in[9]
+  PIN io_in[8]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 166.610 0.000 166.890 4.000 ;
     END
-  END wbs_adr_i[27]
-  PIN wbs_adr_i[28]
+  END io_in[8]
+  PIN io_in[7]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 172.130 0.000 172.410 4.000 ;
     END
-  END wbs_adr_i[28]
-  PIN wbs_adr_i[29]
+  END io_in[7]
+  PIN io_in[6]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 177.650 0.000 177.930 4.000 ;
     END
-  END wbs_adr_i[29]
-  PIN wbs_adr_i[2]
+  END io_in[6]
+  PIN io_in[5]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 25.850 0.000 26.130 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 853.340000 2239.740000 853.640000 ;
     END
-  END wbs_adr_i[2]
-  PIN wbs_adr_i[30]
+  END io_in[5]
+  PIN io_in[4]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 182.710 0.000 182.990 4.000 ;
     END
-  END wbs_adr_i[30]
-  PIN wbs_adr_i[31]
+  END io_in[4]
+  PIN io_in[3]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 188.230 0.000 188.510 4.000 ;
     END
-  END wbs_adr_i[31]
-  PIN wbs_adr_i[3]
+  END io_in[3]
+  PIN io_in[2]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 33.210 0.000 33.490 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 340.940000 2239.740000 341.240000 ;
     END
-  END wbs_adr_i[3]
-  PIN wbs_adr_i[4]
+  END io_in[2]
+  PIN io_in[1]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 40.570 0.000 40.850 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 170.140000 2239.740000 170.440000 ;
     END
-  END wbs_adr_i[4]
-  PIN wbs_adr_i[5]
+  END io_in[1]
+  PIN io_in[0]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 46.090 0.000 46.370 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 4.220000 2239.740000 4.520000 ;
     END
-  END wbs_adr_i[5]
-  PIN wbs_adr_i[6]
-    DIRECTION INPUT ;
+  END io_in[0]
+  PIN io_out[37]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 51.610 0.000 51.890 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 56.070000 0.800000 56.370000 ;
     END
-  END wbs_adr_i[6]
-  PIN wbs_adr_i[7]
-    DIRECTION INPUT ;
+  END io_out[37]
+  PIN io_out[36]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 57.130 0.000 57.410 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 223.820000 0.800000 224.120000 ;
     END
-  END wbs_adr_i[7]
-  PIN wbs_adr_i[8]
-    DIRECTION INPUT ;
+  END io_out[36]
+  PIN io_out[35]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 62.190 0.000 62.470 4.000 ;
     END
-  END wbs_adr_i[8]
-  PIN wbs_adr_i[9]
-    DIRECTION INPUT ;
+  END io_out[35]
+  PIN io_out[34]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 67.710 0.000 67.990 4.000 ;
     END
-  END wbs_adr_i[9]
-  PIN wbs_cyc_i
-    DIRECTION INPUT ;
+  END io_out[34]
+  PIN io_out[33]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 5.610 0.000 5.890 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 838.090000 0.800000 838.390000 ;
     END
-  END wbs_cyc_i
-  PIN wbs_dat_i[0]
-    DIRECTION INPUT ;
+  END io_out[33]
+  PIN io_out[32]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 12.970 0.000 13.250 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 1061.350000 0.800000 1061.650000 ;
     END
-  END wbs_dat_i[0]
-  PIN wbs_dat_i[10]
-    DIRECTION INPUT ;
+  END io_out[32]
+  PIN io_out[31]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 75.070 0.000 75.350 4.000 ;
     END
-  END wbs_dat_i[10]
-  PIN wbs_dat_i[11]
-    DIRECTION INPUT ;
+  END io_out[31]
+  PIN io_out[30]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 80.590 0.000 80.870 4.000 ;
     END
-  END wbs_dat_i[11]
-  PIN wbs_dat_i[12]
-    DIRECTION INPUT ;
+  END io_out[30]
+  PIN io_out[29]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
@@ -4430,453 +4429,453 @@
       LAYER met2 ;
         RECT 135.330 0.000 135.610 4.000 ;
     END
-  END wbs_dat_i[21]
-  PIN wbs_dat_i[22]
-    DIRECTION INPUT ;
+  END io_out[29]
+  PIN io_out[28]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 140.850 0.000 141.130 4.000 ;
     END
-  END wbs_dat_i[22]
-  PIN wbs_dat_i[23]
-    DIRECTION INPUT ;
+  END io_out[28]
+  PIN io_out[27]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 146.370 0.000 146.650 4.000 ;
     END
-  END wbs_dat_i[23]
-  PIN wbs_dat_i[24]
-    DIRECTION INPUT ;
+  END io_out[27]
+  PIN io_out[26]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 151.890 0.000 152.170 4.000 ;
     END
-  END wbs_dat_i[24]
-  PIN wbs_dat_i[25]
-    DIRECTION INPUT ;
+  END io_out[26]
+  PIN io_out[25]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 157.410 0.000 157.690 4.000 ;
     END
-  END wbs_dat_i[25]
-  PIN wbs_dat_i[26]
-    DIRECTION INPUT ;
+  END io_out[25]
+  PIN io_out[24]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 162.930 0.000 163.210 4.000 ;
     END
-  END wbs_dat_i[26]
-  PIN wbs_dat_i[27]
-    DIRECTION INPUT ;
+  END io_out[24]
+  PIN io_out[23]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 168.450 0.000 168.730 4.000 ;
     END
-  END wbs_dat_i[27]
-  PIN wbs_dat_i[28]
-    DIRECTION INPUT ;
+  END io_out[23]
+  PIN io_out[22]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 173.970 0.000 174.250 4.000 ;
     END
-  END wbs_dat_i[28]
-  PIN wbs_dat_i[29]
-    DIRECTION INPUT ;
+  END io_out[22]
+  PIN io_out[21]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 179.490 0.000 179.770 4.000 ;
     END
-  END wbs_dat_i[29]
-  PIN wbs_dat_i[2]
-    DIRECTION INPUT ;
+  END io_out[21]
+  PIN io_out[20]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 27.690 0.000 27.970 4.000 ;
+        RECT 831.840000 2959.550000 831.980000 2960.040000 ;
     END
-  END wbs_dat_i[2]
-  PIN wbs_dat_i[30]
-    DIRECTION INPUT ;
+  END io_out[20]
+  PIN io_out[19]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 184.550 0.000 184.830 4.000 ;
     END
-  END wbs_dat_i[30]
-  PIN wbs_dat_i[31]
-    DIRECTION INPUT ;
+  END io_out[19]
+  PIN io_out[18]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 190.070 0.000 190.350 4.000 ;
     END
-  END wbs_dat_i[31]
-  PIN wbs_dat_i[3]
-    DIRECTION INPUT ;
+  END io_out[18]
+  PIN io_out[17]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 35.050 0.000 35.330 4.000 ;
+        RECT 1600.040000 2959.550000 1600.180000 2960.040000 ;
     END
-  END wbs_dat_i[3]
-  PIN wbs_dat_i[4]
-    DIRECTION INPUT ;
+  END io_out[17]
+  PIN io_out[16]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 42.410 0.000 42.690 4.000 ;
+        RECT 1855.800000 2959.550000 1855.940000 2960.040000 ;
     END
-  END wbs_dat_i[4]
-  PIN wbs_dat_i[5]
-    DIRECTION INPUT ;
+  END io_out[16]
+  PIN io_out[15]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 47.930 0.000 48.210 4.000 ;
+        RECT 2112.020000 2959.550000 2112.160000 2960.040000 ;
     END
-  END wbs_dat_i[5]
-  PIN wbs_dat_i[6]
-    DIRECTION INPUT ;
+  END io_out[15]
+  PIN io_out[14]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 53.450 0.000 53.730 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2902.330000 2239.740000 2902.630000 ;
     END
-  END wbs_dat_i[6]
-  PIN wbs_dat_i[7]
-    DIRECTION INPUT ;
+  END io_out[14]
+  PIN io_out[13]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 58.970 0.000 59.250 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2674.800000 2239.740000 2675.100000 ;
     END
-  END wbs_dat_i[7]
-  PIN wbs_dat_i[8]
-    DIRECTION INPUT ;
+  END io_out[13]
+  PIN io_out[12]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 64.030 0.000 64.310 4.000 ;
     END
-  END wbs_dat_i[8]
-  PIN wbs_dat_i[9]
-    DIRECTION INPUT ;
+  END io_out[12]
+  PIN io_out[11]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 69.550 0.000 69.830 4.000 ;
     END
-  END wbs_dat_i[9]
-  PIN wbs_dat_o[0]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[11]
+  PIN io_out[10]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 14.810 0.000 15.090 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 1991.600000 2239.740000 1991.900000 ;
     END
-  END wbs_dat_o[0]
-  PIN wbs_dat_o[10]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[10]
+  PIN io_out[9]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 76.910 0.000 77.190 4.000 ;
     END
-  END wbs_dat_o[10]
-  PIN wbs_dat_o[11]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[9]
+  PIN io_out[8]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 82.430 0.000 82.710 4.000 ;
     END
-  END wbs_dat_o[11]
-  PIN wbs_dat_o[12]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[8]
+  PIN io_out[7]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 87.950 0.000 88.230 4.000 ;
     END
-  END wbs_dat_o[12]
-  PIN wbs_dat_o[13]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[7]
+  PIN io_out[6]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 93.470 0.000 93.750 4.000 ;
     END
-  END wbs_dat_o[13]
-  PIN wbs_dat_o[14]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[6]
+  PIN io_out[5]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 98.990 0.000 99.270 4.000 ;
     END
-  END wbs_dat_o[14]
-  PIN wbs_dat_o[15]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[5]
+  PIN io_out[4]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 104.510 0.000 104.790 4.000 ;
     END
-  END wbs_dat_o[15]
-  PIN wbs_dat_o[16]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[4]
+  PIN io_out[3]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 110.030 0.000 110.310 4.000 ;
     END
-  END wbs_dat_o[16]
-  PIN wbs_dat_o[17]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[3]
+  PIN io_out[2]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 115.550 0.000 115.830 4.000 ;
     END
-  END wbs_dat_o[17]
-  PIN wbs_dat_o[18]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[2]
+  PIN io_out[1]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 120.610 0.000 120.890 4.000 ;
     END
-  END wbs_dat_o[18]
-  PIN wbs_dat_o[19]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[1]
+  PIN io_out[0]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 126.130 0.000 126.410 4.000 ;
     END
-  END wbs_dat_o[19]
-  PIN wbs_dat_o[1]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_out[0]
+  PIN io_oeb[37]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 22.170 0.000 22.450 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 5.440000 0.800000 5.740000 ;
     END
-  END wbs_dat_o[1]
-  PIN wbs_dat_o[20]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[37]
+  PIN io_oeb[36]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 131.650 0.000 131.930 4.000 ;
     END
-  END wbs_dat_o[20]
-  PIN wbs_dat_o[21]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[36]
+  PIN io_oeb[35]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 137.170 0.000 137.450 4.000 ;
     END
-  END wbs_dat_o[21]
-  PIN wbs_dat_o[22]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[35]
+  PIN io_oeb[34]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 142.690 0.000 142.970 4.000 ;
     END
-  END wbs_dat_o[22]
-  PIN wbs_dat_o[23]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[34]
+  PIN io_oeb[33]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 148.210 0.000 148.490 4.000 ;
     END
-  END wbs_dat_o[23]
-  PIN wbs_dat_o[24]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[33]
+  PIN io_oeb[32]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 153.730 0.000 154.010 4.000 ;
     END
-  END wbs_dat_o[24]
-  PIN wbs_dat_o[25]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[32]
+  PIN io_oeb[31]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 159.250 0.000 159.530 4.000 ;
     END
-  END wbs_dat_o[25]
-  PIN wbs_dat_o[26]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[31]
+  PIN io_oeb[30]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 164.770 0.000 165.050 4.000 ;
     END
-  END wbs_dat_o[26]
-  PIN wbs_dat_o[27]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[30]
+  PIN io_oeb[29]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 170.290 0.000 170.570 4.000 ;
     END
-  END wbs_dat_o[27]
-  PIN wbs_dat_o[28]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[29]
+  PIN io_oeb[28]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 175.810 0.000 176.090 4.000 ;
     END
-  END wbs_dat_o[28]
-  PIN wbs_dat_o[29]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[28]
+  PIN io_oeb[27]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 180.870 0.000 181.150 4.000 ;
     END
-  END wbs_dat_o[29]
-  PIN wbs_dat_o[2]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[27]
+  PIN io_oeb[26]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 29.530 0.000 29.810 4.000 ;
+      LAYER met3 ;
+        RECT 0.000000 2346.010000 0.800000 2346.310000 ;
     END
-  END wbs_dat_o[2]
-  PIN wbs_dat_o[30]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[26]
+  PIN io_oeb[25]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 186.390 0.000 186.670 4.000 ;
     END
-  END wbs_dat_o[30]
-  PIN wbs_dat_o[31]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[25]
+  PIN io_oeb[24]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 191.910 0.000 192.190 4.000 ;
     END
-  END wbs_dat_o[31]
-  PIN wbs_dat_o[3]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[24]
+  PIN io_oeb[23]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 36.890 0.000 37.170 4.000 ;
+        RECT 5.220000 2959.550000 5.360000 2960.040000 ;
     END
-  END wbs_dat_o[3]
-  PIN wbs_dat_o[4]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[23]
+  PIN io_oeb[22]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 44.250 0.000 44.530 4.000 ;
+        RECT 255.920000 2959.550000 256.060000 2960.040000 ;
     END
-  END wbs_dat_o[4]
-  PIN wbs_dat_o[5]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[22]
+  PIN io_oeb[21]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 49.770 0.000 50.050 4.000 ;
+        RECT 512.140000 2959.550000 512.280000 2960.040000 ;
     END
-  END wbs_dat_o[5]
-  PIN wbs_dat_o[6]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[21]
+  PIN io_oeb[20]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 55.290 0.000 55.570 4.000 ;
+        RECT 767.900000 2959.550000 768.040000 2960.040000 ;
     END
-  END wbs_dat_o[6]
-  PIN wbs_dat_o[7]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[20]
+  PIN io_oeb[19]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 60.350 0.000 60.630 4.000 ;
     END
-  END wbs_dat_o[7]
-  PIN wbs_dat_o[8]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[19]
+  PIN io_oeb[18]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 65.870 0.000 66.150 4.000 ;
     END
-  END wbs_dat_o[8]
-  PIN wbs_dat_o[9]
-    DIRECTION OUTPUT TRISTATE ;
+  END io_oeb[18]
+  PIN io_oeb[17]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
         RECT 71.390 0.000 71.670 4.000 ;
     END
-  END wbs_dat_o[9]
-  PIN wbs_sel_i[0]
-    DIRECTION INPUT ;
+  END io_oeb[17]
+  PIN io_oeb[16]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 16.650 0.000 16.930 4.000 ;
+        RECT 1791.860000 2959.550000 1792.000000 2960.040000 ;
     END
-  END wbs_sel_i[0]
-  PIN wbs_sel_i[1]
-    DIRECTION INPUT ;
+  END io_oeb[16]
+  PIN io_oeb[15]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 24.010 0.000 24.290 4.000 ;
+        RECT 2048.080000 2959.550000 2048.220000 2960.040000 ;
     END
-  END wbs_sel_i[1]
-  PIN wbs_sel_i[2]
-    DIRECTION INPUT ;
+  END io_oeb[15]
+  PIN io_oeb[14]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 31.370 0.000 31.650 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2954.180000 2239.740000 2954.480000 ;
     END
-  END wbs_sel_i[2]
-  PIN wbs_sel_i[3]
-    DIRECTION INPUT ;
+  END io_oeb[14]
+  PIN io_oeb[13]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 38.730 0.000 39.010 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2732.140000 2239.740000 2732.440000 ;
     END
-  END wbs_sel_i[3]
-  PIN wbs_stb_i
-    DIRECTION INPUT ;
+  END io_oeb[13]
+  PIN io_oeb[12]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 7.450 0.000 7.730 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2504.000000 2239.740000 2504.300000 ;
     END
-  END wbs_stb_i
-  PIN wbs_we_i
-    DIRECTION INPUT ;
+  END io_oeb[12]
+  PIN io_oeb[11]
+    DIRECTION OUTPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met2 ;
-        RECT 9.290 0.000 9.570 4.000 ;
+      LAYER met3 ;
+        RECT 2238.940000 2276.470000 2239.740000 2276.770000 ;
     END
   END wbs_we_i
   OBS
@@ -5499,5 +5498,5 @@
         RECT 174.640 9.015 867.440 587.760 ;
   END
 END user_proj_example
-END LIBRARY
 
+END LIBRARY

mag/user_project_wrapper.mag

diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index ff669ca..e99ee46 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,15607 +1,15267 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1631895074
-<< locali >>
-rect 287655 460377 287805 460411
-rect 283481 456875 283515 457589
-rect 377597 456807 377631 457453
-rect 379161 457283 379195 457453
-rect 388637 457147 388671 457317
-rect 402989 457079 403023 457453
-rect 403081 456943 403115 457317
-rect 288357 336583 288391 336685
-rect 301789 336651 301823 336685
-rect 301605 336617 301823 336651
-rect 310471 336617 310897 336651
-rect 301605 336583 301639 336617
-rect 268795 336141 268945 336175
-rect 293417 335631 293451 336413
-rect 301697 335903 301731 336549
-rect 376125 335835 376159 336277
-rect 378425 336107 378459 336209
-rect 372537 335563 372571 335801
-rect 378793 335767 378827 336481
-rect 382289 336175 382323 336549
-rect 382841 336311 382875 336481
-rect 387199 336413 387291 336447
-rect 383853 335359 383887 336413
-rect 387257 335359 387291 336413
-rect 390477 336107 390511 336413
-rect 391213 335359 391247 336141
-rect 413109 335359 413143 335597
-rect 387165 335155 387199 335325
-rect 407865 333455 407899 333897
-rect 582389 19839 582423 458269
-rect 258123 8109 258457 8143
-rect 258089 7871 258123 7973
-rect 84301 4097 84577 4131
-rect 84301 4063 84335 4097
-rect 36461 3723 36495 3825
-rect 320741 3723 320775 3893
-rect 326295 3825 326445 3859
-rect 32505 3315 32539 3621
-rect 320281 3519 320315 3689
-rect 329941 3519 329975 3757
-rect 353125 3655 353159 3825
-rect 535009 3383 535043 4097
-rect 102149 3111 102183 3281
-rect 111165 2907 111199 3077
-rect 354137 2975 354171 3145
-<< viali >>
-rect 287621 460377 287655 460411
-rect 287805 460377 287839 460411
-rect 582389 458269 582423 458303
-rect 283481 457589 283515 457623
-rect 283481 456841 283515 456875
-rect 377597 457453 377631 457487
-rect 379161 457453 379195 457487
-rect 402989 457453 403023 457487
-rect 379161 457249 379195 457283
-rect 388637 457317 388671 457351
-rect 388637 457113 388671 457147
-rect 402989 457045 403023 457079
-rect 403081 457317 403115 457351
-rect 403081 456909 403115 456943
-rect 377597 456773 377631 456807
-rect 288357 336685 288391 336719
-rect 301789 336685 301823 336719
-rect 288357 336549 288391 336583
-rect 310437 336617 310471 336651
-rect 310897 336617 310931 336651
-rect 301605 336549 301639 336583
-rect 301697 336549 301731 336583
-rect 293417 336413 293451 336447
-rect 268761 336141 268795 336175
-rect 268945 336141 268979 336175
-rect 382289 336549 382323 336583
-rect 378793 336481 378827 336515
-rect 301697 335869 301731 335903
-rect 376125 336277 376159 336311
-rect 378425 336209 378459 336243
-rect 378425 336073 378459 336107
-rect 293417 335597 293451 335631
-rect 372537 335801 372571 335835
-rect 376125 335801 376159 335835
-rect 382841 336481 382875 336515
-rect 382841 336277 382875 336311
-rect 383853 336413 383887 336447
-rect 387165 336413 387199 336447
-rect 382289 336141 382323 336175
-rect 378793 335733 378827 335767
-rect 372537 335529 372571 335563
-rect 390477 336413 390511 336447
-rect 390477 336073 390511 336107
-rect 391213 336141 391247 336175
-rect 383853 335325 383887 335359
-rect 387165 335325 387199 335359
-rect 387257 335325 387291 335359
-rect 391213 335325 391247 335359
-rect 413109 335597 413143 335631
-rect 413109 335325 413143 335359
-rect 387165 335121 387199 335155
-rect 407865 333897 407899 333931
-rect 407865 333421 407899 333455
-rect 582389 19805 582423 19839
-rect 258089 8109 258123 8143
-rect 258457 8109 258491 8143
-rect 258089 7973 258123 8007
-rect 258089 7837 258123 7871
-rect 84577 4097 84611 4131
-rect 535009 4097 535043 4131
-rect 84301 4029 84335 4063
-rect 320741 3893 320775 3927
-rect 36461 3825 36495 3859
-rect 326261 3825 326295 3859
-rect 326445 3825 326479 3859
-rect 353125 3825 353159 3859
-rect 36461 3689 36495 3723
-rect 320281 3689 320315 3723
-rect 320741 3689 320775 3723
-rect 329941 3757 329975 3791
-rect 32505 3621 32539 3655
-rect 320281 3485 320315 3519
-rect 353125 3621 353159 3655
-rect 329941 3485 329975 3519
-rect 535009 3349 535043 3383
-rect 32505 3281 32539 3315
-rect 102149 3281 102183 3315
-rect 354137 3145 354171 3179
-rect 102149 3077 102183 3111
-rect 111165 3077 111199 3111
-rect 354137 2941 354171 2975
-rect 111165 2873 111199 2907
-<< metal1 >>
-rect 313182 700952 313188 701004
-rect 313240 700992 313246 701004
-rect 462314 700992 462320 701004
-rect 313240 700964 462320 700992
-rect 313240 700952 313246 700964
-rect 462314 700952 462320 700964
-rect 462372 700952 462378 701004
-rect 315942 700884 315948 700936
-rect 316000 700924 316006 700936
-rect 478506 700924 478512 700936
-rect 316000 700896 478512 700924
-rect 316000 700884 316006 700896
-rect 478506 700884 478512 700896
-rect 478564 700884 478570 700936
-rect 154114 700816 154120 700868
-rect 154172 700856 154178 700868
-rect 338114 700856 338120 700868
-rect 154172 700828 338120 700856
-rect 154172 700816 154178 700828
-rect 338114 700816 338120 700828
-rect 338172 700816 338178 700868
-rect 137830 700748 137836 700800
-rect 137888 700788 137894 700800
-rect 336734 700788 336740 700800
-rect 137888 700760 336740 700788
-rect 137888 700748 137894 700760
-rect 336734 700748 336740 700760
-rect 336792 700748 336798 700800
-rect 309042 700680 309048 700732
-rect 309100 700720 309106 700732
-rect 527174 700720 527180 700732
-rect 309100 700692 527180 700720
-rect 309100 700680 309106 700692
-rect 527174 700680 527180 700692
-rect 527232 700680 527238 700732
-rect 310422 700612 310428 700664
-rect 310480 700652 310486 700664
-rect 543458 700652 543464 700664
-rect 310480 700624 543464 700652
-rect 310480 700612 310486 700624
-rect 543458 700612 543464 700624
-rect 543516 700612 543522 700664
-rect 89162 700544 89168 700596
-rect 89220 700584 89226 700596
-rect 342254 700584 342260 700596
-rect 89220 700556 342260 700584
-rect 89220 700544 89226 700556
-rect 342254 700544 342260 700556
-rect 342312 700544 342318 700596
-rect 72970 700476 72976 700528
-rect 73028 700516 73034 700528
-rect 340874 700516 340880 700528
-rect 73028 700488 340880 700516
-rect 73028 700476 73034 700488
-rect 340874 700476 340880 700488
-rect 340932 700476 340938 700528
-rect 40494 700408 40500 700460
-rect 40552 700448 40558 700460
-rect 343634 700448 343640 700460
-rect 40552 700420 343640 700448
-rect 40552 700408 40558 700420
-rect 343634 700408 343640 700420
-rect 343692 700408 343698 700460
-rect 24302 700340 24308 700392
-rect 24360 700380 24366 700392
-rect 347866 700380 347872 700392
-rect 24360 700352 347872 700380
-rect 24360 700340 24366 700352
-rect 347866 700340 347872 700352
-rect 347924 700340 347930 700392
-rect 8110 700272 8116 700324
-rect 8168 700312 8174 700324
-rect 345014 700312 345020 700324
-rect 8168 700284 345020 700312
-rect 8168 700272 8174 700284
-rect 345014 700272 345020 700284
-rect 345072 700272 345078 700324
-rect 202782 700204 202788 700256
-rect 202840 700244 202846 700256
-rect 331306 700244 331312 700256
-rect 202840 700216 331312 700244
-rect 202840 700204 202846 700216
-rect 331306 700204 331312 700216
-rect 331364 700204 331370 700256
-rect 218974 700136 218980 700188
-rect 219032 700176 219038 700188
-rect 332594 700176 332600 700188
-rect 219032 700148 332600 700176
-rect 219032 700136 219038 700148
-rect 332594 700136 332600 700148
-rect 332652 700136 332658 700188
-rect 320082 700068 320088 700120
-rect 320140 700108 320146 700120
-rect 413646 700108 413652 700120
-rect 320140 700080 413652 700108
-rect 320140 700068 320146 700080
-rect 413646 700068 413652 700080
-rect 413704 700068 413710 700120
-rect 318702 700000 318708 700052
-rect 318760 700040 318766 700052
-rect 397454 700040 397460 700052
-rect 318760 700012 397460 700040
-rect 318760 700000 318766 700012
-rect 397454 700000 397460 700012
-rect 397512 700000 397518 700052
-rect 267642 699932 267648 699984
-rect 267700 699972 267706 699984
-rect 327074 699972 327080 699984
-rect 267700 699944 327080 699972
-rect 267700 699932 267706 699944
-rect 327074 699932 327080 699944
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-rect 328454 699904 328460 699916
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-rect 283892 699864 283898 699876
-rect 328454 699864 328460 699876
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-rect 324222 699796 324228 699848
-rect 324280 699836 324286 699848
-rect 348786 699836 348792 699848
-rect 324280 699808 348792 699836
-rect 324280 699796 324286 699808
-rect 348786 699796 348792 699808
-rect 348844 699796 348850 699848
-rect 322842 699728 322848 699780
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-rect 322900 699728 322906 699740
-rect 332502 699728 332508 699740
-rect 332560 699728 332566 699780
-rect 105446 699660 105452 699712
-rect 105504 699700 105510 699712
-rect 106182 699700 106188 699712
-rect 105504 699672 106188 699700
-rect 105504 699660 105510 699672
-rect 106182 699660 106188 699672
-rect 106240 699660 106246 699712
-rect 170306 699660 170312 699712
-rect 170364 699700 170370 699712
-rect 171042 699700 171048 699712
-rect 170364 699672 171048 699700
-rect 170364 699660 170370 699672
-rect 171042 699660 171048 699672
-rect 171100 699660 171106 699712
-rect 235166 699660 235172 699712
-rect 235224 699700 235230 699712
-rect 235902 699700 235908 699712
-rect 235224 699672 235908 699700
-rect 235224 699660 235230 699672
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-rect 235960 699660 235966 699712
-rect 300118 699660 300124 699712
-rect 300176 699700 300182 699712
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-rect 300176 699672 300768 699700
-rect 300176 699660 300182 699672
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-rect 300820 699660 300826 699712
-rect 304902 696940 304908 696992
-rect 304960 696980 304966 696992
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-rect 304960 696940 304966 696952
-rect 580166 696940 580172 696952
-rect 580224 696940 580230 696992
-rect 306282 683204 306288 683256
-rect 306340 683244 306346 683256
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-rect 306340 683204 306346 683216
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-rect 580224 683204 580230 683256
-rect 3418 683136 3424 683188
-rect 3476 683176 3482 683188
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-rect 3476 683148 349160 683176
-rect 3476 683136 3482 683148
-rect 349154 683136 349160 683148
-rect 349212 683136 349218 683188
-rect 302142 670760 302148 670812
-rect 302200 670800 302206 670812
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-rect 302200 670772 580172 670800
-rect 302200 670760 302206 670772
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-rect 580224 670760 580230 670812
-rect 3510 670692 3516 670744
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-rect 351914 670732 351920 670744
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-rect 3568 670692 3574 670704
-rect 351914 670692 351920 670704
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-rect 3418 656888 3424 656940
-rect 3476 656928 3482 656940
-rect 350534 656928 350540 656940
-rect 3476 656900 350540 656928
-rect 3476 656888 3482 656900
-rect 350534 656888 350540 656900
-rect 350592 656888 350598 656940
-rect 299382 643084 299388 643136
-rect 299440 643124 299446 643136
-rect 580166 643124 580172 643136
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-rect 580166 643084 580172 643096
-rect 580224 643084 580230 643136
-rect 3418 632068 3424 632120
-rect 3476 632108 3482 632120
-rect 353294 632108 353300 632120
-rect 3476 632080 353300 632108
-rect 3476 632068 3482 632080
-rect 353294 632068 353300 632080
-rect 353352 632068 353358 632120
-rect 300670 630640 300676 630692
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-rect 300728 630652 580172 630680
-rect 300728 630640 300734 630652
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-rect 3142 618264 3148 618316
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-rect 3200 618276 356060 618304
-rect 3200 618264 3206 618276
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-rect 356112 618264 356118 618316
-rect 298002 616836 298008 616888
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-rect 298060 616848 580172 616876
-rect 298060 616836 298066 616848
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-rect 3234 605820 3240 605872
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-rect 3292 605832 354680 605860
-rect 3292 605820 3298 605832
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-rect 295242 590656 295248 590708
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-rect 295300 590668 579804 590696
-rect 295300 590656 295306 590668
-rect 579798 590656 579804 590668
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-rect 3326 579640 3332 579692
-rect 3384 579680 3390 579692
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-rect 3384 579652 358820 579680
-rect 3384 579640 3390 579652
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-rect 296622 576852 296628 576904
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-rect 580166 576852 580172 576864
-rect 580224 576852 580230 576904
-rect 3418 565836 3424 565888
-rect 3476 565876 3482 565888
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-rect 3476 565836 3482 565848
-rect 361574 565836 361580 565848
-rect 361632 565836 361638 565888
-rect 293862 563048 293868 563100
-rect 293920 563088 293926 563100
-rect 579798 563088 579804 563100
-rect 293920 563060 579804 563088
-rect 293920 563048 293926 563060
-rect 579798 563048 579804 563060
-rect 579856 563048 579862 563100
-rect 3418 553392 3424 553444
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-rect 3476 553404 360200 553432
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-rect 289722 536800 289728 536852
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-rect 580166 536840 580172 536852
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-rect 289780 536800 289786 536812
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-rect 580224 536800 580230 536852
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-rect 3476 527156 362960 527184
-rect 3476 527144 3482 527156
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-rect 291102 524424 291108 524476
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-rect 291160 524436 580172 524464
-rect 291160 524424 291166 524436
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-rect 3476 514808 3482 514820
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-rect 3476 514780 365720 514808
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-rect 288342 510620 288348 510672
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-rect 364426 500964 364432 500976
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-rect 285640 484412 285646 484424
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-rect 3476 474728 368020 474756
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-rect 286962 470568 286968 470620
-rect 287020 470608 287026 470620
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-rect 287020 470580 579988 470608
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-rect 3234 462340 3240 462392
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-rect 371234 462340 371240 462352
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-rect 285030 460776 285036 460828
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-rect 287609 460377 287621 460380
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-rect 287793 460411 287851 460417
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-rect 287793 460371 287851 460377
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-rect 106182 460232 106188 460284
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-rect 399720 459824 399726 459876
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-rect 233970 458668 233976 458720
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-rect 270402 458600 270408 458652
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-rect 401284 458464 401290 458516
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-rect 239214 458260 239220 458312
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-rect 3418 458192 3424 458244
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-rect 3476 458204 373126 458232
-rect 3476 458192 3482 458204
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-rect 278682 457580 278688 457632
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-rect 283427 457592 283472 457620
-rect 278740 457580 278746 457592
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-rect 224218 457444 224224 457496
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-rect 377640 457444 377646 457496
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-rect 275554 457376 275560 457428
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-rect 425698 457416 425704 457428
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-rect 232590 457308 232596 457360
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-rect 379149 457280 379161 457283
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-rect 215996 457240 216002 457252
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-rect 379195 457249 379207 457283
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-rect 226978 457172 226984 457224
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-rect 93118 333344 93124 333396
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-rect 117648 2808 120120 2836
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-<< via1 >>
-rect 313188 700952 313240 701004
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-<< metal2 >>
-rect 8086 703520 8198 704960
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-rect 87984 480 88012 3334
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-rect 542 -960 654 480
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-rect 146208 333532 146260 333538
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-rect 140014 -960 140126 480
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-rect 205100 480 205128 598
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-rect 205560 490 205588 334426
-rect 206296 45558 206324 456962
-rect 209056 137970 209084 458390
-rect 213184 335912 213236 335918
-rect 213184 335854 213236 335860
-rect 209688 333940 209740 333946
-rect 209688 333882 209740 333888
-rect 209044 137964 209096 137970
-rect 209044 137906 209096 137912
-rect 206284 45552 206336 45558
-rect 206284 45494 206336 45500
-rect 206192 9580 206244 9586
-rect 206192 9522 206244 9528
-rect 201470 -960 201582 480
-rect 202666 -960 202778 480
-rect 203862 -960 203974 480
-rect 205058 -960 205170 480
-rect 205284 462 205588 490
-rect 206204 480 206232 9522
-rect 209700 6914 209728 333882
-rect 213196 12238 213224 335854
-rect 213288 293962 213316 458526
-rect 215944 457292 215996 457298
-rect 215944 457234 215996 457240
-rect 214656 457156 214708 457162
-rect 214656 457098 214708 457104
-rect 214564 335980 214616 335986
-rect 214564 335922 214616 335928
-rect 213276 293956 213328 293962
-rect 213276 293898 213328 293904
-rect 213184 12232 213236 12238
-rect 213184 12174 213236 12180
-rect 209780 9648 209832 9654
-rect 209780 9590 209832 9596
-rect 209056 6886 209728 6914
-rect 207388 5296 207440 5302
-rect 207388 5238 207440 5244
-rect 207400 480 207428 5238
-rect 208596 598 208808 626
-rect 208596 480 208624 598
-rect 208780 490 208808 598
-rect 209056 490 209084 6886
-rect 206162 -960 206274 480
-rect 207358 -960 207470 480
-rect 208554 -960 208666 480
-rect 208780 462 209084 490
-rect 209792 480 209820 9590
-rect 213368 8900 213420 8906
-rect 213368 8842 213420 8848
-rect 210976 5364 211028 5370
-rect 210976 5306 211028 5312
-rect 210988 480 211016 5306
-rect 212172 4208 212224 4214
-rect 212172 4150 212224 4156
-rect 212184 480 212212 4150
-rect 213380 480 213408 8842
-rect 214576 6914 214604 335922
-rect 214668 241466 214696 457098
-rect 215956 346390 215984 457234
-rect 220084 457088 220136 457094
-rect 220084 457030 220136 457036
-rect 215944 346384 215996 346390
-rect 215944 346326 215996 346332
-rect 215944 335844 215996 335850
-rect 215944 335786 215996 335792
-rect 214656 241460 214708 241466
-rect 214656 241402 214708 241408
-rect 214300 6886 214604 6914
-rect 214300 4214 214328 6886
-rect 215956 5506 215984 335786
-rect 216588 334416 216640 334422
-rect 216588 334358 216640 334364
-rect 216600 6914 216628 334358
-rect 219256 333192 219308 333198
-rect 219256 333134 219308 333140
-rect 216864 8832 216916 8838
-rect 216864 8774 216916 8780
-rect 216048 6886 216628 6914
-rect 215944 5500 215996 5506
-rect 215944 5442 215996 5448
-rect 214472 5432 214524 5438
-rect 214472 5374 214524 5380
-rect 214288 4208 214340 4214
-rect 214288 4150 214340 4156
-rect 214484 480 214512 5374
-rect 216048 3482 216076 6886
-rect 215680 3454 216076 3482
-rect 215680 480 215708 3454
-rect 216876 480 216904 8774
-rect 218060 5500 218112 5506
-rect 218060 5442 218112 5448
-rect 218072 480 218100 5442
-rect 219268 480 219296 333134
-rect 220096 71738 220124 457030
-rect 222856 398818 222884 458730
-rect 228364 458516 228416 458522
-rect 228364 458458 228416 458464
-rect 224224 457496 224276 457502
-rect 224224 457438 224276 457444
-rect 224236 449886 224264 457438
-rect 226984 457224 227036 457230
-rect 226984 457166 227036 457172
-rect 224224 449880 224276 449886
-rect 224224 449822 224276 449828
-rect 222844 398812 222896 398818
-rect 222844 398754 222896 398760
-rect 224224 335776 224276 335782
-rect 224224 335718 224276 335724
-rect 222844 335708 222896 335714
-rect 222844 335650 222896 335656
-rect 220084 71732 220136 71738
-rect 220084 71674 220136 71680
-rect 220452 8764 220504 8770
-rect 220452 8706 220504 8712
-rect 220464 480 220492 8706
-rect 221556 4752 221608 4758
-rect 221556 4694 221608 4700
-rect 221568 480 221596 4694
-rect 222856 4690 222884 335650
-rect 223488 334348 223540 334354
-rect 223488 334290 223540 334296
-rect 223500 6914 223528 334290
-rect 224236 12034 224264 335718
-rect 226996 164218 227024 457166
-rect 227628 333124 227680 333130
-rect 227628 333066 227680 333072
-rect 226984 164212 227036 164218
-rect 226984 164154 227036 164160
-rect 224224 12028 224276 12034
-rect 224224 11970 224276 11976
-rect 223948 8696 224000 8702
-rect 223948 8638 224000 8644
-rect 223224 6886 223528 6914
-rect 222844 4684 222896 4690
-rect 222844 4626 222896 4632
-rect 222764 598 222976 626
-rect 222764 480 222792 598
-rect 222948 490 222976 598
-rect 223224 490 223252 6886
-rect 209750 -960 209862 480
-rect 210946 -960 211058 480
-rect 212142 -960 212254 480
-rect 213338 -960 213450 480
-rect 214442 -960 214554 480
-rect 215638 -960 215750 480
-rect 216834 -960 216946 480
-rect 218030 -960 218142 480
-rect 219226 -960 219338 480
-rect 220422 -960 220534 480
-rect 221526 -960 221638 480
-rect 222722 -960 222834 480
-rect 222948 462 223252 490
-rect 223960 480 223988 8638
-rect 227536 8628 227588 8634
-rect 227536 8570 227588 8576
-rect 225144 4684 225196 4690
-rect 225144 4626 225196 4632
-rect 225156 480 225184 4626
-rect 226340 4208 226392 4214
-rect 226340 4150 226392 4156
-rect 226352 480 226380 4150
-rect 227548 480 227576 8570
-rect 227640 4214 227668 333066
-rect 228376 111790 228404 458458
-rect 231124 335640 231176 335646
-rect 231124 335582 231176 335588
-rect 228364 111784 228416 111790
-rect 228364 111726 228416 111732
-rect 231136 12102 231164 335582
-rect 231228 320142 231256 458866
-rect 233976 458720 234028 458726
-rect 233976 458662 234028 458668
-rect 232596 457360 232648 457366
-rect 232596 457302 232648 457308
-rect 232504 335572 232556 335578
-rect 232504 335514 232556 335520
-rect 231216 320136 231268 320142
-rect 231216 320078 231268 320084
-rect 232516 12170 232544 335514
-rect 232608 267714 232636 457302
-rect 233884 335436 233936 335442
-rect 233884 335378 233936 335384
-rect 232596 267708 232648 267714
-rect 232596 267650 232648 267656
-rect 232504 12164 232556 12170
-rect 232504 12106 232556 12112
-rect 231124 12096 231176 12102
-rect 231124 12038 231176 12044
-rect 233896 11966 233924 335378
-rect 233988 215286 234016 458662
-rect 239220 458312 239272 458318
-rect 239220 458254 239272 458260
-rect 239232 457994 239260 458254
-rect 255056 457994 255084 459546
-rect 260208 458862 260236 459546
-rect 260196 458856 260248 458862
-rect 260196 458798 260248 458804
-rect 270408 458652 270460 458658
-rect 270408 458594 270460 458600
-rect 238924 457966 239260 457994
-rect 254748 457966 255084 457994
-rect 270420 457994 270448 458594
-rect 272352 457994 272380 460022
-rect 273996 458992 274048 458998
-rect 273996 458934 274048 458940
-rect 274008 457994 274036 458934
-rect 277044 457994 277072 460090
-rect 280080 457994 280108 460498
-rect 281816 460488 281868 460494
-rect 281816 460430 281868 460436
-rect 281828 457994 281856 460430
-rect 285048 457994 285076 460770
-rect 286704 457994 286732 466426
-rect 288268 457994 288296 466426
-rect 289740 457994 289768 536794
-rect 291108 524476 291160 524482
-rect 291108 524418 291160 524424
-rect 291120 457994 291148 524418
-rect 293880 459610 293908 563042
-rect 295260 459610 295288 590650
-rect 296628 576904 296680 576910
-rect 296628 576846 296680 576852
-rect 296640 459610 296668 576846
-rect 298020 460934 298048 616830
-rect 299400 460934 299428 643078
-rect 300676 630692 300728 630698
-rect 300676 630634 300728 630640
-rect 297744 460906 298048 460934
-rect 299308 460906 299428 460934
-rect 292948 459604 293000 459610
-rect 292948 459546 293000 459552
-rect 293868 459604 293920 459610
-rect 293868 459546 293920 459552
-rect 294512 459604 294564 459610
-rect 294512 459546 294564 459552
-rect 295248 459604 295300 459610
-rect 295248 459546 295300 459552
-rect 296076 459604 296128 459610
-rect 296076 459546 296128 459552
-rect 296628 459604 296680 459610
-rect 296628 459546 296680 459552
-rect 292960 457994 292988 459546
-rect 294524 457994 294552 459546
-rect 296088 457994 296116 459546
-rect 297744 457994 297772 460906
-rect 299308 457994 299336 460906
-rect 300688 457994 300716 630634
-rect 300780 460834 300808 699654
-rect 304908 696992 304960 696998
-rect 304908 696934 304960 696940
-rect 302148 670812 302200 670818
-rect 302148 670754 302200 670760
-rect 300768 460828 300820 460834
-rect 300768 460770 300820 460776
-rect 302160 458266 302188 670754
-rect 304920 459610 304948 696934
-rect 306288 683256 306340 683262
-rect 306288 683198 306340 683204
-rect 306300 459610 306328 683198
-rect 309060 460934 309088 700674
-rect 310428 700664 310480 700670
-rect 310428 700606 310480 700612
-rect 310440 460934 310468 700606
-rect 308784 460906 309088 460934
-rect 310348 460906 310468 460934
-rect 307116 460216 307168 460222
-rect 307116 460158 307168 460164
-rect 303988 459604 304040 459610
-rect 303988 459546 304040 459552
-rect 304908 459604 304960 459610
-rect 304908 459546 304960 459552
-rect 305552 459604 305604 459610
-rect 305552 459546 305604 459552
-rect 306288 459604 306340 459610
-rect 306288 459546 306340 459552
-rect 270420 457966 270480 457994
-rect 272044 457966 272380 457994
-rect 273700 457966 274036 457994
-rect 276828 457966 277072 457994
-rect 279956 457966 280108 457994
-rect 281520 457966 281856 457994
-rect 284740 457966 285076 457994
-rect 286304 457966 286732 457994
-rect 287868 457966 288296 457994
-rect 289432 457966 289768 457994
-rect 290996 457966 291148 457994
-rect 292652 457966 292988 457994
-rect 294216 457966 294552 457994
-rect 295780 457966 296116 457994
-rect 297344 457966 297772 457994
-rect 298908 457966 299336 457994
-rect 300472 457966 300716 457994
-rect 302114 458238 302188 458266
-rect 302114 457980 302142 458238
-rect 304000 457994 304028 459546
-rect 305564 457994 305592 459546
-rect 307128 457994 307156 460158
-rect 308784 457994 308812 460906
-rect 310348 457994 310376 460906
-rect 311808 460352 311860 460358
-rect 311808 460294 311860 460300
-rect 311820 457994 311848 460294
-rect 313200 458266 313228 700946
-rect 315948 700936 316000 700942
-rect 315948 700878 316000 700884
-rect 315960 459610 315988 700878
-rect 331312 700256 331364 700262
-rect 331312 700198 331364 700204
-rect 320088 700120 320140 700126
-rect 320088 700062 320140 700068
-rect 318708 700052 318760 700058
-rect 318708 699994 318760 700000
-rect 316592 460624 316644 460630
-rect 316592 460566 316644 460572
-rect 315028 459604 315080 459610
-rect 315028 459546 315080 459552
-rect 315948 459604 316000 459610
-rect 315948 459546 316000 459552
-rect 303692 457966 304028 457994
-rect 305256 457966 305592 457994
-rect 306820 457966 307156 457994
-rect 308384 457966 308812 457994
-rect 309948 457966 310376 457994
-rect 311604 457966 311848 457994
-rect 313154 458238 313228 458266
-rect 313154 457980 313182 458238
-rect 315040 457994 315068 459546
-rect 316604 457994 316632 460566
-rect 318720 459610 318748 699994
-rect 320100 460934 320128 700062
-rect 327080 699984 327132 699990
-rect 327080 699926 327132 699932
-rect 324228 699848 324280 699854
-rect 324228 699790 324280 699796
-rect 322848 699780 322900 699786
-rect 322848 699722 322900 699728
-rect 319824 460906 320128 460934
-rect 317972 459604 318024 459610
-rect 317972 459546 318024 459552
-rect 318708 459604 318760 459610
-rect 318708 459546 318760 459552
-rect 317984 457994 318012 459546
-rect 319824 457994 319852 460906
-rect 321376 460760 321428 460766
-rect 321376 460702 321428 460708
-rect 321388 457994 321416 460702
-rect 322860 457994 322888 699722
-rect 324240 458266 324268 699790
-rect 325700 460828 325752 460834
-rect 325700 460770 325752 460776
-rect 314732 457966 315068 457994
-rect 316296 457966 316632 457994
-rect 317860 457966 318012 457994
-rect 319424 457966 319852 457994
-rect 321080 457966 321416 457994
-rect 322644 457966 322888 457994
-rect 324194 458238 324268 458266
-rect 324194 457980 324222 458238
-rect 325712 457994 325740 460770
-rect 327092 457994 327120 699926
-rect 328460 699916 328512 699922
-rect 328460 699858 328512 699864
-rect 328472 457994 328500 699858
-rect 331324 480254 331352 700198
-rect 332520 699786 332548 703520
-rect 338120 700868 338172 700874
-rect 338120 700810 338172 700816
-rect 336740 700800 336792 700806
-rect 336740 700742 336792 700748
-rect 332600 700188 332652 700194
-rect 332600 700130 332652 700136
-rect 332508 699780 332560 699786
-rect 332508 699722 332560 699728
-rect 332612 480254 332640 700130
-rect 331324 480226 331720 480254
-rect 332612 480226 333284 480254
-rect 330208 460692 330260 460698
-rect 330208 460634 330260 460640
-rect 330220 457994 330248 460634
-rect 331692 457994 331720 480226
-rect 333256 457994 333284 480226
-rect 334900 460420 334952 460426
-rect 334900 460362 334952 460368
-rect 334912 457994 334940 460362
-rect 336752 457994 336780 700742
-rect 338132 457994 338160 700810
-rect 342260 700596 342312 700602
-rect 342260 700538 342312 700544
-rect 340880 700528 340932 700534
-rect 340880 700470 340932 700476
-rect 340892 480254 340920 700470
-rect 342272 480254 342300 700538
-rect 343640 700460 343692 700466
-rect 343640 700402 343692 700408
-rect 343652 480254 343680 700402
-rect 347872 700392 347924 700398
-rect 347872 700334 347924 700340
-rect 345020 700324 345072 700330
-rect 345020 700266 345072 700272
-rect 345032 480254 345060 700266
-rect 340892 480226 341196 480254
-rect 342272 480226 342760 480254
-rect 343652 480226 344324 480254
-rect 345032 480226 345888 480254
-rect 339684 460284 339736 460290
-rect 339684 460226 339736 460232
-rect 339696 457994 339724 460226
-rect 341168 457994 341196 480226
-rect 342732 457994 342760 480226
-rect 344296 457994 344324 480226
-rect 345860 457994 345888 480226
-rect 347884 458266 347912 700334
-rect 348804 699854 348832 703520
-rect 364996 702434 365024 703520
-rect 364352 702406 365024 702434
-rect 348792 699848 348844 699854
-rect 348792 699790 348844 699796
-rect 349160 683188 349212 683194
-rect 349160 683130 349212 683136
-rect 347838 458238 347912 458266
-rect 325712 457966 325772 457994
-rect 327092 457966 327336 457994
-rect 328472 457966 328900 457994
-rect 330220 457966 330556 457994
-rect 331692 457966 332120 457994
-rect 333256 457966 333684 457994
-rect 334912 457966 335248 457994
-rect 336752 457966 336812 457994
-rect 338132 457966 338376 457994
-rect 339696 457966 340032 457994
-rect 341168 457966 341596 457994
-rect 342732 457966 343160 457994
-rect 344296 457966 344724 457994
-rect 345860 457966 346288 457994
-rect 347838 457980 347866 458238
-rect 349172 457994 349200 683130
-rect 351920 670744 351972 670750
-rect 351920 670686 351972 670692
-rect 350540 656940 350592 656946
-rect 350540 656882 350592 656888
-rect 350552 480254 350580 656882
-rect 351932 480254 351960 670686
-rect 353300 632120 353352 632126
-rect 353300 632062 353352 632068
-rect 353312 480254 353340 632062
-rect 356060 618316 356112 618322
-rect 356060 618258 356112 618264
-rect 354680 605872 354732 605878
-rect 354680 605814 354732 605820
-rect 354692 480254 354720 605814
-rect 356072 480254 356100 618258
-rect 358820 579692 358872 579698
-rect 358820 579634 358872 579640
-rect 350552 480226 350672 480254
-rect 351932 480226 352236 480254
-rect 353312 480226 353800 480254
-rect 354692 480226 355364 480254
-rect 356072 480226 356928 480254
-rect 350644 457994 350672 480226
-rect 352208 457994 352236 480226
-rect 353772 457994 353800 480226
-rect 355336 457994 355364 480226
-rect 356900 457994 356928 480226
-rect 358832 457994 358860 579634
-rect 361580 565888 361632 565894
-rect 361580 565830 361632 565836
-rect 360200 553444 360252 553450
-rect 360200 553386 360252 553392
-rect 360212 457994 360240 553386
-rect 361592 480254 361620 565830
-rect 362960 527196 363012 527202
-rect 362960 527138 363012 527144
-rect 362972 480254 363000 527138
-rect 361592 480226 361712 480254
-rect 362972 480226 363276 480254
-rect 361684 457994 361712 480226
-rect 363248 457994 363276 480226
-rect 364352 460766 364380 702406
-rect 397472 700058 397500 703520
-rect 413664 700126 413692 703520
-rect 413652 700120 413704 700126
-rect 413652 700062 413704 700068
-rect 397460 700052 397512 700058
-rect 397460 699994 397512 700000
-rect 365720 514820 365772 514826
-rect 365720 514762 365772 514768
-rect 364432 501016 364484 501022
-rect 364432 500958 364484 500964
-rect 364444 480254 364472 500958
-rect 365732 480254 365760 514762
-rect 364444 480226 364840 480254
-rect 365732 480226 366404 480254
-rect 364340 460760 364392 460766
-rect 364340 460702 364392 460708
-rect 364812 457994 364840 480226
-rect 366376 457994 366404 480226
-rect 368020 474768 368072 474774
-rect 368020 474710 368072 474716
-rect 368032 457994 368060 474710
-rect 371240 462392 371292 462398
-rect 371240 462334 371292 462340
-rect 371252 457994 371280 462334
-rect 394884 460896 394936 460902
-rect 394884 460838 394936 460844
-rect 375932 460012 375984 460018
-rect 375932 459954 375984 459960
-rect 374368 458788 374420 458794
-rect 374368 458730 374420 458736
-rect 373126 458244 373178 458250
-rect 373126 458186 373178 458192
-rect 349172 457966 349508 457994
-rect 350644 457966 351072 457994
-rect 352208 457966 352636 457994
-rect 353772 457966 354200 457994
-rect 355336 457966 355764 457994
-rect 356900 457966 357328 457994
-rect 358832 457966 358984 457994
-rect 360212 457966 360548 457994
-rect 361684 457966 362112 457994
-rect 363248 457966 363676 457994
-rect 364812 457966 365240 457994
-rect 366376 457966 366804 457994
-rect 368032 457966 368460 457994
-rect 371252 457966 371588 457994
-rect 373138 457980 373166 458186
-rect 374380 457994 374408 458730
-rect 375944 457994 375972 459954
-rect 390192 459944 390244 459950
-rect 390192 459886 390244 459892
-rect 380900 459808 380952 459814
-rect 380900 459750 380952 459756
-rect 380912 457994 380940 459750
-rect 385408 459740 385460 459746
-rect 385408 459682 385460 459688
-rect 382280 458924 382332 458930
-rect 382280 458866 382332 458872
-rect 382292 457994 382320 458866
-rect 383936 458584 383988 458590
-rect 383936 458526 383988 458532
-rect 383948 457994 383976 458526
-rect 385420 457994 385448 459682
-rect 390204 457994 390232 459886
-rect 391940 458720 391992 458726
-rect 391940 458662 391992 458668
-rect 391952 457994 391980 458662
-rect 393504 458380 393556 458386
-rect 393504 458322 393556 458328
-rect 393516 457994 393544 458322
-rect 394896 457994 394924 460838
-rect 429212 460630 429240 703582
-rect 429672 703474 429700 703582
-rect 429814 703520 429926 704960
-rect 446098 703520 446210 704960
-rect 462290 703520 462402 704960
-rect 478482 703520 478594 704960
-rect 494072 703582 494652 703610
-rect 429856 703474 429884 703520
-rect 429672 703446 429884 703474
-rect 462332 701010 462360 703520
-rect 462320 701004 462372 701010
-rect 462320 700946 462372 700952
-rect 478524 700942 478552 703520
-rect 478512 700936 478564 700942
-rect 478512 700878 478564 700884
-rect 429200 460624 429252 460630
-rect 429200 460566 429252 460572
-rect 417424 460556 417476 460562
-rect 417424 460498 417476 460504
-rect 399668 459876 399720 459882
-rect 399668 459818 399720 459824
-rect 398104 458448 398156 458454
-rect 398104 458390 398156 458396
-rect 398116 457994 398144 458390
-rect 399680 457994 399708 459818
-rect 404360 459672 404412 459678
-rect 404360 459614 404412 459620
-rect 401232 458516 401284 458522
-rect 401232 458458 401284 458464
-rect 401244 457994 401272 458458
-rect 404372 457994 404400 459614
-rect 374380 457966 374716 457994
-rect 375944 457966 376280 457994
-rect 380912 457966 381064 457994
-rect 382292 457966 382628 457994
-rect 383948 457966 384192 457994
-rect 385420 457966 385756 457994
-rect 390204 457966 390540 457994
-rect 391952 457966 392104 457994
-rect 393516 457966 393668 457994
-rect 394896 457966 395232 457994
-rect 398116 457966 398452 457994
-rect 399680 457966 400016 457994
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-rect 404372 457966 404708 457994
-rect 278688 457632 278740 457638
-rect 278392 457580 278688 457586
-rect 283472 457632 283524 457638
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-rect 283176 457580 283472 457586
-rect 283176 457574 283524 457580
-rect 278392 457558 278728 457574
-rect 283176 457558 283512 457574
-rect 369860 457496 369912 457502
-rect 275264 457434 275600 457450
-rect 377588 457496 377640 457502
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-rect 369860 457438 370024 457444
-rect 379152 457496 379204 457502
-rect 377640 457444 377936 457450
-rect 377588 457438 377936 457444
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-rect 379204 457444 379500 457450
-rect 379152 457438 379500 457444
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-rect 406016 457438 406364 457444
-rect 275264 457428 275612 457434
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-rect 369872 457422 370024 457438
-rect 377600 457422 377936 457438
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-rect 406028 457422 406364 457438
-rect 275560 457370 275612 457376
-rect 387064 457360 387116 457366
-rect 237194 457328 237250 457337
-rect 234632 457286 235796 457314
-rect 233976 215280 234028 215286
-rect 233976 215222 234028 215228
-rect 233884 11960 233936 11966
-rect 233884 11902 233936 11908
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-rect 231032 8502 231084 8508
-rect 229836 7132 229888 7138
-rect 229836 7074 229888 7080
-rect 228732 4616 228784 4622
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-rect 227628 4208 227680 4214
-rect 227628 4150 227680 4156
-rect 228744 480 228772 4558
-rect 229848 480 229876 7074
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-rect 233424 7064 233476 7070
-rect 233424 7006 233476 7012
-rect 232228 4548 232280 4554
-rect 232228 4490 232280 4496
-rect 232240 480 232268 4490
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-rect 234632 6866 234660 457286
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-rect 240488 457286 240782 457314
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-rect 245474 457328 245530 457337
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-rect 243910 457263 243966 457272
-rect 246946 457328 247002 457337
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-rect 248234 457328 248290 457337
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-rect 251822 457328 251878 457337
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-rect 256514 457263 256570 457272
-rect 257526 457328 257582 457337
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-rect 259274 457263 259330 457272
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-rect 264518 457328 264574 457337
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-rect 262862 457263 262918 457272
-rect 266082 457328 266138 457337
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-rect 264518 457263 264574 457272
-rect 267554 457328 267610 457337
-rect 267352 457286 267554 457314
-rect 266082 457263 266138 457272
-rect 269026 457328 269082 457337
-rect 268916 457286 269026 457314
-rect 267554 457263 267610 457272
-rect 388628 457360 388680 457366
-rect 387116 457308 387412 457314
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-rect 388680 457308 388976 457314
-rect 388628 457302 388976 457308
-rect 402980 457360 403032 457366
-rect 396592 457308 396888 457314
-rect 396540 457302 396888 457308
-rect 407580 457360 407632 457366
-rect 403032 457308 403144 457314
-rect 402980 457302 403144 457308
-rect 409142 457328 409198 457337
-rect 407632 457308 407928 457314
-rect 407580 457302 407928 457308
-rect 387076 457286 387412 457302
-rect 388640 457286 388976 457302
-rect 396552 457286 396888 457302
-rect 402992 457286 403144 457302
-rect 407592 457286 407928 457302
-rect 269026 457263 269082 457272
-rect 410706 457328 410762 457337
-rect 409198 457286 409492 457314
-rect 409142 457263 409198 457272
-rect 412270 457328 412326 457337
-rect 410762 457286 411056 457314
-rect 410706 457263 410762 457272
-rect 412326 457286 412620 457314
-rect 414184 457286 414980 457314
-rect 412270 457263 412326 457272
-rect 234908 338014 235152 338042
-rect 235276 338014 235428 338042
-rect 235552 338014 235796 338042
-rect 234804 330472 234856 330478
-rect 234804 330414 234856 330420
-rect 234712 330404 234764 330410
-rect 234712 330346 234764 330352
-rect 234620 6860 234672 6866
-rect 234620 6802 234672 6808
-rect 234724 4962 234752 330346
-rect 234712 4956 234764 4962
-rect 234712 4898 234764 4904
-rect 234816 4894 234844 330414
-rect 234804 4888 234856 4894
-rect 234804 4830 234856 4836
-rect 234908 4826 234936 338014
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-rect 235264 330472 235316 330478
-rect 235264 330414 235316 330420
-rect 235552 330410 235580 338014
-rect 236150 337770 236178 338028
-rect 236288 338014 236532 338042
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-rect 237024 338014 237268 338042
-rect 237484 338014 237636 338042
-rect 237760 338014 238004 338042
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-rect 236150 337742 236224 337770
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-rect 235540 330404 235592 330410
-rect 235540 330346 235592 330352
-rect 234988 8492 235040 8498
-rect 234988 8434 235040 8440
-rect 234896 4820 234948 4826
-rect 234896 4762 234948 4768
-rect 235000 3482 235028 8434
-rect 236104 5030 236132 330414
-rect 236196 7614 236224 337742
-rect 236288 336025 236316 338014
-rect 236274 336016 236330 336025
-rect 236274 335951 236330 335960
-rect 236656 316034 236684 338014
-rect 237024 330478 237052 338014
-rect 237380 335504 237432 335510
-rect 237380 335446 237432 335452
-rect 237392 334286 237420 335446
-rect 237380 334280 237432 334286
-rect 237380 334222 237432 334228
-rect 237012 330472 237064 330478
-rect 237012 330414 237064 330420
-rect 236288 316006 236684 316034
-rect 236184 7608 236236 7614
-rect 236184 7550 236236 7556
-rect 236092 5024 236144 5030
-rect 236092 4966 236144 4972
-rect 235816 4820 235868 4826
-rect 235816 4762 235868 4768
-rect 234632 3454 235028 3482
-rect 234632 480 234660 3454
-rect 235828 480 235856 4762
-rect 236288 3369 236316 316006
-rect 237484 8974 237512 338014
-rect 237760 336297 237788 338014
-rect 237746 336288 237802 336297
-rect 237746 336223 237802 336232
-rect 238128 336122 238156 338014
-rect 238116 336116 238168 336122
-rect 238116 336058 238168 336064
-rect 238496 316034 238524 338014
-rect 238864 334626 238892 338014
-rect 239232 335354 239260 338014
-rect 238956 335326 239260 335354
-rect 238852 334620 238904 334626
-rect 238852 334562 238904 334568
-rect 238956 330528 238984 335326
-rect 237576 316006 238524 316034
-rect 238864 330500 238984 330528
-rect 237472 8968 237524 8974
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-rect 237576 7682 237604 316006
-rect 238116 8968 238168 8974
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-rect 237564 7676 237616 7682
-rect 237564 7618 237616 7624
-rect 237012 7608 237064 7614
-rect 237012 7550 237064 7556
-rect 236274 3360 236330 3369
-rect 236274 3295 236330 3304
-rect 237024 480 237052 7550
-rect 238128 480 238156 8910
-rect 238864 3505 238892 330500
-rect 239600 316034 239628 338014
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-rect 238956 3641 238984 316006
-rect 240152 7750 240180 338014
-rect 240336 329118 240364 338014
-rect 240704 336161 240732 338014
-rect 241072 336433 241100 338014
-rect 241670 337770 241698 338028
-rect 241808 338014 242052 338042
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-rect 243096 338014 243156 338042
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-rect 245120 338014 245364 338042
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-rect 246592 338014 246836 338042
-rect 241670 337742 241744 337770
-rect 241058 336424 241114 336433
-rect 241058 336359 241114 336368
-rect 240690 336152 240746 336161
-rect 240690 336087 240746 336096
-rect 241612 330540 241664 330546
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-rect 240324 329112 240376 329118
-rect 240324 329054 240376 329060
-rect 240140 7744 240192 7750
-rect 240140 7686 240192 7692
-rect 240508 7676 240560 7682
-rect 240508 7618 240560 7624
-rect 239312 4888 239364 4894
-rect 239312 4830 239364 4836
-rect 238942 3632 238998 3641
-rect 238942 3567 238998 3576
-rect 238850 3496 238906 3505
-rect 238850 3431 238906 3440
-rect 239324 480 239352 4830
-rect 240520 480 240548 7618
-rect 241624 3466 241652 330482
-rect 241716 8514 241744 337742
-rect 241808 333266 241836 338014
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-rect 241796 333202 241848 333208
-rect 242176 316034 242204 338014
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-rect 242532 330482 242584 330488
-rect 242992 330540 243044 330546
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-rect 241808 316006 242204 316034
-rect 241808 16574 241836 316006
-rect 241808 16546 241928 16574
-rect 241716 8486 241836 8514
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-rect 241704 8366 241756 8372
-rect 241612 3460 241664 3466
-rect 241612 3402 241664 3408
-rect 241716 480 241744 8366
-rect 241808 7818 241836 8486
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-rect 241796 7754 241848 7760
-rect 241900 3777 241928 16546
-rect 243004 7954 243032 330482
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-rect 242992 7890 243044 7896
-rect 243096 7886 243124 338014
-rect 243280 334694 243308 338014
-rect 243648 336054 243676 338014
-rect 243636 336048 243688 336054
-rect 243636 335990 243688 335996
-rect 243268 334688 243320 334694
-rect 243268 334630 243320 334636
-rect 244016 330546 244044 338014
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-rect 244004 330482 244056 330488
-rect 244372 330540 244424 330546
-rect 244372 330482 244424 330488
-rect 244384 9042 244412 330482
-rect 244476 330478 244504 338014
-rect 244464 330472 244516 330478
-rect 244464 330414 244516 330420
-rect 244752 316034 244780 338014
-rect 245120 330546 245148 338014
-rect 245108 330540 245160 330546
-rect 245108 330482 245160 330488
-rect 245672 329254 245700 338014
-rect 245856 336190 245884 338014
-rect 245844 336184 245896 336190
-rect 245844 336126 245896 336132
-rect 245660 329248 245712 329254
-rect 245660 329190 245712 329196
-rect 246224 316034 246252 338014
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-rect 247098 337770 247126 338028
-rect 247236 338014 247480 338042
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-rect 247098 337742 247172 337770
-rect 247144 330546 247172 337742
-rect 247132 330540 247184 330546
-rect 247132 330482 247184 330488
-rect 246580 329180 246632 329186
-rect 246580 329122 246632 329128
-rect 247132 327412 247184 327418
-rect 247132 327354 247184 327360
-rect 244476 316006 244780 316034
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-rect 244372 9036 244424 9042
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-rect 243084 7880 243136 7886
-rect 243084 7822 243136 7828
-rect 244096 7744 244148 7750
-rect 244096 7686 244148 7692
-rect 242900 4956 242952 4962
-rect 242900 4898 242952 4904
-rect 241886 3768 241942 3777
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-rect 242912 480 242940 4898
-rect 244108 480 244136 7686
-rect 244476 3534 244504 316006
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-rect 245936 9104 245988 9110
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-rect 245200 9036 245252 9042
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-rect 244464 3528 244516 3534
-rect 244464 3470 244516 3476
-rect 245212 480 245240 8978
-rect 246396 5024 246448 5030
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-rect 246408 480 246436 4966
-rect 247144 3670 247172 327354
-rect 247236 10334 247264 338014
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-rect 247592 334756 247644 334762
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-rect 247316 330540 247368 330546
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-rect 247224 10328 247276 10334
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-rect 247132 3664 247184 3670
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-rect 247328 3602 247356 330482
-rect 247972 327418 248000 338014
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-rect 248708 338014 248952 338042
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-rect 248570 337742 248644 337770
-rect 248512 330540 248564 330546
-rect 248512 330482 248564 330488
-rect 247960 327412 248012 327418
-rect 247960 327354 248012 327360
-rect 247592 7812 247644 7818
-rect 247592 7754 247644 7760
-rect 247316 3596 247368 3602
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-rect 247604 480 247632 7754
-rect 248524 6186 248552 330482
-rect 248616 10402 248644 337742
-rect 248708 329322 248736 338014
-rect 248696 329316 248748 329322
-rect 248696 329258 248748 329264
-rect 249076 316034 249104 338014
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-rect 249892 330540 249944 330546
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-rect 248708 316006 249104 316034
-rect 248604 10396 248656 10402
-rect 248604 10338 248656 10344
-rect 248512 6180 248564 6186
-rect 248512 6122 248564 6128
-rect 248708 3738 248736 316006
-rect 249904 10538 249932 330482
-rect 249892 10532 249944 10538
-rect 249892 10474 249944 10480
-rect 249996 10470 250024 338014
-rect 250180 331906 250208 338014
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-rect 250168 331842 250220 331848
-rect 250548 316034 250576 338014
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-rect 251364 330608 251416 330614
-rect 251364 330550 251416 330556
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-rect 251272 330540 251324 330546
-rect 251272 330482 251324 330488
-rect 250088 316006 250576 316034
-rect 249984 10464 250036 10470
-rect 249984 10406 250036 10412
-rect 248788 9104 248840 9110
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-rect 248696 3732 248748 3738
-rect 248696 3674 248748 3680
-rect 248800 480 248828 9046
-rect 250088 6254 250116 316006
-rect 251088 12028 251140 12034
-rect 251088 11970 251140 11976
-rect 250076 6248 250128 6254
-rect 250076 6190 250128 6196
-rect 251100 3534 251128 11970
-rect 251284 10606 251312 330482
-rect 251652 316034 251680 338014
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-rect 252572 331974 252600 338014
-rect 252560 331968 252612 331974
-rect 252560 331910 252612 331916
-rect 252008 330540 252060 330546
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-rect 252652 330540 252704 330546
-rect 252652 330482 252704 330488
-rect 251376 316006 251680 316034
-rect 251272 10600 251324 10606
-rect 251272 10542 251324 10548
-rect 251180 7948 251232 7954
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-rect 249984 3528 250036 3534
-rect 249984 3470 250036 3476
-rect 251088 3528 251140 3534
-rect 251088 3470 251140 3476
-rect 249996 480 250024 3470
-rect 251192 480 251220 7890
-rect 251376 6322 251404 316006
-rect 252376 11960 252428 11966
-rect 252376 11902 252428 11908
-rect 251364 6316 251416 6322
-rect 251364 6258 251416 6264
-rect 252388 480 252416 11902
-rect 252664 10674 252692 330482
-rect 252652 10668 252704 10674
-rect 252652 10610 252704 10616
-rect 252848 6390 252876 338014
-rect 253124 330546 253152 338014
-rect 253112 330540 253164 330546
-rect 253112 330482 253164 330488
-rect 253492 329390 253520 338014
-rect 253940 330472 253992 330478
-rect 253940 330414 253992 330420
-rect 253480 329384 253532 329390
-rect 253480 329326 253532 329332
-rect 253848 10600 253900 10606
-rect 253848 10542 253900 10548
-rect 252836 6384 252888 6390
-rect 252836 6326 252888 6332
-rect 253492 598 253704 626
-rect 253492 480 253520 598
-rect 253676 490 253704 598
-rect 253860 490 253888 10542
-rect 253952 3806 253980 330414
-rect 254044 6458 254072 338014
-rect 254124 330540 254176 330546
-rect 254124 330482 254176 330488
-rect 254136 6526 254164 330482
-rect 254228 10742 254256 338014
-rect 254596 330478 254624 338014
-rect 254964 330546 254992 338014
-rect 254952 330540 255004 330546
-rect 254952 330482 255004 330488
-rect 255320 330540 255372 330546
-rect 255320 330482 255372 330488
-rect 254584 330472 254636 330478
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-rect 254216 10736 254268 10742
-rect 254216 10678 254268 10684
-rect 254676 7880 254728 7886
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-rect 254124 6520 254176 6526
-rect 254124 6462 254176 6468
-rect 254032 6452 254084 6458
-rect 254032 6394 254084 6400
-rect 253940 3800 253992 3806
-rect 253940 3742 253992 3748
-rect 223918 -960 224030 480
-rect 225114 -960 225226 480
-rect 226310 -960 226422 480
-rect 227506 -960 227618 480
-rect 228702 -960 228814 480
-rect 229806 -960 229918 480
-rect 231002 -960 231114 480
-rect 232198 -960 232310 480
-rect 233394 -960 233506 480
-rect 234590 -960 234702 480
-rect 235786 -960 235898 480
-rect 236982 -960 237094 480
-rect 238086 -960 238198 480
-rect 239282 -960 239394 480
-rect 240478 -960 240590 480
-rect 241674 -960 241786 480
-rect 242870 -960 242982 480
-rect 244066 -960 244178 480
-rect 245170 -960 245282 480
-rect 246366 -960 246478 480
-rect 247562 -960 247674 480
-rect 248758 -960 248870 480
-rect 249954 -960 250066 480
-rect 251150 -960 251262 480
-rect 252346 -960 252458 480
-rect 253450 -960 253562 480
-rect 253676 462 253888 490
-rect 254688 480 254716 7822
-rect 255332 3874 255360 330482
-rect 255412 330472 255464 330478
-rect 255412 330414 255464 330420
-rect 255424 6594 255452 330414
-rect 255516 10810 255544 338014
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-rect 255688 330540 255740 330546
-rect 255688 330482 255740 330488
-rect 256068 330478 256096 338014
-rect 256056 330472 256108 330478
-rect 256056 330414 256108 330420
-rect 256436 316034 256464 338014
-rect 256804 336682 256832 338014
-rect 255608 316006 256464 316034
-rect 256712 336654 256832 336682
-rect 255608 10878 255636 316006
-rect 255596 10872 255648 10878
-rect 255596 10814 255648 10820
-rect 255504 10804 255556 10810
-rect 255504 10746 255556 10752
-rect 256608 10328 256660 10334
-rect 256608 10270 256660 10276
-rect 255412 6588 255464 6594
-rect 255412 6530 255464 6536
-rect 255320 3868 255372 3874
-rect 255320 3810 255372 3816
-rect 256620 3534 256648 10270
-rect 256712 3942 256740 336654
-rect 257172 335354 257200 338014
-rect 256804 335326 257200 335354
-rect 256804 8022 256832 335326
-rect 257540 316034 257568 338014
-rect 258138 337770 258166 338028
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-rect 256700 3936 256752 3942
-rect 256700 3878 256752 3884
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-rect 255884 480 255912 3470
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-rect 259472 334830 259500 336126
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-rect 259460 334766 259512 334772
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-rect 259564 8158 259592 337742
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-rect 260024 316034 260052 338014
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-rect 261864 334898 261892 338014
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-rect 259552 8152 259604 8158
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-rect 258264 8084 258316 8090
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-rect 258172 4004 258224 4010
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-rect 259736 4140 259788 4146
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-rect 260668 480 260696 10610
-rect 261036 3398 261064 316006
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-rect 261024 3392 261076 3398
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-rect 262324 3330 262352 338014
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-rect 263508 335990 263560 335996
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-rect 264060 332046 264112 332052
-rect 264440 316034 264468 338014
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-rect 264888 330686 264940 330692
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-rect 263796 316006 264468 316034
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-rect 262968 480 262996 3470
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-rect 265084 10198 265112 329258
-rect 265176 10266 265204 338014
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-rect 265544 316034 265572 338014
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-rect 265072 10192 265124 10198
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-rect 264152 3528 264204 3534
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-rect 263784 3188 263836 3194
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-rect 264164 480 264192 3470
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-rect 265348 8152 265400 8158
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-rect 265360 480 265388 8094
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-rect 267832 336194 267884 336200
-rect 267648 336184 267700 336190
-rect 267648 336126 267700 336132
-rect 267372 333464 267424 333470
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-rect 267004 330540 267056 330546
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-rect 267844 10062 267872 335326
-rect 268488 330818 268516 338014
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-rect 268476 330754 268528 330760
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-rect 267936 316006 268884 316034
-rect 267832 10056 267884 10062
-rect 267832 9998 267884 10004
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-rect 270558 337742 270632 337770
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-rect 270408 336116 270460 336122
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-rect 269580 330880 269632 330886
-rect 269580 330822 269632 330828
-rect 269304 9988 269356 9994
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-rect 269028 3528 269080 3534
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-rect 270052 598 270264 626
-rect 270052 480 270080 598
-rect 270236 490 270264 598
-rect 270420 490 270448 336058
-rect 270604 9926 270632 337742
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-rect 270696 9858 270724 330482
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-rect 271880 336330 271932 336336
-rect 271328 330540 271380 330546
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-rect 271972 330540 272024 330546
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-rect 270788 316006 271092 316034
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-rect 271788 10532 271840 10538
-rect 271788 10474 271840 10480
-rect 271800 3534 271828 10474
-rect 271984 9790 272012 330482
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-rect 271788 3528 271840 3534
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-rect 270776 2916 270828 2922
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-rect 254646 -960 254758 480
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-rect 257038 -960 257150 480
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-rect 259430 -960 259542 480
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-rect 262926 -960 263038 480
-rect 264122 -960 264234 480
-rect 265318 -960 265430 480
-rect 266514 -960 266626 480
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-rect 270236 462 270448 490
-rect 271248 480 271276 3470
-rect 272076 2854 272104 338014
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-rect 273548 335374 273576 338014
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-rect 272800 332240 272852 332246
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-rect 274284 316034 274312 338014
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-rect 274548 336194 274600 336200
-rect 273456 316006 274312 316034
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-rect 274560 3534 274588 336194
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-rect 274732 326392 274784 326398
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-rect 274744 5166 274772 326334
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-rect 277458 337742 277532 337770
-rect 276848 336660 276900 336666
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-rect 277032 336660 277084 336666
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-rect 276308 335326 276520 335354
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-rect 276204 326402 276256 326408
-rect 275744 326392 275796 326398
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-rect 276112 321564 276164 321570
-rect 276112 321506 276164 321512
-rect 274928 316006 275416 316034
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-rect 276124 9246 276152 321506
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-rect 276216 8226 276244 326198
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-rect 277308 336388 277360 336394
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-rect 277032 335096 277084 335102
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-rect 276296 321564 276348 321570
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-rect 276204 8220 276256 8226
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-rect 274824 6656 274876 6662
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-rect 274640 5092 274692 5098
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-rect 277122 3360 277178 3369
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-rect 276020 2916 276072 2922
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-rect 277136 480 277164 3295
-rect 277320 2922 277348 336330
-rect 277504 326398 277532 337742
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-rect 277596 14482 277624 338014
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-rect 277952 334902 278004 334908
-rect 277676 326392 277728 326398
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-rect 277584 14476 277636 14482
-rect 277584 14418 277636 14424
-rect 277688 8294 277716 326334
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-rect 279056 336660 279108 336666
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-rect 279436 316034 279464 338014
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-rect 278976 316006 279464 316034
-rect 277676 8288 277728 8294
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-rect 277492 7540 277544 7546
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-rect 278976 7478 279004 316006
-rect 280264 13190 280292 326334
-rect 280540 316034 280568 338014
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-rect 278964 7472 279016 7478
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-rect 280356 7410 280384 316006
-rect 280344 7404 280396 7410
-rect 280344 7346 280396 7352
-rect 278320 5160 278372 5166
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-rect 277308 2916 277360 2922
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-rect 278332 480 278360 5102
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-rect 281460 3534 281488 331186
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-rect 282104 336518 282408 336546
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-rect 282092 336456 282144 336462
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-rect 282000 331016 282052 331022
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-rect 282196 15910 282224 336398
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-rect 283012 326052 283064 326058
-rect 283012 325994 283064 326000
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-rect 281724 7336 281776 7342
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-rect 283024 7206 283052 325994
-rect 283116 7274 283144 338014
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-rect 283760 338014 284004 338042
-rect 283208 336462 283236 338014
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-rect 283380 336660 283432 336666
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-rect 283196 336456 283248 336462
-rect 283196 336398 283248 336404
-rect 283760 326058 283788 338014
-rect 284358 337770 284386 338028
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-rect 283748 325994 283800 326000
-rect 284404 17270 284432 337742
-rect 284496 335510 284524 338014
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-rect 284864 333742 284892 338014
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-rect 284852 333678 284904 333684
-rect 285232 316034 285260 338014
-rect 285692 335850 285720 338014
-rect 285680 335844 285732 335850
-rect 285680 335786 285732 335792
-rect 285772 330540 285824 330546
-rect 285772 330482 285824 330488
-rect 284496 316006 285260 316034
-rect 284392 17264 284444 17270
-rect 284392 17206 284444 17212
-rect 284496 13258 284524 316006
-rect 284484 13252 284536 13258
-rect 284484 13194 284536 13200
-rect 285784 11898 285812 330482
-rect 285968 316034 285996 338014
-rect 286336 330546 286364 338014
-rect 286416 336660 286468 336666
-rect 286416 336602 286468 336608
-rect 286324 330540 286376 330546
-rect 286324 330482 286376 330488
-rect 286428 316034 286456 336602
-rect 286704 335170 286732 338014
-rect 286692 335164 286744 335170
-rect 286692 335106 286744 335112
-rect 285876 316006 285996 316034
-rect 286336 316006 286456 316034
-rect 285772 11892 285824 11898
-rect 285772 11834 285824 11840
-rect 283104 7268 283156 7274
-rect 283104 7210 283156 7216
-rect 283012 7200 283064 7206
-rect 283012 7142 283064 7148
-rect 285876 6730 285904 316006
-rect 286336 10674 286364 316006
-rect 286324 10668 286376 10674
-rect 286324 10610 286376 10616
-rect 287164 6798 287192 338014
-rect 287440 332382 287468 338014
-rect 287808 335714 287836 338014
-rect 287796 335708 287848 335714
-rect 287796 335650 287848 335656
-rect 287428 332376 287480 332382
-rect 287428 332318 287480 332324
-rect 288176 316034 288204 338014
-rect 288440 336728 288492 336734
-rect 288440 336670 288492 336676
-rect 288348 335640 288400 335646
-rect 288348 335582 288400 335588
-rect 287256 316006 288204 316034
-rect 287152 6792 287204 6798
-rect 287152 6734 287204 6740
-rect 285864 6724 285916 6730
-rect 285864 6666 285916 6672
-rect 287256 6118 287284 316006
-rect 287244 6112 287296 6118
-rect 287244 6054 287296 6060
-rect 281908 4480 281960 4486
-rect 281908 4422 281960 4428
-rect 280712 3528 280764 3534
-rect 280712 3470 280764 3476
-rect 281448 3528 281500 3534
-rect 281448 3470 281500 3476
-rect 280724 480 280752 3470
-rect 281920 480 281948 4422
-rect 285404 4412 285456 4418
-rect 285404 4354 285456 4360
-rect 284300 3596 284352 3602
-rect 284300 3538 284352 3544
-rect 283102 3496 283158 3505
-rect 283102 3431 283158 3440
-rect 283116 480 283144 3431
-rect 284312 480 284340 3538
-rect 285416 480 285444 4354
-rect 286600 3664 286652 3670
-rect 286600 3606 286652 3612
-rect 286612 480 286640 3606
-rect 288360 3398 288388 335582
-rect 288452 333810 288480 336670
-rect 288440 333804 288492 333810
-rect 288440 333746 288492 333752
-rect 288544 332450 288572 338014
-rect 288912 335782 288940 338014
-rect 289280 336682 289308 338014
-rect 289832 336734 289860 338014
-rect 289004 336654 289308 336682
-rect 289820 336728 289872 336734
-rect 289820 336670 289872 336676
-rect 288900 335776 288952 335782
-rect 288900 335718 288952 335724
-rect 288532 332444 288584 332450
-rect 288532 332386 288584 332392
-rect 289004 316034 289032 336654
-rect 289084 335844 289136 335850
-rect 289084 335786 289136 335792
-rect 288636 316006 289032 316034
-rect 288636 6050 288664 316006
-rect 289096 10606 289124 335786
-rect 290016 335374 290044 338014
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-rect 290004 335310 290056 335316
-rect 290384 316034 290412 338014
-rect 290936 332518 290964 338014
-rect 291212 336598 291240 338014
-rect 291384 336728 291436 336734
-rect 291384 336670 291436 336676
-rect 291200 336592 291252 336598
-rect 291200 336534 291252 336540
-rect 291396 332586 291424 336670
-rect 291384 332580 291436 332586
-rect 291384 332522 291436 332528
-rect 290924 332512 290976 332518
-rect 290924 332454 290976 332460
-rect 291292 330540 291344 330546
-rect 291292 330482 291344 330488
-rect 290016 316006 290412 316034
-rect 289084 10600 289136 10606
-rect 289084 10542 289136 10548
-rect 288624 6044 288676 6050
-rect 288624 5986 288676 5992
-rect 290016 5982 290044 316006
-rect 291304 13326 291332 330482
-rect 291488 316034 291516 338014
-rect 291856 330546 291884 338014
-rect 292224 336530 292252 338014
-rect 292212 336524 292264 336530
-rect 292212 336466 292264 336472
-rect 291936 335708 291988 335714
-rect 291936 335650 291988 335656
-rect 291844 330540 291896 330546
-rect 291844 330482 291896 330488
-rect 291948 316034 291976 335650
-rect 291396 316006 291516 316034
-rect 291856 316006 291976 316034
-rect 291292 13320 291344 13326
-rect 291292 13262 291344 13268
-rect 290004 5976 290056 5982
-rect 290004 5918 290056 5924
-rect 291396 5914 291424 316006
-rect 291856 12034 291884 316006
-rect 291844 12028 291896 12034
-rect 291844 11970 291896 11976
-rect 291384 5908 291436 5914
-rect 291384 5850 291436 5856
-rect 292684 5846 292712 338014
-rect 292960 336734 292988 338014
-rect 292948 336728 293000 336734
-rect 292948 336670 293000 336676
-rect 293328 336462 293356 338014
-rect 293316 336456 293368 336462
-rect 293316 336398 293368 336404
-rect 293696 316034 293724 338014
-rect 292776 316006 293724 316034
-rect 292672 5840 292724 5846
-rect 292672 5782 292724 5788
-rect 292776 5778 292804 316006
-rect 294064 9314 294092 338014
-rect 294432 335578 294460 338014
-rect 294420 335572 294472 335578
-rect 294420 335514 294472 335520
-rect 294144 330540 294196 330546
-rect 294144 330482 294196 330488
-rect 294156 9382 294184 330482
-rect 294800 316034 294828 338014
-rect 295168 330546 295196 338014
-rect 295444 335510 295472 338014
-rect 295432 335504 295484 335510
-rect 295432 335446 295484 335452
-rect 295812 333878 295840 338014
-rect 296180 336682 296208 338014
-rect 295904 336654 296208 336682
-rect 295800 333872 295852 333878
-rect 295800 333814 295852 333820
-rect 295156 330540 295208 330546
-rect 295156 330482 295208 330488
-rect 295904 316034 295932 336654
-rect 296536 336592 296588 336598
-rect 296536 336534 296588 336540
-rect 295984 335776 296036 335782
-rect 295984 335718 296036 335724
-rect 294248 316006 294828 316034
-rect 295536 316006 295932 316034
-rect 294144 9376 294196 9382
-rect 294144 9318 294196 9324
-rect 294052 9308 294104 9314
-rect 294052 9250 294104 9256
-rect 292764 5772 292816 5778
-rect 292764 5714 292816 5720
-rect 294248 5710 294276 316006
-rect 295536 9450 295564 316006
-rect 295524 9444 295576 9450
-rect 295524 9386 295576 9392
-rect 295996 6322 296024 335718
-rect 296548 334558 296576 336534
-rect 296628 336524 296680 336530
-rect 296628 336466 296680 336472
-rect 296536 334552 296588 334558
-rect 296536 334494 296588 334500
-rect 295984 6316 296036 6322
-rect 295984 6258 296036 6264
-rect 294236 5704 294288 5710
-rect 294236 5646 294288 5652
-rect 288992 4344 289044 4350
-rect 288992 4286 289044 4292
-rect 287796 3392 287848 3398
-rect 287796 3334 287848 3340
-rect 288348 3392 288400 3398
-rect 288348 3334 288400 3340
-rect 287808 480 287836 3334
-rect 289004 480 289032 4286
-rect 292580 4276 292632 4282
-rect 292580 4218 292632 4224
-rect 291384 3732 291436 3738
-rect 291384 3674 291436 3680
-rect 290186 3632 290242 3641
-rect 290186 3567 290242 3576
-rect 290200 480 290228 3567
-rect 291396 480 291424 3674
-rect 292592 480 292620 4218
-rect 293684 3800 293736 3806
-rect 293684 3742 293736 3748
-rect 294878 3768 294934 3777
-rect 293696 480 293724 3742
-rect 294878 3703 294934 3712
-rect 294892 480 294920 3703
-rect 296640 3058 296668 336466
-rect 296732 335918 296760 338014
-rect 296916 336598 296944 338014
-rect 296904 336592 296956 336598
-rect 296904 336534 296956 336540
-rect 296720 335912 296772 335918
-rect 296720 335854 296772 335860
-rect 297284 335354 297312 338014
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-rect 296824 9518 296852 335326
-rect 297652 316034 297680 338014
-rect 298112 334490 298140 338014
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-rect 298204 335326 298416 335354
-rect 298100 334484 298152 334490
-rect 298100 334426 298152 334432
-rect 296916 316006 297680 316034
-rect 296812 9512 296864 9518
-rect 296812 9454 296864 9460
-rect 296916 5234 296944 316006
-rect 298204 9586 298232 335326
-rect 298756 316034 298784 338014
-rect 299124 333946 299152 338014
-rect 299388 335912 299440 335918
-rect 299388 335854 299440 335860
-rect 299112 333940 299164 333946
-rect 299112 333882 299164 333888
-rect 298296 316006 298784 316034
-rect 298192 9580 298244 9586
-rect 298192 9522 298244 9528
-rect 298296 5302 298324 316006
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-rect 298284 5238 298336 5244
-rect 296904 5228 296956 5234
-rect 296904 5170 296956 5176
-rect 297272 3868 297324 3874
-rect 297272 3810 297324 3816
-rect 296076 3052 296128 3058
-rect 296076 2994 296128 3000
-rect 296628 3052 296680 3058
-rect 296628 2994 296680 3000
-rect 296088 480 296116 2994
-rect 297284 480 297312 3810
-rect 299400 3398 299428 335854
-rect 299572 330540 299624 330546
-rect 299572 330482 299624 330488
-rect 299584 8906 299612 330482
-rect 299676 9654 299704 338014
-rect 299860 316034 299888 338014
-rect 300228 335986 300256 338014
-rect 300216 335980 300268 335986
-rect 300216 335922 300268 335928
-rect 300596 330546 300624 338014
-rect 300676 336728 300728 336734
-rect 300676 336670 300728 336676
-rect 300688 334422 300716 336670
-rect 300768 336592 300820 336598
-rect 300768 336534 300820 336540
-rect 300676 334416 300728 334422
-rect 300676 334358 300728 334364
-rect 300584 330540 300636 330546
-rect 300584 330482 300636 330488
-rect 299768 316006 299888 316034
-rect 299664 9648 299716 9654
-rect 299664 9590 299716 9596
-rect 299572 8900 299624 8906
-rect 299572 8842 299624 8848
-rect 299664 6384 299716 6390
-rect 299664 6326 299716 6332
-rect 298468 3392 298520 3398
-rect 298468 3334 298520 3340
-rect 299388 3392 299440 3398
-rect 299388 3334 299440 3340
-rect 298480 480 298508 3334
-rect 299676 480 299704 6326
-rect 299768 5370 299796 316006
-rect 299756 5364 299808 5370
-rect 299756 5306 299808 5312
-rect 300780 480 300808 336534
-rect 300952 330540 301004 330546
-rect 300952 330482 301004 330488
-rect 300964 8838 300992 330482
-rect 300952 8832 301004 8838
-rect 300952 8774 301004 8780
-rect 301056 5438 301084 338014
-rect 301332 336734 301360 338014
-rect 301320 336728 301372 336734
-rect 301320 336670 301372 336676
-rect 301700 330546 301728 338014
-rect 302298 337770 302326 338028
-rect 302436 338014 302680 338042
-rect 302804 338014 303048 338042
-rect 303172 338014 303416 338042
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-rect 303908 338014 304152 338042
-rect 304276 338014 304520 338042
-rect 304644 338014 304888 338042
-rect 305196 338014 305256 338042
-rect 305380 338014 305624 338042
-rect 305748 338014 305992 338042
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-rect 306484 338014 306728 338042
-rect 306852 338014 307096 338042
-rect 307220 338014 307372 338042
-rect 307496 338014 307740 338042
-rect 307864 338014 308108 338042
-rect 308232 338014 308476 338042
-rect 308600 338014 308844 338042
-rect 302298 337742 302372 337770
-rect 301688 330540 301740 330546
-rect 301688 330482 301740 330488
-rect 302344 5506 302372 337742
-rect 302436 333198 302464 338014
-rect 302804 335354 302832 338014
-rect 302528 335326 302832 335354
-rect 302424 333192 302476 333198
-rect 302424 333134 302476 333140
-rect 302528 330528 302556 335326
-rect 302436 330500 302556 330528
-rect 302436 8770 302464 330500
-rect 303172 316034 303200 338014
-rect 303632 334354 303660 338014
-rect 303908 335354 303936 338014
-rect 303724 335326 303936 335354
-rect 303620 334348 303672 334354
-rect 303620 334290 303672 334296
-rect 302528 316006 303200 316034
-rect 302424 8764 302476 8770
-rect 302424 8706 302476 8712
-rect 302332 5500 302384 5506
-rect 302332 5442 302384 5448
-rect 301044 5432 301096 5438
-rect 301044 5374 301096 5380
-rect 302528 4758 302556 316006
-rect 303724 8702 303752 335326
-rect 304276 316034 304304 338014
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-rect 304908 335980 304960 335986
-rect 304908 335922 304960 335928
-rect 304632 333124 304684 333130
-rect 304632 333066 304684 333072
-rect 303816 316006 304304 316034
-rect 303712 8696 303764 8702
-rect 303712 8638 303764 8644
-rect 303160 6316 303212 6322
-rect 303160 6258 303212 6264
-rect 302516 4752 302568 4758
-rect 302516 4694 302568 4700
-rect 301964 3936 302016 3942
-rect 301964 3878 302016 3884
-rect 301976 480 302004 3878
-rect 303172 480 303200 6258
-rect 303816 4690 303844 316006
-rect 303804 4684 303856 4690
-rect 303804 4626 303856 4632
-rect 304920 3398 304948 335922
-rect 305000 330540 305052 330546
-rect 305000 330482 305052 330488
-rect 305012 4622 305040 330482
-rect 305092 330472 305144 330478
-rect 305092 330414 305144 330420
-rect 305104 7138 305132 330414
-rect 305196 8634 305224 338014
-rect 305380 330546 305408 338014
-rect 305368 330540 305420 330546
-rect 305368 330482 305420 330488
-rect 305748 330478 305776 338014
-rect 305736 330472 305788 330478
-rect 305736 330414 305788 330420
-rect 306116 316034 306144 338014
-rect 306484 335354 306512 338014
-rect 306852 335354 306880 338014
-rect 305288 316006 306144 316034
-rect 306392 335326 306512 335354
-rect 306576 335326 306880 335354
-rect 305184 8628 305236 8634
-rect 305184 8570 305236 8576
-rect 305288 8566 305316 316006
-rect 305276 8560 305328 8566
-rect 305276 8502 305328 8508
-rect 305092 7132 305144 7138
-rect 305092 7074 305144 7080
-rect 305000 4616 305052 4622
-rect 305000 4558 305052 4564
-rect 306392 4554 306420 335326
-rect 306472 330540 306524 330546
-rect 306472 330482 306524 330488
-rect 306484 4826 306512 330482
-rect 306576 7070 306604 335326
-rect 307220 316034 307248 338014
-rect 307496 330546 307524 338014
-rect 307484 330540 307536 330546
-rect 307484 330482 307536 330488
-rect 307760 330540 307812 330546
-rect 307760 330482 307812 330488
-rect 306668 316006 307248 316034
-rect 306668 8498 306696 316006
-rect 306656 8492 306708 8498
-rect 306656 8434 306708 8440
-rect 306564 7064 306616 7070
-rect 306564 7006 306616 7012
-rect 307772 4894 307800 330482
-rect 307864 7614 307892 338014
-rect 308232 316034 308260 338014
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-rect 309198 337770 309226 338028
-rect 309428 338014 309580 338042
-rect 309704 338014 309948 338042
-rect 310072 338014 310316 338042
-rect 309198 337742 309272 337770
-rect 308588 330540 308640 330546
-rect 308588 330482 308640 330488
-rect 309140 330472 309192 330478
-rect 309140 330414 309192 330420
-rect 307956 316006 308260 316034
-rect 307956 8974 307984 316006
-rect 307944 8968 307996 8974
-rect 307944 8910 307996 8916
-rect 307852 7608 307904 7614
-rect 307852 7550 307904 7556
-rect 309152 4962 309180 330414
-rect 309244 7682 309272 337742
-rect 309324 330540 309376 330546
-rect 309324 330482 309376 330488
-rect 309336 7750 309364 330482
-rect 309428 8430 309456 338014
-rect 309704 330478 309732 338014
-rect 310072 330546 310100 338014
-rect 310670 337770 310698 338028
-rect 310808 338014 311052 338042
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-rect 311912 338014 312156 338042
-rect 312280 338014 312524 338042
-rect 312648 338014 312892 338042
-rect 313016 338014 313260 338042
-rect 313384 338014 313628 338042
-rect 313752 338014 313996 338042
-rect 314120 338014 314364 338042
-rect 310670 337742 310744 337770
-rect 310520 336660 310572 336666
-rect 310520 336602 310572 336608
-rect 310060 330540 310112 330546
-rect 310060 330482 310112 330488
-rect 309692 330472 309744 330478
-rect 309692 330414 309744 330420
-rect 309416 8424 309468 8430
-rect 309416 8366 309468 8372
-rect 309324 7744 309376 7750
-rect 309324 7686 309376 7692
-rect 309232 7676 309284 7682
-rect 309232 7618 309284 7624
-rect 310532 5030 310560 336602
-rect 310612 330540 310664 330546
-rect 310612 330482 310664 330488
-rect 310624 7818 310652 330482
-rect 310716 9042 310744 337742
-rect 310808 336666 310836 338014
-rect 310796 336660 310848 336666
-rect 310796 336602 310848 336608
-rect 311176 330546 311204 338014
-rect 311164 330540 311216 330546
-rect 311164 330482 311216 330488
-rect 311544 316034 311572 338014
-rect 311912 335714 311940 338014
-rect 311900 335708 311952 335714
-rect 311900 335650 311952 335656
-rect 311992 330540 312044 330546
-rect 311992 330482 312044 330488
-rect 310808 316006 311572 316034
-rect 310808 9110 310836 316006
-rect 312004 11966 312032 330482
-rect 312280 316034 312308 338014
-rect 312648 330546 312676 338014
-rect 313016 335850 313044 338014
-rect 313004 335844 313056 335850
-rect 313004 335786 313056 335792
-rect 312636 330540 312688 330546
-rect 312636 330482 312688 330488
-rect 313280 330540 313332 330546
-rect 313280 330482 313332 330488
-rect 312096 316006 312308 316034
-rect 311992 11960 312044 11966
-rect 311992 11902 312044 11908
-rect 310796 9104 310848 9110
-rect 310796 9046 310848 9052
-rect 310704 9036 310756 9042
-rect 310704 8978 310756 8984
-rect 312096 7886 312124 316006
-rect 312084 7880 312136 7886
-rect 312084 7822 312136 7828
-rect 310612 7812 310664 7818
-rect 310612 7754 310664 7760
-rect 313292 6186 313320 330482
-rect 313384 7954 313412 338014
-rect 313752 316034 313780 338014
-rect 314120 330546 314148 338014
-rect 314718 337770 314746 338028
-rect 314856 338014 315100 338042
-rect 315224 338014 315468 338042
-rect 315592 338014 315836 338042
-rect 316052 338014 316204 338042
-rect 316328 338014 316572 338042
-rect 316696 338014 316940 338042
-rect 317064 338014 317308 338042
-rect 317616 338014 317676 338042
-rect 317800 338014 318044 338042
-rect 318168 338014 318412 338042
-rect 318536 338014 318780 338042
-rect 318996 338014 319148 338042
-rect 319272 338014 319424 338042
-rect 319548 338014 319792 338042
-rect 319916 338014 320160 338042
-rect 320284 338014 320528 338042
-rect 320652 338014 320896 338042
-rect 321020 338014 321264 338042
-rect 321572 338014 321632 338042
-rect 321756 338014 322000 338042
-rect 322124 338014 322368 338042
-rect 322492 338014 322736 338042
-rect 323044 338014 323104 338042
-rect 323228 338014 323472 338042
-rect 323596 338014 323840 338042
-rect 323964 338014 324208 338042
-rect 324516 338014 324576 338042
-rect 324700 338014 324944 338042
-rect 325068 338014 325312 338042
-rect 325436 338014 325680 338042
-rect 325804 338014 326048 338042
-rect 326172 338014 326416 338042
-rect 326540 338014 326784 338042
-rect 327092 338014 327152 338042
-rect 327276 338014 327520 338042
-rect 327644 338014 327888 338042
-rect 328012 338014 328256 338042
-rect 328472 338014 328624 338042
-rect 328748 338014 328992 338042
-rect 329116 338014 329360 338042
-rect 329484 338014 329728 338042
-rect 330036 338014 330096 338042
-rect 330220 338014 330464 338042
-rect 330588 338014 330832 338042
-rect 330956 338014 331108 338042
-rect 314718 337742 314792 337770
-rect 314108 330540 314160 330546
-rect 314108 330482 314160 330488
-rect 313476 316006 313780 316034
-rect 313476 10334 313504 316006
-rect 313464 10328 313516 10334
-rect 313464 10270 313516 10276
-rect 314764 8022 314792 337742
-rect 314856 335782 314884 338014
-rect 315224 336666 315252 338014
-rect 315212 336660 315264 336666
-rect 315212 336602 315264 336608
-rect 314844 335776 314896 335782
-rect 314844 335718 314896 335724
-rect 315592 316034 315620 338014
-rect 316052 336054 316080 338014
-rect 316328 336682 316356 338014
-rect 316144 336654 316356 336682
-rect 316040 336048 316092 336054
-rect 316040 335990 316092 335996
-rect 314856 316006 315620 316034
-rect 314856 8090 314884 316006
-rect 316144 10402 316172 336654
-rect 316696 335354 316724 338014
-rect 317064 336190 317092 338014
-rect 317052 336184 317104 336190
-rect 317052 336126 317104 336132
-rect 316776 336048 316828 336054
-rect 316776 335990 316828 335996
-rect 316236 335326 316724 335354
-rect 316132 10396 316184 10402
-rect 316132 10338 316184 10344
-rect 316236 8158 316264 335326
-rect 316788 316034 316816 335990
-rect 317512 330540 317564 330546
-rect 317512 330482 317564 330488
-rect 316696 316006 316816 316034
-rect 316224 8152 316276 8158
-rect 316224 8094 316276 8100
-rect 314844 8084 314896 8090
-rect 314844 8026 314896 8032
-rect 314752 8016 314804 8022
-rect 314752 7958 314804 7964
-rect 313372 7948 313424 7954
-rect 313372 7890 313424 7896
-rect 316696 6390 316724 316006
-rect 317524 10538 317552 330482
-rect 317512 10532 317564 10538
-rect 317512 10474 317564 10480
-rect 317616 10470 317644 338014
-rect 317800 316034 317828 338014
-rect 318168 336122 318196 338014
-rect 318156 336116 318208 336122
-rect 318156 336058 318208 336064
-rect 318536 330546 318564 338014
-rect 318524 330540 318576 330546
-rect 318524 330482 318576 330488
-rect 318892 330540 318944 330546
-rect 318892 330482 318944 330488
-rect 317708 316006 317828 316034
-rect 317604 10464 317656 10470
-rect 317604 10406 317656 10412
-rect 316684 6384 316736 6390
-rect 316684 6326 316736 6332
-rect 317708 6254 317736 316006
-rect 317696 6248 317748 6254
-rect 317696 6190 317748 6196
-rect 313280 6180 313332 6186
-rect 313280 6122 313332 6128
-rect 318904 5098 318932 330482
-rect 318892 5092 318944 5098
-rect 318892 5034 318944 5040
-rect 310520 5024 310572 5030
-rect 310520 4966 310572 4972
-rect 309140 4956 309192 4962
-rect 309140 4898 309192 4904
-rect 307760 4888 307812 4894
-rect 307760 4830 307812 4836
-rect 306472 4820 306524 4826
-rect 306472 4762 306524 4768
-rect 306380 4548 306432 4554
-rect 306380 4490 306432 4496
-rect 309048 4140 309100 4146
-rect 309048 4082 309100 4088
-rect 307944 4072 307996 4078
-rect 307944 4014 307996 4020
-rect 305552 4004 305604 4010
-rect 305552 3946 305604 3952
-rect 304356 3392 304408 3398
-rect 304356 3334 304408 3340
-rect 304908 3392 304960 3398
-rect 304908 3334 304960 3340
-rect 304368 480 304396 3334
-rect 305564 480 305592 3946
-rect 306748 3392 306800 3398
-rect 306748 3334 306800 3340
-rect 306760 480 306788 3334
-rect 307956 480 307984 4014
-rect 309060 480 309088 4082
-rect 318996 3466 319024 338014
-rect 319272 336258 319300 338014
-rect 319260 336252 319312 336258
-rect 319260 336194 319312 336200
-rect 319548 330546 319576 338014
-rect 319916 336394 319944 338014
-rect 319904 336388 319956 336394
-rect 319904 336330 319956 336336
-rect 319536 330540 319588 330546
-rect 319536 330482 319588 330488
-rect 320180 330540 320232 330546
-rect 320180 330482 320232 330488
-rect 320192 3534 320220 330482
-rect 320180 3528 320232 3534
-rect 320180 3470 320232 3476
-rect 318984 3460 319036 3466
-rect 318984 3402 319036 3408
-rect 319720 3460 319772 3466
-rect 319720 3402 319772 3408
-rect 310244 3324 310296 3330
-rect 310244 3266 310296 3272
-rect 310256 480 310284 3266
-rect 311440 3256 311492 3262
-rect 311440 3198 311492 3204
-rect 311452 480 311480 3198
-rect 312636 3188 312688 3194
-rect 312636 3130 312688 3136
-rect 312648 480 312676 3130
-rect 313832 3120 313884 3126
-rect 313832 3062 313884 3068
-rect 313844 480 313872 3062
-rect 315028 3052 315080 3058
-rect 315028 2994 315080 3000
-rect 315040 480 315068 2994
-rect 317328 2984 317380 2990
-rect 317328 2926 317380 2932
-rect 316224 2916 316276 2922
-rect 316224 2858 316276 2864
-rect 316236 480 316264 2858
-rect 317340 480 317368 2926
-rect 318524 2848 318576 2854
-rect 318524 2790 318576 2796
-rect 318536 480 318564 2790
-rect 319732 480 319760 3402
-rect 320284 3369 320312 338014
-rect 320652 316034 320680 338014
-rect 321020 330546 321048 338014
-rect 321572 336326 321600 338014
-rect 321560 336320 321612 336326
-rect 321560 336262 321612 336268
-rect 321008 330540 321060 330546
-rect 321008 330482 321060 330488
-rect 321652 330540 321704 330546
-rect 321652 330482 321704 330488
-rect 320376 316006 320680 316034
-rect 320376 5166 320404 316006
-rect 320364 5160 320416 5166
-rect 320364 5102 320416 5108
-rect 320916 3868 320968 3874
-rect 320916 3810 320968 3816
-rect 320270 3360 320326 3369
-rect 320270 3295 320326 3304
-rect 320928 480 320956 3810
-rect 321664 3602 321692 330482
-rect 321756 4486 321784 338014
-rect 322124 316034 322152 338014
-rect 322492 330546 322520 338014
-rect 322480 330540 322532 330546
-rect 322480 330482 322532 330488
-rect 321848 316006 322152 316034
-rect 321744 4480 321796 4486
-rect 321744 4422 321796 4428
-rect 321652 3596 321704 3602
-rect 321652 3538 321704 3544
-rect 321848 3505 321876 316006
-rect 323044 4418 323072 338014
-rect 323124 330540 323176 330546
-rect 323124 330482 323176 330488
-rect 323032 4412 323084 4418
-rect 323032 4354 323084 4360
-rect 323136 4350 323164 330482
-rect 323124 4344 323176 4350
-rect 323124 4286 323176 4292
-rect 323228 3670 323256 338014
-rect 323596 336462 323624 338014
-rect 323584 336456 323636 336462
-rect 323584 336398 323636 336404
-rect 323964 330546 323992 338014
-rect 323952 330540 324004 330546
-rect 323952 330482 324004 330488
-rect 324320 330540 324372 330546
-rect 324320 330482 324372 330488
-rect 324332 4026 324360 330482
-rect 324412 330472 324464 330478
-rect 324412 330414 324464 330420
-rect 324240 3998 324360 4026
-rect 324240 3670 324268 3998
-rect 324424 3924 324452 330414
-rect 324332 3896 324452 3924
-rect 324332 3806 324360 3896
-rect 324320 3800 324372 3806
-rect 324320 3742 324372 3748
-rect 324412 3800 324464 3806
-rect 324412 3742 324464 3748
-rect 323216 3664 323268 3670
-rect 323216 3606 323268 3612
-rect 324228 3664 324280 3670
-rect 324228 3606 324280 3612
-rect 323400 3596 323452 3602
-rect 323400 3538 323452 3544
-rect 322112 3528 322164 3534
-rect 321834 3496 321890 3505
-rect 322112 3470 322164 3476
-rect 321834 3431 321890 3440
-rect 322124 480 322152 3470
-rect 323412 1850 323440 3538
-rect 323320 1822 323440 1850
-rect 323320 480 323348 1822
-rect 324424 480 324452 3742
-rect 324516 3641 324544 338014
-rect 324700 330546 324728 338014
-rect 324688 330540 324740 330546
-rect 324688 330482 324740 330488
-rect 325068 316034 325096 338014
-rect 325436 330478 325464 338014
-rect 325424 330472 325476 330478
-rect 325424 330414 325476 330420
-rect 324608 316006 325096 316034
-rect 324608 4282 324636 316006
-rect 324596 4276 324648 4282
-rect 324596 4218 324648 4224
-rect 325804 3777 325832 338014
-rect 326172 336530 326200 338014
-rect 326160 336524 326212 336530
-rect 326160 336466 326212 336472
-rect 326540 316034 326568 338014
-rect 327092 336598 327120 338014
-rect 327080 336592 327132 336598
-rect 327080 336534 327132 336540
-rect 327276 336054 327304 338014
-rect 327644 336818 327672 338014
-rect 327552 336790 327672 336818
-rect 327552 336734 327580 336790
-rect 327540 336728 327592 336734
-rect 328012 336682 328040 338014
-rect 327540 336670 327592 336676
-rect 327644 336654 328040 336682
-rect 327264 336048 327316 336054
-rect 327264 335990 327316 335996
-rect 327644 316034 327672 336654
-rect 328368 336048 328420 336054
-rect 328368 335990 328420 335996
-rect 327724 335640 327776 335646
-rect 327724 335582 327776 335588
-rect 325896 316006 326568 316034
-rect 327276 316006 327672 316034
-rect 325896 3942 325924 316006
-rect 325884 3936 325936 3942
-rect 325884 3878 325936 3884
-rect 327276 3806 327304 316006
-rect 327736 6322 327764 335582
-rect 327724 6316 327776 6322
-rect 327724 6258 327776 6264
-rect 327264 3800 327316 3806
-rect 325790 3768 325846 3777
-rect 327264 3742 327316 3748
-rect 325790 3703 325846 3712
-rect 326804 3732 326856 3738
-rect 326804 3674 326856 3680
-rect 325608 3664 325660 3670
-rect 324502 3632 324558 3641
-rect 325608 3606 325660 3612
-rect 324502 3567 324558 3576
-rect 325620 480 325648 3606
-rect 326816 480 326844 3674
-rect 328012 598 328224 626
-rect 328012 480 328040 598
-rect 328196 490 328224 598
-rect 328380 490 328408 335990
-rect 328472 335646 328500 338014
-rect 328748 336954 328776 338014
-rect 328564 336926 328776 336954
-rect 328564 335986 328592 336926
-rect 329116 336818 329144 338014
-rect 328656 336790 329144 336818
-rect 328552 335980 328604 335986
-rect 328552 335922 328604 335928
-rect 328460 335640 328512 335646
-rect 328460 335582 328512 335588
-rect 328656 316034 328684 336790
-rect 329484 336682 329512 338014
-rect 329024 336654 329512 336682
-rect 329024 316034 329052 336654
-rect 329104 336524 329156 336530
-rect 329104 336466 329156 336472
-rect 328564 316006 328684 316034
-rect 328748 316006 329052 316034
-rect 328564 4010 328592 316006
-rect 328552 4004 328604 4010
-rect 328552 3946 328604 3952
-rect 328748 3398 328776 316006
-rect 329116 3874 329144 336466
-rect 329840 330540 329892 330546
-rect 329840 330482 329892 330488
-rect 329196 4004 329248 4010
-rect 329196 3946 329248 3952
-rect 329104 3868 329156 3874
-rect 329104 3810 329156 3816
-rect 328736 3392 328788 3398
-rect 328736 3334 328788 3340
-rect 271206 -960 271318 480
-rect 272402 -960 272514 480
-rect 273598 -960 273710 480
-rect 274794 -960 274906 480
-rect 275990 -960 276102 480
-rect 277094 -960 277206 480
-rect 278290 -960 278402 480
-rect 279486 -960 279598 480
-rect 280682 -960 280794 480
-rect 281878 -960 281990 480
-rect 283074 -960 283186 480
-rect 284270 -960 284382 480
-rect 285374 -960 285486 480
-rect 286570 -960 286682 480
-rect 287766 -960 287878 480
-rect 288962 -960 289074 480
-rect 290158 -960 290270 480
-rect 291354 -960 291466 480
-rect 292550 -960 292662 480
-rect 293654 -960 293766 480
-rect 294850 -960 294962 480
-rect 296046 -960 296158 480
-rect 297242 -960 297354 480
-rect 298438 -960 298550 480
-rect 299634 -960 299746 480
-rect 300738 -960 300850 480
-rect 301934 -960 302046 480
-rect 303130 -960 303242 480
-rect 304326 -960 304438 480
-rect 305522 -960 305634 480
-rect 306718 -960 306830 480
-rect 307914 -960 308026 480
-rect 309018 -960 309130 480
-rect 310214 -960 310326 480
-rect 311410 -960 311522 480
-rect 312606 -960 312718 480
-rect 313802 -960 313914 480
-rect 314998 -960 315110 480
-rect 316194 -960 316306 480
-rect 317298 -960 317410 480
-rect 318494 -960 318606 480
-rect 319690 -960 319802 480
-rect 320886 -960 320998 480
-rect 322082 -960 322194 480
-rect 323278 -960 323390 480
-rect 324382 -960 324494 480
-rect 325578 -960 325690 480
-rect 326774 -960 326886 480
-rect 327970 -960 328082 480
-rect 328196 462 328408 490
-rect 329208 480 329236 3946
-rect 329852 3330 329880 330482
-rect 329932 326664 329984 326670
-rect 329932 326606 329984 326612
-rect 329944 4146 329972 326606
-rect 329932 4140 329984 4146
-rect 329932 4082 329984 4088
-rect 330036 4078 330064 338014
-rect 330220 326670 330248 338014
-rect 330588 330546 330616 338014
-rect 330576 330540 330628 330546
-rect 330576 330482 330628 330488
-rect 330208 326664 330260 326670
-rect 330208 326606 330260 326612
-rect 330956 316034 330984 338014
-rect 331462 337770 331490 338028
-rect 331692 338014 331844 338042
-rect 331968 338014 332212 338042
-rect 332336 338014 332580 338042
-rect 332704 338014 332948 338042
-rect 333072 338014 333316 338042
-rect 333440 338014 333684 338042
-rect 333992 338014 334052 338042
-rect 334176 338014 334420 338042
-rect 334544 338014 334788 338042
-rect 334912 338014 335156 338042
-rect 331462 337742 331536 337770
-rect 331508 326466 331536 337742
-rect 331496 326460 331548 326466
-rect 331496 326402 331548 326408
-rect 331312 326392 331364 326398
-rect 331692 326346 331720 338014
-rect 331772 326460 331824 326466
-rect 331772 326402 331824 326408
-rect 331312 326334 331364 326340
-rect 330128 316006 330984 316034
-rect 330024 4072 330076 4078
-rect 330024 4014 330076 4020
-rect 329840 3324 329892 3330
-rect 329840 3266 329892 3272
-rect 330128 3262 330156 316006
-rect 330116 3256 330168 3262
-rect 330116 3198 330168 3204
-rect 330392 3188 330444 3194
-rect 330392 3130 330444 3136
-rect 330404 480 330432 3130
-rect 331324 3058 331352 326334
-rect 331416 326318 331720 326346
-rect 331416 3126 331444 326318
-rect 331496 326256 331548 326262
-rect 331496 326198 331548 326204
-rect 331508 6914 331536 326198
-rect 331784 321554 331812 326402
-rect 331968 326398 331996 338014
-rect 331956 326392 332008 326398
-rect 331956 326334 332008 326340
-rect 332336 326262 332364 338014
-rect 332704 336682 332732 338014
-rect 332612 336654 332732 336682
-rect 332508 335368 332560 335374
-rect 332508 335310 332560 335316
-rect 332324 326256 332376 326262
-rect 332324 326198 332376 326204
-rect 331600 321526 331812 321554
-rect 331600 16574 331628 321526
-rect 331600 16546 331812 16574
-rect 331508 6886 331720 6914
-rect 331588 3528 331640 3534
-rect 331588 3470 331640 3476
-rect 331404 3120 331456 3126
-rect 331404 3062 331456 3068
-rect 331312 3052 331364 3058
-rect 331312 2994 331364 3000
-rect 331600 480 331628 3470
-rect 331692 2922 331720 6886
-rect 331784 3262 331812 16546
-rect 332520 3534 332548 335310
-rect 332508 3528 332560 3534
-rect 332508 3470 332560 3476
-rect 331772 3256 331824 3262
-rect 331772 3198 331824 3204
-rect 332612 2990 332640 336654
-rect 333072 335354 333100 338014
-rect 333440 336682 333468 338014
-rect 332704 335326 333100 335354
-rect 333164 336654 333468 336682
-rect 332704 11762 332732 335326
-rect 333164 316034 333192 336654
-rect 333992 336530 334020 338014
-rect 333980 336524 334032 336530
-rect 333980 336466 334032 336472
-rect 333244 335912 333296 335918
-rect 333244 335854 333296 335860
-rect 332796 316006 333192 316034
-rect 332692 11756 332744 11762
-rect 332692 11698 332744 11704
-rect 332692 4140 332744 4146
-rect 332692 4082 332744 4088
-rect 332600 2984 332652 2990
-rect 332600 2926 332652 2932
-rect 331680 2916 331732 2922
-rect 331680 2858 331732 2864
-rect 332704 480 332732 4082
-rect 332796 3466 332824 316006
-rect 332876 11756 332928 11762
-rect 332876 11698 332928 11704
-rect 332784 3460 332836 3466
-rect 332784 3402 332836 3408
-rect 332888 2854 332916 11698
-rect 333256 3194 333284 335854
-rect 334072 326392 334124 326398
-rect 334072 326334 334124 326340
-rect 333888 3868 333940 3874
-rect 333888 3810 333940 3816
-rect 333244 3188 333296 3194
-rect 333244 3130 333296 3136
-rect 332876 2848 332928 2854
-rect 332876 2790 332928 2796
-rect 333900 480 333928 3810
-rect 334084 3602 334112 326334
-rect 334176 3806 334204 338014
-rect 334544 326398 334572 338014
-rect 334532 326392 334584 326398
-rect 334532 326334 334584 326340
-rect 334912 316034 334940 338014
-rect 335510 337770 335538 338028
-rect 335648 338014 335892 338042
-rect 336016 338014 336260 338042
-rect 336384 338014 336628 338042
-rect 336752 338014 336996 338042
-rect 337120 338014 337364 338042
-rect 337488 338014 337732 338042
-rect 337856 338014 338100 338042
-rect 338316 338014 338468 338042
-rect 338592 338014 338836 338042
-rect 338960 338014 339204 338042
-rect 335510 337742 335584 337770
-rect 335452 336728 335504 336734
-rect 335452 336670 335504 336676
-rect 334268 316006 334940 316034
-rect 334268 3942 334296 316006
-rect 334256 3936 334308 3942
-rect 334256 3878 334308 3884
-rect 334164 3800 334216 3806
-rect 334164 3742 334216 3748
-rect 335464 3738 335492 336670
-rect 335452 3732 335504 3738
-rect 335452 3674 335504 3680
-rect 335556 3670 335584 337742
-rect 335648 336734 335676 338014
-rect 335636 336728 335688 336734
-rect 335636 336670 335688 336676
-rect 336016 336054 336044 338014
-rect 336004 336048 336056 336054
-rect 336004 335990 336056 335996
-rect 336004 335844 336056 335850
-rect 336004 335786 336056 335792
-rect 335636 326392 335688 326398
-rect 335636 326334 335688 326340
-rect 335648 4010 335676 326334
-rect 336016 4146 336044 335786
-rect 336384 326398 336412 338014
-rect 336752 335918 336780 338014
-rect 336740 335912 336792 335918
-rect 336740 335854 336792 335860
-rect 337120 335374 337148 338014
-rect 337488 335850 337516 338014
-rect 337476 335844 337528 335850
-rect 337476 335786 337528 335792
-rect 337108 335368 337160 335374
-rect 337108 335310 337160 335316
-rect 336372 326392 336424 326398
-rect 336372 326334 336424 326340
-rect 337856 316034 337884 338014
-rect 338120 326460 338172 326466
-rect 338120 326402 338172 326408
-rect 336936 316006 337884 316034
-rect 336004 4140 336056 4146
-rect 336004 4082 336056 4088
-rect 335636 4004 335688 4010
-rect 335636 3946 335688 3952
-rect 336936 3874 336964 316006
-rect 336924 3868 336976 3874
-rect 336924 3810 336976 3816
-rect 335544 3664 335596 3670
-rect 335544 3606 335596 3612
-rect 334072 3596 334124 3602
-rect 334072 3538 334124 3544
-rect 338132 3534 338160 326402
-rect 338212 326392 338264 326398
-rect 338212 326334 338264 326340
-rect 337476 3528 337528 3534
-rect 337476 3470 337528 3476
-rect 338120 3528 338172 3534
-rect 338120 3470 338172 3476
-rect 335084 3460 335136 3466
-rect 335084 3402 335136 3408
-rect 336280 3460 336332 3466
-rect 336280 3402 336332 3408
-rect 335096 480 335124 3402
-rect 336292 480 336320 3402
-rect 337488 480 337516 3470
-rect 338224 3466 338252 326334
-rect 338316 3602 338344 338014
-rect 338592 326398 338620 338014
-rect 338960 326466 338988 338014
-rect 339558 337770 339586 338028
-rect 339788 338014 339940 338042
-rect 340308 338014 340552 338042
-rect 340676 338014 340828 338042
-rect 341044 338014 341288 338042
-rect 341412 338014 341656 338042
-rect 341780 338014 342024 338042
-rect 339558 337742 339632 337770
-rect 339500 336728 339552 336734
-rect 339500 336670 339552 336676
-rect 338948 326460 339000 326466
-rect 338948 326402 339000 326408
-rect 338580 326392 338632 326398
-rect 338580 326334 338632 326340
-rect 338304 3596 338356 3602
-rect 338304 3538 338356 3544
-rect 338212 3460 338264 3466
-rect 338212 3402 338264 3408
-rect 338672 3120 338724 3126
-rect 338672 3062 338724 3068
-rect 338684 480 338712 3062
-rect 339512 490 339540 336670
-rect 339604 3126 339632 337742
-rect 339788 336734 339816 338014
-rect 339776 336728 339828 336734
-rect 339776 336670 339828 336676
-rect 340524 335354 340552 338014
-rect 340800 336682 340828 338014
-rect 340800 336654 341196 336682
-rect 341260 336666 341288 338014
-rect 341628 336734 341656 338014
-rect 341616 336728 341668 336734
-rect 341616 336670 341668 336676
-rect 340524 335326 340828 335354
-rect 340800 3482 340828 335326
-rect 341168 16574 341196 336654
-rect 341248 336660 341300 336666
-rect 341248 336602 341300 336608
-rect 341996 335510 342024 338014
-rect 342134 337770 342162 338028
-rect 342516 338014 342760 338042
-rect 342884 338014 343036 338042
-rect 343160 338014 343312 338042
-rect 342134 337742 342208 337770
-rect 342076 336728 342128 336734
-rect 342076 336670 342128 336676
-rect 341984 335504 342036 335510
-rect 341984 335446 342036 335452
-rect 341168 16546 342024 16574
-rect 340800 3454 341012 3482
-rect 339592 3120 339644 3126
-rect 339592 3062 339644 3068
-rect 339696 598 339908 626
-rect 339696 490 339724 598
-rect 329166 -960 329278 480
-rect 330362 -960 330474 480
-rect 331558 -960 331670 480
-rect 332662 -960 332774 480
-rect 333858 -960 333970 480
-rect 335054 -960 335166 480
-rect 336250 -960 336362 480
-rect 337446 -960 337558 480
-rect 338642 -960 338754 480
-rect 339512 462 339724 490
-rect 339880 480 339908 598
-rect 340984 480 341012 3454
-rect 341996 3074 342024 16546
-rect 342088 3194 342116 336670
-rect 342180 3738 342208 337742
-rect 342628 336660 342680 336666
-rect 342628 336602 342680 336608
-rect 342640 16574 342668 336602
-rect 342732 336054 342760 338014
-rect 342720 336048 342772 336054
-rect 342720 335990 342772 335996
-rect 343008 325694 343036 338014
-rect 343284 335714 343312 338014
-rect 343468 338014 343528 338042
-rect 343896 338014 344140 338042
-rect 344264 338014 344508 338042
-rect 344632 338014 344876 338042
-rect 343272 335708 343324 335714
-rect 343272 335650 343324 335656
-rect 343008 325666 343404 325694
-rect 342640 16546 342944 16574
-rect 342168 3732 342220 3738
-rect 342168 3674 342220 3680
-rect 342076 3188 342128 3194
-rect 342076 3130 342128 3136
-rect 341996 3046 342208 3074
-rect 342180 480 342208 3046
-rect 342916 490 342944 16546
-rect 343376 4010 343404 325666
-rect 343468 4078 343496 338014
-rect 344112 336326 344140 338014
-rect 344100 336320 344152 336326
-rect 344100 336262 344152 336268
-rect 343548 335708 343600 335714
-rect 343548 335650 343600 335656
-rect 343560 4146 343588 335650
-rect 344480 335442 344508 338014
-rect 344468 335436 344520 335442
-rect 344468 335378 344520 335384
-rect 344848 325694 344876 338014
-rect 344940 338014 345000 338042
-rect 345368 338014 345612 338042
-rect 345736 338014 345980 338042
-rect 346104 338014 346348 338042
-rect 346472 338014 346716 338042
-rect 346840 338014 347084 338042
-rect 347208 338014 347452 338042
-rect 344940 335374 344968 338014
-rect 345584 336530 345612 338014
-rect 345572 336524 345624 336530
-rect 345572 336466 345624 336472
-rect 345664 336320 345716 336326
-rect 345664 336262 345716 336268
-rect 345112 335504 345164 335510
-rect 345112 335446 345164 335452
-rect 344928 335368 344980 335374
-rect 344928 335310 344980 335316
-rect 344848 325666 344968 325694
-rect 343548 4140 343600 4146
-rect 343548 4082 343600 4088
-rect 343456 4072 343508 4078
-rect 343456 4014 343508 4020
-rect 343364 4004 343416 4010
-rect 343364 3946 343416 3952
-rect 344940 3806 344968 325666
-rect 345124 16574 345152 335446
-rect 345124 16546 345336 16574
-rect 344928 3800 344980 3806
-rect 344928 3742 344980 3748
-rect 344560 3188 344612 3194
-rect 344560 3130 344612 3136
-rect 343192 598 343404 626
-rect 343192 490 343220 598
-rect 339838 -960 339950 480
-rect 340942 -960 341054 480
-rect 342138 -960 342250 480
-rect 342916 462 343220 490
-rect 343376 480 343404 598
-rect 344572 480 344600 3130
-rect 345308 490 345336 16546
-rect 345676 3534 345704 336262
-rect 345756 335368 345808 335374
-rect 345952 335354 345980 338014
-rect 346320 336734 346348 338014
-rect 346308 336728 346360 336734
-rect 346308 336670 346360 336676
-rect 346688 336462 346716 338014
-rect 347056 336666 347084 338014
-rect 347136 336728 347188 336734
-rect 347136 336670 347188 336676
-rect 347044 336660 347096 336666
-rect 347044 336602 347096 336608
-rect 346676 336456 346728 336462
-rect 346676 336398 346728 336404
-rect 347044 335436 347096 335442
-rect 347044 335378 347096 335384
-rect 345952 335326 346348 335354
-rect 345756 335310 345808 335316
-rect 345768 3874 345796 335310
-rect 345756 3868 345808 3874
-rect 345756 3810 345808 3816
-rect 346320 3670 346348 335326
-rect 346952 3732 347004 3738
-rect 346952 3674 347004 3680
-rect 346308 3664 346360 3670
-rect 346308 3606 346360 3612
-rect 345664 3528 345716 3534
-rect 345664 3470 345716 3476
-rect 345584 598 345796 626
-rect 345584 490 345612 598
-rect 343334 -960 343446 480
-rect 344530 -960 344642 480
-rect 345308 462 345612 490
-rect 345768 480 345796 598
-rect 346964 480 346992 3674
-rect 347056 3194 347084 335378
-rect 347148 3602 347176 336670
-rect 347424 336394 347452 338014
-rect 347562 337770 347590 338028
-rect 347944 338014 348188 338042
-rect 348312 338014 348556 338042
-rect 348680 338014 348924 338042
-rect 347562 337742 347636 337770
-rect 347412 336388 347464 336394
-rect 347412 336330 347464 336336
-rect 347136 3596 347188 3602
-rect 347136 3538 347188 3544
-rect 347044 3188 347096 3194
-rect 347044 3130 347096 3136
-rect 347608 2990 347636 337742
-rect 348160 336734 348188 338014
-rect 348148 336728 348200 336734
-rect 348148 336670 348200 336676
-rect 347688 336660 347740 336666
-rect 347688 336602 347740 336608
-rect 347700 3466 347728 336602
-rect 348528 336598 348556 338014
-rect 348516 336592 348568 336598
-rect 348516 336534 348568 336540
-rect 348896 336326 348924 338014
-rect 349034 337770 349062 338028
-rect 349416 338014 349660 338042
-rect 349784 338014 350028 338042
-rect 350152 338014 350304 338042
-rect 349034 337742 349108 337770
-rect 348976 336728 349028 336734
-rect 348976 336670 349028 336676
-rect 348884 336320 348936 336326
-rect 348884 336262 348936 336268
-rect 347872 336048 347924 336054
-rect 347872 335990 347924 335996
-rect 347884 16574 347912 335990
-rect 347884 16546 348096 16574
-rect 347688 3460 347740 3466
-rect 347688 3402 347740 3408
-rect 347596 2984 347648 2990
-rect 347596 2926 347648 2932
-rect 348068 480 348096 16546
-rect 348988 3262 349016 336670
-rect 349080 3330 349108 337742
-rect 349632 336258 349660 338014
-rect 349804 336524 349856 336530
-rect 349804 336466 349856 336472
-rect 349620 336252 349672 336258
-rect 349620 336194 349672 336200
-rect 349252 4004 349304 4010
-rect 349252 3946 349304 3952
-rect 349068 3324 349120 3330
-rect 349068 3266 349120 3272
-rect 348976 3256 349028 3262
-rect 348976 3198 349028 3204
-rect 349264 480 349292 3946
-rect 349816 3058 349844 336466
-rect 350000 336190 350028 338014
-rect 350276 336734 350304 338014
-rect 350368 338014 350520 338042
-rect 350888 338014 351132 338042
-rect 351256 338014 351500 338042
-rect 350264 336728 350316 336734
-rect 350264 336670 350316 336676
-rect 350264 336252 350316 336258
-rect 350264 336194 350316 336200
-rect 349988 336184 350040 336190
-rect 349988 336126 350040 336132
-rect 350276 8974 350304 336194
-rect 350264 8968 350316 8974
-rect 350264 8910 350316 8916
-rect 350368 4486 350396 338014
-rect 350448 336728 350500 336734
-rect 350448 336670 350500 336676
-rect 350356 4480 350408 4486
-rect 350356 4422 350408 4428
-rect 350460 4298 350488 336670
-rect 351104 336666 351132 338014
-rect 351472 336734 351500 338014
-rect 351610 337770 351638 338028
-rect 351992 338014 352236 338042
-rect 352360 338014 352604 338042
-rect 352728 338014 352880 338042
-rect 351610 337742 351684 337770
-rect 351460 336728 351512 336734
-rect 351460 336670 351512 336676
-rect 351092 336660 351144 336666
-rect 351092 336602 351144 336608
-rect 351656 4554 351684 337742
-rect 351828 336728 351880 336734
-rect 351828 336670 351880 336676
-rect 351736 336660 351788 336666
-rect 351736 336602 351788 336608
-rect 351644 4548 351696 4554
-rect 351644 4490 351696 4496
-rect 350368 4270 350488 4298
-rect 350368 3398 350396 4270
-rect 351748 4146 351776 336602
-rect 350448 4140 350500 4146
-rect 350448 4082 350500 4088
-rect 351736 4140 351788 4146
-rect 351736 4082 351788 4088
-rect 350356 3392 350408 3398
-rect 350356 3334 350408 3340
-rect 349804 3052 349856 3058
-rect 349804 2994 349856 3000
-rect 350460 480 350488 4082
-rect 351840 4078 351868 336670
-rect 352208 336258 352236 338014
-rect 352196 336252 352248 336258
-rect 352196 336194 352248 336200
-rect 352576 335714 352604 338014
-rect 352852 336734 352880 338014
-rect 353036 338014 353096 338042
-rect 353464 338014 353708 338042
-rect 353832 338014 354076 338042
-rect 354200 338014 354444 338042
-rect 352840 336728 352892 336734
-rect 352840 336670 352892 336676
-rect 352564 335708 352616 335714
-rect 352564 335650 352616 335656
-rect 353036 10334 353064 338014
-rect 353116 336728 353168 336734
-rect 353116 336670 353168 336676
-rect 353024 10328 353076 10334
-rect 353024 10270 353076 10276
-rect 353128 4622 353156 336670
-rect 353680 336054 353708 338014
-rect 354048 336394 354076 338014
-rect 354416 336462 354444 338014
-rect 354554 337770 354582 338028
-rect 354936 338014 355088 338042
-rect 355212 338014 355456 338042
-rect 355580 338014 355732 338042
-rect 354554 337742 354628 337770
-rect 354404 336456 354456 336462
-rect 354404 336398 354456 336404
-rect 353944 336388 353996 336394
-rect 353944 336330 353996 336336
-rect 354036 336388 354088 336394
-rect 354036 336330 354088 336336
-rect 354496 336388 354548 336394
-rect 354496 336330 354548 336336
-rect 353668 336048 353720 336054
-rect 353668 335990 353720 335996
-rect 353208 335708 353260 335714
-rect 353208 335650 353260 335656
-rect 353116 4616 353168 4622
-rect 353116 4558 353168 4564
-rect 351644 4072 351696 4078
-rect 351644 4014 351696 4020
-rect 351828 4072 351880 4078
-rect 351828 4014 351880 4020
-rect 351656 480 351684 4014
-rect 353220 4010 353248 335650
-rect 353208 4004 353260 4010
-rect 353208 3946 353260 3952
-rect 352840 3528 352892 3534
-rect 352840 3470 352892 3476
-rect 352852 480 352880 3470
-rect 353956 3126 353984 336330
-rect 354508 4690 354536 336330
-rect 354496 4684 354548 4690
-rect 354496 4626 354548 4632
-rect 354600 3942 354628 337742
-rect 355060 336666 355088 338014
-rect 355048 336660 355100 336666
-rect 355048 336602 355100 336608
-rect 355428 336122 355456 338014
-rect 355704 336734 355732 338014
-rect 355796 338014 355948 338042
-rect 356316 338014 356560 338042
-rect 356684 338014 356928 338042
-rect 355692 336728 355744 336734
-rect 355692 336670 355744 336676
-rect 355416 336116 355468 336122
-rect 355416 336058 355468 336064
-rect 355796 5506 355824 338014
-rect 355968 336728 356020 336734
-rect 355968 336670 356020 336676
-rect 355876 336660 355928 336666
-rect 355876 336602 355928 336608
-rect 355784 5500 355836 5506
-rect 355784 5442 355836 5448
-rect 355888 4758 355916 336602
-rect 355876 4752 355928 4758
-rect 355876 4694 355928 4700
-rect 354588 3936 354640 3942
-rect 354588 3878 354640 3884
-rect 355980 3874 356008 336670
-rect 356532 334626 356560 338014
-rect 356900 335354 356928 338014
-rect 356992 338014 357052 338042
-rect 357176 338014 357420 338042
-rect 357788 338014 358032 338042
-rect 358156 338014 358400 338042
-rect 356992 336734 357020 338014
-rect 356980 336728 357032 336734
-rect 356980 336670 357032 336676
-rect 356900 335326 357112 335354
-rect 356520 334620 356572 334626
-rect 356520 334562 356572 334568
-rect 355968 3868 356020 3874
-rect 355968 3810 356020 3816
-rect 357084 3806 357112 335326
-rect 357176 9110 357204 338014
-rect 357256 336728 357308 336734
-rect 357256 336670 357308 336676
-rect 357164 9104 357216 9110
-rect 357164 9046 357216 9052
-rect 357268 5438 357296 336670
-rect 358004 336666 358032 338014
-rect 358372 336734 358400 338014
-rect 358510 337770 358538 338028
-rect 358892 338014 359136 338042
-rect 359260 338014 359504 338042
-rect 359628 338014 359872 338042
-rect 359996 338014 360148 338042
-rect 360364 338014 360608 338042
-rect 360732 338014 360976 338042
-rect 361100 338014 361252 338042
-rect 358510 337742 358584 337770
-rect 358360 336728 358412 336734
-rect 358360 336670 358412 336676
-rect 357992 336660 358044 336666
-rect 357992 336602 358044 336608
-rect 358084 336524 358136 336530
-rect 358084 336466 358136 336472
-rect 357256 5432 357308 5438
-rect 357256 5374 357308 5380
-rect 357072 3800 357124 3806
-rect 357072 3742 357124 3748
-rect 355232 3732 355284 3738
-rect 355232 3674 355284 3680
-rect 354036 3188 354088 3194
-rect 354036 3130 354088 3136
-rect 353944 3120 353996 3126
-rect 353944 3062 353996 3068
-rect 354048 480 354076 3130
-rect 355244 480 355272 3674
-rect 356336 3664 356388 3670
-rect 356336 3606 356388 3612
-rect 356348 480 356376 3606
-rect 357532 3052 357584 3058
-rect 357532 2994 357584 3000
-rect 357544 480 357572 2994
-rect 358096 2990 358124 336466
-rect 358556 5302 358584 337742
-rect 358636 336728 358688 336734
-rect 358636 336670 358688 336676
-rect 358648 5370 358676 336670
-rect 358728 336660 358780 336666
-rect 358728 336602 358780 336608
-rect 358636 5364 358688 5370
-rect 358636 5306 358688 5312
-rect 358544 5296 358596 5302
-rect 358544 5238 358596 5244
-rect 358740 3738 358768 336602
-rect 359108 335986 359136 338014
-rect 359476 336734 359504 338014
-rect 359464 336728 359516 336734
-rect 359464 336670 359516 336676
-rect 359096 335980 359148 335986
-rect 359096 335922 359148 335928
-rect 359844 5166 359872 338014
-rect 359924 336728 359976 336734
-rect 359924 336670 359976 336676
-rect 359936 5234 359964 336670
-rect 360016 335980 360068 335986
-rect 360016 335922 360068 335928
-rect 359924 5228 359976 5234
-rect 359924 5170 359976 5176
-rect 359832 5160 359884 5166
-rect 359832 5102 359884 5108
-rect 358728 3732 358780 3738
-rect 358728 3674 358780 3680
-rect 360028 3670 360056 335922
-rect 360016 3664 360068 3670
-rect 360016 3606 360068 3612
-rect 360120 3602 360148 338014
-rect 360580 335986 360608 338014
-rect 360568 335980 360620 335986
-rect 360568 335922 360620 335928
-rect 360948 326398 360976 338014
-rect 361224 336666 361252 338014
-rect 361408 338014 361468 338042
-rect 361836 338014 362080 338042
-rect 362204 338014 362448 338042
-rect 362572 338014 362724 338042
-rect 361212 336660 361264 336666
-rect 361212 336602 361264 336608
-rect 361120 335980 361172 335986
-rect 361120 335922 361172 335928
-rect 360936 326392 360988 326398
-rect 360936 326334 360988 326340
-rect 361132 321554 361160 335922
-rect 361304 326392 361356 326398
-rect 361304 326334 361356 326340
-rect 361132 321526 361252 321554
-rect 361224 5098 361252 321526
-rect 361212 5092 361264 5098
-rect 361212 5034 361264 5040
-rect 361316 5030 361344 326334
-rect 361304 5024 361356 5030
-rect 361304 4966 361356 4972
-rect 361408 4894 361436 338014
-rect 361488 336660 361540 336666
-rect 361488 336602 361540 336608
-rect 361396 4888 361448 4894
-rect 361396 4830 361448 4836
-rect 358728 3596 358780 3602
-rect 358728 3538 358780 3544
-rect 360108 3596 360160 3602
-rect 360108 3538 360160 3544
-rect 358084 2984 358136 2990
-rect 358084 2926 358136 2932
-rect 358740 480 358768 3538
-rect 361500 3534 361528 336602
-rect 362052 335374 362080 338014
-rect 362420 335986 362448 338014
-rect 362592 336728 362644 336734
-rect 362592 336670 362644 336676
-rect 362408 335980 362460 335986
-rect 362408 335922 362460 335928
-rect 362040 335368 362092 335374
-rect 362040 335310 362092 335316
-rect 362604 7070 362632 336670
-rect 362592 7064 362644 7070
-rect 362592 7006 362644 7012
-rect 362696 4826 362724 338014
-rect 362788 338014 362940 338042
-rect 363308 338014 363552 338042
-rect 363676 338014 363920 338042
-rect 364044 338014 364196 338042
-rect 364412 338014 364656 338042
-rect 364780 338014 365024 338042
-rect 365148 338014 365392 338042
-rect 365516 338014 365668 338042
-rect 365884 338014 366128 338042
-rect 366252 338014 366496 338042
-rect 366620 338014 366864 338042
-rect 362788 336734 362816 338014
-rect 363524 336734 363552 338014
-rect 362776 336728 362828 336734
-rect 362776 336670 362828 336676
-rect 363512 336728 363564 336734
-rect 363512 336670 363564 336676
-rect 363604 336592 363656 336598
-rect 363604 336534 363656 336540
-rect 362868 335980 362920 335986
-rect 362868 335922 362920 335928
-rect 362776 335232 362828 335238
-rect 362776 335174 362828 335180
-rect 362788 4962 362816 335174
-rect 362776 4956 362828 4962
-rect 362776 4898 362828 4904
-rect 362684 4820 362736 4826
-rect 362684 4762 362736 4768
-rect 359924 3528 359976 3534
-rect 359924 3470 359976 3476
-rect 361488 3528 361540 3534
-rect 361488 3470 361540 3476
-rect 359936 480 359964 3470
-rect 362880 3466 362908 335922
-rect 363616 5574 363644 336534
-rect 363892 335782 363920 338014
-rect 363880 335776 363932 335782
-rect 363880 335718 363932 335724
-rect 364168 7138 364196 338014
-rect 364248 336728 364300 336734
-rect 364248 336670 364300 336676
-rect 364156 7132 364208 7138
-rect 364156 7074 364208 7080
-rect 363604 5568 363656 5574
-rect 363604 5510 363656 5516
-rect 362316 3460 362368 3466
-rect 362316 3402 362368 3408
-rect 362868 3460 362920 3466
-rect 362868 3402 362920 3408
-rect 361120 2984 361172 2990
-rect 361120 2926 361172 2932
-rect 361132 480 361160 2926
-rect 362328 480 362356 3402
-rect 363512 3120 363564 3126
-rect 363512 3062 363564 3068
-rect 363524 480 363552 3062
-rect 364260 2854 364288 336670
-rect 364628 335850 364656 338014
-rect 364616 335844 364668 335850
-rect 364616 335786 364668 335792
-rect 364996 335510 365024 338014
-rect 364984 335504 365036 335510
-rect 364984 335446 365036 335452
-rect 365364 335354 365392 338014
-rect 365364 335326 365576 335354
-rect 365548 7206 365576 335326
-rect 365536 7200 365588 7206
-rect 365536 7142 365588 7148
-rect 364616 3188 364668 3194
-rect 364616 3130 364668 3136
-rect 364248 2848 364300 2854
-rect 364248 2790 364300 2796
-rect 364628 480 364656 3130
-rect 365640 2922 365668 338014
-rect 366100 335646 366128 338014
-rect 366468 336734 366496 338014
-rect 366456 336728 366508 336734
-rect 366456 336670 366508 336676
-rect 366836 335714 366864 338014
-rect 366928 338014 366988 338042
-rect 367264 338014 367508 338042
-rect 367632 338014 367876 338042
-rect 368000 338014 368152 338042
-rect 366824 335708 366876 335714
-rect 366824 335650 366876 335656
-rect 366088 335640 366140 335646
-rect 366088 335582 366140 335588
-rect 366928 335442 366956 338014
-rect 367480 336734 367508 338014
-rect 367008 336728 367060 336734
-rect 367008 336670 367060 336676
-rect 367468 336728 367520 336734
-rect 367468 336670 367520 336676
-rect 366916 335436 366968 335442
-rect 366916 335378 366968 335384
-rect 367020 7274 367048 336670
-rect 367848 336530 367876 338014
-rect 367836 336524 367888 336530
-rect 367836 336466 367888 336472
-rect 367376 336320 367428 336326
-rect 367376 336262 367428 336268
-rect 367388 331214 367416 336262
-rect 368124 334558 368152 338014
-rect 368308 338014 368368 338042
-rect 368736 338014 368980 338042
-rect 369104 338014 369348 338042
-rect 369472 338014 369716 338042
-rect 368204 336728 368256 336734
-rect 368204 336670 368256 336676
-rect 368112 334552 368164 334558
-rect 368112 334494 368164 334500
-rect 367388 331186 367508 331214
-rect 367480 16574 367508 331186
-rect 367480 16546 367784 16574
-rect 367008 7268 367060 7274
-rect 367008 7210 367060 7216
-rect 367008 5568 367060 5574
-rect 367008 5510 367060 5516
-rect 365812 3256 365864 3262
-rect 365812 3198 365864 3204
-rect 365628 2916 365680 2922
-rect 365628 2858 365680 2864
-rect 365824 480 365852 3198
-rect 367020 480 367048 5510
-rect 367756 490 367784 16546
-rect 368216 7342 368244 336670
-rect 368308 7410 368336 338014
-rect 368952 336666 368980 338014
-rect 368940 336660 368992 336666
-rect 368940 336602 368992 336608
-rect 369320 336326 369348 338014
-rect 369308 336320 369360 336326
-rect 369308 336262 369360 336268
-rect 369688 7478 369716 338014
-rect 369780 338014 369840 338042
-rect 370208 338014 370452 338042
-rect 370576 338014 370820 338042
-rect 370944 338014 371188 338042
-rect 371312 338014 371556 338042
-rect 371680 338014 371924 338042
-rect 372048 338014 372292 338042
-rect 372416 338014 372568 338042
-rect 372784 338014 373028 338042
-rect 373152 338014 373396 338042
-rect 373520 338014 373764 338042
-rect 369780 336818 369808 338014
-rect 369780 336790 369900 336818
-rect 369768 336660 369820 336666
-rect 369768 336602 369820 336608
-rect 369676 7472 369728 7478
-rect 369676 7414 369728 7420
-rect 368296 7404 368348 7410
-rect 368296 7346 368348 7352
-rect 368204 7336 368256 7342
-rect 368204 7278 368256 7284
-rect 369400 3324 369452 3330
-rect 369400 3266 369452 3272
-rect 368032 598 368244 626
-rect 368032 490 368060 598
-rect 345726 -960 345838 480
-rect 346922 -960 347034 480
-rect 348026 -960 348138 480
-rect 349222 -960 349334 480
-rect 350418 -960 350530 480
-rect 351614 -960 351726 480
-rect 352810 -960 352922 480
-rect 354006 -960 354118 480
-rect 355202 -960 355314 480
-rect 356306 -960 356418 480
-rect 357502 -960 357614 480
-rect 358698 -960 358810 480
-rect 359894 -960 360006 480
-rect 361090 -960 361202 480
-rect 362286 -960 362398 480
-rect 363482 -960 363594 480
-rect 364586 -960 364698 480
-rect 365782 -960 365894 480
-rect 366978 -960 367090 480
-rect 367756 462 368060 490
-rect 368216 480 368244 598
-rect 369412 480 369440 3266
-rect 369780 2990 369808 336602
-rect 369872 335986 369900 336790
-rect 369860 335980 369912 335986
-rect 369860 335922 369912 335928
-rect 370424 335918 370452 338014
-rect 370504 336388 370556 336394
-rect 370504 336330 370556 336336
-rect 370412 335912 370464 335918
-rect 370412 335854 370464 335860
-rect 370516 9042 370544 336330
-rect 370792 335354 370820 338014
-rect 370792 335326 371096 335354
-rect 370504 9036 370556 9042
-rect 370504 8978 370556 8984
-rect 370596 8968 370648 8974
-rect 370596 8910 370648 8916
-rect 369768 2984 369820 2990
-rect 369768 2926 369820 2932
-rect 370608 480 370636 8910
-rect 371068 7546 371096 335326
-rect 371056 7540 371108 7546
-rect 371056 7482 371108 7488
-rect 371160 3058 371188 338014
-rect 371332 336184 371384 336190
-rect 371332 336126 371384 336132
-rect 371148 3052 371200 3058
-rect 371148 2994 371200 3000
-rect 371344 490 371372 336126
-rect 371528 335306 371556 338014
-rect 371792 336252 371844 336258
-rect 371792 336194 371844 336200
-rect 371516 335300 371568 335306
-rect 371516 335242 371568 335248
-rect 371804 325694 371832 336194
-rect 371896 335578 371924 338014
-rect 372264 336666 372292 338014
-rect 372540 336734 372568 338014
-rect 372528 336728 372580 336734
-rect 372528 336670 372580 336676
-rect 372252 336660 372304 336666
-rect 372252 336602 372304 336608
-rect 373000 336190 373028 338014
-rect 373368 336598 373396 338014
-rect 373356 336592 373408 336598
-rect 373356 336534 373408 336540
-rect 372988 336184 373040 336190
-rect 372988 336126 373040 336132
-rect 371884 335572 371936 335578
-rect 371884 335514 371936 335520
-rect 372436 335572 372488 335578
-rect 372436 335514 372488 335520
-rect 371804 325666 371924 325694
-rect 371896 6186 371924 325666
-rect 372448 8294 372476 335514
-rect 373736 335354 373764 338014
-rect 373828 338014 373888 338042
-rect 374256 338014 374500 338042
-rect 374624 338014 374868 338042
-rect 374992 338014 375236 338042
-rect 373828 335850 373856 338014
-rect 373908 336592 373960 336598
-rect 373908 336534 373960 336540
-rect 373816 335844 373868 335850
-rect 373816 335786 373868 335792
-rect 373736 335326 373856 335354
-rect 372436 8288 372488 8294
-rect 372436 8230 372488 8236
-rect 371884 6180 371936 6186
-rect 371884 6122 371936 6128
-rect 373828 5642 373856 335326
-rect 373816 5636 373868 5642
-rect 373816 5578 373868 5584
-rect 372896 3392 372948 3398
-rect 372896 3334 372948 3340
-rect 371528 598 371740 626
-rect 371528 490 371556 598
-rect 368174 -960 368286 480
-rect 369370 -960 369482 480
-rect 370566 -960 370678 480
-rect 371344 462 371556 490
-rect 371712 480 371740 598
-rect 372908 480 372936 3334
-rect 373920 3126 373948 336534
-rect 374472 336258 374500 338014
-rect 374460 336252 374512 336258
-rect 374460 336194 374512 336200
-rect 374644 336184 374696 336190
-rect 374644 336126 374696 336132
-rect 374656 333878 374684 336126
-rect 374644 333872 374696 333878
-rect 374644 333814 374696 333820
-rect 374840 325694 374868 338014
-rect 375208 332314 375236 338014
-rect 375300 338014 375360 338042
-rect 375728 338014 375972 338042
-rect 376096 338014 376248 338042
-rect 376464 338014 376616 338042
-rect 376832 338014 377076 338042
-rect 377200 338014 377444 338042
-rect 377568 338014 377812 338042
-rect 375196 332308 375248 332314
-rect 375196 332250 375248 332256
-rect 374840 325666 375236 325694
-rect 375208 5710 375236 325666
-rect 375196 5704 375248 5710
-rect 375196 5646 375248 5652
-rect 375300 4978 375328 338014
-rect 375944 336598 375972 338014
-rect 375932 336592 375984 336598
-rect 375932 336534 375984 336540
-rect 375380 335844 375432 335850
-rect 375380 335786 375432 335792
-rect 375392 333810 375420 335786
-rect 376024 335776 376076 335782
-rect 376024 335718 376076 335724
-rect 375380 333804 375432 333810
-rect 375380 333746 375432 333752
-rect 376036 9042 376064 335718
-rect 376220 332246 376248 338014
-rect 376588 336326 376616 338014
-rect 376668 336592 376720 336598
-rect 376668 336534 376720 336540
-rect 376576 336320 376628 336326
-rect 376576 336262 376628 336268
-rect 376208 332240 376260 332246
-rect 376208 332182 376260 332188
-rect 376024 9036 376076 9042
-rect 376024 8978 376076 8984
-rect 376680 5778 376708 336534
-rect 377048 336258 377076 338014
-rect 377036 336252 377088 336258
-rect 377036 336194 377088 336200
-rect 377416 333742 377444 338014
-rect 377404 333736 377456 333742
-rect 377404 333678 377456 333684
-rect 376668 5772 376720 5778
-rect 376668 5714 376720 5720
-rect 375208 4950 375328 4978
-rect 374092 4480 374144 4486
-rect 374092 4422 374144 4428
-rect 373908 3120 373960 3126
-rect 373908 3062 373960 3068
-rect 374104 480 374132 4422
-rect 375208 3194 375236 4950
-rect 377680 4548 377732 4554
-rect 377680 4490 377732 4496
-rect 375288 4140 375340 4146
-rect 375288 4082 375340 4088
-rect 375196 3188 375248 3194
-rect 375196 3130 375248 3136
-rect 375300 480 375328 4082
-rect 376484 4072 376536 4078
-rect 376484 4014 376536 4020
-rect 376496 480 376524 4014
-rect 377692 480 377720 4490
-rect 377784 3262 377812 338014
-rect 377922 337770 377950 338028
-rect 378304 338014 378548 338042
-rect 378672 338014 378916 338042
-rect 379040 338014 379192 338042
-rect 379316 338014 379468 338042
-rect 379684 338014 379928 338042
-rect 380052 338014 380296 338042
-rect 380420 338014 380572 338042
-rect 377922 337742 377996 337770
-rect 377864 336252 377916 336258
-rect 377864 336194 377916 336200
-rect 377876 5846 377904 336194
-rect 377968 5914 377996 337742
-rect 378520 332178 378548 338014
-rect 378888 336122 378916 338014
-rect 378876 336116 378928 336122
-rect 378876 336058 378928 336064
-rect 378508 332172 378560 332178
-rect 378508 332114 378560 332120
-rect 379164 325694 379192 338014
-rect 379440 332110 379468 338014
-rect 379900 336530 379928 338014
-rect 380268 336598 380296 338014
-rect 380256 336592 380308 336598
-rect 380256 336534 380308 336540
-rect 379888 336524 379940 336530
-rect 379888 336466 379940 336472
-rect 380544 335238 380572 338014
-rect 380774 337770 380802 338028
-rect 381156 338014 381400 338042
-rect 381524 338014 381768 338042
-rect 380774 337742 380848 337770
-rect 380716 336592 380768 336598
-rect 380716 336534 380768 336540
-rect 380624 336524 380676 336530
-rect 380624 336466 380676 336472
-rect 380532 335232 380584 335238
-rect 380532 335174 380584 335180
-rect 379428 332104 379480 332110
-rect 379428 332046 379480 332052
-rect 379164 325666 379468 325694
-rect 378876 6180 378928 6186
-rect 378876 6122 378928 6128
-rect 377956 5908 378008 5914
-rect 377956 5850 378008 5856
-rect 377864 5840 377916 5846
-rect 377864 5782 377916 5788
-rect 377772 3256 377824 3262
-rect 377772 3198 377824 3204
-rect 378888 480 378916 6122
-rect 379440 5982 379468 325666
-rect 379428 5976 379480 5982
-rect 379428 5918 379480 5924
-rect 379980 4004 380032 4010
-rect 379980 3946 380032 3952
-rect 379992 480 380020 3946
-rect 380636 3330 380664 336466
-rect 380728 6050 380756 336534
-rect 380820 336394 380848 337742
-rect 381372 336530 381400 338014
-rect 381360 336524 381412 336530
-rect 381360 336466 381412 336472
-rect 381740 336462 381768 338014
-rect 381832 338014 381892 338042
-rect 382016 338014 382260 338042
-rect 382628 338014 382872 338042
-rect 382996 338014 383240 338042
-rect 383364 338014 383516 338042
-rect 383732 338014 383976 338042
-rect 384100 338014 384344 338042
-rect 384468 338014 384712 338042
-rect 381832 336598 381860 338014
-rect 381820 336592 381872 336598
-rect 381820 336534 381872 336540
-rect 381728 336456 381780 336462
-rect 381728 336398 381780 336404
-rect 380808 336388 380860 336394
-rect 380808 336330 380860 336336
-rect 382016 6798 382044 338014
-rect 382188 336592 382240 336598
-rect 382188 336534 382240 336540
-rect 382096 336524 382148 336530
-rect 382096 336466 382148 336472
-rect 382004 6792 382056 6798
-rect 382004 6734 382056 6740
-rect 382108 6118 382136 336466
-rect 382096 6112 382148 6118
-rect 382096 6054 382148 6060
-rect 380716 6044 380768 6050
-rect 380716 5986 380768 5992
-rect 381176 4616 381228 4622
-rect 381176 4558 381228 4564
-rect 380624 3324 380676 3330
-rect 380624 3266 380676 3272
-rect 381188 480 381216 4558
-rect 382200 3398 382228 336534
-rect 382844 336190 382872 338014
-rect 383212 336258 383240 338014
-rect 383488 336326 383516 338014
-rect 383948 336462 383976 338014
-rect 383936 336456 383988 336462
-rect 383936 336398 383988 336404
-rect 383476 336320 383528 336326
-rect 383476 336262 383528 336268
-rect 382924 336252 382976 336258
-rect 382924 336194 382976 336200
-rect 383200 336252 383252 336258
-rect 383200 336194 383252 336200
-rect 382832 336184 382884 336190
-rect 382832 336126 382884 336132
-rect 382464 336048 382516 336054
-rect 382464 335990 382516 335996
-rect 382372 10328 382424 10334
-rect 382372 10270 382424 10276
-rect 382188 3392 382240 3398
-rect 382188 3334 382240 3340
-rect 382384 480 382412 10270
-rect 382476 6914 382504 335990
-rect 382936 10334 382964 336194
-rect 383568 336184 383620 336190
-rect 383568 336126 383620 336132
-rect 383580 14482 383608 336126
-rect 384316 335102 384344 338014
-rect 384684 336054 384712 338014
-rect 384776 338014 384836 338042
-rect 385204 338014 385356 338042
-rect 385572 338014 385816 338042
-rect 385940 338014 386184 338042
-rect 384672 336048 384724 336054
-rect 384672 335990 384724 335996
-rect 384304 335096 384356 335102
-rect 384304 335038 384356 335044
-rect 383568 14476 383620 14482
-rect 383568 14418 383620 14424
-rect 382924 10328 382976 10334
-rect 382924 10270 382976 10276
-rect 382476 6886 383608 6914
-rect 383580 480 383608 6886
-rect 384776 6662 384804 338014
-rect 384856 336456 384908 336462
-rect 384856 336398 384908 336404
-rect 384868 6730 384896 336398
-rect 385328 332042 385356 338014
-rect 385788 336462 385816 338014
-rect 385776 336456 385828 336462
-rect 385776 336398 385828 336404
-rect 385316 332036 385368 332042
-rect 385316 331978 385368 331984
-rect 386156 325694 386184 338014
-rect 386294 337770 386322 338028
-rect 386676 338014 386920 338042
-rect 387044 338014 387288 338042
-rect 387412 338014 387656 338042
-rect 386294 337742 386368 337770
-rect 386340 330818 386368 337742
-rect 386892 336190 386920 338014
-rect 387260 336462 387288 338014
-rect 387248 336456 387300 336462
-rect 387248 336398 387300 336404
-rect 386880 336184 386932 336190
-rect 386880 336126 386932 336132
-rect 387628 333674 387656 338014
-rect 387720 338014 387780 338042
-rect 388148 338014 388392 338042
-rect 388516 338014 388760 338042
-rect 388884 338014 389036 338042
-rect 389252 338014 389496 338042
-rect 389620 338014 389864 338042
-rect 389988 338014 390140 338042
-rect 387720 336546 387748 338014
-rect 387720 336518 387840 336546
-rect 387708 336456 387760 336462
-rect 387708 336398 387760 336404
-rect 387616 333668 387668 333674
-rect 387616 333610 387668 333616
-rect 386328 330812 386380 330818
-rect 386328 330754 386380 330760
-rect 386156 325666 386368 325694
-rect 385960 8968 386012 8974
-rect 385960 8910 386012 8916
-rect 384856 6724 384908 6730
-rect 384856 6666 384908 6672
-rect 384764 6656 384816 6662
-rect 384764 6598 384816 6604
-rect 384764 4684 384816 4690
-rect 384764 4626 384816 4632
-rect 384776 480 384804 4626
-rect 385972 480 386000 8910
-rect 386340 6594 386368 325666
-rect 386328 6588 386380 6594
-rect 386328 6530 386380 6536
-rect 387720 6526 387748 336398
-rect 387812 336161 387840 336518
-rect 388364 336462 388392 338014
-rect 388352 336456 388404 336462
-rect 388352 336398 388404 336404
-rect 387984 336184 388036 336190
-rect 387798 336152 387854 336161
-rect 387984 336126 388036 336132
-rect 387798 336087 387854 336096
-rect 387996 335034 388024 336126
-rect 388444 335164 388496 335170
-rect 388444 335106 388496 335112
-rect 387984 335028 388036 335034
-rect 387984 334970 388036 334976
-rect 388456 8974 388484 335106
-rect 388732 330750 388760 338014
-rect 389008 336190 389036 338014
-rect 389468 336462 389496 338014
-rect 389088 336456 389140 336462
-rect 389088 336398 389140 336404
-rect 389456 336456 389508 336462
-rect 389456 336398 389508 336404
-rect 388996 336184 389048 336190
-rect 388996 336126 389048 336132
-rect 388996 336048 389048 336054
-rect 388996 335990 389048 335996
-rect 389008 335170 389036 335990
-rect 388996 335164 389048 335170
-rect 388996 335106 389048 335112
-rect 388720 330744 388772 330750
-rect 388720 330686 388772 330692
-rect 388444 8968 388496 8974
-rect 388444 8910 388496 8916
-rect 387708 6520 387760 6526
-rect 387708 6462 387760 6468
-rect 389100 6458 389128 336398
-rect 389836 331974 389864 338014
-rect 390112 334966 390140 338014
-rect 390204 338014 390356 338042
-rect 390724 338014 390968 338042
-rect 391092 338014 391244 338042
-rect 391368 338014 391612 338042
-rect 391736 338014 391888 338042
-rect 392104 338014 392348 338042
-rect 392472 338014 392716 338042
-rect 392840 338014 392992 338042
-rect 390100 334960 390152 334966
-rect 390100 334902 390152 334908
-rect 389824 331968 389876 331974
-rect 389824 331910 389876 331916
-rect 389456 10328 389508 10334
-rect 389456 10270 389508 10276
-rect 389088 6452 389140 6458
-rect 389088 6394 389140 6400
-rect 388260 4752 388312 4758
-rect 388260 4694 388312 4700
-rect 387156 3936 387208 3942
-rect 387156 3878 387208 3884
-rect 387168 480 387196 3878
-rect 388272 480 388300 4694
-rect 389468 480 389496 10270
-rect 390204 6322 390232 338014
-rect 390376 336456 390428 336462
-rect 390376 336398 390428 336404
-rect 390388 6390 390416 336398
-rect 390940 334898 390968 338014
-rect 391216 336054 391244 338014
-rect 391204 336048 391256 336054
-rect 391204 335990 391256 335996
-rect 391584 335354 391612 338014
-rect 391584 335326 391704 335354
-rect 390928 334892 390980 334898
-rect 390928 334834 390980 334840
-rect 390376 6384 390428 6390
-rect 390376 6326 390428 6332
-rect 390192 6316 390244 6322
-rect 390192 6258 390244 6264
-rect 391676 6254 391704 335326
-rect 391860 331906 391888 338014
-rect 392320 334830 392348 338014
-rect 392688 336025 392716 338014
-rect 392674 336016 392730 336025
-rect 392674 335951 392730 335960
-rect 392308 334824 392360 334830
-rect 392308 334766 392360 334772
-rect 391940 334620 391992 334626
-rect 391940 334562 391992 334568
-rect 391848 331900 391900 331906
-rect 391848 331842 391900 331848
-rect 391952 16574 391980 334562
-rect 392964 330682 392992 338014
-rect 393056 338014 393208 338042
-rect 393576 338014 393820 338042
-rect 393944 338014 394188 338042
-rect 394312 338014 394464 338042
-rect 392952 330676 393004 330682
-rect 392952 330618 393004 330624
-rect 391952 16546 392624 16574
-rect 391664 6248 391716 6254
-rect 391664 6190 391716 6196
-rect 391848 5500 391900 5506
-rect 391848 5442 391900 5448
-rect 390652 3868 390704 3874
-rect 390652 3810 390704 3816
-rect 390664 480 390692 3810
-rect 391860 480 391888 5442
-rect 392596 490 392624 16546
-rect 393056 4282 393084 338014
-rect 393792 334762 393820 338014
-rect 394160 335374 394188 338014
-rect 394148 335368 394200 335374
-rect 394148 335310 394200 335316
-rect 393780 334756 393832 334762
-rect 393780 334698 393832 334704
-rect 394436 4350 394464 338014
-rect 394620 338014 394680 338042
-rect 395048 338014 395292 338042
-rect 395416 338014 395660 338042
-rect 395784 338014 395936 338042
-rect 396152 338014 396396 338042
-rect 396520 338014 396764 338042
-rect 396888 338014 397132 338042
-rect 397256 338014 397408 338042
-rect 397624 338014 397868 338042
-rect 397992 338014 398236 338042
-rect 398360 338014 398512 338042
-rect 394516 335368 394568 335374
-rect 394516 335310 394568 335316
-rect 394528 10334 394556 335310
-rect 394620 333606 394648 338014
-rect 394608 333600 394660 333606
-rect 394608 333542 394660 333548
-rect 395264 329186 395292 338014
-rect 395632 335354 395660 338014
-rect 395632 335326 395844 335354
-rect 395252 329180 395304 329186
-rect 395252 329122 395304 329128
-rect 394516 10328 394568 10334
-rect 394516 10270 394568 10276
-rect 395344 5432 395396 5438
-rect 395344 5374 395396 5380
-rect 394424 4344 394476 4350
-rect 394424 4286 394476 4292
-rect 393044 4276 393096 4282
-rect 393044 4218 393096 4224
-rect 394240 3800 394292 3806
-rect 394240 3742 394292 3748
-rect 392872 598 393084 626
-rect 392872 490 392900 598
-rect 371670 -960 371782 480
-rect 372866 -960 372978 480
-rect 374062 -960 374174 480
-rect 375258 -960 375370 480
-rect 376454 -960 376566 480
-rect 377650 -960 377762 480
-rect 378846 -960 378958 480
-rect 379950 -960 380062 480
-rect 381146 -960 381258 480
-rect 382342 -960 382454 480
-rect 383538 -960 383650 480
-rect 384734 -960 384846 480
-rect 385930 -960 386042 480
-rect 387126 -960 387238 480
-rect 388230 -960 388342 480
-rect 389426 -960 389538 480
-rect 390622 -960 390734 480
-rect 391818 -960 391930 480
-rect 392596 462 392900 490
-rect 393056 480 393084 598
-rect 394252 480 394280 3742
-rect 395356 480 395384 5374
-rect 395816 4418 395844 335326
-rect 395908 333538 395936 338014
-rect 395896 333532 395948 333538
-rect 395896 333474 395948 333480
-rect 396368 330614 396396 338014
-rect 396356 330608 396408 330614
-rect 396356 330550 396408 330556
-rect 396736 325694 396764 338014
-rect 397104 334694 397132 338014
-rect 397092 334688 397144 334694
-rect 397092 334630 397144 334636
-rect 397380 329118 397408 338014
-rect 397840 335374 397868 338014
-rect 397828 335368 397880 335374
-rect 397828 335310 397880 335316
-rect 398208 334626 398236 338014
-rect 398196 334620 398248 334626
-rect 398196 334562 398248 334568
-rect 398484 333946 398512 338014
-rect 398668 338014 398728 338042
-rect 399096 338014 399340 338042
-rect 399464 338014 399708 338042
-rect 398564 335368 398616 335374
-rect 398564 335310 398616 335316
-rect 398472 333940 398524 333946
-rect 398472 333882 398524 333888
-rect 397368 329112 397420 329118
-rect 397368 329054 397420 329060
-rect 396736 325666 397132 325694
-rect 396540 9104 396592 9110
-rect 396540 9046 396592 9052
-rect 395804 4412 395856 4418
-rect 395804 4354 395856 4360
-rect 396552 480 396580 9046
-rect 397104 4486 397132 325666
-rect 398576 4554 398604 335310
-rect 398668 4622 398696 338014
-rect 399312 333470 399340 338014
-rect 399300 333464 399352 333470
-rect 399300 333406 399352 333412
-rect 399680 329254 399708 338014
-rect 399818 337770 399846 338028
-rect 400140 338014 400200 338042
-rect 400568 338014 400812 338042
-rect 400936 338014 401180 338042
-rect 401304 338014 401548 338042
-rect 401672 338014 401916 338042
-rect 402040 338014 402284 338042
-rect 402408 338014 402652 338042
-rect 402776 338014 402928 338042
-rect 403144 338014 403296 338042
-rect 403420 338014 403664 338042
-rect 403788 338014 404032 338042
-rect 399818 337742 399892 337770
-rect 399668 329248 399720 329254
-rect 399668 329190 399720 329196
-rect 398932 5364 398984 5370
-rect 398932 5306 398984 5312
-rect 398656 4616 398708 4622
-rect 398656 4558 398708 4564
-rect 398564 4548 398616 4554
-rect 398564 4490 398616 4496
-rect 397092 4480 397144 4486
-rect 397092 4422 397144 4428
-rect 397736 3732 397788 3738
-rect 397736 3674 397788 3680
-rect 397748 480 397776 3674
-rect 398944 480 398972 5306
-rect 399864 4690 399892 337742
-rect 400140 333402 400168 338014
-rect 400128 333396 400180 333402
-rect 400128 333338 400180 333344
-rect 400784 330478 400812 338014
-rect 401152 335354 401180 338014
-rect 401152 335326 401364 335354
-rect 400772 330472 400824 330478
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-rect 400128 5296 400180 5302
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-rect 399852 4684 399904 4690
-rect 399852 4626 399904 4632
-rect 400140 480 400168 5238
-rect 401336 4758 401364 335326
-rect 401520 333266 401548 338014
-rect 401508 333260 401560 333266
-rect 401508 333202 401560 333208
-rect 401888 330546 401916 338014
-rect 402256 335374 402284 338014
-rect 402244 335368 402296 335374
-rect 402244 335310 402296 335316
-rect 401876 330540 401928 330546
-rect 401876 330482 401928 330488
-rect 402624 8226 402652 338014
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-rect 402704 335310 402756 335316
-rect 402612 8220 402664 8226
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-rect 402716 5506 402744 335310
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-rect 402796 330482 402848 330488
-rect 402704 5500 402756 5506
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-rect 402520 5228 402572 5234
-rect 402520 5170 402572 5176
-rect 401324 4752 401376 4758
-rect 401324 4694 401376 4700
-rect 401324 3664 401376 3670
-rect 401324 3606 401376 3612
-rect 401336 480 401364 3606
-rect 402532 480 402560 5170
-rect 402808 4146 402836 330482
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-rect 402796 4082 402848 4088
-rect 402900 4078 402928 338014
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-rect 403256 335368 403308 335374
-rect 403256 335310 403308 335316
-rect 403636 325694 403664 338014
-rect 404004 330478 404032 338014
-rect 404142 337770 404170 338028
-rect 404524 338014 404768 338042
-rect 404892 338014 405136 338042
-rect 405260 338014 405412 338042
-rect 404142 337742 404216 337770
-rect 404084 335368 404136 335374
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-rect 403992 330472 404044 330478
-rect 403992 330414 404044 330420
-rect 403636 325666 404032 325694
-rect 404004 8158 404032 325666
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-rect 404096 5438 404124 335310
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-rect 404084 5374 404136 5380
-rect 404188 5370 404216 337742
-rect 404740 335374 404768 338014
-rect 404728 335368 404780 335374
-rect 404728 335310 404780 335316
-rect 405108 330478 405136 338014
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-rect 405476 338014 405628 338042
-rect 405996 338014 406240 338042
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-rect 405280 335368 405332 335374
-rect 405280 335310 405332 335316
-rect 405372 335368 405424 335374
-rect 405372 335310 405424 335316
-rect 404268 330472 404320 330478
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-rect 405096 330472 405148 330478
-rect 405096 330414 405148 330420
-rect 404176 5364 404228 5370
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-rect 403624 5160 403676 5166
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-rect 402888 4072 402940 4078
-rect 402888 4014 402940 4020
-rect 403636 480 403664 5102
-rect 404280 4010 404308 330414
-rect 405292 325694 405320 335310
-rect 405292 325666 405412 325694
-rect 405384 8090 405412 325666
-rect 405372 8084 405424 8090
-rect 405372 8026 405424 8032
-rect 405476 8022 405504 338014
-rect 405556 335368 405608 335374
-rect 405556 335310 405608 335316
-rect 405464 8016 405516 8022
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-rect 405568 5302 405596 335310
-rect 406212 330478 406240 338014
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-rect 406718 337770 406746 338028
-rect 406948 338014 407100 338042
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-rect 408204 338014 408448 338042
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-rect 408940 338014 409184 338042
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-rect 406718 337742 406792 337770
-rect 406568 335368 406620 335374
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-rect 405648 330472 405700 330478
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-rect 406200 330472 406252 330478
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-rect 405556 5296 405608 5302
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-rect 404268 4004 404320 4010
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-rect 405660 3942 405688 330414
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-rect 406844 335368 406896 335374
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-rect 406752 7948 406804 7954
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-rect 406016 5092 406068 5098
-rect 406016 5034 406068 5040
-rect 405648 3936 405700 3942
-rect 405648 3878 405700 3884
-rect 404820 3596 404872 3602
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-rect 404832 480 404860 3538
-rect 406028 480 406056 5034
-rect 406948 3806 406976 338014
-rect 407684 335374 407712 338014
-rect 407672 335368 407724 335374
-rect 408052 335354 408080 338014
-rect 408316 335368 408368 335374
-rect 408052 335326 408264 335354
-rect 407672 335310 407724 335316
-rect 407028 330472 407080 330478
-rect 407028 330414 407080 330420
-rect 407040 3874 407068 330414
-rect 408236 7886 408264 335326
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-rect 408224 7880 408276 7886
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-rect 408328 5166 408356 335310
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-rect 407212 4966 407264 4972
-rect 407028 3868 407080 3874
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-rect 406936 3800 406988 3806
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-rect 407224 480 407252 4966
-rect 408420 3738 408448 338014
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-rect 408776 330472 408828 330478
-rect 408776 330414 408828 330420
-rect 409156 325694 409184 338014
-rect 409524 335374 409552 338014
-rect 409616 338014 409676 338042
-rect 410044 338014 410288 338042
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-rect 409512 335368 409564 335374
-rect 409512 335310 409564 335316
-rect 409156 325666 409552 325694
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-rect 409512 7754 409564 7760
-rect 409616 5030 409644 338014
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-rect 409696 330472 409748 330478
-rect 409696 330414 409748 330420
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-rect 409604 5024 409656 5030
-rect 409604 4966 409656 4972
-rect 409604 4888 409656 4894
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-rect 408408 3732 408460 3738
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-rect 408420 480 408448 3470
-rect 409616 480 409644 4830
-rect 409800 3670 409828 335310
-rect 410260 330478 410288 338014
-rect 410248 330472 410300 330478
-rect 410248 330414 410300 330420
-rect 410628 330410 410656 338014
-rect 410720 338014 410780 338042
-rect 410904 338014 411148 338042
-rect 411516 338014 411760 338042
-rect 411884 338014 412128 338042
-rect 410720 335374 410748 338014
-rect 410708 335368 410760 335374
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-rect 410616 330404 410668 330410
-rect 410616 330346 410668 330352
-rect 410904 7682 410932 338014
-rect 411076 335368 411128 335374
-rect 411076 335310 411128 335316
-rect 410984 330472 411036 330478
-rect 410984 330414 411036 330420
-rect 410996 7750 411024 330414
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-rect 410984 7686 411036 7692
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-rect 410892 7618 410944 7624
-rect 411088 4962 411116 335310
-rect 411732 330478 411760 338014
-rect 412100 335374 412128 338014
-rect 412238 337770 412266 338028
-rect 412560 338014 412620 338042
-rect 412988 338014 413232 338042
-rect 413356 338014 413600 338042
-rect 413724 338014 413968 338042
-rect 414092 338014 414336 338042
-rect 414460 338014 414704 338042
-rect 412238 337742 412312 337770
-rect 412088 335368 412140 335374
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-rect 411720 330472 411772 330478
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-rect 411168 330404 411220 330410
-rect 411168 330346 411220 330352
-rect 410800 4956 410852 4962
-rect 410800 4898 410852 4904
-rect 411076 4956 411128 4962
-rect 411076 4898 411128 4904
-rect 409788 3664 409840 3670
-rect 409788 3606 409840 3612
-rect 410812 480 410840 4898
-rect 411180 3602 411208 330346
-rect 412284 6186 412312 337742
-rect 412364 335368 412416 335374
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-rect 412272 6180 412324 6186
-rect 412272 6122 412324 6128
-rect 412376 4894 412404 335310
-rect 412456 330472 412508 330478
-rect 412456 330414 412508 330420
-rect 412364 4888 412416 4894
-rect 412364 4830 412416 4836
-rect 411168 3596 411220 3602
-rect 411168 3538 411220 3544
-rect 412468 3534 412496 330414
-rect 412456 3528 412508 3534
-rect 412456 3470 412508 3476
-rect 412560 3466 412588 338014
-rect 413204 335646 413232 338014
-rect 413192 335640 413244 335646
-rect 413192 335582 413244 335588
-rect 413572 335354 413600 338014
-rect 413836 335640 413888 335646
-rect 413836 335582 413888 335588
-rect 413572 335326 413784 335354
-rect 413756 7614 413784 335326
-rect 413744 7608 413796 7614
-rect 413744 7550 413796 7556
-rect 413848 4826 413876 335582
-rect 413100 4820 413152 4826
-rect 413100 4762 413152 4768
-rect 413836 4820 413888 4826
-rect 413836 4762 413888 4768
-rect 411904 3460 411956 3466
-rect 411904 3402 411956 3408
-rect 412548 3460 412600 3466
-rect 412548 3402 412600 3408
-rect 411916 480 411944 3402
-rect 413112 480 413140 4762
-rect 413940 3777 413968 338014
-rect 414308 330410 414336 338014
-rect 414676 330478 414704 338014
-rect 414768 338014 414828 338042
-rect 414768 335646 414796 338014
-rect 414756 335640 414808 335646
-rect 414756 335582 414808 335588
-rect 414664 330472 414716 330478
-rect 414664 330414 414716 330420
-rect 414296 330404 414348 330410
-rect 414296 330346 414348 330352
-rect 414952 20670 414980 457286
-rect 417436 431934 417464 460498
-rect 435364 460488 435416 460494
-rect 435364 460430 435416 460436
-rect 432604 460148 432656 460154
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-rect 431224 460080 431276 460086
-rect 431224 460022 431276 460028
-rect 418804 458992 418856 458998
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-rect 417424 431928 417476 431934
-rect 417424 431870 417476 431876
-rect 418816 353258 418844 458934
-rect 428464 458652 428516 458658
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-rect 421564 457564 421616 457570
-rect 421564 457506 421616 457512
-rect 421576 405686 421604 457506
-rect 425704 457428 425756 457434
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-rect 421564 405680 421616 405686
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-rect 425716 379506 425744 457370
-rect 425704 379500 425756 379506
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-rect 418804 353252 418856 353258
-rect 418804 353194 418856 353200
-rect 417514 336152 417570 336161
-rect 417514 336087 417570 336096
-rect 415216 335640 415268 335646
-rect 415216 335582 415268 335588
-rect 415124 330472 415176 330478
-rect 415124 330414 415176 330420
-rect 414940 20664 414992 20670
-rect 414940 20606 414992 20612
-rect 414296 7064 414348 7070
-rect 414296 7006 414348 7012
-rect 413926 3768 413982 3777
-rect 413926 3703 413982 3712
-rect 414308 480 414336 7006
-rect 415136 3505 415164 330414
-rect 415122 3496 415178 3505
-rect 415122 3431 415178 3440
-rect 415228 3369 415256 335582
-rect 417424 335504 417476 335510
-rect 417424 335446 417476 335452
-rect 415308 330404 415360 330410
-rect 415308 330346 415360 330352
-rect 415320 3641 415348 330346
-rect 417436 9654 417464 335446
-rect 417424 9648 417476 9654
-rect 417424 9590 417476 9596
-rect 417528 9042 417556 336087
-rect 425060 335708 425112 335714
-rect 425060 335650 425112 335656
-rect 418160 335572 418212 335578
-rect 418160 335514 418212 335520
-rect 418172 16574 418200 335514
-rect 418804 335436 418856 335442
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-rect 418172 16546 418568 16574
-rect 416688 9036 416740 9042
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-rect 417516 9036 417568 9042
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-rect 415306 3632 415362 3641
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-rect 415214 3360 415270 3369
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-rect 415492 2848 415544 2854
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-rect 415504 480 415532 2790
-rect 416700 480 416728 8978
-rect 417884 7132 417936 7138
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-rect 417896 480 417924 7074
-rect 418540 490 418568 16546
-rect 418816 9110 418844 335378
-rect 421564 335368 421616 335374
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-rect 420184 9648 420236 9654
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-rect 418804 9104 418856 9110
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-rect 418816 598 419028 626
-rect 418816 490 418844 598
-rect 393014 -960 393126 480
-rect 394210 -960 394322 480
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-rect 400098 -960 400210 480
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-rect 409574 -960 409686 480
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-rect 411874 -960 411986 480
-rect 413070 -960 413182 480
-rect 414266 -960 414378 480
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-rect 418540 462 418844 490
-rect 419000 480 419028 598
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-rect 421576 8362 421604 335310
-rect 425072 16574 425100 335650
-rect 428476 325650 428504 458594
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-rect 428464 325644 428516 325650
-rect 428464 325586 428516 325592
-rect 425072 16546 425744 16574
-rect 421564 8356 421616 8362
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-rect 421380 7200 421432 7206
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-rect 421392 480 421420 7142
-rect 422576 2916 422628 2922
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-rect 422588 480 422616 2858
-rect 423784 480 423812 8298
-rect 424968 7268 425020 7274
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-rect 424980 480 425008 7210
-rect 425716 490 425744 16546
-rect 427268 9104 427320 9110
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-rect 425992 598 426204 626
-rect 425992 490 426020 598
-rect 418958 -960 419070 480
-rect 420154 -960 420266 480
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-rect 425716 462 426020 490
-rect 426176 480 426204 598
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-rect 428464 7336 428516 7342
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-rect 428476 480 428504 7278
-rect 429212 490 429240 335718
-rect 430580 334552 430632 334558
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-rect 431236 313274 431264 460022
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-rect 543434 703520 543546 704960
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-rect 494808 703474 494836 703520
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-rect 543464 700664 543516 700670
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-rect 494060 460352 494112 460358
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-rect 558932 460222 558960 702406
-rect 580170 697232 580226 697241
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-rect 580170 537840 580226 537849
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-rect 558920 460216 558972 460222
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-rect 580264 458856 580316 458862
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-rect 579816 456890 579844 458079
-rect 579804 456884 579856 456890
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-rect 580172 431928 580224 431934
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-rect 435364 419484 435416 419490
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-rect 579620 405680 579672 405686
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-rect 579632 404977 579660 405622
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-rect 580172 379500 580224 379506
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-rect 432604 365696 432656 365702
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-rect 580172 365696 580224 365702
-rect 580172 365638 580224 365644
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-rect 580170 365120 580226 365129
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-rect 580172 353252 580224 353258
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-rect 439504 336728 439556 336734
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-rect 436100 335980 436152 335986
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-rect 435364 335912 435416 335918
-rect 435364 335854 435416 335860
-rect 432604 335844 432656 335850
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-rect 431224 313268 431276 313274
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-rect 430592 16546 430896 16574
-rect 429488 598 429700 626
-rect 429488 490 429516 598
-rect 426134 -960 426246 480
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-rect 428434 -960 428546 480
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-rect 430868 480 430896 16546
-rect 432616 7546 432644 335786
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-rect 436112 16574 436140 335922
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-rect 432604 7540 432656 7546
-rect 432604 7482 432656 7488
-rect 434444 7540 434496 7546
-rect 434444 7482 434496 7488
-rect 435364 7540 435416 7546
-rect 435364 7482 435416 7488
-rect 432052 7404 432104 7410
-rect 432052 7346 432104 7352
-rect 432064 480 432092 7346
-rect 433248 2984 433300 2990
-rect 433248 2926 433300 2932
-rect 433260 480 433288 2926
-rect 434456 480 434484 7482
-rect 435548 7336 435600 7342
-rect 435548 7278 435600 7284
-rect 435560 480 435588 7278
-rect 436756 480 436784 16546
-rect 439516 7546 439544 336670
-rect 443000 336660 443052 336666
-rect 443000 336602 443052 336608
-rect 440332 335300 440384 335306
-rect 440332 335242 440384 335248
-rect 440344 11762 440372 335242
-rect 443012 16574 443040 336602
-rect 449900 336592 449952 336598
-rect 449900 336534 449952 336540
-rect 445760 333872 445812 333878
-rect 445760 333814 445812 333820
-rect 443012 16546 443408 16574
-rect 440332 11756 440384 11762
-rect 440332 11698 440384 11704
-rect 441528 11756 441580 11762
-rect 441528 11698 441580 11704
-rect 437940 7540 437992 7546
-rect 437940 7482 437992 7488
-rect 439504 7540 439556 7546
-rect 439504 7482 439556 7488
-rect 437952 480 437980 7482
-rect 439136 7404 439188 7410
-rect 439136 7346 439188 7352
-rect 439148 480 439176 7346
-rect 440332 3052 440384 3058
-rect 440332 2994 440384 3000
-rect 440344 480 440372 2994
-rect 441540 480 441568 11698
-rect 442632 8288 442684 8294
-rect 442632 8230 442684 8236
-rect 442644 480 442672 8230
-rect 443380 490 443408 16546
-rect 445024 7540 445076 7546
-rect 445024 7482 445076 7488
-rect 443656 598 443868 626
-rect 443656 490 443684 598
-rect 429630 -960 429742 480
-rect 430826 -960 430938 480
-rect 432022 -960 432134 480
-rect 433218 -960 433330 480
-rect 434414 -960 434526 480
-rect 435518 -960 435630 480
-rect 436714 -960 436826 480
-rect 437910 -960 438022 480
-rect 439106 -960 439218 480
-rect 440302 -960 440414 480
-rect 441498 -960 441610 480
-rect 442602 -960 442714 480
-rect 443380 462 443684 490
-rect 443840 480 443868 598
-rect 445036 480 445064 7482
-rect 445772 490 445800 333814
-rect 448520 333804 448572 333810
-rect 448520 333746 448572 333752
-rect 448532 3126 448560 333746
-rect 449912 16574 449940 336534
-rect 456800 336524 456852 336530
-rect 456800 336466 456852 336472
-rect 452660 332308 452712 332314
-rect 452660 332250 452712 332256
-rect 452672 16574 452700 332250
-rect 449912 16546 450952 16574
-rect 452672 16546 453344 16574
-rect 448612 5636 448664 5642
-rect 448612 5578 448664 5584
-rect 447416 3120 447468 3126
-rect 447416 3062 447468 3068
-rect 448520 3120 448572 3126
-rect 448520 3062 448572 3068
-rect 446048 598 446260 626
-rect 446048 490 446076 598
-rect 443798 -960 443910 480
-rect 444994 -960 445106 480
-rect 445772 462 446076 490
-rect 446232 480 446260 598
-rect 447428 480 447456 3062
-rect 448624 480 448652 5578
-rect 449808 3120 449860 3126
-rect 449808 3062 449860 3068
-rect 449820 480 449848 3062
-rect 450924 480 450952 16546
-rect 452108 5704 452160 5710
-rect 452108 5646 452160 5652
-rect 452120 480 452148 5646
-rect 453316 480 453344 16546
-rect 455696 5772 455748 5778
-rect 455696 5714 455748 5720
-rect 454500 3188 454552 3194
-rect 454500 3130 454552 3136
-rect 454512 480 454540 3130
-rect 455708 480 455736 5714
-rect 456812 3194 456840 336466
-rect 465080 336456 465132 336462
-rect 465080 336398 465132 336404
-rect 459560 333736 459612 333742
-rect 459560 333678 459612 333684
-rect 456892 332240 456944 332246
-rect 456892 332182 456944 332188
-rect 456800 3188 456852 3194
-rect 456800 3130 456852 3136
-rect 456904 480 456932 332182
-rect 459572 16574 459600 333678
-rect 463700 332172 463752 332178
-rect 463700 332114 463752 332120
-rect 463712 16574 463740 332114
-rect 465092 16574 465120 336398
-rect 471980 336388 472032 336394
-rect 471980 336330 472032 336336
-rect 470600 335232 470652 335238
-rect 470600 335174 470652 335180
-rect 466460 332104 466512 332110
-rect 466460 332046 466512 332052
-rect 466472 16574 466500 332046
-rect 459572 16546 459968 16574
-rect 463712 16546 464016 16574
-rect 465092 16546 465212 16574
-rect 466472 16546 467512 16574
-rect 459192 5840 459244 5846
-rect 459192 5782 459244 5788
-rect 458088 3188 458140 3194
-rect 458088 3130 458140 3136
-rect 458100 480 458128 3130
-rect 459204 480 459232 5782
-rect 459940 490 459968 16546
-rect 462780 5908 462832 5914
-rect 462780 5850 462832 5856
-rect 461584 3256 461636 3262
-rect 461584 3198 461636 3204
-rect 460216 598 460428 626
-rect 460216 490 460244 598
-rect 446190 -960 446302 480
-rect 447386 -960 447498 480
-rect 448582 -960 448694 480
-rect 449778 -960 449890 480
-rect 450882 -960 450994 480
-rect 452078 -960 452190 480
-rect 453274 -960 453386 480
-rect 454470 -960 454582 480
-rect 455666 -960 455778 480
-rect 456862 -960 456974 480
-rect 458058 -960 458170 480
-rect 459162 -960 459274 480
-rect 459940 462 460244 490
-rect 460400 480 460428 598
-rect 461596 480 461624 3198
-rect 462792 480 462820 5850
-rect 463988 480 464016 16546
-rect 465184 480 465212 16546
-rect 466276 5976 466328 5982
-rect 466276 5918 466328 5924
-rect 466288 480 466316 5918
-rect 467484 480 467512 16546
-rect 469864 6044 469916 6050
-rect 469864 5986 469916 5992
-rect 468668 3324 468720 3330
-rect 468668 3266 468720 3272
-rect 468680 480 468708 3266
-rect 469876 480 469904 5986
-rect 470612 490 470640 335174
-rect 471992 16574 472020 336330
-rect 475384 336320 475436 336326
-rect 475384 336262 475436 336268
-rect 471992 16546 472296 16574
-rect 470888 598 471100 626
-rect 470888 490 470916 598
-rect 460358 -960 460470 480
-rect 461554 -960 461666 480
-rect 462750 -960 462862 480
-rect 463946 -960 464058 480
-rect 465142 -960 465254 480
-rect 466246 -960 466358 480
-rect 467442 -960 467554 480
-rect 468638 -960 468750 480
-rect 469834 -960 469946 480
-rect 470612 462 470916 490
-rect 471072 480 471100 598
-rect 472268 480 472296 16546
-rect 474556 8968 474608 8974
-rect 474556 8910 474608 8916
-rect 473452 6112 473504 6118
-rect 473452 6054 473504 6060
-rect 473464 480 473492 6054
-rect 474568 480 474596 8910
-rect 475396 5574 475424 336262
-rect 478880 336252 478932 336258
-rect 478880 336194 478932 336200
-rect 478144 14476 478196 14482
-rect 478144 14418 478196 14424
-rect 476948 6792 477000 6798
-rect 476948 6734 477000 6740
-rect 475384 5568 475436 5574
-rect 475384 5510 475436 5516
-rect 475752 3392 475804 3398
-rect 475752 3334 475804 3340
-rect 475764 480 475792 3334
-rect 476960 480 476988 6734
-rect 478156 480 478184 14418
-rect 478892 490 478920 336194
-rect 486424 336184 486476 336190
-rect 486424 336126 486476 336132
-rect 483020 335164 483072 335170
-rect 483020 335106 483072 335112
-rect 481640 335096 481692 335102
-rect 481640 335038 481692 335044
-rect 481652 16574 481680 335038
-rect 483032 16574 483060 335106
-rect 485780 332036 485832 332042
-rect 485780 331978 485832 331984
-rect 485044 329248 485096 329254
-rect 485044 329190 485096 329196
-rect 481652 16546 482416 16574
-rect 483032 16546 484072 16574
-rect 481732 6724 481784 6730
-rect 481732 6666 481784 6672
-rect 480536 5568 480588 5574
-rect 480536 5510 480588 5516
-rect 479168 598 479380 626
-rect 479168 490 479196 598
-rect 471030 -960 471142 480
-rect 472226 -960 472338 480
-rect 473422 -960 473534 480
-rect 474526 -960 474638 480
-rect 475722 -960 475834 480
-rect 476918 -960 477030 480
-rect 478114 -960 478226 480
-rect 478892 462 479196 490
-rect 479352 480 479380 598
-rect 480548 480 480576 5510
-rect 481744 480 481772 6666
-rect 482388 490 482416 16546
-rect 482664 598 482876 626
-rect 482664 490 482692 598
-rect 479310 -960 479422 480
-rect 480506 -960 480618 480
-rect 481702 -960 481814 480
-rect 482388 462 482692 490
-rect 482848 480 482876 598
-rect 484044 480 484072 16546
-rect 485056 3330 485084 329190
-rect 485792 16574 485820 331978
-rect 485792 16546 486372 16574
-rect 485228 6656 485280 6662
-rect 485228 6598 485280 6604
-rect 485044 3324 485096 3330
-rect 485044 3266 485096 3272
-rect 485240 480 485268 6598
-rect 486344 3482 486372 16546
-rect 486436 5574 486464 336126
-rect 497464 336116 497516 336122
-rect 497464 336058 497516 336064
-rect 490012 335028 490064 335034
-rect 490012 334970 490064 334976
-rect 489184 330812 489236 330818
-rect 489184 330754 489236 330760
-rect 488816 6588 488868 6594
-rect 488816 6530 488868 6536
-rect 486424 5568 486476 5574
-rect 486424 5510 486476 5516
-rect 487620 5568 487672 5574
-rect 487620 5510 487672 5516
-rect 486344 3454 486464 3482
-rect 486436 480 486464 3454
-rect 487632 480 487660 5510
-rect 488828 480 488856 6530
-rect 489196 3398 489224 330754
-rect 490024 16574 490052 334970
-rect 492680 333668 492732 333674
-rect 492680 333610 492732 333616
-rect 492692 16574 492720 333610
-rect 496820 330744 496872 330750
-rect 496820 330686 496872 330692
-rect 496832 16574 496860 330686
-rect 490024 16546 490696 16574
-rect 492692 16546 493088 16574
-rect 496832 16546 497136 16574
-rect 489184 3392 489236 3398
-rect 489184 3334 489236 3340
-rect 489920 3392 489972 3398
-rect 489920 3334 489972 3340
-rect 489932 480 489960 3334
-rect 490668 490 490696 16546
-rect 492312 6520 492364 6526
-rect 492312 6462 492364 6468
-rect 490944 598 491156 626
-rect 490944 490 490972 598
-rect 482806 -960 482918 480
-rect 484002 -960 484114 480
-rect 485198 -960 485310 480
-rect 486394 -960 486506 480
-rect 487590 -960 487702 480
-rect 488786 -960 488898 480
-rect 489890 -960 490002 480
-rect 490668 462 490972 490
-rect 491128 480 491156 598
-rect 492324 480 492352 6462
-rect 493060 490 493088 16546
-rect 494704 9036 494756 9042
-rect 494704 8978 494756 8984
-rect 493336 598 493548 626
-rect 493336 490 493364 598
-rect 491086 -960 491198 480
-rect 492282 -960 492394 480
-rect 493060 462 493364 490
-rect 493520 480 493548 598
-rect 494716 480 494744 8978
-rect 495900 6452 495952 6458
-rect 495900 6394 495952 6400
-rect 495912 480 495940 6394
-rect 497108 480 497136 16546
-rect 497476 5574 497504 336058
-rect 504364 336048 504416 336054
-rect 504364 335990 504416 335996
-rect 507122 336016 507178 336025
-rect 500960 334960 501012 334966
-rect 500960 334902 501012 334908
-rect 499580 331968 499632 331974
-rect 499580 331910 499632 331916
-rect 499592 16574 499620 331910
-rect 500972 16574 501000 334902
-rect 502984 334892 503036 334898
-rect 502984 334834 503036 334840
-rect 499592 16546 500632 16574
-rect 500972 16546 501368 16574
-rect 499396 6384 499448 6390
-rect 499396 6326 499448 6332
-rect 497464 5568 497516 5574
-rect 497464 5510 497516 5516
-rect 498200 5568 498252 5574
-rect 498200 5510 498252 5516
-rect 498212 480 498240 5510
-rect 499408 480 499436 6326
-rect 500604 480 500632 16546
-rect 501340 490 501368 16546
-rect 502892 6316 502944 6322
-rect 502892 6258 502944 6264
-rect 502904 3210 502932 6258
-rect 502996 3330 503024 334834
-rect 504376 5574 504404 335990
-rect 507122 335951 507178 335960
-rect 506480 331900 506532 331906
-rect 506480 331842 506532 331848
-rect 506492 16574 506520 331842
-rect 506492 16546 507072 16574
-rect 506480 6248 506532 6254
-rect 506480 6190 506532 6196
-rect 504364 5568 504416 5574
-rect 504364 5510 504416 5516
-rect 505376 5568 505428 5574
-rect 505376 5510 505428 5516
-rect 502984 3324 503036 3330
-rect 502984 3266 503036 3272
-rect 504180 3324 504232 3330
-rect 504180 3266 504232 3272
-rect 502904 3182 503024 3210
-rect 501616 598 501828 626
-rect 501616 490 501644 598
-rect 493478 -960 493590 480
-rect 494674 -960 494786 480
-rect 495870 -960 495982 480
-rect 497066 -960 497178 480
-rect 498170 -960 498282 480
-rect 499366 -960 499478 480
-rect 500562 -960 500674 480
-rect 501340 462 501644 490
-rect 501800 480 501828 598
-rect 502996 480 503024 3182
-rect 504192 480 504220 3266
-rect 505388 480 505416 5510
-rect 506492 480 506520 6190
-rect 507044 626 507072 16546
-rect 507136 5574 507164 335951
-rect 507860 334824 507912 334830
-rect 507860 334766 507912 334772
-rect 507872 16574 507900 334766
-rect 512644 334756 512696 334762
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-rect 510620 330676 510672 330682
-rect 510620 330618 510672 330624
-rect 510632 16574 510660 330618
-rect 507872 16546 508912 16574
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-rect 507124 5510 507176 5516
-rect 507044 598 507256 626
-rect 507228 490 507256 598
-rect 507504 598 507716 626
-rect 507504 490 507532 598
-rect 501758 -960 501870 480
-rect 502954 -960 503066 480
-rect 504150 -960 504262 480
-rect 505346 -960 505458 480
-rect 506450 -960 506562 480
-rect 507228 462 507532 490
-rect 507688 480 507716 598
-rect 508884 480 508912 16546
-rect 510068 5568 510120 5574
-rect 510068 5510 510120 5516
-rect 510080 480 510108 5510
-rect 511276 480 511304 16546
-rect 512460 4276 512512 4282
-rect 512460 4218 512512 4224
-rect 512472 480 512500 4218
-rect 512656 3194 512684 334698
-rect 522304 334688 522356 334694
-rect 522304 334630 522356 334636
-rect 515404 333600 515456 333606
-rect 515404 333542 515456 333548
-rect 514760 10328 514812 10334
-rect 514760 10270 514812 10276
-rect 512644 3188 512696 3194
-rect 512644 3130 512696 3136
-rect 513564 3188 513616 3194
-rect 513564 3130 513616 3136
-rect 513576 480 513604 3130
-rect 514772 480 514800 10270
-rect 515416 3330 515444 333542
-rect 520280 333532 520332 333538
-rect 520280 333474 520332 333480
-rect 519544 330608 519596 330614
-rect 519544 330550 519596 330556
-rect 517520 329180 517572 329186
-rect 517520 329122 517572 329128
-rect 517532 16574 517560 329122
-rect 519556 16574 519584 330550
-rect 517532 16546 517928 16574
-rect 519556 16546 519676 16574
-rect 515956 4344 516008 4350
-rect 515956 4286 516008 4292
-rect 515404 3324 515456 3330
-rect 515404 3266 515456 3272
-rect 515968 480 515996 4286
-rect 517152 3324 517204 3330
-rect 517152 3266 517204 3272
-rect 517164 480 517192 3266
-rect 517900 490 517928 16546
-rect 519544 4412 519596 4418
-rect 519544 4354 519596 4360
-rect 518176 598 518388 626
-rect 518176 490 518204 598
-rect 507646 -960 507758 480
-rect 508842 -960 508954 480
-rect 510038 -960 510150 480
-rect 511234 -960 511346 480
-rect 512430 -960 512542 480
-rect 513534 -960 513646 480
-rect 514730 -960 514842 480
-rect 515926 -960 516038 480
-rect 517122 -960 517234 480
-rect 517900 462 518204 490
-rect 518360 480 518388 598
-rect 519556 480 519584 4354
-rect 519648 3330 519676 16546
-rect 519636 3324 519688 3330
-rect 519636 3266 519688 3272
-rect 520292 490 520320 333474
-rect 522316 3330 522344 334630
-rect 526444 334620 526496 334626
-rect 526444 334562 526496 334568
-rect 524420 329112 524472 329118
-rect 524420 329054 524472 329060
-rect 524432 16574 524460 329054
-rect 524432 16546 525472 16574
-rect 523040 4480 523092 4486
-rect 523040 4422 523092 4428
-rect 521844 3324 521896 3330
-rect 521844 3266 521896 3272
-rect 522304 3324 522356 3330
-rect 522304 3266 522356 3272
-rect 520568 598 520780 626
-rect 520568 490 520596 598
-rect 518318 -960 518430 480
-rect 519514 -960 519626 480
-rect 520292 462 520596 490
-rect 520752 480 520780 598
-rect 521856 480 521884 3266
-rect 523052 480 523080 4422
-rect 524236 3324 524288 3330
-rect 524236 3266 524288 3272
-rect 524248 480 524276 3266
-rect 525444 480 525472 16546
-rect 526456 3262 526484 334562
-rect 528560 333464 528612 333470
-rect 528560 333406 528612 333412
-rect 526628 4548 526680 4554
-rect 526628 4490 526680 4496
-rect 526444 3256 526496 3262
-rect 526444 3198 526496 3204
-rect 526640 480 526668 4490
-rect 527824 3256 527876 3262
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-rect 527836 480 527864 3198
-rect 528572 490 528600 333406
-rect 530584 333396 530636 333402
-rect 530584 333338 530636 333344
-rect 530124 4616 530176 4622
-rect 530124 4558 530176 4564
-rect 528848 598 529060 626
-rect 528848 490 528876 598
-rect 520710 -960 520822 480
-rect 521814 -960 521926 480
-rect 523010 -960 523122 480
-rect 524206 -960 524318 480
-rect 525402 -960 525514 480
-rect 526598 -960 526710 480
-rect 527794 -960 527906 480
-rect 528572 462 528876 490
-rect 529032 480 529060 598
-rect 530136 480 530164 4558
-rect 530596 3398 530624 333338
-rect 533344 333328 533396 333334
-rect 533344 333270 533396 333276
-rect 533356 3398 533384 333270
-rect 538220 333260 538272 333266
-rect 538220 333202 538272 333208
-rect 535460 330540 535512 330546
-rect 535460 330482 535512 330488
-rect 535472 16574 535500 330482
-rect 538232 16574 538260 333202
-rect 579896 325644 579948 325650
-rect 579896 325586 579948 325592
-rect 579908 325281 579936 325586
-rect 579894 325272 579950 325281
-rect 579894 325207 579950 325216
-rect 580172 313268 580224 313274
-rect 580172 313210 580224 313216
-rect 580184 312089 580212 313210
-rect 580170 312080 580226 312089
-rect 580170 312015 580226 312024
-rect 580276 165889 580304 458798
-rect 580262 165880 580318 165889
-rect 580262 165815 580318 165824
-rect 582380 19848 582432 19854
-rect 582378 19816 582380 19825
-rect 582432 19816 582434 19825
-rect 582378 19751 582434 19760
-rect 535472 16546 536144 16574
-rect 538232 16546 538444 16574
-rect 533712 4684 533764 4690
-rect 533712 4626 533764 4632
-rect 530584 3392 530636 3398
-rect 530584 3334 530636 3340
-rect 531320 3392 531372 3398
-rect 531320 3334 531372 3340
-rect 533344 3392 533396 3398
-rect 533344 3334 533396 3340
-rect 531332 480 531360 3334
-rect 532516 3324 532568 3330
-rect 532516 3266 532568 3272
-rect 532528 480 532556 3266
-rect 533724 480 533752 4626
-rect 534908 3392 534960 3398
-rect 534908 3334 534960 3340
-rect 534920 480 534948 3334
-rect 536116 480 536144 16546
-rect 537208 4752 537260 4758
-rect 537208 4694 537260 4700
-rect 537220 480 537248 4694
-rect 538416 480 538444 16546
-rect 541992 8220 542044 8226
-rect 541992 8162 542044 8168
-rect 540796 5500 540848 5506
-rect 540796 5442 540848 5448
-rect 539600 3392 539652 3398
-rect 539600 3334 539652 3340
-rect 539612 480 539640 3334
-rect 540808 480 540836 5442
-rect 542004 480 542032 8162
-rect 545488 8152 545540 8158
-rect 545488 8094 545540 8100
-rect 544384 5432 544436 5438
-rect 544384 5374 544436 5380
-rect 543188 4072 543240 4078
-rect 543188 4014 543240 4020
-rect 543200 480 543228 4014
-rect 544396 480 544424 5374
-rect 545500 480 545528 8094
-rect 549076 8084 549128 8090
-rect 549076 8026 549128 8032
-rect 547880 5364 547932 5370
-rect 547880 5306 547932 5312
-rect 546684 4004 546736 4010
-rect 546684 3946 546736 3952
-rect 546696 480 546724 3946
-rect 547892 480 547920 5306
-rect 549088 480 549116 8026
-rect 552664 8016 552716 8022
-rect 552664 7958 552716 7964
-rect 551468 5296 551520 5302
-rect 551468 5238 551520 5244
-rect 550272 3936 550324 3942
-rect 550272 3878 550324 3884
-rect 550284 480 550312 3878
-rect 551480 480 551508 5238
-rect 552676 480 552704 7958
-rect 556160 7948 556212 7954
-rect 556160 7890 556212 7896
-rect 554964 5228 555016 5234
-rect 554964 5170 555016 5176
-rect 553768 3868 553820 3874
-rect 553768 3810 553820 3816
-rect 553780 480 553808 3810
-rect 554976 480 555004 5170
-rect 556172 480 556200 7890
-rect 559748 7880 559800 7886
-rect 559748 7822 559800 7828
-rect 558552 5160 558604 5166
-rect 558552 5102 558604 5108
-rect 557356 3800 557408 3806
-rect 557356 3742 557408 3748
-rect 557368 480 557396 3742
-rect 558564 480 558592 5102
-rect 559760 480 559788 7822
-rect 563244 7812 563296 7818
-rect 563244 7754 563296 7760
-rect 562048 5092 562100 5098
-rect 562048 5034 562100 5040
-rect 560852 3732 560904 3738
-rect 560852 3674 560904 3680
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+<< metal3 >>
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-rect -960 462576 3238 462632
-rect 3294 462576 3299 462632
-rect -960 462574 3299 462576
-rect -960 462484 480 462574
-rect 3233 462571 3299 462574
-rect 579797 458146 579863 458149
-rect 583520 458146 584960 458236
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-rect 579797 458088 579802 458144
-rect 579858 458088 584960 458144
-rect 579797 458086 584960 458088
-rect 579797 458083 579863 458086
-rect 583520 457996 584960 458086
-rect 237189 457332 237255 457333
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-rect 237300 457330 237306 457332
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-rect 237300 457270 237346 457330
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-rect 237300 457268 237306 457270
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-rect 242341 457272 242346 457328
-rect 242402 457272 242756 457328
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-rect 243905 457272 243910 457328
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-rect 244038 457268 244044 457270
-rect 244108 457268 244114 457332
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-rect 245580 457330 245586 457332
-rect 245469 457272 245474 457328
-rect 245469 457268 245516 457272
-rect 245580 457270 245626 457330
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-rect 246798 457268 246804 457332
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-rect 246941 457330 247007 457333
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-rect 246868 457272 246946 457328
-rect 247002 457272 247007 457328
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-rect 245469 457267 245535 457268
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-rect 248340 457330 248346 457332
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-rect 248340 457270 248386 457330
-rect 250253 457328 251036 457330
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-rect 250253 457267 250319 457270
-rect 251030 457268 251036 457270
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-rect 251817 457330 251883 457333
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-rect 251817 457272 251822 457328
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-rect 253381 457272 253386 457328
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-rect 253606 457268 253612 457270
-rect 253676 457268 253682 457332
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-rect 256509 457272 256514 457328
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-rect 256620 457270 256666 457330
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-rect 257286 457268 257292 457332
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-rect 257521 457330 257587 457333
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-rect 257356 457272 257526 457328
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-rect 256509 457267 256575 457268
-rect 257521 457267 257587 457270
-rect 259269 457332 259335 457333
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-rect 259380 457330 259386 457332
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-rect 259269 457268 259316 457272
-rect 259380 457270 259426 457330
-rect 261293 457328 262076 457330
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-rect 259380 457268 259386 457270
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-rect 262070 457268 262076 457270
-rect 262140 457268 262146 457332
-rect 262857 457330 262923 457333
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-rect 262857 457272 262862 457328
-rect 262918 457272 263364 457328
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-rect 263428 457268 263434 457332
-rect 264513 457330 264579 457333
-rect 266077 457332 266143 457333
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-rect 264513 457328 264652 457330
-rect 264513 457272 264518 457328
-rect 264574 457272 264652 457328
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-rect 264716 457268 264722 457332
-rect 266077 457328 266124 457332
-rect 266188 457330 266194 457332
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-rect 266188 457270 266234 457330
-rect 267549 457328 267596 457332
-rect 267660 457330 267666 457332
-rect 267549 457272 267554 457328
-rect 266188 457268 266194 457270
-rect 267549 457268 267596 457272
-rect 267660 457270 267706 457330
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-rect 268878 457268 268884 457332
-rect 268948 457330 268954 457332
-rect 269021 457330 269087 457333
-rect 268948 457328 269087 457330
-rect 268948 457272 269026 457328
-rect 269082 457272 269087 457328
-rect 268948 457270 269087 457272
-rect 268948 457268 268954 457270
-rect 266077 457267 266143 457268
-rect 267549 457267 267615 457268
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-rect 408718 457268 408724 457332
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-rect 409137 457330 409203 457333
-rect 408788 457328 409203 457330
-rect 408788 457272 409142 457328
-rect 409198 457272 409203 457328
-rect 408788 457270 409203 457272
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-rect 409137 457267 409203 457270
-rect 409822 457268 409828 457332
-rect 409892 457330 409898 457332
-rect 410701 457330 410767 457333
-rect 409892 457328 410767 457330
-rect 409892 457272 410706 457328
-rect 410762 457272 410767 457328
-rect 409892 457270 410767 457272
-rect 409892 457268 409898 457270
-rect 410701 457267 410767 457270
-rect 411294 457268 411300 457332
-rect 411364 457330 411370 457332
-rect 412265 457330 412331 457333
-rect 411364 457328 412331 457330
-rect 411364 457272 412270 457328
-rect 412326 457272 412331 457328
-rect 411364 457270 412331 457272
-rect 411364 457268 411370 457270
-rect 412265 457267 412331 457270
-rect -960 449578 480 449668
-rect 3325 449578 3391 449581
-rect -960 449576 3391 449578
-rect -960 449520 3330 449576
-rect 3386 449520 3391 449576
-rect -960 449518 3391 449520
-rect -960 449428 480 449518
-rect 3325 449515 3391 449518
-rect 583520 444668 584960 444908
-rect -960 436508 480 436748
-rect 580165 431626 580231 431629
-rect 583520 431626 584960 431716
-rect 580165 431624 584960 431626
-rect 580165 431568 580170 431624
-rect 580226 431568 584960 431624
-rect 580165 431566 584960 431568
-rect 580165 431563 580231 431566
-rect 583520 431476 584960 431566
-rect -960 423602 480 423692
-rect 3417 423602 3483 423605
-rect -960 423600 3483 423602
-rect -960 423544 3422 423600
-rect 3478 423544 3483 423600
-rect -960 423542 3483 423544
-rect -960 423452 480 423542
-rect 3417 423539 3483 423542
-rect 580165 418298 580231 418301
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-rect 580165 418235 580231 418238
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-rect -960 410546 480 410636
-rect 3417 410546 3483 410549
-rect -960 410544 3483 410546
-rect -960 410488 3422 410544
-rect 3478 410488 3483 410544
-rect -960 410486 3483 410488
-rect -960 410396 480 410486
-rect 3417 410483 3483 410486
-rect 579613 404970 579679 404973
-rect 583520 404970 584960 405060
-rect 579613 404968 584960 404970
-rect 579613 404912 579618 404968
-rect 579674 404912 584960 404968
-rect 579613 404910 584960 404912
-rect 579613 404907 579679 404910
-rect 583520 404820 584960 404910
-rect -960 397490 480 397580
-rect 3233 397490 3299 397493
-rect -960 397488 3299 397490
-rect -960 397432 3238 397488
-rect 3294 397432 3299 397488
-rect -960 397430 3299 397432
-rect -960 397340 480 397430
-rect 3233 397427 3299 397430
-rect 583520 391628 584960 391868
-rect -960 384284 480 384524
-rect 580165 378450 580231 378453
-rect 583520 378450 584960 378540
-rect 580165 378448 584960 378450
-rect 580165 378392 580170 378448
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-rect 580165 378390 584960 378392
-rect 580165 378387 580231 378390
-rect 583520 378300 584960 378390
-rect -960 371378 480 371468
-rect 2773 371378 2839 371381
-rect -960 371376 2839 371378
-rect -960 371320 2778 371376
-rect 2834 371320 2839 371376
-rect -960 371318 2839 371320
-rect -960 371228 480 371318
-rect 2773 371315 2839 371318
-rect 580165 365122 580231 365125
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-rect 580165 365064 580170 365120
-rect 580226 365064 584960 365120
-rect 580165 365062 584960 365064
-rect 580165 365059 580231 365062
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-rect -960 358458 480 358548
-rect 3325 358458 3391 358461
-rect -960 358456 3391 358458
-rect -960 358400 3330 358456
-rect 3386 358400 3391 358456
-rect -960 358398 3391 358400
-rect -960 358308 480 358398
-rect 3325 358395 3391 358398
-rect 580165 351930 580231 351933
-rect 583520 351930 584960 352020
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-rect 580165 351872 580170 351928
-rect 580226 351872 584960 351928
-rect 580165 351870 584960 351872
-rect 580165 351867 580231 351870
-rect 583520 351780 584960 351870
-rect -960 345402 480 345492
-rect 3141 345402 3207 345405
-rect -960 345400 3207 345402
-rect -960 345344 3146 345400
-rect 3202 345344 3207 345400
-rect -960 345342 3207 345344
-rect -960 345252 480 345342
-rect 3141 345339 3207 345342
-rect 583520 338452 584960 338692
-rect 43437 336426 43503 336429
-rect 241053 336426 241119 336429
-rect 43437 336424 241119 336426
-rect 43437 336368 43442 336424
-rect 43498 336368 241058 336424
-rect 241114 336368 241119 336424
-rect 43437 336366 241119 336368
-rect 43437 336363 43503 336366
-rect 241053 336363 241119 336366
-rect 18597 336290 18663 336293
-rect 237741 336290 237807 336293
-rect 18597 336288 237807 336290
-rect 18597 336232 18602 336288
-rect 18658 336232 237746 336288
-rect 237802 336232 237807 336288
-rect 18597 336230 237807 336232
-rect 18597 336227 18663 336230
-rect 237741 336227 237807 336230
-rect 21357 336154 21423 336157
-rect 240685 336154 240751 336157
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-rect 21357 336096 21362 336152
-rect 21418 336096 240690 336152
-rect 240746 336096 240751 336152
-rect 21357 336094 240751 336096
-rect 21357 336091 21423 336094
-rect 240685 336091 240751 336094
-rect 387793 336154 387859 336157
-rect 417509 336154 417575 336157
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-rect 387854 336096 417514 336152
-rect 417570 336096 417575 336152
-rect 387793 336094 417575 336096
-rect 387793 336091 387859 336094
-rect 417509 336091 417575 336094
-rect 11697 336018 11763 336021
-rect 236269 336018 236335 336021
-rect 11697 336016 236335 336018
-rect 11697 335960 11702 336016
-rect 11758 335960 236274 336016
-rect 236330 335960 236335 336016
-rect 11697 335958 236335 335960
-rect 11697 335955 11763 335958
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-rect 392669 336018 392735 336021
-rect 507117 336018 507183 336021
-rect 392669 336016 507183 336018
-rect 392669 335960 392674 336016
-rect 392730 335960 507122 336016
-rect 507178 335960 507183 336016
-rect 392669 335958 507183 335960
-rect 392669 335955 392735 335958
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-rect -960 332196 480 332436
-rect 579889 325274 579955 325277
-rect 583520 325274 584960 325364
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-rect 579950 325216 584960 325272
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-rect 579889 325211 579955 325214
-rect 583520 325124 584960 325214
-rect -960 319290 480 319380
-rect 3141 319290 3207 319293
-rect -960 319288 3207 319290
-rect -960 319232 3146 319288
-rect 3202 319232 3207 319288
-rect -960 319230 3207 319232
-rect -960 319140 480 319230
-rect 3141 319227 3207 319230
-rect 580165 312082 580231 312085
-rect 583520 312082 584960 312172
-rect 580165 312080 584960 312082
-rect 580165 312024 580170 312080
-rect 580226 312024 584960 312080
-rect 580165 312022 584960 312024
-rect 580165 312019 580231 312022
-rect 583520 311932 584960 312022
-rect -960 306234 480 306324
-rect 3417 306234 3483 306237
-rect -960 306232 3483 306234
-rect -960 306176 3422 306232
-rect 3478 306176 3483 306232
-rect -960 306174 3483 306176
-rect -960 306084 480 306174
-rect 3417 306171 3483 306174
-rect 583520 298754 584960 298844
-rect 583342 298694 584960 298754
-rect 583342 298618 583402 298694
-rect 583520 298618 584960 298694
-rect 583342 298604 584960 298618
-rect 583342 298558 583586 298604
-rect 268878 298148 268884 298212
-rect 268948 298210 268954 298212
-rect 583526 298210 583586 298558
-rect 268948 298150 583586 298210
-rect 268948 298148 268954 298150
-rect -960 293178 480 293268
-rect 3049 293178 3115 293181
-rect -960 293176 3115 293178
-rect -960 293120 3054 293176
-rect 3110 293120 3115 293176
-rect -960 293118 3115 293120
-rect -960 293028 480 293118
-rect 3049 293115 3115 293118
-rect 583520 285276 584960 285516
-rect -960 279972 480 280212
-rect 583520 272234 584960 272324
-rect 567150 272174 584960 272234
-rect 266118 271900 266124 271964
-rect 266188 271962 266194 271964
-rect 567150 271962 567210 272174
-rect 583520 272084 584960 272174
-rect 266188 271902 567210 271962
-rect 266188 271900 266194 271902
-rect -960 267202 480 267292
-rect 3509 267202 3575 267205
-rect -960 267200 3575 267202
-rect -960 267144 3514 267200
-rect 3570 267144 3575 267200
-rect -960 267142 3575 267144
-rect -960 267052 480 267142
-rect 3509 267139 3575 267142
-rect 583520 258906 584960 258996
-rect 583342 258846 584960 258906
-rect 583342 258770 583402 258846
-rect 583520 258770 584960 258846
-rect 583342 258756 584960 258770
-rect 583342 258710 583586 258756
-rect 267590 258028 267596 258092
-rect 267660 258090 267666 258092
-rect 267660 258030 267842 258090
-rect 267660 258028 267666 258030
-rect 267782 257954 267842 258030
-rect 583526 257954 583586 258710
-rect 267782 257894 583586 257954
-rect -960 254146 480 254236
-rect 3417 254146 3483 254149
-rect -960 254144 3483 254146
-rect -960 254088 3422 254144
-rect 3478 254088 3483 254144
-rect -960 254086 3483 254088
-rect -960 253996 480 254086
-rect 3417 254083 3483 254086
-rect 583520 245578 584960 245668
-rect 583342 245518 584960 245578
-rect 583342 245442 583402 245518
-rect 583520 245442 584960 245518
-rect 583342 245428 584960 245442
-rect 583342 245382 583586 245428
-rect 264646 244292 264652 244356
-rect 264716 244354 264722 244356
-rect 583526 244354 583586 245382
-rect 264716 244294 583586 244354
-rect 264716 244292 264722 244294
-rect -960 241090 480 241180
-rect 3417 241090 3483 241093
-rect -960 241088 3483 241090
-rect -960 241032 3422 241088
-rect 3478 241032 3483 241088
-rect -960 241030 3483 241032
-rect -960 240940 480 241030
-rect 3417 241027 3483 241030
-rect 583520 232386 584960 232476
-rect 583342 232326 584960 232386
-rect 583342 232250 583402 232326
-rect 583520 232250 584960 232326
-rect 583342 232236 584960 232250
-rect 583342 232190 583586 232236
-rect 262070 231916 262076 231980
-rect 262140 231978 262146 231980
-rect 583526 231978 583586 232190
-rect 262140 231918 583586 231978
-rect 262140 231916 262146 231918
-rect -960 227884 480 228124
-rect 583520 219058 584960 219148
-rect 583342 218998 584960 219058
-rect 583342 218922 583402 218998
-rect 583520 218922 584960 218998
-rect 583342 218908 584960 218922
-rect 583342 218862 583586 218908
-rect 263358 218044 263364 218108
-rect 263428 218106 263434 218108
-rect 583526 218106 583586 218862
-rect 263428 218046 583586 218106
-rect 263428 218044 263434 218046
-rect -960 214978 480 215068
-rect 3325 214978 3391 214981
-rect -960 214976 3391 214978
-rect -960 214920 3330 214976
-rect 3386 214920 3391 214976
-rect -960 214918 3391 214920
-rect -960 214828 480 214918
-rect 3325 214915 3391 214918
-rect 259310 205668 259316 205732
-rect 259380 205730 259386 205732
-rect 583520 205730 584960 205820
-rect 259380 205670 584960 205730
-rect 259380 205668 259386 205670
-rect 583520 205580 584960 205670
-rect -960 201922 480 202012
-rect 3417 201922 3483 201925
-rect -960 201920 3483 201922
-rect -960 201864 3422 201920
-rect 3478 201864 3483 201920
-rect -960 201862 3483 201864
-rect -960 201772 480 201862
-rect 3417 201859 3483 201862
-rect 583520 192538 584960 192628
-rect 583342 192478 584960 192538
-rect 583342 192402 583402 192478
-rect 583520 192402 584960 192478
-rect 583342 192388 584960 192402
-rect 583342 192342 583586 192388
-rect 256550 191796 256556 191860
-rect 256620 191858 256626 191860
-rect 583526 191858 583586 192342
-rect 256620 191798 583586 191858
-rect 256620 191796 256626 191798
-rect -960 188866 480 188956
-rect 3417 188866 3483 188869
-rect -960 188864 3483 188866
-rect -960 188808 3422 188864
-rect 3478 188808 3483 188864
-rect -960 188806 3483 188808
-rect -960 188716 480 188806
-rect 3417 188803 3483 188806
-rect 583520 179210 584960 179300
-rect 583342 179150 584960 179210
-rect 583342 179074 583402 179150
-rect 583520 179074 584960 179150
-rect 583342 179060 584960 179074
-rect 583342 179014 583586 179060
-rect 257286 178060 257292 178124
-rect 257356 178122 257362 178124
-rect 583526 178122 583586 179014
-rect 257356 178062 583586 178122
-rect 257356 178060 257362 178062
-rect -960 175796 480 176036
-rect 580257 165882 580323 165885
-rect 583520 165882 584960 165972
-rect 580257 165880 584960 165882
-rect 580257 165824 580262 165880
-rect 580318 165824 584960 165880
-rect 580257 165822 584960 165824
-rect 580257 165819 580323 165822
-rect 583520 165732 584960 165822
-rect -960 162890 480 162980
-rect 3233 162890 3299 162893
-rect -960 162888 3299 162890
-rect -960 162832 3238 162888
-rect 3294 162832 3299 162888
-rect -960 162830 3299 162832
-rect -960 162740 480 162830
-rect 3233 162827 3299 162830
-rect 583520 152690 584960 152780
-rect 583342 152630 584960 152690
-rect 583342 152554 583402 152630
-rect 583520 152554 584960 152630
-rect 583342 152540 584960 152554
-rect 583342 152494 583586 152540
-rect 252318 151812 252324 151876
-rect 252388 151874 252394 151876
-rect 583526 151874 583586 152494
-rect 252388 151814 583586 151874
-rect 252388 151812 252394 151814
-rect -960 149834 480 149924
-rect 3417 149834 3483 149837
-rect -960 149832 3483 149834
-rect -960 149776 3422 149832
-rect 3478 149776 3483 149832
-rect -960 149774 3483 149776
-rect -960 149684 480 149774
-rect 3417 149771 3483 149774
-rect 583520 139362 584960 139452
-rect 583342 139302 584960 139362
-rect 583342 139226 583402 139302
-rect 583520 139226 584960 139302
-rect 583342 139212 584960 139226
-rect 583342 139166 583586 139212
-rect 253606 138076 253612 138140
-rect 253676 138138 253682 138140
-rect 583526 138138 583586 139166
-rect 253676 138078 583586 138138
-rect 253676 138076 253682 138078
-rect -960 136778 480 136868
-rect 3233 136778 3299 136781
-rect -960 136776 3299 136778
-rect -960 136720 3238 136776
-rect 3294 136720 3299 136776
-rect -960 136718 3299 136720
-rect -960 136628 480 136718
-rect 3233 136715 3299 136718
-rect 583520 126034 584960 126124
-rect 583342 125974 584960 126034
-rect 583342 125898 583402 125974
-rect 583520 125898 584960 125974
-rect 583342 125884 584960 125898
-rect 583342 125838 583586 125884
-rect 251030 125564 251036 125628
-rect 251100 125626 251106 125628
-rect 583526 125626 583586 125838
-rect 251100 125566 583586 125626
-rect 251100 125564 251106 125566
-rect -960 123572 480 123812
-rect 583520 112842 584960 112932
-rect 583342 112782 584960 112842
-rect 583342 112706 583402 112782
-rect 583520 112706 584960 112782
-rect 583342 112692 584960 112706
-rect 583342 112646 583586 112692
-rect 246798 111828 246804 111892
-rect 246868 111890 246874 111892
-rect 583526 111890 583586 112646
-rect 246868 111830 583586 111890
-rect 246868 111828 246874 111830
-rect -960 110666 480 110756
-rect 3417 110666 3483 110669
-rect -960 110664 3483 110666
-rect -960 110608 3422 110664
-rect 3478 110608 3483 110664
-rect -960 110606 3483 110608
-rect -960 110516 480 110606
-rect 3417 110603 3483 110606
-rect 248270 99452 248276 99516
-rect 248340 99514 248346 99516
-rect 583520 99514 584960 99604
-rect 248340 99454 584960 99514
-rect 248340 99452 248346 99454
-rect 583520 99364 584960 99454
-rect -960 97610 480 97700
-rect 3417 97610 3483 97613
-rect -960 97608 3483 97610
-rect -960 97552 3422 97608
-rect 3478 97552 3483 97608
-rect -960 97550 3483 97552
-rect -960 97460 480 97550
-rect 3417 97547 3483 97550
-rect 583520 86186 584960 86276
-rect 583342 86126 584960 86186
-rect 583342 86050 583402 86126
-rect 583520 86050 584960 86126
-rect 583342 86036 584960 86050
-rect 583342 85990 583586 86036
-rect 245510 85580 245516 85644
-rect 245580 85642 245586 85644
-rect 583526 85642 583586 85990
-rect 245580 85582 583586 85642
-rect 245580 85580 245586 85582
-rect -960 84690 480 84780
-rect 3141 84690 3207 84693
-rect -960 84688 3207 84690
-rect -960 84632 3146 84688
-rect 3202 84632 3207 84688
-rect -960 84630 3207 84632
-rect -960 84540 480 84630
-rect 3141 84627 3207 84630
-rect 583520 72994 584960 73084
-rect 583342 72934 584960 72994
-rect 583342 72858 583402 72934
-rect 583520 72858 584960 72934
-rect 583342 72844 584960 72858
-rect 583342 72798 583586 72844
-rect 242750 71844 242756 71908
-rect 242820 71906 242826 71908
-rect 583526 71906 583586 72798
-rect 242820 71846 583586 71906
-rect 242820 71844 242826 71846
-rect -960 71634 480 71724
-rect 3417 71634 3483 71637
-rect -960 71632 3483 71634
-rect -960 71576 3422 71632
-rect 3478 71576 3483 71632
-rect -960 71574 3483 71576
-rect -960 71484 480 71574
-rect 3417 71571 3483 71574
-rect 583520 59666 584960 59756
-rect 567150 59606 584960 59666
-rect 244038 59332 244044 59396
-rect 244108 59394 244114 59396
-rect 567150 59394 567210 59606
-rect 583520 59516 584960 59606
-rect 244108 59334 567210 59394
-rect 244108 59332 244114 59334
-rect 3325 59258 3391 59261
-rect 408718 59258 408724 59260
-rect 3325 59256 408724 59258
-rect 3325 59200 3330 59256
-rect 3386 59200 408724 59256
-rect 3325 59198 408724 59200
-rect 3325 59195 3391 59198
-rect 408718 59196 408724 59198
-rect 408788 59196 408794 59260
-rect -960 58578 480 58668
-rect 3325 58578 3391 58581
-rect -960 58576 3391 58578
-rect -960 58520 3330 58576
-rect 3386 58520 3391 58576
-rect -960 58518 3391 58520
-rect -960 58428 480 58518
-rect 3325 58515 3391 58518
-rect 583520 46338 584960 46428
-rect 583342 46278 584960 46338
-rect 583342 46202 583402 46278
-rect 583520 46202 584960 46278
-rect 583342 46188 584960 46202
-rect 583342 46142 583586 46188
-rect -960 45522 480 45612
-rect 241278 45596 241284 45660
-rect 241348 45658 241354 45660
-rect 583526 45658 583586 46142
-rect 241348 45598 583586 45658
-rect 241348 45596 241354 45598
-rect 3417 45522 3483 45525
-rect -960 45520 3483 45522
-rect -960 45464 3422 45520
-rect 3478 45464 3483 45520
-rect -960 45462 3483 45464
-rect -960 45372 480 45462
-rect 3417 45459 3483 45462
-rect 3325 33146 3391 33149
-rect 409822 33146 409828 33148
-rect 3325 33144 409828 33146
-rect 3325 33088 3330 33144
-rect 3386 33088 409828 33144
-rect 3325 33086 409828 33088
-rect 3325 33083 3391 33086
-rect 409822 33084 409828 33086
-rect 409892 33084 409898 33148
-rect 583520 33146 584960 33236
-rect 583342 33086 584960 33146
-rect 583342 33010 583402 33086
-rect 583520 33010 584960 33086
-rect 583342 32996 584960 33010
-rect 583342 32950 583586 32996
-rect -960 32466 480 32556
-rect 3325 32466 3391 32469
-rect -960 32464 3391 32466
-rect -960 32408 3330 32464
-rect 3386 32408 3391 32464
-rect -960 32406 3391 32408
-rect -960 32316 480 32406
-rect 3325 32403 3391 32406
-rect 237230 31724 237236 31788
-rect 237300 31786 237306 31788
-rect 583526 31786 583586 32950
-rect 237300 31726 583586 31786
-rect 237300 31724 237306 31726
-rect 582373 19818 582439 19821
-rect 583520 19818 584960 19908
-rect 582373 19816 584960 19818
-rect 582373 19760 582378 19816
-rect 582434 19760 584960 19816
-rect 582373 19758 584960 19760
-rect 582373 19755 582439 19758
-rect 583520 19668 584960 19758
-rect -960 19410 480 19500
-rect 3417 19410 3483 19413
-rect -960 19408 3483 19410
-rect -960 19352 3422 19408
-rect 3478 19352 3483 19408
-rect -960 19350 3483 19352
-rect -960 19260 480 19350
-rect 3417 19347 3483 19350
-rect 411294 6898 411300 6900
-rect 6870 6838 411300 6898
-rect -960 6490 480 6580
-rect 6870 6490 6930 6838
-rect 411294 6836 411300 6838
-rect 411364 6836 411370 6900
-rect 580165 6626 580231 6629
-rect 583520 6626 584960 6716
-rect 580165 6624 584960 6626
-rect 580165 6568 580170 6624
-rect 580226 6568 584960 6624
-rect 580165 6566 584960 6568
-rect 580165 6563 580231 6566
-rect -960 6430 6930 6490
-rect 583520 6476 584960 6566
-rect -960 6340 480 6430
-rect 24209 3770 24275 3773
-rect 241881 3770 241947 3773
-rect 24209 3768 241947 3770
-rect 24209 3712 24214 3768
-rect 24270 3712 241886 3768
-rect 241942 3712 241947 3768
-rect 24209 3710 241947 3712
-rect 24209 3707 24275 3710
-rect 241881 3707 241947 3710
-rect 294873 3770 294939 3773
-rect 325785 3770 325851 3773
-rect 294873 3768 325851 3770
-rect 294873 3712 294878 3768
-rect 294934 3712 325790 3768
-rect 325846 3712 325851 3768
-rect 294873 3710 325851 3712
-rect 294873 3707 294939 3710
-rect 325785 3707 325851 3710
-rect 413921 3770 413987 3773
-rect 578601 3770 578667 3773
-rect 413921 3768 578667 3770
-rect 413921 3712 413926 3768
-rect 413982 3712 578606 3768
-rect 578662 3712 578667 3768
-rect 413921 3710 578667 3712
-rect 413921 3707 413987 3710
-rect 578601 3707 578667 3710
-rect 15929 3634 15995 3637
-rect 238937 3634 239003 3637
-rect 15929 3632 239003 3634
-rect 15929 3576 15934 3632
-rect 15990 3576 238942 3632
-rect 238998 3576 239003 3632
-rect 15929 3574 239003 3576
-rect 15929 3571 15995 3574
-rect 238937 3571 239003 3574
-rect 290181 3634 290247 3637
-rect 324497 3634 324563 3637
-rect 290181 3632 324563 3634
-rect 290181 3576 290186 3632
-rect 290242 3576 324502 3632
-rect 324558 3576 324563 3632
-rect 290181 3574 324563 3576
-rect 290181 3571 290247 3574
-rect 324497 3571 324563 3574
-rect 415301 3634 415367 3637
-rect 580993 3634 581059 3637
-rect 415301 3632 581059 3634
-rect 415301 3576 415306 3632
-rect 415362 3576 580998 3632
-rect 581054 3576 581059 3632
-rect 415301 3574 581059 3576
-rect 415301 3571 415367 3574
-rect 580993 3571 581059 3574
-rect 14733 3498 14799 3501
-rect 238845 3498 238911 3501
-rect 14733 3496 238911 3498
-rect 14733 3440 14738 3496
-rect 14794 3440 238850 3496
-rect 238906 3440 238911 3496
-rect 14733 3438 238911 3440
-rect 14733 3435 14799 3438
-rect 238845 3435 238911 3438
-rect 283097 3498 283163 3501
-rect 321829 3498 321895 3501
-rect 283097 3496 321895 3498
-rect 283097 3440 283102 3496
-rect 283158 3440 321834 3496
-rect 321890 3440 321895 3496
-rect 283097 3438 321895 3440
-rect 283097 3435 283163 3438
-rect 321829 3435 321895 3438
-rect 415117 3498 415183 3501
-rect 582189 3498 582255 3501
-rect 415117 3496 582255 3498
-rect 415117 3440 415122 3496
-rect 415178 3440 582194 3496
-rect 582250 3440 582255 3496
-rect 415117 3438 582255 3440
-rect 415117 3435 415183 3438
-rect 582189 3435 582255 3438
-rect 6453 3362 6519 3365
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-rect 6453 3304 6458 3360
-rect 6514 3304 236274 3360
-rect 236330 3304 236335 3360
-rect 6453 3302 236335 3304
-rect 6453 3299 6519 3302
-rect 236269 3299 236335 3302
-rect 277117 3362 277183 3365
-rect 320265 3362 320331 3365
-rect 277117 3360 320331 3362
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-rect 277178 3304 320270 3360
-rect 320326 3304 320331 3360
-rect 277117 3302 320331 3304
-rect 277117 3299 277183 3302
-rect 320265 3299 320331 3302
-rect 415209 3362 415275 3365
-rect 583385 3362 583451 3365
-rect 415209 3360 583451 3362
-rect 415209 3304 415214 3360
-rect 415270 3304 583390 3360
-rect 583446 3304 583451 3360
-rect 415209 3302 583451 3304
-rect 415209 3299 415275 3302
-rect 583385 3299 583451 3302
-<< via3 >>
-rect 237236 457328 237300 457332
-rect 237236 457272 237250 457328
-rect 237250 457272 237300 457328
-rect 237236 457268 237300 457272
-rect 241284 457268 241348 457332
-rect 242756 457268 242820 457332
-rect 244044 457268 244108 457332
-rect 245516 457328 245580 457332
-rect 245516 457272 245530 457328
-rect 245530 457272 245580 457328
-rect 245516 457268 245580 457272
-rect 246804 457268 246868 457332
-rect 248276 457328 248340 457332
-rect 248276 457272 248290 457328
-rect 248290 457272 248340 457328
-rect 248276 457268 248340 457272
-rect 251036 457268 251100 457332
-rect 252324 457268 252388 457332
-rect 253612 457268 253676 457332
-rect 256556 457328 256620 457332
-rect 256556 457272 256570 457328
-rect 256570 457272 256620 457328
-rect 256556 457268 256620 457272
-rect 257292 457268 257356 457332
-rect 259316 457328 259380 457332
-rect 259316 457272 259330 457328
-rect 259330 457272 259380 457328
-rect 259316 457268 259380 457272
-rect 262076 457268 262140 457332
-rect 263364 457268 263428 457332
-rect 264652 457268 264716 457332
-rect 266124 457328 266188 457332
-rect 266124 457272 266138 457328
-rect 266138 457272 266188 457328
-rect 266124 457268 266188 457272
-rect 267596 457328 267660 457332
-rect 267596 457272 267610 457328
-rect 267610 457272 267660 457328
-rect 267596 457268 267660 457272
-rect 268884 457268 268948 457332
-rect 408724 457268 408788 457332
-rect 409828 457268 409892 457332
-rect 411300 457268 411364 457332
-rect 268884 298148 268948 298212
-rect 266124 271900 266188 271964
-rect 267596 258028 267660 258092
-rect 264652 244292 264716 244356
-rect 262076 231916 262140 231980
-rect 263364 218044 263428 218108
-rect 259316 205668 259380 205732
-rect 256556 191796 256620 191860
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-rect 252324 151812 252388 151876
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-rect 251036 125564 251100 125628
-rect 246804 111828 246868 111892
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-rect 242756 71844 242820 71908
-rect 244044 59332 244108 59396
-rect 408724 59196 408788 59260
-rect 241284 45596 241348 45660
-rect 409828 33084 409892 33148
-rect 237236 31724 237300 31788
-rect 411300 6836 411364 6900
-<< metal4 >>
-rect -8726 711558 -8106 711590
-rect -8726 711322 -8694 711558
-rect -8458 711322 -8374 711558
-rect -8138 711322 -8106 711558
-rect -8726 711238 -8106 711322
-rect -8726 711002 -8694 711238
-rect -8458 711002 -8374 711238
-rect -8138 711002 -8106 711238
-rect -8726 680614 -8106 711002
-rect -8726 680378 -8694 680614
-rect -8458 680378 -8374 680614
-rect -8138 680378 -8106 680614
-rect -8726 680294 -8106 680378
-rect -8726 680058 -8694 680294
-rect -8458 680058 -8374 680294
-rect -8138 680058 -8106 680294
-rect -8726 644614 -8106 680058
-rect -8726 644378 -8694 644614
-rect -8458 644378 -8374 644614
-rect -8138 644378 -8106 644614
-rect -8726 644294 -8106 644378
-rect -8726 644058 -8694 644294
-rect -8458 644058 -8374 644294
-rect -8138 644058 -8106 644294
-rect -8726 608614 -8106 644058
-rect -8726 608378 -8694 608614
-rect -8458 608378 -8374 608614
-rect -8138 608378 -8106 608614
-rect -8726 608294 -8106 608378
-rect -8726 608058 -8694 608294
-rect -8458 608058 -8374 608294
-rect -8138 608058 -8106 608294
-rect -8726 572614 -8106 608058
-rect -8726 572378 -8694 572614
-rect -8458 572378 -8374 572614
-rect -8138 572378 -8106 572614
-rect -8726 572294 -8106 572378
-rect -8726 572058 -8694 572294
-rect -8458 572058 -8374 572294
-rect -8138 572058 -8106 572294
-rect -8726 536614 -8106 572058
-rect -8726 536378 -8694 536614
-rect -8458 536378 -8374 536614
-rect -8138 536378 -8106 536614
-rect -8726 536294 -8106 536378
-rect -8726 536058 -8694 536294
-rect -8458 536058 -8374 536294
-rect -8138 536058 -8106 536294
-rect -8726 500614 -8106 536058
-rect -8726 500378 -8694 500614
-rect -8458 500378 -8374 500614
-rect -8138 500378 -8106 500614
-rect -8726 500294 -8106 500378
-rect -8726 500058 -8694 500294
-rect -8458 500058 -8374 500294
-rect -8138 500058 -8106 500294
-rect -8726 464614 -8106 500058
-rect -8726 464378 -8694 464614
-rect -8458 464378 -8374 464614
-rect -8138 464378 -8106 464614
-rect -8726 464294 -8106 464378
-rect -8726 464058 -8694 464294
-rect -8458 464058 -8374 464294
-rect -8138 464058 -8106 464294
-rect -8726 428614 -8106 464058
-rect -8726 428378 -8694 428614
-rect -8458 428378 -8374 428614
-rect -8138 428378 -8106 428614
-rect -8726 428294 -8106 428378
-rect -8726 428058 -8694 428294
-rect -8458 428058 -8374 428294
-rect -8138 428058 -8106 428294
-rect -8726 392614 -8106 428058
-rect -8726 392378 -8694 392614
-rect -8458 392378 -8374 392614
-rect -8138 392378 -8106 392614
-rect -8726 392294 -8106 392378
-rect -8726 392058 -8694 392294
-rect -8458 392058 -8374 392294
-rect -8138 392058 -8106 392294
-rect -8726 356614 -8106 392058
-rect -8726 356378 -8694 356614
-rect -8458 356378 -8374 356614
-rect -8138 356378 -8106 356614
-rect -8726 356294 -8106 356378
-rect -8726 356058 -8694 356294
-rect -8458 356058 -8374 356294
-rect -8138 356058 -8106 356294
-rect -8726 320614 -8106 356058
-rect -8726 320378 -8694 320614
-rect -8458 320378 -8374 320614
-rect -8138 320378 -8106 320614
-rect -8726 320294 -8106 320378
-rect -8726 320058 -8694 320294
-rect -8458 320058 -8374 320294
-rect -8138 320058 -8106 320294
-rect -8726 284614 -8106 320058
-rect -8726 284378 -8694 284614
-rect -8458 284378 -8374 284614
-rect -8138 284378 -8106 284614
-rect -8726 284294 -8106 284378
-rect -8726 284058 -8694 284294
-rect -8458 284058 -8374 284294
-rect -8138 284058 -8106 284294
-rect -8726 248614 -8106 284058
-rect -8726 248378 -8694 248614
-rect -8458 248378 -8374 248614
-rect -8138 248378 -8106 248614
-rect -8726 248294 -8106 248378
-rect -8726 248058 -8694 248294
-rect -8458 248058 -8374 248294
-rect -8138 248058 -8106 248294
-rect -8726 212614 -8106 248058
-rect -8726 212378 -8694 212614
-rect -8458 212378 -8374 212614
-rect -8138 212378 -8106 212614
-rect -8726 212294 -8106 212378
-rect -8726 212058 -8694 212294
-rect -8458 212058 -8374 212294
-rect -8138 212058 -8106 212294
-rect -8726 176614 -8106 212058
-rect -8726 176378 -8694 176614
-rect -8458 176378 -8374 176614
-rect -8138 176378 -8106 176614
-rect -8726 176294 -8106 176378
-rect -8726 176058 -8694 176294
-rect -8458 176058 -8374 176294
-rect -8138 176058 -8106 176294
-rect -8726 140614 -8106 176058
-rect -8726 140378 -8694 140614
-rect -8458 140378 -8374 140614
-rect -8138 140378 -8106 140614
-rect -8726 140294 -8106 140378
-rect -8726 140058 -8694 140294
-rect -8458 140058 -8374 140294
-rect -8138 140058 -8106 140294
-rect -8726 104614 -8106 140058
-rect -8726 104378 -8694 104614
-rect -8458 104378 -8374 104614
-rect -8138 104378 -8106 104614
-rect -8726 104294 -8106 104378
-rect -8726 104058 -8694 104294
-rect -8458 104058 -8374 104294
-rect -8138 104058 -8106 104294
-rect -8726 68614 -8106 104058
-rect -8726 68378 -8694 68614
-rect -8458 68378 -8374 68614
-rect -8138 68378 -8106 68614
-rect -8726 68294 -8106 68378
-rect -8726 68058 -8694 68294
-rect -8458 68058 -8374 68294
-rect -8138 68058 -8106 68294
-rect -8726 32614 -8106 68058
-rect -8726 32378 -8694 32614
-rect -8458 32378 -8374 32614
-rect -8138 32378 -8106 32614
-rect -8726 32294 -8106 32378
-rect -8726 32058 -8694 32294
-rect -8458 32058 -8374 32294
-rect -8138 32058 -8106 32294
-rect -8726 -7066 -8106 32058
-rect -7766 710598 -7146 710630
-rect -7766 710362 -7734 710598
-rect -7498 710362 -7414 710598
-rect -7178 710362 -7146 710598
-rect -7766 710278 -7146 710362
-rect -7766 710042 -7734 710278
-rect -7498 710042 -7414 710278
-rect -7178 710042 -7146 710278
-rect -7766 698614 -7146 710042
-rect 12954 710598 13574 711590
-rect 12954 710362 12986 710598
-rect 13222 710362 13306 710598
-rect 13542 710362 13574 710598
-rect 12954 710278 13574 710362
-rect 12954 710042 12986 710278
-rect 13222 710042 13306 710278
-rect 13542 710042 13574 710278
-rect -7766 698378 -7734 698614
-rect -7498 698378 -7414 698614
-rect -7178 698378 -7146 698614
-rect -7766 698294 -7146 698378
-rect -7766 698058 -7734 698294
-rect -7498 698058 -7414 698294
-rect -7178 698058 -7146 698294
-rect -7766 662614 -7146 698058
-rect -7766 662378 -7734 662614
-rect -7498 662378 -7414 662614
-rect -7178 662378 -7146 662614
-rect -7766 662294 -7146 662378
-rect -7766 662058 -7734 662294
-rect -7498 662058 -7414 662294
-rect -7178 662058 -7146 662294
-rect -7766 626614 -7146 662058
-rect -7766 626378 -7734 626614
-rect -7498 626378 -7414 626614
-rect -7178 626378 -7146 626614
-rect -7766 626294 -7146 626378
-rect -7766 626058 -7734 626294
-rect -7498 626058 -7414 626294
-rect -7178 626058 -7146 626294
-rect -7766 590614 -7146 626058
-rect -7766 590378 -7734 590614
-rect -7498 590378 -7414 590614
-rect -7178 590378 -7146 590614
-rect -7766 590294 -7146 590378
-rect -7766 590058 -7734 590294
-rect -7498 590058 -7414 590294
-rect -7178 590058 -7146 590294
-rect -7766 554614 -7146 590058
-rect -7766 554378 -7734 554614
-rect -7498 554378 -7414 554614
-rect -7178 554378 -7146 554614
-rect -7766 554294 -7146 554378
-rect -7766 554058 -7734 554294
-rect -7498 554058 -7414 554294
-rect -7178 554058 -7146 554294
-rect -7766 518614 -7146 554058
-rect -7766 518378 -7734 518614
-rect -7498 518378 -7414 518614
-rect -7178 518378 -7146 518614
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-rect -1738 75218 -1654 75454
-rect -1418 75218 -1386 75454
-rect -2006 75134 -1386 75218
-rect -2006 74898 -1974 75134
-rect -1738 74898 -1654 75134
-rect -1418 74898 -1386 75134
-rect -2006 39454 -1386 74898
-rect -2006 39218 -1974 39454
-rect -1738 39218 -1654 39454
-rect -1418 39218 -1386 39454
-rect -2006 39134 -1386 39218
-rect -2006 38898 -1974 39134
-rect -1738 38898 -1654 39134
-rect -1418 38898 -1386 39134
-rect -2006 3454 -1386 38898
-rect -2006 3218 -1974 3454
-rect -1738 3218 -1654 3454
-rect -1418 3218 -1386 3454
-rect -2006 3134 -1386 3218
-rect -2006 2898 -1974 3134
-rect -1738 2898 -1654 3134
-rect -1418 2898 -1386 3134
-rect -2006 -346 -1386 2898
-rect -2006 -582 -1974 -346
-rect -1738 -582 -1654 -346
-rect -1418 -582 -1386 -346
-rect -2006 -666 -1386 -582
-rect -2006 -902 -1974 -666
-rect -1738 -902 -1654 -666
-rect -1418 -902 -1386 -666
-rect -2006 -934 -1386 -902
-rect 1794 704838 2414 705830
-rect 1794 704602 1826 704838
-rect 2062 704602 2146 704838
-rect 2382 704602 2414 704838
-rect 1794 704518 2414 704602
-rect 1794 704282 1826 704518
-rect 2062 704282 2146 704518
-rect 2382 704282 2414 704518
-rect 1794 687454 2414 704282
-rect 1794 687218 1826 687454
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-rect 2382 687218 2414 687454
-rect 1794 687134 2414 687218
-rect 1794 686898 1826 687134
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-rect 1794 651454 2414 686898
-rect 1794 651218 1826 651454
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-rect 2382 651218 2414 651454
-rect 1794 651134 2414 651218
-rect 1794 650898 1826 651134
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-rect 2382 650898 2414 651134
-rect 1794 615454 2414 650898
-rect 1794 615218 1826 615454
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-rect 2382 615218 2414 615454
-rect 1794 615134 2414 615218
-rect 1794 614898 1826 615134
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-rect 1794 579454 2414 614898
-rect 1794 579218 1826 579454
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-rect 2382 579218 2414 579454
-rect 1794 579134 2414 579218
-rect 1794 578898 1826 579134
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-rect 2382 578898 2414 579134
-rect 1794 543454 2414 578898
-rect 1794 543218 1826 543454
-rect 2062 543218 2146 543454
-rect 2382 543218 2414 543454
-rect 1794 543134 2414 543218
-rect 1794 542898 1826 543134
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-rect 1794 507454 2414 542898
-rect 1794 507218 1826 507454
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-rect 2382 507218 2414 507454
-rect 1794 507134 2414 507218
-rect 1794 506898 1826 507134
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-rect 2382 506898 2414 507134
-rect 1794 471454 2414 506898
-rect 1794 471218 1826 471454
-rect 2062 471218 2146 471454
-rect 2382 471218 2414 471454
-rect 1794 471134 2414 471218
-rect 1794 470898 1826 471134
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-rect 1794 435454 2414 470898
-rect 1794 435218 1826 435454
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-rect 2382 435218 2414 435454
-rect 1794 435134 2414 435218
-rect 1794 434898 1826 435134
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-rect 1794 399454 2414 434898
-rect 1794 399218 1826 399454
-rect 2062 399218 2146 399454
-rect 2382 399218 2414 399454
-rect 1794 399134 2414 399218
-rect 1794 398898 1826 399134
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-rect 1794 363454 2414 398898
-rect 1794 363218 1826 363454
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-rect 2382 363218 2414 363454
-rect 1794 363134 2414 363218
-rect 1794 362898 1826 363134
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-rect 1794 327454 2414 362898
-rect 1794 327218 1826 327454
-rect 2062 327218 2146 327454
-rect 2382 327218 2414 327454
-rect 1794 327134 2414 327218
-rect 1794 326898 1826 327134
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-rect 1794 291454 2414 326898
-rect 1794 291218 1826 291454
-rect 2062 291218 2146 291454
-rect 2382 291218 2414 291454
-rect 1794 291134 2414 291218
-rect 1794 290898 1826 291134
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-rect 2382 290898 2414 291134
-rect 1794 255454 2414 290898
-rect 1794 255218 1826 255454
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-rect 2382 255218 2414 255454
-rect 1794 255134 2414 255218
-rect 1794 254898 1826 255134
-rect 2062 254898 2146 255134
-rect 2382 254898 2414 255134
-rect 1794 219454 2414 254898
-rect 1794 219218 1826 219454
-rect 2062 219218 2146 219454
-rect 2382 219218 2414 219454
-rect 1794 219134 2414 219218
-rect 1794 218898 1826 219134
-rect 2062 218898 2146 219134
-rect 2382 218898 2414 219134
-rect 1794 183454 2414 218898
-rect 1794 183218 1826 183454
-rect 2062 183218 2146 183454
-rect 2382 183218 2414 183454
-rect 1794 183134 2414 183218
-rect 1794 182898 1826 183134
-rect 2062 182898 2146 183134
-rect 2382 182898 2414 183134
-rect 1794 147454 2414 182898
-rect 1794 147218 1826 147454
-rect 2062 147218 2146 147454
-rect 2382 147218 2414 147454
-rect 1794 147134 2414 147218
-rect 1794 146898 1826 147134
-rect 2062 146898 2146 147134
-rect 2382 146898 2414 147134
-rect 1794 111454 2414 146898
-rect 1794 111218 1826 111454
-rect 2062 111218 2146 111454
-rect 2382 111218 2414 111454
-rect 1794 111134 2414 111218
-rect 1794 110898 1826 111134
-rect 2062 110898 2146 111134
-rect 2382 110898 2414 111134
-rect 1794 75454 2414 110898
-rect 1794 75218 1826 75454
-rect 2062 75218 2146 75454
-rect 2382 75218 2414 75454
-rect 1794 75134 2414 75218
-rect 1794 74898 1826 75134
-rect 2062 74898 2146 75134
-rect 2382 74898 2414 75134
-rect 1794 39454 2414 74898
-rect 1794 39218 1826 39454
-rect 2062 39218 2146 39454
-rect 2382 39218 2414 39454
-rect 1794 39134 2414 39218
-rect 1794 38898 1826 39134
-rect 2062 38898 2146 39134
-rect 2382 38898 2414 39134
-rect 1794 3454 2414 38898
-rect 1794 3218 1826 3454
-rect 2062 3218 2146 3454
-rect 2382 3218 2414 3454
-rect 1794 3134 2414 3218
-rect 1794 2898 1826 3134
-rect 2062 2898 2146 3134
-rect 2382 2898 2414 3134
-rect 1794 -346 2414 2898
-rect 1794 -582 1826 -346
-rect 2062 -582 2146 -346
-rect 2382 -582 2414 -346
-rect 1794 -666 2414 -582
-rect 1794 -902 1826 -666
-rect 2062 -902 2146 -666
-rect 2382 -902 2414 -666
-rect -2966 -1542 -2934 -1306
-rect -2698 -1542 -2614 -1306
-rect -2378 -1542 -2346 -1306
-rect -2966 -1626 -2346 -1542
-rect -2966 -1862 -2934 -1626
-rect -2698 -1862 -2614 -1626
-rect -2378 -1862 -2346 -1626
-rect -2966 -1894 -2346 -1862
-rect 1794 -1894 2414 -902
-rect 5514 691174 6134 706202
-rect 5514 690938 5546 691174
-rect 5782 690938 5866 691174
-rect 6102 690938 6134 691174
-rect 5514 690854 6134 690938
-rect 5514 690618 5546 690854
-rect 5782 690618 5866 690854
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-rect 5514 655174 6134 690618
-rect 5514 654938 5546 655174
-rect 5782 654938 5866 655174
-rect 6102 654938 6134 655174
-rect 5514 654854 6134 654938
-rect 5514 654618 5546 654854
-rect 5782 654618 5866 654854
-rect 6102 654618 6134 654854
-rect 5514 619174 6134 654618
-rect 5514 618938 5546 619174
-rect 5782 618938 5866 619174
-rect 6102 618938 6134 619174
-rect 5514 618854 6134 618938
-rect 5514 618618 5546 618854
-rect 5782 618618 5866 618854
-rect 6102 618618 6134 618854
-rect 5514 583174 6134 618618
-rect 5514 582938 5546 583174
-rect 5782 582938 5866 583174
-rect 6102 582938 6134 583174
-rect 5514 582854 6134 582938
-rect 5514 582618 5546 582854
-rect 5782 582618 5866 582854
-rect 6102 582618 6134 582854
-rect 5514 547174 6134 582618
-rect 5514 546938 5546 547174
-rect 5782 546938 5866 547174
-rect 6102 546938 6134 547174
-rect 5514 546854 6134 546938
-rect 5514 546618 5546 546854
-rect 5782 546618 5866 546854
-rect 6102 546618 6134 546854
-rect 5514 511174 6134 546618
-rect 5514 510938 5546 511174
-rect 5782 510938 5866 511174
-rect 6102 510938 6134 511174
-rect 5514 510854 6134 510938
-rect 5514 510618 5546 510854
-rect 5782 510618 5866 510854
-rect 6102 510618 6134 510854
-rect 5514 475174 6134 510618
-rect 5514 474938 5546 475174
-rect 5782 474938 5866 475174
-rect 6102 474938 6134 475174
-rect 5514 474854 6134 474938
-rect 5514 474618 5546 474854
-rect 5782 474618 5866 474854
-rect 6102 474618 6134 474854
-rect 5514 439174 6134 474618
-rect 5514 438938 5546 439174
-rect 5782 438938 5866 439174
-rect 6102 438938 6134 439174
-rect 5514 438854 6134 438938
-rect 5514 438618 5546 438854
-rect 5782 438618 5866 438854
-rect 6102 438618 6134 438854
-rect 5514 403174 6134 438618
-rect 5514 402938 5546 403174
-rect 5782 402938 5866 403174
-rect 6102 402938 6134 403174
-rect 5514 402854 6134 402938
-rect 5514 402618 5546 402854
-rect 5782 402618 5866 402854
-rect 6102 402618 6134 402854
-rect 5514 367174 6134 402618
-rect 5514 366938 5546 367174
-rect 5782 366938 5866 367174
-rect 6102 366938 6134 367174
-rect 5514 366854 6134 366938
-rect 5514 366618 5546 366854
-rect 5782 366618 5866 366854
-rect 6102 366618 6134 366854
-rect 5514 331174 6134 366618
-rect 5514 330938 5546 331174
-rect 5782 330938 5866 331174
-rect 6102 330938 6134 331174
-rect 5514 330854 6134 330938
-rect 5514 330618 5546 330854
-rect 5782 330618 5866 330854
-rect 6102 330618 6134 330854
-rect 5514 295174 6134 330618
-rect 5514 294938 5546 295174
-rect 5782 294938 5866 295174
-rect 6102 294938 6134 295174
-rect 5514 294854 6134 294938
-rect 5514 294618 5546 294854
-rect 5782 294618 5866 294854
-rect 6102 294618 6134 294854
-rect 5514 259174 6134 294618
-rect 5514 258938 5546 259174
-rect 5782 258938 5866 259174
-rect 6102 258938 6134 259174
-rect 5514 258854 6134 258938
-rect 5514 258618 5546 258854
-rect 5782 258618 5866 258854
-rect 6102 258618 6134 258854
-rect 5514 223174 6134 258618
-rect 5514 222938 5546 223174
-rect 5782 222938 5866 223174
-rect 6102 222938 6134 223174
-rect 5514 222854 6134 222938
-rect 5514 222618 5546 222854
-rect 5782 222618 5866 222854
-rect 6102 222618 6134 222854
-rect 5514 187174 6134 222618
-rect 5514 186938 5546 187174
-rect 5782 186938 5866 187174
-rect 6102 186938 6134 187174
-rect 5514 186854 6134 186938
-rect 5514 186618 5546 186854
-rect 5782 186618 5866 186854
-rect 6102 186618 6134 186854
-rect 5514 151174 6134 186618
-rect 5514 150938 5546 151174
-rect 5782 150938 5866 151174
-rect 6102 150938 6134 151174
-rect 5514 150854 6134 150938
-rect 5514 150618 5546 150854
-rect 5782 150618 5866 150854
-rect 6102 150618 6134 150854
-rect 5514 115174 6134 150618
-rect 5514 114938 5546 115174
-rect 5782 114938 5866 115174
-rect 6102 114938 6134 115174
-rect 5514 114854 6134 114938
-rect 5514 114618 5546 114854
-rect 5782 114618 5866 114854
-rect 6102 114618 6134 114854
-rect 5514 79174 6134 114618
-rect 5514 78938 5546 79174
-rect 5782 78938 5866 79174
-rect 6102 78938 6134 79174
-rect 5514 78854 6134 78938
-rect 5514 78618 5546 78854
-rect 5782 78618 5866 78854
-rect 6102 78618 6134 78854
-rect 5514 43174 6134 78618
-rect 5514 42938 5546 43174
-rect 5782 42938 5866 43174
-rect 6102 42938 6134 43174
-rect 5514 42854 6134 42938
-rect 5514 42618 5546 42854
-rect 5782 42618 5866 42854
-rect 6102 42618 6134 42854
-rect 5514 7174 6134 42618
-rect 5514 6938 5546 7174
-rect 5782 6938 5866 7174
-rect 6102 6938 6134 7174
-rect 5514 6854 6134 6938
-rect 5514 6618 5546 6854
-rect 5782 6618 5866 6854
-rect 6102 6618 6134 6854
-rect -3926 -2502 -3894 -2266
-rect -3658 -2502 -3574 -2266
-rect -3338 -2502 -3306 -2266
-rect -3926 -2586 -3306 -2502
-rect -3926 -2822 -3894 -2586
-rect -3658 -2822 -3574 -2586
-rect -3338 -2822 -3306 -2586
-rect -3926 -2854 -3306 -2822
-rect 5514 -2266 6134 6618
-rect 5514 -2502 5546 -2266
-rect 5782 -2502 5866 -2266
-rect 6102 -2502 6134 -2266
-rect 5514 -2586 6134 -2502
-rect 5514 -2822 5546 -2586
-rect 5782 -2822 5866 -2586
-rect 6102 -2822 6134 -2586
-rect -4886 -3462 -4854 -3226
-rect -4618 -3462 -4534 -3226
-rect -4298 -3462 -4266 -3226
-rect -4886 -3546 -4266 -3462
-rect -4886 -3782 -4854 -3546
-rect -4618 -3782 -4534 -3546
-rect -4298 -3782 -4266 -3546
-rect -4886 -3814 -4266 -3782
-rect 5514 -3814 6134 -2822
-rect 9234 694894 9854 708122
-rect 9234 694658 9266 694894
-rect 9502 694658 9586 694894
-rect 9822 694658 9854 694894
-rect 9234 694574 9854 694658
-rect 9234 694338 9266 694574
-rect 9502 694338 9586 694574
-rect 9822 694338 9854 694574
-rect 9234 658894 9854 694338
-rect 9234 658658 9266 658894
-rect 9502 658658 9586 658894
-rect 9822 658658 9854 658894
-rect 9234 658574 9854 658658
-rect 9234 658338 9266 658574
-rect 9502 658338 9586 658574
-rect 9822 658338 9854 658574
-rect 9234 622894 9854 658338
-rect 9234 622658 9266 622894
-rect 9502 622658 9586 622894
-rect 9822 622658 9854 622894
-rect 9234 622574 9854 622658
-rect 9234 622338 9266 622574
-rect 9502 622338 9586 622574
-rect 9822 622338 9854 622574
-rect 9234 586894 9854 622338
-rect 9234 586658 9266 586894
-rect 9502 586658 9586 586894
-rect 9822 586658 9854 586894
-rect 9234 586574 9854 586658
-rect 9234 586338 9266 586574
-rect 9502 586338 9586 586574
-rect 9822 586338 9854 586574
-rect 9234 550894 9854 586338
-rect 9234 550658 9266 550894
-rect 9502 550658 9586 550894
-rect 9822 550658 9854 550894
-rect 9234 550574 9854 550658
-rect 9234 550338 9266 550574
-rect 9502 550338 9586 550574
-rect 9822 550338 9854 550574
-rect 9234 514894 9854 550338
-rect 9234 514658 9266 514894
-rect 9502 514658 9586 514894
-rect 9822 514658 9854 514894
-rect 9234 514574 9854 514658
-rect 9234 514338 9266 514574
-rect 9502 514338 9586 514574
-rect 9822 514338 9854 514574
-rect 9234 478894 9854 514338
-rect 9234 478658 9266 478894
-rect 9502 478658 9586 478894
-rect 9822 478658 9854 478894
-rect 9234 478574 9854 478658
-rect 9234 478338 9266 478574
-rect 9502 478338 9586 478574
-rect 9822 478338 9854 478574
-rect 9234 442894 9854 478338
-rect 9234 442658 9266 442894
-rect 9502 442658 9586 442894
-rect 9822 442658 9854 442894
-rect 9234 442574 9854 442658
-rect 9234 442338 9266 442574
-rect 9502 442338 9586 442574
-rect 9822 442338 9854 442574
-rect 9234 406894 9854 442338
-rect 9234 406658 9266 406894
-rect 9502 406658 9586 406894
-rect 9822 406658 9854 406894
-rect 9234 406574 9854 406658
-rect 9234 406338 9266 406574
-rect 9502 406338 9586 406574
-rect 9822 406338 9854 406574
-rect 9234 370894 9854 406338
-rect 9234 370658 9266 370894
-rect 9502 370658 9586 370894
-rect 9822 370658 9854 370894
-rect 9234 370574 9854 370658
-rect 9234 370338 9266 370574
-rect 9502 370338 9586 370574
-rect 9822 370338 9854 370574
-rect 9234 334894 9854 370338
-rect 9234 334658 9266 334894
-rect 9502 334658 9586 334894
-rect 9822 334658 9854 334894
-rect 9234 334574 9854 334658
-rect 9234 334338 9266 334574
-rect 9502 334338 9586 334574
-rect 9822 334338 9854 334574
-rect 9234 298894 9854 334338
-rect 9234 298658 9266 298894
-rect 9502 298658 9586 298894
-rect 9822 298658 9854 298894
-rect 9234 298574 9854 298658
-rect 9234 298338 9266 298574
-rect 9502 298338 9586 298574
-rect 9822 298338 9854 298574
-rect 9234 262894 9854 298338
-rect 9234 262658 9266 262894
-rect 9502 262658 9586 262894
-rect 9822 262658 9854 262894
-rect 9234 262574 9854 262658
-rect 9234 262338 9266 262574
-rect 9502 262338 9586 262574
-rect 9822 262338 9854 262574
-rect 9234 226894 9854 262338
-rect 9234 226658 9266 226894
-rect 9502 226658 9586 226894
-rect 9822 226658 9854 226894
-rect 9234 226574 9854 226658
-rect 9234 226338 9266 226574
-rect 9502 226338 9586 226574
-rect 9822 226338 9854 226574
-rect 9234 190894 9854 226338
-rect 9234 190658 9266 190894
-rect 9502 190658 9586 190894
-rect 9822 190658 9854 190894
-rect 9234 190574 9854 190658
-rect 9234 190338 9266 190574
-rect 9502 190338 9586 190574
-rect 9822 190338 9854 190574
-rect 9234 154894 9854 190338
-rect 9234 154658 9266 154894
-rect 9502 154658 9586 154894
-rect 9822 154658 9854 154894
-rect 9234 154574 9854 154658
-rect 9234 154338 9266 154574
-rect 9502 154338 9586 154574
-rect 9822 154338 9854 154574
-rect 9234 118894 9854 154338
-rect 9234 118658 9266 118894
-rect 9502 118658 9586 118894
-rect 9822 118658 9854 118894
-rect 9234 118574 9854 118658
-rect 9234 118338 9266 118574
-rect 9502 118338 9586 118574
-rect 9822 118338 9854 118574
-rect 9234 82894 9854 118338
-rect 9234 82658 9266 82894
-rect 9502 82658 9586 82894
-rect 9822 82658 9854 82894
-rect 9234 82574 9854 82658
-rect 9234 82338 9266 82574
-rect 9502 82338 9586 82574
-rect 9822 82338 9854 82574
-rect 9234 46894 9854 82338
-rect 9234 46658 9266 46894
-rect 9502 46658 9586 46894
-rect 9822 46658 9854 46894
-rect 9234 46574 9854 46658
-rect 9234 46338 9266 46574
-rect 9502 46338 9586 46574
-rect 9822 46338 9854 46574
-rect 9234 10894 9854 46338
-rect 9234 10658 9266 10894
-rect 9502 10658 9586 10894
-rect 9822 10658 9854 10894
-rect 9234 10574 9854 10658
-rect 9234 10338 9266 10574
-rect 9502 10338 9586 10574
-rect 9822 10338 9854 10574
-rect -5846 -4422 -5814 -4186
-rect -5578 -4422 -5494 -4186
-rect -5258 -4422 -5226 -4186
-rect -5846 -4506 -5226 -4422
-rect -5846 -4742 -5814 -4506
-rect -5578 -4742 -5494 -4506
-rect -5258 -4742 -5226 -4506
-rect -5846 -4774 -5226 -4742
-rect 9234 -4186 9854 10338
-rect 9234 -4422 9266 -4186
-rect 9502 -4422 9586 -4186
-rect 9822 -4422 9854 -4186
-rect 9234 -4506 9854 -4422
-rect 9234 -4742 9266 -4506
-rect 9502 -4742 9586 -4506
-rect 9822 -4742 9854 -4506
-rect -6806 -5382 -6774 -5146
-rect -6538 -5382 -6454 -5146
-rect -6218 -5382 -6186 -5146
-rect -6806 -5466 -6186 -5382
-rect -6806 -5702 -6774 -5466
-rect -6538 -5702 -6454 -5466
-rect -6218 -5702 -6186 -5466
-rect -6806 -5734 -6186 -5702
-rect 9234 -5734 9854 -4742
-rect 12954 698614 13574 710042
-rect 30954 711558 31574 711590
-rect 30954 711322 30986 711558
-rect 31222 711322 31306 711558
-rect 31542 711322 31574 711558
-rect 30954 711238 31574 711322
-rect 30954 711002 30986 711238
-rect 31222 711002 31306 711238
-rect 31542 711002 31574 711238
-rect 27234 709638 27854 709670
-rect 27234 709402 27266 709638
-rect 27502 709402 27586 709638
-rect 27822 709402 27854 709638
-rect 27234 709318 27854 709402
-rect 27234 709082 27266 709318
-rect 27502 709082 27586 709318
-rect 27822 709082 27854 709318
-rect 23514 707718 24134 707750
-rect 23514 707482 23546 707718
-rect 23782 707482 23866 707718
-rect 24102 707482 24134 707718
-rect 23514 707398 24134 707482
-rect 23514 707162 23546 707398
-rect 23782 707162 23866 707398
-rect 24102 707162 24134 707398
-rect 12954 698378 12986 698614
-rect 13222 698378 13306 698614
-rect 13542 698378 13574 698614
-rect 12954 698294 13574 698378
-rect 12954 698058 12986 698294
-rect 13222 698058 13306 698294
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-rect 12954 662614 13574 698058
-rect 12954 662378 12986 662614
-rect 13222 662378 13306 662614
-rect 13542 662378 13574 662614
-rect 12954 662294 13574 662378
-rect 12954 662058 12986 662294
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-rect 12954 626614 13574 662058
-rect 12954 626378 12986 626614
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-rect 13542 626378 13574 626614
-rect 12954 626294 13574 626378
-rect 12954 626058 12986 626294
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-rect 12954 590614 13574 626058
-rect 12954 590378 12986 590614
-rect 13222 590378 13306 590614
-rect 13542 590378 13574 590614
-rect 12954 590294 13574 590378
-rect 12954 590058 12986 590294
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-rect 12954 554614 13574 590058
-rect 12954 554378 12986 554614
-rect 13222 554378 13306 554614
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-rect 12954 554294 13574 554378
-rect 12954 554058 12986 554294
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-rect 12954 518614 13574 554058
-rect 12954 518378 12986 518614
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-rect 12954 518294 13574 518378
-rect 12954 518058 12986 518294
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-rect 12954 482614 13574 518058
-rect 12954 482378 12986 482614
-rect 13222 482378 13306 482614
-rect 13542 482378 13574 482614
-rect 12954 482294 13574 482378
-rect 12954 482058 12986 482294
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-rect 12954 446614 13574 482058
-rect 12954 446378 12986 446614
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-rect 12954 446294 13574 446378
-rect 12954 446058 12986 446294
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-rect 12954 410378 12986 410614
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-rect 12954 410294 13574 410378
-rect 12954 410058 12986 410294
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-rect 12954 374614 13574 410058
-rect 12954 374378 12986 374614
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-rect 12954 374294 13574 374378
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-rect 12954 338614 13574 374058
-rect 12954 338378 12986 338614
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-rect 12954 338294 13574 338378
-rect 12954 338058 12986 338294
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-rect 12954 302614 13574 338058
-rect 12954 302378 12986 302614
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-rect 12954 302294 13574 302378
-rect 12954 302058 12986 302294
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-rect 12954 266614 13574 302058
-rect 12954 266378 12986 266614
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-rect 12954 266058 12986 266294
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-rect 12954 230378 12986 230614
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-rect 12954 230294 13574 230378
-rect 12954 230058 12986 230294
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-rect 12954 194614 13574 230058
-rect 12954 194378 12986 194614
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-rect 12954 194294 13574 194378
-rect 12954 194058 12986 194294
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-rect 12954 158378 12986 158614
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-rect 12954 158294 13574 158378
-rect 12954 158058 12986 158294
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-rect 12954 122614 13574 158058
-rect 12954 122378 12986 122614
-rect 13222 122378 13306 122614
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-rect 12954 122294 13574 122378
-rect 12954 122058 12986 122294
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-rect 12954 86614 13574 122058
-rect 12954 86378 12986 86614
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-rect 13542 86378 13574 86614
-rect 12954 86294 13574 86378
-rect 12954 86058 12986 86294
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-rect 12954 50614 13574 86058
-rect 12954 50378 12986 50614
-rect 13222 50378 13306 50614
-rect 13542 50378 13574 50614
-rect 12954 50294 13574 50378
-rect 12954 50058 12986 50294
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-rect 12954 14614 13574 50058
-rect 12954 14378 12986 14614
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-rect 12954 14058 12986 14294
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-rect 13542 14058 13574 14294
-rect -7766 -6342 -7734 -6106
-rect -7498 -6342 -7414 -6106
-rect -7178 -6342 -7146 -6106
-rect -7766 -6426 -7146 -6342
-rect -7766 -6662 -7734 -6426
-rect -7498 -6662 -7414 -6426
-rect -7178 -6662 -7146 -6426
-rect -7766 -6694 -7146 -6662
-rect 12954 -6106 13574 14058
-rect 19794 705798 20414 705830
-rect 19794 705562 19826 705798
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-rect 19794 705478 20414 705562
-rect 19794 705242 19826 705478
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-rect 19794 669454 20414 705242
-rect 19794 669218 19826 669454
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-rect 19794 669134 20414 669218
-rect 19794 668898 19826 669134
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-rect 19794 633454 20414 668898
-rect 19794 633218 19826 633454
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-rect 19794 633134 20414 633218
-rect 19794 632898 19826 633134
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-rect 19794 597454 20414 632898
-rect 19794 597218 19826 597454
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-rect 19794 597134 20414 597218
-rect 19794 596898 19826 597134
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-rect 19794 561454 20414 596898
-rect 19794 561218 19826 561454
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-rect 19794 561134 20414 561218
-rect 19794 560898 19826 561134
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-rect 20382 560898 20414 561134
-rect 19794 525454 20414 560898
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-rect 19794 525134 20414 525218
-rect 19794 524898 19826 525134
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-rect 20382 524898 20414 525134
-rect 19794 489454 20414 524898
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-rect 20382 489218 20414 489454
-rect 19794 489134 20414 489218
-rect 19794 488898 19826 489134
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-rect 19794 453454 20414 488898
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-rect 20062 453218 20146 453454
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-rect 19794 453134 20414 453218
-rect 19794 452898 19826 453134
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-rect 19794 417454 20414 452898
-rect 19794 417218 19826 417454
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-rect 19794 416898 19826 417134
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-rect 19794 381454 20414 416898
-rect 19794 381218 19826 381454
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-rect 19794 381134 20414 381218
-rect 19794 380898 19826 381134
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-rect 19794 345454 20414 380898
-rect 19794 345218 19826 345454
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-rect 20382 345218 20414 345454
-rect 19794 345134 20414 345218
-rect 19794 344898 19826 345134
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-rect 19794 309454 20414 344898
-rect 19794 309218 19826 309454
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-rect 19794 309134 20414 309218
-rect 19794 308898 19826 309134
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-rect 19794 273454 20414 308898
-rect 19794 273218 19826 273454
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-rect 19794 273134 20414 273218
-rect 19794 272898 19826 273134
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-rect 19794 237454 20414 272898
-rect 19794 237218 19826 237454
-rect 20062 237218 20146 237454
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-rect 19794 237134 20414 237218
-rect 19794 236898 19826 237134
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-rect 19794 201454 20414 236898
-rect 19794 201218 19826 201454
-rect 20062 201218 20146 201454
-rect 20382 201218 20414 201454
-rect 19794 201134 20414 201218
-rect 19794 200898 19826 201134
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-rect 20382 200898 20414 201134
-rect 19794 165454 20414 200898
-rect 19794 165218 19826 165454
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-rect 19794 165134 20414 165218
-rect 19794 164898 19826 165134
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-rect 19794 129454 20414 164898
-rect 19794 129218 19826 129454
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-rect 19794 129134 20414 129218
-rect 19794 128898 19826 129134
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-rect 19794 93454 20414 128898
-rect 19794 93218 19826 93454
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-rect 19794 93134 20414 93218
-rect 19794 92898 19826 93134
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-rect 19794 57454 20414 92898
-rect 19794 57218 19826 57454
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-rect 20382 57218 20414 57454
-rect 19794 57134 20414 57218
-rect 19794 56898 19826 57134
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-rect 20382 56898 20414 57134
-rect 19794 21454 20414 56898
-rect 19794 21218 19826 21454
-rect 20062 21218 20146 21454
-rect 20382 21218 20414 21454
-rect 19794 21134 20414 21218
-rect 19794 20898 19826 21134
-rect 20062 20898 20146 21134
-rect 20382 20898 20414 21134
-rect 19794 -1306 20414 20898
-rect 19794 -1542 19826 -1306
-rect 20062 -1542 20146 -1306
-rect 20382 -1542 20414 -1306
-rect 19794 -1626 20414 -1542
-rect 19794 -1862 19826 -1626
-rect 20062 -1862 20146 -1626
-rect 20382 -1862 20414 -1626
-rect 19794 -1894 20414 -1862
-rect 23514 673174 24134 707162
-rect 23514 672938 23546 673174
-rect 23782 672938 23866 673174
-rect 24102 672938 24134 673174
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-rect 23514 672618 23546 672854
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-rect 24102 672618 24134 672854
-rect 23514 637174 24134 672618
-rect 23514 636938 23546 637174
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-rect 23514 636854 24134 636938
-rect 23514 636618 23546 636854
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-rect 23514 601174 24134 636618
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-rect 23514 600854 24134 600938
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-rect 23514 565174 24134 600618
-rect 23514 564938 23546 565174
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-rect 23514 564854 24134 564938
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-rect 24102 564618 24134 564854
-rect 23514 529174 24134 564618
-rect 23514 528938 23546 529174
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-rect 24102 528938 24134 529174
-rect 23514 528854 24134 528938
-rect 23514 528618 23546 528854
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-rect 23514 493174 24134 528618
-rect 23514 492938 23546 493174
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-rect 23514 492854 24134 492938
-rect 23514 492618 23546 492854
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-rect 23514 457174 24134 492618
-rect 23514 456938 23546 457174
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-rect 24102 456938 24134 457174
-rect 23514 456854 24134 456938
-rect 23514 456618 23546 456854
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-rect 23514 421174 24134 456618
-rect 23514 420938 23546 421174
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-rect 24102 420938 24134 421174
-rect 23514 420854 24134 420938
-rect 23514 420618 23546 420854
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-rect 23514 385174 24134 420618
-rect 23514 384938 23546 385174
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-rect 23514 384854 24134 384938
-rect 23514 384618 23546 384854
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-rect 24102 384618 24134 384854
-rect 23514 349174 24134 384618
-rect 23514 348938 23546 349174
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-rect 23514 348854 24134 348938
-rect 23514 348618 23546 348854
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-rect 23514 313174 24134 348618
-rect 23514 312938 23546 313174
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-rect 23514 312854 24134 312938
-rect 23514 312618 23546 312854
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-rect 24102 312618 24134 312854
-rect 23514 277174 24134 312618
-rect 23514 276938 23546 277174
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-rect 23514 276854 24134 276938
-rect 23514 276618 23546 276854
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-rect 23514 241174 24134 276618
-rect 23514 240938 23546 241174
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-rect 23514 240618 23546 240854
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-rect 23514 204854 24134 204938
-rect 23514 204618 23546 204854
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-rect 23514 169174 24134 204618
-rect 23514 168938 23546 169174
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-rect 23514 168854 24134 168938
-rect 23514 168618 23546 168854
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-rect 24102 168618 24134 168854
-rect 23514 133174 24134 168618
-rect 23514 132938 23546 133174
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-rect 24102 132938 24134 133174
-rect 23514 132854 24134 132938
-rect 23514 132618 23546 132854
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-rect 24102 132618 24134 132854
-rect 23514 97174 24134 132618
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-rect 23514 96854 24134 96938
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-rect 23514 61174 24134 96618
-rect 23514 60938 23546 61174
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-rect 24102 60938 24134 61174
-rect 23514 60854 24134 60938
-rect 23514 60618 23546 60854
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-rect 23514 24938 23546 25174
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-rect 24102 24938 24134 25174
-rect 23514 24854 24134 24938
-rect 23514 24618 23546 24854
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-rect 24102 24618 24134 24854
-rect 23514 -3226 24134 24618
-rect 23514 -3462 23546 -3226
-rect 23782 -3462 23866 -3226
-rect 24102 -3462 24134 -3226
-rect 23514 -3546 24134 -3462
-rect 23514 -3782 23546 -3546
-rect 23782 -3782 23866 -3546
-rect 24102 -3782 24134 -3546
-rect 23514 -3814 24134 -3782
-rect 27234 676894 27854 709082
-rect 27234 676658 27266 676894
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-rect 27234 676338 27266 676574
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-rect 27234 640894 27854 676338
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-rect 27234 604894 27854 640338
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-rect 27234 568894 27854 604338
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-rect 27234 532894 27854 568338
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-rect 27234 532574 27854 532658
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-rect 27234 496894 27854 532338
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-rect 27234 460894 27854 496338
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-rect 27234 424894 27854 460338
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-rect 27234 388658 27266 388894
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-rect 27234 388338 27266 388574
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-rect 27234 352894 27854 388338
-rect 27234 352658 27266 352894
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-rect 27234 352338 27266 352574
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-rect 27234 316894 27854 352338
-rect 27234 316658 27266 316894
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-rect 27234 316338 27266 316574
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-rect 27234 280894 27854 316338
-rect 27234 280658 27266 280894
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-rect 27234 280338 27266 280574
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-rect 27234 244894 27854 280338
-rect 27234 244658 27266 244894
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-rect 27234 244338 27266 244574
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-rect 27822 244338 27854 244574
-rect 27234 208894 27854 244338
-rect 27234 208658 27266 208894
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-rect 27234 208574 27854 208658
-rect 27234 208338 27266 208574
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-rect 27234 172894 27854 208338
-rect 27234 172658 27266 172894
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-rect 27234 172574 27854 172658
-rect 27234 172338 27266 172574
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-rect 27234 136894 27854 172338
-rect 27234 136658 27266 136894
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-rect 27234 136574 27854 136658
-rect 27234 136338 27266 136574
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-rect 27234 100894 27854 136338
-rect 27234 100658 27266 100894
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-rect 27822 100658 27854 100894
-rect 27234 100574 27854 100658
-rect 27234 100338 27266 100574
-rect 27502 100338 27586 100574
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-rect 27234 64894 27854 100338
-rect 27234 64658 27266 64894
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-rect 27234 64574 27854 64658
-rect 27234 64338 27266 64574
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-rect 27822 64338 27854 64574
-rect 27234 28894 27854 64338
-rect 27234 28658 27266 28894
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-rect 27822 28658 27854 28894
-rect 27234 28574 27854 28658
-rect 27234 28338 27266 28574
-rect 27502 28338 27586 28574
-rect 27822 28338 27854 28574
-rect 27234 -5146 27854 28338
-rect 27234 -5382 27266 -5146
-rect 27502 -5382 27586 -5146
-rect 27822 -5382 27854 -5146
-rect 27234 -5466 27854 -5382
-rect 27234 -5702 27266 -5466
-rect 27502 -5702 27586 -5466
-rect 27822 -5702 27854 -5466
-rect 27234 -5734 27854 -5702
-rect 30954 680614 31574 711002
-rect 48954 710598 49574 711590
-rect 48954 710362 48986 710598
-rect 49222 710362 49306 710598
-rect 49542 710362 49574 710598
-rect 48954 710278 49574 710362
-rect 48954 710042 48986 710278
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-rect 45234 708678 45854 709670
-rect 45234 708442 45266 708678
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-rect 45234 708358 45854 708442
-rect 45234 708122 45266 708358
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-rect 41514 706758 42134 707750
-rect 41514 706522 41546 706758
-rect 41782 706522 41866 706758
-rect 42102 706522 42134 706758
-rect 41514 706438 42134 706522
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-rect 41782 706202 41866 706438
-rect 42102 706202 42134 706438
-rect 30954 680378 30986 680614
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-rect 30954 680294 31574 680378
-rect 30954 680058 30986 680294
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-rect 30954 644614 31574 680058
-rect 30954 644378 30986 644614
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-rect 30954 644294 31574 644378
-rect 30954 644058 30986 644294
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-rect 30954 608614 31574 644058
-rect 30954 608378 30986 608614
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-rect 30954 608058 30986 608294
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-rect 30954 572614 31574 608058
-rect 30954 572378 30986 572614
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-rect 30954 572294 31574 572378
-rect 30954 572058 30986 572294
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-rect 30954 536378 30986 536614
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-rect 30954 536294 31574 536378
-rect 30954 536058 30986 536294
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-rect 30954 500614 31574 536058
-rect 30954 500378 30986 500614
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-rect 31542 500378 31574 500614
-rect 30954 500294 31574 500378
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-rect 30954 464378 30986 464614
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-rect 30954 428058 30986 428294
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-rect 30954 392614 31574 428058
-rect 30954 392378 30986 392614
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-rect 30954 392294 31574 392378
-rect 30954 392058 30986 392294
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-rect 30954 356378 30986 356614
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-rect 31542 356378 31574 356614
-rect 30954 356294 31574 356378
-rect 30954 356058 30986 356294
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-rect 30954 320614 31574 356058
-rect 30954 320378 30986 320614
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-rect 30954 320058 30986 320294
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-rect 30954 284378 30986 284614
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-rect 31542 284378 31574 284614
-rect 30954 284294 31574 284378
-rect 30954 284058 30986 284294
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-rect 30954 248378 30986 248614
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-rect 30954 212614 31574 248058
-rect 30954 212378 30986 212614
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-rect 30954 212294 31574 212378
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-rect 30954 176378 30986 176614
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-rect 31542 176378 31574 176614
-rect 30954 176294 31574 176378
-rect 30954 176058 30986 176294
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-rect 30954 140614 31574 176058
-rect 30954 140378 30986 140614
-rect 31222 140378 31306 140614
-rect 31542 140378 31574 140614
-rect 30954 140294 31574 140378
-rect 30954 140058 30986 140294
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-rect 30954 104378 30986 104614
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-rect 30954 104294 31574 104378
-rect 30954 104058 30986 104294
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-rect 30954 68614 31574 104058
-rect 30954 68378 30986 68614
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-rect 30954 68294 31574 68378
-rect 30954 68058 30986 68294
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-rect 30954 32614 31574 68058
-rect 30954 32378 30986 32614
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-rect 30954 32294 31574 32378
-rect 30954 32058 30986 32294
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-rect 12954 -6342 12986 -6106
-rect 13222 -6342 13306 -6106
-rect 13542 -6342 13574 -6106
-rect 12954 -6426 13574 -6342
-rect 12954 -6662 12986 -6426
-rect 13222 -6662 13306 -6426
-rect 13542 -6662 13574 -6426
-rect -8726 -7302 -8694 -7066
-rect -8458 -7302 -8374 -7066
-rect -8138 -7302 -8106 -7066
-rect -8726 -7386 -8106 -7302
-rect -8726 -7622 -8694 -7386
-rect -8458 -7622 -8374 -7386
-rect -8138 -7622 -8106 -7386
-rect -8726 -7654 -8106 -7622
-rect 12954 -7654 13574 -6662
-rect 30954 -7066 31574 32058
-rect 37794 704838 38414 705830
-rect 37794 704602 37826 704838
-rect 38062 704602 38146 704838
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-rect 37794 704518 38414 704602
-rect 37794 704282 37826 704518
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-rect 37794 687454 38414 704282
-rect 37794 687218 37826 687454
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-rect 37794 686898 37826 687134
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-rect 37794 651454 38414 686898
-rect 37794 651218 37826 651454
-rect 38062 651218 38146 651454
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-rect 37794 650898 37826 651134
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-rect 37794 615454 38414 650898
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-rect 37794 614898 37826 615134
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-rect 37794 579454 38414 614898
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-rect 37794 578898 37826 579134
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-rect 37794 543454 38414 578898
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-rect 37794 542898 37826 543134
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-rect 37794 507454 38414 542898
-rect 37794 507218 37826 507454
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-rect 37794 506898 37826 507134
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-rect 37794 471454 38414 506898
-rect 37794 471218 37826 471454
-rect 38062 471218 38146 471454
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-rect 37794 470898 37826 471134
-rect 38062 470898 38146 471134
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-rect 37794 435454 38414 470898
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-rect 37794 435134 38414 435218
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-rect 37794 399454 38414 434898
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-rect 37794 363454 38414 398898
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-rect 38062 363218 38146 363454
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-rect 37794 363134 38414 363218
-rect 37794 362898 37826 363134
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-rect 37794 327454 38414 362898
-rect 37794 327218 37826 327454
-rect 38062 327218 38146 327454
-rect 38382 327218 38414 327454
-rect 37794 327134 38414 327218
-rect 37794 326898 37826 327134
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-rect 37794 291454 38414 326898
-rect 37794 291218 37826 291454
-rect 38062 291218 38146 291454
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-rect 37794 291134 38414 291218
-rect 37794 290898 37826 291134
-rect 38062 290898 38146 291134
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-rect 37794 255454 38414 290898
-rect 37794 255218 37826 255454
-rect 38062 255218 38146 255454
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-rect 37794 255134 38414 255218
-rect 37794 254898 37826 255134
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-rect 37794 219454 38414 254898
-rect 37794 219218 37826 219454
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-rect 38382 219218 38414 219454
-rect 37794 219134 38414 219218
-rect 37794 218898 37826 219134
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-rect 38382 218898 38414 219134
-rect 37794 183454 38414 218898
-rect 37794 183218 37826 183454
-rect 38062 183218 38146 183454
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-rect 37794 183134 38414 183218
-rect 37794 182898 37826 183134
-rect 38062 182898 38146 183134
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-rect 37794 147454 38414 182898
-rect 37794 147218 37826 147454
-rect 38062 147218 38146 147454
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-rect 37794 147134 38414 147218
-rect 37794 146898 37826 147134
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-rect 37794 111454 38414 146898
-rect 37794 111218 37826 111454
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-rect 37794 111134 38414 111218
-rect 37794 110898 37826 111134
-rect 38062 110898 38146 111134
-rect 38382 110898 38414 111134
-rect 37794 75454 38414 110898
-rect 37794 75218 37826 75454
-rect 38062 75218 38146 75454
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-rect 37794 75134 38414 75218
-rect 37794 74898 37826 75134
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-rect 37794 39454 38414 74898
-rect 37794 39218 37826 39454
-rect 38062 39218 38146 39454
-rect 38382 39218 38414 39454
-rect 37794 39134 38414 39218
-rect 37794 38898 37826 39134
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-rect 38382 38898 38414 39134
-rect 37794 3454 38414 38898
-rect 37794 3218 37826 3454
-rect 38062 3218 38146 3454
-rect 38382 3218 38414 3454
-rect 37794 3134 38414 3218
-rect 37794 2898 37826 3134
-rect 38062 2898 38146 3134
-rect 38382 2898 38414 3134
-rect 37794 -346 38414 2898
-rect 37794 -582 37826 -346
-rect 38062 -582 38146 -346
-rect 38382 -582 38414 -346
-rect 37794 -666 38414 -582
-rect 37794 -902 37826 -666
-rect 38062 -902 38146 -666
-rect 38382 -902 38414 -666
-rect 37794 -1894 38414 -902
-rect 41514 691174 42134 706202
-rect 41514 690938 41546 691174
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-rect 42102 690938 42134 691174
-rect 41514 690854 42134 690938
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-rect 41514 655174 42134 690618
-rect 41514 654938 41546 655174
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-rect 42102 654938 42134 655174
-rect 41514 654854 42134 654938
-rect 41514 654618 41546 654854
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-rect 41514 618854 42134 618938
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-rect 42102 618618 42134 618854
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-rect 41514 582938 41546 583174
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-rect 41514 582854 42134 582938
-rect 41514 582618 41546 582854
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-rect 42102 582618 42134 582854
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-rect 42102 546938 42134 547174
-rect 41514 546854 42134 546938
-rect 41514 546618 41546 546854
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-rect 42102 546618 42134 546854
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-rect 42102 510938 42134 511174
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-rect 41514 474854 42134 474938
-rect 41514 474618 41546 474854
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-rect 41514 403174 42134 438618
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-rect 42102 402938 42134 403174
-rect 41514 402854 42134 402938
-rect 41514 402618 41546 402854
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-rect 42102 402618 42134 402854
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-rect 41514 366938 41546 367174
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-rect 42102 366938 42134 367174
-rect 41514 366854 42134 366938
-rect 41514 366618 41546 366854
-rect 41782 366618 41866 366854
-rect 42102 366618 42134 366854
-rect 41514 331174 42134 366618
-rect 41514 330938 41546 331174
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-rect 42102 330938 42134 331174
-rect 41514 330854 42134 330938
-rect 41514 330618 41546 330854
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-rect 42102 330618 42134 330854
-rect 41514 295174 42134 330618
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-rect 42102 294938 42134 295174
-rect 41514 294854 42134 294938
-rect 41514 294618 41546 294854
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-rect 41514 259174 42134 294618
-rect 41514 258938 41546 259174
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-rect 42102 258938 42134 259174
-rect 41514 258854 42134 258938
-rect 41514 258618 41546 258854
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-rect 42102 258618 42134 258854
-rect 41514 223174 42134 258618
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-rect 42102 222938 42134 223174
-rect 41514 222854 42134 222938
-rect 41514 222618 41546 222854
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-rect 42102 222618 42134 222854
-rect 41514 187174 42134 222618
-rect 41514 186938 41546 187174
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-rect 42102 186938 42134 187174
-rect 41514 186854 42134 186938
-rect 41514 186618 41546 186854
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-rect 42102 186618 42134 186854
-rect 41514 151174 42134 186618
-rect 41514 150938 41546 151174
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-rect 42102 150938 42134 151174
-rect 41514 150854 42134 150938
-rect 41514 150618 41546 150854
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-rect 42102 150618 42134 150854
-rect 41514 115174 42134 150618
-rect 41514 114938 41546 115174
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-rect 42102 114938 42134 115174
-rect 41514 114854 42134 114938
-rect 41514 114618 41546 114854
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-rect 42102 114618 42134 114854
-rect 41514 79174 42134 114618
-rect 41514 78938 41546 79174
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-rect 42102 78938 42134 79174
-rect 41514 78854 42134 78938
-rect 41514 78618 41546 78854
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-rect 42102 78618 42134 78854
-rect 41514 43174 42134 78618
-rect 41514 42938 41546 43174
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-rect 42102 42938 42134 43174
-rect 41514 42854 42134 42938
-rect 41514 42618 41546 42854
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-rect 42102 42618 42134 42854
-rect 41514 7174 42134 42618
-rect 41514 6938 41546 7174
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-rect 42102 6938 42134 7174
-rect 41514 6854 42134 6938
-rect 41514 6618 41546 6854
-rect 41782 6618 41866 6854
-rect 42102 6618 42134 6854
-rect 41514 -2266 42134 6618
-rect 41514 -2502 41546 -2266
-rect 41782 -2502 41866 -2266
-rect 42102 -2502 42134 -2266
-rect 41514 -2586 42134 -2502
-rect 41514 -2822 41546 -2586
-rect 41782 -2822 41866 -2586
-rect 42102 -2822 42134 -2586
-rect 41514 -3814 42134 -2822
-rect 45234 694894 45854 708122
-rect 45234 694658 45266 694894
-rect 45502 694658 45586 694894
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-rect 45234 694574 45854 694658
-rect 45234 694338 45266 694574
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-rect 45234 658894 45854 694338
-rect 45234 658658 45266 658894
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-rect 45234 658574 45854 658658
-rect 45234 658338 45266 658574
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-rect 45234 622894 45854 658338
-rect 45234 622658 45266 622894
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-rect 45234 622574 45854 622658
-rect 45234 622338 45266 622574
-rect 45502 622338 45586 622574
-rect 45822 622338 45854 622574
-rect 45234 586894 45854 622338
-rect 45234 586658 45266 586894
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-rect 45234 586574 45854 586658
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-rect 45234 550894 45854 586338
-rect 45234 550658 45266 550894
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-rect 45234 550574 45854 550658
-rect 45234 550338 45266 550574
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-rect 45234 514894 45854 550338
-rect 45234 514658 45266 514894
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-rect 45234 514338 45266 514574
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-rect 45234 478894 45854 514338
-rect 45234 478658 45266 478894
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-rect 45822 478658 45854 478894
-rect 45234 478574 45854 478658
-rect 45234 478338 45266 478574
-rect 45502 478338 45586 478574
-rect 45822 478338 45854 478574
-rect 45234 442894 45854 478338
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-rect 73794 704838 74414 705830
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-rect 77514 691174 78134 706202
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-rect 113514 691174 114134 706202
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-rect 117234 694894 117854 708122
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-rect 120954 698614 121574 710042
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-rect 199794 705242 199826 705478
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-rect 199794 669454 200414 705242
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-rect 199794 308898 199826 309134
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-rect 199794 273454 200414 308898
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-rect 199794 237454 200414 272898
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-rect 199794 201218 199826 201454
-rect 200062 201218 200146 201454
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-rect 199794 201134 200414 201218
-rect 199794 200898 199826 201134
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-rect 199794 164898 199826 165134
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-rect 199794 128898 199826 129134
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-rect 199794 93454 200414 128898
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-rect 199794 92898 199826 93134
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-rect 199794 57454 200414 92898
-rect 199794 57218 199826 57454
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-rect 199794 56898 199826 57134
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-rect 199794 21454 200414 56898
-rect 199794 21218 199826 21454
-rect 200062 21218 200146 21454
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-rect 199794 21134 200414 21218
-rect 199794 20898 199826 21134
-rect 200062 20898 200146 21134
-rect 200382 20898 200414 21134
-rect 199794 -1306 200414 20898
-rect 199794 -1542 199826 -1306
-rect 200062 -1542 200146 -1306
-rect 200382 -1542 200414 -1306
-rect 199794 -1626 200414 -1542
-rect 199794 -1862 199826 -1626
-rect 200062 -1862 200146 -1626
-rect 200382 -1862 200414 -1626
-rect 199794 -1894 200414 -1862
-rect 203514 673174 204134 707162
-rect 203514 672938 203546 673174
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-rect 203514 421174 204134 456618
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-rect 203514 277174 204134 312618
-rect 203514 276938 203546 277174
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-rect 204102 276938 204134 277174
-rect 203514 276854 204134 276938
-rect 203514 276618 203546 276854
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-rect 203514 241174 204134 276618
-rect 203514 240938 203546 241174
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-rect 203514 240618 203546 240854
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-rect 203514 204938 203546 205174
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-rect 204102 204938 204134 205174
-rect 203514 204854 204134 204938
-rect 203514 204618 203546 204854
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-rect 203514 168938 203546 169174
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-rect 203514 168854 204134 168938
-rect 203514 168618 203546 168854
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-rect 203514 133174 204134 168618
-rect 203514 132938 203546 133174
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-rect 203514 132618 203546 132854
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-rect 203514 97174 204134 132618
-rect 203514 96938 203546 97174
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-rect 203514 96854 204134 96938
-rect 203514 96618 203546 96854
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-rect 203514 61174 204134 96618
-rect 203514 60938 203546 61174
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-rect 204102 60938 204134 61174
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-rect 203514 60618 203546 60854
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-rect 204102 24938 204134 25174
-rect 203514 24854 204134 24938
-rect 203514 24618 203546 24854
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-rect 203514 -3226 204134 24618
-rect 203514 -3462 203546 -3226
-rect 203782 -3462 203866 -3226
-rect 204102 -3462 204134 -3226
-rect 203514 -3546 204134 -3462
-rect 203514 -3782 203546 -3546
-rect 203782 -3782 203866 -3546
-rect 204102 -3782 204134 -3546
-rect 203514 -3814 204134 -3782
-rect 207234 676894 207854 709082
-rect 207234 676658 207266 676894
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-rect 207822 568338 207854 568574
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-rect 207822 460338 207854 460574
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-rect 207822 424338 207854 424574
-rect 207234 388894 207854 424338
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-rect 207822 388658 207854 388894
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-rect 207234 352894 207854 388338
-rect 207234 352658 207266 352894
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-rect 207234 352338 207266 352574
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-rect 207822 352338 207854 352574
-rect 207234 316894 207854 352338
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-rect 207822 316658 207854 316894
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-rect 207234 280894 207854 316338
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-rect 207502 280658 207586 280894
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-rect 207234 280574 207854 280658
-rect 207234 280338 207266 280574
-rect 207502 280338 207586 280574
-rect 207822 280338 207854 280574
-rect 207234 244894 207854 280338
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-rect 207234 244338 207266 244574
-rect 207502 244338 207586 244574
-rect 207822 244338 207854 244574
-rect 207234 208894 207854 244338
-rect 207234 208658 207266 208894
-rect 207502 208658 207586 208894
-rect 207822 208658 207854 208894
-rect 207234 208574 207854 208658
-rect 207234 208338 207266 208574
-rect 207502 208338 207586 208574
-rect 207822 208338 207854 208574
-rect 207234 172894 207854 208338
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-rect 207502 172658 207586 172894
-rect 207822 172658 207854 172894
-rect 207234 172574 207854 172658
-rect 207234 172338 207266 172574
-rect 207502 172338 207586 172574
-rect 207822 172338 207854 172574
-rect 207234 136894 207854 172338
-rect 207234 136658 207266 136894
-rect 207502 136658 207586 136894
-rect 207822 136658 207854 136894
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-rect 207502 136338 207586 136574
-rect 207822 136338 207854 136574
-rect 207234 100894 207854 136338
-rect 207234 100658 207266 100894
-rect 207502 100658 207586 100894
-rect 207822 100658 207854 100894
-rect 207234 100574 207854 100658
-rect 207234 100338 207266 100574
-rect 207502 100338 207586 100574
-rect 207822 100338 207854 100574
-rect 207234 64894 207854 100338
-rect 207234 64658 207266 64894
-rect 207502 64658 207586 64894
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-rect 207234 64574 207854 64658
-rect 207234 64338 207266 64574
-rect 207502 64338 207586 64574
-rect 207822 64338 207854 64574
-rect 207234 28894 207854 64338
-rect 207234 28658 207266 28894
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-rect 207822 28658 207854 28894
-rect 207234 28574 207854 28658
-rect 207234 28338 207266 28574
-rect 207502 28338 207586 28574
-rect 207822 28338 207854 28574
-rect 207234 -5146 207854 28338
-rect 207234 -5382 207266 -5146
-rect 207502 -5382 207586 -5146
-rect 207822 -5382 207854 -5146
-rect 207234 -5466 207854 -5382
-rect 207234 -5702 207266 -5466
-rect 207502 -5702 207586 -5466
-rect 207822 -5702 207854 -5466
-rect 207234 -5734 207854 -5702
-rect 210954 680614 211574 711002
-rect 228954 710598 229574 711590
-rect 228954 710362 228986 710598
-rect 229222 710362 229306 710598
-rect 229542 710362 229574 710598
-rect 228954 710278 229574 710362
-rect 228954 710042 228986 710278
-rect 229222 710042 229306 710278
-rect 229542 710042 229574 710278
-rect 225234 708678 225854 709670
-rect 225234 708442 225266 708678
-rect 225502 708442 225586 708678
-rect 225822 708442 225854 708678
-rect 225234 708358 225854 708442
-rect 225234 708122 225266 708358
-rect 225502 708122 225586 708358
-rect 225822 708122 225854 708358
-rect 221514 706758 222134 707750
-rect 221514 706522 221546 706758
-rect 221782 706522 221866 706758
-rect 222102 706522 222134 706758
-rect 221514 706438 222134 706522
-rect 221514 706202 221546 706438
-rect 221782 706202 221866 706438
-rect 222102 706202 222134 706438
-rect 210954 680378 210986 680614
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-rect 210954 680294 211574 680378
-rect 210954 680058 210986 680294
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-rect 211542 680058 211574 680294
-rect 210954 644614 211574 680058
-rect 210954 644378 210986 644614
-rect 211222 644378 211306 644614
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-rect 210954 644294 211574 644378
-rect 210954 644058 210986 644294
-rect 211222 644058 211306 644294
-rect 211542 644058 211574 644294
-rect 210954 608614 211574 644058
-rect 210954 608378 210986 608614
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-rect 210954 608058 210986 608294
-rect 211222 608058 211306 608294
-rect 211542 608058 211574 608294
-rect 210954 572614 211574 608058
-rect 210954 572378 210986 572614
-rect 211222 572378 211306 572614
-rect 211542 572378 211574 572614
-rect 210954 572294 211574 572378
-rect 210954 572058 210986 572294
-rect 211222 572058 211306 572294
-rect 211542 572058 211574 572294
-rect 210954 536614 211574 572058
-rect 210954 536378 210986 536614
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-rect 211542 536378 211574 536614
-rect 210954 536294 211574 536378
-rect 210954 536058 210986 536294
-rect 211222 536058 211306 536294
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-rect 210954 500614 211574 536058
-rect 210954 500378 210986 500614
-rect 211222 500378 211306 500614
-rect 211542 500378 211574 500614
-rect 210954 500294 211574 500378
-rect 210954 500058 210986 500294
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-rect 211542 500058 211574 500294
-rect 210954 464614 211574 500058
-rect 210954 464378 210986 464614
-rect 211222 464378 211306 464614
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-rect 210954 464294 211574 464378
-rect 210954 464058 210986 464294
-rect 211222 464058 211306 464294
-rect 211542 464058 211574 464294
-rect 210954 428614 211574 464058
-rect 210954 428378 210986 428614
-rect 211222 428378 211306 428614
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-rect 210954 428294 211574 428378
-rect 210954 428058 210986 428294
-rect 211222 428058 211306 428294
-rect 211542 428058 211574 428294
-rect 210954 392614 211574 428058
-rect 210954 392378 210986 392614
-rect 211222 392378 211306 392614
-rect 211542 392378 211574 392614
-rect 210954 392294 211574 392378
-rect 210954 392058 210986 392294
-rect 211222 392058 211306 392294
-rect 211542 392058 211574 392294
-rect 210954 356614 211574 392058
-rect 210954 356378 210986 356614
-rect 211222 356378 211306 356614
-rect 211542 356378 211574 356614
-rect 210954 356294 211574 356378
-rect 210954 356058 210986 356294
-rect 211222 356058 211306 356294
-rect 211542 356058 211574 356294
-rect 210954 320614 211574 356058
-rect 210954 320378 210986 320614
-rect 211222 320378 211306 320614
-rect 211542 320378 211574 320614
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-rect 311514 707718 312134 707750
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-rect 300954 698378 300986 698614
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-rect 307794 705798 308414 705830
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-rect 307794 525218 307826 525454
-rect 308062 525218 308146 525454
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-rect 311514 673174 312134 707162
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-rect 351234 676894 351854 709082
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-rect 275514 313174 276134 336000
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-rect 279234 316894 279854 336000
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-rect 282954 320614 283574 336000
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-rect 264954 -6342 264986 -6106
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-rect 289794 327454 290414 338000
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-rect 290382 254898 290414 255134
-rect 289794 219454 290414 254898
-rect 289794 219218 289826 219454
-rect 290062 219218 290146 219454
-rect 290382 219218 290414 219454
-rect 289794 219134 290414 219218
-rect 289794 218898 289826 219134
-rect 290062 218898 290146 219134
-rect 290382 218898 290414 219134
-rect 289794 183454 290414 218898
-rect 289794 183218 289826 183454
-rect 290062 183218 290146 183454
-rect 290382 183218 290414 183454
-rect 289794 183134 290414 183218
-rect 289794 182898 289826 183134
-rect 290062 182898 290146 183134
-rect 290382 182898 290414 183134
-rect 289794 147454 290414 182898
-rect 289794 147218 289826 147454
-rect 290062 147218 290146 147454
-rect 290382 147218 290414 147454
-rect 289794 147134 290414 147218
-rect 289794 146898 289826 147134
-rect 290062 146898 290146 147134
-rect 290382 146898 290414 147134
-rect 289794 111454 290414 146898
-rect 289794 111218 289826 111454
-rect 290062 111218 290146 111454
-rect 290382 111218 290414 111454
-rect 289794 111134 290414 111218
-rect 289794 110898 289826 111134
-rect 290062 110898 290146 111134
-rect 290382 110898 290414 111134
-rect 289794 75454 290414 110898
-rect 289794 75218 289826 75454
-rect 290062 75218 290146 75454
-rect 290382 75218 290414 75454
-rect 289794 75134 290414 75218
-rect 289794 74898 289826 75134
-rect 290062 74898 290146 75134
-rect 290382 74898 290414 75134
-rect 289794 39454 290414 74898
-rect 289794 39218 289826 39454
-rect 290062 39218 290146 39454
-rect 290382 39218 290414 39454
-rect 289794 39134 290414 39218
-rect 289794 38898 289826 39134
-rect 290062 38898 290146 39134
-rect 290382 38898 290414 39134
-rect 289794 3454 290414 38898
-rect 289794 3218 289826 3454
-rect 290062 3218 290146 3454
-rect 290382 3218 290414 3454
-rect 289794 3134 290414 3218
-rect 289794 2898 289826 3134
-rect 290062 2898 290146 3134
-rect 290382 2898 290414 3134
-rect 289794 -346 290414 2898
-rect 289794 -582 289826 -346
-rect 290062 -582 290146 -346
-rect 290382 -582 290414 -346
-rect 289794 -666 290414 -582
-rect 289794 -902 289826 -666
-rect 290062 -902 290146 -666
-rect 290382 -902 290414 -666
-rect 289794 -1894 290414 -902
-rect 293514 331174 294134 336000
-rect 293514 330938 293546 331174
-rect 293782 330938 293866 331174
-rect 294102 330938 294134 331174
-rect 293514 330854 294134 330938
-rect 293514 330618 293546 330854
-rect 293782 330618 293866 330854
-rect 294102 330618 294134 330854
-rect 293514 295174 294134 330618
-rect 293514 294938 293546 295174
-rect 293782 294938 293866 295174
-rect 294102 294938 294134 295174
-rect 293514 294854 294134 294938
-rect 293514 294618 293546 294854
-rect 293782 294618 293866 294854
-rect 294102 294618 294134 294854
-rect 293514 259174 294134 294618
-rect 293514 258938 293546 259174
-rect 293782 258938 293866 259174
-rect 294102 258938 294134 259174
-rect 293514 258854 294134 258938
-rect 293514 258618 293546 258854
-rect 293782 258618 293866 258854
-rect 294102 258618 294134 258854
-rect 293514 223174 294134 258618
-rect 293514 222938 293546 223174
-rect 293782 222938 293866 223174
-rect 294102 222938 294134 223174
-rect 293514 222854 294134 222938
-rect 293514 222618 293546 222854
-rect 293782 222618 293866 222854
-rect 294102 222618 294134 222854
-rect 293514 187174 294134 222618
-rect 293514 186938 293546 187174
-rect 293782 186938 293866 187174
-rect 294102 186938 294134 187174
-rect 293514 186854 294134 186938
-rect 293514 186618 293546 186854
-rect 293782 186618 293866 186854
-rect 294102 186618 294134 186854
-rect 293514 151174 294134 186618
-rect 293514 150938 293546 151174
-rect 293782 150938 293866 151174
-rect 294102 150938 294134 151174
-rect 293514 150854 294134 150938
-rect 293514 150618 293546 150854
-rect 293782 150618 293866 150854
-rect 294102 150618 294134 150854
-rect 293514 115174 294134 150618
-rect 293514 114938 293546 115174
-rect 293782 114938 293866 115174
-rect 294102 114938 294134 115174
-rect 293514 114854 294134 114938
-rect 293514 114618 293546 114854
-rect 293782 114618 293866 114854
-rect 294102 114618 294134 114854
-rect 293514 79174 294134 114618
-rect 293514 78938 293546 79174
-rect 293782 78938 293866 79174
-rect 294102 78938 294134 79174
-rect 293514 78854 294134 78938
-rect 293514 78618 293546 78854
-rect 293782 78618 293866 78854
-rect 294102 78618 294134 78854
-rect 293514 43174 294134 78618
-rect 293514 42938 293546 43174
-rect 293782 42938 293866 43174
-rect 294102 42938 294134 43174
-rect 293514 42854 294134 42938
-rect 293514 42618 293546 42854
-rect 293782 42618 293866 42854
-rect 294102 42618 294134 42854
-rect 293514 7174 294134 42618
-rect 293514 6938 293546 7174
-rect 293782 6938 293866 7174
-rect 294102 6938 294134 7174
-rect 293514 6854 294134 6938
-rect 293514 6618 293546 6854
-rect 293782 6618 293866 6854
-rect 294102 6618 294134 6854
-rect 293514 -2266 294134 6618
-rect 293514 -2502 293546 -2266
-rect 293782 -2502 293866 -2266
-rect 294102 -2502 294134 -2266
-rect 293514 -2586 294134 -2502
-rect 293514 -2822 293546 -2586
-rect 293782 -2822 293866 -2586
-rect 294102 -2822 294134 -2586
-rect 293514 -3814 294134 -2822
-rect 297234 334894 297854 336000
-rect 297234 334658 297266 334894
-rect 297502 334658 297586 334894
-rect 297822 334658 297854 334894
-rect 297234 334574 297854 334658
-rect 297234 334338 297266 334574
-rect 297502 334338 297586 334574
-rect 297822 334338 297854 334574
-rect 297234 298894 297854 334338
-rect 297234 298658 297266 298894
-rect 297502 298658 297586 298894
-rect 297822 298658 297854 298894
-rect 297234 298574 297854 298658
-rect 297234 298338 297266 298574
-rect 297502 298338 297586 298574
-rect 297822 298338 297854 298574
-rect 297234 262894 297854 298338
-rect 297234 262658 297266 262894
-rect 297502 262658 297586 262894
-rect 297822 262658 297854 262894
-rect 297234 262574 297854 262658
-rect 297234 262338 297266 262574
-rect 297502 262338 297586 262574
-rect 297822 262338 297854 262574
-rect 297234 226894 297854 262338
-rect 297234 226658 297266 226894
-rect 297502 226658 297586 226894
-rect 297822 226658 297854 226894
-rect 297234 226574 297854 226658
-rect 297234 226338 297266 226574
-rect 297502 226338 297586 226574
-rect 297822 226338 297854 226574
-rect 297234 190894 297854 226338
-rect 297234 190658 297266 190894
-rect 297502 190658 297586 190894
-rect 297822 190658 297854 190894
-rect 297234 190574 297854 190658
-rect 297234 190338 297266 190574
-rect 297502 190338 297586 190574
-rect 297822 190338 297854 190574
-rect 297234 154894 297854 190338
-rect 297234 154658 297266 154894
-rect 297502 154658 297586 154894
-rect 297822 154658 297854 154894
-rect 297234 154574 297854 154658
-rect 297234 154338 297266 154574
-rect 297502 154338 297586 154574
-rect 297822 154338 297854 154574
-rect 297234 118894 297854 154338
-rect 297234 118658 297266 118894
-rect 297502 118658 297586 118894
-rect 297822 118658 297854 118894
-rect 297234 118574 297854 118658
-rect 297234 118338 297266 118574
-rect 297502 118338 297586 118574
-rect 297822 118338 297854 118574
-rect 297234 82894 297854 118338
-rect 297234 82658 297266 82894
-rect 297502 82658 297586 82894
-rect 297822 82658 297854 82894
-rect 297234 82574 297854 82658
-rect 297234 82338 297266 82574
-rect 297502 82338 297586 82574
-rect 297822 82338 297854 82574
-rect 297234 46894 297854 82338
-rect 297234 46658 297266 46894
-rect 297502 46658 297586 46894
-rect 297822 46658 297854 46894
-rect 297234 46574 297854 46658
-rect 297234 46338 297266 46574
-rect 297502 46338 297586 46574
-rect 297822 46338 297854 46574
-rect 297234 10894 297854 46338
-rect 297234 10658 297266 10894
-rect 297502 10658 297586 10894
-rect 297822 10658 297854 10894
-rect 297234 10574 297854 10658
-rect 297234 10338 297266 10574
-rect 297502 10338 297586 10574
-rect 297822 10338 297854 10574
-rect 297234 -4186 297854 10338
-rect 297234 -4422 297266 -4186
-rect 297502 -4422 297586 -4186
-rect 297822 -4422 297854 -4186
-rect 297234 -4506 297854 -4422
-rect 297234 -4742 297266 -4506
-rect 297502 -4742 297586 -4506
-rect 297822 -4742 297854 -4506
-rect 297234 -5734 297854 -4742
-rect 300954 302614 301574 336000
-rect 300954 302378 300986 302614
-rect 301222 302378 301306 302614
-rect 301542 302378 301574 302614
-rect 300954 302294 301574 302378
-rect 300954 302058 300986 302294
-rect 301222 302058 301306 302294
-rect 301542 302058 301574 302294
-rect 300954 266614 301574 302058
-rect 300954 266378 300986 266614
-rect 301222 266378 301306 266614
-rect 301542 266378 301574 266614
-rect 300954 266294 301574 266378
-rect 300954 266058 300986 266294
-rect 301222 266058 301306 266294
-rect 301542 266058 301574 266294
-rect 300954 230614 301574 266058
-rect 300954 230378 300986 230614
-rect 301222 230378 301306 230614
-rect 301542 230378 301574 230614
-rect 300954 230294 301574 230378
-rect 300954 230058 300986 230294
-rect 301222 230058 301306 230294
-rect 301542 230058 301574 230294
-rect 300954 194614 301574 230058
-rect 300954 194378 300986 194614
-rect 301222 194378 301306 194614
-rect 301542 194378 301574 194614
-rect 300954 194294 301574 194378
-rect 300954 194058 300986 194294
-rect 301222 194058 301306 194294
-rect 301542 194058 301574 194294
-rect 300954 158614 301574 194058
-rect 300954 158378 300986 158614
-rect 301222 158378 301306 158614
-rect 301542 158378 301574 158614
-rect 300954 158294 301574 158378
-rect 300954 158058 300986 158294
-rect 301222 158058 301306 158294
-rect 301542 158058 301574 158294
-rect 300954 122614 301574 158058
-rect 300954 122378 300986 122614
-rect 301222 122378 301306 122614
-rect 301542 122378 301574 122614
-rect 300954 122294 301574 122378
-rect 300954 122058 300986 122294
-rect 301222 122058 301306 122294
-rect 301542 122058 301574 122294
-rect 300954 86614 301574 122058
-rect 300954 86378 300986 86614
-rect 301222 86378 301306 86614
-rect 301542 86378 301574 86614
-rect 300954 86294 301574 86378
-rect 300954 86058 300986 86294
-rect 301222 86058 301306 86294
-rect 301542 86058 301574 86294
-rect 300954 50614 301574 86058
-rect 300954 50378 300986 50614
-rect 301222 50378 301306 50614
-rect 301542 50378 301574 50614
-rect 300954 50294 301574 50378
-rect 300954 50058 300986 50294
-rect 301222 50058 301306 50294
-rect 301542 50058 301574 50294
-rect 300954 14614 301574 50058
-rect 300954 14378 300986 14614
-rect 301222 14378 301306 14614
-rect 301542 14378 301574 14614
-rect 300954 14294 301574 14378
-rect 300954 14058 300986 14294
-rect 301222 14058 301306 14294
-rect 301542 14058 301574 14294
-rect 282954 -7302 282986 -7066
-rect 283222 -7302 283306 -7066
-rect 283542 -7302 283574 -7066
-rect 282954 -7386 283574 -7302
-rect 282954 -7622 282986 -7386
-rect 283222 -7622 283306 -7386
-rect 283542 -7622 283574 -7386
-rect 282954 -7654 283574 -7622
-rect 300954 -6106 301574 14058
-rect 307794 309454 308414 338000
-rect 307794 309218 307826 309454
-rect 308062 309218 308146 309454
-rect 308382 309218 308414 309454
-rect 307794 309134 308414 309218
-rect 307794 308898 307826 309134
-rect 308062 308898 308146 309134
-rect 308382 308898 308414 309134
-rect 307794 273454 308414 308898
-rect 307794 273218 307826 273454
-rect 308062 273218 308146 273454
-rect 308382 273218 308414 273454
-rect 307794 273134 308414 273218
-rect 307794 272898 307826 273134
-rect 308062 272898 308146 273134
-rect 308382 272898 308414 273134
-rect 307794 237454 308414 272898
-rect 307794 237218 307826 237454
-rect 308062 237218 308146 237454
-rect 308382 237218 308414 237454
-rect 307794 237134 308414 237218
-rect 307794 236898 307826 237134
-rect 308062 236898 308146 237134
-rect 308382 236898 308414 237134
-rect 307794 201454 308414 236898
-rect 307794 201218 307826 201454
-rect 308062 201218 308146 201454
-rect 308382 201218 308414 201454
-rect 307794 201134 308414 201218
-rect 307794 200898 307826 201134
-rect 308062 200898 308146 201134
-rect 308382 200898 308414 201134
-rect 307794 165454 308414 200898
-rect 307794 165218 307826 165454
-rect 308062 165218 308146 165454
-rect 308382 165218 308414 165454
-rect 307794 165134 308414 165218
-rect 307794 164898 307826 165134
-rect 308062 164898 308146 165134
-rect 308382 164898 308414 165134
-rect 307794 129454 308414 164898
-rect 307794 129218 307826 129454
-rect 308062 129218 308146 129454
-rect 308382 129218 308414 129454
-rect 307794 129134 308414 129218
-rect 307794 128898 307826 129134
-rect 308062 128898 308146 129134
-rect 308382 128898 308414 129134
-rect 307794 93454 308414 128898
-rect 307794 93218 307826 93454
-rect 308062 93218 308146 93454
-rect 308382 93218 308414 93454
-rect 307794 93134 308414 93218
-rect 307794 92898 307826 93134
-rect 308062 92898 308146 93134
-rect 308382 92898 308414 93134
-rect 307794 57454 308414 92898
-rect 307794 57218 307826 57454
-rect 308062 57218 308146 57454
-rect 308382 57218 308414 57454
-rect 307794 57134 308414 57218
-rect 307794 56898 307826 57134
-rect 308062 56898 308146 57134
-rect 308382 56898 308414 57134
-rect 307794 21454 308414 56898
-rect 307794 21218 307826 21454
-rect 308062 21218 308146 21454
-rect 308382 21218 308414 21454
-rect 307794 21134 308414 21218
-rect 307794 20898 307826 21134
-rect 308062 20898 308146 21134
-rect 308382 20898 308414 21134
-rect 307794 -1306 308414 20898
-rect 307794 -1542 307826 -1306
-rect 308062 -1542 308146 -1306
-rect 308382 -1542 308414 -1306
-rect 307794 -1626 308414 -1542
-rect 307794 -1862 307826 -1626
-rect 308062 -1862 308146 -1626
-rect 308382 -1862 308414 -1626
-rect 307794 -1894 308414 -1862
-rect 311514 313174 312134 336000
-rect 311514 312938 311546 313174
-rect 311782 312938 311866 313174
-rect 312102 312938 312134 313174
-rect 311514 312854 312134 312938
-rect 311514 312618 311546 312854
-rect 311782 312618 311866 312854
-rect 312102 312618 312134 312854
-rect 311514 277174 312134 312618
-rect 311514 276938 311546 277174
-rect 311782 276938 311866 277174
-rect 312102 276938 312134 277174
-rect 311514 276854 312134 276938
-rect 311514 276618 311546 276854
-rect 311782 276618 311866 276854
-rect 312102 276618 312134 276854
-rect 311514 241174 312134 276618
-rect 311514 240938 311546 241174
-rect 311782 240938 311866 241174
-rect 312102 240938 312134 241174
-rect 311514 240854 312134 240938
-rect 311514 240618 311546 240854
-rect 311782 240618 311866 240854
-rect 312102 240618 312134 240854
-rect 311514 205174 312134 240618
-rect 311514 204938 311546 205174
-rect 311782 204938 311866 205174
-rect 312102 204938 312134 205174
-rect 311514 204854 312134 204938
-rect 311514 204618 311546 204854
-rect 311782 204618 311866 204854
-rect 312102 204618 312134 204854
-rect 311514 169174 312134 204618
-rect 311514 168938 311546 169174
-rect 311782 168938 311866 169174
-rect 312102 168938 312134 169174
-rect 311514 168854 312134 168938
-rect 311514 168618 311546 168854
-rect 311782 168618 311866 168854
-rect 312102 168618 312134 168854
-rect 311514 133174 312134 168618
-rect 311514 132938 311546 133174
-rect 311782 132938 311866 133174
-rect 312102 132938 312134 133174
-rect 311514 132854 312134 132938
-rect 311514 132618 311546 132854
-rect 311782 132618 311866 132854
-rect 312102 132618 312134 132854
-rect 311514 97174 312134 132618
-rect 311514 96938 311546 97174
-rect 311782 96938 311866 97174
-rect 312102 96938 312134 97174
-rect 311514 96854 312134 96938
-rect 311514 96618 311546 96854
-rect 311782 96618 311866 96854
-rect 312102 96618 312134 96854
-rect 311514 61174 312134 96618
-rect 311514 60938 311546 61174
-rect 311782 60938 311866 61174
-rect 312102 60938 312134 61174
-rect 311514 60854 312134 60938
-rect 311514 60618 311546 60854
-rect 311782 60618 311866 60854
-rect 312102 60618 312134 60854
-rect 311514 25174 312134 60618
-rect 311514 24938 311546 25174
-rect 311782 24938 311866 25174
-rect 312102 24938 312134 25174
-rect 311514 24854 312134 24938
-rect 311514 24618 311546 24854
-rect 311782 24618 311866 24854
-rect 312102 24618 312134 24854
-rect 311514 -3226 312134 24618
-rect 311514 -3462 311546 -3226
-rect 311782 -3462 311866 -3226
-rect 312102 -3462 312134 -3226
-rect 311514 -3546 312134 -3462
-rect 311514 -3782 311546 -3546
-rect 311782 -3782 311866 -3546
-rect 312102 -3782 312134 -3546
-rect 311514 -3814 312134 -3782
-rect 315234 316894 315854 336000
-rect 315234 316658 315266 316894
-rect 315502 316658 315586 316894
-rect 315822 316658 315854 316894
-rect 315234 316574 315854 316658
-rect 315234 316338 315266 316574
-rect 315502 316338 315586 316574
-rect 315822 316338 315854 316574
-rect 315234 280894 315854 316338
-rect 315234 280658 315266 280894
-rect 315502 280658 315586 280894
-rect 315822 280658 315854 280894
-rect 315234 280574 315854 280658
-rect 315234 280338 315266 280574
-rect 315502 280338 315586 280574
-rect 315822 280338 315854 280574
-rect 315234 244894 315854 280338
-rect 315234 244658 315266 244894
-rect 315502 244658 315586 244894
-rect 315822 244658 315854 244894
-rect 315234 244574 315854 244658
-rect 315234 244338 315266 244574
-rect 315502 244338 315586 244574
-rect 315822 244338 315854 244574
-rect 315234 208894 315854 244338
-rect 315234 208658 315266 208894
-rect 315502 208658 315586 208894
-rect 315822 208658 315854 208894
-rect 315234 208574 315854 208658
-rect 315234 208338 315266 208574
-rect 315502 208338 315586 208574
-rect 315822 208338 315854 208574
-rect 315234 172894 315854 208338
-rect 315234 172658 315266 172894
-rect 315502 172658 315586 172894
-rect 315822 172658 315854 172894
-rect 315234 172574 315854 172658
-rect 315234 172338 315266 172574
-rect 315502 172338 315586 172574
-rect 315822 172338 315854 172574
-rect 315234 136894 315854 172338
-rect 315234 136658 315266 136894
-rect 315502 136658 315586 136894
-rect 315822 136658 315854 136894
-rect 315234 136574 315854 136658
-rect 315234 136338 315266 136574
-rect 315502 136338 315586 136574
-rect 315822 136338 315854 136574
-rect 315234 100894 315854 136338
-rect 315234 100658 315266 100894
-rect 315502 100658 315586 100894
-rect 315822 100658 315854 100894
-rect 315234 100574 315854 100658
-rect 315234 100338 315266 100574
-rect 315502 100338 315586 100574
-rect 315822 100338 315854 100574
-rect 315234 64894 315854 100338
-rect 315234 64658 315266 64894
-rect 315502 64658 315586 64894
-rect 315822 64658 315854 64894
-rect 315234 64574 315854 64658
-rect 315234 64338 315266 64574
-rect 315502 64338 315586 64574
-rect 315822 64338 315854 64574
-rect 315234 28894 315854 64338
-rect 315234 28658 315266 28894
-rect 315502 28658 315586 28894
-rect 315822 28658 315854 28894
-rect 315234 28574 315854 28658
-rect 315234 28338 315266 28574
-rect 315502 28338 315586 28574
-rect 315822 28338 315854 28574
-rect 315234 -5146 315854 28338
-rect 315234 -5382 315266 -5146
-rect 315502 -5382 315586 -5146
-rect 315822 -5382 315854 -5146
-rect 315234 -5466 315854 -5382
-rect 315234 -5702 315266 -5466
-rect 315502 -5702 315586 -5466
-rect 315822 -5702 315854 -5466
-rect 315234 -5734 315854 -5702
-rect 318954 320614 319574 336000
-rect 318954 320378 318986 320614
-rect 319222 320378 319306 320614
-rect 319542 320378 319574 320614
-rect 318954 320294 319574 320378
-rect 318954 320058 318986 320294
-rect 319222 320058 319306 320294
-rect 319542 320058 319574 320294
-rect 318954 284614 319574 320058
-rect 318954 284378 318986 284614
-rect 319222 284378 319306 284614
-rect 319542 284378 319574 284614
-rect 318954 284294 319574 284378
-rect 318954 284058 318986 284294
-rect 319222 284058 319306 284294
-rect 319542 284058 319574 284294
-rect 318954 248614 319574 284058
-rect 318954 248378 318986 248614
-rect 319222 248378 319306 248614
-rect 319542 248378 319574 248614
-rect 318954 248294 319574 248378
-rect 318954 248058 318986 248294
-rect 319222 248058 319306 248294
-rect 319542 248058 319574 248294
-rect 318954 212614 319574 248058
-rect 318954 212378 318986 212614
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-rect 300954 -6342 300986 -6106
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-rect 325794 -346 326414 2898
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-rect 325794 -666 326414 -582
-rect 325794 -902 325826 -666
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-rect 329514 -2586 330134 -2502
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-rect 333234 -4506 333854 -4422
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-rect 336954 302614 337574 336000
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-rect 318954 -7302 318986 -7066
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-rect 318954 -7386 319574 -7302
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-rect 319222 -7622 319306 -7386
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-rect 318954 -7654 319574 -7622
-rect 336954 -6106 337574 14058
-rect 343794 309454 344414 338000
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-rect 347514 313174 348134 336000
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-rect 348102 -3462 348134 -3226
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-rect 348102 -3782 348134 -3546
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-rect 351234 316894 351854 336000
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-rect 369234 334894 369854 336000
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-rect 372954 302614 373574 336000
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-rect 379794 309454 380414 338000
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-rect 383514 313174 384134 336000
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-rect 390954 -7302 390986 -7066
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-rect 411302 6901 411362 457267
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-rect 415794 -1306 416414 20898
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-rect 419514 673174 420134 707162
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-rect 423234 676894 423854 709082
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-rect 426954 356378 426986 356614
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-rect 459502 316658 459586 316894
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-rect 459234 316574 459854 316658
-rect 459234 316338 459266 316574
-rect 459502 316338 459586 316574
-rect 459822 316338 459854 316574
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-rect 459234 280658 459266 280894
-rect 459502 280658 459586 280894
-rect 459822 280658 459854 280894
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-rect 459234 280338 459266 280574
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-rect 459822 280338 459854 280574
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-rect 459822 244658 459854 244894
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-rect 459822 244338 459854 244574
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-rect 459502 208658 459586 208894
-rect 459822 208658 459854 208894
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-rect 459234 208338 459266 208574
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-rect 459502 172658 459586 172894
-rect 459822 172658 459854 172894
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-rect 459822 172338 459854 172574
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-rect 459234 136658 459266 136894
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-rect 459822 136658 459854 136894
-rect 459234 136574 459854 136658
-rect 459234 136338 459266 136574
-rect 459502 136338 459586 136574
-rect 459822 136338 459854 136574
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-rect 459234 100658 459266 100894
-rect 459502 100658 459586 100894
-rect 459822 100658 459854 100894
-rect 459234 100574 459854 100658
-rect 459234 100338 459266 100574
-rect 459502 100338 459586 100574
-rect 459822 100338 459854 100574
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-rect 459822 64658 459854 64894
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-rect 459234 64338 459266 64574
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-rect 459822 64338 459854 64574
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-rect 459822 28658 459854 28894
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-rect 459234 28338 459266 28574
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-rect 459822 28338 459854 28574
-rect 459234 -5146 459854 28338
-rect 459234 -5382 459266 -5146
-rect 459502 -5382 459586 -5146
-rect 459822 -5382 459854 -5146
-rect 459234 -5466 459854 -5382
-rect 459234 -5702 459266 -5466
-rect 459502 -5702 459586 -5466
-rect 459822 -5702 459854 -5466
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-rect 462954 680614 463574 711002
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-rect 473514 706758 474134 707750
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-rect 462954 680378 462986 680614
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-rect 462954 320614 463574 356058
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-rect 462954 68614 463574 104058
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-rect 462954 32614 463574 68058
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-rect 444954 -6342 444986 -6106
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-rect 462954 -7066 463574 32058
-rect 469794 704838 470414 705830
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-rect 469794 -346 470414 2898
-rect 469794 -582 469826 -346
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-rect 470382 -582 470414 -346
-rect 469794 -666 470414 -582
-rect 469794 -902 469826 -666
-rect 470062 -902 470146 -666
-rect 470382 -902 470414 -666
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-rect 473514 691174 474134 706202
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-rect 473782 330938 473866 331174
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-rect 473782 294938 473866 295174
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-rect 473514 114938 473546 115174
-rect 473782 114938 473866 115174
-rect 474102 114938 474134 115174
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-rect 549822 226338 549854 226574
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-rect 549234 -4186 549854 10338
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-rect 549502 -4422 549586 -4186
-rect 549822 -4422 549854 -4186
-rect 549234 -4506 549854 -4422
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-rect 549502 -4742 549586 -4506
-rect 549822 -4742 549854 -4506
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-rect 552954 698614 553574 710042
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-rect 534954 -7302 534986 -7066
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-rect 590378 100658 590462 100894
-rect 590698 100658 590730 100894
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-<< via4 >>
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-rect -1974 704602 -1738 704838
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-rect 1826 147218 2062 147454
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-rect 1826 111218 2062 111454
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-rect 1826 75218 2062 75454
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-rect 1826 39218 2062 39454
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-rect 1826 38898 2062 39134
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-rect 1826 3218 2062 3454
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-rect 1826 2898 2062 3134
-rect 2146 2898 2382 3134
-rect 1826 -582 2062 -346
-rect 2146 -582 2382 -346
-rect 1826 -902 2062 -666
-rect 2146 -902 2382 -666
-rect -2934 -1542 -2698 -1306
-rect -2614 -1542 -2378 -1306
-rect -2934 -1862 -2698 -1626
-rect -2614 -1862 -2378 -1626
-rect 5546 690938 5782 691174
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-rect 5546 690618 5782 690854
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-rect 5546 618618 5782 618854
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-rect 5546 294618 5782 294854
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-rect 5546 258618 5782 258854
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-rect 5546 222938 5782 223174
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-rect 5546 150938 5782 151174
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-rect 5546 78938 5782 79174
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-rect -3894 -2502 -3658 -2266
-rect -3574 -2502 -3338 -2266
-rect -3894 -2822 -3658 -2586
-rect -3574 -2822 -3338 -2586
-rect 5546 -2502 5782 -2266
-rect 5866 -2502 6102 -2266
-rect 5546 -2822 5782 -2586
-rect 5866 -2822 6102 -2586
-rect -4854 -3462 -4618 -3226
-rect -4534 -3462 -4298 -3226
-rect -4854 -3782 -4618 -3546
-rect -4534 -3782 -4298 -3546
-rect 9266 694658 9502 694894
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-rect 9266 658658 9502 658894
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-rect 9266 622658 9502 622894
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-rect 9266 622338 9502 622574
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-rect 9266 442658 9502 442894
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-rect 9266 298658 9502 298894
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-rect 9266 262658 9502 262894
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-rect 9266 190338 9502 190574
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-rect 9266 154658 9502 154894
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-rect 9266 82658 9502 82894
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-rect 9266 46658 9502 46894
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-rect -5814 -4422 -5578 -4186
-rect -5494 -4422 -5258 -4186
-rect -5814 -4742 -5578 -4506
-rect -5494 -4742 -5258 -4506
-rect 9266 -4422 9502 -4186
-rect 9586 -4422 9822 -4186
-rect 9266 -4742 9502 -4506
-rect 9586 -4742 9822 -4506
-rect -6774 -5382 -6538 -5146
-rect -6454 -5382 -6218 -5146
-rect -6774 -5702 -6538 -5466
-rect -6454 -5702 -6218 -5466
-rect 30986 711322 31222 711558
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-rect 30986 711002 31222 711238
-rect 31306 711002 31542 711238
-rect 27266 709402 27502 709638
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-rect 27266 709082 27502 709318
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-rect 23546 707482 23782 707718
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-rect 23546 707162 23782 707398
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-rect 12986 698378 13222 698614
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-rect 12986 698058 13222 698294
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-rect 12986 662378 13222 662614
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-rect 12986 662058 13222 662294
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-rect 12986 626378 13222 626614
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-rect 12986 626058 13222 626294
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-rect 12986 590378 13222 590614
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-rect 12986 590058 13222 590294
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-rect 12986 554378 13222 554614
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-rect 12986 518378 13222 518614
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-rect 12986 518058 13222 518294
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-rect 12986 482378 13222 482614
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-rect 12986 482058 13222 482294
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-rect 12986 446378 13222 446614
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-rect 12986 410378 13222 410614
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-rect 12986 374378 13222 374614
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-rect 12986 338378 13222 338614
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-rect 12986 338058 13222 338294
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-rect 12986 302378 13222 302614
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-rect 12986 302058 13222 302294
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-rect 12986 266378 13222 266614
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-rect 12986 266058 13222 266294
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-rect 12986 230378 13222 230614
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-rect 12986 194378 13222 194614
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-rect 12986 194058 13222 194294
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-rect 12986 158378 13222 158614
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-rect 12986 122378 13222 122614
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-rect 12986 122058 13222 122294
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-rect 12986 86378 13222 86614
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-rect 12986 86058 13222 86294
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-rect 12986 50378 13222 50614
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-rect 12986 50058 13222 50294
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-rect 12986 14378 13222 14614
-rect 13306 14378 13542 14614
-rect 12986 14058 13222 14294
-rect 13306 14058 13542 14294
-rect -7734 -6342 -7498 -6106
-rect -7414 -6342 -7178 -6106
-rect -7734 -6662 -7498 -6426
-rect -7414 -6662 -7178 -6426
-rect 19826 705562 20062 705798
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-rect 19826 705242 20062 705478
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-rect 19826 669218 20062 669454
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-rect 19826 668898 20062 669134
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-rect 19826 633218 20062 633454
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-rect 19826 597218 20062 597454
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-rect 19826 561218 20062 561454
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-rect 19826 560898 20062 561134
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-rect 19826 525218 20062 525454
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-rect 19826 489218 20062 489454
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-rect 19826 453218 20062 453454
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-rect 19826 417218 20062 417454
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-rect 19826 381218 20062 381454
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-rect 19826 273218 20062 273454
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-rect 19826 -1542 20062 -1306
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-rect 19826 -1862 20062 -1626
-rect 20146 -1862 20382 -1626
-rect 23546 672938 23782 673174
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-rect 23546 384938 23782 385174
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-rect 23546 312938 23782 313174
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-rect 23546 240938 23782 241174
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-rect 23546 -3462 23782 -3226
-rect 23866 -3462 24102 -3226
-rect 23546 -3782 23782 -3546
-rect 23866 -3782 24102 -3546
-rect 27266 676658 27502 676894
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-rect 27266 640658 27502 640894
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-rect 27266 568658 27502 568894
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-rect 27266 352658 27502 352894
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-rect 27266 316658 27502 316894
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-rect 27266 316338 27502 316574
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-rect 27266 280338 27502 280574
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-rect 27266 208658 27502 208894
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-rect 27266 208338 27502 208574
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-rect 27266 172658 27502 172894
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-rect 27266 172338 27502 172574
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-rect 27266 136658 27502 136894
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-rect 27266 136338 27502 136574
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-rect 27266 100658 27502 100894
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-rect 27266 64658 27502 64894
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-rect 27266 64338 27502 64574
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-rect 27266 28658 27502 28894
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-rect 27266 28338 27502 28574
-rect 27586 28338 27822 28574
-rect 27266 -5382 27502 -5146
-rect 27586 -5382 27822 -5146
-rect 27266 -5702 27502 -5466
-rect 27586 -5702 27822 -5466
-rect 48986 710362 49222 710598
-rect 49306 710362 49542 710598
-rect 48986 710042 49222 710278
-rect 49306 710042 49542 710278
-rect 45266 708442 45502 708678
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-rect 45266 708122 45502 708358
-rect 45586 708122 45822 708358
-rect 41546 706522 41782 706758
-rect 41866 706522 42102 706758
-rect 41546 706202 41782 706438
-rect 41866 706202 42102 706438
-rect 30986 680378 31222 680614
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-rect 30986 680058 31222 680294
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-rect 30986 644378 31222 644614
-rect 31306 644378 31542 644614
-rect 30986 644058 31222 644294
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-rect 30986 608378 31222 608614
-rect 31306 608378 31542 608614
-rect 30986 608058 31222 608294
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-rect 30986 572378 31222 572614
-rect 31306 572378 31542 572614
-rect 30986 572058 31222 572294
-rect 31306 572058 31542 572294
-rect 30986 536378 31222 536614
-rect 31306 536378 31542 536614
-rect 30986 536058 31222 536294
-rect 31306 536058 31542 536294
-rect 30986 500378 31222 500614
-rect 31306 500378 31542 500614
-rect 30986 500058 31222 500294
-rect 31306 500058 31542 500294
-rect 30986 464378 31222 464614
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-rect 30986 464058 31222 464294
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-rect 30986 428378 31222 428614
-rect 31306 428378 31542 428614
-rect 30986 428058 31222 428294
-rect 31306 428058 31542 428294
-rect 30986 392378 31222 392614
-rect 31306 392378 31542 392614
-rect 30986 392058 31222 392294
-rect 31306 392058 31542 392294
-rect 30986 356378 31222 356614
-rect 31306 356378 31542 356614
-rect 30986 356058 31222 356294
-rect 31306 356058 31542 356294
-rect 30986 320378 31222 320614
-rect 31306 320378 31542 320614
-rect 30986 320058 31222 320294
-rect 31306 320058 31542 320294
-rect 30986 284378 31222 284614
-rect 31306 284378 31542 284614
-rect 30986 284058 31222 284294
-rect 31306 284058 31542 284294
-rect 30986 248378 31222 248614
-rect 31306 248378 31542 248614
-rect 30986 248058 31222 248294
-rect 31306 248058 31542 248294
-rect 30986 212378 31222 212614
-rect 31306 212378 31542 212614
-rect 30986 212058 31222 212294
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-rect 102986 -7302 103222 -7066
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-rect 127826 705562 128062 705798
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-rect 207266 -5382 207502 -5146
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-rect 228986 710362 229222 710598
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-rect 192986 -6342 193222 -6106
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-rect 217826 704602 218062 704838
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-rect 279266 640658 279502 640894
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-rect 279266 604338 279502 604574
-rect 279586 604338 279822 604574
-rect 279266 568658 279502 568894
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-rect 279266 532658 279502 532894
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-rect 279266 496658 279502 496894
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-rect 279266 460658 279502 460894
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-rect 300986 710362 301222 710598
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-rect 297266 708442 297502 708678
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-rect 297266 708122 297502 708358
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-rect 293546 706522 293782 706758
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-rect 282986 680378 283222 680614
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-rect 282986 680058 283222 680294
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-rect 282986 644378 283222 644614
-rect 283306 644378 283542 644614
-rect 282986 644058 283222 644294
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-rect 282986 608058 283222 608294
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-rect 282986 572378 283222 572614
-rect 283306 572378 283542 572614
-rect 282986 572058 283222 572294
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-rect 282986 536378 283222 536614
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-rect 282986 536058 283222 536294
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-rect 282986 464058 283222 464294
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-rect 289826 687218 290062 687454
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-rect 289826 686898 290062 687134
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-rect 289826 651218 290062 651454
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-rect 289826 615218 290062 615454
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-rect 289826 543218 290062 543454
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-rect 293546 690938 293782 691174
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-rect 293546 690618 293782 690854
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-rect 297266 694658 297502 694894
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-rect 297266 622658 297502 622894
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-rect 297266 586658 297502 586894
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-rect 297266 550338 297502 550574
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-rect 318986 711322 319222 711558
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-rect 315266 709402 315502 709638
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-rect 307826 705562 308062 705798
-rect 308146 705562 308382 705798
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-rect 307826 669218 308062 669454
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-rect 307826 668898 308062 669134
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-rect 307826 633218 308062 633454
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-rect 307826 632898 308062 633134
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-rect 307826 597218 308062 597454
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-rect 307826 596898 308062 597134
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-rect 307826 561218 308062 561454
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-rect 307826 560898 308062 561134
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-rect 307826 525218 308062 525454
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-rect 311546 672938 311782 673174
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-rect 311546 636938 311782 637174
-rect 311866 636938 312102 637174
-rect 311546 636618 311782 636854
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-rect 311866 564938 312102 565174
-rect 311546 564618 311782 564854
-rect 311866 564618 312102 564854
-rect 311546 528938 311782 529174
-rect 311866 528938 312102 529174
-rect 311546 528618 311782 528854
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-rect 311546 492938 311782 493174
-rect 311866 492938 312102 493174
-rect 311546 492618 311782 492854
-rect 311866 492618 312102 492854
-rect 315266 676658 315502 676894
-rect 315586 676658 315822 676894
-rect 315266 676338 315502 676574
-rect 315586 676338 315822 676574
-rect 315266 640658 315502 640894
-rect 315586 640658 315822 640894
-rect 315266 640338 315502 640574
-rect 315586 640338 315822 640574
-rect 315266 604658 315502 604894
-rect 315586 604658 315822 604894
-rect 315266 604338 315502 604574
-rect 315586 604338 315822 604574
-rect 315266 568658 315502 568894
-rect 315586 568658 315822 568894
-rect 315266 568338 315502 568574
-rect 315586 568338 315822 568574
-rect 315266 532658 315502 532894
-rect 315586 532658 315822 532894
-rect 315266 532338 315502 532574
-rect 315586 532338 315822 532574
-rect 315266 496658 315502 496894
-rect 315586 496658 315822 496894
-rect 315266 496338 315502 496574
-rect 315586 496338 315822 496574
-rect 315266 460658 315502 460894
-rect 315586 460658 315822 460894
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-rect 315586 460338 315822 460574
-rect 336986 710362 337222 710598
-rect 337306 710362 337542 710598
-rect 336986 710042 337222 710278
-rect 337306 710042 337542 710278
-rect 333266 708442 333502 708678
-rect 333586 708442 333822 708678
-rect 333266 708122 333502 708358
-rect 333586 708122 333822 708358
-rect 329546 706522 329782 706758
-rect 329866 706522 330102 706758
-rect 329546 706202 329782 706438
-rect 329866 706202 330102 706438
-rect 318986 680378 319222 680614
-rect 319306 680378 319542 680614
-rect 318986 680058 319222 680294
-rect 319306 680058 319542 680294
-rect 318986 644378 319222 644614
-rect 319306 644378 319542 644614
-rect 318986 644058 319222 644294
-rect 319306 644058 319542 644294
-rect 318986 608378 319222 608614
-rect 319306 608378 319542 608614
-rect 318986 608058 319222 608294
-rect 319306 608058 319542 608294
-rect 318986 572378 319222 572614
-rect 319306 572378 319542 572614
-rect 318986 572058 319222 572294
-rect 319306 572058 319542 572294
-rect 318986 536378 319222 536614
-rect 319306 536378 319542 536614
-rect 318986 536058 319222 536294
-rect 319306 536058 319542 536294
-rect 318986 500378 319222 500614
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-rect 318986 500058 319222 500294
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-rect 318986 464378 319222 464614
-rect 319306 464378 319542 464614
-rect 318986 464058 319222 464294
-rect 319306 464058 319542 464294
-rect 325826 704602 326062 704838
-rect 326146 704602 326382 704838
-rect 325826 704282 326062 704518
-rect 326146 704282 326382 704518
-rect 325826 687218 326062 687454
-rect 326146 687218 326382 687454
-rect 325826 686898 326062 687134
-rect 326146 686898 326382 687134
-rect 325826 651218 326062 651454
-rect 326146 651218 326382 651454
-rect 325826 650898 326062 651134
-rect 326146 650898 326382 651134
-rect 325826 615218 326062 615454
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-rect 325826 543218 326062 543454
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-rect 325826 542898 326062 543134
-rect 326146 542898 326382 543134
-rect 325826 507218 326062 507454
-rect 326146 507218 326382 507454
-rect 325826 506898 326062 507134
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-rect 325826 471218 326062 471454
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-rect 329546 690938 329782 691174
-rect 329866 690938 330102 691174
-rect 329546 690618 329782 690854
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-rect 329546 654938 329782 655174
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-rect 329546 618938 329782 619174
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-rect 333266 694658 333502 694894
-rect 333586 694658 333822 694894
-rect 333266 694338 333502 694574
-rect 333586 694338 333822 694574
-rect 333266 658658 333502 658894
-rect 333586 658658 333822 658894
-rect 333266 658338 333502 658574
-rect 333586 658338 333822 658574
-rect 333266 622658 333502 622894
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-rect 333266 622338 333502 622574
-rect 333586 622338 333822 622574
-rect 333266 586658 333502 586894
-rect 333586 586658 333822 586894
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-rect 333266 550658 333502 550894
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-rect 333266 514338 333502 514574
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-rect 333266 478658 333502 478894
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-rect 333266 478338 333502 478574
-rect 333586 478338 333822 478574
-rect 354986 711322 355222 711558
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-rect 351266 709402 351502 709638
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-rect 351266 709082 351502 709318
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-rect 347546 707482 347782 707718
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-rect 347546 707162 347782 707398
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-rect 336986 698378 337222 698614
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-rect 336986 698058 337222 698294
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-rect 336986 662378 337222 662614
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-rect 336986 662058 337222 662294
-rect 337306 662058 337542 662294
-rect 336986 626378 337222 626614
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-rect 336986 626058 337222 626294
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-rect 336986 518058 337222 518294
-rect 337306 518058 337542 518294
-rect 336986 482378 337222 482614
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-rect 336986 482058 337222 482294
-rect 337306 482058 337542 482294
-rect 343826 705562 344062 705798
-rect 344146 705562 344382 705798
-rect 343826 705242 344062 705478
-rect 344146 705242 344382 705478
-rect 343826 669218 344062 669454
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-rect 343826 633218 344062 633454
-rect 344146 633218 344382 633454
-rect 343826 632898 344062 633134
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-rect 344146 597218 344382 597454
-rect 343826 596898 344062 597134
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-rect 343826 561218 344062 561454
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-rect 343826 560898 344062 561134
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-rect 343826 525218 344062 525454
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-rect 347546 672938 347782 673174
-rect 347866 672938 348102 673174
-rect 347546 672618 347782 672854
-rect 347866 672618 348102 672854
-rect 347546 636938 347782 637174
-rect 347866 636938 348102 637174
-rect 347546 636618 347782 636854
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-rect 347866 564938 348102 565174
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-rect 347546 528938 347782 529174
-rect 347866 528938 348102 529174
-rect 347546 528618 347782 528854
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-rect 347546 492938 347782 493174
-rect 347866 492938 348102 493174
-rect 347546 492618 347782 492854
-rect 347866 492618 348102 492854
-rect 351266 676658 351502 676894
-rect 351586 676658 351822 676894
-rect 351266 676338 351502 676574
-rect 351586 676338 351822 676574
-rect 351266 640658 351502 640894
-rect 351586 640658 351822 640894
-rect 351266 640338 351502 640574
-rect 351586 640338 351822 640574
-rect 351266 604658 351502 604894
-rect 351586 604658 351822 604894
-rect 351266 604338 351502 604574
-rect 351586 604338 351822 604574
-rect 351266 568658 351502 568894
-rect 351586 568658 351822 568894
-rect 351266 568338 351502 568574
-rect 351586 568338 351822 568574
-rect 351266 532658 351502 532894
-rect 351586 532658 351822 532894
-rect 351266 532338 351502 532574
-rect 351586 532338 351822 532574
-rect 351266 496658 351502 496894
-rect 351586 496658 351822 496894
-rect 351266 496338 351502 496574
-rect 351586 496338 351822 496574
-rect 351266 460658 351502 460894
-rect 351586 460658 351822 460894
-rect 351266 460338 351502 460574
-rect 351586 460338 351822 460574
-rect 372986 710362 373222 710598
-rect 373306 710362 373542 710598
-rect 372986 710042 373222 710278
-rect 373306 710042 373542 710278
-rect 369266 708442 369502 708678
-rect 369586 708442 369822 708678
-rect 369266 708122 369502 708358
-rect 369586 708122 369822 708358
-rect 365546 706522 365782 706758
-rect 365866 706522 366102 706758
-rect 365546 706202 365782 706438
-rect 365866 706202 366102 706438
-rect 354986 680378 355222 680614
-rect 355306 680378 355542 680614
-rect 354986 680058 355222 680294
-rect 355306 680058 355542 680294
-rect 354986 644378 355222 644614
-rect 355306 644378 355542 644614
-rect 354986 644058 355222 644294
-rect 355306 644058 355542 644294
-rect 354986 608378 355222 608614
-rect 355306 608378 355542 608614
-rect 354986 608058 355222 608294
-rect 355306 608058 355542 608294
-rect 354986 572378 355222 572614
-rect 355306 572378 355542 572614
-rect 354986 572058 355222 572294
-rect 355306 572058 355542 572294
-rect 354986 536378 355222 536614
-rect 355306 536378 355542 536614
-rect 354986 536058 355222 536294
-rect 355306 536058 355542 536294
-rect 354986 500378 355222 500614
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-rect 354986 500058 355222 500294
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-rect 354986 464378 355222 464614
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-rect 354986 464058 355222 464294
-rect 355306 464058 355542 464294
-rect 361826 704602 362062 704838
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-rect 361826 704282 362062 704518
-rect 362146 704282 362382 704518
-rect 361826 687218 362062 687454
-rect 362146 687218 362382 687454
-rect 361826 686898 362062 687134
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-rect 239546 -3462 239782 -3226
-rect 239866 -3462 240102 -3226
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-rect 243266 -5382 243502 -5146
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-rect 243266 -5702 243502 -5466
-rect 243586 -5702 243822 -5466
-rect 246986 32378 247222 32614
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-rect 228986 -6342 229222 -6106
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-rect 253826 75218 254062 75454
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-rect 253826 2898 254062 3134
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-rect 253826 -582 254062 -346
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-rect 253826 -902 254062 -666
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-rect 257546 150938 257782 151174
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-rect 257546 -2822 257782 -2586
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-rect 264986 302378 265222 302614
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-rect 261266 154658 261502 154894
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-rect 261266 10658 261502 10894
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-rect 261266 -4422 261502 -4186
-rect 261586 -4422 261822 -4186
-rect 261266 -4742 261502 -4506
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-rect 264986 194378 265222 194614
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-rect 246986 -7302 247222 -7066
-rect 247306 -7302 247542 -7066
-rect 246986 -7622 247222 -7386
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-rect 271826 237218 272062 237454
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-rect 271826 201218 272062 201454
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-rect 271826 165218 272062 165454
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-rect 271826 129218 272062 129454
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-rect 271826 93218 272062 93454
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-rect 271826 92898 272062 93134
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-rect 271826 57218 272062 57454
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-rect 271826 56898 272062 57134
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-rect 271826 21218 272062 21454
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-rect 271826 -1542 272062 -1306
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-rect 271826 -1862 272062 -1626
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-rect 275546 312938 275782 313174
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-rect 275546 24938 275782 25174
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-rect 275546 -3462 275782 -3226
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-rect 275546 -3782 275782 -3546
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-rect 279266 316658 279502 316894
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-rect 279266 208658 279502 208894
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-rect 279266 172658 279502 172894
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-rect 279266 136658 279502 136894
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-rect 279266 64658 279502 64894
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-rect 279266 28658 279502 28894
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-rect 279266 -5382 279502 -5146
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-rect 279266 -5702 279502 -5466
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-rect 282986 320378 283222 320614
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-rect 282986 68378 283222 68614
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-rect 282986 68058 283222 68294
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-rect 282986 32378 283222 32614
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-rect 282986 32058 283222 32294
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-rect 264986 -6342 265222 -6106
-rect 265306 -6342 265542 -6106
-rect 264986 -6662 265222 -6426
-rect 265306 -6662 265542 -6426
-rect 289826 327218 290062 327454
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-rect 289826 291218 290062 291454
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-rect 289826 255218 290062 255454
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-rect 289826 219218 290062 219454
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-rect 289826 75218 290062 75454
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-rect 289826 39218 290062 39454
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-rect 289826 2898 290062 3134
-rect 290146 2898 290382 3134
-rect 289826 -582 290062 -346
-rect 290146 -582 290382 -346
-rect 289826 -902 290062 -666
-rect 290146 -902 290382 -666
-rect 293546 330938 293782 331174
-rect 293866 330938 294102 331174
-rect 293546 330618 293782 330854
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-rect 293546 294938 293782 295174
-rect 293866 294938 294102 295174
-rect 293546 294618 293782 294854
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-rect 293546 258938 293782 259174
-rect 293866 258938 294102 259174
-rect 293546 258618 293782 258854
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-rect 293546 222938 293782 223174
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-rect 293546 222618 293782 222854
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-rect 293546 186938 293782 187174
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-rect 293546 186618 293782 186854
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-rect 293546 150938 293782 151174
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-rect 293546 150618 293782 150854
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-rect 293546 114938 293782 115174
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-rect 293546 114618 293782 114854
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-rect 293546 78938 293782 79174
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-rect 293546 78618 293782 78854
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-rect 293546 42938 293782 43174
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-rect 293546 42618 293782 42854
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-rect 293546 6938 293782 7174
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-rect 293546 6618 293782 6854
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-rect 293546 -2502 293782 -2266
-rect 293866 -2502 294102 -2266
-rect 293546 -2822 293782 -2586
-rect 293866 -2822 294102 -2586
-rect 297266 334658 297502 334894
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-rect 297266 334338 297502 334574
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-rect 297266 298658 297502 298894
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-rect 297266 262658 297502 262894
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-rect 297266 262338 297502 262574
-rect 297586 262338 297822 262574
-rect 297266 226658 297502 226894
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-rect 297266 190658 297502 190894
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-rect 297266 190338 297502 190574
-rect 297586 190338 297822 190574
-rect 297266 154658 297502 154894
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-rect 297266 154338 297502 154574
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-rect 297266 118658 297502 118894
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-rect 297266 118338 297502 118574
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-rect 297266 82658 297502 82894
-rect 297586 82658 297822 82894
-rect 297266 82338 297502 82574
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-rect 297266 46658 297502 46894
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-rect 297266 10658 297502 10894
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-rect 297266 10338 297502 10574
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-rect 297266 -4422 297502 -4186
-rect 297586 -4422 297822 -4186
-rect 297266 -4742 297502 -4506
-rect 297586 -4742 297822 -4506
-rect 300986 302378 301222 302614
-rect 301306 302378 301542 302614
-rect 300986 302058 301222 302294
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-rect 300986 266378 301222 266614
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-rect 300986 266058 301222 266294
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-rect 300986 230378 301222 230614
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-rect 300986 230058 301222 230294
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-rect 300986 194378 301222 194614
-rect 301306 194378 301542 194614
-rect 300986 194058 301222 194294
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-rect 300986 158378 301222 158614
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-rect 300986 158058 301222 158294
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-rect 300986 122378 301222 122614
-rect 301306 122378 301542 122614
-rect 300986 122058 301222 122294
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-rect 300986 86378 301222 86614
-rect 301306 86378 301542 86614
-rect 300986 86058 301222 86294
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-rect 300986 50378 301222 50614
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-rect 300986 50058 301222 50294
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-rect 300986 14378 301222 14614
-rect 301306 14378 301542 14614
-rect 300986 14058 301222 14294
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-rect 282986 -7302 283222 -7066
-rect 283306 -7302 283542 -7066
-rect 282986 -7622 283222 -7386
-rect 283306 -7622 283542 -7386
-rect 307826 309218 308062 309454
-rect 308146 309218 308382 309454
-rect 307826 308898 308062 309134
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-rect 307826 273218 308062 273454
-rect 308146 273218 308382 273454
-rect 307826 272898 308062 273134
-rect 308146 272898 308382 273134
-rect 307826 237218 308062 237454
-rect 308146 237218 308382 237454
-rect 307826 236898 308062 237134
-rect 308146 236898 308382 237134
-rect 307826 201218 308062 201454
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-rect 307826 200898 308062 201134
-rect 308146 200898 308382 201134
-rect 307826 165218 308062 165454
-rect 308146 165218 308382 165454
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-rect 307826 129218 308062 129454
-rect 308146 129218 308382 129454
-rect 307826 128898 308062 129134
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-rect 307826 93218 308062 93454
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-rect 307826 92898 308062 93134
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-rect 307826 57218 308062 57454
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-rect 307826 56898 308062 57134
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-rect 307826 21218 308062 21454
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-rect 307826 20898 308062 21134
-rect 308146 20898 308382 21134
-rect 307826 -1542 308062 -1306
-rect 308146 -1542 308382 -1306
-rect 307826 -1862 308062 -1626
-rect 308146 -1862 308382 -1626
-rect 311546 312938 311782 313174
-rect 311866 312938 312102 313174
-rect 311546 312618 311782 312854
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-rect 311546 276938 311782 277174
-rect 311866 276938 312102 277174
-rect 311546 276618 311782 276854
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-rect 311546 240938 311782 241174
-rect 311866 240938 312102 241174
-rect 311546 240618 311782 240854
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-rect 311866 204938 312102 205174
-rect 311546 204618 311782 204854
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-rect 311546 168938 311782 169174
-rect 311866 168938 312102 169174
-rect 311546 168618 311782 168854
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-rect 311546 132938 311782 133174
-rect 311866 132938 312102 133174
-rect 311546 132618 311782 132854
-rect 311866 132618 312102 132854
-rect 311546 96938 311782 97174
-rect 311866 96938 312102 97174
-rect 311546 96618 311782 96854
-rect 311866 96618 312102 96854
-rect 311546 60938 311782 61174
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-rect 311546 60618 311782 60854
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-rect 311546 24938 311782 25174
-rect 311866 24938 312102 25174
-rect 311546 24618 311782 24854
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-rect 311546 -3462 311782 -3226
-rect 311866 -3462 312102 -3226
-rect 311546 -3782 311782 -3546
-rect 311866 -3782 312102 -3546
-rect 315266 316658 315502 316894
-rect 315586 316658 315822 316894
-rect 315266 316338 315502 316574
-rect 315586 316338 315822 316574
-rect 315266 280658 315502 280894
-rect 315586 280658 315822 280894
-rect 315266 280338 315502 280574
-rect 315586 280338 315822 280574
-rect 315266 244658 315502 244894
-rect 315586 244658 315822 244894
-rect 315266 244338 315502 244574
-rect 315586 244338 315822 244574
-rect 315266 208658 315502 208894
-rect 315586 208658 315822 208894
-rect 315266 208338 315502 208574
-rect 315586 208338 315822 208574
-rect 315266 172658 315502 172894
-rect 315586 172658 315822 172894
-rect 315266 172338 315502 172574
-rect 315586 172338 315822 172574
-rect 315266 136658 315502 136894
-rect 315586 136658 315822 136894
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-rect 315266 100658 315502 100894
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-rect 315586 100338 315822 100574
-rect 315266 64658 315502 64894
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-rect 315586 64338 315822 64574
-rect 315266 28658 315502 28894
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-rect 315266 28338 315502 28574
-rect 315586 28338 315822 28574
-rect 315266 -5382 315502 -5146
-rect 315586 -5382 315822 -5146
-rect 315266 -5702 315502 -5466
-rect 315586 -5702 315822 -5466
-rect 318986 320378 319222 320614
-rect 319306 320378 319542 320614
-rect 318986 320058 319222 320294
-rect 319306 320058 319542 320294
-rect 318986 284378 319222 284614
-rect 319306 284378 319542 284614
-rect 318986 284058 319222 284294
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-rect 318986 248378 319222 248614
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-rect 318986 212378 319222 212614
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-rect 318986 212058 319222 212294
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-rect 318986 176378 319222 176614
-rect 319306 176378 319542 176614
-rect 318986 176058 319222 176294
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-rect 318986 140378 319222 140614
-rect 319306 140378 319542 140614
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-rect 318986 104378 319222 104614
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-rect 318986 104058 319222 104294
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-rect 318986 68378 319222 68614
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-rect 318986 68058 319222 68294
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-rect 318986 32378 319222 32614
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-rect 318986 32058 319222 32294
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-rect 300986 -6342 301222 -6106
-rect 301306 -6342 301542 -6106
-rect 300986 -6662 301222 -6426
-rect 301306 -6662 301542 -6426
-rect 325826 327218 326062 327454
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-rect 325826 326898 326062 327134
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-rect 325826 291218 326062 291454
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-rect 325826 290898 326062 291134
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-rect 325826 255218 326062 255454
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-rect 325826 254898 326062 255134
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-rect 325826 219218 326062 219454
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-rect 325826 183218 326062 183454
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-rect 325826 182898 326062 183134
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-rect 325826 147218 326062 147454
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-rect 325826 111218 326062 111454
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-rect 325826 75218 326062 75454
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-rect 325826 39218 326062 39454
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-rect 325826 38898 326062 39134
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-rect 325826 3218 326062 3454
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-rect 325826 2898 326062 3134
-rect 326146 2898 326382 3134
-rect 325826 -582 326062 -346
-rect 326146 -582 326382 -346
-rect 325826 -902 326062 -666
-rect 326146 -902 326382 -666
-rect 329546 330938 329782 331174
-rect 329866 330938 330102 331174
-rect 329546 330618 329782 330854
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-rect 329546 294938 329782 295174
-rect 329866 294938 330102 295174
-rect 329546 294618 329782 294854
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-rect 329546 258938 329782 259174
-rect 329866 258938 330102 259174
-rect 329546 258618 329782 258854
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-rect 329546 222938 329782 223174
-rect 329866 222938 330102 223174
-rect 329546 222618 329782 222854
-rect 329866 222618 330102 222854
-rect 329546 186938 329782 187174
-rect 329866 186938 330102 187174
-rect 329546 186618 329782 186854
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-rect 329546 150938 329782 151174
-rect 329866 150938 330102 151174
-rect 329546 150618 329782 150854
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-rect 329546 114938 329782 115174
-rect 329866 114938 330102 115174
-rect 329546 114618 329782 114854
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-rect 329546 78938 329782 79174
-rect 329866 78938 330102 79174
-rect 329546 78618 329782 78854
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-rect 329546 42938 329782 43174
-rect 329866 42938 330102 43174
-rect 329546 42618 329782 42854
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-rect 329546 6938 329782 7174
-rect 329866 6938 330102 7174
-rect 329546 6618 329782 6854
-rect 329866 6618 330102 6854
-rect 329546 -2502 329782 -2266
-rect 329866 -2502 330102 -2266
-rect 329546 -2822 329782 -2586
-rect 329866 -2822 330102 -2586
-rect 333266 334658 333502 334894
-rect 333586 334658 333822 334894
-rect 333266 334338 333502 334574
-rect 333586 334338 333822 334574
-rect 333266 298658 333502 298894
-rect 333586 298658 333822 298894
-rect 333266 298338 333502 298574
-rect 333586 298338 333822 298574
-rect 333266 262658 333502 262894
-rect 333586 262658 333822 262894
-rect 333266 262338 333502 262574
-rect 333586 262338 333822 262574
-rect 333266 226658 333502 226894
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-rect 333266 226338 333502 226574
-rect 333586 226338 333822 226574
-rect 333266 190658 333502 190894
-rect 333586 190658 333822 190894
-rect 333266 190338 333502 190574
-rect 333586 190338 333822 190574
-rect 333266 154658 333502 154894
-rect 333586 154658 333822 154894
-rect 333266 154338 333502 154574
-rect 333586 154338 333822 154574
-rect 333266 118658 333502 118894
-rect 333586 118658 333822 118894
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-rect 333586 118338 333822 118574
-rect 333266 82658 333502 82894
-rect 333586 82658 333822 82894
-rect 333266 82338 333502 82574
-rect 333586 82338 333822 82574
-rect 333266 46658 333502 46894
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-rect 333266 46338 333502 46574
-rect 333586 46338 333822 46574
-rect 333266 10658 333502 10894
-rect 333586 10658 333822 10894
-rect 333266 10338 333502 10574
-rect 333586 10338 333822 10574
-rect 333266 -4422 333502 -4186
-rect 333586 -4422 333822 -4186
-rect 333266 -4742 333502 -4506
-rect 333586 -4742 333822 -4506
-rect 336986 302378 337222 302614
-rect 337306 302378 337542 302614
-rect 336986 302058 337222 302294
-rect 337306 302058 337542 302294
-rect 336986 266378 337222 266614
-rect 337306 266378 337542 266614
-rect 336986 266058 337222 266294
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-rect 336986 230378 337222 230614
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-rect 336986 230058 337222 230294
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-rect 336986 194378 337222 194614
-rect 337306 194378 337542 194614
-rect 336986 194058 337222 194294
-rect 337306 194058 337542 194294
-rect 336986 158378 337222 158614
-rect 337306 158378 337542 158614
-rect 336986 158058 337222 158294
-rect 337306 158058 337542 158294
-rect 336986 122378 337222 122614
-rect 337306 122378 337542 122614
-rect 336986 122058 337222 122294
-rect 337306 122058 337542 122294
-rect 336986 86378 337222 86614
-rect 337306 86378 337542 86614
-rect 336986 86058 337222 86294
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-rect 336986 50378 337222 50614
-rect 337306 50378 337542 50614
-rect 336986 50058 337222 50294
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-rect 336986 14378 337222 14614
-rect 337306 14378 337542 14614
-rect 336986 14058 337222 14294
-rect 337306 14058 337542 14294
-rect 318986 -7302 319222 -7066
-rect 319306 -7302 319542 -7066
-rect 318986 -7622 319222 -7386
-rect 319306 -7622 319542 -7386
-rect 343826 309218 344062 309454
-rect 344146 309218 344382 309454
-rect 343826 308898 344062 309134
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-rect 343826 273218 344062 273454
-rect 344146 273218 344382 273454
-rect 343826 272898 344062 273134
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-rect 343826 237218 344062 237454
-rect 344146 237218 344382 237454
-rect 343826 236898 344062 237134
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-rect 343826 201218 344062 201454
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-rect 343826 200898 344062 201134
-rect 344146 200898 344382 201134
-rect 343826 165218 344062 165454
-rect 344146 165218 344382 165454
-rect 343826 164898 344062 165134
-rect 344146 164898 344382 165134
-rect 343826 129218 344062 129454
-rect 344146 129218 344382 129454
-rect 343826 128898 344062 129134
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-rect 343826 93218 344062 93454
-rect 344146 93218 344382 93454
-rect 343826 92898 344062 93134
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-rect 343826 57218 344062 57454
-rect 344146 57218 344382 57454
-rect 343826 56898 344062 57134
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-rect 343826 21218 344062 21454
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-rect 343826 20898 344062 21134
-rect 344146 20898 344382 21134
-rect 343826 -1542 344062 -1306
-rect 344146 -1542 344382 -1306
-rect 343826 -1862 344062 -1626
-rect 344146 -1862 344382 -1626
-rect 347546 312938 347782 313174
-rect 347866 312938 348102 313174
-rect 347546 312618 347782 312854
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-rect 347546 276938 347782 277174
-rect 347866 276938 348102 277174
-rect 347546 276618 347782 276854
-rect 347866 276618 348102 276854
-rect 347546 240938 347782 241174
-rect 347866 240938 348102 241174
-rect 347546 240618 347782 240854
-rect 347866 240618 348102 240854
-rect 347546 204938 347782 205174
-rect 347866 204938 348102 205174
-rect 347546 204618 347782 204854
-rect 347866 204618 348102 204854
-rect 347546 168938 347782 169174
-rect 347866 168938 348102 169174
-rect 347546 168618 347782 168854
-rect 347866 168618 348102 168854
-rect 347546 132938 347782 133174
-rect 347866 132938 348102 133174
-rect 347546 132618 347782 132854
-rect 347866 132618 348102 132854
-rect 347546 96938 347782 97174
-rect 347866 96938 348102 97174
-rect 347546 96618 347782 96854
-rect 347866 96618 348102 96854
-rect 347546 60938 347782 61174
-rect 347866 60938 348102 61174
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-rect 347546 24938 347782 25174
-rect 347866 24938 348102 25174
-rect 347546 24618 347782 24854
-rect 347866 24618 348102 24854
-rect 347546 -3462 347782 -3226
-rect 347866 -3462 348102 -3226
-rect 347546 -3782 347782 -3546
-rect 347866 -3782 348102 -3546
-rect 351266 316658 351502 316894
-rect 351586 316658 351822 316894
-rect 351266 316338 351502 316574
-rect 351586 316338 351822 316574
-rect 351266 280658 351502 280894
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-rect 351586 280338 351822 280574
-rect 351266 244658 351502 244894
-rect 351586 244658 351822 244894
-rect 351266 244338 351502 244574
-rect 351586 244338 351822 244574
-rect 351266 208658 351502 208894
-rect 351586 208658 351822 208894
-rect 351266 208338 351502 208574
-rect 351586 208338 351822 208574
-rect 351266 172658 351502 172894
-rect 351586 172658 351822 172894
-rect 351266 172338 351502 172574
-rect 351586 172338 351822 172574
-rect 351266 136658 351502 136894
-rect 351586 136658 351822 136894
-rect 351266 136338 351502 136574
-rect 351586 136338 351822 136574
-rect 351266 100658 351502 100894
-rect 351586 100658 351822 100894
-rect 351266 100338 351502 100574
-rect 351586 100338 351822 100574
-rect 351266 64658 351502 64894
-rect 351586 64658 351822 64894
-rect 351266 64338 351502 64574
-rect 351586 64338 351822 64574
-rect 351266 28658 351502 28894
-rect 351586 28658 351822 28894
-rect 351266 28338 351502 28574
-rect 351586 28338 351822 28574
-rect 351266 -5382 351502 -5146
-rect 351586 -5382 351822 -5146
-rect 351266 -5702 351502 -5466
-rect 351586 -5702 351822 -5466
-rect 354986 320378 355222 320614
-rect 355306 320378 355542 320614
-rect 354986 320058 355222 320294
-rect 355306 320058 355542 320294
-rect 354986 284378 355222 284614
-rect 355306 284378 355542 284614
-rect 354986 284058 355222 284294
-rect 355306 284058 355542 284294
-rect 354986 248378 355222 248614
-rect 355306 248378 355542 248614
-rect 354986 248058 355222 248294
-rect 355306 248058 355542 248294
-rect 354986 212378 355222 212614
-rect 355306 212378 355542 212614
-rect 354986 212058 355222 212294
-rect 355306 212058 355542 212294
-rect 354986 176378 355222 176614
-rect 355306 176378 355542 176614
-rect 354986 176058 355222 176294
-rect 355306 176058 355542 176294
-rect 354986 140378 355222 140614
-rect 355306 140378 355542 140614
-rect 354986 140058 355222 140294
-rect 355306 140058 355542 140294
-rect 354986 104378 355222 104614
-rect 355306 104378 355542 104614
-rect 354986 104058 355222 104294
-rect 355306 104058 355542 104294
-rect 354986 68378 355222 68614
-rect 355306 68378 355542 68614
-rect 354986 68058 355222 68294
-rect 355306 68058 355542 68294
-rect 354986 32378 355222 32614
-rect 355306 32378 355542 32614
-rect 354986 32058 355222 32294
-rect 355306 32058 355542 32294
-rect 336986 -6342 337222 -6106
-rect 337306 -6342 337542 -6106
-rect 336986 -6662 337222 -6426
-rect 337306 -6662 337542 -6426
-rect 361826 327218 362062 327454
-rect 362146 327218 362382 327454
-rect 361826 326898 362062 327134
-rect 362146 326898 362382 327134
-rect 361826 291218 362062 291454
-rect 362146 291218 362382 291454
-rect 361826 290898 362062 291134
-rect 362146 290898 362382 291134
-rect 361826 255218 362062 255454
-rect 362146 255218 362382 255454
-rect 361826 254898 362062 255134
-rect 362146 254898 362382 255134
-rect 361826 219218 362062 219454
-rect 362146 219218 362382 219454
-rect 361826 218898 362062 219134
-rect 362146 218898 362382 219134
-rect 361826 183218 362062 183454
-rect 362146 183218 362382 183454
-rect 361826 182898 362062 183134
-rect 362146 182898 362382 183134
-rect 361826 147218 362062 147454
-rect 362146 147218 362382 147454
-rect 361826 146898 362062 147134
-rect 362146 146898 362382 147134
-rect 361826 111218 362062 111454
-rect 362146 111218 362382 111454
-rect 361826 110898 362062 111134
-rect 362146 110898 362382 111134
-rect 361826 75218 362062 75454
-rect 362146 75218 362382 75454
-rect 361826 74898 362062 75134
-rect 362146 74898 362382 75134
-rect 361826 39218 362062 39454
-rect 362146 39218 362382 39454
-rect 361826 38898 362062 39134
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-rect 361826 3218 362062 3454
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-rect 361826 2898 362062 3134
-rect 362146 2898 362382 3134
-rect 361826 -582 362062 -346
-rect 362146 -582 362382 -346
-rect 361826 -902 362062 -666
-rect 362146 -902 362382 -666
-rect 365546 330938 365782 331174
-rect 365866 330938 366102 331174
-rect 365546 330618 365782 330854
-rect 365866 330618 366102 330854
-rect 365546 294938 365782 295174
-rect 365866 294938 366102 295174
-rect 365546 294618 365782 294854
-rect 365866 294618 366102 294854
-rect 365546 258938 365782 259174
-rect 365866 258938 366102 259174
-rect 365546 258618 365782 258854
-rect 365866 258618 366102 258854
-rect 365546 222938 365782 223174
-rect 365866 222938 366102 223174
-rect 365546 222618 365782 222854
-rect 365866 222618 366102 222854
-rect 365546 186938 365782 187174
-rect 365866 186938 366102 187174
-rect 365546 186618 365782 186854
-rect 365866 186618 366102 186854
-rect 365546 150938 365782 151174
-rect 365866 150938 366102 151174
-rect 365546 150618 365782 150854
-rect 365866 150618 366102 150854
-rect 365546 114938 365782 115174
-rect 365866 114938 366102 115174
-rect 365546 114618 365782 114854
-rect 365866 114618 366102 114854
-rect 365546 78938 365782 79174
-rect 365866 78938 366102 79174
-rect 365546 78618 365782 78854
-rect 365866 78618 366102 78854
-rect 365546 42938 365782 43174
-rect 365866 42938 366102 43174
-rect 365546 42618 365782 42854
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-rect 365546 6938 365782 7174
-rect 365866 6938 366102 7174
-rect 365546 6618 365782 6854
-rect 365866 6618 366102 6854
-rect 365546 -2502 365782 -2266
-rect 365866 -2502 366102 -2266
-rect 365546 -2822 365782 -2586
-rect 365866 -2822 366102 -2586
-rect 369266 334658 369502 334894
-rect 369586 334658 369822 334894
-rect 369266 334338 369502 334574
-rect 369586 334338 369822 334574
-rect 369266 298658 369502 298894
-rect 369586 298658 369822 298894
-rect 369266 298338 369502 298574
-rect 369586 298338 369822 298574
-rect 369266 262658 369502 262894
-rect 369586 262658 369822 262894
-rect 369266 262338 369502 262574
-rect 369586 262338 369822 262574
-rect 369266 226658 369502 226894
-rect 369586 226658 369822 226894
-rect 369266 226338 369502 226574
-rect 369586 226338 369822 226574
-rect 369266 190658 369502 190894
-rect 369586 190658 369822 190894
-rect 369266 190338 369502 190574
-rect 369586 190338 369822 190574
-rect 369266 154658 369502 154894
-rect 369586 154658 369822 154894
-rect 369266 154338 369502 154574
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-rect 390986 -7302 391222 -7066
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-rect 419546 672938 419782 673174
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-rect 423266 676658 423502 676894
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-rect 423586 280658 423822 280894
-rect 423266 280338 423502 280574
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-rect 423266 -5382 423502 -5146
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-rect 437546 690938 437782 691174
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-rect 441266 694658 441502 694894
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-rect 455546 672938 455782 673174
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-rect 455546 600938 455782 601174
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-rect 527546 672938 527782 673174
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-rect 531266 676658 531502 676894
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-rect 545546 690938 545782 691174
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-<< metal5 >>
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-rect -4886 564586 588810 564618
-rect -2966 561454 586890 561486
-rect -2966 561218 -2934 561454
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-rect -2966 560898 -2934 561134
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-rect -2966 560866 586890 560898
-rect -8726 554614 592650 554646
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-rect -8726 554026 592650 554058
-rect -6806 550894 590730 550926
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-rect -6806 550338 -5814 550574
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-rect -6806 550306 590730 550338
-rect -4886 547174 588810 547206
-rect -4886 546938 -3894 547174
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-rect -4886 546854 588810 546938
-rect -4886 546618 -3894 546854
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-rect 294102 546618 329546 546854
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-rect -2966 543134 586890 543218
-rect -2966 542898 -1974 543134
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-rect -2966 542866 586890 542898
-rect -8726 536614 592650 536646
-rect -8726 536378 -8694 536614
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-rect -8726 536294 592650 536378
-rect -8726 536058 -8694 536294
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-rect -8726 536026 592650 536058
-rect -6806 532894 590730 532926
-rect -6806 532658 -6774 532894
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-rect -6806 532574 590730 532658
-rect -6806 532338 -6774 532574
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-rect 567822 532338 590142 532574
-rect 590378 532338 590462 532574
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-rect -6806 532306 590730 532338
-rect -4886 529174 588810 529206
-rect -4886 528938 -4854 529174
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-rect -4298 528938 23546 529174
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-rect 24102 528938 59546 529174
-rect 59782 528938 59866 529174
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-rect -4886 528854 588810 528938
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-rect -6806 514894 590730 514926
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-rect -6806 514574 590730 514658
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-rect -6806 514306 590730 514338
-rect -4886 511174 588810 511206
-rect -4886 510938 -3894 511174
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-rect -4886 510618 -3894 510854
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-rect -2966 507454 586890 507486
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-rect -2966 506898 -1974 507134
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-rect -2966 506866 586890 506898
-rect -8726 500614 592650 500646
-rect -8726 500378 -8694 500614
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-rect -8726 500026 592650 500058
-rect -6806 496894 590730 496926
-rect -6806 496658 -6774 496894
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-rect -6806 496574 590730 496658
-rect -6806 496338 -6774 496574
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-rect -8726 446614 592650 446646
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-rect -6806 442574 590730 442658
-rect -6806 442338 -5814 442574
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-rect -6806 442306 590730 442338
-rect -4886 439174 588810 439206
-rect -4886 438938 -3894 439174
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-rect -4886 438618 -3894 438854
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-rect -2966 435454 586890 435486
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-rect -2966 434866 586890 434898
-rect -8726 428614 592650 428646
-rect -8726 428378 -8694 428614
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-rect -8726 428294 592650 428378
-rect -8726 428058 -8694 428294
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-rect -8726 428026 592650 428058
-rect -6806 424894 590730 424926
-rect -6806 424658 -6774 424894
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-rect -6806 424574 590730 424658
-rect -6806 424338 -6774 424574
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-rect -6218 424338 27266 424574
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-rect 171502 424338 171586 424574
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-rect 423822 424338 459266 424574
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-rect 459822 424338 495266 424574
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-rect 495822 424338 531266 424574
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-rect -6806 424306 590730 424338
-rect -4886 421174 588810 421206
-rect -4886 420938 -4854 421174
-rect -4618 420938 -4534 421174
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-rect 588778 420938 588810 421174
-rect -4886 420854 588810 420938
-rect -4886 420618 -4854 420854
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-rect -6806 388894 590730 388926
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-rect -6806 388338 -6774 388574
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-rect -6806 388306 590730 388338
-rect -4886 385174 588810 385206
-rect -4886 384938 -4854 385174
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-rect -4886 384854 588810 384938
-rect -4886 384618 -4854 384854
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-rect -4886 384586 588810 384618
-rect -2966 381454 586890 381486
-rect -2966 381218 -2934 381454
-rect -2698 381218 -2614 381454
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-rect -2966 381134 586890 381218
-rect -2966 380898 -2934 381134
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-rect -2966 380866 586890 380898
-rect -8726 374614 592650 374646
-rect -8726 374378 -7734 374614
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-rect 481542 374378 516986 374614
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-rect -6806 370894 590730 370926
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-rect -4886 366618 -3894 366854
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-rect -8726 356614 592650 356646
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-rect -6806 352574 590730 352658
-rect -6806 352338 -6774 352574
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-rect -6806 352306 590730 352338
-rect -4886 349174 588810 349206
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-rect -4886 348854 588810 348938
-rect -4886 348618 -4854 348854
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-rect -4886 348586 588810 348618
-rect -2966 345454 586890 345486
-rect -2966 345218 -2934 345454
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-rect -2966 345134 586890 345218
-rect -2966 344898 -2934 345134
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-rect -2966 344866 586890 344898
-rect -8726 338614 592650 338646
-rect -8726 338378 -7734 338614
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-rect -8726 338294 592650 338378
-rect -8726 338058 -7734 338294
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-rect -8726 338026 592650 338058
-rect -6806 334894 590730 334926
-rect -6806 334658 -5814 334894
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-rect -6806 334574 590730 334658
-rect -6806 334338 -5814 334574
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-rect 189822 334338 225266 334574
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-rect 549822 334338 589182 334574
-rect 589418 334338 589502 334574
-rect 589738 334338 590730 334574
-rect -6806 334306 590730 334338
-rect -4886 331174 588810 331206
-rect -4886 330938 -3894 331174
-rect -3658 330938 -3574 331174
-rect -3338 330938 5546 331174
-rect 5782 330938 5866 331174
-rect 6102 330938 41546 331174
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-rect 42102 330938 77546 331174
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-rect 78102 330938 113546 331174
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-rect 114102 330938 149546 331174
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-rect 150102 330938 185546 331174
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-rect 186102 330938 221546 331174
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-rect 330102 330938 365546 331174
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-rect 401782 330938 401866 331174
-rect 402102 330938 437546 331174
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-rect 509782 330938 509866 331174
-rect 510102 330938 545546 331174
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-rect 546102 330938 581546 331174
-rect 581782 330938 581866 331174
-rect 582102 330938 587262 331174
-rect 587498 330938 587582 331174
-rect 587818 330938 588810 331174
-rect -4886 330854 588810 330938
-rect -4886 330618 -3894 330854
-rect -3658 330618 -3574 330854
-rect -3338 330618 5546 330854
-rect 5782 330618 5866 330854
-rect 6102 330618 41546 330854
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-rect 42102 330618 77546 330854
-rect 77782 330618 77866 330854
-rect 78102 330618 113546 330854
-rect 113782 330618 113866 330854
-rect 114102 330618 149546 330854
-rect 149782 330618 149866 330854
-rect 150102 330618 185546 330854
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-rect 186102 330618 221546 330854
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-rect 258102 330618 293546 330854
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-rect 294102 330618 329546 330854
-rect 329782 330618 329866 330854
-rect 330102 330618 365546 330854
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-rect 401782 330618 401866 330854
-rect 402102 330618 437546 330854
-rect 437782 330618 437866 330854
-rect 438102 330618 473546 330854
-rect 473782 330618 473866 330854
-rect 474102 330618 509546 330854
-rect 509782 330618 509866 330854
-rect 510102 330618 545546 330854
-rect 545782 330618 545866 330854
-rect 546102 330618 581546 330854
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-rect 582102 330618 587262 330854
-rect 587498 330618 587582 330854
-rect 587818 330618 588810 330854
-rect -4886 330586 588810 330618
-rect -2966 327454 586890 327486
-rect -2966 327218 -1974 327454
-rect -1738 327218 -1654 327454
-rect -1418 327218 1826 327454
-rect 2062 327218 2146 327454
-rect 2382 327218 37826 327454
-rect 38062 327218 38146 327454
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-rect 74382 327218 109826 327454
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-rect 110382 327218 145826 327454
-rect 146062 327218 146146 327454
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-rect 218062 327218 218146 327454
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-rect 254382 327218 289826 327454
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-rect 290382 327218 325826 327454
-rect 326062 327218 326146 327454
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-rect 362382 327218 397826 327454
-rect 398062 327218 398146 327454
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-rect 434062 327218 434146 327454
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-rect 470382 327218 505826 327454
-rect 506062 327218 506146 327454
-rect 506382 327218 541826 327454
-rect 542062 327218 542146 327454
-rect 542382 327218 577826 327454
-rect 578062 327218 578146 327454
-rect 578382 327218 585342 327454
-rect 585578 327218 585662 327454
-rect 585898 327218 586890 327454
-rect -2966 327134 586890 327218
-rect -2966 326898 -1974 327134
-rect -1738 326898 -1654 327134
-rect -1418 326898 1826 327134
-rect 2062 326898 2146 327134
-rect 2382 326898 37826 327134
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-rect 38382 326898 73826 327134
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-rect 74382 326898 109826 327134
-rect 110062 326898 110146 327134
-rect 110382 326898 145826 327134
-rect 146062 326898 146146 327134
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-rect 182062 326898 182146 327134
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-rect 218062 326898 218146 327134
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-rect 254062 326898 254146 327134
-rect 254382 326898 289826 327134
-rect 290062 326898 290146 327134
-rect 290382 326898 325826 327134
-rect 326062 326898 326146 327134
-rect 326382 326898 361826 327134
-rect 362062 326898 362146 327134
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-rect 398062 326898 398146 327134
-rect 398382 326898 433826 327134
-rect 434062 326898 434146 327134
-rect 434382 326898 469826 327134
-rect 470062 326898 470146 327134
-rect 470382 326898 505826 327134
-rect 506062 326898 506146 327134
-rect 506382 326898 541826 327134
-rect 542062 326898 542146 327134
-rect 542382 326898 577826 327134
-rect 578062 326898 578146 327134
-rect 578382 326898 585342 327134
-rect 585578 326898 585662 327134
-rect 585898 326898 586890 327134
-rect -2966 326866 586890 326898
-rect -8726 320614 592650 320646
-rect -8726 320378 -8694 320614
-rect -8458 320378 -8374 320614
-rect -8138 320378 30986 320614
-rect 31222 320378 31306 320614
-rect 31542 320378 66986 320614
-rect 67222 320378 67306 320614
-rect 67542 320378 102986 320614
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-rect 103542 320378 138986 320614
-rect 139222 320378 139306 320614
-rect 139542 320378 174986 320614
-rect 175222 320378 175306 320614
-rect 175542 320378 210986 320614
-rect 211222 320378 211306 320614
-rect 211542 320378 246986 320614
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-rect 247542 320378 282986 320614
-rect 283222 320378 283306 320614
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-rect 319542 320378 354986 320614
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-rect 355542 320378 390986 320614
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-rect 427222 320378 427306 320614
-rect 427542 320378 462986 320614
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-rect 463542 320378 498986 320614
-rect 499222 320378 499306 320614
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-rect 571222 320378 571306 320614
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-rect 592298 320378 592382 320614
-rect 592618 320378 592650 320614
-rect -8726 320294 592650 320378
-rect -8726 320058 -8694 320294
-rect -8458 320058 -8374 320294
-rect -8138 320058 30986 320294
-rect 31222 320058 31306 320294
-rect 31542 320058 66986 320294
-rect 67222 320058 67306 320294
-rect 67542 320058 102986 320294
-rect 103222 320058 103306 320294
-rect 103542 320058 138986 320294
-rect 139222 320058 139306 320294
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-rect 175222 320058 175306 320294
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-rect 211222 320058 211306 320294
-rect 211542 320058 246986 320294
-rect 247222 320058 247306 320294
-rect 247542 320058 282986 320294
-rect 283222 320058 283306 320294
-rect 283542 320058 318986 320294
-rect 319222 320058 319306 320294
-rect 319542 320058 354986 320294
-rect 355222 320058 355306 320294
-rect 355542 320058 390986 320294
-rect 391222 320058 391306 320294
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-rect 427222 320058 427306 320294
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-rect 463542 320058 498986 320294
-rect 499222 320058 499306 320294
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-rect 535222 320058 535306 320294
-rect 535542 320058 570986 320294
-rect 571222 320058 571306 320294
-rect 571542 320058 592062 320294
-rect 592298 320058 592382 320294
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-rect -8726 320026 592650 320058
-rect -6806 316894 590730 316926
-rect -6806 316658 -6774 316894
-rect -6538 316658 -6454 316894
-rect -6218 316658 27266 316894
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-rect 63822 316658 99266 316894
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-rect 135822 316658 171266 316894
-rect 171502 316658 171586 316894
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-rect 315822 316658 351266 316894
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-rect 351822 316658 387266 316894
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-rect 387822 316658 423266 316894
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-rect 423822 316658 459266 316894
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-rect 495822 316658 531266 316894
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-rect 531822 316658 567266 316894
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-rect 590378 316658 590462 316894
-rect 590698 316658 590730 316894
-rect -6806 316574 590730 316658
-rect -6806 316338 -6774 316574
-rect -6538 316338 -6454 316574
-rect -6218 316338 27266 316574
-rect 27502 316338 27586 316574
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-rect 63822 316338 99266 316574
-rect 99502 316338 99586 316574
-rect 99822 316338 135266 316574
-rect 135502 316338 135586 316574
-rect 135822 316338 171266 316574
-rect 171502 316338 171586 316574
-rect 171822 316338 207266 316574
-rect 207502 316338 207586 316574
-rect 207822 316338 243266 316574
-rect 243502 316338 243586 316574
-rect 243822 316338 279266 316574
-rect 279502 316338 279586 316574
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-rect 315502 316338 315586 316574
-rect 315822 316338 351266 316574
-rect 351502 316338 351586 316574
-rect 351822 316338 387266 316574
-rect 387502 316338 387586 316574
-rect 387822 316338 423266 316574
-rect 423502 316338 423586 316574
-rect 423822 316338 459266 316574
-rect 459502 316338 459586 316574
-rect 459822 316338 495266 316574
-rect 495502 316338 495586 316574
-rect 495822 316338 531266 316574
-rect 531502 316338 531586 316574
-rect 531822 316338 567266 316574
-rect 567502 316338 567586 316574
-rect 567822 316338 590142 316574
-rect 590378 316338 590462 316574
-rect 590698 316338 590730 316574
-rect -6806 316306 590730 316338
-rect -4886 313174 588810 313206
-rect -4886 312938 -4854 313174
-rect -4618 312938 -4534 313174
-rect -4298 312938 23546 313174
-rect 23782 312938 23866 313174
-rect 24102 312938 59546 313174
-rect 59782 312938 59866 313174
-rect 60102 312938 95546 313174
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-rect 96102 312938 131546 313174
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-rect 132102 312938 167546 313174
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-rect 168102 312938 203546 313174
-rect 203782 312938 203866 313174
-rect 204102 312938 239546 313174
-rect 239782 312938 239866 313174
-rect 240102 312938 275546 313174
-rect 275782 312938 275866 313174
-rect 276102 312938 311546 313174
-rect 311782 312938 311866 313174
-rect 312102 312938 347546 313174
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-rect 384102 312938 419546 313174
-rect 419782 312938 419866 313174
-rect 420102 312938 455546 313174
-rect 455782 312938 455866 313174
-rect 456102 312938 491546 313174
-rect 491782 312938 491866 313174
-rect 492102 312938 527546 313174
-rect 527782 312938 527866 313174
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-rect 563782 312938 563866 313174
-rect 564102 312938 588222 313174
-rect 588458 312938 588542 313174
-rect 588778 312938 588810 313174
-rect -4886 312854 588810 312938
-rect -4886 312618 -4854 312854
-rect -4618 312618 -4534 312854
-rect -4298 312618 23546 312854
-rect 23782 312618 23866 312854
-rect 24102 312618 59546 312854
-rect 59782 312618 59866 312854
-rect 60102 312618 95546 312854
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-rect 96102 312618 131546 312854
-rect 131782 312618 131866 312854
-rect 132102 312618 167546 312854
-rect 167782 312618 167866 312854
-rect 168102 312618 203546 312854
-rect 203782 312618 203866 312854
-rect 204102 312618 239546 312854
-rect 239782 312618 239866 312854
-rect 240102 312618 275546 312854
-rect 275782 312618 275866 312854
-rect 276102 312618 311546 312854
-rect 311782 312618 311866 312854
-rect 312102 312618 347546 312854
-rect 347782 312618 347866 312854
-rect 348102 312618 383546 312854
-rect 383782 312618 383866 312854
-rect 384102 312618 419546 312854
-rect 419782 312618 419866 312854
-rect 420102 312618 455546 312854
-rect 455782 312618 455866 312854
-rect 456102 312618 491546 312854
-rect 491782 312618 491866 312854
-rect 492102 312618 527546 312854
-rect 527782 312618 527866 312854
-rect 528102 312618 563546 312854
-rect 563782 312618 563866 312854
-rect 564102 312618 588222 312854
-rect 588458 312618 588542 312854
-rect 588778 312618 588810 312854
-rect -4886 312586 588810 312618
-rect -2966 309454 586890 309486
-rect -2966 309218 -2934 309454
-rect -2698 309218 -2614 309454
-rect -2378 309218 19826 309454
-rect 20062 309218 20146 309454
-rect 20382 309218 55826 309454
-rect 56062 309218 56146 309454
-rect 56382 309218 91826 309454
-rect 92062 309218 92146 309454
-rect 92382 309218 127826 309454
-rect 128062 309218 128146 309454
-rect 128382 309218 163826 309454
-rect 164062 309218 164146 309454
-rect 164382 309218 199826 309454
-rect 200062 309218 200146 309454
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-rect 236062 309218 236146 309454
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-rect 308062 309218 308146 309454
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-rect 344062 309218 344146 309454
-rect 344382 309218 379826 309454
-rect 380062 309218 380146 309454
-rect 380382 309218 415826 309454
-rect 416062 309218 416146 309454
-rect 416382 309218 451826 309454
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-rect 452382 309218 487826 309454
-rect 488062 309218 488146 309454
-rect 488382 309218 523826 309454
-rect 524062 309218 524146 309454
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-rect 560062 309218 560146 309454
-rect 560382 309218 586302 309454
-rect 586538 309218 586622 309454
-rect 586858 309218 586890 309454
-rect -2966 309134 586890 309218
-rect -2966 308898 -2934 309134
-rect -2698 308898 -2614 309134
-rect -2378 308898 19826 309134
-rect 20062 308898 20146 309134
-rect 20382 308898 55826 309134
-rect 56062 308898 56146 309134
-rect 56382 308898 91826 309134
-rect 92062 308898 92146 309134
-rect 92382 308898 127826 309134
-rect 128062 308898 128146 309134
-rect 128382 308898 163826 309134
-rect 164062 308898 164146 309134
-rect 164382 308898 199826 309134
-rect 200062 308898 200146 309134
-rect 200382 308898 235826 309134
-rect 236062 308898 236146 309134
-rect 236382 308898 271826 309134
-rect 272062 308898 272146 309134
-rect 272382 308898 307826 309134
-rect 308062 308898 308146 309134
-rect 308382 308898 343826 309134
-rect 344062 308898 344146 309134
-rect 344382 308898 379826 309134
-rect 380062 308898 380146 309134
-rect 380382 308898 415826 309134
-rect 416062 308898 416146 309134
-rect 416382 308898 451826 309134
-rect 452062 308898 452146 309134
-rect 452382 308898 487826 309134
-rect 488062 308898 488146 309134
-rect 488382 308898 523826 309134
-rect 524062 308898 524146 309134
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-rect 560062 308898 560146 309134
-rect 560382 308898 586302 309134
-rect 586538 308898 586622 309134
-rect 586858 308898 586890 309134
-rect -2966 308866 586890 308898
-rect -8726 302614 592650 302646
-rect -8726 302378 -7734 302614
-rect -7498 302378 -7414 302614
-rect -7178 302378 12986 302614
-rect 13222 302378 13306 302614
-rect 13542 302378 48986 302614
-rect 49222 302378 49306 302614
-rect 49542 302378 84986 302614
-rect 85222 302378 85306 302614
-rect 85542 302378 120986 302614
-rect 121222 302378 121306 302614
-rect 121542 302378 156986 302614
-rect 157222 302378 157306 302614
-rect 157542 302378 192986 302614
-rect 193222 302378 193306 302614
-rect 193542 302378 228986 302614
-rect 229222 302378 229306 302614
-rect 229542 302378 264986 302614
-rect 265222 302378 265306 302614
-rect 265542 302378 300986 302614
-rect 301222 302378 301306 302614
-rect 301542 302378 336986 302614
-rect 337222 302378 337306 302614
-rect 337542 302378 372986 302614
-rect 373222 302378 373306 302614
-rect 373542 302378 408986 302614
-rect 409222 302378 409306 302614
-rect 409542 302378 444986 302614
-rect 445222 302378 445306 302614
-rect 445542 302378 480986 302614
-rect 481222 302378 481306 302614
-rect 481542 302378 516986 302614
-rect 517222 302378 517306 302614
-rect 517542 302378 552986 302614
-rect 553222 302378 553306 302614
-rect 553542 302378 591102 302614
-rect 591338 302378 591422 302614
-rect 591658 302378 592650 302614
-rect -8726 302294 592650 302378
-rect -8726 302058 -7734 302294
-rect -7498 302058 -7414 302294
-rect -7178 302058 12986 302294
-rect 13222 302058 13306 302294
-rect 13542 302058 48986 302294
-rect 49222 302058 49306 302294
-rect 49542 302058 84986 302294
-rect 85222 302058 85306 302294
-rect 85542 302058 120986 302294
-rect 121222 302058 121306 302294
-rect 121542 302058 156986 302294
-rect 157222 302058 157306 302294
-rect 157542 302058 192986 302294
-rect 193222 302058 193306 302294
-rect 193542 302058 228986 302294
-rect 229222 302058 229306 302294
-rect 229542 302058 264986 302294
-rect 265222 302058 265306 302294
-rect 265542 302058 300986 302294
-rect 301222 302058 301306 302294
-rect 301542 302058 336986 302294
-rect 337222 302058 337306 302294
-rect 337542 302058 372986 302294
-rect 373222 302058 373306 302294
-rect 373542 302058 408986 302294
-rect 409222 302058 409306 302294
-rect 409542 302058 444986 302294
-rect 445222 302058 445306 302294
-rect 445542 302058 480986 302294
-rect 481222 302058 481306 302294
-rect 481542 302058 516986 302294
-rect 517222 302058 517306 302294
-rect 517542 302058 552986 302294
-rect 553222 302058 553306 302294
-rect 553542 302058 591102 302294
-rect 591338 302058 591422 302294
-rect 591658 302058 592650 302294
-rect -8726 302026 592650 302058
-rect -6806 298894 590730 298926
-rect -6806 298658 -5814 298894
-rect -5578 298658 -5494 298894
-rect -5258 298658 9266 298894
-rect 9502 298658 9586 298894
-rect 9822 298658 45266 298894
-rect 45502 298658 45586 298894
-rect 45822 298658 81266 298894
-rect 81502 298658 81586 298894
-rect 81822 298658 117266 298894
-rect 117502 298658 117586 298894
-rect 117822 298658 153266 298894
-rect 153502 298658 153586 298894
-rect 153822 298658 189266 298894
-rect 189502 298658 189586 298894
-rect 189822 298658 225266 298894
-rect 225502 298658 225586 298894
-rect 225822 298658 261266 298894
-rect 261502 298658 261586 298894
-rect 261822 298658 297266 298894
-rect 297502 298658 297586 298894
-rect 297822 298658 333266 298894
-rect 333502 298658 333586 298894
-rect 333822 298658 369266 298894
-rect 369502 298658 369586 298894
-rect 369822 298658 405266 298894
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-rect -6806 244338 -6774 244574
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-rect -4886 240618 -4854 240854
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-rect -2966 237454 586890 237486
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-rect -2966 237134 586890 237218
-rect -2966 236898 -2934 237134
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-rect -2966 236866 586890 236898
-rect -8726 230614 592650 230646
-rect -8726 230378 -7734 230614
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-rect -7178 230378 12986 230614
-rect 13222 230378 13306 230614
-rect 13542 230378 48986 230614
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-rect 49542 230378 84986 230614
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-rect 85542 230378 120986 230614
-rect 121222 230378 121306 230614
-rect 121542 230378 156986 230614
-rect 157222 230378 157306 230614
-rect 157542 230378 192986 230614
-rect 193222 230378 193306 230614
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-rect 229542 230378 264986 230614
-rect 265222 230378 265306 230614
-rect 265542 230378 300986 230614
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-rect 301542 230378 336986 230614
-rect 337222 230378 337306 230614
-rect 337542 230378 372986 230614
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-rect 373542 230378 408986 230614
-rect 409222 230378 409306 230614
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-rect 445542 230378 480986 230614
-rect 481222 230378 481306 230614
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-rect 517542 230378 552986 230614
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-rect 553542 230378 591102 230614
-rect 591338 230378 591422 230614
-rect 591658 230378 592650 230614
-rect -8726 230294 592650 230378
-rect -8726 230058 -7734 230294
-rect -7498 230058 -7414 230294
-rect -7178 230058 12986 230294
-rect 13222 230058 13306 230294
-rect 13542 230058 48986 230294
-rect 49222 230058 49306 230294
-rect 49542 230058 84986 230294
-rect 85222 230058 85306 230294
-rect 85542 230058 120986 230294
-rect 121222 230058 121306 230294
-rect 121542 230058 156986 230294
-rect 157222 230058 157306 230294
-rect 157542 230058 192986 230294
-rect 193222 230058 193306 230294
-rect 193542 230058 228986 230294
-rect 229222 230058 229306 230294
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-rect 265222 230058 265306 230294
-rect 265542 230058 300986 230294
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-rect 301542 230058 336986 230294
-rect 337222 230058 337306 230294
-rect 337542 230058 372986 230294
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-rect 373542 230058 408986 230294
-rect 409222 230058 409306 230294
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-rect 445222 230058 445306 230294
-rect 445542 230058 480986 230294
-rect 481222 230058 481306 230294
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-rect 591338 230058 591422 230294
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-rect -8726 230026 592650 230058
-rect -6806 226894 590730 226926
-rect -6806 226658 -5814 226894
-rect -5578 226658 -5494 226894
-rect -5258 226658 9266 226894
-rect 9502 226658 9586 226894
-rect 9822 226658 45266 226894
-rect 45502 226658 45586 226894
-rect 45822 226658 81266 226894
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-rect 81822 226658 117266 226894
-rect 117502 226658 117586 226894
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-rect 153502 226658 153586 226894
-rect 153822 226658 189266 226894
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-rect 189822 226658 225266 226894
-rect 225502 226658 225586 226894
-rect 225822 226658 261266 226894
-rect 261502 226658 261586 226894
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-rect 297502 226658 297586 226894
-rect 297822 226658 333266 226894
-rect 333502 226658 333586 226894
-rect 333822 226658 369266 226894
-rect 369502 226658 369586 226894
-rect 369822 226658 405266 226894
-rect 405502 226658 405586 226894
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-rect 441502 226658 441586 226894
-rect 441822 226658 477266 226894
-rect 477502 226658 477586 226894
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-rect 513502 226658 513586 226894
-rect 513822 226658 549266 226894
-rect 549502 226658 549586 226894
-rect 549822 226658 589182 226894
-rect 589418 226658 589502 226894
-rect 589738 226658 590730 226894
-rect -6806 226574 590730 226658
-rect -6806 226338 -5814 226574
-rect -5578 226338 -5494 226574
-rect -5258 226338 9266 226574
-rect 9502 226338 9586 226574
-rect 9822 226338 45266 226574
-rect 45502 226338 45586 226574
-rect 45822 226338 81266 226574
-rect 81502 226338 81586 226574
-rect 81822 226338 117266 226574
-rect 117502 226338 117586 226574
-rect 117822 226338 153266 226574
-rect 153502 226338 153586 226574
-rect 153822 226338 189266 226574
-rect 189502 226338 189586 226574
-rect 189822 226338 225266 226574
-rect 225502 226338 225586 226574
-rect 225822 226338 261266 226574
-rect 261502 226338 261586 226574
-rect 261822 226338 297266 226574
-rect 297502 226338 297586 226574
-rect 297822 226338 333266 226574
-rect 333502 226338 333586 226574
-rect 333822 226338 369266 226574
-rect 369502 226338 369586 226574
-rect 369822 226338 405266 226574
-rect 405502 226338 405586 226574
-rect 405822 226338 441266 226574
-rect 441502 226338 441586 226574
-rect 441822 226338 477266 226574
-rect 477502 226338 477586 226574
-rect 477822 226338 513266 226574
-rect 513502 226338 513586 226574
-rect 513822 226338 549266 226574
-rect 549502 226338 549586 226574
-rect 549822 226338 589182 226574
-rect 589418 226338 589502 226574
-rect 589738 226338 590730 226574
-rect -6806 226306 590730 226338
-rect -4886 223174 588810 223206
-rect -4886 222938 -3894 223174
-rect -3658 222938 -3574 223174
-rect -3338 222938 5546 223174
-rect 5782 222938 5866 223174
-rect 6102 222938 41546 223174
-rect 41782 222938 41866 223174
-rect 42102 222938 77546 223174
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-rect 78102 222938 113546 223174
-rect 113782 222938 113866 223174
-rect 114102 222938 149546 223174
-rect 149782 222938 149866 223174
-rect 150102 222938 185546 223174
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-rect 186102 222938 221546 223174
-rect 221782 222938 221866 223174
-rect 222102 222938 257546 223174
-rect 257782 222938 257866 223174
-rect 258102 222938 293546 223174
-rect 293782 222938 293866 223174
-rect 294102 222938 329546 223174
-rect 329782 222938 329866 223174
-rect 330102 222938 365546 223174
-rect 365782 222938 365866 223174
-rect 366102 222938 401546 223174
-rect 401782 222938 401866 223174
-rect 402102 222938 437546 223174
-rect 437782 222938 437866 223174
-rect 438102 222938 473546 223174
-rect 473782 222938 473866 223174
-rect 474102 222938 509546 223174
-rect 509782 222938 509866 223174
-rect 510102 222938 545546 223174
-rect 545782 222938 545866 223174
-rect 546102 222938 581546 223174
-rect 581782 222938 581866 223174
-rect 582102 222938 587262 223174
-rect 587498 222938 587582 223174
-rect 587818 222938 588810 223174
-rect -4886 222854 588810 222938
-rect -4886 222618 -3894 222854
-rect -3658 222618 -3574 222854
-rect -3338 222618 5546 222854
-rect 5782 222618 5866 222854
-rect 6102 222618 41546 222854
-rect 41782 222618 41866 222854
-rect 42102 222618 77546 222854
-rect 77782 222618 77866 222854
-rect 78102 222618 113546 222854
-rect 113782 222618 113866 222854
-rect 114102 222618 149546 222854
-rect 149782 222618 149866 222854
-rect 150102 222618 185546 222854
-rect 185782 222618 185866 222854
-rect 186102 222618 221546 222854
-rect 221782 222618 221866 222854
-rect 222102 222618 257546 222854
-rect 257782 222618 257866 222854
-rect 258102 222618 293546 222854
-rect 293782 222618 293866 222854
-rect 294102 222618 329546 222854
-rect 329782 222618 329866 222854
-rect 330102 222618 365546 222854
-rect 365782 222618 365866 222854
-rect 366102 222618 401546 222854
-rect 401782 222618 401866 222854
-rect 402102 222618 437546 222854
-rect 437782 222618 437866 222854
-rect 438102 222618 473546 222854
-rect 473782 222618 473866 222854
-rect 474102 222618 509546 222854
-rect 509782 222618 509866 222854
-rect 510102 222618 545546 222854
-rect 545782 222618 545866 222854
-rect 546102 222618 581546 222854
-rect 581782 222618 581866 222854
-rect 582102 222618 587262 222854
-rect 587498 222618 587582 222854
-rect 587818 222618 588810 222854
-rect -4886 222586 588810 222618
-rect -2966 219454 586890 219486
-rect -2966 219218 -1974 219454
-rect -1738 219218 -1654 219454
-rect -1418 219218 1826 219454
-rect 2062 219218 2146 219454
-rect 2382 219218 37826 219454
-rect 38062 219218 38146 219454
-rect 38382 219218 73826 219454
-rect 74062 219218 74146 219454
-rect 74382 219218 109826 219454
-rect 110062 219218 110146 219454
-rect 110382 219218 145826 219454
-rect 146062 219218 146146 219454
-rect 146382 219218 181826 219454
-rect 182062 219218 182146 219454
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-rect 218062 219218 218146 219454
-rect 218382 219218 253826 219454
-rect 254062 219218 254146 219454
-rect 254382 219218 289826 219454
-rect 290062 219218 290146 219454
-rect 290382 219218 325826 219454
-rect 326062 219218 326146 219454
-rect 326382 219218 361826 219454
-rect 362062 219218 362146 219454
-rect 362382 219218 397826 219454
-rect 398062 219218 398146 219454
-rect 398382 219218 433826 219454
-rect 434062 219218 434146 219454
-rect 434382 219218 469826 219454
-rect 470062 219218 470146 219454
-rect 470382 219218 505826 219454
-rect 506062 219218 506146 219454
-rect 506382 219218 541826 219454
-rect 542062 219218 542146 219454
-rect 542382 219218 577826 219454
-rect 578062 219218 578146 219454
-rect 578382 219218 585342 219454
-rect 585578 219218 585662 219454
-rect 585898 219218 586890 219454
-rect -2966 219134 586890 219218
-rect -2966 218898 -1974 219134
-rect -1738 218898 -1654 219134
-rect -1418 218898 1826 219134
-rect 2062 218898 2146 219134
-rect 2382 218898 37826 219134
-rect 38062 218898 38146 219134
-rect 38382 218898 73826 219134
-rect 74062 218898 74146 219134
-rect 74382 218898 109826 219134
-rect 110062 218898 110146 219134
-rect 110382 218898 145826 219134
-rect 146062 218898 146146 219134
-rect 146382 218898 181826 219134
-rect 182062 218898 182146 219134
-rect 182382 218898 217826 219134
-rect 218062 218898 218146 219134
-rect 218382 218898 253826 219134
-rect 254062 218898 254146 219134
-rect 254382 218898 289826 219134
-rect 290062 218898 290146 219134
-rect 290382 218898 325826 219134
-rect 326062 218898 326146 219134
-rect 326382 218898 361826 219134
-rect 362062 218898 362146 219134
-rect 362382 218898 397826 219134
-rect 398062 218898 398146 219134
-rect 398382 218898 433826 219134
-rect 434062 218898 434146 219134
-rect 434382 218898 469826 219134
-rect 470062 218898 470146 219134
-rect 470382 218898 505826 219134
-rect 506062 218898 506146 219134
-rect 506382 218898 541826 219134
-rect 542062 218898 542146 219134
-rect 542382 218898 577826 219134
-rect 578062 218898 578146 219134
-rect 578382 218898 585342 219134
-rect 585578 218898 585662 219134
-rect 585898 218898 586890 219134
-rect -2966 218866 586890 218898
-rect -8726 212614 592650 212646
-rect -8726 212378 -8694 212614
-rect -8458 212378 -8374 212614
-rect -8138 212378 30986 212614
-rect 31222 212378 31306 212614
-rect 31542 212378 66986 212614
-rect 67222 212378 67306 212614
-rect 67542 212378 102986 212614
-rect 103222 212378 103306 212614
-rect 103542 212378 138986 212614
-rect 139222 212378 139306 212614
-rect 139542 212378 174986 212614
-rect 175222 212378 175306 212614
-rect 175542 212378 210986 212614
-rect 211222 212378 211306 212614
-rect 211542 212378 246986 212614
-rect 247222 212378 247306 212614
-rect 247542 212378 282986 212614
-rect 283222 212378 283306 212614
-rect 283542 212378 318986 212614
-rect 319222 212378 319306 212614
-rect 319542 212378 354986 212614
-rect 355222 212378 355306 212614
-rect 355542 212378 390986 212614
-rect 391222 212378 391306 212614
-rect 391542 212378 426986 212614
-rect 427222 212378 427306 212614
-rect 427542 212378 462986 212614
-rect 463222 212378 463306 212614
-rect 463542 212378 498986 212614
-rect 499222 212378 499306 212614
-rect 499542 212378 534986 212614
-rect 535222 212378 535306 212614
-rect 535542 212378 570986 212614
-rect 571222 212378 571306 212614
-rect 571542 212378 592062 212614
-rect 592298 212378 592382 212614
-rect 592618 212378 592650 212614
-rect -8726 212294 592650 212378
-rect -8726 212058 -8694 212294
-rect -8458 212058 -8374 212294
-rect -8138 212058 30986 212294
-rect 31222 212058 31306 212294
-rect 31542 212058 66986 212294
-rect 67222 212058 67306 212294
-rect 67542 212058 102986 212294
-rect 103222 212058 103306 212294
-rect 103542 212058 138986 212294
-rect 139222 212058 139306 212294
-rect 139542 212058 174986 212294
-rect 175222 212058 175306 212294
-rect 175542 212058 210986 212294
-rect 211222 212058 211306 212294
-rect 211542 212058 246986 212294
-rect 247222 212058 247306 212294
-rect 247542 212058 282986 212294
-rect 283222 212058 283306 212294
-rect 283542 212058 318986 212294
-rect 319222 212058 319306 212294
-rect 319542 212058 354986 212294
-rect 355222 212058 355306 212294
-rect 355542 212058 390986 212294
-rect 391222 212058 391306 212294
-rect 391542 212058 426986 212294
-rect 427222 212058 427306 212294
-rect 427542 212058 462986 212294
-rect 463222 212058 463306 212294
-rect 463542 212058 498986 212294
-rect 499222 212058 499306 212294
-rect 499542 212058 534986 212294
-rect 535222 212058 535306 212294
-rect 535542 212058 570986 212294
-rect 571222 212058 571306 212294
-rect 571542 212058 592062 212294
-rect 592298 212058 592382 212294
-rect 592618 212058 592650 212294
-rect -8726 212026 592650 212058
-rect -6806 208894 590730 208926
-rect -6806 208658 -6774 208894
-rect -6538 208658 -6454 208894
-rect -6218 208658 27266 208894
-rect 27502 208658 27586 208894
-rect 27822 208658 63266 208894
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-rect 135502 208658 135586 208894
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-rect 171502 208658 171586 208894
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-rect 207822 208658 243266 208894
-rect 243502 208658 243586 208894
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-rect 315822 208658 351266 208894
-rect 351502 208658 351586 208894
-rect 351822 208658 387266 208894
-rect 387502 208658 387586 208894
-rect 387822 208658 423266 208894
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-rect 423822 208658 459266 208894
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-rect 459822 208658 495266 208894
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-rect 495822 208658 531266 208894
-rect 531502 208658 531586 208894
-rect 531822 208658 567266 208894
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-rect 567822 208658 590142 208894
-rect 590378 208658 590462 208894
-rect 590698 208658 590730 208894
-rect -6806 208574 590730 208658
-rect -6806 208338 -6774 208574
-rect -6538 208338 -6454 208574
-rect -6218 208338 27266 208574
-rect 27502 208338 27586 208574
-rect 27822 208338 63266 208574
-rect 63502 208338 63586 208574
-rect 63822 208338 99266 208574
-rect 99502 208338 99586 208574
-rect 99822 208338 135266 208574
-rect 135502 208338 135586 208574
-rect 135822 208338 171266 208574
-rect 171502 208338 171586 208574
-rect 171822 208338 207266 208574
-rect 207502 208338 207586 208574
-rect 207822 208338 243266 208574
-rect 243502 208338 243586 208574
-rect 243822 208338 279266 208574
-rect 279502 208338 279586 208574
-rect 279822 208338 315266 208574
-rect 315502 208338 315586 208574
-rect 315822 208338 351266 208574
-rect 351502 208338 351586 208574
-rect 351822 208338 387266 208574
-rect 387502 208338 387586 208574
-rect 387822 208338 423266 208574
-rect 423502 208338 423586 208574
-rect 423822 208338 459266 208574
-rect 459502 208338 459586 208574
-rect 459822 208338 495266 208574
-rect 495502 208338 495586 208574
-rect 495822 208338 531266 208574
-rect 531502 208338 531586 208574
-rect 531822 208338 567266 208574
-rect 567502 208338 567586 208574
-rect 567822 208338 590142 208574
-rect 590378 208338 590462 208574
-rect 590698 208338 590730 208574
-rect -6806 208306 590730 208338
-rect -4886 205174 588810 205206
-rect -4886 204938 -4854 205174
-rect -4618 204938 -4534 205174
-rect -4298 204938 23546 205174
-rect 23782 204938 23866 205174
-rect 24102 204938 59546 205174
-rect 59782 204938 59866 205174
-rect 60102 204938 95546 205174
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-rect 96102 204938 131546 205174
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-rect 132102 204938 167546 205174
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-rect 168102 204938 203546 205174
-rect 203782 204938 203866 205174
-rect 204102 204938 239546 205174
-rect 239782 204938 239866 205174
-rect 240102 204938 275546 205174
-rect 275782 204938 275866 205174
-rect 276102 204938 311546 205174
-rect 311782 204938 311866 205174
-rect 312102 204938 347546 205174
-rect 347782 204938 347866 205174
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-rect 383782 204938 383866 205174
-rect 384102 204938 419546 205174
-rect 419782 204938 419866 205174
-rect 420102 204938 455546 205174
-rect 455782 204938 455866 205174
-rect 456102 204938 491546 205174
-rect 491782 204938 491866 205174
-rect 492102 204938 527546 205174
-rect 527782 204938 527866 205174
-rect 528102 204938 563546 205174
-rect 563782 204938 563866 205174
-rect 564102 204938 588222 205174
-rect 588458 204938 588542 205174
-rect 588778 204938 588810 205174
-rect -4886 204854 588810 204938
-rect -4886 204618 -4854 204854
-rect -4618 204618 -4534 204854
-rect -4298 204618 23546 204854
-rect 23782 204618 23866 204854
-rect 24102 204618 59546 204854
-rect 59782 204618 59866 204854
-rect 60102 204618 95546 204854
-rect 95782 204618 95866 204854
-rect 96102 204618 131546 204854
-rect 131782 204618 131866 204854
-rect 132102 204618 167546 204854
-rect 167782 204618 167866 204854
-rect 168102 204618 203546 204854
-rect 203782 204618 203866 204854
-rect 204102 204618 239546 204854
-rect 239782 204618 239866 204854
-rect 240102 204618 275546 204854
-rect 275782 204618 275866 204854
-rect 276102 204618 311546 204854
-rect 311782 204618 311866 204854
-rect 312102 204618 347546 204854
-rect 347782 204618 347866 204854
-rect 348102 204618 383546 204854
-rect 383782 204618 383866 204854
-rect 384102 204618 419546 204854
-rect 419782 204618 419866 204854
-rect 420102 204618 455546 204854
-rect 455782 204618 455866 204854
-rect 456102 204618 491546 204854
-rect 491782 204618 491866 204854
-rect 492102 204618 527546 204854
-rect 527782 204618 527866 204854
-rect 528102 204618 563546 204854
-rect 563782 204618 563866 204854
-rect 564102 204618 588222 204854
-rect 588458 204618 588542 204854
-rect 588778 204618 588810 204854
-rect -4886 204586 588810 204618
-rect -2966 201454 586890 201486
-rect -2966 201218 -2934 201454
-rect -2698 201218 -2614 201454
-rect -2378 201218 19826 201454
-rect 20062 201218 20146 201454
-rect 20382 201218 55826 201454
-rect 56062 201218 56146 201454
-rect 56382 201218 91826 201454
-rect 92062 201218 92146 201454
-rect 92382 201218 127826 201454
-rect 128062 201218 128146 201454
-rect 128382 201218 163826 201454
-rect 164062 201218 164146 201454
-rect 164382 201218 199826 201454
-rect 200062 201218 200146 201454
-rect 200382 201218 235826 201454
-rect 236062 201218 236146 201454
-rect 236382 201218 271826 201454
-rect 272062 201218 272146 201454
-rect 272382 201218 307826 201454
-rect 308062 201218 308146 201454
-rect 308382 201218 343826 201454
-rect 344062 201218 344146 201454
-rect 344382 201218 379826 201454
-rect 380062 201218 380146 201454
-rect 380382 201218 415826 201454
-rect 416062 201218 416146 201454
-rect 416382 201218 451826 201454
-rect 452062 201218 452146 201454
-rect 452382 201218 487826 201454
-rect 488062 201218 488146 201454
-rect 488382 201218 523826 201454
-rect 524062 201218 524146 201454
-rect 524382 201218 559826 201454
-rect 560062 201218 560146 201454
-rect 560382 201218 586302 201454
-rect 586538 201218 586622 201454
-rect 586858 201218 586890 201454
-rect -2966 201134 586890 201218
-rect -2966 200898 -2934 201134
-rect -2698 200898 -2614 201134
-rect -2378 200898 19826 201134
-rect 20062 200898 20146 201134
-rect 20382 200898 55826 201134
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-rect 588778 132938 588810 133174
-rect -4886 132854 588810 132938
-rect -4886 132618 -4854 132854
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-rect -8726 122026 592650 122058
-rect -6806 118894 590730 118926
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-rect -6806 118574 590730 118658
-rect -6806 118338 -5814 118574
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-rect 153502 118338 153586 118574
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-rect 297502 118338 297586 118574
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-rect -6806 118306 590730 118338
-rect -4886 115174 588810 115206
-rect -4886 114938 -3894 115174
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-rect 150102 114938 185546 115174
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-rect 258102 114938 293546 115174
-rect 293782 114938 293866 115174
-rect 294102 114938 329546 115174
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-rect 587818 114938 588810 115174
-rect -4886 114854 588810 114938
-rect -4886 114618 -3894 114854
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-rect 113782 114618 113866 114854
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-rect 150102 114618 185546 114854
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-rect 294102 114618 329546 114854
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-rect -4886 114586 588810 114618
-rect -2966 111454 586890 111486
-rect -2966 111218 -1974 111454
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-rect -2966 111134 586890 111218
-rect -2966 110898 -1974 111134
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-rect -2966 110866 586890 110898
-rect -8726 104614 592650 104646
-rect -8726 104378 -8694 104614
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-rect -8726 104294 592650 104378
-rect -8726 104058 -8694 104294
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-rect 283222 104058 283306 104294
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-rect 499222 104058 499306 104294
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-rect 571222 104058 571306 104294
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-rect -8726 104026 592650 104058
-rect -6806 100894 590730 100926
-rect -6806 100658 -6774 100894
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-rect -6218 100658 27266 100894
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-rect 171502 100658 171586 100894
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-rect 495822 100658 531266 100894
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-rect 590378 100658 590462 100894
-rect 590698 100658 590730 100894
-rect -6806 100574 590730 100658
-rect -6806 100338 -6774 100574
-rect -6538 100338 -6454 100574
-rect -6218 100338 27266 100574
-rect 27502 100338 27586 100574
-rect 27822 100338 63266 100574
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-rect 63822 100338 99266 100574
-rect 99502 100338 99586 100574
-rect 99822 100338 135266 100574
-rect 135502 100338 135586 100574
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-rect 171502 100338 171586 100574
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-rect 207502 100338 207586 100574
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-rect 243502 100338 243586 100574
-rect 243822 100338 279266 100574
-rect 279502 100338 279586 100574
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-rect 315502 100338 315586 100574
-rect 315822 100338 351266 100574
-rect 351502 100338 351586 100574
-rect 351822 100338 387266 100574
-rect 387502 100338 387586 100574
-rect 387822 100338 423266 100574
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-rect 423822 100338 459266 100574
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-rect 459822 100338 495266 100574
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-rect 495822 100338 531266 100574
-rect 531502 100338 531586 100574
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-rect 567502 100338 567586 100574
-rect 567822 100338 590142 100574
-rect 590378 100338 590462 100574
-rect 590698 100338 590730 100574
-rect -6806 100306 590730 100338
-rect -4886 97174 588810 97206
-rect -4886 96938 -4854 97174
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-rect 63822 28658 99266 28894
-rect 99502 28658 99586 28894
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-rect 171502 28658 171586 28894
-rect 171822 28658 207266 28894
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-rect 315822 28658 351266 28894
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-rect 387822 28658 423266 28894
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-rect 423822 28658 459266 28894
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-rect 459822 28658 495266 28894
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-rect 590378 28658 590462 28894
-rect 590698 28658 590730 28894
-rect -6806 28574 590730 28658
-rect -6806 28338 -6774 28574
-rect -6538 28338 -6454 28574
-rect -6218 28338 27266 28574
-rect 27502 28338 27586 28574
-rect 27822 28338 63266 28574
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-rect 171502 28338 171586 28574
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-rect 315822 28338 351266 28574
-rect 351502 28338 351586 28574
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-rect 387822 28338 423266 28574
-rect 423502 28338 423586 28574
-rect 423822 28338 459266 28574
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-rect 459822 28338 495266 28574
-rect 495502 28338 495586 28574
-rect 495822 28338 531266 28574
-rect 531502 28338 531586 28574
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-rect 567502 28338 567586 28574
-rect 567822 28338 590142 28574
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-rect -6806 28306 590730 28338
-rect -4886 25174 588810 25206
-rect -4886 24938 -4854 25174
-rect -4618 24938 -4534 25174
-rect -4298 24938 23546 25174
-rect 23782 24938 23866 25174
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-rect 132102 24938 167546 25174
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-rect 168102 24938 203546 25174
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-rect 312102 24938 347546 25174
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-rect 384102 24938 419546 25174
-rect 419782 24938 419866 25174
-rect 420102 24938 455546 25174
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-rect 492102 24938 527546 25174
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-rect 528102 24938 563546 25174
-rect 563782 24938 563866 25174
-rect 564102 24938 588222 25174
-rect 588458 24938 588542 25174
-rect 588778 24938 588810 25174
-rect -4886 24854 588810 24938
-rect -4886 24618 -4854 24854
-rect -4618 24618 -4534 24854
-rect -4298 24618 23546 24854
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-rect 24102 24618 59546 24854
-rect 59782 24618 59866 24854
-rect 60102 24618 95546 24854
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-rect 96102 24618 131546 24854
-rect 131782 24618 131866 24854
-rect 132102 24618 167546 24854
-rect 167782 24618 167866 24854
-rect 168102 24618 203546 24854
-rect 203782 24618 203866 24854
-rect 204102 24618 239546 24854
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-rect 240102 24618 275546 24854
-rect 275782 24618 275866 24854
-rect 276102 24618 311546 24854
-rect 311782 24618 311866 24854
-rect 312102 24618 347546 24854
-rect 347782 24618 347866 24854
-rect 348102 24618 383546 24854
-rect 383782 24618 383866 24854
-rect 384102 24618 419546 24854
-rect 419782 24618 419866 24854
-rect 420102 24618 455546 24854
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-rect 456102 24618 491546 24854
-rect 491782 24618 491866 24854
-rect 492102 24618 527546 24854
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-rect 528102 24618 563546 24854
-rect 563782 24618 563866 24854
-rect 564102 24618 588222 24854
-rect 588458 24618 588542 24854
-rect 588778 24618 588810 24854
-rect -4886 24586 588810 24618
-rect -2966 21454 586890 21486
-rect -2966 21218 -2934 21454
-rect -2698 21218 -2614 21454
-rect -2378 21218 19826 21454
-rect 20062 21218 20146 21454
-rect 20382 21218 55826 21454
-rect 56062 21218 56146 21454
-rect 56382 21218 91826 21454
-rect 92062 21218 92146 21454
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-rect 128062 21218 128146 21454
-rect 128382 21218 163826 21454
-rect 164062 21218 164146 21454
-rect 164382 21218 199826 21454
-rect 200062 21218 200146 21454
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-rect 272062 21218 272146 21454
-rect 272382 21218 307826 21454
-rect 308062 21218 308146 21454
-rect 308382 21218 343826 21454
-rect 344062 21218 344146 21454
-rect 344382 21218 379826 21454
-rect 380062 21218 380146 21454
-rect 380382 21218 415826 21454
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-rect 452062 21218 452146 21454
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-rect 488062 21218 488146 21454
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-rect 560062 21218 560146 21454
-rect 560382 21218 586302 21454
-rect 586538 21218 586622 21454
-rect 586858 21218 586890 21454
-rect -2966 21134 586890 21218
-rect -2966 20898 -2934 21134
-rect -2698 20898 -2614 21134
-rect -2378 20898 19826 21134
-rect 20062 20898 20146 21134
-rect 20382 20898 55826 21134
-rect 56062 20898 56146 21134
-rect 56382 20898 91826 21134
-rect 92062 20898 92146 21134
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-rect 128062 20898 128146 21134
-rect 128382 20898 163826 21134
-rect 164062 20898 164146 21134
-rect 164382 20898 199826 21134
-rect 200062 20898 200146 21134
-rect 200382 20898 235826 21134
-rect 236062 20898 236146 21134
-rect 236382 20898 271826 21134
-rect 272062 20898 272146 21134
-rect 272382 20898 307826 21134
-rect 308062 20898 308146 21134
-rect 308382 20898 343826 21134
-rect 344062 20898 344146 21134
-rect 344382 20898 379826 21134
-rect 380062 20898 380146 21134
-rect 380382 20898 415826 21134
-rect 416062 20898 416146 21134
-rect 416382 20898 451826 21134
-rect 452062 20898 452146 21134
-rect 452382 20898 487826 21134
-rect 488062 20898 488146 21134
-rect 488382 20898 523826 21134
-rect 524062 20898 524146 21134
-rect 524382 20898 559826 21134
-rect 560062 20898 560146 21134
-rect 560382 20898 586302 21134
-rect 586538 20898 586622 21134
-rect 586858 20898 586890 21134
-rect -2966 20866 586890 20898
-rect -8726 14614 592650 14646
-rect -8726 14378 -7734 14614
-rect -7498 14378 -7414 14614
-rect -7178 14378 12986 14614
-rect 13222 14378 13306 14614
-rect 13542 14378 48986 14614
-rect 49222 14378 49306 14614
-rect 49542 14378 84986 14614
-rect 85222 14378 85306 14614
-rect 85542 14378 120986 14614
-rect 121222 14378 121306 14614
-rect 121542 14378 156986 14614
-rect 157222 14378 157306 14614
-rect 157542 14378 192986 14614
-rect 193222 14378 193306 14614
-rect 193542 14378 228986 14614
-rect 229222 14378 229306 14614
-rect 229542 14378 264986 14614
-rect 265222 14378 265306 14614
-rect 265542 14378 300986 14614
-rect 301222 14378 301306 14614
-rect 301542 14378 336986 14614
-rect 337222 14378 337306 14614
-rect 337542 14378 372986 14614
-rect 373222 14378 373306 14614
-rect 373542 14378 408986 14614
-rect 409222 14378 409306 14614
-rect 409542 14378 444986 14614
-rect 445222 14378 445306 14614
-rect 445542 14378 480986 14614
-rect 481222 14378 481306 14614
-rect 481542 14378 516986 14614
-rect 517222 14378 517306 14614
-rect 517542 14378 552986 14614
-rect 553222 14378 553306 14614
-rect 553542 14378 591102 14614
-rect 591338 14378 591422 14614
-rect 591658 14378 592650 14614
-rect -8726 14294 592650 14378
-rect -8726 14058 -7734 14294
-rect -7498 14058 -7414 14294
-rect -7178 14058 12986 14294
-rect 13222 14058 13306 14294
-rect 13542 14058 48986 14294
-rect 49222 14058 49306 14294
-rect 49542 14058 84986 14294
-rect 85222 14058 85306 14294
-rect 85542 14058 120986 14294
-rect 121222 14058 121306 14294
-rect 121542 14058 156986 14294
-rect 157222 14058 157306 14294
-rect 157542 14058 192986 14294
-rect 193222 14058 193306 14294
-rect 193542 14058 228986 14294
-rect 229222 14058 229306 14294
-rect 229542 14058 264986 14294
-rect 265222 14058 265306 14294
-rect 265542 14058 300986 14294
-rect 301222 14058 301306 14294
-rect 301542 14058 336986 14294
-rect 337222 14058 337306 14294
-rect 337542 14058 372986 14294
-rect 373222 14058 373306 14294
-rect 373542 14058 408986 14294
-rect 409222 14058 409306 14294
-rect 409542 14058 444986 14294
-rect 445222 14058 445306 14294
-rect 445542 14058 480986 14294
-rect 481222 14058 481306 14294
-rect 481542 14058 516986 14294
-rect 517222 14058 517306 14294
-rect 517542 14058 552986 14294
-rect 553222 14058 553306 14294
-rect 553542 14058 591102 14294
-rect 591338 14058 591422 14294
-rect 591658 14058 592650 14294
-rect -8726 14026 592650 14058
-rect -6806 10894 590730 10926
-rect -6806 10658 -5814 10894
-rect -5578 10658 -5494 10894
-rect -5258 10658 9266 10894
-rect 9502 10658 9586 10894
-rect 9822 10658 45266 10894
-rect 45502 10658 45586 10894
-rect 45822 10658 81266 10894
-rect 81502 10658 81586 10894
-rect 81822 10658 117266 10894
-rect 117502 10658 117586 10894
-rect 117822 10658 153266 10894
-rect 153502 10658 153586 10894
-rect 153822 10658 189266 10894
-rect 189502 10658 189586 10894
-rect 189822 10658 225266 10894
-rect 225502 10658 225586 10894
-rect 225822 10658 261266 10894
-rect 261502 10658 261586 10894
-rect 261822 10658 297266 10894
-rect 297502 10658 297586 10894
-rect 297822 10658 333266 10894
-rect 333502 10658 333586 10894
-rect 333822 10658 369266 10894
-rect 369502 10658 369586 10894
-rect 369822 10658 405266 10894
-rect 405502 10658 405586 10894
-rect 405822 10658 441266 10894
-rect 441502 10658 441586 10894
-rect 441822 10658 477266 10894
-rect 477502 10658 477586 10894
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-rect 513502 10658 513586 10894
-rect 513822 10658 549266 10894
-rect 549502 10658 549586 10894
-rect 549822 10658 589182 10894
-rect 589418 10658 589502 10894
-rect 589738 10658 590730 10894
-rect -6806 10574 590730 10658
-rect -6806 10338 -5814 10574
-rect -5578 10338 -5494 10574
-rect -5258 10338 9266 10574
-rect 9502 10338 9586 10574
-rect 9822 10338 45266 10574
-rect 45502 10338 45586 10574
-rect 45822 10338 81266 10574
-rect 81502 10338 81586 10574
-rect 81822 10338 117266 10574
-rect 117502 10338 117586 10574
-rect 117822 10338 153266 10574
-rect 153502 10338 153586 10574
-rect 153822 10338 189266 10574
-rect 189502 10338 189586 10574
-rect 189822 10338 225266 10574
-rect 225502 10338 225586 10574
-rect 225822 10338 261266 10574
-rect 261502 10338 261586 10574
-rect 261822 10338 297266 10574
-rect 297502 10338 297586 10574
-rect 297822 10338 333266 10574
-rect 333502 10338 333586 10574
-rect 333822 10338 369266 10574
-rect 369502 10338 369586 10574
-rect 369822 10338 405266 10574
-rect 405502 10338 405586 10574
-rect 405822 10338 441266 10574
-rect 441502 10338 441586 10574
-rect 441822 10338 477266 10574
-rect 477502 10338 477586 10574
-rect 477822 10338 513266 10574
-rect 513502 10338 513586 10574
-rect 513822 10338 549266 10574
-rect 549502 10338 549586 10574
-rect 549822 10338 589182 10574
-rect 589418 10338 589502 10574
-rect 589738 10338 590730 10574
-rect -6806 10306 590730 10338
-rect -4886 7174 588810 7206
-rect -4886 6938 -3894 7174
-rect -3658 6938 -3574 7174
-rect -3338 6938 5546 7174
-rect 5782 6938 5866 7174
-rect 6102 6938 41546 7174
-rect 41782 6938 41866 7174
-rect 42102 6938 77546 7174
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-rect 78102 6938 113546 7174
-rect 113782 6938 113866 7174
-rect 114102 6938 149546 7174
-rect 149782 6938 149866 7174
-rect 150102 6938 185546 7174
-rect 185782 6938 185866 7174
-rect 186102 6938 221546 7174
-rect 221782 6938 221866 7174
-rect 222102 6938 257546 7174
-rect 257782 6938 257866 7174
-rect 258102 6938 293546 7174
-rect 293782 6938 293866 7174
-rect 294102 6938 329546 7174
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-rect 330102 6938 365546 7174
-rect 365782 6938 365866 7174
-rect 366102 6938 401546 7174
-rect 401782 6938 401866 7174
-rect 402102 6938 437546 7174
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-rect 438102 6938 473546 7174
-rect 473782 6938 473866 7174
-rect 474102 6938 509546 7174
-rect 509782 6938 509866 7174
-rect 510102 6938 545546 7174
-rect 545782 6938 545866 7174
-rect 546102 6938 581546 7174
-rect 581782 6938 581866 7174
-rect 582102 6938 587262 7174
-rect 587498 6938 587582 7174
-rect 587818 6938 588810 7174
-rect -4886 6854 588810 6938
-rect -4886 6618 -3894 6854
-rect -3658 6618 -3574 6854
-rect -3338 6618 5546 6854
-rect 5782 6618 5866 6854
-rect 6102 6618 41546 6854
-rect 41782 6618 41866 6854
-rect 42102 6618 77546 6854
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-rect 78102 6618 113546 6854
-rect 113782 6618 113866 6854
-rect 114102 6618 149546 6854
-rect 149782 6618 149866 6854
-rect 150102 6618 185546 6854
-rect 185782 6618 185866 6854
-rect 186102 6618 221546 6854
-rect 221782 6618 221866 6854
-rect 222102 6618 257546 6854
-rect 257782 6618 257866 6854
-rect 258102 6618 293546 6854
-rect 293782 6618 293866 6854
-rect 294102 6618 329546 6854
-rect 329782 6618 329866 6854
-rect 330102 6618 365546 6854
-rect 365782 6618 365866 6854
-rect 366102 6618 401546 6854
-rect 401782 6618 401866 6854
-rect 402102 6618 437546 6854
-rect 437782 6618 437866 6854
-rect 438102 6618 473546 6854
-rect 473782 6618 473866 6854
-rect 474102 6618 509546 6854
-rect 509782 6618 509866 6854
-rect 510102 6618 545546 6854
-rect 545782 6618 545866 6854
-rect 546102 6618 581546 6854
-rect 581782 6618 581866 6854
-rect 582102 6618 587262 6854
-rect 587498 6618 587582 6854
-rect 587818 6618 588810 6854
-rect -4886 6586 588810 6618
-rect -2966 3454 586890 3486
-rect -2966 3218 -1974 3454
-rect -1738 3218 -1654 3454
-rect -1418 3218 1826 3454
-rect 2062 3218 2146 3454
-rect 2382 3218 37826 3454
-rect 38062 3218 38146 3454
-rect 38382 3218 73826 3454
-rect 74062 3218 74146 3454
-rect 74382 3218 109826 3454
-rect 110062 3218 110146 3454
-rect 110382 3218 145826 3454
-rect 146062 3218 146146 3454
-rect 146382 3218 181826 3454
-rect 182062 3218 182146 3454
-rect 182382 3218 217826 3454
-rect 218062 3218 218146 3454
-rect 218382 3218 253826 3454
-rect 254062 3218 254146 3454
-rect 254382 3218 289826 3454
-rect 290062 3218 290146 3454
-rect 290382 3218 325826 3454
-rect 326062 3218 326146 3454
-rect 326382 3218 361826 3454
-rect 362062 3218 362146 3454
-rect 362382 3218 397826 3454
-rect 398062 3218 398146 3454
-rect 398382 3218 433826 3454
-rect 434062 3218 434146 3454
-rect 434382 3218 469826 3454
-rect 470062 3218 470146 3454
-rect 470382 3218 505826 3454
-rect 506062 3218 506146 3454
-rect 506382 3218 541826 3454
-rect 542062 3218 542146 3454
-rect 542382 3218 577826 3454
-rect 578062 3218 578146 3454
-rect 578382 3218 585342 3454
-rect 585578 3218 585662 3454
-rect 585898 3218 586890 3454
-rect -2966 3134 586890 3218
-rect -2966 2898 -1974 3134
-rect -1738 2898 -1654 3134
-rect -1418 2898 1826 3134
-rect 2062 2898 2146 3134
-rect 2382 2898 37826 3134
-rect 38062 2898 38146 3134
-rect 38382 2898 73826 3134
-rect 74062 2898 74146 3134
-rect 74382 2898 109826 3134
-rect 110062 2898 110146 3134
-rect 110382 2898 145826 3134
-rect 146062 2898 146146 3134
-rect 146382 2898 181826 3134
-rect 182062 2898 182146 3134
-rect 182382 2898 217826 3134
-rect 218062 2898 218146 3134
-rect 218382 2898 253826 3134
-rect 254062 2898 254146 3134
-rect 254382 2898 289826 3134
-rect 290062 2898 290146 3134
-rect 290382 2898 325826 3134
-rect 326062 2898 326146 3134
-rect 326382 2898 361826 3134
-rect 362062 2898 362146 3134
-rect 362382 2898 397826 3134
-rect 398062 2898 398146 3134
-rect 398382 2898 433826 3134
-rect 434062 2898 434146 3134
-rect 434382 2898 469826 3134
-rect 470062 2898 470146 3134
-rect 470382 2898 505826 3134
-rect 506062 2898 506146 3134
-rect 506382 2898 541826 3134
-rect 542062 2898 542146 3134
-rect 542382 2898 577826 3134
-rect 578062 2898 578146 3134
-rect 578382 2898 585342 3134
-rect 585578 2898 585662 3134
-rect 585898 2898 586890 3134
-rect -2966 2866 586890 2898
-rect -2006 -346 585930 -314
-rect -2006 -582 -1974 -346
-rect -1738 -582 -1654 -346
-rect -1418 -582 1826 -346
-rect 2062 -582 2146 -346
-rect 2382 -582 37826 -346
-rect 38062 -582 38146 -346
-rect 38382 -582 73826 -346
-rect 74062 -582 74146 -346
-rect 74382 -582 109826 -346
-rect 110062 -582 110146 -346
-rect 110382 -582 145826 -346
-rect 146062 -582 146146 -346
-rect 146382 -582 181826 -346
-rect 182062 -582 182146 -346
-rect 182382 -582 217826 -346
-rect 218062 -582 218146 -346
-rect 218382 -582 253826 -346
-rect 254062 -582 254146 -346
-rect 254382 -582 289826 -346
-rect 290062 -582 290146 -346
-rect 290382 -582 325826 -346
-rect 326062 -582 326146 -346
-rect 326382 -582 361826 -346
-rect 362062 -582 362146 -346
-rect 362382 -582 397826 -346
-rect 398062 -582 398146 -346
-rect 398382 -582 433826 -346
-rect 434062 -582 434146 -346
-rect 434382 -582 469826 -346
-rect 470062 -582 470146 -346
-rect 470382 -582 505826 -346
-rect 506062 -582 506146 -346
-rect 506382 -582 541826 -346
-rect 542062 -582 542146 -346
-rect 542382 -582 577826 -346
-rect 578062 -582 578146 -346
-rect 578382 -582 585342 -346
-rect 585578 -582 585662 -346
-rect 585898 -582 585930 -346
-rect -2006 -666 585930 -582
-rect -2006 -902 -1974 -666
-rect -1738 -902 -1654 -666
-rect -1418 -902 1826 -666
-rect 2062 -902 2146 -666
-rect 2382 -902 37826 -666
-rect 38062 -902 38146 -666
-rect 38382 -902 73826 -666
-rect 74062 -902 74146 -666
-rect 74382 -902 109826 -666
-rect 110062 -902 110146 -666
-rect 110382 -902 145826 -666
-rect 146062 -902 146146 -666
-rect 146382 -902 181826 -666
-rect 182062 -902 182146 -666
-rect 182382 -902 217826 -666
-rect 218062 -902 218146 -666
-rect 218382 -902 253826 -666
-rect 254062 -902 254146 -666
-rect 254382 -902 289826 -666
-rect 290062 -902 290146 -666
-rect 290382 -902 325826 -666
-rect 326062 -902 326146 -666
-rect 326382 -902 361826 -666
-rect 362062 -902 362146 -666
-rect 362382 -902 397826 -666
-rect 398062 -902 398146 -666
-rect 398382 -902 433826 -666
-rect 434062 -902 434146 -666
-rect 434382 -902 469826 -666
-rect 470062 -902 470146 -666
-rect 470382 -902 505826 -666
-rect 506062 -902 506146 -666
-rect 506382 -902 541826 -666
-rect 542062 -902 542146 -666
-rect 542382 -902 577826 -666
-rect 578062 -902 578146 -666
-rect 578382 -902 585342 -666
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-rect 585898 -902 585930 -666
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-rect -2378 -1542 19826 -1306
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-rect 56382 -1542 91826 -1306
-rect 92062 -1542 92146 -1306
-rect 92382 -1542 127826 -1306
-rect 128062 -1542 128146 -1306
-rect 128382 -1542 163826 -1306
-rect 164062 -1542 164146 -1306
-rect 164382 -1542 199826 -1306
-rect 200062 -1542 200146 -1306
-rect 200382 -1542 235826 -1306
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-rect 236382 -1542 271826 -1306
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-rect 272382 -1542 307826 -1306
-rect 308062 -1542 308146 -1306
-rect 308382 -1542 343826 -1306
-rect 344062 -1542 344146 -1306
-rect 344382 -1542 379826 -1306
-rect 380062 -1542 380146 -1306
-rect 380382 -1542 415826 -1306
-rect 416062 -1542 416146 -1306
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-rect 452062 -1542 452146 -1306
-rect 452382 -1542 487826 -1306
-rect 488062 -1542 488146 -1306
-rect 488382 -1542 523826 -1306
-rect 524062 -1542 524146 -1306
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-rect 560062 -1542 560146 -1306
-rect 560382 -1542 586302 -1306
-rect 586538 -1542 586622 -1306
-rect 586858 -1542 586890 -1306
-rect -2966 -1626 586890 -1542
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-rect -2698 -1862 -2614 -1626
-rect -2378 -1862 19826 -1626
-rect 20062 -1862 20146 -1626
-rect 20382 -1862 55826 -1626
-rect 56062 -1862 56146 -1626
-rect 56382 -1862 91826 -1626
-rect 92062 -1862 92146 -1626
-rect 92382 -1862 127826 -1626
-rect 128062 -1862 128146 -1626
-rect 128382 -1862 163826 -1626
-rect 164062 -1862 164146 -1626
-rect 164382 -1862 199826 -1626
-rect 200062 -1862 200146 -1626
-rect 200382 -1862 235826 -1626
-rect 236062 -1862 236146 -1626
-rect 236382 -1862 271826 -1626
-rect 272062 -1862 272146 -1626
-rect 272382 -1862 307826 -1626
-rect 308062 -1862 308146 -1626
-rect 308382 -1862 343826 -1626
-rect 344062 -1862 344146 -1626
-rect 344382 -1862 379826 -1626
-rect 380062 -1862 380146 -1626
-rect 380382 -1862 415826 -1626
-rect 416062 -1862 416146 -1626
-rect 416382 -1862 451826 -1626
-rect 452062 -1862 452146 -1626
-rect 452382 -1862 487826 -1626
-rect 488062 -1862 488146 -1626
-rect 488382 -1862 523826 -1626
-rect 524062 -1862 524146 -1626
-rect 524382 -1862 559826 -1626
-rect 560062 -1862 560146 -1626
-rect 560382 -1862 586302 -1626
-rect 586538 -1862 586622 -1626
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-rect -2966 -1894 586890 -1862
-rect -3926 -2266 587850 -2234
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-rect -3338 -2502 5546 -2266
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-rect 6102 -2502 41546 -2266
-rect 41782 -2502 41866 -2266
-rect 42102 -2502 77546 -2266
-rect 77782 -2502 77866 -2266
-rect 78102 -2502 113546 -2266
-rect 113782 -2502 113866 -2266
-rect 114102 -2502 149546 -2266
-rect 149782 -2502 149866 -2266
-rect 150102 -2502 185546 -2266
-rect 185782 -2502 185866 -2266
-rect 186102 -2502 221546 -2266
-rect 221782 -2502 221866 -2266
-rect 222102 -2502 257546 -2266
-rect 257782 -2502 257866 -2266
-rect 258102 -2502 293546 -2266
-rect 293782 -2502 293866 -2266
-rect 294102 -2502 329546 -2266
-rect 329782 -2502 329866 -2266
-rect 330102 -2502 365546 -2266
-rect 365782 -2502 365866 -2266
-rect 366102 -2502 401546 -2266
-rect 401782 -2502 401866 -2266
-rect 402102 -2502 437546 -2266
-rect 437782 -2502 437866 -2266
-rect 438102 -2502 473546 -2266
-rect 473782 -2502 473866 -2266
-rect 474102 -2502 509546 -2266
-rect 509782 -2502 509866 -2266
-rect 510102 -2502 545546 -2266
-rect 545782 -2502 545866 -2266
-rect 546102 -2502 581546 -2266
-rect 581782 -2502 581866 -2266
-rect 582102 -2502 587262 -2266
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-rect -3926 -2822 -3894 -2586
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-rect -3338 -2822 5546 -2586
-rect 5782 -2822 5866 -2586
-rect 6102 -2822 41546 -2586
-rect 41782 -2822 41866 -2586
-rect 42102 -2822 77546 -2586
-rect 77782 -2822 77866 -2586
-rect 78102 -2822 113546 -2586
-rect 113782 -2822 113866 -2586
-rect 114102 -2822 149546 -2586
-rect 149782 -2822 149866 -2586
-rect 150102 -2822 185546 -2586
-rect 185782 -2822 185866 -2586
-rect 186102 -2822 221546 -2586
-rect 221782 -2822 221866 -2586
-rect 222102 -2822 257546 -2586
-rect 257782 -2822 257866 -2586
-rect 258102 -2822 293546 -2586
-rect 293782 -2822 293866 -2586
-rect 294102 -2822 329546 -2586
-rect 329782 -2822 329866 -2586
-rect 330102 -2822 365546 -2586
-rect 365782 -2822 365866 -2586
-rect 366102 -2822 401546 -2586
-rect 401782 -2822 401866 -2586
-rect 402102 -2822 437546 -2586
-rect 437782 -2822 437866 -2586
-rect 438102 -2822 473546 -2586
-rect 473782 -2822 473866 -2586
-rect 474102 -2822 509546 -2586
-rect 509782 -2822 509866 -2586
-rect 510102 -2822 545546 -2586
-rect 545782 -2822 545866 -2586
-rect 546102 -2822 581546 -2586
-rect 581782 -2822 581866 -2586
-rect 582102 -2822 587262 -2586
-rect 587498 -2822 587582 -2586
-rect 587818 -2822 587850 -2586
-rect -3926 -2854 587850 -2822
-rect -4886 -3226 588810 -3194
-rect -4886 -3462 -4854 -3226
-rect -4618 -3462 -4534 -3226
-rect -4298 -3462 23546 -3226
-rect 23782 -3462 23866 -3226
-rect 24102 -3462 59546 -3226
-rect 59782 -3462 59866 -3226
-rect 60102 -3462 95546 -3226
-rect 95782 -3462 95866 -3226
-rect 96102 -3462 131546 -3226
-rect 131782 -3462 131866 -3226
-rect 132102 -3462 167546 -3226
-rect 167782 -3462 167866 -3226
-rect 168102 -3462 203546 -3226
-rect 203782 -3462 203866 -3226
-rect 204102 -3462 239546 -3226
-rect 239782 -3462 239866 -3226
-rect 240102 -3462 275546 -3226
-rect 275782 -3462 275866 -3226
-rect 276102 -3462 311546 -3226
-rect 311782 -3462 311866 -3226
-rect 312102 -3462 347546 -3226
-rect 347782 -3462 347866 -3226
-rect 348102 -3462 383546 -3226
-rect 383782 -3462 383866 -3226
-rect 384102 -3462 419546 -3226
-rect 419782 -3462 419866 -3226
-rect 420102 -3462 455546 -3226
-rect 455782 -3462 455866 -3226
-rect 456102 -3462 491546 -3226
-rect 491782 -3462 491866 -3226
-rect 492102 -3462 527546 -3226
-rect 527782 -3462 527866 -3226
-rect 528102 -3462 563546 -3226
-rect 563782 -3462 563866 -3226
-rect 564102 -3462 588222 -3226
-rect 588458 -3462 588542 -3226
-rect 588778 -3462 588810 -3226
-rect -4886 -3546 588810 -3462
-rect -4886 -3782 -4854 -3546
-rect -4618 -3782 -4534 -3546
-rect -4298 -3782 23546 -3546
-rect 23782 -3782 23866 -3546
-rect 24102 -3782 59546 -3546
-rect 59782 -3782 59866 -3546
-rect 60102 -3782 95546 -3546
-rect 95782 -3782 95866 -3546
-rect 96102 -3782 131546 -3546
-rect 131782 -3782 131866 -3546
-rect 132102 -3782 167546 -3546
-rect 167782 -3782 167866 -3546
-rect 168102 -3782 203546 -3546
-rect 203782 -3782 203866 -3546
-rect 204102 -3782 239546 -3546
-rect 239782 -3782 239866 -3546
-rect 240102 -3782 275546 -3546
-rect 275782 -3782 275866 -3546
-rect 276102 -3782 311546 -3546
-rect 311782 -3782 311866 -3546
-rect 312102 -3782 347546 -3546
-rect 347782 -3782 347866 -3546
-rect 348102 -3782 383546 -3546
-rect 383782 -3782 383866 -3546
-rect 384102 -3782 419546 -3546
-rect 419782 -3782 419866 -3546
-rect 420102 -3782 455546 -3546
-rect 455782 -3782 455866 -3546
-rect 456102 -3782 491546 -3546
-rect 491782 -3782 491866 -3546
-rect 492102 -3782 527546 -3546
-rect 527782 -3782 527866 -3546
-rect 528102 -3782 563546 -3546
-rect 563782 -3782 563866 -3546
-rect 564102 -3782 588222 -3546
-rect 588458 -3782 588542 -3546
-rect 588778 -3782 588810 -3546
-rect -4886 -3814 588810 -3782
-rect -5846 -4186 589770 -4154
-rect -5846 -4422 -5814 -4186
-rect -5578 -4422 -5494 -4186
-rect -5258 -4422 9266 -4186
-rect 9502 -4422 9586 -4186
-rect 9822 -4422 45266 -4186
-rect 45502 -4422 45586 -4186
-rect 45822 -4422 81266 -4186
-rect 81502 -4422 81586 -4186
-rect 81822 -4422 117266 -4186
-rect 117502 -4422 117586 -4186
-rect 117822 -4422 153266 -4186
-rect 153502 -4422 153586 -4186
-rect 153822 -4422 189266 -4186
-rect 189502 -4422 189586 -4186
-rect 189822 -4422 225266 -4186
-rect 225502 -4422 225586 -4186
-rect 225822 -4422 261266 -4186
-rect 261502 -4422 261586 -4186
-rect 261822 -4422 297266 -4186
-rect 297502 -4422 297586 -4186
-rect 297822 -4422 333266 -4186
-rect 333502 -4422 333586 -4186
-rect 333822 -4422 369266 -4186
-rect 369502 -4422 369586 -4186
-rect 369822 -4422 405266 -4186
-rect 405502 -4422 405586 -4186
-rect 405822 -4422 441266 -4186
-rect 441502 -4422 441586 -4186
-rect 441822 -4422 477266 -4186
-rect 477502 -4422 477586 -4186
-rect 477822 -4422 513266 -4186
-rect 513502 -4422 513586 -4186
-rect 513822 -4422 549266 -4186
-rect 549502 -4422 549586 -4186
-rect 549822 -4422 589182 -4186
-rect 589418 -4422 589502 -4186
-rect 589738 -4422 589770 -4186
-rect -5846 -4506 589770 -4422
-rect -5846 -4742 -5814 -4506
-rect -5578 -4742 -5494 -4506
-rect -5258 -4742 9266 -4506
-rect 9502 -4742 9586 -4506
-rect 9822 -4742 45266 -4506
-rect 45502 -4742 45586 -4506
-rect 45822 -4742 81266 -4506
-rect 81502 -4742 81586 -4506
-rect 81822 -4742 117266 -4506
-rect 117502 -4742 117586 -4506
-rect 117822 -4742 153266 -4506
-rect 153502 -4742 153586 -4506
-rect 153822 -4742 189266 -4506
-rect 189502 -4742 189586 -4506
-rect 189822 -4742 225266 -4506
-rect 225502 -4742 225586 -4506
-rect 225822 -4742 261266 -4506
-rect 261502 -4742 261586 -4506
-rect 261822 -4742 297266 -4506
-rect 297502 -4742 297586 -4506
-rect 297822 -4742 333266 -4506
-rect 333502 -4742 333586 -4506
-rect 333822 -4742 369266 -4506
-rect 369502 -4742 369586 -4506
-rect 369822 -4742 405266 -4506
-rect 405502 -4742 405586 -4506
-rect 405822 -4742 441266 -4506
-rect 441502 -4742 441586 -4506
-rect 441822 -4742 477266 -4506
-rect 477502 -4742 477586 -4506
-rect 477822 -4742 513266 -4506
-rect 513502 -4742 513586 -4506
-rect 513822 -4742 549266 -4506
-rect 549502 -4742 549586 -4506
-rect 549822 -4742 589182 -4506
-rect 589418 -4742 589502 -4506
-rect 589738 -4742 589770 -4506
-rect -5846 -4774 589770 -4742
-rect -6806 -5146 590730 -5114
-rect -6806 -5382 -6774 -5146
-rect -6538 -5382 -6454 -5146
-rect -6218 -5382 27266 -5146
-rect 27502 -5382 27586 -5146
-rect 27822 -5382 63266 -5146
-rect 63502 -5382 63586 -5146
-rect 63822 -5382 99266 -5146
-rect 99502 -5382 99586 -5146
-rect 99822 -5382 135266 -5146
-rect 135502 -5382 135586 -5146
-rect 135822 -5382 171266 -5146
-rect 171502 -5382 171586 -5146
-rect 171822 -5382 207266 -5146
-rect 207502 -5382 207586 -5146
-rect 207822 -5382 243266 -5146
-rect 243502 -5382 243586 -5146
-rect 243822 -5382 279266 -5146
-rect 279502 -5382 279586 -5146
-rect 279822 -5382 315266 -5146
-rect 315502 -5382 315586 -5146
-rect 315822 -5382 351266 -5146
-rect 351502 -5382 351586 -5146
-rect 351822 -5382 387266 -5146
-rect 387502 -5382 387586 -5146
-rect 387822 -5382 423266 -5146
-rect 423502 -5382 423586 -5146
-rect 423822 -5382 459266 -5146
-rect 459502 -5382 459586 -5146
-rect 459822 -5382 495266 -5146
-rect 495502 -5382 495586 -5146
-rect 495822 -5382 531266 -5146
-rect 531502 -5382 531586 -5146
-rect 531822 -5382 567266 -5146
-rect 567502 -5382 567586 -5146
-rect 567822 -5382 590142 -5146
-rect 590378 -5382 590462 -5146
-rect 590698 -5382 590730 -5146
-rect -6806 -5466 590730 -5382
-rect -6806 -5702 -6774 -5466
-rect -6538 -5702 -6454 -5466
-rect -6218 -5702 27266 -5466
-rect 27502 -5702 27586 -5466
-rect 27822 -5702 63266 -5466
-rect 63502 -5702 63586 -5466
-rect 63822 -5702 99266 -5466
-rect 99502 -5702 99586 -5466
-rect 99822 -5702 135266 -5466
-rect 135502 -5702 135586 -5466
-rect 135822 -5702 171266 -5466
-rect 171502 -5702 171586 -5466
-rect 171822 -5702 207266 -5466
-rect 207502 -5702 207586 -5466
-rect 207822 -5702 243266 -5466
-rect 243502 -5702 243586 -5466
-rect 243822 -5702 279266 -5466
-rect 279502 -5702 279586 -5466
-rect 279822 -5702 315266 -5466
-rect 315502 -5702 315586 -5466
-rect 315822 -5702 351266 -5466
-rect 351502 -5702 351586 -5466
-rect 351822 -5702 387266 -5466
-rect 387502 -5702 387586 -5466
-rect 387822 -5702 423266 -5466
-rect 423502 -5702 423586 -5466
-rect 423822 -5702 459266 -5466
-rect 459502 -5702 459586 -5466
-rect 459822 -5702 495266 -5466
-rect 495502 -5702 495586 -5466
-rect 495822 -5702 531266 -5466
-rect 531502 -5702 531586 -5466
-rect 531822 -5702 567266 -5466
-rect 567502 -5702 567586 -5466
-rect 567822 -5702 590142 -5466
-rect 590378 -5702 590462 -5466
-rect 590698 -5702 590730 -5466
-rect -6806 -5734 590730 -5702
-rect -7766 -6106 591690 -6074
-rect -7766 -6342 -7734 -6106
-rect -7498 -6342 -7414 -6106
-rect -7178 -6342 12986 -6106
-rect 13222 -6342 13306 -6106
-rect 13542 -6342 48986 -6106
-rect 49222 -6342 49306 -6106
-rect 49542 -6342 84986 -6106
-rect 85222 -6342 85306 -6106
-rect 85542 -6342 120986 -6106
-rect 121222 -6342 121306 -6106
-rect 121542 -6342 156986 -6106
-rect 157222 -6342 157306 -6106
-rect 157542 -6342 192986 -6106
-rect 193222 -6342 193306 -6106
-rect 193542 -6342 228986 -6106
-rect 229222 -6342 229306 -6106
-rect 229542 -6342 264986 -6106
-rect 265222 -6342 265306 -6106
-rect 265542 -6342 300986 -6106
-rect 301222 -6342 301306 -6106
-rect 301542 -6342 336986 -6106
-rect 337222 -6342 337306 -6106
-rect 337542 -6342 372986 -6106
-rect 373222 -6342 373306 -6106
-rect 373542 -6342 408986 -6106
-rect 409222 -6342 409306 -6106
-rect 409542 -6342 444986 -6106
-rect 445222 -6342 445306 -6106
-rect 445542 -6342 480986 -6106
-rect 481222 -6342 481306 -6106
-rect 481542 -6342 516986 -6106
-rect 517222 -6342 517306 -6106
-rect 517542 -6342 552986 -6106
-rect 553222 -6342 553306 -6106
-rect 553542 -6342 591102 -6106
-rect 591338 -6342 591422 -6106
-rect 591658 -6342 591690 -6106
-rect -7766 -6426 591690 -6342
-rect -7766 -6662 -7734 -6426
-rect -7498 -6662 -7414 -6426
-rect -7178 -6662 12986 -6426
-rect 13222 -6662 13306 -6426
-rect 13542 -6662 48986 -6426
-rect 49222 -6662 49306 -6426
-rect 49542 -6662 84986 -6426
-rect 85222 -6662 85306 -6426
-rect 85542 -6662 120986 -6426
-rect 121222 -6662 121306 -6426
-rect 121542 -6662 156986 -6426
-rect 157222 -6662 157306 -6426
-rect 157542 -6662 192986 -6426
-rect 193222 -6662 193306 -6426
-rect 193542 -6662 228986 -6426
-rect 229222 -6662 229306 -6426
-rect 229542 -6662 264986 -6426
-rect 265222 -6662 265306 -6426
-rect 265542 -6662 300986 -6426
-rect 301222 -6662 301306 -6426
-rect 301542 -6662 336986 -6426
-rect 337222 -6662 337306 -6426
-rect 337542 -6662 372986 -6426
-rect 373222 -6662 373306 -6426
-rect 373542 -6662 408986 -6426
-rect 409222 -6662 409306 -6426
-rect 409542 -6662 444986 -6426
-rect 445222 -6662 445306 -6426
-rect 445542 -6662 480986 -6426
-rect 481222 -6662 481306 -6426
-rect 481542 -6662 516986 -6426
-rect 517222 -6662 517306 -6426
-rect 517542 -6662 552986 -6426
-rect 553222 -6662 553306 -6426
-rect 553542 -6662 591102 -6426
-rect 591338 -6662 591422 -6426
-rect 591658 -6662 591690 -6426
-rect -7766 -6694 591690 -6662
-rect -8726 -7066 592650 -7034
-rect -8726 -7302 -8694 -7066
-rect -8458 -7302 -8374 -7066
-rect -8138 -7302 30986 -7066
-rect 31222 -7302 31306 -7066
-rect 31542 -7302 66986 -7066
-rect 67222 -7302 67306 -7066
-rect 67542 -7302 102986 -7066
-rect 103222 -7302 103306 -7066
-rect 103542 -7302 138986 -7066
-rect 139222 -7302 139306 -7066
-rect 139542 -7302 174986 -7066
-rect 175222 -7302 175306 -7066
-rect 175542 -7302 210986 -7066
-rect 211222 -7302 211306 -7066
-rect 211542 -7302 246986 -7066
-rect 247222 -7302 247306 -7066
-rect 247542 -7302 282986 -7066
-rect 283222 -7302 283306 -7066
-rect 283542 -7302 318986 -7066
-rect 319222 -7302 319306 -7066
-rect 319542 -7302 354986 -7066
-rect 355222 -7302 355306 -7066
-rect 355542 -7302 390986 -7066
-rect 391222 -7302 391306 -7066
-rect 391542 -7302 426986 -7066
-rect 427222 -7302 427306 -7066
-rect 427542 -7302 462986 -7066
-rect 463222 -7302 463306 -7066
-rect 463542 -7302 498986 -7066
-rect 499222 -7302 499306 -7066
-rect 499542 -7302 534986 -7066
-rect 535222 -7302 535306 -7066
-rect 535542 -7302 570986 -7066
-rect 571222 -7302 571306 -7066
-rect 571542 -7302 592062 -7066
-rect 592298 -7302 592382 -7066
-rect 592618 -7302 592650 -7066
-rect -8726 -7386 592650 -7302
-rect -8726 -7622 -8694 -7386
-rect -8458 -7622 -8374 -7386
-rect -8138 -7622 30986 -7386
-rect 31222 -7622 31306 -7386
-rect 31542 -7622 66986 -7386
-rect 67222 -7622 67306 -7386
-rect 67542 -7622 102986 -7386
-rect 103222 -7622 103306 -7386
-rect 103542 -7622 138986 -7386
-rect 139222 -7622 139306 -7386
-rect 139542 -7622 174986 -7386
-rect 175222 -7622 175306 -7386
-rect 175542 -7622 210986 -7386
-rect 211222 -7622 211306 -7386
-rect 211542 -7622 246986 -7386
-rect 247222 -7622 247306 -7386
-rect 247542 -7622 282986 -7386
-rect 283222 -7622 283306 -7386
-rect 283542 -7622 318986 -7386
-rect 319222 -7622 319306 -7386
-rect 319542 -7622 354986 -7386
-rect 355222 -7622 355306 -7386
-rect 355542 -7622 390986 -7386
-rect 391222 -7622 391306 -7386
-rect 391542 -7622 426986 -7386
-rect 427222 -7622 427306 -7386
-rect 427542 -7622 462986 -7386
-rect 463222 -7622 463306 -7386
-rect 463542 -7622 498986 -7386
-rect 499222 -7622 499306 -7386
-rect 499542 -7622 534986 -7386
-rect 535222 -7622 535306 -7386
-rect 535542 -7622 570986 -7386
-rect 571222 -7622 571306 -7386
-rect 571542 -7622 592062 -7386
-rect 592298 -7622 592382 -7386
-rect 592618 -7622 592650 -7386
-rect -8726 -7654 592650 -7622
-use user_proj_example  mprj
-timestamp 1631895074
-transform 1 0 235000 0 1 338000
-box 106 0 179846 120000
-<< labels >>
-rlabel metal3 s 583520 285276 584960 285516 6 analog_io[0]
-port 0 nsew signal bidirectional
-rlabel metal2 s 446098 703520 446210 704960 6 analog_io[10]
-port 1 nsew signal bidirectional
-rlabel metal2 s 381146 703520 381258 704960 6 analog_io[11]
-port 2 nsew signal bidirectional
-rlabel metal2 s 316286 703520 316398 704960 6 analog_io[12]
-port 3 nsew signal bidirectional
-rlabel metal2 s 251426 703520 251538 704960 6 analog_io[13]
-port 4 nsew signal bidirectional
-rlabel metal2 s 186474 703520 186586 704960 6 analog_io[14]
-port 5 nsew signal bidirectional
-rlabel metal2 s 121614 703520 121726 704960 6 analog_io[15]
-port 6 nsew signal bidirectional
-rlabel metal2 s 56754 703520 56866 704960 6 analog_io[16]
-port 7 nsew signal bidirectional
-rlabel metal3 s -960 697220 480 697460 4 analog_io[17]
-port 8 nsew signal bidirectional
-rlabel metal3 s -960 644996 480 645236 4 analog_io[18]
-port 9 nsew signal bidirectional
-rlabel metal3 s -960 592908 480 593148 4 analog_io[19]
-port 10 nsew signal bidirectional
-rlabel metal3 s 583520 338452 584960 338692 6 analog_io[1]
-port 11 nsew signal bidirectional
-rlabel metal3 s -960 540684 480 540924 4 analog_io[20]
-port 12 nsew signal bidirectional
-rlabel metal3 s -960 488596 480 488836 4 analog_io[21]
-port 13 nsew signal bidirectional
-rlabel metal3 s -960 436508 480 436748 4 analog_io[22]
-port 14 nsew signal bidirectional
-rlabel metal3 s -960 384284 480 384524 4 analog_io[23]
-port 15 nsew signal bidirectional
-rlabel metal3 s -960 332196 480 332436 4 analog_io[24]
-port 16 nsew signal bidirectional
-rlabel metal3 s -960 279972 480 280212 4 analog_io[25]
-port 17 nsew signal bidirectional
-rlabel metal3 s -960 227884 480 228124 4 analog_io[26]
-port 18 nsew signal bidirectional
-rlabel metal3 s -960 175796 480 176036 4 analog_io[27]
-port 19 nsew signal bidirectional
-rlabel metal3 s -960 123572 480 123812 4 analog_io[28]
-port 20 nsew signal bidirectional
-rlabel metal3 s 583520 391628 584960 391868 6 analog_io[2]
-port 21 nsew signal bidirectional
-rlabel metal3 s 583520 444668 584960 444908 6 analog_io[3]
-port 22 nsew signal bidirectional
-rlabel metal3 s 583520 497844 584960 498084 6 analog_io[4]
-port 23 nsew signal bidirectional
-rlabel metal3 s 583520 551020 584960 551260 6 analog_io[5]
-port 24 nsew signal bidirectional
-rlabel metal3 s 583520 604060 584960 604300 6 analog_io[6]
-port 25 nsew signal bidirectional
-rlabel metal3 s 583520 657236 584960 657476 6 analog_io[7]
-port 26 nsew signal bidirectional
-rlabel metal2 s 575818 703520 575930 704960 6 analog_io[8]
-port 27 nsew signal bidirectional
-rlabel metal2 s 510958 703520 511070 704960 6 analog_io[9]
-port 28 nsew signal bidirectional
-rlabel metal3 s 583520 6476 584960 6716 6 io_in[0]
-port 29 nsew signal input
-rlabel metal3 s 583520 457996 584960 458236 6 io_in[10]
-port 30 nsew signal input
-rlabel metal3 s 583520 511172 584960 511412 6 io_in[11]
-port 31 nsew signal input
-rlabel metal3 s 583520 564212 584960 564452 6 io_in[12]
-port 32 nsew signal input
-rlabel metal3 s 583520 617388 584960 617628 6 io_in[13]
-port 33 nsew signal input
-rlabel metal3 s 583520 670564 584960 670804 6 io_in[14]
-port 34 nsew signal input
-rlabel metal2 s 559626 703520 559738 704960 6 io_in[15]
-port 35 nsew signal input
-rlabel metal2 s 494766 703520 494878 704960 6 io_in[16]
-port 36 nsew signal input
-rlabel metal2 s 429814 703520 429926 704960 6 io_in[17]
-port 37 nsew signal input
-rlabel metal2 s 364954 703520 365066 704960 6 io_in[18]
-port 38 nsew signal input
-rlabel metal2 s 300094 703520 300206 704960 6 io_in[19]
-port 39 nsew signal input
-rlabel metal3 s 583520 46188 584960 46428 6 io_in[1]
-port 40 nsew signal input
-rlabel metal2 s 235142 703520 235254 704960 6 io_in[20]
-port 41 nsew signal input
-rlabel metal2 s 170282 703520 170394 704960 6 io_in[21]
-port 42 nsew signal input
-rlabel metal2 s 105422 703520 105534 704960 6 io_in[22]
-port 43 nsew signal input
-rlabel metal2 s 40470 703520 40582 704960 6 io_in[23]
-port 44 nsew signal input
-rlabel metal3 s -960 684164 480 684404 4 io_in[24]
-port 45 nsew signal input
-rlabel metal3 s -960 631940 480 632180 4 io_in[25]
-port 46 nsew signal input
-rlabel metal3 s -960 579852 480 580092 4 io_in[26]
-port 47 nsew signal input
-rlabel metal3 s -960 527764 480 528004 4 io_in[27]
-port 48 nsew signal input
-rlabel metal3 s -960 475540 480 475780 4 io_in[28]
-port 49 nsew signal input
-rlabel metal3 s -960 423452 480 423692 4 io_in[29]
-port 50 nsew signal input
-rlabel metal3 s 583520 86036 584960 86276 6 io_in[2]
-port 51 nsew signal input
-rlabel metal3 s -960 371228 480 371468 4 io_in[30]
-port 52 nsew signal input
-rlabel metal3 s -960 319140 480 319380 4 io_in[31]
-port 53 nsew signal input
-rlabel metal3 s -960 267052 480 267292 4 io_in[32]
-port 54 nsew signal input
-rlabel metal3 s -960 214828 480 215068 4 io_in[33]
-port 55 nsew signal input
-rlabel metal3 s -960 162740 480 162980 4 io_in[34]
-port 56 nsew signal input
-rlabel metal3 s -960 110516 480 110756 4 io_in[35]
-port 57 nsew signal input
-rlabel metal3 s -960 71484 480 71724 4 io_in[36]
-port 58 nsew signal input
-rlabel metal3 s -960 32316 480 32556 4 io_in[37]
-port 59 nsew signal input
-rlabel metal3 s 583520 125884 584960 126124 6 io_in[3]
-port 60 nsew signal input
-rlabel metal3 s 583520 165732 584960 165972 6 io_in[4]
-port 61 nsew signal input
-rlabel metal3 s 583520 205580 584960 205820 6 io_in[5]
-port 62 nsew signal input
-rlabel metal3 s 583520 245428 584960 245668 6 io_in[6]
-port 63 nsew signal input
-rlabel metal3 s 583520 298604 584960 298844 6 io_in[7]
-port 64 nsew signal input
-rlabel metal3 s 583520 351780 584960 352020 6 io_in[8]
-port 65 nsew signal input
-rlabel metal3 s 583520 404820 584960 405060 6 io_in[9]
-port 66 nsew signal input
-rlabel metal3 s 583520 32996 584960 33236 6 io_oeb[0]
-port 67 nsew signal tristate
-rlabel metal3 s 583520 484516 584960 484756 6 io_oeb[10]
-port 68 nsew signal tristate
-rlabel metal3 s 583520 537692 584960 537932 6 io_oeb[11]
-port 69 nsew signal tristate
-rlabel metal3 s 583520 590868 584960 591108 6 io_oeb[12]
-port 70 nsew signal tristate
-rlabel metal3 s 583520 643908 584960 644148 6 io_oeb[13]
-port 71 nsew signal tristate
-rlabel metal3 s 583520 697084 584960 697324 6 io_oeb[14]
-port 72 nsew signal tristate
-rlabel metal2 s 527150 703520 527262 704960 6 io_oeb[15]
-port 73 nsew signal tristate
-rlabel metal2 s 462290 703520 462402 704960 6 io_oeb[16]
-port 74 nsew signal tristate
-rlabel metal2 s 397430 703520 397542 704960 6 io_oeb[17]
-port 75 nsew signal tristate
-rlabel metal2 s 332478 703520 332590 704960 6 io_oeb[18]
-port 76 nsew signal tristate
-rlabel metal2 s 267618 703520 267730 704960 6 io_oeb[19]
-port 77 nsew signal tristate
-rlabel metal3 s 583520 72844 584960 73084 6 io_oeb[1]
-port 78 nsew signal tristate
-rlabel metal2 s 202758 703520 202870 704960 6 io_oeb[20]
-port 79 nsew signal tristate
-rlabel metal2 s 137806 703520 137918 704960 6 io_oeb[21]
-port 80 nsew signal tristate
-rlabel metal2 s 72946 703520 73058 704960 6 io_oeb[22]
-port 81 nsew signal tristate
-rlabel metal2 s 8086 703520 8198 704960 6 io_oeb[23]
-port 82 nsew signal tristate
-rlabel metal3 s -960 658052 480 658292 4 io_oeb[24]
-port 83 nsew signal tristate
-rlabel metal3 s -960 605964 480 606204 4 io_oeb[25]
-port 84 nsew signal tristate
-rlabel metal3 s -960 553740 480 553980 4 io_oeb[26]
-port 85 nsew signal tristate
-rlabel metal3 s -960 501652 480 501892 4 io_oeb[27]
-port 86 nsew signal tristate
-rlabel metal3 s -960 449428 480 449668 4 io_oeb[28]
-port 87 nsew signal tristate
-rlabel metal3 s -960 397340 480 397580 4 io_oeb[29]
-port 88 nsew signal tristate
-rlabel metal3 s 583520 112692 584960 112932 6 io_oeb[2]
-port 89 nsew signal tristate
-rlabel metal3 s -960 345252 480 345492 4 io_oeb[30]
-port 90 nsew signal tristate
-rlabel metal3 s -960 293028 480 293268 4 io_oeb[31]
-port 91 nsew signal tristate
-rlabel metal3 s -960 240940 480 241180 4 io_oeb[32]
-port 92 nsew signal tristate
-rlabel metal3 s -960 188716 480 188956 4 io_oeb[33]
-port 93 nsew signal tristate
-rlabel metal3 s -960 136628 480 136868 4 io_oeb[34]
-port 94 nsew signal tristate
-rlabel metal3 s -960 84540 480 84780 4 io_oeb[35]
-port 95 nsew signal tristate
-rlabel metal3 s -960 45372 480 45612 4 io_oeb[36]
-port 96 nsew signal tristate
-rlabel metal3 s -960 6340 480 6580 4 io_oeb[37]
-port 97 nsew signal tristate
-rlabel metal3 s 583520 152540 584960 152780 6 io_oeb[3]
-port 98 nsew signal tristate
-rlabel metal3 s 583520 192388 584960 192628 6 io_oeb[4]
-port 99 nsew signal tristate
-rlabel metal3 s 583520 232236 584960 232476 6 io_oeb[5]
-port 100 nsew signal tristate
-rlabel metal3 s 583520 272084 584960 272324 6 io_oeb[6]
-port 101 nsew signal tristate
-rlabel metal3 s 583520 325124 584960 325364 6 io_oeb[7]
-port 102 nsew signal tristate
-rlabel metal3 s 583520 378300 584960 378540 6 io_oeb[8]
-port 103 nsew signal tristate
-rlabel metal3 s 583520 431476 584960 431716 6 io_oeb[9]
-port 104 nsew signal tristate
-rlabel metal3 s 583520 19668 584960 19908 6 io_out[0]
-port 105 nsew signal tristate
-rlabel metal3 s 583520 471324 584960 471564 6 io_out[10]
-port 106 nsew signal tristate
-rlabel metal3 s 583520 524364 584960 524604 6 io_out[11]
-port 107 nsew signal tristate
-rlabel metal3 s 583520 577540 584960 577780 6 io_out[12]
-port 108 nsew signal tristate
-rlabel metal3 s 583520 630716 584960 630956 6 io_out[13]
-port 109 nsew signal tristate
-rlabel metal3 s 583520 683756 584960 683996 6 io_out[14]
-port 110 nsew signal tristate
-rlabel metal2 s 543434 703520 543546 704960 6 io_out[15]
-port 111 nsew signal tristate
-rlabel metal2 s 478482 703520 478594 704960 6 io_out[16]
-port 112 nsew signal tristate
-rlabel metal2 s 413622 703520 413734 704960 6 io_out[17]
-port 113 nsew signal tristate
-rlabel metal2 s 348762 703520 348874 704960 6 io_out[18]
-port 114 nsew signal tristate
-rlabel metal2 s 283810 703520 283922 704960 6 io_out[19]
-port 115 nsew signal tristate
-rlabel metal3 s 583520 59516 584960 59756 6 io_out[1]
-port 116 nsew signal tristate
-rlabel metal2 s 218950 703520 219062 704960 6 io_out[20]
-port 117 nsew signal tristate
-rlabel metal2 s 154090 703520 154202 704960 6 io_out[21]
-port 118 nsew signal tristate
-rlabel metal2 s 89138 703520 89250 704960 6 io_out[22]
-port 119 nsew signal tristate
-rlabel metal2 s 24278 703520 24390 704960 6 io_out[23]
-port 120 nsew signal tristate
-rlabel metal3 s -960 671108 480 671348 4 io_out[24]
-port 121 nsew signal tristate
-rlabel metal3 s -960 619020 480 619260 4 io_out[25]
-port 122 nsew signal tristate
-rlabel metal3 s -960 566796 480 567036 4 io_out[26]
-port 123 nsew signal tristate
-rlabel metal3 s -960 514708 480 514948 4 io_out[27]
-port 124 nsew signal tristate
-rlabel metal3 s -960 462484 480 462724 4 io_out[28]
-port 125 nsew signal tristate
-rlabel metal3 s -960 410396 480 410636 4 io_out[29]
-port 126 nsew signal tristate
-rlabel metal3 s 583520 99364 584960 99604 6 io_out[2]
-port 127 nsew signal tristate
-rlabel metal3 s -960 358308 480 358548 4 io_out[30]
-port 128 nsew signal tristate
-rlabel metal3 s -960 306084 480 306324 4 io_out[31]
-port 129 nsew signal tristate
-rlabel metal3 s -960 253996 480 254236 4 io_out[32]
-port 130 nsew signal tristate
-rlabel metal3 s -960 201772 480 202012 4 io_out[33]
-port 131 nsew signal tristate
-rlabel metal3 s -960 149684 480 149924 4 io_out[34]
-port 132 nsew signal tristate
-rlabel metal3 s -960 97460 480 97700 4 io_out[35]
-port 133 nsew signal tristate
-rlabel metal3 s -960 58428 480 58668 4 io_out[36]
-port 134 nsew signal tristate
-rlabel metal3 s -960 19260 480 19500 4 io_out[37]
-port 135 nsew signal tristate
-rlabel metal3 s 583520 139212 584960 139452 6 io_out[3]
-port 136 nsew signal tristate
-rlabel metal3 s 583520 179060 584960 179300 6 io_out[4]
-port 137 nsew signal tristate
-rlabel metal3 s 583520 218908 584960 219148 6 io_out[5]
-port 138 nsew signal tristate
-rlabel metal3 s 583520 258756 584960 258996 6 io_out[6]
-port 139 nsew signal tristate
-rlabel metal3 s 583520 311932 584960 312172 6 io_out[7]
-port 140 nsew signal tristate
-rlabel metal3 s 583520 364972 584960 365212 6 io_out[8]
-port 141 nsew signal tristate
-rlabel metal3 s 583520 418148 584960 418388 6 io_out[9]
-port 142 nsew signal tristate
-rlabel metal2 s 125846 -960 125958 480 8 la_data_in[0]
-port 143 nsew signal input
-rlabel metal2 s 480506 -960 480618 480 8 la_data_in[100]
-port 144 nsew signal input
-rlabel metal2 s 484002 -960 484114 480 8 la_data_in[101]
-port 145 nsew signal input
-rlabel metal2 s 487590 -960 487702 480 8 la_data_in[102]
-port 146 nsew signal input
-rlabel metal2 s 491086 -960 491198 480 8 la_data_in[103]
-port 147 nsew signal input
-rlabel metal2 s 494674 -960 494786 480 8 la_data_in[104]
-port 148 nsew signal input
-rlabel metal2 s 498170 -960 498282 480 8 la_data_in[105]
-port 149 nsew signal input
-rlabel metal2 s 501758 -960 501870 480 8 la_data_in[106]
-port 150 nsew signal input
-rlabel metal2 s 505346 -960 505458 480 8 la_data_in[107]
-port 151 nsew signal input
-rlabel metal2 s 508842 -960 508954 480 8 la_data_in[108]
-port 152 nsew signal input
-rlabel metal2 s 512430 -960 512542 480 8 la_data_in[109]
-port 153 nsew signal input
-rlabel metal2 s 161266 -960 161378 480 8 la_data_in[10]
-port 154 nsew signal input
-rlabel metal2 s 515926 -960 516038 480 8 la_data_in[110]
-port 155 nsew signal input
-rlabel metal2 s 519514 -960 519626 480 8 la_data_in[111]
-port 156 nsew signal input
-rlabel metal2 s 523010 -960 523122 480 8 la_data_in[112]
-port 157 nsew signal input
-rlabel metal2 s 526598 -960 526710 480 8 la_data_in[113]
-port 158 nsew signal input
-rlabel metal2 s 530094 -960 530206 480 8 la_data_in[114]
-port 159 nsew signal input
-rlabel metal2 s 533682 -960 533794 480 8 la_data_in[115]
-port 160 nsew signal input
-rlabel metal2 s 537178 -960 537290 480 8 la_data_in[116]
-port 161 nsew signal input
-rlabel metal2 s 540766 -960 540878 480 8 la_data_in[117]
-port 162 nsew signal input
-rlabel metal2 s 544354 -960 544466 480 8 la_data_in[118]
-port 163 nsew signal input
-rlabel metal2 s 547850 -960 547962 480 8 la_data_in[119]
-port 164 nsew signal input
-rlabel metal2 s 164854 -960 164966 480 8 la_data_in[11]
-port 165 nsew signal input
-rlabel metal2 s 551438 -960 551550 480 8 la_data_in[120]
-port 166 nsew signal input
-rlabel metal2 s 554934 -960 555046 480 8 la_data_in[121]
-port 167 nsew signal input
-rlabel metal2 s 558522 -960 558634 480 8 la_data_in[122]
-port 168 nsew signal input
-rlabel metal2 s 562018 -960 562130 480 8 la_data_in[123]
-port 169 nsew signal input
-rlabel metal2 s 565606 -960 565718 480 8 la_data_in[124]
-port 170 nsew signal input
-rlabel metal2 s 569102 -960 569214 480 8 la_data_in[125]
-port 171 nsew signal input
-rlabel metal2 s 572690 -960 572802 480 8 la_data_in[126]
-port 172 nsew signal input
-rlabel metal2 s 576278 -960 576390 480 8 la_data_in[127]
-port 173 nsew signal input
-rlabel metal2 s 168350 -960 168462 480 8 la_data_in[12]
-port 174 nsew signal input
-rlabel metal2 s 171938 -960 172050 480 8 la_data_in[13]
-port 175 nsew signal input
-rlabel metal2 s 175434 -960 175546 480 8 la_data_in[14]
-port 176 nsew signal input
-rlabel metal2 s 179022 -960 179134 480 8 la_data_in[15]
-port 177 nsew signal input
-rlabel metal2 s 182518 -960 182630 480 8 la_data_in[16]
-port 178 nsew signal input
-rlabel metal2 s 186106 -960 186218 480 8 la_data_in[17]
-port 179 nsew signal input
-rlabel metal2 s 189694 -960 189806 480 8 la_data_in[18]
-port 180 nsew signal input
-rlabel metal2 s 193190 -960 193302 480 8 la_data_in[19]
-port 181 nsew signal input
-rlabel metal2 s 129342 -960 129454 480 8 la_data_in[1]
-port 182 nsew signal input
-rlabel metal2 s 196778 -960 196890 480 8 la_data_in[20]
-port 183 nsew signal input
-rlabel metal2 s 200274 -960 200386 480 8 la_data_in[21]
-port 184 nsew signal input
-rlabel metal2 s 203862 -960 203974 480 8 la_data_in[22]
-port 185 nsew signal input
-rlabel metal2 s 207358 -960 207470 480 8 la_data_in[23]
-port 186 nsew signal input
-rlabel metal2 s 210946 -960 211058 480 8 la_data_in[24]
-port 187 nsew signal input
-rlabel metal2 s 214442 -960 214554 480 8 la_data_in[25]
-port 188 nsew signal input
-rlabel metal2 s 218030 -960 218142 480 8 la_data_in[26]
-port 189 nsew signal input
-rlabel metal2 s 221526 -960 221638 480 8 la_data_in[27]
-port 190 nsew signal input
-rlabel metal2 s 225114 -960 225226 480 8 la_data_in[28]
-port 191 nsew signal input
-rlabel metal2 s 228702 -960 228814 480 8 la_data_in[29]
-port 192 nsew signal input
-rlabel metal2 s 132930 -960 133042 480 8 la_data_in[2]
-port 193 nsew signal input
-rlabel metal2 s 232198 -960 232310 480 8 la_data_in[30]
-port 194 nsew signal input
-rlabel metal2 s 235786 -960 235898 480 8 la_data_in[31]
-port 195 nsew signal input
-rlabel metal2 s 239282 -960 239394 480 8 la_data_in[32]
-port 196 nsew signal input
-rlabel metal2 s 242870 -960 242982 480 8 la_data_in[33]
-port 197 nsew signal input
-rlabel metal2 s 246366 -960 246478 480 8 la_data_in[34]
-port 198 nsew signal input
-rlabel metal2 s 249954 -960 250066 480 8 la_data_in[35]
-port 199 nsew signal input
-rlabel metal2 s 253450 -960 253562 480 8 la_data_in[36]
-port 200 nsew signal input
-rlabel metal2 s 257038 -960 257150 480 8 la_data_in[37]
-port 201 nsew signal input
-rlabel metal2 s 260626 -960 260738 480 8 la_data_in[38]
-port 202 nsew signal input
-rlabel metal2 s 264122 -960 264234 480 8 la_data_in[39]
-port 203 nsew signal input
-rlabel metal2 s 136426 -960 136538 480 8 la_data_in[3]
-port 204 nsew signal input
-rlabel metal2 s 267710 -960 267822 480 8 la_data_in[40]
-port 205 nsew signal input
-rlabel metal2 s 271206 -960 271318 480 8 la_data_in[41]
-port 206 nsew signal input
-rlabel metal2 s 274794 -960 274906 480 8 la_data_in[42]
-port 207 nsew signal input
-rlabel metal2 s 278290 -960 278402 480 8 la_data_in[43]
-port 208 nsew signal input
-rlabel metal2 s 281878 -960 281990 480 8 la_data_in[44]
-port 209 nsew signal input
-rlabel metal2 s 285374 -960 285486 480 8 la_data_in[45]
-port 210 nsew signal input
-rlabel metal2 s 288962 -960 289074 480 8 la_data_in[46]
-port 211 nsew signal input
-rlabel metal2 s 292550 -960 292662 480 8 la_data_in[47]
-port 212 nsew signal input
-rlabel metal2 s 296046 -960 296158 480 8 la_data_in[48]
-port 213 nsew signal input
-rlabel metal2 s 299634 -960 299746 480 8 la_data_in[49]
-port 214 nsew signal input
-rlabel metal2 s 140014 -960 140126 480 8 la_data_in[4]
-port 215 nsew signal input
-rlabel metal2 s 303130 -960 303242 480 8 la_data_in[50]
-port 216 nsew signal input
-rlabel metal2 s 306718 -960 306830 480 8 la_data_in[51]
-port 217 nsew signal input
-rlabel metal2 s 310214 -960 310326 480 8 la_data_in[52]
-port 218 nsew signal input
-rlabel metal2 s 313802 -960 313914 480 8 la_data_in[53]
-port 219 nsew signal input
-rlabel metal2 s 317298 -960 317410 480 8 la_data_in[54]
-port 220 nsew signal input
-rlabel metal2 s 320886 -960 320998 480 8 la_data_in[55]
-port 221 nsew signal input
-rlabel metal2 s 324382 -960 324494 480 8 la_data_in[56]
-port 222 nsew signal input
-rlabel metal2 s 327970 -960 328082 480 8 la_data_in[57]
-port 223 nsew signal input
-rlabel metal2 s 331558 -960 331670 480 8 la_data_in[58]
-port 224 nsew signal input
-rlabel metal2 s 335054 -960 335166 480 8 la_data_in[59]
-port 225 nsew signal input
-rlabel metal2 s 143510 -960 143622 480 8 la_data_in[5]
-port 226 nsew signal input
-rlabel metal2 s 338642 -960 338754 480 8 la_data_in[60]
-port 227 nsew signal input
-rlabel metal2 s 342138 -960 342250 480 8 la_data_in[61]
-port 228 nsew signal input
-rlabel metal2 s 345726 -960 345838 480 8 la_data_in[62]
-port 229 nsew signal input
-rlabel metal2 s 349222 -960 349334 480 8 la_data_in[63]
-port 230 nsew signal input
-rlabel metal2 s 352810 -960 352922 480 8 la_data_in[64]
-port 231 nsew signal input
-rlabel metal2 s 356306 -960 356418 480 8 la_data_in[65]
-port 232 nsew signal input
-rlabel metal2 s 359894 -960 360006 480 8 la_data_in[66]
-port 233 nsew signal input
-rlabel metal2 s 363482 -960 363594 480 8 la_data_in[67]
-port 234 nsew signal input
-rlabel metal2 s 366978 -960 367090 480 8 la_data_in[68]
-port 235 nsew signal input
-rlabel metal2 s 370566 -960 370678 480 8 la_data_in[69]
-port 236 nsew signal input
-rlabel metal2 s 147098 -960 147210 480 8 la_data_in[6]
-port 237 nsew signal input
-rlabel metal2 s 374062 -960 374174 480 8 la_data_in[70]
-port 238 nsew signal input
-rlabel metal2 s 377650 -960 377762 480 8 la_data_in[71]
-port 239 nsew signal input
-rlabel metal2 s 381146 -960 381258 480 8 la_data_in[72]
-port 240 nsew signal input
-rlabel metal2 s 384734 -960 384846 480 8 la_data_in[73]
-port 241 nsew signal input
-rlabel metal2 s 388230 -960 388342 480 8 la_data_in[74]
-port 242 nsew signal input
-rlabel metal2 s 391818 -960 391930 480 8 la_data_in[75]
-port 243 nsew signal input
-rlabel metal2 s 395314 -960 395426 480 8 la_data_in[76]
-port 244 nsew signal input
-rlabel metal2 s 398902 -960 399014 480 8 la_data_in[77]
-port 245 nsew signal input
-rlabel metal2 s 402490 -960 402602 480 8 la_data_in[78]
-port 246 nsew signal input
-rlabel metal2 s 405986 -960 406098 480 8 la_data_in[79]
-port 247 nsew signal input
-rlabel metal2 s 150594 -960 150706 480 8 la_data_in[7]
-port 248 nsew signal input
-rlabel metal2 s 409574 -960 409686 480 8 la_data_in[80]
-port 249 nsew signal input
-rlabel metal2 s 413070 -960 413182 480 8 la_data_in[81]
-port 250 nsew signal input
-rlabel metal2 s 416658 -960 416770 480 8 la_data_in[82]
-port 251 nsew signal input
-rlabel metal2 s 420154 -960 420266 480 8 la_data_in[83]
-port 252 nsew signal input
-rlabel metal2 s 423742 -960 423854 480 8 la_data_in[84]
-port 253 nsew signal input
-rlabel metal2 s 427238 -960 427350 480 8 la_data_in[85]
-port 254 nsew signal input
-rlabel metal2 s 430826 -960 430938 480 8 la_data_in[86]
-port 255 nsew signal input
-rlabel metal2 s 434414 -960 434526 480 8 la_data_in[87]
-port 256 nsew signal input
-rlabel metal2 s 437910 -960 438022 480 8 la_data_in[88]
-port 257 nsew signal input
-rlabel metal2 s 441498 -960 441610 480 8 la_data_in[89]
-port 258 nsew signal input
-rlabel metal2 s 154182 -960 154294 480 8 la_data_in[8]
-port 259 nsew signal input
-rlabel metal2 s 444994 -960 445106 480 8 la_data_in[90]
-port 260 nsew signal input
-rlabel metal2 s 448582 -960 448694 480 8 la_data_in[91]
-port 261 nsew signal input
-rlabel metal2 s 452078 -960 452190 480 8 la_data_in[92]
-port 262 nsew signal input
-rlabel metal2 s 455666 -960 455778 480 8 la_data_in[93]
-port 263 nsew signal input
-rlabel metal2 s 459162 -960 459274 480 8 la_data_in[94]
-port 264 nsew signal input
-rlabel metal2 s 462750 -960 462862 480 8 la_data_in[95]
-port 265 nsew signal input
-rlabel metal2 s 466246 -960 466358 480 8 la_data_in[96]
-port 266 nsew signal input
-rlabel metal2 s 469834 -960 469946 480 8 la_data_in[97]
-port 267 nsew signal input
-rlabel metal2 s 473422 -960 473534 480 8 la_data_in[98]
-port 268 nsew signal input
-rlabel metal2 s 476918 -960 477030 480 8 la_data_in[99]
-port 269 nsew signal input
-rlabel metal2 s 157770 -960 157882 480 8 la_data_in[9]
-port 270 nsew signal input
-rlabel metal2 s 126950 -960 127062 480 8 la_data_out[0]
-port 271 nsew signal tristate
-rlabel metal2 s 481702 -960 481814 480 8 la_data_out[100]
-port 272 nsew signal tristate
-rlabel metal2 s 485198 -960 485310 480 8 la_data_out[101]
-port 273 nsew signal tristate
-rlabel metal2 s 488786 -960 488898 480 8 la_data_out[102]
-port 274 nsew signal tristate
-rlabel metal2 s 492282 -960 492394 480 8 la_data_out[103]
-port 275 nsew signal tristate
-rlabel metal2 s 495870 -960 495982 480 8 la_data_out[104]
-port 276 nsew signal tristate
-rlabel metal2 s 499366 -960 499478 480 8 la_data_out[105]
-port 277 nsew signal tristate
-rlabel metal2 s 502954 -960 503066 480 8 la_data_out[106]
-port 278 nsew signal tristate
-rlabel metal2 s 506450 -960 506562 480 8 la_data_out[107]
-port 279 nsew signal tristate
-rlabel metal2 s 510038 -960 510150 480 8 la_data_out[108]
-port 280 nsew signal tristate
-rlabel metal2 s 513534 -960 513646 480 8 la_data_out[109]
-port 281 nsew signal tristate
-rlabel metal2 s 162462 -960 162574 480 8 la_data_out[10]
-port 282 nsew signal tristate
-rlabel metal2 s 517122 -960 517234 480 8 la_data_out[110]
-port 283 nsew signal tristate
-rlabel metal2 s 520710 -960 520822 480 8 la_data_out[111]
-port 284 nsew signal tristate
-rlabel metal2 s 524206 -960 524318 480 8 la_data_out[112]
-port 285 nsew signal tristate
-rlabel metal2 s 527794 -960 527906 480 8 la_data_out[113]
-port 286 nsew signal tristate
-rlabel metal2 s 531290 -960 531402 480 8 la_data_out[114]
-port 287 nsew signal tristate
-rlabel metal2 s 534878 -960 534990 480 8 la_data_out[115]
-port 288 nsew signal tristate
-rlabel metal2 s 538374 -960 538486 480 8 la_data_out[116]
-port 289 nsew signal tristate
-rlabel metal2 s 541962 -960 542074 480 8 la_data_out[117]
-port 290 nsew signal tristate
-rlabel metal2 s 545458 -960 545570 480 8 la_data_out[118]
-port 291 nsew signal tristate
-rlabel metal2 s 549046 -960 549158 480 8 la_data_out[119]
-port 292 nsew signal tristate
-rlabel metal2 s 166050 -960 166162 480 8 la_data_out[11]
-port 293 nsew signal tristate
-rlabel metal2 s 552634 -960 552746 480 8 la_data_out[120]
-port 294 nsew signal tristate
-rlabel metal2 s 556130 -960 556242 480 8 la_data_out[121]
-port 295 nsew signal tristate
-rlabel metal2 s 559718 -960 559830 480 8 la_data_out[122]
-port 296 nsew signal tristate
-rlabel metal2 s 563214 -960 563326 480 8 la_data_out[123]
-port 297 nsew signal tristate
-rlabel metal2 s 566802 -960 566914 480 8 la_data_out[124]
-port 298 nsew signal tristate
-rlabel metal2 s 570298 -960 570410 480 8 la_data_out[125]
-port 299 nsew signal tristate
-rlabel metal2 s 573886 -960 573998 480 8 la_data_out[126]
-port 300 nsew signal tristate
-rlabel metal2 s 577382 -960 577494 480 8 la_data_out[127]
-port 301 nsew signal tristate
-rlabel metal2 s 169546 -960 169658 480 8 la_data_out[12]
-port 302 nsew signal tristate
-rlabel metal2 s 173134 -960 173246 480 8 la_data_out[13]
-port 303 nsew signal tristate
-rlabel metal2 s 176630 -960 176742 480 8 la_data_out[14]
-port 304 nsew signal tristate
-rlabel metal2 s 180218 -960 180330 480 8 la_data_out[15]
-port 305 nsew signal tristate
-rlabel metal2 s 183714 -960 183826 480 8 la_data_out[16]
-port 306 nsew signal tristate
-rlabel metal2 s 187302 -960 187414 480 8 la_data_out[17]
-port 307 nsew signal tristate
-rlabel metal2 s 190798 -960 190910 480 8 la_data_out[18]
-port 308 nsew signal tristate
-rlabel metal2 s 194386 -960 194498 480 8 la_data_out[19]
-port 309 nsew signal tristate
-rlabel metal2 s 130538 -960 130650 480 8 la_data_out[1]
-port 310 nsew signal tristate
-rlabel metal2 s 197882 -960 197994 480 8 la_data_out[20]
-port 311 nsew signal tristate
-rlabel metal2 s 201470 -960 201582 480 8 la_data_out[21]
-port 312 nsew signal tristate
-rlabel metal2 s 205058 -960 205170 480 8 la_data_out[22]
-port 313 nsew signal tristate
-rlabel metal2 s 208554 -960 208666 480 8 la_data_out[23]
-port 314 nsew signal tristate
-rlabel metal2 s 212142 -960 212254 480 8 la_data_out[24]
-port 315 nsew signal tristate
-rlabel metal2 s 215638 -960 215750 480 8 la_data_out[25]
-port 316 nsew signal tristate
-rlabel metal2 s 219226 -960 219338 480 8 la_data_out[26]
-port 317 nsew signal tristate
-rlabel metal2 s 222722 -960 222834 480 8 la_data_out[27]
-port 318 nsew signal tristate
-rlabel metal2 s 226310 -960 226422 480 8 la_data_out[28]
-port 319 nsew signal tristate
-rlabel metal2 s 229806 -960 229918 480 8 la_data_out[29]
-port 320 nsew signal tristate
-rlabel metal2 s 134126 -960 134238 480 8 la_data_out[2]
-port 321 nsew signal tristate
-rlabel metal2 s 233394 -960 233506 480 8 la_data_out[30]
-port 322 nsew signal tristate
-rlabel metal2 s 236982 -960 237094 480 8 la_data_out[31]
-port 323 nsew signal tristate
-rlabel metal2 s 240478 -960 240590 480 8 la_data_out[32]
-port 324 nsew signal tristate
-rlabel metal2 s 244066 -960 244178 480 8 la_data_out[33]
-port 325 nsew signal tristate
-rlabel metal2 s 247562 -960 247674 480 8 la_data_out[34]
-port 326 nsew signal tristate
-rlabel metal2 s 251150 -960 251262 480 8 la_data_out[35]
-port 327 nsew signal tristate
-rlabel metal2 s 254646 -960 254758 480 8 la_data_out[36]
-port 328 nsew signal tristate
-rlabel metal2 s 258234 -960 258346 480 8 la_data_out[37]
-port 329 nsew signal tristate
-rlabel metal2 s 261730 -960 261842 480 8 la_data_out[38]
-port 330 nsew signal tristate
-rlabel metal2 s 265318 -960 265430 480 8 la_data_out[39]
-port 331 nsew signal tristate
-rlabel metal2 s 137622 -960 137734 480 8 la_data_out[3]
-port 332 nsew signal tristate
-rlabel metal2 s 268814 -960 268926 480 8 la_data_out[40]
-port 333 nsew signal tristate
-rlabel metal2 s 272402 -960 272514 480 8 la_data_out[41]
-port 334 nsew signal tristate
-rlabel metal2 s 275990 -960 276102 480 8 la_data_out[42]
-port 335 nsew signal tristate
-rlabel metal2 s 279486 -960 279598 480 8 la_data_out[43]
-port 336 nsew signal tristate
-rlabel metal2 s 283074 -960 283186 480 8 la_data_out[44]
-port 337 nsew signal tristate
-rlabel metal2 s 286570 -960 286682 480 8 la_data_out[45]
-port 338 nsew signal tristate
-rlabel metal2 s 290158 -960 290270 480 8 la_data_out[46]
-port 339 nsew signal tristate
-rlabel metal2 s 293654 -960 293766 480 8 la_data_out[47]
-port 340 nsew signal tristate
-rlabel metal2 s 297242 -960 297354 480 8 la_data_out[48]
-port 341 nsew signal tristate
-rlabel metal2 s 300738 -960 300850 480 8 la_data_out[49]
-port 342 nsew signal tristate
-rlabel metal2 s 141210 -960 141322 480 8 la_data_out[4]
-port 343 nsew signal tristate
-rlabel metal2 s 304326 -960 304438 480 8 la_data_out[50]
-port 344 nsew signal tristate
-rlabel metal2 s 307914 -960 308026 480 8 la_data_out[51]
-port 345 nsew signal tristate
-rlabel metal2 s 311410 -960 311522 480 8 la_data_out[52]
-port 346 nsew signal tristate
-rlabel metal2 s 314998 -960 315110 480 8 la_data_out[53]
-port 347 nsew signal tristate
-rlabel metal2 s 318494 -960 318606 480 8 la_data_out[54]
-port 348 nsew signal tristate
-rlabel metal2 s 322082 -960 322194 480 8 la_data_out[55]
-port 349 nsew signal tristate
-rlabel metal2 s 325578 -960 325690 480 8 la_data_out[56]
-port 350 nsew signal tristate
-rlabel metal2 s 329166 -960 329278 480 8 la_data_out[57]
-port 351 nsew signal tristate
-rlabel metal2 s 332662 -960 332774 480 8 la_data_out[58]
-port 352 nsew signal tristate
-rlabel metal2 s 336250 -960 336362 480 8 la_data_out[59]
-port 353 nsew signal tristate
-rlabel metal2 s 144706 -960 144818 480 8 la_data_out[5]
-port 354 nsew signal tristate
-rlabel metal2 s 339838 -960 339950 480 8 la_data_out[60]
-port 355 nsew signal tristate
-rlabel metal2 s 343334 -960 343446 480 8 la_data_out[61]
-port 356 nsew signal tristate
-rlabel metal2 s 346922 -960 347034 480 8 la_data_out[62]
-port 357 nsew signal tristate
-rlabel metal2 s 350418 -960 350530 480 8 la_data_out[63]
-port 358 nsew signal tristate
-rlabel metal2 s 354006 -960 354118 480 8 la_data_out[64]
-port 359 nsew signal tristate
-rlabel metal2 s 357502 -960 357614 480 8 la_data_out[65]
-port 360 nsew signal tristate
-rlabel metal2 s 361090 -960 361202 480 8 la_data_out[66]
-port 361 nsew signal tristate
-rlabel metal2 s 364586 -960 364698 480 8 la_data_out[67]
-port 362 nsew signal tristate
-rlabel metal2 s 368174 -960 368286 480 8 la_data_out[68]
-port 363 nsew signal tristate
-rlabel metal2 s 371670 -960 371782 480 8 la_data_out[69]
-port 364 nsew signal tristate
-rlabel metal2 s 148294 -960 148406 480 8 la_data_out[6]
-port 365 nsew signal tristate
-rlabel metal2 s 375258 -960 375370 480 8 la_data_out[70]
-port 366 nsew signal tristate
-rlabel metal2 s 378846 -960 378958 480 8 la_data_out[71]
-port 367 nsew signal tristate
-rlabel metal2 s 382342 -960 382454 480 8 la_data_out[72]
-port 368 nsew signal tristate
-rlabel metal2 s 385930 -960 386042 480 8 la_data_out[73]
-port 369 nsew signal tristate
-rlabel metal2 s 389426 -960 389538 480 8 la_data_out[74]
-port 370 nsew signal tristate
-rlabel metal2 s 393014 -960 393126 480 8 la_data_out[75]
-port 371 nsew signal tristate
-rlabel metal2 s 396510 -960 396622 480 8 la_data_out[76]
-port 372 nsew signal tristate
-rlabel metal2 s 400098 -960 400210 480 8 la_data_out[77]
-port 373 nsew signal tristate
-rlabel metal2 s 403594 -960 403706 480 8 la_data_out[78]
-port 374 nsew signal tristate
-rlabel metal2 s 407182 -960 407294 480 8 la_data_out[79]
-port 375 nsew signal tristate
-rlabel metal2 s 151790 -960 151902 480 8 la_data_out[7]
-port 376 nsew signal tristate
-rlabel metal2 s 410770 -960 410882 480 8 la_data_out[80]
-port 377 nsew signal tristate
-rlabel metal2 s 414266 -960 414378 480 8 la_data_out[81]
-port 378 nsew signal tristate
-rlabel metal2 s 417854 -960 417966 480 8 la_data_out[82]
-port 379 nsew signal tristate
-rlabel metal2 s 421350 -960 421462 480 8 la_data_out[83]
-port 380 nsew signal tristate
-rlabel metal2 s 424938 -960 425050 480 8 la_data_out[84]
-port 381 nsew signal tristate
-rlabel metal2 s 428434 -960 428546 480 8 la_data_out[85]
-port 382 nsew signal tristate
-rlabel metal2 s 432022 -960 432134 480 8 la_data_out[86]
-port 383 nsew signal tristate
-rlabel metal2 s 435518 -960 435630 480 8 la_data_out[87]
-port 384 nsew signal tristate
-rlabel metal2 s 439106 -960 439218 480 8 la_data_out[88]
-port 385 nsew signal tristate
-rlabel metal2 s 442602 -960 442714 480 8 la_data_out[89]
-port 386 nsew signal tristate
-rlabel metal2 s 155378 -960 155490 480 8 la_data_out[8]
-port 387 nsew signal tristate
-rlabel metal2 s 446190 -960 446302 480 8 la_data_out[90]
-port 388 nsew signal tristate
-rlabel metal2 s 449778 -960 449890 480 8 la_data_out[91]
-port 389 nsew signal tristate
-rlabel metal2 s 453274 -960 453386 480 8 la_data_out[92]
-port 390 nsew signal tristate
-rlabel metal2 s 456862 -960 456974 480 8 la_data_out[93]
-port 391 nsew signal tristate
-rlabel metal2 s 460358 -960 460470 480 8 la_data_out[94]
-port 392 nsew signal tristate
-rlabel metal2 s 463946 -960 464058 480 8 la_data_out[95]
-port 393 nsew signal tristate
-rlabel metal2 s 467442 -960 467554 480 8 la_data_out[96]
-port 394 nsew signal tristate
-rlabel metal2 s 471030 -960 471142 480 8 la_data_out[97]
-port 395 nsew signal tristate
-rlabel metal2 s 474526 -960 474638 480 8 la_data_out[98]
-port 396 nsew signal tristate
-rlabel metal2 s 478114 -960 478226 480 8 la_data_out[99]
-port 397 nsew signal tristate
-rlabel metal2 s 158874 -960 158986 480 8 la_data_out[9]
-port 398 nsew signal tristate
-rlabel metal2 s 128146 -960 128258 480 8 la_oenb[0]
-port 399 nsew signal input
-rlabel metal2 s 482806 -960 482918 480 8 la_oenb[100]
-port 400 nsew signal input
-rlabel metal2 s 486394 -960 486506 480 8 la_oenb[101]
-port 401 nsew signal input
-rlabel metal2 s 489890 -960 490002 480 8 la_oenb[102]
-port 402 nsew signal input
-rlabel metal2 s 493478 -960 493590 480 8 la_oenb[103]
-port 403 nsew signal input
-rlabel metal2 s 497066 -960 497178 480 8 la_oenb[104]
-port 404 nsew signal input
-rlabel metal2 s 500562 -960 500674 480 8 la_oenb[105]
-port 405 nsew signal input
-rlabel metal2 s 504150 -960 504262 480 8 la_oenb[106]
-port 406 nsew signal input
-rlabel metal2 s 507646 -960 507758 480 8 la_oenb[107]
-port 407 nsew signal input
-rlabel metal2 s 511234 -960 511346 480 8 la_oenb[108]
-port 408 nsew signal input
-rlabel metal2 s 514730 -960 514842 480 8 la_oenb[109]
-port 409 nsew signal input
-rlabel metal2 s 163658 -960 163770 480 8 la_oenb[10]
-port 410 nsew signal input
-rlabel metal2 s 518318 -960 518430 480 8 la_oenb[110]
-port 411 nsew signal input
-rlabel metal2 s 521814 -960 521926 480 8 la_oenb[111]
-port 412 nsew signal input
-rlabel metal2 s 525402 -960 525514 480 8 la_oenb[112]
-port 413 nsew signal input
-rlabel metal2 s 528990 -960 529102 480 8 la_oenb[113]
-port 414 nsew signal input
-rlabel metal2 s 532486 -960 532598 480 8 la_oenb[114]
-port 415 nsew signal input
-rlabel metal2 s 536074 -960 536186 480 8 la_oenb[115]
-port 416 nsew signal input
-rlabel metal2 s 539570 -960 539682 480 8 la_oenb[116]
-port 417 nsew signal input
-rlabel metal2 s 543158 -960 543270 480 8 la_oenb[117]
-port 418 nsew signal input
-rlabel metal2 s 546654 -960 546766 480 8 la_oenb[118]
-port 419 nsew signal input
-rlabel metal2 s 550242 -960 550354 480 8 la_oenb[119]
-port 420 nsew signal input
-rlabel metal2 s 167154 -960 167266 480 8 la_oenb[11]
-port 421 nsew signal input
-rlabel metal2 s 553738 -960 553850 480 8 la_oenb[120]
-port 422 nsew signal input
-rlabel metal2 s 557326 -960 557438 480 8 la_oenb[121]
-port 423 nsew signal input
-rlabel metal2 s 560822 -960 560934 480 8 la_oenb[122]
-port 424 nsew signal input
-rlabel metal2 s 564410 -960 564522 480 8 la_oenb[123]
-port 425 nsew signal input
-rlabel metal2 s 567998 -960 568110 480 8 la_oenb[124]
-port 426 nsew signal input
-rlabel metal2 s 571494 -960 571606 480 8 la_oenb[125]
-port 427 nsew signal input
-rlabel metal2 s 575082 -960 575194 480 8 la_oenb[126]
-port 428 nsew signal input
-rlabel metal2 s 578578 -960 578690 480 8 la_oenb[127]
-port 429 nsew signal input
-rlabel metal2 s 170742 -960 170854 480 8 la_oenb[12]
-port 430 nsew signal input
-rlabel metal2 s 174238 -960 174350 480 8 la_oenb[13]
-port 431 nsew signal input
-rlabel metal2 s 177826 -960 177938 480 8 la_oenb[14]
-port 432 nsew signal input
-rlabel metal2 s 181414 -960 181526 480 8 la_oenb[15]
-port 433 nsew signal input
-rlabel metal2 s 184910 -960 185022 480 8 la_oenb[16]
-port 434 nsew signal input
-rlabel metal2 s 188498 -960 188610 480 8 la_oenb[17]
-port 435 nsew signal input
-rlabel metal2 s 191994 -960 192106 480 8 la_oenb[18]
-port 436 nsew signal input
-rlabel metal2 s 195582 -960 195694 480 8 la_oenb[19]
-port 437 nsew signal input
-rlabel metal2 s 131734 -960 131846 480 8 la_oenb[1]
-port 438 nsew signal input
-rlabel metal2 s 199078 -960 199190 480 8 la_oenb[20]
-port 439 nsew signal input
-rlabel metal2 s 202666 -960 202778 480 8 la_oenb[21]
-port 440 nsew signal input
-rlabel metal2 s 206162 -960 206274 480 8 la_oenb[22]
-port 441 nsew signal input
-rlabel metal2 s 209750 -960 209862 480 8 la_oenb[23]
-port 442 nsew signal input
-rlabel metal2 s 213338 -960 213450 480 8 la_oenb[24]
-port 443 nsew signal input
-rlabel metal2 s 216834 -960 216946 480 8 la_oenb[25]
-port 444 nsew signal input
-rlabel metal2 s 220422 -960 220534 480 8 la_oenb[26]
-port 445 nsew signal input
-rlabel metal2 s 223918 -960 224030 480 8 la_oenb[27]
-port 446 nsew signal input
-rlabel metal2 s 227506 -960 227618 480 8 la_oenb[28]
-port 447 nsew signal input
-rlabel metal2 s 231002 -960 231114 480 8 la_oenb[29]
-port 448 nsew signal input
-rlabel metal2 s 135230 -960 135342 480 8 la_oenb[2]
-port 449 nsew signal input
-rlabel metal2 s 234590 -960 234702 480 8 la_oenb[30]
-port 450 nsew signal input
-rlabel metal2 s 238086 -960 238198 480 8 la_oenb[31]
-port 451 nsew signal input
-rlabel metal2 s 241674 -960 241786 480 8 la_oenb[32]
-port 452 nsew signal input
-rlabel metal2 s 245170 -960 245282 480 8 la_oenb[33]
-port 453 nsew signal input
-rlabel metal2 s 248758 -960 248870 480 8 la_oenb[34]
-port 454 nsew signal input
-rlabel metal2 s 252346 -960 252458 480 8 la_oenb[35]
-port 455 nsew signal input
-rlabel metal2 s 255842 -960 255954 480 8 la_oenb[36]
-port 456 nsew signal input
-rlabel metal2 s 259430 -960 259542 480 8 la_oenb[37]
-port 457 nsew signal input
-rlabel metal2 s 262926 -960 263038 480 8 la_oenb[38]
-port 458 nsew signal input
-rlabel metal2 s 266514 -960 266626 480 8 la_oenb[39]
-port 459 nsew signal input
-rlabel metal2 s 138818 -960 138930 480 8 la_oenb[3]
-port 460 nsew signal input
-rlabel metal2 s 270010 -960 270122 480 8 la_oenb[40]
-port 461 nsew signal input
-rlabel metal2 s 273598 -960 273710 480 8 la_oenb[41]
-port 462 nsew signal input
-rlabel metal2 s 277094 -960 277206 480 8 la_oenb[42]
-port 463 nsew signal input
-rlabel metal2 s 280682 -960 280794 480 8 la_oenb[43]
-port 464 nsew signal input
-rlabel metal2 s 284270 -960 284382 480 8 la_oenb[44]
-port 465 nsew signal input
-rlabel metal2 s 287766 -960 287878 480 8 la_oenb[45]
-port 466 nsew signal input
-rlabel metal2 s 291354 -960 291466 480 8 la_oenb[46]
-port 467 nsew signal input
-rlabel metal2 s 294850 -960 294962 480 8 la_oenb[47]
-port 468 nsew signal input
-rlabel metal2 s 298438 -960 298550 480 8 la_oenb[48]
-port 469 nsew signal input
-rlabel metal2 s 301934 -960 302046 480 8 la_oenb[49]
-port 470 nsew signal input
-rlabel metal2 s 142406 -960 142518 480 8 la_oenb[4]
-port 471 nsew signal input
-rlabel metal2 s 305522 -960 305634 480 8 la_oenb[50]
-port 472 nsew signal input
-rlabel metal2 s 309018 -960 309130 480 8 la_oenb[51]
-port 473 nsew signal input
-rlabel metal2 s 312606 -960 312718 480 8 la_oenb[52]
-port 474 nsew signal input
-rlabel metal2 s 316194 -960 316306 480 8 la_oenb[53]
-port 475 nsew signal input
-rlabel metal2 s 319690 -960 319802 480 8 la_oenb[54]
-port 476 nsew signal input
-rlabel metal2 s 323278 -960 323390 480 8 la_oenb[55]
-port 477 nsew signal input
-rlabel metal2 s 326774 -960 326886 480 8 la_oenb[56]
-port 478 nsew signal input
-rlabel metal2 s 330362 -960 330474 480 8 la_oenb[57]
-port 479 nsew signal input
-rlabel metal2 s 333858 -960 333970 480 8 la_oenb[58]
-port 480 nsew signal input
-rlabel metal2 s 337446 -960 337558 480 8 la_oenb[59]
-port 481 nsew signal input
-rlabel metal2 s 145902 -960 146014 480 8 la_oenb[5]
-port 482 nsew signal input
-rlabel metal2 s 340942 -960 341054 480 8 la_oenb[60]
-port 483 nsew signal input
-rlabel metal2 s 344530 -960 344642 480 8 la_oenb[61]
-port 484 nsew signal input
-rlabel metal2 s 348026 -960 348138 480 8 la_oenb[62]
-port 485 nsew signal input
-rlabel metal2 s 351614 -960 351726 480 8 la_oenb[63]
-port 486 nsew signal input
-rlabel metal2 s 355202 -960 355314 480 8 la_oenb[64]
-port 487 nsew signal input
-rlabel metal2 s 358698 -960 358810 480 8 la_oenb[65]
-port 488 nsew signal input
-rlabel metal2 s 362286 -960 362398 480 8 la_oenb[66]
-port 489 nsew signal input
-rlabel metal2 s 365782 -960 365894 480 8 la_oenb[67]
-port 490 nsew signal input
-rlabel metal2 s 369370 -960 369482 480 8 la_oenb[68]
-port 491 nsew signal input
-rlabel metal2 s 372866 -960 372978 480 8 la_oenb[69]
-port 492 nsew signal input
-rlabel metal2 s 149490 -960 149602 480 8 la_oenb[6]
-port 493 nsew signal input
-rlabel metal2 s 376454 -960 376566 480 8 la_oenb[70]
-port 494 nsew signal input
-rlabel metal2 s 379950 -960 380062 480 8 la_oenb[71]
-port 495 nsew signal input
-rlabel metal2 s 383538 -960 383650 480 8 la_oenb[72]
-port 496 nsew signal input
-rlabel metal2 s 387126 -960 387238 480 8 la_oenb[73]
-port 497 nsew signal input
-rlabel metal2 s 390622 -960 390734 480 8 la_oenb[74]
-port 498 nsew signal input
-rlabel metal2 s 394210 -960 394322 480 8 la_oenb[75]
-port 499 nsew signal input
-rlabel metal2 s 397706 -960 397818 480 8 la_oenb[76]
-port 500 nsew signal input
-rlabel metal2 s 401294 -960 401406 480 8 la_oenb[77]
-port 501 nsew signal input
-rlabel metal2 s 404790 -960 404902 480 8 la_oenb[78]
-port 502 nsew signal input
-rlabel metal2 s 408378 -960 408490 480 8 la_oenb[79]
-port 503 nsew signal input
-rlabel metal2 s 152986 -960 153098 480 8 la_oenb[7]
-port 504 nsew signal input
-rlabel metal2 s 411874 -960 411986 480 8 la_oenb[80]
-port 505 nsew signal input
-rlabel metal2 s 415462 -960 415574 480 8 la_oenb[81]
-port 506 nsew signal input
-rlabel metal2 s 418958 -960 419070 480 8 la_oenb[82]
-port 507 nsew signal input
-rlabel metal2 s 422546 -960 422658 480 8 la_oenb[83]
-port 508 nsew signal input
-rlabel metal2 s 426134 -960 426246 480 8 la_oenb[84]
-port 509 nsew signal input
-rlabel metal2 s 429630 -960 429742 480 8 la_oenb[85]
-port 510 nsew signal input
-rlabel metal2 s 433218 -960 433330 480 8 la_oenb[86]
-port 511 nsew signal input
-rlabel metal2 s 436714 -960 436826 480 8 la_oenb[87]
-port 512 nsew signal input
-rlabel metal2 s 440302 -960 440414 480 8 la_oenb[88]
-port 513 nsew signal input
-rlabel metal2 s 443798 -960 443910 480 8 la_oenb[89]
-port 514 nsew signal input
-rlabel metal2 s 156574 -960 156686 480 8 la_oenb[8]
-port 515 nsew signal input
-rlabel metal2 s 447386 -960 447498 480 8 la_oenb[90]
-port 516 nsew signal input
-rlabel metal2 s 450882 -960 450994 480 8 la_oenb[91]
-port 517 nsew signal input
-rlabel metal2 s 454470 -960 454582 480 8 la_oenb[92]
-port 518 nsew signal input
-rlabel metal2 s 458058 -960 458170 480 8 la_oenb[93]
-port 519 nsew signal input
-rlabel metal2 s 461554 -960 461666 480 8 la_oenb[94]
-port 520 nsew signal input
-rlabel metal2 s 465142 -960 465254 480 8 la_oenb[95]
-port 521 nsew signal input
-rlabel metal2 s 468638 -960 468750 480 8 la_oenb[96]
-port 522 nsew signal input
-rlabel metal2 s 472226 -960 472338 480 8 la_oenb[97]
-port 523 nsew signal input
-rlabel metal2 s 475722 -960 475834 480 8 la_oenb[98]
-port 524 nsew signal input
-rlabel metal2 s 479310 -960 479422 480 8 la_oenb[99]
-port 525 nsew signal input
-rlabel metal2 s 160070 -960 160182 480 8 la_oenb[9]
-port 526 nsew signal input
-rlabel metal2 s 579774 -960 579886 480 8 user_clock2
-port 527 nsew signal input
-rlabel metal2 s 580970 -960 581082 480 8 user_irq[0]
-port 528 nsew signal tristate
-rlabel metal2 s 582166 -960 582278 480 8 user_irq[1]
-port 529 nsew signal tristate
-rlabel metal2 s 583362 -960 583474 480 8 user_irq[2]
-port 530 nsew signal tristate
-rlabel metal5 s -2006 -934 585930 -314 8 vccd1
-port 531 nsew power input
-rlabel metal5 s -3926 -2854 587850 -2234 8 vccd2
-port 532 nsew power input
-rlabel metal5 s -5846 -4774 589770 -4154 8 vdda1
-port 533 nsew power input
-rlabel metal5 s -7766 -6694 591690 -6074 8 vdda2
-port 534 nsew power input
-rlabel metal5 s -6806 -5734 590730 -5114 8 vssa1
-port 535 nsew ground input
-rlabel metal5 s -8726 -7654 592650 -7034 8 vssa2
-port 536 nsew ground input
-rlabel metal5 s -2966 -1894 586890 -1274 8 vssd1
-port 537 nsew ground input
-rlabel metal5 s -4886 -3814 588810 -3194 8 vssd2
-port 538 nsew ground input
-rlabel metal2 s 542 -960 654 480 8 wb_clk_i
-port 539 nsew signal input
-rlabel metal2 s 1646 -960 1758 480 8 wb_rst_i
-port 540 nsew signal input
-rlabel metal2 s 2842 -960 2954 480 8 wbs_ack_o
-port 541 nsew signal tristate
-rlabel metal2 s 7626 -960 7738 480 8 wbs_adr_i[0]
-port 542 nsew signal input
-rlabel metal2 s 47830 -960 47942 480 8 wbs_adr_i[10]
-port 543 nsew signal input
-rlabel metal2 s 51326 -960 51438 480 8 wbs_adr_i[11]
-port 544 nsew signal input
-rlabel metal2 s 54914 -960 55026 480 8 wbs_adr_i[12]
-port 545 nsew signal input
-rlabel metal2 s 58410 -960 58522 480 8 wbs_adr_i[13]
-port 546 nsew signal input
-rlabel metal2 s 61998 -960 62110 480 8 wbs_adr_i[14]
-port 547 nsew signal input
-rlabel metal2 s 65494 -960 65606 480 8 wbs_adr_i[15]
-port 548 nsew signal input
-rlabel metal2 s 69082 -960 69194 480 8 wbs_adr_i[16]
-port 549 nsew signal input
-rlabel metal2 s 72578 -960 72690 480 8 wbs_adr_i[17]
-port 550 nsew signal input
-rlabel metal2 s 76166 -960 76278 480 8 wbs_adr_i[18]
-port 551 nsew signal input
-rlabel metal2 s 79662 -960 79774 480 8 wbs_adr_i[19]
-port 552 nsew signal input
-rlabel metal2 s 12318 -960 12430 480 8 wbs_adr_i[1]
-port 553 nsew signal input
-rlabel metal2 s 83250 -960 83362 480 8 wbs_adr_i[20]
-port 554 nsew signal input
-rlabel metal2 s 86838 -960 86950 480 8 wbs_adr_i[21]
-port 555 nsew signal input
-rlabel metal2 s 90334 -960 90446 480 8 wbs_adr_i[22]
-port 556 nsew signal input
-rlabel metal2 s 93922 -960 94034 480 8 wbs_adr_i[23]
-port 557 nsew signal input
-rlabel metal2 s 97418 -960 97530 480 8 wbs_adr_i[24]
-port 558 nsew signal input
-rlabel metal2 s 101006 -960 101118 480 8 wbs_adr_i[25]
-port 559 nsew signal input
-rlabel metal2 s 104502 -960 104614 480 8 wbs_adr_i[26]
-port 560 nsew signal input
-rlabel metal2 s 108090 -960 108202 480 8 wbs_adr_i[27]
-port 561 nsew signal input
-rlabel metal2 s 111586 -960 111698 480 8 wbs_adr_i[28]
-port 562 nsew signal input
-rlabel metal2 s 115174 -960 115286 480 8 wbs_adr_i[29]
-port 563 nsew signal input
-rlabel metal2 s 17010 -960 17122 480 8 wbs_adr_i[2]
-port 564 nsew signal input
-rlabel metal2 s 118762 -960 118874 480 8 wbs_adr_i[30]
-port 565 nsew signal input
-rlabel metal2 s 122258 -960 122370 480 8 wbs_adr_i[31]
-port 566 nsew signal input
-rlabel metal2 s 21794 -960 21906 480 8 wbs_adr_i[3]
-port 567 nsew signal input
-rlabel metal2 s 26486 -960 26598 480 8 wbs_adr_i[4]
-port 568 nsew signal input
-rlabel metal2 s 30074 -960 30186 480 8 wbs_adr_i[5]
-port 569 nsew signal input
-rlabel metal2 s 33570 -960 33682 480 8 wbs_adr_i[6]
-port 570 nsew signal input
-rlabel metal2 s 37158 -960 37270 480 8 wbs_adr_i[7]
-port 571 nsew signal input
-rlabel metal2 s 40654 -960 40766 480 8 wbs_adr_i[8]
-port 572 nsew signal input
-rlabel metal2 s 44242 -960 44354 480 8 wbs_adr_i[9]
-port 573 nsew signal input
-rlabel metal2 s 4038 -960 4150 480 8 wbs_cyc_i
-port 574 nsew signal input
-rlabel metal2 s 8730 -960 8842 480 8 wbs_dat_i[0]
-port 575 nsew signal input
-rlabel metal2 s 48934 -960 49046 480 8 wbs_dat_i[10]
-port 576 nsew signal input
-rlabel metal2 s 52522 -960 52634 480 8 wbs_dat_i[11]
-port 577 nsew signal input
-rlabel metal2 s 56018 -960 56130 480 8 wbs_dat_i[12]
-port 578 nsew signal input
-rlabel metal2 s 59606 -960 59718 480 8 wbs_dat_i[13]
-port 579 nsew signal input
-rlabel metal2 s 63194 -960 63306 480 8 wbs_dat_i[14]
-port 580 nsew signal input
-rlabel metal2 s 66690 -960 66802 480 8 wbs_dat_i[15]
-port 581 nsew signal input
-rlabel metal2 s 70278 -960 70390 480 8 wbs_dat_i[16]
-port 582 nsew signal input
-rlabel metal2 s 73774 -960 73886 480 8 wbs_dat_i[17]
-port 583 nsew signal input
-rlabel metal2 s 77362 -960 77474 480 8 wbs_dat_i[18]
-port 584 nsew signal input
-rlabel metal2 s 80858 -960 80970 480 8 wbs_dat_i[19]
-port 585 nsew signal input
-rlabel metal2 s 13514 -960 13626 480 8 wbs_dat_i[1]
-port 586 nsew signal input
-rlabel metal2 s 84446 -960 84558 480 8 wbs_dat_i[20]
-port 587 nsew signal input
-rlabel metal2 s 87942 -960 88054 480 8 wbs_dat_i[21]
-port 588 nsew signal input
-rlabel metal2 s 91530 -960 91642 480 8 wbs_dat_i[22]
-port 589 nsew signal input
-rlabel metal2 s 95118 -960 95230 480 8 wbs_dat_i[23]
-port 590 nsew signal input
-rlabel metal2 s 98614 -960 98726 480 8 wbs_dat_i[24]
-port 591 nsew signal input
-rlabel metal2 s 102202 -960 102314 480 8 wbs_dat_i[25]
-port 592 nsew signal input
-rlabel metal2 s 105698 -960 105810 480 8 wbs_dat_i[26]
-port 593 nsew signal input
-rlabel metal2 s 109286 -960 109398 480 8 wbs_dat_i[27]
-port 594 nsew signal input
-rlabel metal2 s 112782 -960 112894 480 8 wbs_dat_i[28]
-port 595 nsew signal input
-rlabel metal2 s 116370 -960 116482 480 8 wbs_dat_i[29]
-port 596 nsew signal input
-rlabel metal2 s 18206 -960 18318 480 8 wbs_dat_i[2]
-port 597 nsew signal input
-rlabel metal2 s 119866 -960 119978 480 8 wbs_dat_i[30]
-port 598 nsew signal input
-rlabel metal2 s 123454 -960 123566 480 8 wbs_dat_i[31]
-port 599 nsew signal input
-rlabel metal2 s 22990 -960 23102 480 8 wbs_dat_i[3]
-port 600 nsew signal input
-rlabel metal2 s 27682 -960 27794 480 8 wbs_dat_i[4]
-port 601 nsew signal input
-rlabel metal2 s 31270 -960 31382 480 8 wbs_dat_i[5]
-port 602 nsew signal input
-rlabel metal2 s 34766 -960 34878 480 8 wbs_dat_i[6]
-port 603 nsew signal input
-rlabel metal2 s 38354 -960 38466 480 8 wbs_dat_i[7]
-port 604 nsew signal input
-rlabel metal2 s 41850 -960 41962 480 8 wbs_dat_i[8]
-port 605 nsew signal input
-rlabel metal2 s 45438 -960 45550 480 8 wbs_dat_i[9]
-port 606 nsew signal input
-rlabel metal2 s 9926 -960 10038 480 8 wbs_dat_o[0]
-port 607 nsew signal tristate
-rlabel metal2 s 50130 -960 50242 480 8 wbs_dat_o[10]
-port 608 nsew signal tristate
-rlabel metal2 s 53718 -960 53830 480 8 wbs_dat_o[11]
-port 609 nsew signal tristate
-rlabel metal2 s 57214 -960 57326 480 8 wbs_dat_o[12]
-port 610 nsew signal tristate
-rlabel metal2 s 60802 -960 60914 480 8 wbs_dat_o[13]
-port 611 nsew signal tristate
-rlabel metal2 s 64298 -960 64410 480 8 wbs_dat_o[14]
-port 612 nsew signal tristate
-rlabel metal2 s 67886 -960 67998 480 8 wbs_dat_o[15]
-port 613 nsew signal tristate
-rlabel metal2 s 71474 -960 71586 480 8 wbs_dat_o[16]
-port 614 nsew signal tristate
-rlabel metal2 s 74970 -960 75082 480 8 wbs_dat_o[17]
-port 615 nsew signal tristate
-rlabel metal2 s 78558 -960 78670 480 8 wbs_dat_o[18]
-port 616 nsew signal tristate
-rlabel metal2 s 82054 -960 82166 480 8 wbs_dat_o[19]
-port 617 nsew signal tristate
-rlabel metal2 s 14710 -960 14822 480 8 wbs_dat_o[1]
-port 618 nsew signal tristate
-rlabel metal2 s 85642 -960 85754 480 8 wbs_dat_o[20]
-port 619 nsew signal tristate
-rlabel metal2 s 89138 -960 89250 480 8 wbs_dat_o[21]
-port 620 nsew signal tristate
-rlabel metal2 s 92726 -960 92838 480 8 wbs_dat_o[22]
-port 621 nsew signal tristate
-rlabel metal2 s 96222 -960 96334 480 8 wbs_dat_o[23]
-port 622 nsew signal tristate
-rlabel metal2 s 99810 -960 99922 480 8 wbs_dat_o[24]
-port 623 nsew signal tristate
-rlabel metal2 s 103306 -960 103418 480 8 wbs_dat_o[25]
-port 624 nsew signal tristate
-rlabel metal2 s 106894 -960 107006 480 8 wbs_dat_o[26]
-port 625 nsew signal tristate
-rlabel metal2 s 110482 -960 110594 480 8 wbs_dat_o[27]
-port 626 nsew signal tristate
-rlabel metal2 s 113978 -960 114090 480 8 wbs_dat_o[28]
-port 627 nsew signal tristate
-rlabel metal2 s 117566 -960 117678 480 8 wbs_dat_o[29]
-port 628 nsew signal tristate
-rlabel metal2 s 19402 -960 19514 480 8 wbs_dat_o[2]
-port 629 nsew signal tristate
-rlabel metal2 s 121062 -960 121174 480 8 wbs_dat_o[30]
-port 630 nsew signal tristate
-rlabel metal2 s 124650 -960 124762 480 8 wbs_dat_o[31]
-port 631 nsew signal tristate
-rlabel metal2 s 24186 -960 24298 480 8 wbs_dat_o[3]
-port 632 nsew signal tristate
-rlabel metal2 s 28878 -960 28990 480 8 wbs_dat_o[4]
-port 633 nsew signal tristate
-rlabel metal2 s 32374 -960 32486 480 8 wbs_dat_o[5]
-port 634 nsew signal tristate
-rlabel metal2 s 35962 -960 36074 480 8 wbs_dat_o[6]
-port 635 nsew signal tristate
-rlabel metal2 s 39550 -960 39662 480 8 wbs_dat_o[7]
-port 636 nsew signal tristate
-rlabel metal2 s 43046 -960 43158 480 8 wbs_dat_o[8]
-port 637 nsew signal tristate
-rlabel metal2 s 46634 -960 46746 480 8 wbs_dat_o[9]
-port 638 nsew signal tristate
-rlabel metal2 s 11122 -960 11234 480 8 wbs_sel_i[0]
-port 639 nsew signal input
-rlabel metal2 s 15906 -960 16018 480 8 wbs_sel_i[1]
-port 640 nsew signal input
-rlabel metal2 s 20598 -960 20710 480 8 wbs_sel_i[2]
-port 641 nsew signal input
-rlabel metal2 s 25290 -960 25402 480 8 wbs_sel_i[3]
-port 642 nsew signal input
-rlabel metal2 s 5234 -960 5346 480 8 wbs_stb_i
-port 643 nsew signal input
-rlabel metal2 s 6430 -960 6542 480 8 wbs_we_i
-port 644 nsew signal input
-<< properties >>
-string FIXED_BBOX 0 0 584000 704000
-<< end >>

maglef/user_project_wrapper.lef.mag

diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.lef.mag
similarity index 100%
rename from maglef/user_project_wrapper.mag
rename to maglef/user_project_wrapper.lef.mag

verilog/dv/BrqRV_EB1/BrqRV_EB1.c

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
new file mode 100644
index 0000000..bc4267d
--- /dev/null
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
@@ -0,0 +1,121 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+void main()
+{
+
+        /* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+
+   //reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+   reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  // reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+  // reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+  reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+  
+  reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+  reg_mprj_xfer = 1;
+  while(reg_mprj_xfer == 1);
+   
+  // For CPU input keep bit 1 for output from CPU keep bit 0 
+  reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0] 
+  reg_la1_oenb = reg_la1_iena = 0xFFFF0000;    // [63:32]
+  reg_la2_oenb = reg_la2_iena = 0xFFFFFFFE;    // [95:64]
+  reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+  
+  // Set clk & reset to one
+  reg_la2_data = 0x00000001;
+  reg_la2_data = 0x00000000;
+  
+  // writing data into memory 1
+  reg_la0_data = 0x00000002; // 0
+  reg_la0_data = 0x0008000a; // 1 
+  reg_la0_data = 0x00100012; // 2
+  reg_la0_data = 0x0018001a; // 3 
+  reg_la0_data = 0x00200022; // 4
+  reg_la0_data = 0x0028002a; // 5 
+  reg_la0_data = 0x00300032; // 6
+  reg_la0_data = 0x0038003a; // 7
+  reg_la0_data = 0x00400042; // 8
+  reg_la0_data = 0x0048004a; // 9     
+  
+  // Turning off memory 1
+  reg_la0_data = 0x00000007;  
+  
+  // writing data into memory 2
+  reg_la0_data = 0x00000001; // 0
+  reg_la0_data = 0x00080009; // 1 
+  reg_la0_data = 0x00100011; // 2
+  reg_la0_data = 0x00180019; // 3 
+  reg_la0_data = 0x00200021; // 4
+  reg_la0_data = 0x00280029; // 5 
+  reg_la0_data = 0x00300031; // 6
+  reg_la0_data = 0x00380039; // 7
+  reg_la0_data = 0x00400041; // 8
+  reg_la0_data = 0x00480049; // 9     
+  
+  // Turning off memory 2
+  reg_la0_data = 0x00000007;  
+  reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0] 
+  reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+  reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+  reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+  reg_mprj_datah = 0x20;
+
+}

verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v

diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
new file mode 100644
index 0000000..11394a7
--- /dev/null
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -0,0 +1,266 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+//`include "tb_prog.v"
+
+module BrqRV_EB1_tb();
+    reg clock;
+    reg RSTB;
+    reg CSB;
+    reg power1, power2;
+    reg power3, power4;
+    
+    wire gpio;
+    wire [37:0] mprj_io;
+
+    wire [7:0] mprj_io_0;
+    wire mprj_ready;
+    reg [31:0] count;
+    
+    assign mprj_io_0 = mprj_io[34:27];
+    assign mprj_ready = mprj_io[37];
+    
+    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+    assign mprj_io[8] = (mprj_ready) ? 1'b0 : 1'b1;
+    assign mprj_io[9] = (mprj_ready) ? 1'b1 : 1'b1;
+    assign mprj_io[10] = (mprj_ready) ? 1'b1 : 1'b1;
+    assign mprj_io[35] = 1'b1;
+    assign mprj_io[26:11] = (mprj_ready) ? count : 16'h0000;
+    
+    always #12.5 clock <= (clock === 1'b0);
+    
+    initial begin
+        clock = 0;
+        count = 0;
+    end
+ 
+    always @(posedge clock) begin
+    	if(mprj_ready) begin
+    		count = count + 32'd1;
+    	end
+    end
+    		
+    initial begin
+        $dumpfile("BrqRV_EB1.vcd");
+        $dumpvars(0, BrqRV_EB1_tb);
+
+        // Repeat cycles of 1000 clock edges as needed to complete testbench
+        //repeat (300) begin
+        //    repeat (1000) @(posedge clock);
+        //end
+        //$display("%c[1;31m",27);
+        //$display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+        //$display("%c[0m",27);
+        //$finish;
+    end
+
+	initial begin
+	    $display("I am not ready");
+	    wait(mprj_ready == 1'b1)
+	    $display("I am ready");
+	    // Memory output
+	    //wait(mprj_io_0 == 8'h00);
+	    //wait(mprj_io_0 == 8'h01);
+	    //wait(mprj_io_0 == 8'h02);
+	    //wait(mprj_io_0 == 8'h03);
+	    //wait(mprj_io_0 == 8'h04);
+	    //wait(mprj_io_0 == 8'h05);
+	    //wait(mprj_io_0 == 8'h06);
+	    //wait(mprj_io_0 == 8'h07);
+	    //wait(mprj_io_0 == 8'h08);
+	    wait(mprj_io_0 == 8'h99);
+	    // Observe Output pins [35:8] for factorial
+	    /*wait(mprj_io_0 == 28'h0000001);
+	    wait(mprj_io_0 == 28'h0000002);
+	    wait(mprj_io_0 == 28'h0000006);
+    	    wait(mprj_io_0 == 28'h0000018);
+	    wait(mprj_io_0 == 28'h0000078);
+            wait(mprj_io_0 == 28'h00002D0);
+	    wait(mprj_io_0 == 28'h00013B0);
+            wait(mprj_io_0 == 28'h0009D80);
+	    wait(mprj_io_0 == 28'h0058980);
+            wait(mprj_io_0 == 28'h0375F00);
+            */
+            // Observe Output pins [35:8] for prime_num
+	    /*wait(mprj_io_0 == 28'd1);
+	    wait(mprj_io_0 == 28'd3);
+	    wait(mprj_io_0 == 28'd5);
+    	    wait(mprj_io_0 == 28'd7);
+	    wait(mprj_io_0 == 28'd11);
+            wait(mprj_io_0 == 28'd13);
+            */
+            // Observe Output pins [35:8] for multliplication_table
+            /*wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd10);
+            wait(mprj_io_0 == 28'd15);
+            wait(mprj_io_0 == 28'd20);
+            wait(mprj_io_0 == 28'd25);
+            wait(mprj_io_0 == 28'd30);
+            */
+            // Observe Output pins [35:8] for mean & Determinant
+           // wait(mprj_io_0 == 28'd5);
+            
+            // Observe Output pins [35:8] for power
+            //wait(mprj_io_0 == 28'd64);
+            
+            // Observe Output pins [35:8] for flip number
+            //wait(mprj_io_0 == 28'd4889874);
+            
+            // Observe Output pins [35:8] for Queue 
+            /*wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd7);
+            */
+            // Observe Output pins [35:8] for perfect square
+            //wait(mprj_io_0 == 28'd5);
+            
+            // Observe Output pins [35:8] for counter / ascending
+            /*wait(mprj_io_0 == 28'd0);
+            wait(mprj_io_0 == 28'd1);
+            wait(mprj_io_0 == 28'd2);
+            wait(mprj_io_0 == 28'd3);
+            wait(mprj_io_0 == 28'd4);
+            wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd7);
+            wait(mprj_io_0 == 28'd8);
+            wait(mprj_io_0 == 28'd9);
+            wait(mprj_io_0 == 28'd10);
+            wait(mprj_io_0 == 28'd11);
+            */
+            // Observe Output pin [35:8] for reverse
+            /*wait(mprj_io_0 == 28'd15);
+            wait(mprj_io_0 == 28'd14);
+            wait(mprj_io_0 == 28'd13);
+            wait(mprj_io_0 == 28'd12);
+            wait(mprj_io_0 == 28'd11);
+            wait(mprj_io_0 == 28'd10);
+            wait(mprj_io_0 == 28'd9);
+            wait(mprj_io_0 == 28'd8);
+            wait(mprj_io_0 == 28'd7);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd4); 
+            wait(mprj_io_0 == 28'd3);
+            wait(mprj_io_0 == 28'd2);
+            wait(mprj_io_0 == 28'd1);
+            wait(mprj_io_0 == 28'd0);
+            */
+            //$display("MPRJ-IO state = %d", mprj_io[35:8]);  
+		
+		`ifdef GL
+	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+		`else
+		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+		`endif
+	    $finish;
+	end
+	
+	// Reset Operation
+    initial begin
+        RSTB <= 1'b0;
+        CSB  <= 1'b1;       // Force CSB high
+        #2000;
+        RSTB <= 1'b1;       // Release reset
+        #170000;
+        CSB = 1'b0;         // CSB can be released
+    end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+	
+	always @(mprj_io) begin
+		$display("MPRJ-IO state = %h, at time = %0t  ", mprj_io[34:27], $time);
+	end
+	
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	//assign mprj_io[3:0] = 4'h0;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+
+       	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("BrqRV_EB1.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+	
+	
+	/*uartprog #(
+		.FILENAME("../hex/uart.hex")
+	) prog_uut (
+		//.clk(clock),
+		.mprj_ready (mprj_ready),
+		.r_Rx_Serial (r_Rx_Serial)
+	);*/
+
+endmodule
+`default_nettype wire
+    

verilog/dv/BrqRV_EB1/Makefile

diff --git a/verilog/dv/BrqRV_EB1/Makefile b/verilog/dv/BrqRV_EB1/Makefile
new file mode 100644
index 0000000..ba427e6
--- /dev/null
+++ b/verilog/dv/BrqRV_EB1/Makefile
@@ -0,0 +1,79 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/rams/ram_256x32_2r1w/
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC 
+#GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+#PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = BrqRV_EB1
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH_BRQ) -I $(UPRJ_RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH_BRQ) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

verilog/dv/asm/Determinent.s

diff --git a/verilog/dv/asm/Determinent.s b/verilog/dv/asm/Determinent.s
new file mode 100644
index 0000000..2408d8e
--- /dev/null
+++ b/verilog/dv/asm/Determinent.s
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+csrw minstret, zero
+csrw minstreth, zero
+li x1, 0x5f555555
+csrw 0x7c0, x1
+li x1, 4
+csrw 0x7f9, x1
+nop
+
+li x8,0xf0040000	//For Load
+li x19,STDOUT		//B.addr
+
+li	x5,4		//A1 of matrix
+sb	x5,0(x8)
+li 	x5,3		//A2 of matrix
+sb	x5,1(x8)
+li	x5,1		//A3 of matrix
+sb	x5,2(x8)
+li	x5,2		//A4 of matrix
+sb	x5,3(x8)
+
+//Determinent
+lb	x5,0(x8)		
+lb	x6,3(x8)
+mul	x7,x5,x6		//Multiply diagonal A1 and A4
+lb	x5,1(x8)
+lb	x6,2(x8)
+mul	x8,x5,x6		//Multiply diagonal A2 and A3
+sub	x5,x7,x8		//Determinent result
+sb	x5,5(x8)		//Save to DCCM
+sb	x5,0(x19)		//Save to AXI
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+

verilog/dv/asm/Power.s

diff --git a/verilog/dv/asm/Power.s b/verilog/dv/asm/Power.s
new file mode 100644
index 0000000..bfea2f0
--- /dev/null
+++ b/verilog/dv/asm/Power.s
@@ -0,0 +1,65 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+csrw minstret, zero
+csrw minstreth, zero
+li x1, 0x5f555555
+csrw 0x7c0, x1
+li x1, 4
+csrw 0x7f9, x1
+nop
+
+li x8,0xf0040000	//For Load
+li x19,STDOUT		//B.addr
+
+li x5,4  // Base number
+sb x5,0(x8)
+//li x5,4  // Base number
+//sb x5,4(x8)
+li x5,3	 // power number
+sb x5,4(x8)
+lb x5,0(x8)
+lb x6,0(x8)
+lb x7,4(x8)
+addi x7,x7,-1
+loop:
+mul x6,x6,x5
+addi x7,x7,-1
+beq x7,x0,exit
+bne x7,x0,loop
+exit:
+sb x6,0(x19)
+
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+

verilog/dv/asm/Queue_push.s

diff --git a/verilog/dv/asm/Queue_push.s b/verilog/dv/asm/Queue_push.s
new file mode 100644
index 0000000..576ff71
--- /dev/null
+++ b/verilog/dv/asm/Queue_push.s
@@ -0,0 +1,115 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+ 
+  
+  // li x1, 0x5f555555
+ //  csrw 0x7c0, x1
+
+     csrw minstret, zero
+     csrw minstreth, zero
+
+     li x4, 4        // Neccessary for terminating code
+     csrw 0x7f9 ,x4  // Neccessary for terminating code
+     
+     
+     
+     li s0, 0xf0040000  //dccm base address
+     //li s5,0xf0040100 //Queue Adress  
+
+     addi s1,x0,5 //element 1 to push  INPUT   expected output should be 5 6 7 
+     addi s2,x0,6 //element 2 to push  INPUT
+     addi s3,x0,7 //element 3 to push  INPUT
+         
+     addi s4,x0,3 //size of queue      
+
+     addi t0,x0,0 //counter initialization
+     
+     addi t1,x0,1 //
+     addi t2,x0,2 //
+     addi t3,x0,3 //
+     
+     jal ra,PUSH //JUMP to push elements
+     j LOAD_QUEUE       //code will load Queue Elements
+
+     PUSH:
+     addi t0,t0,1 //counter increment
+     beq t0,t1,PUSH1  //if count == 1 jump to push 1
+     beq t0,t2,PUSH2  //if count == 2 jump to push 2
+     beq t0,t3,PUSH3  //if count == 3 jump to push 3
+     ret
+     
+     PUSH1:
+     sw s1,0(s0) // save element 1 on first location of queue
+     j PUSH      // jump to push function
+
+     PUSH2:     
+     sw s2,4(s0) // save element 2 on second location of queue
+     j PUSH
+
+     PUSH3:
+     sw s3,8(s0) // save element 3 on third location of queue
+     j PUSH
+
+     LOAD_QUEUE:
+
+     lw x5,0(s0) 
+     lw x6,4(s0)
+     lw x7,8(s0)
+     
+     li s6,STDOUT
+
+     sw x5,0(s6)  //Sending element 1 to tb
+     addi s6, s6, 4
+     nop
+     nop
+     nop 
+     nop
+     sw x6,0(s6)  //Sending element 2 to tb
+     addi s6, s6, 4
+     nop
+     nop
+     nop
+     sw x7,0(s6)  //Sending element 3 to tb
+     nop
+     nop
+     nop
+     
+
+
+
+        
+   
+   
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/ascending_num.s

diff --git a/verilog/dv/asm/ascending_num.s b/verilog/dv/asm/ascending_num.s
new file mode 100644
index 0000000..bb55e2b
--- /dev/null
+++ b/verilog/dv/asm/ascending_num.s
@@ -0,0 +1,63 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range 
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+ 
+li x4, 4        // Neccessary for terminating code
+csrw 0x7f9 ,x4  // Neccessary for terminating code
+nop
+
+li s0,0xB // UPPER BOUND
+li t0,0 // COUNTER
+li t1,0xf0040000 // BASE ADRESS
+li t2,STDOUT
+
+LOOP:
+
+sw t0,0(t1)
+sw t0,0(t2)
+addi t2,t2,4
+addi t1,t1,4
+beq t0,s0,END
+addi t0,t0,1
+
+j LOOP
+
+END:
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/counter.s

diff --git a/verilog/dv/asm/counter.s b/verilog/dv/asm/counter.s
new file mode 100644
index 0000000..fdefc99
--- /dev/null
+++ b/verilog/dv/asm/counter.s
@@ -0,0 +1,86 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+//Counter_loop (Count/Increment 1 till 10)
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+    
+ // Code to execute
+.section .text
+.global _start
+_start:
+
+    // Clear minstret
+    csrw minstret, zero
+    csrw minstreth, zero
+    li x1, 0x5f555555
+    csrw 0x7c0, x1
+    li x1, 4
+    csrw 0x7f9, x1
+
+    li x8, 0xf0040000 // dccm address
+    li x3, STDOUT	    
+    addi x9, x0, 0xA  //no of values needs to be count 
+    addi x6, x0, 0    
+    addi x12, x0, 0   //initial value to start loop 
+    addi x11, x0, 0   //increment value from x12 save in x11 register
+    addi x13, x0, 0
+ 
+    
+store:    
+    add x5, x0, x6 
+    sw x5, 0(x8)
+    addi x6, x6, 1
+    addi x8, x8, 4
+    bne x9, x6, store
+    li x8, 0xf0040000
+    j counter_loop
+    
+next:
+    sw x11, 0(x8) 
+    addi x8, x8, 4
+    sw x11, 0(x3)
+    addi x3, x3, 4
+    beq x13, x9, _finish
+    addi x13, x13, 1
+    addi x11, x0, 1
+    addi x12, x0, 1
+    
+counter_loop:
+    
+    addi x11, x12, 1
+    beq x12, x13,  next
+    addi x12, x12, 1
+    j counter_loop
+    
+    
+    
+
+    
+	
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+

verilog/dv/asm/factorial.s

diff --git a/verilog/dv/asm/factorial.s b/verilog/dv/asm/factorial.s
new file mode 100644
index 0000000..ee00fc0
--- /dev/null
+++ b/verilog/dv/asm/factorial.s
@@ -0,0 +1,84 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+    // Clear minstret
+    csrw minstret, zero
+    csrw minstreth, zero
+    //li x1, 0x5f555555
+    //csrw 0x7c0, x1
+    li x1, 4
+    csrw 0x7f9, x1
+
+    li x8, 0xf0040000 // dccm address
+    li x3, STDOUT	
+    li x13, 0x1      // the number whose factorial needs to be calculated  1 till 10
+    addi x9, x0, 0xA
+    addi x6, x0, 0
+    addi x11, x0, 1 // initial value
+    addi x12, x0, 1 
+    nop
+    
+store:    
+    add x5, x0, x6 
+    sw x5, 0(x8)
+    addi x6, x6, 1
+    addi x8, x8, 4
+    bne x9, x6, store
+    li x8, 0xf0040000
+    j factorial_loop
+    
+next:
+    sw x11, 0(x8) 
+    addi x8, x8, 4
+    sw x11, 0(x3)
+    addi x3, x3, 4
+    beq x13, x9,  _finish
+    addi x13, x13, 1 
+    addi x11, x0, 1  
+    addi x12, x0, 1 
+    
+    
+factorial_loop:
+	mul x11, x11, x12
+	beq x12, x13, next
+	addi x12,x12,1
+	j factorial_loop
+	
+
+
+   
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+
+

verilog/dv/asm/flip_num.s

diff --git a/verilog/dv/asm/flip_num.s b/verilog/dv/asm/flip_num.s
new file mode 100644
index 0000000..af544f6
--- /dev/null
+++ b/verilog/dv/asm/flip_num.s
@@ -0,0 +1,82 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range 
+
+
+
+csrw minstret, zero
+csrw minstreth, zero
+li x1, 0x5f555555
+csrw 0x7c0, x1 
+li x4, 4        // Neccessary for terminating code
+csrw 0x7f9 ,x4  // Neccessary for terminating code
+
+
+
+li s0,4789884  //Number to reverse INPUT Expected output should be 4889874 in decimal or 4A9D12 in HEX
+li s1,7        // length of number INPUT
+li t0,10       //constant     
+li t4,4    
+li s2,0xf0040000    //base adress
+mul t3,s1,t4
+add t3,t3,s2
+sub t3,t3,t4
+sub s2,s2,t4
+addi s4,t3,0
+li t1,2
+
+LOOP:
+beqz t1,ORDER
+div t1,s0,t0
+rem t2,s0,t0
+addi s0,t1,0
+
+sb t2,0(t3)
+sub t3,t3,t4
+j LOOP
+
+
+ORDER:
+mul t6,t6,t0
+lb t5,0(s4)
+sub s4,s4,t4
+add t6,t6,t5
+
+bne s2,s4,ORDER
+
+
+END:
+li t0,STDOUT
+sw t6,0(t0)
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/mean.s

diff --git a/verilog/dv/asm/mean.s b/verilog/dv/asm/mean.s
new file mode 100644
index 0000000..3fc3b0a
--- /dev/null
+++ b/verilog/dv/asm/mean.s
@@ -0,0 +1,60 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+    
+    csrw minstret, zero
+    csrw minstreth, zero
+    li x1, 0x5f555555
+    csrw 0x7c0, x1
+    li x1, 4
+    csrw 0x7f9, x1
+nop
+li x8,0xf0040000	//For Load
+li x19,STDOUT		//B.addr
+
+li x5,4				//Value1
+sb x5,0(x8)			//Stored in loc 1
+li x5,5				//Value2
+sb x5,1(x8)			//Stored in loc 2
+li x5,6				//Value3
+sb x5,2(x8)			//Stored in loc 3
+lb x5,0(x8)			//Load 1st Value
+lb x6,1(x8)			//Load 2nd Value
+add x7,x5,x6		//Adding First two values
+lb x5,2(x8)			//Load 3rd Value
+add x6,x7,x5		//Sum of all three values
+li x5,3				//divisor value (total number of values)
+div x7,x6,x5		//MEAN
+sb x7,3(x8)         //Store to DCCM
+sb x7,0(x19)		//Store to AXI
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/multiplication_table.s

diff --git a/verilog/dv/asm/multiplication_table.s b/verilog/dv/asm/multiplication_table.s
new file mode 100644
index 0000000..b4fb7d8
--- /dev/null
+++ b/verilog/dv/asm/multiplication_table.s
@@ -0,0 +1,65 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range 
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+ 
+li x4, 4        // Neccessary for terminating code
+csrw 0x7f9 ,x4  // Neccessary for terminating code
+nop
+
+//Multiplication table
+li s0,5 // Number for table generation: INPUT  expected result= 5 10 15 20 25 30
+li s1,6 // Number of times of table:   INPUT
+li t1,0 // counter i
+li t2,0xf0040000 // memory base adress
+li t3,STDOUT 
+
+LOOP:
+addi t1,t1,1 // i++
+mul t0,s0,t1 // t0=4*i
+sw t0,0(t2)  // store t0
+sw t0,0(t3)  // store t0 to tb
+addi t2,t2,4 // increment word adress
+addi t3,t3,4 // increment word adress
+bne t1,s1,LOOP
+
+END:
+
+
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/perfect_square.s

diff --git a/verilog/dv/asm/perfect_square.s b/verilog/dv/asm/perfect_square.s
new file mode 100644
index 0000000..4bb47ef
--- /dev/null
+++ b/verilog/dv/asm/perfect_square.s
@@ -0,0 +1,58 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// SQ_root of number
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+    csrw minstret, zero
+    csrw minstreth, zero
+
+    li x4, 4        // Neccessary for terminating code
+    csrw 0x7f9 ,x4  // Neccessary for terminating code
+     
+    li x8, 0xf0040000 // dccm address
+    li x3, STDOUT // axi address	
+    li x13, 0  // initial value     
+    li x12, 25  // sqrt number
+    addi x6, x0, 0 // counter
+    li x11, 200
+
+    
+sq_root:
+    addi x6, x6, 1
+    mul x9, x6, x6
+    beq x11, x6, _finish
+    bne x12, x9, sq_root
+    sw x6, 0(x8)
+    sw x6, 0(x3)
+  
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/prime_num.s

diff --git a/verilog/dv/asm/prime_num.s b/verilog/dv/asm/prime_num.s
new file mode 100644
index 0000000..a14db49
--- /dev/null
+++ b/verilog/dv/asm/prime_num.s
@@ -0,0 +1,92 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range 
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+ 
+li x4, 4        // Neccessary for terminating code
+csrw 0x7f9 ,x4  // Neccessary for terminating code
+nop
+
+li s0,0 // count of divisors
+li s1,1 // minimun range INPUT    Expected result = 1 3 5 7 11 13
+li s2,15 // maximum range INPUT
+li t1,1 // divider
+li t2,2 
+li t5,1
+li t3,0xf0040000 //base adress
+li t4,STDOUT
+
+beq s1,t5,STORE
+LOOP2:
+addi s1,s1,2
+li t5,0
+
+LOOP:
+beq s1,s2,END
+rem t0,s1,t1
+beqz t0,INC
+addi t1,t1,1
+beq t1,s1,LOOP1
+j LOOP
+
+INC:
+addi s0,s0,1
+addi t1,t1,1
+beq t1,s1,LOOP1
+j LOOP
+
+LOOP1:
+addi s0,s0,1
+beq s0,t2,STORE
+li t1,1
+li s0,0
+addi s1,s1,1
+j LOOP
+
+STORE:
+sw s1,0(t3)
+sw s1,0(t4)
+addi t3,t3,4
+addi t4,t4,4
+beq s1,t5,LOOP2
+bne s1,s2,LOOP1
+END:
+
+
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/asm/reverse_number.s

diff --git a/verilog/dv/asm/reverse_number.s b/verilog/dv/asm/reverse_number.s
new file mode 100644
index 0000000..4fd9f78
--- /dev/null
+++ b/verilog/dv/asm/reverse_number.s
@@ -0,0 +1,65 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range 
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+ 
+li x4, 4        // Neccessary for terminating code
+csrw 0x7f9 ,x4  // Neccessary for terminating code
+nop
+
+li s0,15 // UPPER BOUND
+li t0,0 // COUNTER
+li t1,0xf0040000 // BASE ADRESS
+li t3,1
+addi t0,s0,0
+li t2,STDOUT
+
+LOOP:
+
+sw t0,0(t1)
+sw t0,0(t2)
+addi t2,t2,4
+addi t1,t1,4
+beqz t0,END
+sub t0,t0,t3
+
+j LOOP
+
+END:
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr

verilog/dv/hex/ascending_num.hex

diff --git a/verilog/dv/hex/ascending_num.hex b/verilog/dv/hex/ascending_num.hex
new file mode 100644
index 0000000..d93b3a2
--- /dev/null
+++ b/verilog/dv/hex/ascending_num.hex
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+42 81 44 2D F0 04 03 37 D0 58 03 B7 00 53 20 23
+00 53 A0 23 03 11 03 91 00 82 84 63 B7 FD 02 85
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF 

verilog/dv/hex/counter.hex

diff --git a/verilog/dv/hex/counter.hex b/verilog/dv/hex/counter.hex
new file mode 100644
index 0000000..0feda45
--- /dev/null
+++ b/verilog/dv/hex/counter.hex
@@ -0,0 +1,10 @@
+@00000000
+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
+7C 00 90 73 90 73 40 91 04 37 7F 90 01 B7 F0 04
+04 93 D0 58 03 13 00 A0 06 13 00 00 05 93 00 00
+06 93 00 00 02 B3 00 00 20 23 00 60 03 05 00 54
+9A E3 04 11 04 37 FE 64 A8 29 F0 04 04 11 C0 0C
+00 B1 A0 23 8D 63 01 91 06 85 00 96 00 10 05 93
+00 10 06 13 00 16 05 93 FE D6 02 E3 BF DD 06 05
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF 

verilog/dv/hex/determinant.hex

diff --git a/verilog/dv/hex/determinant.hex b/verilog/dv/hex/determinant.hex
new file mode 100755
index 0000000..87076f3
--- /dev/null
+++ b/verilog/dv/hex/determinant.hex
@@ -0,0 +1,9 @@
+@00000000

+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93

+7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37

+D0 58 09 B7 00 23 42 91 42 8D 00 54 00 54 00 A3

+01 23 42 85 42 89 00 54 00 54 01 A3 00 04 02 83

+00 34 03 03 02 62 83 B3 00 14 02 83 00 24 03 03

+02 62 84 33 40 83 82 B3 00 54 02 A3 00 59 80 23

+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3

+00 01 00 01 00 00 0F FF 

verilog/dv/hex/factorial.hex

diff --git a/verilog/dv/hex/factorial.hex b/verilog/dv/hex/factorial.hex
new file mode 100755
index 0000000..6a24372
--- /dev/null
+++ b/verilog/dv/hex/factorial.hex
@@ -0,0 +1,9 @@
+@00000000

+B0 20 10 73 B8 20 10 73 90 73 40 91 04 37 7F 90

+01 B7 F0 04 46 85 D0 58 00 A0 04 93 00 00 03 13

+00 10 05 93 00 10 06 13 02 B3 00 01 20 23 00 60

+03 05 00 54 9A E3 04 11 04 37 FE 64 A8 29 F0 04

+04 11 C0 0C 00 B1 A0 23 8D 63 01 91 06 85 00 96

+00 10 05 93 00 10 06 13 02 C5 85 B3 FE D6 02 E3

+BF DD 06 05 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/flip_num.hex

diff --git a/verilog/dv/hex/flip_num.hex b/verilog/dv/hex/flip_num.hex
new file mode 100755
index 0000000..d19dd5d
--- /dev/null
+++ b/verilog/dv/hex/flip_num.hex
@@ -0,0 +1,10 @@
+@00000000

+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93

+7C 00 90 73 10 73 42 11 14 37 7F 92 04 13 00 49

+44 9D 67 C4 4E 91 42 A9 F0 04 09 37 03 D4 8E 33

+0E 33 9E 4A 09 33 41 DE 0A 13 41 D9 43 09 00 0E

+00 03 0D 63 02 54 43 33 02 54 63 B3 00 03 04 13

+00 7E 00 23 41 DE 0E 33 8F B3 B7 E5 0F 03 02 5F

+0A 33 00 0A 9F FA 41 DA FF 49 19 E3 D0 58 02 B7

+01 F2 A0 23 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/mean.hex

diff --git a/verilog/dv/hex/mean.hex b/verilog/dv/hex/mean.hex
new file mode 100755
index 0000000..a1a7a1a
--- /dev/null
+++ b/verilog/dv/hex/mean.hex
@@ -0,0 +1,8 @@
+@00000000

+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93

+7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37

+D0 58 09 B7 00 23 42 91 42 95 00 54 00 54 00 A3

+01 23 42 99 02 83 00 54 03 03 00 04 83 B3 00 14

+02 83 00 62 83 33 00 24 42 8D 00 53 02 53 43 B3

+00 74 01 A3 00 79 80 23 D0 58 01 B7 0F F0 02 93

+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/multiplication_table.hex

diff --git a/verilog/dv/hex/multiplication_table.hex b/verilog/dv/hex/multiplication_table.hex
new file mode 100755
index 0000000..5509980
--- /dev/null
+++ b/verilog/dv/hex/multiplication_table.hex
@@ -0,0 +1,6 @@
+@00000000

+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92

+44 99 44 15 03 B7 43 01 0E 37 F0 04 03 05 D0 58

+02 64 02 B3 00 53 A0 23 00 5E 20 23 0E 11 03 91

+FE 93 17 E3 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/perfect_square.hex

diff --git a/verilog/dv/hex/perfect_square.hex b/verilog/dv/hex/perfect_square.hex
new file mode 100644
index 0000000..fd0b465
--- /dev/null
+++ b/verilog/dv/hex/perfect_square.hex
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92
+01 B7 F0 04 46 81 D0 58 03 13 46 65 05 93 00 00
+03 05 0C 80 02 63 04 B3 00 65 88 63 FE 96 1B E3
+00 64 20 23 00 61 A0 23 D0 58 01 B7 0F F0 02 93
+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/power.hex

diff --git a/verilog/dv/hex/power.hex b/verilog/dv/hex/power.hex
new file mode 100755
index 0000000..e8e3012
--- /dev/null
+++ b/verilog/dv/hex/power.hex
@@ -0,0 +1,8 @@
+@00000000

+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93

+7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37

+D0 58 09 B7 00 23 42 91 42 8D 00 54 00 54 02 23

+00 04 02 83 00 04 03 03 00 44 03 83 03 33 13 FD

+13 FD 02 53 00 03 84 63 FE 03 9B E3 00 69 80 23

+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3

+00 01 00 01 00 00 0F FF 

verilog/dv/hex/prime_num.hex

diff --git a/verilog/dv/hex/prime_num.hex b/verilog/dv/hex/prime_num.hex
new file mode 100755
index 0000000..c6b2a4e
--- /dev/null
+++ b/verilog/dv/hex/prime_num.hex
@@ -0,0 +1,10 @@
+@00000000

+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92

+44 85 44 01 43 05 49 3D 4F 05 43 89 F0 04 0E 37

+D0 58 0E B7 03 E4 8A 63 4F 01 04 89 05 24 80 63

+02 64 E2 B3 00 02 86 63 08 63 03 05 B7 FD 00 93

+03 05 04 05 00 93 03 63 04 05 B7 D5 00 74 06 63

+44 01 43 05 BF D9 04 85 00 9E 20 23 00 9E A0 23

+0E 91 0E 11 FD E4 82 E3 FF 24 91 E3 D0 58 01 B7

+0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01

+ 00 00 0F FF 

verilog/dv/hex/queue.hex

diff --git a/verilog/dv/hex/queue.hex b/verilog/dv/hex/queue.hex
new file mode 100755
index 0000000..5a3b56e
--- /dev/null
+++ b/verilog/dv/hex/queue.hex
@@ -0,0 +1,12 @@
+@00000000

+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92

+04 93 F0 04 09 13 00 50 09 93 00 60 0A 13 00 70

+02 93 00 30 03 13 00 00 03 93 00 10 0E 13 00 20

+00 EF 00 30 A0 0D 00 60 87 63 02 85 87 63 00 62

+88 63 00 72 80 82 01 C2 B7 FD C0 04 01 24 22 23

+24 23 B7 E5 B7 CD 01 34 00 04 22 83 00 44 23 03

+00 84 23 83 D0 58 0B 37 00 5B 20 23 00 01 0B 11

+00 01 00 01 20 23 00 01 0B 11 00 6B 00 01 00 01

+20 23 00 01 00 01 00 7B 00 01 00 01 D0 58 01 B7

+0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01

+00 00 0F FF 

verilog/dv/hex/reverse_num.hex

diff --git a/verilog/dv/hex/reverse_num.hex b/verilog/dv/hex/reverse_num.hex
new file mode 100644
index 0000000..ea36e87
--- /dev/null
+++ b/verilog/dv/hex/reverse_num.hex
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+42 81 44 3D F0 04 03 37 02 93 4E 05 03 B7 00 04
+20 23 D0 58 A0 23 00 53 03 91 00 53 85 63 03 11
+82 B3 00 02 B7 F5 41 C2 D0 58 01 B7 0F F0 02 93
+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/hex/uart.hex

diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
new file mode 100755
index 0000000..5509980
--- /dev/null
+++ b/verilog/dv/hex/uart.hex
@@ -0,0 +1,6 @@
+@00000000

+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92

+44 99 44 15 03 B7 43 01 0E 37 F0 04 03 05 D0 58

+02 64 02 B3 00 53 A0 23 00 5E 20 23 0E 11 03 91

+FE 93 17 E3 D0 58 01 B7 0F F0 02 93 00 51 80 23

+FE 00 0A E3 00 01 00 01 00 00 0F FF 

verilog/dv/tb_prog.v

diff --git a/verilog/dv/tb_prog.v b/verilog/dv/tb_prog.v
new file mode 100644
index 0000000..88e1944
--- /dev/null
+++ b/verilog/dv/tb_prog.v
@@ -0,0 +1,105 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1ns / 1ps
+
+module uartprog #(
+    parameter FILENAME="program.hex"
+)(
+    input mprj_ready,
+    output reg r_Rx_Serial // used by task UART_WRITE_BYTE
+);
+
+reg r_Clock = 0;
+parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE
+parameter c_CLOCK_PERIOD_NS = 100;
+
+reg [7:0] INSTR [16384-1:0];
+integer instr_count = 0;
+reg ready;
+reg test;
+
+always @ ( posedge r_Clock ) begin
+  if (mprj_ready) begin
+    ready <= 1'b1;
+  end else begin
+    ready <= 1'b0;
+  end
+end
+
+initial begin
+    $readmemh(FILENAME,INSTR);
+end
+
+task UART_WRITE_BYTE;
+    input [7:0] i_Data;
+    integer     ii;
+    begin
+        // Send Start Bit
+        r_Rx_Serial <= 1'b0;
+        #(c_BIT_PERIOD);
+        #1000;
+
+        // Send Data Byte
+        for (ii=0; ii<8; ii=ii+1) begin
+            r_Rx_Serial <= i_Data[ii];
+            #(c_BIT_PERIOD);
+        end
+
+        // Send Stop Bit
+        r_Rx_Serial <= 1'b1;
+        #(c_BIT_PERIOD);
+     end
+endtask // UART_WRITE_BYTE
+
+initial begin
+        test = 1'b0;
+  #1000 test = 1'b1;
+end
+
+always
+    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
+
+initial begin
+    r_Rx_Serial <= 1'b1;
+    #2000;
+    while (!ready && test) begin
+      @(posedge r_Clock)
+      r_Rx_Serial <= 1'b1;
+    end
+    while ((instr_count < 16384) && ({INSTR[instr_count],INSTR[instr_count+1],INSTR[instr_count+2],INSTR[instr_count+3]} != 32'h00000FFF)) begin
+        @(posedge r_Clock);
+        UART_WRITE_BYTE(INSTR[instr_count][7:0]);
+        @(posedge r_Clock);
+        UART_WRITE_BYTE(INSTR[instr_count+1][7:0]);
+        @(posedge r_Clock);
+        UART_WRITE_BYTE(INSTR[instr_count+2][7:0]);
+        @(posedge r_Clock);
+        UART_WRITE_BYTE(INSTR[instr_count+3][7:0]);
+        @(posedge r_Clock);
+        instr_count = instr_count + 32'd4;
+    end
+    @(posedge r_Clock);
+    UART_WRITE_BYTE(8'h00);
+    @(posedge r_Clock);
+    UART_WRITE_BYTE(8'h00);
+    @(posedge r_Clock);
+    UART_WRITE_BYTE(8'h0F);
+    @(posedge r_Clock);
+    UART_WRITE_BYTE(8'hFF);
+    @(posedge r_Clock);
+end
+
+endmodule

verilog/gl/user_proj_example.v.gz

diff --git a/verilog/gl/user_proj_example.v.gz b/verilog/gl/user_proj_example.v.gz
new file mode 100644
index 0000000..8a0eb3c
--- /dev/null
+++ b/verilog/gl/user_proj_example.v.gz
Binary files differ

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index ecae883..113f719 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -58,9 +58,8 @@
     .vssd1(vssd1),
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_cyc_i(wbs_cyc_i),
     .wbs_stb_i(wbs_stb_i),
+    .wbs_cyc_i(wbs_cyc_i),
     .wbs_we_i(wbs_we_i),
     .io_in({io_in[37],
     io_in[36],
@@ -176,9 +175,6 @@
     io_out[2],
     io_out[1],
     io_out[0]}),
-    .irq({user_irq[2],
-    user_irq[1],
-    user_irq[0]}),
     .la_data_in({la_data_in[127],
     la_data_in[126],
     la_data_in[125],
@@ -563,6 +559,9 @@
     la_oenb[2],
     la_oenb[1],
     la_oenb[0]}),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}),
     .wbs_adr_i({wbs_adr_i[31],
     wbs_adr_i[30],
     wbs_adr_i[29],

verilog/rtl/BrqRV_EB1/BrqRV_EB1.v

diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
new file mode 100644
index 0000000..f5dd676
--- /dev/null
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
@@ -0,0 +1,23083 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+
+module eb1_brqrv_wrapper (
+`ifdef USE_POWER_PINS
+	vccd1,
+	vssd1,
+`endif	
+	clk,
+	rst_l,
+	dbg_rst_l,
+	rst_vec,
+	nmi_int,
+	nmi_vec,
+	jtag_id,
+	uart_rx,
+	trace_rv_i_insn_ip,
+	trace_rv_i_address_ip,
+	trace_rv_i_valid_ip,
+	trace_rv_i_exception_ip,
+	trace_rv_i_ecause_ip,
+	trace_rv_i_interrupt_ip,
+	trace_rv_i_tval_ip,
+	lsu_axi_awvalid,
+	lsu_axi_awready,
+	lsu_axi_awid,
+	lsu_axi_awaddr,
+	lsu_axi_awregion,
+	lsu_axi_awlen,
+	lsu_axi_awsize,
+	lsu_axi_awburst,
+	lsu_axi_awlock,
+	lsu_axi_awcache,
+	lsu_axi_awprot,
+	lsu_axi_awqos,
+	lsu_axi_wvalid,
+	lsu_axi_wready,
+	lsu_axi_wdata,
+	lsu_axi_wstrb,
+	lsu_axi_wlast,
+	lsu_axi_bvalid,
+	lsu_axi_bready,
+	lsu_axi_bresp,
+	lsu_axi_bid,
+	lsu_axi_arvalid,
+	lsu_axi_arready,
+	lsu_axi_arid,
+	lsu_axi_araddr,
+	lsu_axi_arregion,
+	lsu_axi_arlen,
+	lsu_axi_arsize,
+	lsu_axi_arburst,
+	lsu_axi_arlock,
+	lsu_axi_arcache,
+	lsu_axi_arprot,
+	lsu_axi_arqos,
+	lsu_axi_rvalid,
+	lsu_axi_rready,
+	lsu_axi_rid,
+	lsu_axi_rdata,
+	lsu_axi_rresp,
+	lsu_axi_rlast,
+	ifu_axi_awvalid,
+	ifu_axi_awready,
+	ifu_axi_awid,
+	ifu_axi_awaddr,
+	ifu_axi_awregion,
+	ifu_axi_awlen,
+	ifu_axi_awsize,
+	ifu_axi_awburst,
+	ifu_axi_awlock,
+	ifu_axi_awcache,
+	ifu_axi_awprot,
+	ifu_axi_awqos,
+	ifu_axi_wvalid,
+	ifu_axi_wready,
+	ifu_axi_wdata,
+	ifu_axi_wstrb,
+	ifu_axi_wlast,
+	ifu_axi_bvalid,
+	ifu_axi_bready,
+	ifu_axi_bresp,
+	ifu_axi_bid,
+	ifu_axi_arvalid,
+	ifu_axi_arready,
+	ifu_axi_arid,
+	ifu_axi_araddr,
+	ifu_axi_arregion,
+	ifu_axi_arlen,
+	ifu_axi_arsize,
+	ifu_axi_arburst,
+	ifu_axi_arlock,
+	ifu_axi_arcache,
+	ifu_axi_arprot,
+	ifu_axi_arqos,
+	ifu_axi_rvalid,
+	ifu_axi_rready,
+	ifu_axi_rid,
+	ifu_axi_rdata,
+	ifu_axi_rresp,
+	ifu_axi_rlast,
+	sb_axi_awvalid,
+	sb_axi_awready,
+	sb_axi_awid,
+	sb_axi_awaddr,
+	sb_axi_awregion,
+	sb_axi_awlen,
+	sb_axi_awsize,
+	sb_axi_awburst,
+	sb_axi_awlock,
+	sb_axi_awcache,
+	sb_axi_awprot,
+	sb_axi_awqos,
+	sb_axi_wvalid,
+	sb_axi_wready,
+	sb_axi_wdata,
+	sb_axi_wstrb,
+	sb_axi_wlast,
+	sb_axi_bvalid,
+	sb_axi_bready,
+	sb_axi_bresp,
+	sb_axi_bid,
+	sb_axi_arvalid,
+	sb_axi_arready,
+	sb_axi_arid,
+	sb_axi_araddr,
+	sb_axi_arregion,
+	sb_axi_arlen,
+	sb_axi_arsize,
+	sb_axi_arburst,
+	sb_axi_arlock,
+	sb_axi_arcache,
+	sb_axi_arprot,
+	sb_axi_arqos,
+	sb_axi_rvalid,
+	sb_axi_rready,
+	sb_axi_rid,
+	sb_axi_rdata,
+	sb_axi_rresp,
+	sb_axi_rlast,
+	dma_axi_awvalid,
+	dma_axi_awready,
+	dma_axi_awid,
+	dma_axi_awaddr,
+	dma_axi_awsize,
+	dma_axi_awprot,
+	dma_axi_awlen,
+	dma_axi_awburst,
+	dma_axi_wvalid,
+	dma_axi_wready,
+	dma_axi_wdata,
+	dma_axi_wstrb,
+	dma_axi_wlast,
+	dma_axi_bvalid,
+	dma_axi_bready,
+	dma_axi_bresp,
+	dma_axi_bid,
+	dma_axi_arvalid,
+	dma_axi_arready,
+	dma_axi_arid,
+	dma_axi_araddr,
+	dma_axi_arsize,
+	dma_axi_arprot,
+	dma_axi_arlen,
+	dma_axi_arburst,
+	dma_axi_rvalid,
+	dma_axi_rready,
+	dma_axi_rid,
+	dma_axi_rdata,
+	dma_axi_rresp,
+	dma_axi_rlast,
+	lsu_bus_clk_en,
+	ifu_bus_clk_en,
+	dbg_bus_clk_en,
+	dma_bus_clk_en,
+	dccm_ext_in_pkt,
+	iccm_ext_in_pkt,
+	ic_data_ext_in_pkt,
+	ic_tag_ext_in_pkt,
+	timer_int,
+	soft_int,
+	extintsrc_req,
+	dec_tlu_perfcnt0,
+	dec_tlu_perfcnt1,
+	dec_tlu_perfcnt2,
+	dec_tlu_perfcnt3,
+	jtag_tck,
+	jtag_tms,
+	jtag_tdi,
+	jtag_trst_n,
+	jtag_tdo,
+	core_id,
+	mpc_debug_halt_req,
+	mpc_debug_run_req,
+	mpc_reset_run_req,
+	mpc_debug_halt_ack,
+	mpc_debug_run_ack,
+	debug_brkpt_status,
+	i_cpu_halt_req,
+	o_cpu_halt_ack,
+	o_cpu_halt_status,
+	o_debug_mode_status,
+	i_cpu_run_req,
+	o_cpu_run_ack,
+	scan_mode,
+	mbist_mode,
+	CLKS_PER_BIT
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+`ifdef USE_POWER_PINS
+	inout wire vccd1;
+	inout wire vssd1;
+`endif
+	input wire clk;
+	input wire rst_l;
+	input wire dbg_rst_l;
+	input wire [31:1] rst_vec;
+	input wire nmi_int;
+	input wire [31:1] nmi_vec;
+	input wire [31:1] jtag_id;
+	input uart_rx;
+	output wire [31:0] trace_rv_i_insn_ip;
+	output wire [31:0] trace_rv_i_address_ip;
+	output wire trace_rv_i_valid_ip;
+	output wire trace_rv_i_exception_ip;
+	output wire [4:0] trace_rv_i_ecause_ip;
+	output wire trace_rv_i_interrupt_ip;
+	output wire [31:0] trace_rv_i_tval_ip;
+	output wire lsu_axi_awvalid;
+	input wire lsu_axi_awready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_awid;
+	output wire [31:0] lsu_axi_awaddr;
+	output wire [3:0] lsu_axi_awregion;
+	output wire [7:0] lsu_axi_awlen;
+	output wire [2:0] lsu_axi_awsize;
+	output wire [1:0] lsu_axi_awburst;
+	output wire lsu_axi_awlock;
+	output wire [3:0] lsu_axi_awcache;
+	output wire [2:0] lsu_axi_awprot;
+	output wire [3:0] lsu_axi_awqos;
+	output wire lsu_axi_wvalid;
+	input wire lsu_axi_wready;
+	output wire [63:0] lsu_axi_wdata;
+	output wire [7:0] lsu_axi_wstrb;
+	output wire lsu_axi_wlast;
+	input wire lsu_axi_bvalid;
+	output wire lsu_axi_bready;
+	input wire [1:0] lsu_axi_bresp;
+	input wire [pt[181-:8] - 1:0] lsu_axi_bid;
+	output wire lsu_axi_arvalid;
+	input wire lsu_axi_arready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_arid;
+	output wire [31:0] lsu_axi_araddr;
+	output wire [3:0] lsu_axi_arregion;
+	output wire [7:0] lsu_axi_arlen;
+	output wire [2:0] lsu_axi_arsize;
+	output wire [1:0] lsu_axi_arburst;
+	output wire lsu_axi_arlock;
+	output wire [3:0] lsu_axi_arcache;
+	output wire [2:0] lsu_axi_arprot;
+	output wire [3:0] lsu_axi_arqos;
+	input wire lsu_axi_rvalid;
+	output wire lsu_axi_rready;
+	input wire [pt[181-:8] - 1:0] lsu_axi_rid;
+	input wire [63:0] lsu_axi_rdata;
+	input wire [1:0] lsu_axi_rresp;
+	input wire lsu_axi_rlast;
+	output wire ifu_axi_awvalid;
+	input wire ifu_axi_awready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_awid;
+	output wire [31:0] ifu_axi_awaddr;
+	output wire [3:0] ifu_axi_awregion;
+	output wire [7:0] ifu_axi_awlen;
+	output wire [2:0] ifu_axi_awsize;
+	output wire [1:0] ifu_axi_awburst;
+	output wire ifu_axi_awlock;
+	output wire [3:0] ifu_axi_awcache;
+	output wire [2:0] ifu_axi_awprot;
+	output wire [3:0] ifu_axi_awqos;
+	output wire ifu_axi_wvalid;
+	input wire ifu_axi_wready;
+	output wire [63:0] ifu_axi_wdata;
+	output wire [7:0] ifu_axi_wstrb;
+	output wire ifu_axi_wlast;
+	input wire ifu_axi_bvalid;
+	output wire ifu_axi_bready;
+	input wire [1:0] ifu_axi_bresp;
+	input wire [pt[826-:8] - 1:0] ifu_axi_bid;
+	output wire ifu_axi_arvalid;
+	input wire ifu_axi_arready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_arid;
+	output wire [31:0] ifu_axi_araddr;
+	output wire [3:0] ifu_axi_arregion;
+	output wire [7:0] ifu_axi_arlen;
+	output wire [2:0] ifu_axi_arsize;
+	output wire [1:0] ifu_axi_arburst;
+	output wire ifu_axi_arlock;
+	output wire [3:0] ifu_axi_arcache;
+	output wire [2:0] ifu_axi_arprot;
+	output wire [3:0] ifu_axi_arqos;
+	input wire ifu_axi_rvalid;
+	output wire ifu_axi_rready;
+	input wire [pt[826-:8] - 1:0] ifu_axi_rid;
+	input wire [63:0] ifu_axi_rdata;
+	input wire [1:0] ifu_axi_rresp;
+	input wire ifu_axi_rlast;
+	output wire sb_axi_awvalid;
+	input wire sb_axi_awready;
+	output wire [pt[12-:8] - 1:0] sb_axi_awid;
+	output wire [31:0] sb_axi_awaddr;
+	output wire [3:0] sb_axi_awregion;
+	output wire [7:0] sb_axi_awlen;
+	output wire [2:0] sb_axi_awsize;
+	output wire [1:0] sb_axi_awburst;
+	output wire sb_axi_awlock;
+	output wire [3:0] sb_axi_awcache;
+	output wire [2:0] sb_axi_awprot;
+	output wire [3:0] sb_axi_awqos;
+	output wire sb_axi_wvalid;
+	input wire sb_axi_wready;
+	output wire [63:0] sb_axi_wdata;
+	output wire [7:0] sb_axi_wstrb;
+	output wire sb_axi_wlast;
+	input wire sb_axi_bvalid;
+	output wire sb_axi_bready;
+	input wire [1:0] sb_axi_bresp;
+	input wire [pt[12-:8] - 1:0] sb_axi_bid;
+	output wire sb_axi_arvalid;
+	input wire sb_axi_arready;
+	output wire [pt[12-:8] - 1:0] sb_axi_arid;
+	output wire [31:0] sb_axi_araddr;
+	output wire [3:0] sb_axi_arregion;
+	output wire [7:0] sb_axi_arlen;
+	output wire [2:0] sb_axi_arsize;
+	output wire [1:0] sb_axi_arburst;
+	output wire sb_axi_arlock;
+	output wire [3:0] sb_axi_arcache;
+	output wire [2:0] sb_axi_arprot;
+	output wire [3:0] sb_axi_arqos;
+	input wire sb_axi_rvalid;
+	output wire sb_axi_rready;
+	input wire [pt[12-:8] - 1:0] sb_axi_rid;
+	input wire [63:0] sb_axi_rdata;
+	input wire [1:0] sb_axi_rresp;
+	input wire sb_axi_rlast;
+	input wire dma_axi_awvalid;
+	output wire dma_axi_awready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_awid;
+	input wire [31:0] dma_axi_awaddr;
+	input wire [2:0] dma_axi_awsize;
+	input wire [2:0] dma_axi_awprot;
+	input wire [7:0] dma_axi_awlen;
+	input wire [1:0] dma_axi_awburst;
+	input wire dma_axi_wvalid;
+	output wire dma_axi_wready;
+	input wire [63:0] dma_axi_wdata;
+	input wire [7:0] dma_axi_wstrb;
+	input wire dma_axi_wlast;
+	output wire dma_axi_bvalid;
+	input wire dma_axi_bready;
+	output wire [1:0] dma_axi_bresp;
+	output wire [pt[1235-:8] - 1:0] dma_axi_bid;
+	input wire dma_axi_arvalid;
+	output wire dma_axi_arready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_arid;
+	input wire [31:0] dma_axi_araddr;
+	input wire [2:0] dma_axi_arsize;
+	input wire [2:0] dma_axi_arprot;
+	input wire [7:0] dma_axi_arlen;
+	input wire [1:0] dma_axi_arburst;
+	output wire dma_axi_rvalid;
+	input wire dma_axi_rready;
+	output wire [pt[1235-:8] - 1:0] dma_axi_rid;
+	output wire [63:0] dma_axi_rdata;
+	output wire [1:0] dma_axi_rresp;
+	output wire dma_axi_rlast;
+	input wire lsu_bus_clk_en;
+	input wire ifu_bus_clk_en;
+	input wire dbg_bus_clk_en;
+	input wire dma_bus_clk_en;
+	input wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt;
+	input wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt;
+	input wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt;
+	input wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt;
+	input wire timer_int;
+	input wire soft_int;
+	input wire [pt[56-:12]:1] extintsrc_req;
+	output wire dec_tlu_perfcnt0;
+	output wire dec_tlu_perfcnt1;
+	output wire dec_tlu_perfcnt2;
+	output wire dec_tlu_perfcnt3;
+	input wire jtag_tck;
+	input wire jtag_tms;
+	input wire jtag_tdi;
+	input wire jtag_trst_n;
+	output wire jtag_tdo;
+	input wire [31:4] core_id;
+	input wire mpc_debug_halt_req;
+	input wire mpc_debug_run_req;
+	input wire mpc_reset_run_req;
+	output wire mpc_debug_halt_ack;
+	output wire mpc_debug_run_ack;
+	output wire debug_brkpt_status;
+	input wire i_cpu_halt_req;
+	output wire o_cpu_halt_ack;
+	output wire o_cpu_halt_status;
+	output wire o_debug_mode_status;
+	input wire i_cpu_run_req;
+	output wire o_cpu_run_ack;
+	input wire scan_mode;
+	input wire mbist_mode;
+	input [15:0] CLKS_PER_BIT;
+	wire active_l2clk;
+	wire free_l2clk;
+	wire dccm_wren;
+	wire dccm_rden;
+	wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	wire [31:1] ic_rw_addr;
+	wire [pt[1060-:7] - 1:0] ic_wr_en;
+	wire ic_rd_en;
+	wire [pt[1060-:7] - 1:0] ic_tag_valid;
+	wire [pt[1060-:7] - 1:0] ic_rd_hit;
+	wire ic_tag_perr;
+	wire [pt[1104-:9]:3] ic_debug_addr;
+	wire ic_debug_rd_en;
+	wire ic_debug_wr_en;
+	wire ic_debug_tag_array;
+	wire [pt[1060-:7] - 1:0] ic_debug_way;
+	wire [25:0] ictag_debug_rd_data;
+	wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data;
+	wire [63:0] ic_rd_data;
+	wire [70:0] ic_debug_rd_data;
+	wire [70:0] ic_debug_wr_data;
+	wire [pt[1189-:7] - 1:0] ic_eccerr;
+	wire [pt[1189-:7] - 1:0] ic_parerr;
+	wire [63:0] ic_premux_data;
+	wire ic_sel_premux_data;
+	wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	wire iccm_wren;
+	wire iccm_rden;
+	wire [2:0] iccm_wr_size;
+	wire [77:0] iccm_wr_data;
+	wire iccm_buf_correct_ecc;
+	wire iccm_correction_state;
+	wire [63:0] iccm_rd_data;
+	wire [77:0] iccm_rd_data_ecc;
+	wire core_rst;
+	wire core_rst_l;
+	wire jtag_tdoEn;
+	wire dccm_clk_override;
+	wire icm_clk_override;
+	wire dec_tlu_core_ecc_disable;
+	wire [31:0] haddr;
+	wire [2:0] hburst;
+	wire hmastlock;
+	wire [3:0] hprot;
+	wire [2:0] hsize;
+	wire [1:0] htrans;
+	wire hwrite;
+	wire [63:0] hrdata;
+	wire hready;
+	wire hresp;
+	wire [31:0] lsu_haddr;
+	wire [2:0] lsu_hburst;
+	wire lsu_hmastlock;
+	wire [3:0] lsu_hprot;
+	wire [2:0] lsu_hsize;
+	wire [1:0] lsu_htrans;
+	wire lsu_hwrite;
+	wire [63:0] lsu_hwdata;
+	wire [63:0] lsu_hrdata;
+	wire lsu_hready;
+	wire lsu_hresp;
+	wire [31:0] sb_haddr;
+	wire [2:0] sb_hburst;
+	wire sb_hmastlock;
+	wire [3:0] sb_hprot;
+	wire [2:0] sb_hsize;
+	wire [1:0] sb_htrans;
+	wire sb_hwrite;
+	wire [63:0] sb_hwdata;
+	wire [63:0] sb_hrdata;
+	wire sb_hready;
+	wire sb_hresp;
+	wire dma_hsel;
+	wire [31:0] dma_haddr;
+	wire [2:0] dma_hburst;
+	wire dma_hmastlock;
+	wire [3:0] dma_hprot;
+	wire [2:0] dma_hsize;
+	wire [1:0] dma_htrans;
+	wire dma_hwrite;
+	wire [63:0] dma_hwdata;
+	wire dma_hreadyin;
+	wire [63:0] dma_hrdata;
+	wire dma_hreadyout;
+	wire dma_hresp;
+	assign hrdata[63:0] = {64 {1'sb0}};
+	assign hready = 1'b0;
+	assign hresp = 1'b0;
+	assign lsu_hrdata[63:0] = {64 {1'sb0}};
+	assign lsu_hready = 1'b0;
+	assign lsu_hresp = 1'b0;
+	assign sb_hrdata[63:0] = {64 {1'sb0}};
+	assign sb_hready = 1'b0;
+	assign sb_hresp = 1'b0;
+	assign dma_hsel = 1'b0;
+	assign dma_haddr[31:0] = {32 {1'sb0}};
+	assign dma_hburst[2:0] = {3 {1'sb0}};
+	assign dma_hmastlock = 1'b0;
+	assign dma_hprot[3:0] = {4 {1'sb0}};
+	assign dma_hsize[2:0] = {3 {1'sb0}};
+	assign dma_htrans[1:0] = {2 {1'sb0}};
+	assign dma_hwrite = 1'b0;
+	assign dma_hwdata[63:0] = {64 {1'sb0}};
+	assign dma_hreadyin = 1'b0;
+	wire dmi_reg_en;
+	wire [6:0] dmi_reg_addr;
+	wire dmi_reg_wr_en;
+	wire [31:0] dmi_reg_wdata;
+	wire [31:0] dmi_reg_rdata;
+	wire rx_dv_i;
+	wire [7:0] rx_byte_i;
+	wire iccm_instr_we;
+	wire [13:0] iccm_instr_addr;
+	wire [31:0] iccm_instr_wdata;
+	eb1_brqrv #(.pt(pt)) brqrv(
+		.clk(clk),
+		.rst_l(core_rst),
+		.dbg_rst_l(dbg_rst_l),
+		.rst_vec(rst_vec),
+		.nmi_int(nmi_int),
+		.nmi_vec(nmi_vec),
+		.core_rst_l(core_rst_l),
+		.active_l2clk(active_l2clk),
+		.free_l2clk(free_l2clk),
+		.trace_rv_i_insn_ip(trace_rv_i_insn_ip),
+		.trace_rv_i_address_ip(trace_rv_i_address_ip),
+		.trace_rv_i_valid_ip(trace_rv_i_valid_ip),
+		.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
+		.trace_rv_i_ecause_ip(trace_rv_i_ecause_ip),
+		.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
+		.trace_rv_i_tval_ip(trace_rv_i_tval_ip),
+		.dccm_clk_override(dccm_clk_override),
+		.icm_clk_override(icm_clk_override),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.i_cpu_halt_req(i_cpu_halt_req),
+		.i_cpu_run_req(i_cpu_run_req),
+		.o_cpu_halt_ack(o_cpu_halt_ack),
+		.o_cpu_halt_status(o_cpu_halt_status),
+		.o_cpu_run_ack(o_cpu_run_ack),
+		.o_debug_mode_status(o_debug_mode_status),
+		.core_id(core_id),
+		.mpc_debug_halt_req(mpc_debug_halt_req),
+		.mpc_debug_run_req(mpc_debug_run_req),
+		.mpc_reset_run_req(mpc_reset_run_req),
+		.mpc_debug_halt_ack(mpc_debug_halt_ack),
+		.mpc_debug_run_ack(mpc_debug_run_ack),
+		.debug_brkpt_status(debug_brkpt_status),
+		.dec_tlu_perfcnt0(dec_tlu_perfcnt0),
+		.dec_tlu_perfcnt1(dec_tlu_perfcnt1),
+		.dec_tlu_perfcnt2(dec_tlu_perfcnt2),
+		.dec_tlu_perfcnt3(dec_tlu_perfcnt3),
+		.dccm_wren(dccm_wren),
+		.dccm_rden(dccm_rden),
+		.dccm_wr_addr_lo(dccm_wr_addr_lo),
+		.dccm_wr_addr_hi(dccm_wr_addr_hi),
+		.dccm_rd_addr_lo(dccm_rd_addr_lo),
+		.dccm_rd_addr_hi(dccm_rd_addr_hi),
+		.dccm_wr_data_lo(dccm_wr_data_lo),
+		.dccm_wr_data_hi(dccm_wr_data_hi),
+		.dccm_rd_data_lo(dccm_rd_data_lo),
+		.dccm_rd_data_hi(dccm_rd_data_hi),
+		.iccm_rw_addr(iccm_rw_addr),
+		.iccm_wren(iccm_wren),
+		.iccm_rden(iccm_rden),
+		.iccm_wr_size(iccm_wr_size),
+		.iccm_wr_data(iccm_wr_data),
+		.iccm_buf_correct_ecc(iccm_buf_correct_ecc),
+		.iccm_correction_state(iccm_correction_state),
+		.iccm_rd_data(iccm_rd_data),
+		.iccm_rd_data_ecc(iccm_rd_data_ecc),
+		.ic_rw_addr(ic_rw_addr),
+		.ic_tag_valid(ic_tag_valid),
+		.ic_wr_en(ic_wr_en),
+		.ic_rd_en(ic_rd_en),
+		.ic_wr_data(ic_wr_data),
+		.ic_rd_data(ic_rd_data),
+		.ic_debug_rd_data(ic_debug_rd_data),
+		.ictag_debug_rd_data(ictag_debug_rd_data),
+		.ic_debug_wr_data(ic_debug_wr_data),
+		.ic_eccerr(ic_eccerr),
+		.ic_parerr(ic_parerr),
+		.ic_premux_data(ic_premux_data),
+		.ic_sel_premux_data(ic_sel_premux_data),
+		.ic_debug_addr(ic_debug_addr),
+		.ic_debug_rd_en(ic_debug_rd_en),
+		.ic_debug_wr_en(ic_debug_wr_en),
+		.ic_debug_tag_array(ic_debug_tag_array),
+		.ic_debug_way(ic_debug_way),
+		.ic_rd_hit(ic_rd_hit),
+		.ic_tag_perr(ic_tag_perr),
+		.lsu_axi_awvalid(lsu_axi_awvalid),
+		.lsu_axi_awready(lsu_axi_awready),
+		.lsu_axi_awid(lsu_axi_awid),
+		.lsu_axi_awaddr(lsu_axi_awaddr),
+		.lsu_axi_awregion(lsu_axi_awregion),
+		.lsu_axi_awlen(lsu_axi_awlen),
+		.lsu_axi_awsize(lsu_axi_awsize),
+		.lsu_axi_awburst(lsu_axi_awburst),
+		.lsu_axi_awlock(lsu_axi_awlock),
+		.lsu_axi_awcache(lsu_axi_awcache),
+		.lsu_axi_awprot(lsu_axi_awprot),
+		.lsu_axi_awqos(lsu_axi_awqos),
+		.lsu_axi_wvalid(lsu_axi_wvalid),
+		.lsu_axi_wready(lsu_axi_wready),
+		.lsu_axi_wdata(lsu_axi_wdata),
+		.lsu_axi_wstrb(lsu_axi_wstrb),
+		.lsu_axi_wlast(lsu_axi_wlast),
+		.lsu_axi_bvalid(lsu_axi_bvalid),
+		.lsu_axi_bready(lsu_axi_bready),
+		.lsu_axi_bresp(lsu_axi_bresp),
+		.lsu_axi_bid(lsu_axi_bid),
+		.lsu_axi_arvalid(lsu_axi_arvalid),
+		.lsu_axi_arready(lsu_axi_arready),
+		.lsu_axi_arid(lsu_axi_arid),
+		.lsu_axi_araddr(lsu_axi_araddr),
+		.lsu_axi_arregion(lsu_axi_arregion),
+		.lsu_axi_arlen(lsu_axi_arlen),
+		.lsu_axi_arsize(lsu_axi_arsize),
+		.lsu_axi_arburst(lsu_axi_arburst),
+		.lsu_axi_arlock(lsu_axi_arlock),
+		.lsu_axi_arcache(lsu_axi_arcache),
+		.lsu_axi_arprot(lsu_axi_arprot),
+		.lsu_axi_arqos(lsu_axi_arqos),
+		.lsu_axi_rvalid(lsu_axi_rvalid),
+		.lsu_axi_rready(lsu_axi_rready),
+		.lsu_axi_rid(lsu_axi_rid),
+		.lsu_axi_rdata(lsu_axi_rdata),
+		.lsu_axi_rresp(lsu_axi_rresp),
+		.lsu_axi_rlast(lsu_axi_rlast),
+		.ifu_axi_awvalid(ifu_axi_awvalid),
+		.ifu_axi_awready(ifu_axi_awready),
+		.ifu_axi_awid(ifu_axi_awid),
+		.ifu_axi_awaddr(ifu_axi_awaddr),
+		.ifu_axi_awregion(ifu_axi_awregion),
+		.ifu_axi_awlen(ifu_axi_awlen),
+		.ifu_axi_awsize(ifu_axi_awsize),
+		.ifu_axi_awburst(ifu_axi_awburst),
+		.ifu_axi_awlock(ifu_axi_awlock),
+		.ifu_axi_awcache(ifu_axi_awcache),
+		.ifu_axi_awprot(ifu_axi_awprot),
+		.ifu_axi_awqos(ifu_axi_awqos),
+		.ifu_axi_wvalid(ifu_axi_wvalid),
+		.ifu_axi_wready(ifu_axi_wready),
+		.ifu_axi_wdata(ifu_axi_wdata),
+		.ifu_axi_wstrb(ifu_axi_wstrb),
+		.ifu_axi_wlast(ifu_axi_wlast),
+		.ifu_axi_bvalid(ifu_axi_bvalid),
+		.ifu_axi_bready(ifu_axi_bready),
+		.ifu_axi_bresp(ifu_axi_bresp),
+		.ifu_axi_bid(ifu_axi_bid),
+		.ifu_axi_arvalid(ifu_axi_arvalid),
+		.ifu_axi_arready(ifu_axi_arready),
+		.ifu_axi_arid(ifu_axi_arid),
+		.ifu_axi_araddr(ifu_axi_araddr),
+		.ifu_axi_arregion(ifu_axi_arregion),
+		.ifu_axi_arlen(ifu_axi_arlen),
+		.ifu_axi_arsize(ifu_axi_arsize),
+		.ifu_axi_arburst(ifu_axi_arburst),
+		.ifu_axi_arlock(ifu_axi_arlock),
+		.ifu_axi_arcache(ifu_axi_arcache),
+		.ifu_axi_arprot(ifu_axi_arprot),
+		.ifu_axi_arqos(ifu_axi_arqos),
+		.ifu_axi_rvalid(ifu_axi_rvalid),
+		.ifu_axi_rready(ifu_axi_rready),
+		.ifu_axi_rid(ifu_axi_rid),
+		.ifu_axi_rdata(ifu_axi_rdata),
+		.ifu_axi_rresp(ifu_axi_rresp),
+		.ifu_axi_rlast(ifu_axi_rlast),
+		.sb_axi_awvalid(sb_axi_awvalid),
+		.sb_axi_awready(sb_axi_awready),
+		.sb_axi_awid(sb_axi_awid),
+		.sb_axi_awaddr(sb_axi_awaddr),
+		.sb_axi_awregion(sb_axi_awregion),
+		.sb_axi_awlen(sb_axi_awlen),
+		.sb_axi_awsize(sb_axi_awsize),
+		.sb_axi_awburst(sb_axi_awburst),
+		.sb_axi_awlock(sb_axi_awlock),
+		.sb_axi_awcache(sb_axi_awcache),
+		.sb_axi_awprot(sb_axi_awprot),
+		.sb_axi_awqos(sb_axi_awqos),
+		.sb_axi_wvalid(sb_axi_wvalid),
+		.sb_axi_wready(sb_axi_wready),
+		.sb_axi_wdata(sb_axi_wdata),
+		.sb_axi_wstrb(sb_axi_wstrb),
+		.sb_axi_wlast(sb_axi_wlast),
+		.sb_axi_bvalid(sb_axi_bvalid),
+		.sb_axi_bready(sb_axi_bready),
+		.sb_axi_bresp(sb_axi_bresp),
+		.sb_axi_bid(sb_axi_bid),
+		.sb_axi_arvalid(sb_axi_arvalid),
+		.sb_axi_arready(sb_axi_arready),
+		.sb_axi_arid(sb_axi_arid),
+		.sb_axi_araddr(sb_axi_araddr),
+		.sb_axi_arregion(sb_axi_arregion),
+		.sb_axi_arlen(sb_axi_arlen),
+		.sb_axi_arsize(sb_axi_arsize),
+		.sb_axi_arburst(sb_axi_arburst),
+		.sb_axi_arlock(sb_axi_arlock),
+		.sb_axi_arcache(sb_axi_arcache),
+		.sb_axi_arprot(sb_axi_arprot),
+		.sb_axi_arqos(sb_axi_arqos),
+		.sb_axi_rvalid(sb_axi_rvalid),
+		.sb_axi_rready(sb_axi_rready),
+		.sb_axi_rid(sb_axi_rid),
+		.sb_axi_rdata(sb_axi_rdata),
+		.sb_axi_rresp(sb_axi_rresp),
+		.sb_axi_rlast(sb_axi_rlast),
+		.dma_axi_awvalid(dma_axi_awvalid),
+		.dma_axi_awready(dma_axi_awready),
+		.dma_axi_awid(dma_axi_awid),
+		.dma_axi_awaddr(dma_axi_awaddr),
+		.dma_axi_awsize(dma_axi_awsize),
+		.dma_axi_awprot(dma_axi_awprot),
+		.dma_axi_awlen(dma_axi_awlen),
+		.dma_axi_awburst(dma_axi_awburst),
+		.dma_axi_wvalid(dma_axi_wvalid),
+		.dma_axi_wready(dma_axi_wready),
+		.dma_axi_wdata(dma_axi_wdata),
+		.dma_axi_wstrb(dma_axi_wstrb),
+		.dma_axi_wlast(dma_axi_wlast),
+		.dma_axi_bvalid(dma_axi_bvalid),
+		.dma_axi_bready(dma_axi_bready),
+		.dma_axi_bresp(dma_axi_bresp),
+		.dma_axi_bid(dma_axi_bid),
+		.dma_axi_arvalid(dma_axi_arvalid),
+		.dma_axi_arready(dma_axi_arready),
+		.dma_axi_arid(dma_axi_arid),
+		.dma_axi_araddr(dma_axi_araddr),
+		.dma_axi_arsize(dma_axi_arsize),
+		.dma_axi_arprot(dma_axi_arprot),
+		.dma_axi_arlen(dma_axi_arlen),
+		.dma_axi_arburst(dma_axi_arburst),
+		.dma_axi_rvalid(dma_axi_rvalid),
+		.dma_axi_rready(dma_axi_rready),
+		.dma_axi_rid(dma_axi_rid),
+		.dma_axi_rdata(dma_axi_rdata),
+		.dma_axi_rresp(dma_axi_rresp),
+		.dma_axi_rlast(dma_axi_rlast),
+		.haddr(haddr),
+		.hburst(hburst),
+		.hmastlock(hmastlock),
+		.hprot(hprot),
+		.hsize(hsize),
+		.htrans(htrans),
+		.hwrite(hwrite),
+		.hrdata(hrdata),
+		.hready(hready),
+		.hresp(hresp),
+		.lsu_haddr(lsu_haddr),
+		.lsu_hburst(lsu_hburst),
+		.lsu_hmastlock(lsu_hmastlock),
+		.lsu_hprot(lsu_hprot),
+		.lsu_hsize(lsu_hsize),
+		.lsu_htrans(lsu_htrans),
+		.lsu_hwrite(lsu_hwrite),
+		.lsu_hwdata(lsu_hwdata),
+		.lsu_hrdata(lsu_hrdata),
+		.lsu_hready(lsu_hready),
+		.lsu_hresp(lsu_hresp),
+		.sb_haddr(sb_haddr),
+		.sb_hburst(sb_hburst),
+		.sb_hmastlock(sb_hmastlock),
+		.sb_hprot(sb_hprot),
+		.sb_hsize(sb_hsize),
+		.sb_htrans(sb_htrans),
+		.sb_hwrite(sb_hwrite),
+		.sb_hwdata(sb_hwdata),
+		.sb_hrdata(sb_hrdata),
+		.sb_hready(sb_hready),
+		.sb_hresp(sb_hresp),
+		.dma_hsel(dma_hsel),
+		.dma_haddr(dma_haddr),
+		.dma_hburst(dma_hburst),
+		.dma_hmastlock(dma_hmastlock),
+		.dma_hprot(dma_hprot),
+		.dma_hsize(dma_hsize),
+		.dma_htrans(dma_htrans),
+		.dma_hwrite(dma_hwrite),
+		.dma_hwdata(dma_hwdata),
+		.dma_hreadyin(dma_hreadyin),
+		.dma_hrdata(dma_hrdata),
+		.dma_hreadyout(dma_hreadyout),
+		.dma_hresp(dma_hresp),
+		.lsu_bus_clk_en(lsu_bus_clk_en),
+		.ifu_bus_clk_en(ifu_bus_clk_en),
+		.dbg_bus_clk_en(dbg_bus_clk_en),
+		.dma_bus_clk_en(dma_bus_clk_en),
+		.dmi_reg_en(dmi_reg_en),
+		.dmi_reg_addr(dmi_reg_addr),
+		.dmi_reg_wr_en(dmi_reg_wr_en),
+		.dmi_reg_wdata(dmi_reg_wdata),
+		.dmi_reg_rdata(dmi_reg_rdata),
+		.extintsrc_req(extintsrc_req),
+		.timer_int(timer_int),
+		.soft_int(soft_int),
+		.scan_mode(scan_mode)
+	);
+	eb1_mem #(.pt(pt)) mem(
+		.clk(active_l2clk),
+		.rst_l(rst_l),
+		.iccm_rw_addr((core_rst ? iccm_rw_addr : iccm_instr_addr[10:0])),
+		.iccm_wren((core_rst ? iccm_wren : iccm_instr_we)),
+		.iccm_wr_data((core_rst ? iccm_wr_data : {7'h00, iccm_instr_wdata, 7'h00, iccm_instr_wdata})),
+		.iccm_wr_size((core_rst ? iccm_wr_size : 3'b010)),
+		`ifdef USE_POWER_PINS
+		.vccd1(vccd1),
+		.vssd1(vssd1),
+		`endif
+		.dccm_clk_override(dccm_clk_override),
+		.icm_clk_override(icm_clk_override),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.dccm_wren(dccm_wren),
+		.dccm_rden(dccm_rden),
+		.dccm_wr_addr_lo(dccm_wr_addr_lo),
+		.dccm_wr_addr_hi(dccm_wr_addr_hi),
+		.dccm_rd_addr_lo(dccm_rd_addr_lo),
+		.dccm_rd_addr_hi(dccm_rd_addr_hi),
+		.dccm_wr_data_lo(dccm_wr_data_lo),
+		.dccm_wr_data_hi(dccm_wr_data_hi),
+		.dccm_rd_data_lo(dccm_rd_data_lo),
+		.dccm_rd_data_hi(dccm_rd_data_hi),
+		.dccm_ext_in_pkt(dccm_ext_in_pkt),
+		.iccm_ext_in_pkt(iccm_ext_in_pkt),
+		.iccm_buf_correct_ecc(iccm_buf_correct_ecc),
+		.iccm_correction_state(iccm_correction_state),
+		.iccm_rden(iccm_rden),
+		.iccm_rd_data(iccm_rd_data),
+		.iccm_rd_data_ecc(iccm_rd_data_ecc),
+		.ic_rw_addr(ic_rw_addr),
+		.ic_tag_valid(ic_tag_valid),
+		.ic_wr_en(ic_wr_en),
+		.ic_rd_en(ic_rd_en),
+		.ic_premux_data(ic_premux_data),
+		.ic_sel_premux_data(ic_sel_premux_data),
+		.ic_data_ext_in_pkt(ic_data_ext_in_pkt),
+		.ic_tag_ext_in_pkt(ic_tag_ext_in_pkt),
+		.ic_wr_data(ic_wr_data),
+		.ic_debug_wr_data(ic_debug_wr_data),
+		.ic_debug_rd_data(ic_debug_rd_data),
+		.ic_debug_addr(ic_debug_addr),
+		.ic_debug_rd_en(ic_debug_rd_en),
+		.ic_debug_wr_en(ic_debug_wr_en),
+		.ic_debug_tag_array(ic_debug_tag_array),
+		.ic_debug_way(ic_debug_way),
+		.ic_rd_data(ic_rd_data),
+		.ictag_debug_rd_data(ictag_debug_rd_data),
+		.ic_eccerr(ic_eccerr),
+		.ic_parerr(ic_parerr),
+		.ic_rd_hit(ic_rd_hit),
+		.ic_tag_perr(ic_tag_perr),
+		.scan_mode(scan_mode)
+	);
+	eb1_iccm_controller iccm_controller(
+		.clk_i(clk),
+		.rst_ni(rst_l),
+		.rx_dv_i(rx_dv_i),
+		.rx_byte_i(rx_byte_i),
+		.we_o(iccm_instr_we),
+		.addr_o(iccm_instr_addr),
+		.wdata_o(iccm_instr_wdata),
+		.reset_o(core_rst)
+	);
+	
+	always @(iccm_instr_we) begin
+	$display("Instruction = %h", iccm_instr_wdata);
+	end
+	
+	eb1_uart_rx_prog uart_rx_m(
+		.i_Clock(clk),
+		.rst_ni(rst_l),
+		.i_Rx_Serial(uart_rx),
+		.CLKS_PER_BIT(CLKS_PER_BIT),
+		.o_Rx_DV(rx_dv_i),
+		.o_Rx_Byte(rx_byte_i)
+	);
+	dmi_wrapper dmi_wrapper(
+		.trst_n(jtag_trst_n),
+		.tck(jtag_tck),
+		.tms(jtag_tms),
+		.tdi(jtag_tdi),
+		.tdo(jtag_tdo),
+		.tdoEnable(),
+		.core_rst_n(dbg_rst_l),
+		.core_clk(clk),
+		.jtag_id(jtag_id),
+		.rd_data(dmi_reg_rdata),
+		.reg_wr_data(dmi_reg_wdata),
+		.reg_wr_addr(dmi_reg_addr),
+		.reg_en(dmi_reg_en),
+		.reg_wr_en(dmi_reg_wr_en),
+		.dmi_hard_reset()
+	);
+endmodule
+module eb1_brqrv (
+	clk,
+	rst_l,
+	dbg_rst_l,
+	rst_vec,
+	nmi_int,
+	nmi_vec,
+	core_rst_l,
+	active_l2clk,
+	free_l2clk,
+	trace_rv_i_insn_ip,
+	trace_rv_i_address_ip,
+	trace_rv_i_valid_ip,
+	trace_rv_i_exception_ip,
+	trace_rv_i_ecause_ip,
+	trace_rv_i_interrupt_ip,
+	trace_rv_i_tval_ip,
+	dccm_clk_override,
+	icm_clk_override,
+	dec_tlu_core_ecc_disable,
+	i_cpu_halt_req,
+	i_cpu_run_req,
+	o_cpu_halt_ack,
+	o_cpu_halt_status,
+	o_cpu_run_ack,
+	o_debug_mode_status,
+	core_id,
+	mpc_debug_halt_req,
+	mpc_debug_run_req,
+	mpc_reset_run_req,
+	mpc_debug_halt_ack,
+	mpc_debug_run_ack,
+	debug_brkpt_status,
+	dec_tlu_perfcnt0,
+	dec_tlu_perfcnt1,
+	dec_tlu_perfcnt2,
+	dec_tlu_perfcnt3,
+	dccm_wren,
+	dccm_rden,
+	dccm_wr_addr_lo,
+	dccm_wr_addr_hi,
+	dccm_rd_addr_lo,
+	dccm_rd_addr_hi,
+	dccm_wr_data_lo,
+	dccm_wr_data_hi,
+	dccm_rd_data_lo,
+	dccm_rd_data_hi,
+	iccm_rw_addr,
+	iccm_wren,
+	iccm_rden,
+	iccm_wr_size,
+	iccm_wr_data,
+	iccm_buf_correct_ecc,
+	iccm_correction_state,
+	iccm_rd_data,
+	iccm_rd_data_ecc,
+	ic_rw_addr,
+	ic_tag_valid,
+	ic_wr_en,
+	ic_rd_en,
+	ic_wr_data,
+	ic_rd_data,
+	ic_debug_rd_data,
+	ictag_debug_rd_data,
+	ic_debug_wr_data,
+	ic_eccerr,
+	ic_parerr,
+	ic_premux_data,
+	ic_sel_premux_data,
+	ic_debug_addr,
+	ic_debug_rd_en,
+	ic_debug_wr_en,
+	ic_debug_tag_array,
+	ic_debug_way,
+	ic_rd_hit,
+	ic_tag_perr,
+	lsu_axi_awvalid,
+	lsu_axi_awready,
+	lsu_axi_awid,
+	lsu_axi_awaddr,
+	lsu_axi_awregion,
+	lsu_axi_awlen,
+	lsu_axi_awsize,
+	lsu_axi_awburst,
+	lsu_axi_awlock,
+	lsu_axi_awcache,
+	lsu_axi_awprot,
+	lsu_axi_awqos,
+	lsu_axi_wvalid,
+	lsu_axi_wready,
+	lsu_axi_wdata,
+	lsu_axi_wstrb,
+	lsu_axi_wlast,
+	lsu_axi_bvalid,
+	lsu_axi_bready,
+	lsu_axi_bresp,
+	lsu_axi_bid,
+	lsu_axi_arvalid,
+	lsu_axi_arready,
+	lsu_axi_arid,
+	lsu_axi_araddr,
+	lsu_axi_arregion,
+	lsu_axi_arlen,
+	lsu_axi_arsize,
+	lsu_axi_arburst,
+	lsu_axi_arlock,
+	lsu_axi_arcache,
+	lsu_axi_arprot,
+	lsu_axi_arqos,
+	lsu_axi_rvalid,
+	lsu_axi_rready,
+	lsu_axi_rid,
+	lsu_axi_rdata,
+	lsu_axi_rresp,
+	lsu_axi_rlast,
+	ifu_axi_awvalid,
+	ifu_axi_awready,
+	ifu_axi_awid,
+	ifu_axi_awaddr,
+	ifu_axi_awregion,
+	ifu_axi_awlen,
+	ifu_axi_awsize,
+	ifu_axi_awburst,
+	ifu_axi_awlock,
+	ifu_axi_awcache,
+	ifu_axi_awprot,
+	ifu_axi_awqos,
+	ifu_axi_wvalid,
+	ifu_axi_wready,
+	ifu_axi_wdata,
+	ifu_axi_wstrb,
+	ifu_axi_wlast,
+	ifu_axi_bvalid,
+	ifu_axi_bready,
+	ifu_axi_bresp,
+	ifu_axi_bid,
+	ifu_axi_arvalid,
+	ifu_axi_arready,
+	ifu_axi_arid,
+	ifu_axi_araddr,
+	ifu_axi_arregion,
+	ifu_axi_arlen,
+	ifu_axi_arsize,
+	ifu_axi_arburst,
+	ifu_axi_arlock,
+	ifu_axi_arcache,
+	ifu_axi_arprot,
+	ifu_axi_arqos,
+	ifu_axi_rvalid,
+	ifu_axi_rready,
+	ifu_axi_rid,
+	ifu_axi_rdata,
+	ifu_axi_rresp,
+	ifu_axi_rlast,
+	sb_axi_awvalid,
+	sb_axi_awready,
+	sb_axi_awid,
+	sb_axi_awaddr,
+	sb_axi_awregion,
+	sb_axi_awlen,
+	sb_axi_awsize,
+	sb_axi_awburst,
+	sb_axi_awlock,
+	sb_axi_awcache,
+	sb_axi_awprot,
+	sb_axi_awqos,
+	sb_axi_wvalid,
+	sb_axi_wready,
+	sb_axi_wdata,
+	sb_axi_wstrb,
+	sb_axi_wlast,
+	sb_axi_bvalid,
+	sb_axi_bready,
+	sb_axi_bresp,
+	sb_axi_bid,
+	sb_axi_arvalid,
+	sb_axi_arready,
+	sb_axi_arid,
+	sb_axi_araddr,
+	sb_axi_arregion,
+	sb_axi_arlen,
+	sb_axi_arsize,
+	sb_axi_arburst,
+	sb_axi_arlock,
+	sb_axi_arcache,
+	sb_axi_arprot,
+	sb_axi_arqos,
+	sb_axi_rvalid,
+	sb_axi_rready,
+	sb_axi_rid,
+	sb_axi_rdata,
+	sb_axi_rresp,
+	sb_axi_rlast,
+	dma_axi_awvalid,
+	dma_axi_awready,
+	dma_axi_awid,
+	dma_axi_awaddr,
+	dma_axi_awsize,
+	dma_axi_awprot,
+	dma_axi_awlen,
+	dma_axi_awburst,
+	dma_axi_wvalid,
+	dma_axi_wready,
+	dma_axi_wdata,
+	dma_axi_wstrb,
+	dma_axi_wlast,
+	dma_axi_bvalid,
+	dma_axi_bready,
+	dma_axi_bresp,
+	dma_axi_bid,
+	dma_axi_arvalid,
+	dma_axi_arready,
+	dma_axi_arid,
+	dma_axi_araddr,
+	dma_axi_arsize,
+	dma_axi_arprot,
+	dma_axi_arlen,
+	dma_axi_arburst,
+	dma_axi_rvalid,
+	dma_axi_rready,
+	dma_axi_rid,
+	dma_axi_rdata,
+	dma_axi_rresp,
+	dma_axi_rlast,
+	haddr,
+	hburst,
+	hmastlock,
+	hprot,
+	hsize,
+	htrans,
+	hwrite,
+	hrdata,
+	hready,
+	hresp,
+	lsu_haddr,
+	lsu_hburst,
+	lsu_hmastlock,
+	lsu_hprot,
+	lsu_hsize,
+	lsu_htrans,
+	lsu_hwrite,
+	lsu_hwdata,
+	lsu_hrdata,
+	lsu_hready,
+	lsu_hresp,
+	sb_haddr,
+	sb_hburst,
+	sb_hmastlock,
+	sb_hprot,
+	sb_hsize,
+	sb_htrans,
+	sb_hwrite,
+	sb_hwdata,
+	sb_hrdata,
+	sb_hready,
+	sb_hresp,
+	dma_hsel,
+	dma_haddr,
+	dma_hburst,
+	dma_hmastlock,
+	dma_hprot,
+	dma_hsize,
+	dma_htrans,
+	dma_hwrite,
+	dma_hwdata,
+	dma_hreadyin,
+	dma_hrdata,
+	dma_hreadyout,
+	dma_hresp,
+	lsu_bus_clk_en,
+	ifu_bus_clk_en,
+	dbg_bus_clk_en,
+	dma_bus_clk_en,
+	dmi_reg_en,
+	dmi_reg_addr,
+	dmi_reg_wr_en,
+	dmi_reg_wdata,
+	dmi_reg_rdata,
+	extintsrc_req,
+	timer_int,
+	soft_int,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire dbg_rst_l;
+	input wire [31:1] rst_vec;
+	input wire nmi_int;
+	input wire [31:1] nmi_vec;
+	output wire core_rst_l;
+	output wire active_l2clk;
+	output wire free_l2clk;
+	output wire [31:0] trace_rv_i_insn_ip;
+	output wire [31:0] trace_rv_i_address_ip;
+	output wire trace_rv_i_valid_ip;
+	output wire trace_rv_i_exception_ip;
+	output wire [4:0] trace_rv_i_ecause_ip;
+	output wire trace_rv_i_interrupt_ip;
+	output wire [31:0] trace_rv_i_tval_ip;
+	output wire dccm_clk_override;
+	output wire icm_clk_override;
+	output wire dec_tlu_core_ecc_disable;
+	input wire i_cpu_halt_req;
+	input wire i_cpu_run_req;
+	output wire o_cpu_halt_ack;
+	output wire o_cpu_halt_status;
+	output wire o_cpu_run_ack;
+	output wire o_debug_mode_status;
+	input wire [31:4] core_id;
+	input wire mpc_debug_halt_req;
+	input wire mpc_debug_run_req;
+	input wire mpc_reset_run_req;
+	output wire mpc_debug_halt_ack;
+	output wire mpc_debug_run_ack;
+	output wire debug_brkpt_status;
+	output wire dec_tlu_perfcnt0;
+	output wire dec_tlu_perfcnt1;
+	output wire dec_tlu_perfcnt2;
+	output wire dec_tlu_perfcnt3;
+	output wire dccm_wren;
+	output wire dccm_rden;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	output wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	output wire iccm_wren;
+	output wire iccm_rden;
+	output wire [2:0] iccm_wr_size;
+	output wire [77:0] iccm_wr_data;
+	output wire iccm_buf_correct_ecc;
+	output wire iccm_correction_state;
+	input wire [63:0] iccm_rd_data;
+	input wire [77:0] iccm_rd_data_ecc;
+	output wire [31:1] ic_rw_addr;
+	output wire [pt[1060-:7] - 1:0] ic_tag_valid;
+	output wire [pt[1060-:7] - 1:0] ic_wr_en;
+	output wire ic_rd_en;
+	output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data;
+	input wire [63:0] ic_rd_data;
+	input wire [70:0] ic_debug_rd_data;
+	input wire [25:0] ictag_debug_rd_data;
+	output wire [70:0] ic_debug_wr_data;
+	input wire [pt[1189-:7] - 1:0] ic_eccerr;
+	input wire [pt[1189-:7] - 1:0] ic_parerr;
+	output wire [63:0] ic_premux_data;
+	output wire ic_sel_premux_data;
+	output wire [pt[1104-:9]:3] ic_debug_addr;
+	output wire ic_debug_rd_en;
+	output wire ic_debug_wr_en;
+	output wire ic_debug_tag_array;
+	output wire [pt[1060-:7] - 1:0] ic_debug_way;
+	input wire [pt[1060-:7] - 1:0] ic_rd_hit;
+	input wire ic_tag_perr;
+	output wire lsu_axi_awvalid;
+	input wire lsu_axi_awready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_awid;
+	output wire [31:0] lsu_axi_awaddr;
+	output wire [3:0] lsu_axi_awregion;
+	output wire [7:0] lsu_axi_awlen;
+	output wire [2:0] lsu_axi_awsize;
+	output wire [1:0] lsu_axi_awburst;
+	output wire lsu_axi_awlock;
+	output wire [3:0] lsu_axi_awcache;
+	output wire [2:0] lsu_axi_awprot;
+	output wire [3:0] lsu_axi_awqos;
+	output wire lsu_axi_wvalid;
+	input wire lsu_axi_wready;
+	output wire [63:0] lsu_axi_wdata;
+	output wire [7:0] lsu_axi_wstrb;
+	output wire lsu_axi_wlast;
+	input wire lsu_axi_bvalid;
+	output wire lsu_axi_bready;
+	input wire [1:0] lsu_axi_bresp;
+	input wire [pt[181-:8] - 1:0] lsu_axi_bid;
+	output wire lsu_axi_arvalid;
+	input wire lsu_axi_arready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_arid;
+	output wire [31:0] lsu_axi_araddr;
+	output wire [3:0] lsu_axi_arregion;
+	output wire [7:0] lsu_axi_arlen;
+	output wire [2:0] lsu_axi_arsize;
+	output wire [1:0] lsu_axi_arburst;
+	output wire lsu_axi_arlock;
+	output wire [3:0] lsu_axi_arcache;
+	output wire [2:0] lsu_axi_arprot;
+	output wire [3:0] lsu_axi_arqos;
+	input wire lsu_axi_rvalid;
+	output wire lsu_axi_rready;
+	input wire [pt[181-:8] - 1:0] lsu_axi_rid;
+	input wire [63:0] lsu_axi_rdata;
+	input wire [1:0] lsu_axi_rresp;
+	input wire lsu_axi_rlast;
+	output wire ifu_axi_awvalid;
+	input wire ifu_axi_awready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_awid;
+	output wire [31:0] ifu_axi_awaddr;
+	output wire [3:0] ifu_axi_awregion;
+	output wire [7:0] ifu_axi_awlen;
+	output wire [2:0] ifu_axi_awsize;
+	output wire [1:0] ifu_axi_awburst;
+	output wire ifu_axi_awlock;
+	output wire [3:0] ifu_axi_awcache;
+	output wire [2:0] ifu_axi_awprot;
+	output wire [3:0] ifu_axi_awqos;
+	output wire ifu_axi_wvalid;
+	input wire ifu_axi_wready;
+	output wire [63:0] ifu_axi_wdata;
+	output wire [7:0] ifu_axi_wstrb;
+	output wire ifu_axi_wlast;
+	input wire ifu_axi_bvalid;
+	output wire ifu_axi_bready;
+	input wire [1:0] ifu_axi_bresp;
+	input wire [pt[826-:8] - 1:0] ifu_axi_bid;
+	output wire ifu_axi_arvalid;
+	input wire ifu_axi_arready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_arid;
+	output wire [31:0] ifu_axi_araddr;
+	output wire [3:0] ifu_axi_arregion;
+	output wire [7:0] ifu_axi_arlen;
+	output wire [2:0] ifu_axi_arsize;
+	output wire [1:0] ifu_axi_arburst;
+	output wire ifu_axi_arlock;
+	output wire [3:0] ifu_axi_arcache;
+	output wire [2:0] ifu_axi_arprot;
+	output wire [3:0] ifu_axi_arqos;
+	input wire ifu_axi_rvalid;
+	output wire ifu_axi_rready;
+	input wire [pt[826-:8] - 1:0] ifu_axi_rid;
+	input wire [63:0] ifu_axi_rdata;
+	input wire [1:0] ifu_axi_rresp;
+	input wire ifu_axi_rlast;
+	output wire sb_axi_awvalid;
+	input wire sb_axi_awready;
+	output wire [pt[12-:8] - 1:0] sb_axi_awid;
+	output wire [31:0] sb_axi_awaddr;
+	output wire [3:0] sb_axi_awregion;
+	output wire [7:0] sb_axi_awlen;
+	output wire [2:0] sb_axi_awsize;
+	output wire [1:0] sb_axi_awburst;
+	output wire sb_axi_awlock;
+	output wire [3:0] sb_axi_awcache;
+	output wire [2:0] sb_axi_awprot;
+	output wire [3:0] sb_axi_awqos;
+	output wire sb_axi_wvalid;
+	input wire sb_axi_wready;
+	output wire [63:0] sb_axi_wdata;
+	output wire [7:0] sb_axi_wstrb;
+	output wire sb_axi_wlast;
+	input wire sb_axi_bvalid;
+	output wire sb_axi_bready;
+	input wire [1:0] sb_axi_bresp;
+	input wire [pt[12-:8] - 1:0] sb_axi_bid;
+	output wire sb_axi_arvalid;
+	input wire sb_axi_arready;
+	output wire [pt[12-:8] - 1:0] sb_axi_arid;
+	output wire [31:0] sb_axi_araddr;
+	output wire [3:0] sb_axi_arregion;
+	output wire [7:0] sb_axi_arlen;
+	output wire [2:0] sb_axi_arsize;
+	output wire [1:0] sb_axi_arburst;
+	output wire sb_axi_arlock;
+	output wire [3:0] sb_axi_arcache;
+	output wire [2:0] sb_axi_arprot;
+	output wire [3:0] sb_axi_arqos;
+	input wire sb_axi_rvalid;
+	output wire sb_axi_rready;
+	input wire [pt[12-:8] - 1:0] sb_axi_rid;
+	input wire [63:0] sb_axi_rdata;
+	input wire [1:0] sb_axi_rresp;
+	input wire sb_axi_rlast;
+	input wire dma_axi_awvalid;
+	output wire dma_axi_awready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_awid;
+	input wire [31:0] dma_axi_awaddr;
+	input wire [2:0] dma_axi_awsize;
+	input wire [2:0] dma_axi_awprot;
+	input wire [7:0] dma_axi_awlen;
+	input wire [1:0] dma_axi_awburst;
+	input wire dma_axi_wvalid;
+	output wire dma_axi_wready;
+	input wire [63:0] dma_axi_wdata;
+	input wire [7:0] dma_axi_wstrb;
+	input wire dma_axi_wlast;
+	output wire dma_axi_bvalid;
+	input wire dma_axi_bready;
+	output wire [1:0] dma_axi_bresp;
+	output wire [pt[1235-:8] - 1:0] dma_axi_bid;
+	input wire dma_axi_arvalid;
+	output wire dma_axi_arready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_arid;
+	input wire [31:0] dma_axi_araddr;
+	input wire [2:0] dma_axi_arsize;
+	input wire [2:0] dma_axi_arprot;
+	input wire [7:0] dma_axi_arlen;
+	input wire [1:0] dma_axi_arburst;
+	output wire dma_axi_rvalid;
+	input wire dma_axi_rready;
+	output wire [pt[1235-:8] - 1:0] dma_axi_rid;
+	output wire [63:0] dma_axi_rdata;
+	output wire [1:0] dma_axi_rresp;
+	output wire dma_axi_rlast;
+	output wire [31:0] haddr;
+	output wire [2:0] hburst;
+	output wire hmastlock;
+	output wire [3:0] hprot;
+	output wire [2:0] hsize;
+	output wire [1:0] htrans;
+	output wire hwrite;
+	input wire [63:0] hrdata;
+	input wire hready;
+	input wire hresp;
+	output wire [31:0] lsu_haddr;
+	output wire [2:0] lsu_hburst;
+	output wire lsu_hmastlock;
+	output wire [3:0] lsu_hprot;
+	output wire [2:0] lsu_hsize;
+	output wire [1:0] lsu_htrans;
+	output wire lsu_hwrite;
+	output wire [63:0] lsu_hwdata;
+	input wire [63:0] lsu_hrdata;
+	input wire lsu_hready;
+	input wire lsu_hresp;
+	output wire [31:0] sb_haddr;
+	output wire [2:0] sb_hburst;
+	output wire sb_hmastlock;
+	output wire [3:0] sb_hprot;
+	output wire [2:0] sb_hsize;
+	output wire [1:0] sb_htrans;
+	output wire sb_hwrite;
+	output wire [63:0] sb_hwdata;
+	input wire [63:0] sb_hrdata;
+	input wire sb_hready;
+	input wire sb_hresp;
+	input wire dma_hsel;
+	input wire [31:0] dma_haddr;
+	input wire [2:0] dma_hburst;
+	input wire dma_hmastlock;
+	input wire [3:0] dma_hprot;
+	input wire [2:0] dma_hsize;
+	input wire [1:0] dma_htrans;
+	input wire dma_hwrite;
+	input wire [63:0] dma_hwdata;
+	input wire dma_hreadyin;
+	output wire [63:0] dma_hrdata;
+	output wire dma_hreadyout;
+	output wire dma_hresp;
+	input wire lsu_bus_clk_en;
+	input wire ifu_bus_clk_en;
+	input wire dbg_bus_clk_en;
+	input wire dma_bus_clk_en;
+	input wire dmi_reg_en;
+	input wire [6:0] dmi_reg_addr;
+	input wire dmi_reg_wr_en;
+	input wire [31:0] dmi_reg_wdata;
+	output wire [31:0] dmi_reg_rdata;
+	input wire [pt[56-:12]:1] extintsrc_req;
+	input wire timer_int;
+	input wire soft_int;
+	input wire scan_mode;
+	wire [63:0] hwdata_nc;
+	wire ifu_pmu_instr_aligned;
+	wire ifu_ic_error_start;
+	wire ifu_iccm_rd_ecc_single_err;
+	wire lsu_axi_awready_ahb;
+	wire lsu_axi_wready_ahb;
+	wire lsu_axi_bvalid_ahb;
+	wire lsu_axi_bready_ahb;
+	wire [1:0] lsu_axi_bresp_ahb;
+	wire [pt[181-:8] - 1:0] lsu_axi_bid_ahb;
+	wire lsu_axi_arready_ahb;
+	wire lsu_axi_rvalid_ahb;
+	wire [pt[181-:8] - 1:0] lsu_axi_rid_ahb;
+	wire [63:0] lsu_axi_rdata_ahb;
+	wire [1:0] lsu_axi_rresp_ahb;
+	wire lsu_axi_rlast_ahb;
+	wire lsu_axi_awready_int;
+	wire lsu_axi_wready_int;
+	wire lsu_axi_bvalid_int;
+	wire lsu_axi_bready_int;
+	wire [1:0] lsu_axi_bresp_int;
+	wire [pt[181-:8] - 1:0] lsu_axi_bid_int;
+	wire lsu_axi_arready_int;
+	wire lsu_axi_rvalid_int;
+	wire [pt[181-:8] - 1:0] lsu_axi_rid_int;
+	wire [63:0] lsu_axi_rdata_int;
+	wire [1:0] lsu_axi_rresp_int;
+	wire lsu_axi_rlast_int;
+	wire ifu_axi_awready_ahb;
+	wire ifu_axi_wready_ahb;
+	wire ifu_axi_bvalid_ahb;
+	wire ifu_axi_bready_ahb;
+	wire [1:0] ifu_axi_bresp_ahb;
+	wire [pt[826-:8] - 1:0] ifu_axi_bid_ahb;
+	wire ifu_axi_arready_ahb;
+	wire ifu_axi_rvalid_ahb;
+	wire [pt[826-:8] - 1:0] ifu_axi_rid_ahb;
+	wire [63:0] ifu_axi_rdata_ahb;
+	wire [1:0] ifu_axi_rresp_ahb;
+	wire ifu_axi_rlast_ahb;
+	wire ifu_axi_awready_int;
+	wire ifu_axi_wready_int;
+	wire ifu_axi_bvalid_int;
+	wire ifu_axi_bready_int;
+	wire [1:0] ifu_axi_bresp_int;
+	wire [pt[826-:8] - 1:0] ifu_axi_bid_int;
+	wire ifu_axi_arready_int;
+	wire ifu_axi_rvalid_int;
+	wire [pt[826-:8] - 1:0] ifu_axi_rid_int;
+	wire [63:0] ifu_axi_rdata_int;
+	wire [1:0] ifu_axi_rresp_int;
+	wire ifu_axi_rlast_int;
+	wire sb_axi_awready_ahb;
+	wire sb_axi_wready_ahb;
+	wire sb_axi_bvalid_ahb;
+	wire sb_axi_bready_ahb;
+	wire [1:0] sb_axi_bresp_ahb;
+	wire [pt[12-:8] - 1:0] sb_axi_bid_ahb;
+	wire sb_axi_arready_ahb;
+	wire sb_axi_rvalid_ahb;
+	wire [pt[12-:8] - 1:0] sb_axi_rid_ahb;
+	wire [63:0] sb_axi_rdata_ahb;
+	wire [1:0] sb_axi_rresp_ahb;
+	wire sb_axi_rlast_ahb;
+	wire sb_axi_awready_int;
+	wire sb_axi_wready_int;
+	wire sb_axi_bvalid_int;
+	wire sb_axi_bready_int;
+	wire [1:0] sb_axi_bresp_int;
+	wire [pt[12-:8] - 1:0] sb_axi_bid_int;
+	wire sb_axi_arready_int;
+	wire sb_axi_rvalid_int;
+	wire [pt[12-:8] - 1:0] sb_axi_rid_int;
+	wire [63:0] sb_axi_rdata_int;
+	wire [1:0] sb_axi_rresp_int;
+	wire sb_axi_rlast_int;
+	wire dma_axi_awvalid_ahb;
+	wire [pt[1235-:8] - 1:0] dma_axi_awid_ahb;
+	wire [31:0] dma_axi_awaddr_ahb;
+	wire [2:0] dma_axi_awsize_ahb;
+	wire [2:0] dma_axi_awprot_ahb;
+	wire [7:0] dma_axi_awlen_ahb;
+	wire [1:0] dma_axi_awburst_ahb;
+	wire dma_axi_wvalid_ahb;
+	wire [63:0] dma_axi_wdata_ahb;
+	wire [7:0] dma_axi_wstrb_ahb;
+	wire dma_axi_wlast_ahb;
+	wire dma_axi_bready_ahb;
+	wire dma_axi_arvalid_ahb;
+	wire [pt[1235-:8] - 1:0] dma_axi_arid_ahb;
+	wire [31:0] dma_axi_araddr_ahb;
+	wire [2:0] dma_axi_arsize_ahb;
+	wire [2:0] dma_axi_arprot_ahb;
+	wire [7:0] dma_axi_arlen_ahb;
+	wire [1:0] dma_axi_arburst_ahb;
+	wire dma_axi_rready_ahb;
+	wire dma_axi_awvalid_int;
+	wire [pt[1235-:8] - 1:0] dma_axi_awid_int;
+	wire [31:0] dma_axi_awaddr_int;
+	wire [2:0] dma_axi_awsize_int;
+	wire [2:0] dma_axi_awprot_int;
+	wire [7:0] dma_axi_awlen_int;
+	wire [1:0] dma_axi_awburst_int;
+	wire dma_axi_wvalid_int;
+	wire [63:0] dma_axi_wdata_int;
+	wire [7:0] dma_axi_wstrb_int;
+	wire dma_axi_wlast_int;
+	wire dma_axi_bready_int;
+	wire dma_axi_arvalid_int;
+	wire [pt[1235-:8] - 1:0] dma_axi_arid_int;
+	wire [31:0] dma_axi_araddr_int;
+	wire [2:0] dma_axi_arsize_int;
+	wire [2:0] dma_axi_arprot_int;
+	wire [7:0] dma_axi_arlen_int;
+	wire [1:0] dma_axi_arburst_int;
+	wire dma_axi_rready_int;
+	wire [70:0] ifu_ic_debug_rd_data;
+	wire ifu_ic_debug_rd_data_valid;
+	wire [89:0] dec_tlu_ic_diag_pkt;
+	wire dec_i0_rs1_en_d;
+	wire dec_i0_rs2_en_d;
+	wire [31:0] gpr_i0_rs1_d;
+	wire [31:0] gpr_i0_rs2_d;
+	wire [31:0] dec_i0_result_r;
+	wire [31:0] exu_i0_result_x;
+	wire [31:1] exu_i0_pc_x;
+	wire [31:1] exu_npc_r;
+	wire [43:0] i0_ap;
+	wire [151:0] trigger_pkt_any;
+	wire [3:0] lsu_trigger_match_m;
+	wire [31:0] dec_i0_immed_d;
+	wire [12:1] dec_i0_br_immed_d;
+	wire dec_i0_select_pc_d;
+	wire [31:1] dec_i0_pc_d;
+	wire [3:0] dec_i0_rs1_bypass_en_d;
+	wire [3:0] dec_i0_rs2_bypass_en_d;
+	wire dec_i0_alu_decode_d;
+	wire dec_i0_branch_d;
+	wire ifu_miss_state_idle;
+	wire dec_tlu_flush_noredir_r;
+	wire dec_tlu_flush_leak_one_r;
+	wire dec_tlu_flush_err_r;
+	wire ifu_i0_valid;
+	wire [31:0] ifu_i0_instr;
+	wire [31:1] ifu_i0_pc;
+	wire exu_flush_final;
+	wire [31:1] exu_flush_path_final;
+	wire [31:0] exu_lsu_rs1_d;
+	wire [31:0] exu_lsu_rs2_d;
+	wire [13:0] lsu_p;
+	wire dec_qual_lsu_d;
+	wire dec_lsu_valid_raw_d;
+	wire [11:0] dec_lsu_offset_d;
+	wire [31:0] lsu_result_m;
+	wire [31:0] lsu_result_corr_r;
+	wire lsu_single_ecc_error_incr;
+	wire [39:0] lsu_error_pkt_r;
+	wire lsu_imprecise_error_load_any;
+	wire lsu_imprecise_error_store_any;
+	wire [31:0] lsu_imprecise_error_addr_any;
+	wire lsu_load_stall_any;
+	wire lsu_store_stall_any;
+	wire lsu_idle_any;
+	wire lsu_active;
+	wire [31:1] lsu_fir_addr;
+	wire [1:0] lsu_fir_error;
+	wire lsu_nonblock_load_valid_m;
+	wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	wire lsu_nonblock_load_inv_r;
+	wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	wire lsu_nonblock_load_data_valid;
+	wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	wire [31:0] lsu_nonblock_load_data;
+	wire dec_csr_ren_d;
+	wire [31:0] dec_csr_rddata_d;
+	wire [31:0] exu_csr_rs1_x;
+	wire dec_tlu_i0_commit_cmt;
+	wire dec_tlu_flush_lower_r;
+	wire dec_tlu_flush_lower_wb;
+	wire dec_tlu_i0_kill_writeb_r;
+	wire dec_tlu_fence_i_r;
+	wire [31:1] dec_tlu_flush_path_r;
+	wire [31:0] dec_tlu_mrac_ff;
+	wire ifu_i0_pc4;
+	wire [19:0] mul_p;
+	wire [2:0] div_p;
+	wire dec_div_cancel;
+	wire [31:0] exu_div_result;
+	wire exu_div_wren;
+	wire dec_i0_decode_d;
+	wire [31:1] pred_correct_npc_x;
+	wire [6:0] dec_tlu_br0_r_pkt;
+	wire [55:0] exu_mp_pkt;
+	wire [pt[2236-:8] - 1:0] exu_mp_eghr;
+	wire [pt[2236-:8] - 1:0] exu_mp_fghr;
+	wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index;
+	wire [pt[2139-:9] - 1:0] exu_mp_btag;
+	wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r;
+	wire [1:0] exu_i0_br_hist_r;
+	wire exu_i0_br_error_r;
+	wire exu_i0_br_start_error_r;
+	wire exu_i0_br_valid_r;
+	wire exu_i0_br_mp_r;
+	wire exu_i0_br_middle_r;
+	wire exu_i0_br_way_r;
+	wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r;
+	wire dma_dccm_req;
+	wire dma_iccm_req;
+	wire [2:0] dma_mem_tag;
+	wire [31:0] dma_mem_addr;
+	wire [2:0] dma_mem_sz;
+	wire dma_mem_write;
+	wire [63:0] dma_mem_wdata;
+	wire dccm_dma_rvalid;
+	wire dccm_dma_ecc_error;
+	wire [2:0] dccm_dma_rtag;
+	wire [63:0] dccm_dma_rdata;
+	wire iccm_dma_rvalid;
+	wire iccm_dma_ecc_error;
+	wire [2:0] iccm_dma_rtag;
+	wire [63:0] iccm_dma_rdata;
+	wire dma_dccm_stall_any;
+	wire dma_iccm_stall_any;
+	wire dccm_ready;
+	wire iccm_ready;
+	wire dma_pmu_dccm_read;
+	wire dma_pmu_dccm_write;
+	wire dma_pmu_any_read;
+	wire dma_pmu_any_write;
+	wire ifu_i0_icaf;
+	wire [1:0] ifu_i0_icaf_type;
+	wire ifu_i0_icaf_second;
+	wire ifu_i0_dbecc;
+	wire iccm_dma_sb_error;
+	wire [50:0] i0_brp;
+	wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index;
+	wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr;
+	wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag;
+	wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index;
+	wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index;
+	wire [55:0] dec_i0_predict_p_d;
+	wire [pt[2236-:8] - 1:0] i0_predict_fghr_d;
+	wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d;
+	wire [pt[2139-:9] - 1:0] i0_predict_btag_d;
+	wire picm_wren;
+	wire picm_rden;
+	wire picm_mken;
+	wire [31:0] picm_rdaddr;
+	wire [31:0] picm_wraddr;
+	wire [31:0] picm_wr_data;
+	wire [31:0] picm_rd_data;
+	wire dec_tlu_external_ldfwd_disable;
+	wire dec_tlu_bpred_disable;
+	wire dec_tlu_wb_coalescing_disable;
+	wire dec_tlu_sideeffect_posted_disable;
+	wire [2:0] dec_tlu_dma_qos_prty;
+	wire dec_tlu_misc_clk_override;
+	wire dec_tlu_ifu_clk_override;
+	wire dec_tlu_lsu_clk_override;
+	wire dec_tlu_bus_clk_override;
+	wire dec_tlu_pic_clk_override;
+	wire dec_tlu_dccm_clk_override;
+	wire dec_tlu_icm_clk_override;
+	wire dec_tlu_picio_clk_override;
+	assign dccm_clk_override = dec_tlu_dccm_clk_override;
+	assign icm_clk_override = dec_tlu_icm_clk_override;
+	wire [31:0] dbg_cmd_addr;
+	wire [31:0] dbg_cmd_wrdata;
+	wire dbg_cmd_valid;
+	wire dbg_cmd_write;
+	wire [1:0] dbg_cmd_type;
+	wire [1:0] dbg_cmd_size;
+	wire dbg_halt_req;
+	wire dbg_resume_req;
+	wire dbg_core_rst_l;
+	wire core_dbg_cmd_done;
+	wire core_dbg_cmd_fail;
+	wire [31:0] core_dbg_rddata;
+	wire dma_dbg_cmd_done;
+	wire dma_dbg_cmd_fail;
+	wire [31:0] dma_dbg_rddata;
+	wire dbg_dma_bubble;
+	wire dma_dbg_ready;
+	wire [31:0] dec_dbg_rddata;
+	wire dec_dbg_cmd_done;
+	wire dec_dbg_cmd_fail;
+	wire dec_tlu_mpc_halted_only;
+	wire dec_tlu_dbg_halted;
+	wire dec_tlu_resume_ack;
+	wire dec_tlu_debug_mode;
+	wire dec_debug_wdata_rs1_d;
+	wire dec_tlu_force_halt;
+	wire [1:0] dec_data_en;
+	wire [1:0] dec_ctl_en;
+	wire exu_pmu_i0_br_misp;
+	wire exu_pmu_i0_br_ataken;
+	wire exu_pmu_i0_pc4;
+	wire lsu_pmu_load_external_m;
+	wire lsu_pmu_store_external_m;
+	wire lsu_pmu_misaligned_m;
+	wire lsu_pmu_bus_trxn;
+	wire lsu_pmu_bus_misaligned;
+	wire lsu_pmu_bus_error;
+	wire lsu_pmu_bus_busy;
+	wire ifu_pmu_fetch_stall;
+	wire ifu_pmu_ic_miss;
+	wire ifu_pmu_ic_hit;
+	wire ifu_pmu_bus_error;
+	wire ifu_pmu_bus_busy;
+	wire ifu_pmu_bus_trxn;
+	wire active_state;
+	wire free_clk;
+	wire active_clk;
+	wire dec_pause_state_cg;
+	wire lsu_nonblock_load_data_error;
+	wire [15:0] ifu_i0_cinst;
+	wire [31:2] dec_tlu_meihap;
+	wire dec_extint_stall;
+	wire [103:0] trace_rv_trace_pkt;
+	wire lsu_fastint_stall_any;
+	wire [7:0] pic_claimid;
+	wire [3:0] pic_pl;
+	wire [3:0] dec_tlu_meicurpl;
+	wire [3:0] dec_tlu_meipt;
+	wire mexintpend;
+	wire mhwakeup;
+	wire dma_active;
+	wire pause_state;
+	wire halt_state;
+	wire dec_tlu_core_empty;
+	assign pause_state = (dec_pause_state_cg & ~(dma_active | lsu_active)) & dec_tlu_core_empty;
+	assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);
+	assign active_state = ((~(halt_state | pause_state) | dec_tlu_flush_lower_r) | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;
+	rvoclkhdr free_cg2(
+		.clk(clk),
+		.en(1'b1),
+		.l1clk(free_l2clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr active_cg2(
+		.clk(clk),
+		.en(active_state),
+		.l1clk(active_l2clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr free_cg1(
+		.clk(free_l2clk),
+		.en(1'b1),
+		.l1clk(free_clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr active_cg1(
+		.clk(active_l2clk),
+		.en(1'b1),
+		.l1clk(active_clk),
+		.scan_mode(scan_mode)
+	);
+	assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
+	assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
+	assign core_dbg_rddata[31:0] = (dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0]);
+	eb1_dbg #(.pt(pt)) dbg(
+		.rst_l(core_rst_l),
+		.clk(free_l2clk),
+		.clk_override(dec_tlu_misc_clk_override),
+		.sb_axi_awready(sb_axi_awready_int),
+		.sb_axi_wready(sb_axi_wready_int),
+		.sb_axi_bvalid(sb_axi_bvalid_int),
+		.sb_axi_bresp(sb_axi_bresp_int[1:0]),
+		.sb_axi_arready(sb_axi_arready_int),
+		.sb_axi_rvalid(sb_axi_rvalid_int),
+		.sb_axi_rdata(sb_axi_rdata_int[63:0]),
+		.sb_axi_rresp(sb_axi_rresp_int[1:0]),
+		.dbg_cmd_addr(dbg_cmd_addr),
+		.dbg_cmd_wrdata(dbg_cmd_wrdata),
+		.dbg_cmd_valid(dbg_cmd_valid),
+		.dbg_cmd_write(dbg_cmd_write),
+		.dbg_cmd_type(dbg_cmd_type),
+		.dbg_cmd_size(dbg_cmd_size),
+		.dbg_core_rst_l(dbg_core_rst_l),
+		.core_dbg_rddata(core_dbg_rddata),
+		.core_dbg_cmd_done(core_dbg_cmd_done),
+		.core_dbg_cmd_fail(core_dbg_cmd_fail),
+		.dbg_dma_bubble(dbg_dma_bubble),
+		.dma_dbg_ready(dma_dbg_ready),
+		.dbg_halt_req(dbg_halt_req),
+		.dbg_resume_req(dbg_resume_req),
+		.dec_tlu_debug_mode(dec_tlu_debug_mode),
+		.dec_tlu_dbg_halted(dec_tlu_dbg_halted),
+		.dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only),
+		.dec_tlu_resume_ack(dec_tlu_resume_ack),
+		.dmi_reg_en(dmi_reg_en),
+		.dmi_reg_addr(dmi_reg_addr),
+		.dmi_reg_wr_en(dmi_reg_wr_en),
+		.dmi_reg_wdata(dmi_reg_wdata),
+		.dmi_reg_rdata(dmi_reg_rdata),
+		.sb_axi_awvalid(sb_axi_awvalid),
+		.sb_axi_awid(sb_axi_awid),
+		.sb_axi_awaddr(sb_axi_awaddr),
+		.sb_axi_awregion(sb_axi_awregion),
+		.sb_axi_awlen(sb_axi_awlen),
+		.sb_axi_awsize(sb_axi_awsize),
+		.sb_axi_awburst(sb_axi_awburst),
+		.sb_axi_awlock(sb_axi_awlock),
+		.sb_axi_awcache(sb_axi_awcache),
+		.sb_axi_awprot(sb_axi_awprot),
+		.sb_axi_awqos(sb_axi_awqos),
+		.sb_axi_wvalid(sb_axi_wvalid),
+		.sb_axi_wdata(sb_axi_wdata),
+		.sb_axi_wstrb(sb_axi_wstrb),
+		.sb_axi_wlast(sb_axi_wlast),
+		.sb_axi_bready(sb_axi_bready),
+		.sb_axi_arvalid(sb_axi_arvalid),
+		.sb_axi_arid(sb_axi_arid),
+		.sb_axi_araddr(sb_axi_araddr),
+		.sb_axi_arregion(sb_axi_arregion),
+		.sb_axi_arlen(sb_axi_arlen),
+		.sb_axi_arsize(sb_axi_arsize),
+		.sb_axi_arburst(sb_axi_arburst),
+		.sb_axi_arlock(sb_axi_arlock),
+		.sb_axi_arcache(sb_axi_arcache),
+		.sb_axi_arprot(sb_axi_arprot),
+		.sb_axi_arqos(sb_axi_arqos),
+		.sb_axi_rready(sb_axi_rready),
+		.dbg_bus_clk_en(dbg_bus_clk_en),
+		.dbg_rst_l(dbg_rst_l),
+		.scan_mode(scan_mode)
+	);
+	assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
+	eb1_ifu #(.pt(pt)) ifu(
+		.clk(active_l2clk),
+		.rst_l(core_rst_l),
+		.dec_tlu_flush_err_wb(dec_tlu_flush_err_r),
+		.dec_tlu_flush_noredir_wb(dec_tlu_flush_noredir_r),
+		.dec_tlu_fence_i_wb(dec_tlu_fence_i_r),
+		.dec_tlu_flush_leak_one_wb(dec_tlu_flush_leak_one_r),
+		.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_r),
+		.ifu_axi_arready(ifu_axi_arready_int),
+		.ifu_axi_rvalid(ifu_axi_rvalid_int),
+		.ifu_axi_rid(ifu_axi_rid_int[pt[826-:8] - 1:0]),
+		.ifu_axi_rdata(ifu_axi_rdata_int[63:0]),
+		.ifu_axi_rresp(ifu_axi_rresp_int[1:0]),
+		.exu_flush_final(exu_flush_final),
+		.free_l2clk(free_l2clk),
+		.active_clk(active_clk),
+		.dec_i0_decode_d(dec_i0_decode_d),
+		.dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt),
+		.exu_flush_path_final(exu_flush_path_final),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.dec_tlu_bpred_disable(dec_tlu_bpred_disable),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.ifu_axi_awvalid(ifu_axi_awvalid),
+		.ifu_axi_awid(ifu_axi_awid),
+		.ifu_axi_awaddr(ifu_axi_awaddr),
+		.ifu_axi_awregion(ifu_axi_awregion),
+		.ifu_axi_awlen(ifu_axi_awlen),
+		.ifu_axi_awsize(ifu_axi_awsize),
+		.ifu_axi_awburst(ifu_axi_awburst),
+		.ifu_axi_awlock(ifu_axi_awlock),
+		.ifu_axi_awcache(ifu_axi_awcache),
+		.ifu_axi_awprot(ifu_axi_awprot),
+		.ifu_axi_awqos(ifu_axi_awqos),
+		.ifu_axi_wvalid(ifu_axi_wvalid),
+		.ifu_axi_wdata(ifu_axi_wdata),
+		.ifu_axi_wstrb(ifu_axi_wstrb),
+		.ifu_axi_wlast(ifu_axi_wlast),
+		.ifu_axi_bready(ifu_axi_bready),
+		.ifu_axi_arvalid(ifu_axi_arvalid),
+		.ifu_axi_arid(ifu_axi_arid),
+		.ifu_axi_araddr(ifu_axi_araddr),
+		.ifu_axi_arregion(ifu_axi_arregion),
+		.ifu_axi_arlen(ifu_axi_arlen),
+		.ifu_axi_arsize(ifu_axi_arsize),
+		.ifu_axi_arburst(ifu_axi_arburst),
+		.ifu_axi_arlock(ifu_axi_arlock),
+		.ifu_axi_arcache(ifu_axi_arcache),
+		.ifu_axi_arprot(ifu_axi_arprot),
+		.ifu_axi_arqos(ifu_axi_arqos),
+		.ifu_axi_rready(ifu_axi_rready),
+		.ifu_bus_clk_en(ifu_bus_clk_en),
+		.dma_iccm_req(dma_iccm_req),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_sz(dma_mem_sz),
+		.dma_mem_write(dma_mem_write),
+		.dma_mem_wdata(dma_mem_wdata),
+		.dma_mem_tag(dma_mem_tag),
+		.dma_iccm_stall_any(dma_iccm_stall_any),
+		.iccm_dma_ecc_error(iccm_dma_ecc_error),
+		.iccm_dma_rvalid(iccm_dma_rvalid),
+		.iccm_dma_rdata(iccm_dma_rdata),
+		.iccm_dma_rtag(iccm_dma_rtag),
+		.iccm_ready(iccm_ready),
+		.ifu_pmu_instr_aligned(ifu_pmu_instr_aligned),
+		.ifu_pmu_fetch_stall(ifu_pmu_fetch_stall),
+		.ifu_ic_error_start(ifu_ic_error_start),
+		.ic_rw_addr(ic_rw_addr),
+		.ic_wr_en(ic_wr_en),
+		.ic_rd_en(ic_rd_en),
+		.ic_wr_data(ic_wr_data),
+		.ic_rd_data(ic_rd_data),
+		.ic_debug_rd_data(ic_debug_rd_data),
+		.ictag_debug_rd_data(ictag_debug_rd_data),
+		.ic_debug_wr_data(ic_debug_wr_data),
+		.ifu_ic_debug_rd_data(ifu_ic_debug_rd_data),
+		.ic_eccerr(ic_eccerr),
+		.ic_parerr(ic_parerr),
+		.ic_premux_data(ic_premux_data),
+		.ic_sel_premux_data(ic_sel_premux_data),
+		.ic_debug_addr(ic_debug_addr),
+		.ic_debug_rd_en(ic_debug_rd_en),
+		.ic_debug_wr_en(ic_debug_wr_en),
+		.ic_debug_tag_array(ic_debug_tag_array),
+		.ic_debug_way(ic_debug_way),
+		.ic_tag_valid(ic_tag_valid),
+		.ic_rd_hit(ic_rd_hit),
+		.ic_tag_perr(ic_tag_perr),
+		.iccm_rw_addr(iccm_rw_addr),
+		.iccm_wren(iccm_wren),
+		.iccm_rden(iccm_rden),
+		.iccm_wr_data(iccm_wr_data),
+		.iccm_wr_size(iccm_wr_size),
+		.iccm_rd_data(iccm_rd_data),
+		.iccm_rd_data_ecc(iccm_rd_data_ecc),
+		.ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err),
+		.ifu_pmu_ic_miss(ifu_pmu_ic_miss),
+		.ifu_pmu_ic_hit(ifu_pmu_ic_hit),
+		.ifu_pmu_bus_error(ifu_pmu_bus_error),
+		.ifu_pmu_bus_busy(ifu_pmu_bus_busy),
+		.ifu_pmu_bus_trxn(ifu_pmu_bus_trxn),
+		.ifu_i0_icaf(ifu_i0_icaf),
+		.ifu_i0_icaf_type(ifu_i0_icaf_type),
+		.ifu_i0_valid(ifu_i0_valid),
+		.ifu_i0_icaf_second(ifu_i0_icaf_second),
+		.ifu_i0_dbecc(ifu_i0_dbecc),
+		.iccm_dma_sb_error(iccm_dma_sb_error),
+		.ifu_i0_instr(ifu_i0_instr),
+		.ifu_i0_pc(ifu_i0_pc),
+		.ifu_i0_pc4(ifu_i0_pc4),
+		.ifu_miss_state_idle(ifu_miss_state_idle),
+		.i0_brp(i0_brp),
+		.ifu_i0_bp_index(ifu_i0_bp_index),
+		.ifu_i0_bp_fghr(ifu_i0_bp_fghr),
+		.ifu_i0_bp_btag(ifu_i0_bp_btag),
+		.ifu_i0_fa_index(ifu_i0_fa_index),
+		.exu_mp_pkt(exu_mp_pkt),
+		.exu_mp_eghr(exu_mp_eghr),
+		.exu_mp_fghr(exu_mp_fghr),
+		.exu_mp_index(exu_mp_index),
+		.exu_mp_btag(exu_mp_btag),
+		.dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt),
+		.exu_i0_br_fghr_r(exu_i0_br_fghr_r),
+		.exu_i0_br_index_r(exu_i0_br_index_r),
+		.dec_fa_error_index(dec_fa_error_index),
+		.ifu_i0_cinst(ifu_i0_cinst),
+		.dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt),
+		.ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid),
+		.iccm_buf_correct_ecc(iccm_buf_correct_ecc),
+		.iccm_correction_state(iccm_correction_state),
+		.scan_mode(scan_mode)
+	);
+	eb1_dec #(.pt(pt)) dec(
+		.clk(active_l2clk),
+		.dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
+		.rst_l(core_rst_l),
+		.i_cpu_halt_req(i_cpu_halt_req),
+		.i_cpu_run_req(i_cpu_run_req),
+		.active_clk(active_clk),
+		.free_clk(free_clk),
+		.free_l2clk(free_l2clk),
+		.lsu_fastint_stall_any(lsu_fastint_stall_any),
+		.dec_extint_stall(dec_extint_stall),
+		.dec_i0_decode_d(dec_i0_decode_d),
+		.dec_pause_state_cg(dec_pause_state_cg),
+		.dec_tlu_core_empty(dec_tlu_core_empty),
+		.rst_vec(rst_vec),
+		.nmi_int(nmi_int),
+		.nmi_vec(nmi_vec),
+		.o_cpu_halt_status(o_cpu_halt_status),
+		.o_cpu_halt_ack(o_cpu_halt_ack),
+		.o_cpu_run_ack(o_cpu_run_ack),
+		.o_debug_mode_status(o_debug_mode_status),
+		.core_id(core_id),
+		.mpc_debug_halt_req(mpc_debug_halt_req),
+		.mpc_debug_run_req(mpc_debug_run_req),
+		.mpc_reset_run_req(mpc_reset_run_req),
+		.mpc_debug_halt_ack(mpc_debug_halt_ack),
+		.mpc_debug_run_ack(mpc_debug_run_ack),
+		.debug_brkpt_status(debug_brkpt_status),
+		.exu_pmu_i0_br_misp(exu_pmu_i0_br_misp),
+		.exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken),
+		.exu_pmu_i0_pc4(exu_pmu_i0_pc4),
+		.lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m),
+		.lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m),
+		.lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r),
+		.lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r),
+		.lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid),
+		.lsu_nonblock_load_data_error(lsu_nonblock_load_data_error),
+		.lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag),
+		.lsu_nonblock_load_data(lsu_nonblock_load_data),
+		.lsu_pmu_bus_trxn(lsu_pmu_bus_trxn),
+		.lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned),
+		.lsu_pmu_bus_error(lsu_pmu_bus_error),
+		.lsu_pmu_bus_busy(lsu_pmu_bus_busy),
+		.lsu_pmu_misaligned_m(lsu_pmu_misaligned_m),
+		.lsu_pmu_load_external_m(lsu_pmu_load_external_m),
+		.lsu_pmu_store_external_m(lsu_pmu_store_external_m),
+		.dma_pmu_dccm_read(dma_pmu_dccm_read),
+		.dma_pmu_dccm_write(dma_pmu_dccm_write),
+		.dma_pmu_any_read(dma_pmu_any_read),
+		.dma_pmu_any_write(dma_pmu_any_write),
+		.lsu_fir_addr(lsu_fir_addr),
+		.lsu_fir_error(lsu_fir_error),
+		.ifu_pmu_instr_aligned(ifu_pmu_instr_aligned),
+		.ifu_pmu_fetch_stall(ifu_pmu_fetch_stall),
+		.ifu_pmu_ic_miss(ifu_pmu_ic_miss),
+		.ifu_pmu_ic_hit(ifu_pmu_ic_hit),
+		.ifu_pmu_bus_error(ifu_pmu_bus_error),
+		.ifu_pmu_bus_busy(ifu_pmu_bus_busy),
+		.ifu_pmu_bus_trxn(ifu_pmu_bus_trxn),
+		.ifu_ic_error_start(ifu_ic_error_start),
+		.ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err),
+		.lsu_trigger_match_m(lsu_trigger_match_m),
+		.dbg_cmd_valid(dbg_cmd_valid),
+		.dbg_cmd_write(dbg_cmd_write),
+		.dbg_cmd_type(dbg_cmd_type),
+		.dbg_cmd_addr(dbg_cmd_addr),
+		.ifu_i0_icaf(ifu_i0_icaf),
+		.ifu_i0_icaf_type(ifu_i0_icaf_type),
+		.ifu_i0_icaf_second(ifu_i0_icaf_second),
+		.ifu_i0_dbecc(ifu_i0_dbecc),
+		.lsu_idle_any(lsu_idle_any),
+		.i0_brp(i0_brp),
+		.ifu_i0_bp_index(ifu_i0_bp_index),
+		.ifu_i0_bp_fghr(ifu_i0_bp_fghr),
+		.ifu_i0_bp_btag(ifu_i0_bp_btag),
+		.ifu_i0_fa_index(ifu_i0_fa_index),
+		.lsu_error_pkt_r(lsu_error_pkt_r),
+		.lsu_single_ecc_error_incr(lsu_single_ecc_error_incr),
+		.lsu_imprecise_error_load_any(lsu_imprecise_error_load_any),
+		.lsu_imprecise_error_store_any(lsu_imprecise_error_store_any),
+		.lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any),
+		.exu_div_result(exu_div_result),
+		.exu_div_wren(exu_div_wren),
+		.exu_csr_rs1_x(exu_csr_rs1_x),
+		.lsu_result_m(lsu_result_m),
+		.lsu_result_corr_r(lsu_result_corr_r),
+		.lsu_load_stall_any(lsu_load_stall_any),
+		.lsu_store_stall_any(lsu_store_stall_any),
+		.dma_dccm_stall_any(dma_dccm_stall_any),
+		.dma_iccm_stall_any(dma_iccm_stall_any),
+		.iccm_dma_sb_error(iccm_dma_sb_error),
+		.exu_flush_final(exu_flush_final),
+		.exu_npc_r(exu_npc_r),
+		.exu_i0_result_x(exu_i0_result_x),
+		.ifu_i0_valid(ifu_i0_valid),
+		.ifu_i0_instr(ifu_i0_instr),
+		.ifu_i0_pc(ifu_i0_pc),
+		.ifu_i0_pc4(ifu_i0_pc4),
+		.exu_i0_pc_x(exu_i0_pc_x),
+		.mexintpend(mexintpend),
+		.timer_int(timer_int),
+		.soft_int(soft_int),
+		.pic_claimid(pic_claimid),
+		.pic_pl(pic_pl),
+		.mhwakeup(mhwakeup),
+		.dec_tlu_meicurpl(dec_tlu_meicurpl),
+		.dec_tlu_meipt(dec_tlu_meipt),
+		.ifu_ic_debug_rd_data(ifu_ic_debug_rd_data),
+		.ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid),
+		.dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt),
+		.dbg_halt_req(dbg_halt_req),
+		.dbg_resume_req(dbg_resume_req),
+		.ifu_miss_state_idle(ifu_miss_state_idle),
+		.dec_tlu_dbg_halted(dec_tlu_dbg_halted),
+		.dec_tlu_debug_mode(dec_tlu_debug_mode),
+		.dec_tlu_resume_ack(dec_tlu_resume_ack),
+		.dec_tlu_flush_noredir_r(dec_tlu_flush_noredir_r),
+		.dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only),
+		.dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r),
+		.dec_tlu_flush_err_r(dec_tlu_flush_err_r),
+		.dec_tlu_meihap(dec_tlu_meihap),
+		.dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d),
+		.dec_dbg_rddata(dec_dbg_rddata),
+		.dec_dbg_cmd_done(dec_dbg_cmd_done),
+		.dec_dbg_cmd_fail(dec_dbg_cmd_fail),
+		.trigger_pkt_any(trigger_pkt_any),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.exu_i0_br_hist_r(exu_i0_br_hist_r),
+		.exu_i0_br_error_r(exu_i0_br_error_r),
+		.exu_i0_br_start_error_r(exu_i0_br_start_error_r),
+		.exu_i0_br_valid_r(exu_i0_br_valid_r),
+		.exu_i0_br_mp_r(exu_i0_br_mp_r),
+		.exu_i0_br_middle_r(exu_i0_br_middle_r),
+		.exu_i0_br_way_r(exu_i0_br_way_r),
+		.dec_i0_rs1_en_d(dec_i0_rs1_en_d),
+		.dec_i0_rs2_en_d(dec_i0_rs2_en_d),
+		.gpr_i0_rs1_d(gpr_i0_rs1_d),
+		.gpr_i0_rs2_d(gpr_i0_rs2_d),
+		.dec_i0_immed_d(dec_i0_immed_d),
+		.dec_i0_br_immed_d(dec_i0_br_immed_d),
+		.i0_ap(i0_ap),
+		.dec_i0_alu_decode_d(dec_i0_alu_decode_d),
+		.dec_i0_branch_d(dec_i0_branch_d),
+		.dec_i0_select_pc_d(dec_i0_select_pc_d),
+		.dec_i0_pc_d(dec_i0_pc_d),
+		.dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d),
+		.dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d),
+		.dec_i0_result_r(dec_i0_result_r),
+		.lsu_p(lsu_p),
+		.dec_qual_lsu_d(dec_qual_lsu_d),
+		.mul_p(mul_p),
+		.div_p(div_p),
+		.dec_div_cancel(dec_div_cancel),
+		.dec_lsu_offset_d(dec_lsu_offset_d),
+		.dec_csr_ren_d(dec_csr_ren_d),
+		.dec_csr_rddata_d(dec_csr_rddata_d),
+		.dec_tlu_flush_lower_r(dec_tlu_flush_lower_r),
+		.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb),
+		.dec_tlu_flush_path_r(dec_tlu_flush_path_r),
+		.dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
+		.dec_tlu_fence_i_r(dec_tlu_fence_i_r),
+		.pred_correct_npc_x(pred_correct_npc_x),
+		.dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt),
+		.dec_tlu_perfcnt0(dec_tlu_perfcnt0),
+		.dec_tlu_perfcnt1(dec_tlu_perfcnt1),
+		.dec_tlu_perfcnt2(dec_tlu_perfcnt2),
+		.dec_tlu_perfcnt3(dec_tlu_perfcnt3),
+		.dec_i0_predict_p_d(dec_i0_predict_p_d),
+		.i0_predict_fghr_d(i0_predict_fghr_d),
+		.i0_predict_index_d(i0_predict_index_d),
+		.i0_predict_btag_d(i0_predict_btag_d),
+		.dec_fa_error_index(dec_fa_error_index),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.dec_data_en(dec_data_en),
+		.dec_ctl_en(dec_ctl_en),
+		.ifu_i0_cinst(ifu_i0_cinst),
+		.trace_rv_trace_pkt(trace_rv_trace_pkt),
+		.dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable),
+		.dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.dec_tlu_bpred_disable(dec_tlu_bpred_disable),
+		.dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable),
+		.dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty),
+		.dec_tlu_misc_clk_override(dec_tlu_misc_clk_override),
+		.dec_tlu_ifu_clk_override(dec_tlu_ifu_clk_override),
+		.dec_tlu_lsu_clk_override(dec_tlu_lsu_clk_override),
+		.dec_tlu_bus_clk_override(dec_tlu_bus_clk_override),
+		.dec_tlu_pic_clk_override(dec_tlu_pic_clk_override),
+		.dec_tlu_picio_clk_override(dec_tlu_picio_clk_override),
+		.dec_tlu_dccm_clk_override(dec_tlu_dccm_clk_override),
+		.dec_tlu_icm_clk_override(dec_tlu_icm_clk_override),
+		.dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt),
+		.scan_mode(scan_mode)
+	);
+	eb1_exu #(.pt(pt)) exu(
+		.clk(active_l2clk),
+		.rst_l(core_rst_l),
+		.scan_mode(scan_mode),
+		.dec_data_en(dec_data_en),
+		.dec_ctl_en(dec_ctl_en),
+		.dbg_cmd_wrdata(dbg_cmd_wrdata),
+		.i0_ap(i0_ap),
+		.dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d),
+		.dec_i0_predict_p_d(dec_i0_predict_p_d),
+		.i0_predict_fghr_d(i0_predict_fghr_d),
+		.i0_predict_index_d(i0_predict_index_d),
+		.i0_predict_btag_d(i0_predict_btag_d),
+		.lsu_result_m(lsu_result_m),
+		.lsu_nonblock_load_data(lsu_nonblock_load_data),
+		.dec_i0_rs1_en_d(dec_i0_rs1_en_d),
+		.dec_i0_rs2_en_d(dec_i0_rs2_en_d),
+		.gpr_i0_rs1_d(gpr_i0_rs1_d),
+		.gpr_i0_rs2_d(gpr_i0_rs2_d),
+		.dec_i0_immed_d(dec_i0_immed_d),
+		.dec_i0_result_r(dec_i0_result_r),
+		.dec_i0_br_immed_d(dec_i0_br_immed_d),
+		.dec_i0_alu_decode_d(dec_i0_alu_decode_d),
+		.dec_i0_branch_d(dec_i0_branch_d),
+		.dec_i0_select_pc_d(dec_i0_select_pc_d),
+		.dec_i0_pc_d(dec_i0_pc_d),
+		.dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d),
+		.dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d),
+		.dec_csr_ren_d(dec_csr_ren_d),
+		.dec_csr_rddata_d(dec_csr_rddata_d),
+		.dec_qual_lsu_d(dec_qual_lsu_d),
+		.mul_p(mul_p),
+		.div_p(div_p),
+		.dec_div_cancel(dec_div_cancel),
+		.pred_correct_npc_x(pred_correct_npc_x),
+		.dec_tlu_flush_lower_r(dec_tlu_flush_lower_r),
+		.dec_tlu_flush_path_r(dec_tlu_flush_path_r),
+		.dec_extint_stall(dec_extint_stall),
+		.dec_tlu_meihap(dec_tlu_meihap),
+		.exu_lsu_rs1_d(exu_lsu_rs1_d),
+		.exu_lsu_rs2_d(exu_lsu_rs2_d),
+		.exu_flush_final(exu_flush_final),
+		.exu_flush_path_final(exu_flush_path_final),
+		.exu_i0_result_x(exu_i0_result_x),
+		.exu_i0_pc_x(exu_i0_pc_x),
+		.exu_csr_rs1_x(exu_csr_rs1_x),
+		.exu_npc_r(exu_npc_r),
+		.exu_i0_br_hist_r(exu_i0_br_hist_r),
+		.exu_i0_br_error_r(exu_i0_br_error_r),
+		.exu_i0_br_start_error_r(exu_i0_br_start_error_r),
+		.exu_i0_br_index_r(exu_i0_br_index_r),
+		.exu_i0_br_valid_r(exu_i0_br_valid_r),
+		.exu_i0_br_mp_r(exu_i0_br_mp_r),
+		.exu_i0_br_middle_r(exu_i0_br_middle_r),
+		.exu_i0_br_fghr_r(exu_i0_br_fghr_r),
+		.exu_i0_br_way_r(exu_i0_br_way_r),
+		.exu_mp_pkt(exu_mp_pkt),
+		.exu_mp_eghr(exu_mp_eghr),
+		.exu_mp_fghr(exu_mp_fghr),
+		.exu_mp_index(exu_mp_index),
+		.exu_mp_btag(exu_mp_btag),
+		.exu_pmu_i0_br_misp(exu_pmu_i0_br_misp),
+		.exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken),
+		.exu_pmu_i0_pc4(exu_pmu_i0_pc4),
+		.exu_div_result(exu_div_result),
+		.exu_div_wren(exu_div_wren)
+	);
+	eb1_lsu #(.pt(pt)) lsu(
+		.clk(active_l2clk),
+		.rst_l(core_rst_l),
+		.clk_override(dec_tlu_lsu_clk_override),
+		.dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
+		.lsu_axi_awready(lsu_axi_awready_int),
+		.lsu_axi_wready(lsu_axi_wready_int),
+		.lsu_axi_bvalid(lsu_axi_bvalid_int),
+		.lsu_axi_bid(lsu_axi_bid_int[pt[181-:8] - 1:0]),
+		.lsu_axi_bresp(lsu_axi_bresp_int[1:0]),
+		.lsu_axi_arready(lsu_axi_arready_int),
+		.lsu_axi_rvalid(lsu_axi_rvalid_int),
+		.lsu_axi_rid(lsu_axi_rid_int[pt[181-:8] - 1:0]),
+		.lsu_axi_rdata(lsu_axi_rdata_int[63:0]),
+		.lsu_axi_rresp(lsu_axi_rresp_int[1:0]),
+		.lsu_axi_rlast(lsu_axi_rlast_int),
+		.dec_tlu_flush_lower_r(dec_tlu_flush_lower_r),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable),
+		.dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable),
+		.dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.exu_lsu_rs1_d(exu_lsu_rs1_d),
+		.exu_lsu_rs2_d(exu_lsu_rs2_d),
+		.dec_lsu_offset_d(dec_lsu_offset_d),
+		.lsu_p(lsu_p),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.lsu_result_m(lsu_result_m),
+		.lsu_result_corr_r(lsu_result_corr_r),
+		.lsu_load_stall_any(lsu_load_stall_any),
+		.lsu_store_stall_any(lsu_store_stall_any),
+		.lsu_fastint_stall_any(lsu_fastint_stall_any),
+		.lsu_idle_any(lsu_idle_any),
+		.lsu_active(lsu_active),
+		.lsu_fir_addr(lsu_fir_addr),
+		.lsu_fir_error(lsu_fir_error),
+		.lsu_single_ecc_error_incr(lsu_single_ecc_error_incr),
+		.lsu_error_pkt_r(lsu_error_pkt_r),
+		.lsu_imprecise_error_load_any(lsu_imprecise_error_load_any),
+		.lsu_imprecise_error_store_any(lsu_imprecise_error_store_any),
+		.lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any),
+		.lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m),
+		.lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m),
+		.lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r),
+		.lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r),
+		.lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid),
+		.lsu_nonblock_load_data_error(lsu_nonblock_load_data_error),
+		.lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag),
+		.lsu_nonblock_load_data(lsu_nonblock_load_data),
+		.lsu_pmu_load_external_m(lsu_pmu_load_external_m),
+		.lsu_pmu_store_external_m(lsu_pmu_store_external_m),
+		.lsu_pmu_misaligned_m(lsu_pmu_misaligned_m),
+		.lsu_pmu_bus_trxn(lsu_pmu_bus_trxn),
+		.lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned),
+		.lsu_pmu_bus_error(lsu_pmu_bus_error),
+		.lsu_pmu_bus_busy(lsu_pmu_bus_busy),
+		.trigger_pkt_any(trigger_pkt_any),
+		.lsu_trigger_match_m(lsu_trigger_match_m),
+		.dccm_wren(dccm_wren),
+		.dccm_rden(dccm_rden),
+		.dccm_wr_addr_lo(dccm_wr_addr_lo),
+		.dccm_wr_addr_hi(dccm_wr_addr_hi),
+		.dccm_rd_addr_lo(dccm_rd_addr_lo),
+		.dccm_rd_addr_hi(dccm_rd_addr_hi),
+		.dccm_wr_data_lo(dccm_wr_data_lo),
+		.dccm_wr_data_hi(dccm_wr_data_hi),
+		.dccm_rd_data_lo(dccm_rd_data_lo),
+		.dccm_rd_data_hi(dccm_rd_data_hi),
+		.picm_wren(picm_wren),
+		.picm_rden(picm_rden),
+		.picm_mken(picm_mken),
+		.picm_rdaddr(picm_rdaddr),
+		.picm_wraddr(picm_wraddr),
+		.picm_wr_data(picm_wr_data),
+		.picm_rd_data(picm_rd_data),
+		.lsu_axi_awvalid(lsu_axi_awvalid),
+		.lsu_axi_awid(lsu_axi_awid),
+		.lsu_axi_awaddr(lsu_axi_awaddr),
+		.lsu_axi_awregion(lsu_axi_awregion),
+		.lsu_axi_awlen(lsu_axi_awlen),
+		.lsu_axi_awsize(lsu_axi_awsize),
+		.lsu_axi_awburst(lsu_axi_awburst),
+		.lsu_axi_awlock(lsu_axi_awlock),
+		.lsu_axi_awcache(lsu_axi_awcache),
+		.lsu_axi_awprot(lsu_axi_awprot),
+		.lsu_axi_awqos(lsu_axi_awqos),
+		.lsu_axi_wvalid(lsu_axi_wvalid),
+		.lsu_axi_wdata(lsu_axi_wdata),
+		.lsu_axi_wstrb(lsu_axi_wstrb),
+		.lsu_axi_wlast(lsu_axi_wlast),
+		.lsu_axi_bready(lsu_axi_bready),
+		.lsu_axi_arvalid(lsu_axi_arvalid),
+		.lsu_axi_arid(lsu_axi_arid),
+		.lsu_axi_araddr(lsu_axi_araddr),
+		.lsu_axi_arregion(lsu_axi_arregion),
+		.lsu_axi_arlen(lsu_axi_arlen),
+		.lsu_axi_arsize(lsu_axi_arsize),
+		.lsu_axi_arburst(lsu_axi_arburst),
+		.lsu_axi_arlock(lsu_axi_arlock),
+		.lsu_axi_arcache(lsu_axi_arcache),
+		.lsu_axi_arprot(lsu_axi_arprot),
+		.lsu_axi_arqos(lsu_axi_arqos),
+		.lsu_axi_rready(lsu_axi_rready),
+		.lsu_bus_clk_en(lsu_bus_clk_en),
+		.dma_dccm_req(dma_dccm_req),
+		.dma_mem_tag(dma_mem_tag),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_sz(dma_mem_sz),
+		.dma_mem_write(dma_mem_write),
+		.dma_mem_wdata(dma_mem_wdata),
+		.dccm_dma_rvalid(dccm_dma_rvalid),
+		.dccm_dma_ecc_error(dccm_dma_ecc_error),
+		.dccm_dma_rtag(dccm_dma_rtag),
+		.dccm_dma_rdata(dccm_dma_rdata),
+		.dccm_ready(dccm_ready),
+		.scan_mode(scan_mode),
+		.active_clk(active_clk)
+	);
+	eb1_pic_ctrl #(.pt(pt)) pic_ctrl_inst(
+		.clk(free_l2clk),
+		.clk_override(dec_tlu_pic_clk_override),
+		.io_clk_override(dec_tlu_picio_clk_override),
+		.picm_mken(picm_mken),
+		.extintsrc_req({extintsrc_req[pt[56-:12]:1], 1'b0}),
+		.pl(pic_pl[3:0]),
+		.claimid(pic_claimid[7:0]),
+		.meicurpl(dec_tlu_meicurpl[3:0]),
+		.meipt(dec_tlu_meipt[3:0]),
+		.rst_l(core_rst_l),
+		.free_clk(free_clk),
+		.picm_rdaddr(picm_rdaddr),
+		.picm_wraddr(picm_wraddr),
+		.picm_wr_data(picm_wr_data),
+		.picm_wren(picm_wren),
+		.picm_rden(picm_rden),
+		.mexintpend(mexintpend),
+		.picm_rd_data(picm_rd_data),
+		.mhwakeup(mhwakeup),
+		.scan_mode(scan_mode)
+	);
+	eb1_dma_ctrl #(.pt(pt)) dma_ctrl(
+		.clk(free_l2clk),
+		.rst_l(core_rst_l),
+		.clk_override(dec_tlu_misc_clk_override),
+		.dma_axi_awvalid(dma_axi_awvalid_int),
+		.dma_axi_awid(dma_axi_awid_int[pt[1235-:8] - 1:0]),
+		.dma_axi_awaddr(dma_axi_awaddr_int[31:0]),
+		.dma_axi_awsize(dma_axi_awsize_int[2:0]),
+		.dma_axi_wvalid(dma_axi_wvalid_int),
+		.dma_axi_wdata(dma_axi_wdata_int[63:0]),
+		.dma_axi_wstrb(dma_axi_wstrb_int[7:0]),
+		.dma_axi_bready(dma_axi_bready_int),
+		.dma_axi_arvalid(dma_axi_arvalid_int),
+		.dma_axi_arid(dma_axi_arid_int[pt[1235-:8] - 1:0]),
+		.dma_axi_araddr(dma_axi_araddr_int[31:0]),
+		.dma_axi_arsize(dma_axi_arsize_int[2:0]),
+		.dma_axi_rready(dma_axi_rready_int),
+		.free_clk(free_clk),
+		.dma_bus_clk_en(dma_bus_clk_en),
+		.scan_mode(scan_mode),
+		.dbg_cmd_addr(dbg_cmd_addr),
+		.dbg_cmd_wrdata(dbg_cmd_wrdata),
+		.dbg_cmd_valid(dbg_cmd_valid),
+		.dbg_cmd_write(dbg_cmd_write),
+		.dbg_cmd_type(dbg_cmd_type),
+		.dbg_cmd_size(dbg_cmd_size),
+		.dbg_dma_bubble(dbg_dma_bubble),
+		.dma_dbg_ready(dma_dbg_ready),
+		.dma_dbg_cmd_done(dma_dbg_cmd_done),
+		.dma_dbg_cmd_fail(dma_dbg_cmd_fail),
+		.dma_dbg_rddata(dma_dbg_rddata),
+		.dma_dccm_req(dma_dccm_req),
+		.dma_iccm_req(dma_iccm_req),
+		.dma_mem_tag(dma_mem_tag),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_sz(dma_mem_sz),
+		.dma_mem_write(dma_mem_write),
+		.dma_mem_wdata(dma_mem_wdata),
+		.dccm_dma_rvalid(dccm_dma_rvalid),
+		.dccm_dma_ecc_error(dccm_dma_ecc_error),
+		.dccm_dma_rtag(dccm_dma_rtag),
+		.dccm_dma_rdata(dccm_dma_rdata),
+		.iccm_dma_rvalid(iccm_dma_rvalid),
+		.iccm_dma_ecc_error(iccm_dma_ecc_error),
+		.iccm_dma_rtag(iccm_dma_rtag),
+		.iccm_dma_rdata(iccm_dma_rdata),
+		.dma_active(dma_active),
+		.dma_dccm_stall_any(dma_dccm_stall_any),
+		.dma_iccm_stall_any(dma_iccm_stall_any),
+		.dccm_ready(dccm_ready),
+		.iccm_ready(iccm_ready),
+		.dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty),
+		.dma_pmu_dccm_read(dma_pmu_dccm_read),
+		.dma_pmu_dccm_write(dma_pmu_dccm_write),
+		.dma_pmu_any_read(dma_pmu_any_read),
+		.dma_pmu_any_write(dma_pmu_any_write),
+		.dma_axi_awready(dma_axi_awready),
+		.dma_axi_wready(dma_axi_wready),
+		.dma_axi_bvalid(dma_axi_bvalid),
+		.dma_axi_bresp(dma_axi_bresp),
+		.dma_axi_bid(dma_axi_bid),
+		.dma_axi_arready(dma_axi_arready),
+		.dma_axi_rvalid(dma_axi_rvalid),
+		.dma_axi_rid(dma_axi_rid),
+		.dma_axi_rdata(dma_axi_rdata),
+		.dma_axi_rresp(dma_axi_rresp),
+		.dma_axi_rlast(dma_axi_rlast)
+	);
+	generate
+		if (pt[2038] == 1) begin : Gen_AXI_To_AHB
+			axi4_to_ahb #(
+				.pt(pt),
+				.TAG(pt[181-:8])
+			) lsu_axi4_to_ahb(
+				.clk(free_l2clk),
+				.free_clk(free_clk),
+				.rst_l(core_rst_l),
+				.clk_override(dec_tlu_bus_clk_override),
+				.bus_clk_en(lsu_bus_clk_en),
+				.dec_tlu_force_halt(dec_tlu_force_halt),
+				.axi_awvalid(lsu_axi_awvalid),
+				.axi_awready(lsu_axi_awready_ahb),
+				.axi_awid(lsu_axi_awid[pt[181-:8] - 1:0]),
+				.axi_awaddr(lsu_axi_awaddr[31:0]),
+				.axi_awsize(lsu_axi_awsize[2:0]),
+				.axi_awprot(lsu_axi_awprot[2:0]),
+				.axi_wvalid(lsu_axi_wvalid),
+				.axi_wready(lsu_axi_wready_ahb),
+				.axi_wdata(lsu_axi_wdata[63:0]),
+				.axi_wstrb(lsu_axi_wstrb[7:0]),
+				.axi_wlast(lsu_axi_wlast),
+				.axi_bvalid(lsu_axi_bvalid_ahb),
+				.axi_bready(lsu_axi_bready),
+				.axi_bresp(lsu_axi_bresp_ahb[1:0]),
+				.axi_bid(lsu_axi_bid_ahb[pt[181-:8] - 1:0]),
+				.axi_arvalid(lsu_axi_arvalid),
+				.axi_arready(lsu_axi_arready_ahb),
+				.axi_arid(lsu_axi_arid[pt[181-:8] - 1:0]),
+				.axi_araddr(lsu_axi_araddr[31:0]),
+				.axi_arsize(lsu_axi_arsize[2:0]),
+				.axi_arprot(lsu_axi_arprot[2:0]),
+				.axi_rvalid(lsu_axi_rvalid_ahb),
+				.axi_rready(lsu_axi_rready),
+				.axi_rid(lsu_axi_rid_ahb[pt[181-:8] - 1:0]),
+				.axi_rdata(lsu_axi_rdata_ahb[63:0]),
+				.axi_rresp(lsu_axi_rresp_ahb[1:0]),
+				.axi_rlast(lsu_axi_rlast_ahb),
+				.ahb_haddr(lsu_haddr[31:0]),
+				.ahb_hburst(lsu_hburst),
+				.ahb_hmastlock(lsu_hmastlock),
+				.ahb_hprot(lsu_hprot[3:0]),
+				.ahb_hsize(lsu_hsize[2:0]),
+				.ahb_htrans(lsu_htrans[1:0]),
+				.ahb_hwrite(lsu_hwrite),
+				.ahb_hwdata(lsu_hwdata[63:0]),
+				.ahb_hrdata(lsu_hrdata[63:0]),
+				.ahb_hready(lsu_hready),
+				.ahb_hresp(lsu_hresp),
+				.scan_mode(scan_mode)
+			);
+			axi4_to_ahb #(
+				.pt(pt),
+				.TAG(pt[826-:8])
+			) ifu_axi4_to_ahb(
+				.clk(free_l2clk),
+				.free_clk(free_clk),
+				.rst_l(core_rst_l),
+				.clk_override(dec_tlu_bus_clk_override),
+				.bus_clk_en(ifu_bus_clk_en),
+				.dec_tlu_force_halt(dec_tlu_force_halt),
+				.ahb_haddr(haddr[31:0]),
+				.ahb_hburst(hburst),
+				.ahb_hmastlock(hmastlock),
+				.ahb_hprot(hprot[3:0]),
+				.ahb_hsize(hsize[2:0]),
+				.ahb_htrans(htrans[1:0]),
+				.ahb_hwrite(hwrite),
+				.ahb_hwdata(hwdata_nc[63:0]),
+				.ahb_hrdata(hrdata[63:0]),
+				.ahb_hready(hready),
+				.ahb_hresp(hresp),
+				.axi_awvalid(ifu_axi_awvalid),
+				.axi_awready(ifu_axi_awready_ahb),
+				.axi_awid(ifu_axi_awid[pt[826-:8] - 1:0]),
+				.axi_awaddr(ifu_axi_awaddr[31:0]),
+				.axi_awsize(ifu_axi_awsize[2:0]),
+				.axi_awprot(ifu_axi_awprot[2:0]),
+				.axi_wvalid(ifu_axi_wvalid),
+				.axi_wready(ifu_axi_wready_ahb),
+				.axi_wdata(ifu_axi_wdata[63:0]),
+				.axi_wstrb(ifu_axi_wstrb[7:0]),
+				.axi_wlast(ifu_axi_wlast),
+				.axi_bvalid(ifu_axi_bvalid_ahb),
+				.axi_bready(1'b1),
+				.axi_bresp(ifu_axi_bresp_ahb[1:0]),
+				.axi_bid(ifu_axi_bid_ahb[pt[826-:8] - 1:0]),
+				.axi_arvalid(ifu_axi_arvalid),
+				.axi_arready(ifu_axi_arready_ahb),
+				.axi_arid(ifu_axi_arid[pt[826-:8] - 1:0]),
+				.axi_araddr(ifu_axi_araddr[31:0]),
+				.axi_arsize(ifu_axi_arsize[2:0]),
+				.axi_arprot(ifu_axi_arprot[2:0]),
+				.axi_rvalid(ifu_axi_rvalid_ahb),
+				.axi_rready(ifu_axi_rready),
+				.axi_rid(ifu_axi_rid_ahb[pt[826-:8] - 1:0]),
+				.axi_rdata(ifu_axi_rdata_ahb[63:0]),
+				.axi_rresp(ifu_axi_rresp_ahb[1:0]),
+				.axi_rlast(ifu_axi_rlast_ahb),
+				.scan_mode(scan_mode)
+			);
+			axi4_to_ahb #(
+				.pt(pt),
+				.TAG(pt[12-:8])
+			) sb_axi4_to_ahb(
+				.clk(free_l2clk),
+				.free_clk(free_clk),
+				.rst_l(dbg_rst_l),
+				.clk_override(dec_tlu_bus_clk_override),
+				.bus_clk_en(dbg_bus_clk_en),
+				.dec_tlu_force_halt(1'b0),
+				.axi_awvalid(sb_axi_awvalid),
+				.axi_awready(sb_axi_awready_ahb),
+				.axi_awid(sb_axi_awid[pt[12-:8] - 1:0]),
+				.axi_awaddr(sb_axi_awaddr[31:0]),
+				.axi_awsize(sb_axi_awsize[2:0]),
+				.axi_awprot(sb_axi_awprot[2:0]),
+				.axi_wvalid(sb_axi_wvalid),
+				.axi_wready(sb_axi_wready_ahb),
+				.axi_wdata(sb_axi_wdata[63:0]),
+				.axi_wstrb(sb_axi_wstrb[7:0]),
+				.axi_wlast(sb_axi_wlast),
+				.axi_bvalid(sb_axi_bvalid_ahb),
+				.axi_bready(sb_axi_bready),
+				.axi_bresp(sb_axi_bresp_ahb[1:0]),
+				.axi_bid(sb_axi_bid_ahb[pt[12-:8] - 1:0]),
+				.axi_arvalid(sb_axi_arvalid),
+				.axi_arready(sb_axi_arready_ahb),
+				.axi_arid(sb_axi_arid[pt[12-:8] - 1:0]),
+				.axi_araddr(sb_axi_araddr[31:0]),
+				.axi_arsize(sb_axi_arsize[2:0]),
+				.axi_arprot(sb_axi_arprot[2:0]),
+				.axi_rvalid(sb_axi_rvalid_ahb),
+				.axi_rready(sb_axi_rready),
+				.axi_rid(sb_axi_rid_ahb[pt[12-:8] - 1:0]),
+				.axi_rdata(sb_axi_rdata_ahb[63:0]),
+				.axi_rresp(sb_axi_rresp_ahb[1:0]),
+				.axi_rlast(sb_axi_rlast_ahb),
+				.ahb_haddr(sb_haddr[31:0]),
+				.ahb_hburst(sb_hburst),
+				.ahb_hmastlock(sb_hmastlock),
+				.ahb_hprot(sb_hprot[3:0]),
+				.ahb_hsize(sb_hsize[2:0]),
+				.ahb_htrans(sb_htrans[1:0]),
+				.ahb_hwrite(sb_hwrite),
+				.ahb_hwdata(sb_hwdata[63:0]),
+				.ahb_hrdata(sb_hrdata[63:0]),
+				.ahb_hready(sb_hready),
+				.ahb_hresp(sb_hresp),
+				.scan_mode(scan_mode)
+			);
+			ahb_to_axi4 #(
+				.pt(pt),
+				.TAG(pt[1235-:8])
+			) dma_ahb_to_axi4(
+				.clk(free_l2clk),
+				.rst_l(core_rst_l),
+				.clk_override(dec_tlu_bus_clk_override),
+				.bus_clk_en(dma_bus_clk_en),
+				.axi_awvalid(dma_axi_awvalid_ahb),
+				.axi_awready(dma_axi_awready),
+				.axi_awid(dma_axi_awid_ahb[pt[1235-:8] - 1:0]),
+				.axi_awaddr(dma_axi_awaddr_ahb[31:0]),
+				.axi_awsize(dma_axi_awsize_ahb[2:0]),
+				.axi_awprot(dma_axi_awprot_ahb[2:0]),
+				.axi_awlen(dma_axi_awlen_ahb[7:0]),
+				.axi_awburst(dma_axi_awburst_ahb[1:0]),
+				.axi_wvalid(dma_axi_wvalid_ahb),
+				.axi_wready(dma_axi_wready),
+				.axi_wdata(dma_axi_wdata_ahb[63:0]),
+				.axi_wstrb(dma_axi_wstrb_ahb[7:0]),
+				.axi_wlast(dma_axi_wlast_ahb),
+				.axi_bvalid(dma_axi_bvalid),
+				.axi_bready(dma_axi_bready_ahb),
+				.axi_bresp(dma_axi_bresp[1:0]),
+				.axi_bid(dma_axi_bid[pt[1235-:8] - 1:0]),
+				.axi_arvalid(dma_axi_arvalid_ahb),
+				.axi_arready(dma_axi_arready),
+				.axi_arid(dma_axi_arid_ahb[pt[1235-:8] - 1:0]),
+				.axi_araddr(dma_axi_araddr_ahb[31:0]),
+				.axi_arsize(dma_axi_arsize_ahb[2:0]),
+				.axi_arprot(dma_axi_arprot_ahb[2:0]),
+				.axi_arlen(dma_axi_arlen_ahb[7:0]),
+				.axi_arburst(dma_axi_arburst_ahb[1:0]),
+				.axi_rvalid(dma_axi_rvalid),
+				.axi_rready(dma_axi_rready_ahb),
+				.axi_rid(dma_axi_rid[pt[1235-:8] - 1:0]),
+				.axi_rdata(dma_axi_rdata[63:0]),
+				.axi_rresp(dma_axi_rresp[1:0]),
+				.ahb_haddr(dma_haddr[31:0]),
+				.ahb_hburst(dma_hburst),
+				.ahb_hmastlock(dma_hmastlock),
+				.ahb_hprot(dma_hprot[3:0]),
+				.ahb_hsize(dma_hsize[2:0]),
+				.ahb_htrans(dma_htrans[1:0]),
+				.ahb_hwrite(dma_hwrite),
+				.ahb_hwdata(dma_hwdata[63:0]),
+				.ahb_hrdata(dma_hrdata[63:0]),
+				.ahb_hreadyout(dma_hreadyout),
+				.ahb_hresp(dma_hresp),
+				.ahb_hreadyin(dma_hreadyin),
+				.ahb_hsel(dma_hsel),
+				.scan_mode(scan_mode)
+			);
+		end
+	endgenerate
+	assign lsu_axi_awready_int = (pt[2038] ? lsu_axi_awready_ahb : lsu_axi_awready);
+	assign lsu_axi_wready_int = (pt[2038] ? lsu_axi_wready_ahb : lsu_axi_wready);
+	assign lsu_axi_bvalid_int = (pt[2038] ? lsu_axi_bvalid_ahb : lsu_axi_bvalid);
+	assign lsu_axi_bready_int = (pt[2038] ? lsu_axi_bready_ahb : lsu_axi_bready);
+	assign lsu_axi_bresp_int[1:0] = (pt[2038] ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0]);
+	assign lsu_axi_bid_int[pt[181-:8] - 1:0] = (pt[2038] ? lsu_axi_bid_ahb[pt[181-:8] - 1:0] : lsu_axi_bid[pt[181-:8] - 1:0]);
+	assign lsu_axi_arready_int = (pt[2038] ? lsu_axi_arready_ahb : lsu_axi_arready);
+	assign lsu_axi_rvalid_int = (pt[2038] ? lsu_axi_rvalid_ahb : lsu_axi_rvalid);
+	assign lsu_axi_rid_int[pt[181-:8] - 1:0] = (pt[2038] ? lsu_axi_rid_ahb[pt[181-:8] - 1:0] : lsu_axi_rid[pt[181-:8] - 1:0]);
+	assign lsu_axi_rdata_int[63:0] = (pt[2038] ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0]);
+	assign lsu_axi_rresp_int[1:0] = (pt[2038] ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0]);
+	assign lsu_axi_rlast_int = (pt[2038] ? lsu_axi_rlast_ahb : lsu_axi_rlast);
+	assign ifu_axi_awready_int = (pt[2038] ? ifu_axi_awready_ahb : ifu_axi_awready);
+	assign ifu_axi_wready_int = (pt[2038] ? ifu_axi_wready_ahb : ifu_axi_wready);
+	assign ifu_axi_bvalid_int = (pt[2038] ? ifu_axi_bvalid_ahb : ifu_axi_bvalid);
+	assign ifu_axi_bready_int = (pt[2038] ? ifu_axi_bready_ahb : ifu_axi_bready);
+	assign ifu_axi_bresp_int[1:0] = (pt[2038] ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0]);
+	assign ifu_axi_bid_int[pt[826-:8] - 1:0] = (pt[2038] ? ifu_axi_bid_ahb[pt[826-:8] - 1:0] : ifu_axi_bid[pt[826-:8] - 1:0]);
+	assign ifu_axi_arready_int = (pt[2038] ? ifu_axi_arready_ahb : ifu_axi_arready);
+	assign ifu_axi_rvalid_int = (pt[2038] ? ifu_axi_rvalid_ahb : ifu_axi_rvalid);
+	assign ifu_axi_rid_int[pt[826-:8] - 1:0] = (pt[2038] ? ifu_axi_rid_ahb[pt[826-:8] - 1:0] : ifu_axi_rid[pt[826-:8] - 1:0]);
+	assign ifu_axi_rdata_int[63:0] = (pt[2038] ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0]);
+	assign ifu_axi_rresp_int[1:0] = (pt[2038] ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0]);
+	assign ifu_axi_rlast_int = (pt[2038] ? ifu_axi_rlast_ahb : ifu_axi_rlast);
+	assign sb_axi_awready_int = (pt[2038] ? sb_axi_awready_ahb : sb_axi_awready);
+	assign sb_axi_wready_int = (pt[2038] ? sb_axi_wready_ahb : sb_axi_wready);
+	assign sb_axi_bvalid_int = (pt[2038] ? sb_axi_bvalid_ahb : sb_axi_bvalid);
+	assign sb_axi_bready_int = (pt[2038] ? sb_axi_bready_ahb : sb_axi_bready);
+	assign sb_axi_bresp_int[1:0] = (pt[2038] ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0]);
+	assign sb_axi_bid_int[pt[12-:8] - 1:0] = (pt[2038] ? sb_axi_bid_ahb[pt[12-:8] - 1:0] : sb_axi_bid[pt[12-:8] - 1:0]);
+	assign sb_axi_arready_int = (pt[2038] ? sb_axi_arready_ahb : sb_axi_arready);
+	assign sb_axi_rvalid_int = (pt[2038] ? sb_axi_rvalid_ahb : sb_axi_rvalid);
+	assign sb_axi_rid_int[pt[12-:8] - 1:0] = (pt[2038] ? sb_axi_rid_ahb[pt[12-:8] - 1:0] : sb_axi_rid[pt[12-:8] - 1:0]);
+	assign sb_axi_rdata_int[63:0] = (pt[2038] ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0]);
+	assign sb_axi_rresp_int[1:0] = (pt[2038] ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0]);
+	assign sb_axi_rlast_int = (pt[2038] ? sb_axi_rlast_ahb : sb_axi_rlast);
+	assign dma_axi_awvalid_int = (pt[2038] ? dma_axi_awvalid_ahb : dma_axi_awvalid);
+	assign dma_axi_awid_int[pt[1235-:8] - 1:0] = (pt[2038] ? dma_axi_awid_ahb[pt[1235-:8] - 1:0] : dma_axi_awid[pt[1235-:8] - 1:0]);
+	assign dma_axi_awaddr_int[31:0] = (pt[2038] ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0]);
+	assign dma_axi_awsize_int[2:0] = (pt[2038] ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0]);
+	assign dma_axi_awprot_int[2:0] = (pt[2038] ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0]);
+	assign dma_axi_awlen_int[7:0] = (pt[2038] ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0]);
+	assign dma_axi_awburst_int[1:0] = (pt[2038] ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0]);
+	assign dma_axi_wvalid_int = (pt[2038] ? dma_axi_wvalid_ahb : dma_axi_wvalid);
+	assign dma_axi_wdata_int[63:0] = (pt[2038] ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata);
+	assign dma_axi_wstrb_int[7:0] = (pt[2038] ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0]);
+	assign dma_axi_wlast_int = (pt[2038] ? dma_axi_wlast_ahb : dma_axi_wlast);
+	assign dma_axi_bready_int = (pt[2038] ? dma_axi_bready_ahb : dma_axi_bready);
+	assign dma_axi_arvalid_int = (pt[2038] ? dma_axi_arvalid_ahb : dma_axi_arvalid);
+	assign dma_axi_arid_int[pt[1235-:8] - 1:0] = (pt[2038] ? dma_axi_arid_ahb[pt[1235-:8] - 1:0] : dma_axi_arid[pt[1235-:8] - 1:0]);
+	assign dma_axi_araddr_int[31:0] = (pt[2038] ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0]);
+	assign dma_axi_arsize_int[2:0] = (pt[2038] ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0]);
+	assign dma_axi_arprot_int[2:0] = (pt[2038] ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0]);
+	assign dma_axi_arlen_int[7:0] = (pt[2038] ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0]);
+	assign dma_axi_arburst_int[1:0] = (pt[2038] ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0]);
+	assign dma_axi_rready_int = (pt[2038] ? dma_axi_rready_ahb : dma_axi_rready);
+	assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt[102:71];
+	assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt[70:39];
+	assign trace_rv_i_valid_ip = trace_rv_trace_pkt[103];
+	assign trace_rv_i_exception_ip = trace_rv_trace_pkt[38];
+	assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt[37:33];
+	assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt[32];
+	assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt[31:0];
+endmodule
+module dmi_wrapper (
+	trst_n,
+	tck,
+	tms,
+	tdi,
+	tdo,
+	tdoEnable,
+	core_rst_n,
+	core_clk,
+	jtag_id,
+	rd_data,
+	reg_wr_data,
+	reg_wr_addr,
+	reg_en,
+	reg_wr_en,
+	dmi_hard_reset
+);
+	input trst_n;
+	input tck;
+	input tms;
+	input tdi;
+	output tdo;
+	output tdoEnable;
+	input core_rst_n;
+	input core_clk;
+	input [31:1] jtag_id;
+	input [31:0] rd_data;
+	output [31:0] reg_wr_data;
+	output [6:0] reg_wr_addr;
+	output reg_en;
+	output reg_wr_en;
+	output dmi_hard_reset;
+	wire rd_en;
+	wire wr_en;
+	wire dmireset;
+	rvjtag_tap i_jtag_tap(
+		.trst(trst_n),
+		.tck(tck),
+		.tms(tms),
+		.tdi(tdi),
+		.tdo(tdo),
+		.tdoEnable(tdoEnable),
+		.wr_data(reg_wr_data),
+		.wr_addr(reg_wr_addr),
+		.rd_en(rd_en),
+		.wr_en(wr_en),
+		.rd_data(rd_data),
+		.rd_status(2'b00),
+		.idle(3'h0),
+		.dmi_stat(2'b00),
+		.version(4'h1),
+		.jtag_id(jtag_id),
+		.dmi_hard_reset(dmi_hard_reset),
+		.dmi_reset(dmireset)
+	);
+	dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
+		.wr_en(wr_en),
+		.rd_en(rd_en),
+		.rst_n(core_rst_n),
+		.clk(core_clk),
+		.reg_en(reg_en),
+		.reg_wr_en(reg_wr_en)
+	);
+endmodule
+module eb1_uart_rx_prog (
+	i_Clock,
+	rst_ni,
+	i_Rx_Serial,
+	CLKS_PER_BIT,
+	o_Rx_DV,
+	o_Rx_Byte
+);
+	input i_Clock;
+	input rst_ni;
+	input i_Rx_Serial;
+	input [15:0] CLKS_PER_BIT;
+	output o_Rx_DV;
+	output [7:0] o_Rx_Byte;
+	parameter s_IDLE = 3'b000;
+	parameter s_RX_START_BIT = 3'b001;
+	parameter s_RX_DATA_BITS = 3'b010;
+	parameter s_RX_STOP_BIT = 3'b011;
+	parameter s_CLEANUP = 3'b100;
+	reg r_Rx_Data_R;
+	reg r_Rx_Data;
+	reg [15:0] r_Clock_Count;
+	reg [2:0] r_Bit_Index;
+	reg [7:0] r_Rx_Byte;
+	reg r_Rx_DV;
+	reg [2:0] r_SM_Main;
+	always @(posedge i_Clock)
+		if (rst_ni == 1'b0) begin
+			r_Rx_Data_R <= 1'b1;
+			r_Rx_Data <= 1'b1;
+		end
+		else begin
+			r_Rx_Data_R <= i_Rx_Serial;
+			r_Rx_Data <= r_Rx_Data_R;
+		end
+	always @(posedge i_Clock or negedge rst_ni)
+		if (rst_ni == 1'b0) begin
+			r_SM_Main <= s_IDLE;
+			r_Rx_DV <= 1'b0;
+			r_Clock_Count <= 16'h0000;
+			r_Bit_Index <= 3'b000;
+			r_Rx_Byte <= 8'h00;
+		end
+		else
+			case (r_SM_Main)
+				s_IDLE: begin
+					r_Rx_DV <= 1'b0;
+					r_Clock_Count <= 0;
+					r_Bit_Index <= 0;
+					if (r_Rx_Data == 1'b0)
+						r_SM_Main <= s_RX_START_BIT;
+					else
+						r_SM_Main <= s_IDLE;
+				end
+				s_RX_START_BIT:
+					if (r_Clock_Count == ((CLKS_PER_BIT - 1) >> 1)) begin
+						if (r_Rx_Data == 1'b0) begin
+							r_Clock_Count <= 0;
+							r_SM_Main <= s_RX_DATA_BITS;
+						end
+						else
+							r_SM_Main <= s_IDLE;
+					end
+					else begin
+						r_Clock_Count <= r_Clock_Count + 1;
+						r_SM_Main <= s_RX_START_BIT;
+					end
+				s_RX_DATA_BITS:
+					if (r_Clock_Count < (CLKS_PER_BIT - 1)) begin
+						r_Clock_Count <= r_Clock_Count + 1;
+						r_SM_Main <= s_RX_DATA_BITS;
+					end
+					else begin
+						r_Clock_Count <= 0;
+						r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+						if (r_Bit_Index < 7) begin
+							r_Bit_Index <= r_Bit_Index + 1;
+							r_SM_Main <= s_RX_DATA_BITS;
+						end
+						else begin
+							r_Bit_Index <= 0;
+							r_SM_Main <= s_RX_STOP_BIT;
+						end
+					end
+				s_RX_STOP_BIT:
+					if (r_Clock_Count < (CLKS_PER_BIT - 1)) begin
+						r_Clock_Count <= r_Clock_Count + 1;
+						r_SM_Main <= s_RX_STOP_BIT;
+					end
+					else begin
+						r_Rx_DV <= 1'b1;
+						r_Clock_Count <= 0;
+						r_SM_Main <= s_CLEANUP;
+					end
+				s_CLEANUP: begin
+					r_SM_Main <= s_IDLE;
+					r_Rx_DV <= 1'b0;
+				end
+				default: r_SM_Main <= s_IDLE;
+			endcase
+	assign o_Rx_DV = r_Rx_DV;
+	assign o_Rx_Byte = r_Rx_Byte;
+endmodule
+module eb1_iccm_controller (
+	clk_i,
+	rst_ni,
+	rx_dv_i,
+	rx_byte_i,
+	we_o,
+	addr_o,
+	wdata_o,
+	reset_o
+);
+	input wire clk_i;
+	input wire rst_ni;
+	input wire rx_dv_i;
+	input wire [7:0] rx_byte_i;
+	output wire we_o;
+	output wire [13:0] addr_o;
+	output wire [31:0] wdata_o;
+	output wire reset_o;
+	reg [1:0] ctrl_fsm_cs;
+	reg [1:0] ctrl_fsm_ns;
+	wire [7:0] rx_byte_d;
+	reg [7:0] rx_byte_q0;
+	reg [7:0] rx_byte_q1;
+	reg [7:0] rx_byte_q2;
+	reg [7:0] rx_byte_q3;
+	reg we_q;
+	reg we_d;
+	reg [13:0] addr_q;
+	reg [13:0] addr_d;
+	reg reset_q;
+	reg reset_d;
+	reg [1:0] byte_count;
+	localparam [1:0] DONE = 3;
+	localparam [1:0] LOAD = 1;
+	localparam [1:0] PROG = 2;
+	localparam [1:0] RESET = 0;
+	always @(*) begin
+		we_d = we_q;
+		addr_d = addr_q;
+		reset_d = reset_q;
+		ctrl_fsm_ns = ctrl_fsm_cs;
+		case (ctrl_fsm_cs)
+			RESET: begin
+				we_d = 1'b0;
+				reset_d = 1'b0;
+				if (rx_dv_i)
+					ctrl_fsm_ns = LOAD;
+				else
+					ctrl_fsm_ns = RESET;
+			end
+			LOAD:
+				if (((byte_count == 2'b11) && (rx_byte_q2 != 8'h0f)) && (rx_byte_d != 8'hff)) begin
+					we_d = 1'b1;
+					ctrl_fsm_ns = PROG;
+				end
+				else
+					ctrl_fsm_ns = DONE;
+			PROG: begin
+				we_d = 1'b0;
+				ctrl_fsm_ns = DONE;
+			end
+			DONE:
+				if (wdata_o == 32'h00000fff) begin
+					ctrl_fsm_ns = DONE;
+					reset_d = 1'b1;
+				end
+				else if (rx_dv_i)
+					ctrl_fsm_ns = LOAD;
+				else
+					ctrl_fsm_ns = DONE;
+			default: ctrl_fsm_ns = RESET;
+		endcase
+	end
+	assign rx_byte_d = rx_byte_i;
+	assign we_o = we_q;
+	assign addr_o = addr_q;
+	assign wdata_o = {rx_byte_q0, rx_byte_q1, rx_byte_q2, rx_byte_q3};
+	assign reset_o = reset_q;
+	always @(posedge clk_i or negedge rst_ni)
+		if (!rst_ni) begin
+			we_q <= 1'b0;
+			addr_q <= 14'b00000000000000;
+			rx_byte_q0 <= 8'b00000000;
+			rx_byte_q1 <= 8'b00000000;
+			rx_byte_q2 <= 8'b00000000;
+			rx_byte_q3 <= 8'b00000000;
+			reset_q <= 1'b0;
+			byte_count <= 2'b00;
+			ctrl_fsm_cs <= RESET;
+		end
+		else begin
+			we_q <= we_d;
+			if (ctrl_fsm_cs == LOAD) begin
+				if (byte_count == 2'b00) begin
+					rx_byte_q0 <= rx_byte_d;
+					byte_count <= 2'b01;
+				end
+				else if (byte_count == 2'b01) begin
+					rx_byte_q1 <= rx_byte_d;
+					byte_count <= 2'b10;
+				end
+				else if (byte_count == 2'b10) begin
+					rx_byte_q2 <= rx_byte_d;
+					byte_count <= 2'b11;
+				end
+				else begin
+					rx_byte_q3 <= rx_byte_d;
+					byte_count <= 2'b00;
+				end
+				addr_q <= addr_d;
+			end
+			if (ctrl_fsm_cs == PROG)
+				addr_q <= addr_d + 2'h2;
+			reset_q <= reset_d;
+			ctrl_fsm_cs <= ctrl_fsm_ns;
+		end
+endmodule
+module eb1_mem (
+`ifdef USE_POWER_PINS
+	vccd1,
+	vssd1,
+`endif
+	clk,
+	rst_l,
+	dccm_clk_override,
+	icm_clk_override,
+	dec_tlu_core_ecc_disable,
+	dccm_wren,
+	dccm_rden,
+	dccm_wr_addr_lo,
+	dccm_wr_addr_hi,
+	dccm_rd_addr_lo,
+	dccm_rd_addr_hi,
+	dccm_wr_data_lo,
+	dccm_wr_data_hi,
+	dccm_rd_data_lo,
+	dccm_rd_data_hi,
+	dccm_ext_in_pkt,
+	iccm_ext_in_pkt,
+	iccm_rw_addr,
+	iccm_buf_correct_ecc,
+	iccm_correction_state,
+	iccm_wren,
+	iccm_rden,
+	iccm_wr_size,
+	iccm_wr_data,
+	iccm_rd_data,
+	iccm_rd_data_ecc,
+	ic_rw_addr,
+	ic_tag_valid,
+	ic_wr_en,
+	ic_rd_en,
+	ic_premux_data,
+	ic_sel_premux_data,
+	ic_data_ext_in_pkt,
+	ic_tag_ext_in_pkt,
+	ic_wr_data,
+	ic_debug_wr_data,
+	ic_debug_rd_data,
+	ic_debug_addr,
+	ic_debug_rd_en,
+	ic_debug_wr_en,
+	ic_debug_tag_array,
+	ic_debug_way,
+	ic_rd_data,
+	ictag_debug_rd_data,
+	ic_eccerr,
+	ic_parerr,
+	ic_rd_hit,
+	ic_tag_perr,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+`ifdef USE_POWER_PINS
+	inout wire vccd1;
+	inout wire vssd1;
+`endif
+	input wire clk;
+	input wire rst_l;
+	input wire dccm_clk_override;
+	input wire icm_clk_override;
+	input wire dec_tlu_core_ecc_disable;
+	input wire dccm_wren;
+	input wire dccm_rden;
+	input wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	input wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	input wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	input wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	input wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	input wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	output wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	output wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	input wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt;
+	input wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt;
+	input wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	input wire iccm_buf_correct_ecc;
+	input wire iccm_correction_state;
+	input wire iccm_wren;
+	input wire iccm_rden;
+	input wire [2:0] iccm_wr_size;
+	input wire [77:0] iccm_wr_data;
+	output wire [63:0] iccm_rd_data;
+	output wire [77:0] iccm_rd_data_ecc;
+	input wire [31:1] ic_rw_addr;
+	input wire [pt[1060-:7] - 1:0] ic_tag_valid;
+	input wire [pt[1060-:7] - 1:0] ic_wr_en;
+	input wire ic_rd_en;
+	input wire [63:0] ic_premux_data;
+	input wire ic_sel_premux_data;
+	input wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt;
+	input wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt;
+	input wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data;
+	input wire [70:0] ic_debug_wr_data;
+	output wire [70:0] ic_debug_rd_data;
+	input wire [pt[1104-:9]:3] ic_debug_addr;
+	input wire ic_debug_rd_en;
+	input wire ic_debug_wr_en;
+	input wire ic_debug_tag_array;
+	input wire [pt[1060-:7] - 1:0] ic_debug_way;
+	output wire [63:0] ic_rd_data;
+	output wire [25:0] ictag_debug_rd_data;
+	output wire [pt[1189-:7] - 1:0] ic_eccerr;
+	output wire [pt[1189-:7] - 1:0] ic_parerr;
+	output wire [pt[1060-:7] - 1:0] ic_rd_hit;
+	output wire ic_tag_perr;
+	input wire scan_mode;
+	wire active_clk;
+	rvoclkhdr active_cg(
+		.en(1'b1),
+		.l1clk(active_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	generate
+		if (pt[1365-:5] == 1) begin : Gen_dccm_enable
+			eb1_lsu_dccm_mem #(.pt(pt)) dccm(
+				.clk_override(dccm_clk_override),
+				`ifdef USE_POWER_PINS
+				.vccd1(vccd1),
+				.vssd1(vssd1),
+				`endif
+				.clk(clk),
+				.active_clk(active_clk),
+				.rst_l(rst_l),
+				.dccm_wren(dccm_wren),
+				.dccm_rden(dccm_rden),
+				.dccm_wr_addr_lo(dccm_wr_addr_lo),
+				.dccm_wr_addr_hi(dccm_wr_addr_hi),
+				.dccm_rd_addr_lo(dccm_rd_addr_lo),
+				.dccm_rd_addr_hi(dccm_rd_addr_hi),
+				.dccm_wr_data_lo(dccm_wr_data_lo),
+				.dccm_wr_data_hi(dccm_wr_data_hi),
+				.dccm_ext_in_pkt(dccm_ext_in_pkt),
+				.dccm_rd_data_lo(dccm_rd_data_lo),
+				.dccm_rd_data_hi(dccm_rd_data_hi),
+				.scan_mode(scan_mode)
+			);
+		end
+		else begin : Gen_dccm_disable
+			assign dccm_rd_data_lo = {pt[1360-:10] {1'sb0}};
+			assign dccm_rd_data_hi = {pt[1360-:10] {1'sb0}};
+		end
+	endgenerate
+	generate
+		if (pt[1120-:5]) begin : icache
+			eb1_ifu_ic_mem #(.pt(pt)) icm(
+				.clk_override(icm_clk_override),
+				.*
+			);
+		end
+		else begin
+			assign ic_rd_hit[pt[1060-:7] - 1:0] = {pt[1060-:7] {1'sb0}};
+			assign ic_tag_perr = 1'b0;
+			assign ic_rd_data = {64 {1'sb0}};
+			assign ictag_debug_rd_data = {26 {1'sb0}};
+		end
+	endgenerate
+	generate
+		if (pt[927-:5]) begin : iccm
+			eb1_ifu_iccm_mem #(.pt(pt)) iccm(
+				`ifdef USE_POWER_PINS
+				.vccd1(vccd1),
+				.vssd1(vssd1),
+				`endif
+				.clk(clk),
+				.active_clk(active_clk),
+				.rst_l(rst_l),
+				.iccm_wren(iccm_wren),
+				.iccm_rden(iccm_rden),
+				.iccm_buf_correct_ecc(iccm_buf_correct_ecc),
+				.iccm_correction_state(iccm_correction_state),
+				.iccm_wr_size(iccm_wr_size),
+				.iccm_wr_data(iccm_wr_data),
+				.iccm_ext_in_pkt(iccm_ext_in_pkt),
+				.iccm_rd_data_ecc(iccm_rd_data_ecc),
+				.scan_mode(scan_mode),
+				.clk_override(icm_clk_override),
+				.iccm_rw_addr(iccm_rw_addr[pt[936-:9] - 1:1]),
+				.iccm_rd_data(iccm_rd_data[63:0])
+			);
+		end
+		else begin
+			assign iccm_rd_data = {64 {1'sb0}};
+			assign iccm_rd_data_ecc = {78 {1'sb0}};
+		end
+	endgenerate
+endmodule
+module eb1_pic_ctrl (
+	clk,
+	free_clk,
+	rst_l,
+	clk_override,
+	io_clk_override,
+	extintsrc_req,
+	picm_rdaddr,
+	picm_wraddr,
+	picm_wr_data,
+	picm_wren,
+	picm_rden,
+	picm_mken,
+	meicurpl,
+	meipt,
+	mexintpend,
+	claimid,
+	pl,
+	picm_rd_data,
+	mhwakeup,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire free_clk;
+	input wire rst_l;
+	input wire clk_override;
+	input wire io_clk_override;
+	input wire [pt[44-:13] - 1:0] extintsrc_req;
+	input wire [31:0] picm_rdaddr;
+	input wire [31:0] picm_wraddr;
+	input wire [31:0] picm_wr_data;
+	input wire picm_wren;
+	input wire picm_rden;
+	input wire picm_mken;
+	input wire [3:0] meicurpl;
+	input wire [3:0] meipt;
+	output wire mexintpend;
+	output wire [7:0] claimid;
+	output wire [3:0] pl;
+	output wire [31:0] picm_rd_data;
+	output wire mhwakeup;
+	input wire scan_mode;
+	localparam NUM_LEVELS = $clog2(pt[44-:13]);
+	localparam INTPRIORITY_BASE_ADDR = pt[130-:36];
+	localparam INTPEND_BASE_ADDR = pt[130-:36] + 32'h00001000;
+	localparam INTENABLE_BASE_ADDR = pt[130-:36] + 32'h00002000;
+	localparam EXT_INTR_PIC_CONFIG = pt[130-:36] + 32'h00003000;
+	localparam EXT_INTR_GW_CONFIG = pt[130-:36] + 32'h00004000;
+	localparam EXT_INTR_GW_CLEAR = pt[130-:36] + 32'h00005000;
+	localparam INTPEND_SIZE = (pt[44-:13] < 32 ? 32 : (pt[44-:13] < 64 ? 64 : (pt[44-:13] < 128 ? 128 : (pt[44-:13] < 256 ? 256 : (pt[44-:13] < 512 ? 512 : 1024)))));
+	localparam INT_GRPS = INTPEND_SIZE / 32;
+	localparam INTPRIORITY_BITS = 4;
+	localparam ID_BITS = 8;
+	localparam signed [(pt[44-:13] * 32) - 1:0] GW_CONFIG = {pt[44-:13] {32'sd0}};
+	localparam INT_ENABLE_GRPS = (pt[44-:13] - 1) / 4;
+	wire [pt[44-:13] - 1:0] intenable_clk_enable;
+	wire [INT_ENABLE_GRPS:0] intenable_clk_enable_grp;
+	wire [INT_ENABLE_GRPS:0] gw_clk;
+	wire addr_intpend_base_match;
+	wire raddr_config_pic_match;
+	wire raddr_intenable_base_match;
+	wire raddr_intpriority_base_match;
+	wire raddr_config_gw_base_match;
+	wire waddr_config_pic_match;
+	wire waddr_intpriority_base_match;
+	wire waddr_intenable_base_match;
+	wire waddr_config_gw_base_match;
+	wire addr_clear_gw_base_match;
+	wire mexintpend_in;
+	wire mhwakeup_in;
+	wire intpend_reg_read;
+	wire [31:0] picm_rd_data_in;
+	reg [31:0] intpend_rd_out;
+	reg intenable_rd_out;
+	reg [3:0] intpriority_rd_out;
+	reg [1:0] gw_config_rd_out;
+	wire [(pt[44-:13] * 4) - 1:0] intpriority_reg;
+	wire [(pt[44-:13] * 4) - 1:0] intpriority_reg_inv;
+	wire [pt[44-:13] - 1:0] intpriority_reg_we;
+	wire [pt[44-:13] - 1:0] intpriority_reg_re;
+	wire [(pt[44-:13] * 2) - 1:0] gw_config_reg;
+	wire [pt[44-:13] - 1:0] intenable_reg;
+	wire [pt[44-:13] - 1:0] intenable_reg_we;
+	wire [pt[44-:13] - 1:0] intenable_reg_re;
+	wire [pt[44-:13] - 1:0] gw_config_reg_we;
+	wire [pt[44-:13] - 1:0] gw_config_reg_re;
+	wire [pt[44-:13] - 1:0] gw_clear_reg_we;
+	wire [INTPEND_SIZE - 1:0] intpend_reg_extended;
+	wire [(pt[44-:13] * 4) - 1:0] intpend_w_prior_en;
+	wire [(pt[44-:13] * 8) - 1:0] intpend_id;
+	wire [3:0] maxint;
+	wire [3:0] selected_int_priority;
+	wire [(INT_GRPS * 32) - 1:0] intpend_rd_part_out;
+	wire config_reg;
+	wire intpriord;
+	wire config_reg_we;
+	wire config_reg_re;
+	wire config_reg_in;
+	wire prithresh_reg_write;
+	wire prithresh_reg_read;
+	wire intpriority_reg_read;
+	wire intenable_reg_read;
+	wire gw_config_reg_read;
+	wire picm_wren_ff;
+	wire picm_rden_ff;
+	wire [31:0] picm_raddr_ff;
+	wire [31:0] picm_waddr_ff;
+	wire [31:0] picm_wr_data_ff;
+	reg [3:0] mask;
+	wire picm_mken_ff;
+	wire [7:0] claimid_in;
+	wire [3:0] pl_in;
+	wire [3:0] pl_in_q;
+	wire [pt[44-:13] - 1:0] extintsrc_req_sync;
+	wire [pt[44-:13] - 1:0] extintsrc_req_gw;
+	wire picm_bypass_ff;
+	wire pic_raddr_c1_clken;
+	wire pic_waddr_c1_clken;
+	wire pic_data_c1_clken;
+	wire pic_pri_c1_clken;
+	wire pic_int_c1_clken;
+	wire gw_config_c1_clken;
+	wire pic_raddr_c1_clk;
+	wire pic_data_c1_clk;
+	wire pic_pri_c1_clk;
+	wire pic_int_c1_clk;
+	wire gw_config_c1_clk;
+	assign pic_raddr_c1_clken = (picm_mken | picm_rden) | clk_override;
+	assign pic_data_c1_clken = picm_wren | clk_override;
+	assign pic_pri_c1_clken = ((waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff)) | clk_override;
+	assign pic_int_c1_clken = ((waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff)) | clk_override;
+	assign gw_config_c1_clken = ((waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff)) | clk_override;
+	rvoclkhdr pic_addr_c1_cgc(
+		.en(pic_raddr_c1_clken),
+		.l1clk(pic_raddr_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr pic_data_c1_cgc(
+		.en(pic_data_c1_clken),
+		.l1clk(pic_data_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr pic_pri_c1_cgc(
+		.en(pic_pri_c1_clken),
+		.l1clk(pic_pri_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr pic_int_c1_cgc(
+		.en(pic_int_c1_clken),
+		.l1clk(pic_int_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr gw_config_c1_cgc(
+		.en(gw_config_c1_clken),
+		.l1clk(gw_config_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign raddr_intenable_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS + 2];
+	assign raddr_intpriority_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS + 2];
+	assign raddr_config_gw_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS + 2];
+	assign raddr_config_pic_match = picm_raddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0];
+	assign addr_intpend_base_match = picm_raddr_ff[31:6] == INTPEND_BASE_ADDR[31:6];
+	assign waddr_config_pic_match = picm_waddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0];
+	assign addr_clear_gw_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS + 2];
+	assign waddr_intpriority_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS + 2];
+	assign waddr_intenable_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS + 2];
+	assign waddr_config_gw_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS + 2];
+	assign picm_bypass_ff = (picm_rden_ff & picm_wren_ff) & (picm_raddr_ff[31:0] == picm_waddr_ff[31:0]);
+	rvdff #(.WIDTH(32)) picm_radd_flop(
+		.rst_l(rst_l),
+		.din(picm_rdaddr),
+		.dout(picm_raddr_ff),
+		.clk(pic_raddr_c1_clk)
+	);
+	rvdff #(.WIDTH(32)) picm_wadd_flop(
+		.rst_l(rst_l),
+		.din(picm_wraddr),
+		.dout(picm_waddr_ff),
+		.clk(pic_data_c1_clk)
+	);
+	rvdff #(.WIDTH(1)) picm_wre_flop(
+		.rst_l(rst_l),
+		.din(picm_wren),
+		.dout(picm_wren_ff),
+		.clk(free_clk)
+	);
+	rvdff #(.WIDTH(1)) picm_rde_flop(
+		.rst_l(rst_l),
+		.din(picm_rden),
+		.dout(picm_rden_ff),
+		.clk(free_clk)
+	);
+	rvdff #(.WIDTH(1)) picm_mke_flop(
+		.rst_l(rst_l),
+		.din(picm_mken),
+		.dout(picm_mken_ff),
+		.clk(free_clk)
+	);
+	rvdff #(.WIDTH(32)) picm_dat_flop(
+		.rst_l(rst_l),
+		.din(picm_wr_data[31:0]),
+		.dout(picm_wr_data_ff[31:0]),
+		.clk(pic_data_c1_clk)
+	);
+	genvar p;
+	generate
+		for (p = 0; p <= INT_ENABLE_GRPS; p = p + 1) begin : IO_CLK_GRP
+			if (p == INT_ENABLE_GRPS) begin : LAST_GRP
+				assign intenable_clk_enable_grp[p] = |intenable_clk_enable[pt[44-:13] - 1:p * 4] | io_clk_override;
+				rvoclkhdr intenable_c1_cgc(
+					.en(intenable_clk_enable_grp[p]),
+					.l1clk(gw_clk[p]),
+					.clk(clk),
+					.scan_mode(scan_mode)
+				);
+			end
+			else begin : CLK_GRPS
+				assign intenable_clk_enable_grp[p] = |intenable_clk_enable[(p * 4) + 3:p * 4] | io_clk_override;
+				rvoclkhdr intenable_c1_cgc(
+					.en(intenable_clk_enable_grp[p]),
+					.l1clk(gw_clk[p]),
+					.clk(clk),
+					.scan_mode(scan_mode)
+				);
+			end
+		end
+	endgenerate
+	genvar i;
+	generate
+		for (i = 0; i < pt[44-:13]; i = i + 1) begin : SETREG
+			if (i > 0) begin : NON_ZERO_INT
+				assign intpriority_reg_we[i] = (waddr_intpriority_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff;
+				assign intpriority_reg_re[i] = (raddr_intpriority_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff;
+				assign intenable_reg_we[i] = (waddr_intenable_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff;
+				assign intenable_reg_re[i] = (raddr_intenable_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff;
+				assign gw_config_reg_we[i] = (waddr_config_gw_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff;
+				assign gw_config_reg_re[i] = (raddr_config_gw_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff;
+				assign gw_clear_reg_we[i] = (addr_clear_gw_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff;
+				rvdffs #(.WIDTH(INTPRIORITY_BITS)) intpriority_ff(
+					.rst_l(rst_l),
+					.en(intpriority_reg_we[i]),
+					.din(picm_wr_data_ff[3:0]),
+					.dout(intpriority_reg[i * 4+:4]),
+					.clk(pic_pri_c1_clk)
+				);
+				rvdffs #(.WIDTH(1)) intenable_ff(
+					.rst_l(rst_l),
+					.en(intenable_reg_we[i]),
+					.din(picm_wr_data_ff[0]),
+					.dout(intenable_reg[i]),
+					.clk(pic_int_c1_clk)
+				);
+				assign intenable_clk_enable[i] = ((gw_config_reg[(i * 2) + 1] | intenable_reg_we[i]) | intenable_reg[i]) | gw_clear_reg_we[i];
+				rvsyncss_fpga #(.WIDTH(1)) sync_inst(
+					.gw_clk(gw_clk[i / 4]),
+					.rawclk(clk),
+					.clken(intenable_clk_enable_grp[i / 4]),
+					.dout(extintsrc_req_sync[i]),
+					.din(extintsrc_req[i]),
+					.rst_l(rst_l)
+				);
+				rvdffs #(.WIDTH(2)) gw_config_ff(
+					.rst_l(rst_l),
+					.en(gw_config_reg_we[i]),
+					.din(picm_wr_data_ff[1:0]),
+					.dout(gw_config_reg[i * 2+:2]),
+					.clk(gw_config_c1_clk)
+				);
+				eb1_configurable_gw config_gw_inst(
+					.rst_l(rst_l),
+					.gw_clk(gw_clk[i / 4]),
+					.rawclk(clk),
+					.clken(intenable_clk_enable_grp[i / 4]),
+					.extintsrc_req_sync(extintsrc_req_sync[i]),
+					.meigwctrl_polarity(gw_config_reg[i * 2]),
+					.meigwctrl_type(gw_config_reg[(i * 2) + 1]),
+					.meigwclr(gw_clear_reg_we[i]),
+					.extintsrc_req_config(extintsrc_req_gw[i])
+				);
+			end
+			else begin : INT_ZERO
+				assign intpriority_reg_we[i] = 1'b0;
+				assign intpriority_reg_re[i] = 1'b0;
+				assign intenable_reg_we[i] = 1'b0;
+				assign intenable_reg_re[i] = 1'b0;
+				assign gw_config_reg_we[i] = 1'b0;
+				assign gw_config_reg_re[i] = 1'b0;
+				assign gw_clear_reg_we[i] = 1'b0;
+				assign gw_config_reg[i * 2+:2] = {2 {1'sb0}};
+				assign intpriority_reg[i * 4+:4] = {INTPRIORITY_BITS {1'b0}};
+				assign intenable_reg[i] = 1'b0;
+				assign extintsrc_req_gw[i] = 1'b0;
+				assign extintsrc_req_sync[i] = 1'b0;
+				assign intenable_clk_enable[i] = 1'b0;
+			end
+			assign intpriority_reg_inv[i * 4+:4] = (intpriord ? ~intpriority_reg[i * 4+:4] : intpriority_reg[i * 4+:4]);
+			assign intpend_w_prior_en[i * 4+:4] = {INTPRIORITY_BITS {extintsrc_req_gw[i] & intenable_reg[i]}} & intpriority_reg_inv[i * 4+:4];
+			assign intpend_id[i * 8+:8] = i;
+		end
+	endgenerate
+	assign pl_in[3:0] = selected_int_priority[3:0];
+	genvar l;
+	genvar m;
+	genvar j;
+	genvar k;
+	generate
+		if (pt[135-:5] == 1) begin : genblock
+			wire [(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))))) + 1) * 4) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 4) - 1) : (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))) + 1) * 4) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 4) - 1)):(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 4 : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 4)] level_intpend_w_prior_en;
+			wire [(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))))) + 1) * 8) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 8) - 1) : (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))) + 1) * 8) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 8) - 1)):(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 8 : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 8)] level_intpend_id;
+			wire [((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))))) + 1) * 4) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 4) - 1) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))) + 1) * 4) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 4) - 1)):((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 4 : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 4)] levelx_intpend_w_prior_en;
+			wire [((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))))) + 1) * 8) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 8) - 1) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))) + 1) * 8) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 8) - 1)):((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 8 : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 8)] levelx_intpend_id;
+			assign level_intpend_w_prior_en[4 * (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))))+:4 * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))] = {12'b000000000000, intpend_w_prior_en[4 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:4 * pt[44-:13]]};
+			assign level_intpend_id[8 * (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))))+:8 * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))] = {24'b000000000000000000000000, intpend_id[8 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:8 * pt[44-:13]]};
+			wire [((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) * 4) - 1 : ((1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) * 4) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 4) - 1)):((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 4)] l2_intpend_w_prior_en_ff;
+			wire [((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) * 8) - 1 : ((1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) * 8) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 8) - 1)):((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 8)] l2_intpend_id_ff;
+			assign levelx_intpend_w_prior_en[4 * ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))))+:4 * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))] = {{4 {1'b0}}, l2_intpend_w_prior_en_ff[4 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)) : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)))+:4 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))]};
+			assign levelx_intpend_id[8 * ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))))+:8 * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))] = {{8 {1'b1}}, l2_intpend_id_ff[8 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)) : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)))+:8 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))]};
+			for (l = 0; l < (NUM_LEVELS / 2); l = l + 1) begin : TOP_LEVEL
+				for (m = 0; m <= (pt[44-:13] / (2 ** (l + 1))); m = m + 1) begin : COMPARE
+					if (m == (pt[44-:13] / (2 ** (l + 1)))) begin
+						assign level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4] = {4 {1'sb0}};
+						assign level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8] = {8 {1'sb0}};
+					end
+					eb1_cmp_and_mux #(
+						.ID_BITS(ID_BITS),
+						.INTPRIORITY_BITS(INTPRIORITY_BITS)
+					) cmp_l1(
+						.a_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]),
+						.a_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]),
+						.b_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]),
+						.b_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]),
+						.out_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]),
+						.out_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4])
+					);
+				end
+			end
+			for (i = 0; i <= (pt[44-:13] / (2 ** (NUM_LEVELS / 2))); i = i + 1) begin : MIDDLE_FLOPS
+				rvdff #(.WIDTH(INTPRIORITY_BITS)) leveb1_intpend_prior_reg(
+					.rst_l(rst_l),
+					.din(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]),
+					.dout(l2_intpend_w_prior_en_ff[((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? i : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - i) * 4+:4]),
+					.clk(free_clk)
+				);
+				rvdff #(.WIDTH(ID_BITS)) leveb1_intpend_id_reg(
+					.rst_l(rst_l),
+					.din(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]),
+					.dout(l2_intpend_id_ff[((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? i : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - i) * 8+:8]),
+					.clk(free_clk)
+				);
+			end
+			for (j = NUM_LEVELS / 2; j < NUM_LEVELS; j = j + 1) begin : BOT_LEVELS
+				for (k = 0; k <= (pt[44-:13] / (2 ** (j + 1))); k = k + 1) begin : COMPARE
+					if (k == (pt[44-:13] / (2 ** (j + 1)))) begin
+						assign levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4] = {4 {1'sb0}};
+						assign levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8] = {8 {1'sb0}};
+					end
+					eb1_cmp_and_mux #(
+						.ID_BITS(ID_BITS),
+						.INTPRIORITY_BITS(INTPRIORITY_BITS)
+					) cmp_l1(
+						.a_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]),
+						.a_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]),
+						.b_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]),
+						.b_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]),
+						.out_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]),
+						.out_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4])
+					);
+				end
+			end
+			assign claimid_in[7:0] = levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8];
+			assign selected_int_priority[3:0] = levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4];
+		end
+		else begin : genblock
+			wire [((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))))) + 1) * 4) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 4) - 1) : ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))) + 1) * 4) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 4) - 1)):((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 4 : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 4)] level_intpend_w_prior_en;
+			wire [((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))))) + 1) * 8) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 8) - 1) : ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))) + 1) * 8) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 8) - 1)):((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 8 : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 8)] level_intpend_id;
+			assign level_intpend_w_prior_en[4 * ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))))+:4 * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))] = {{8 {1'b0}}, intpend_w_prior_en[4 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:4 * pt[44-:13]]};
+			assign level_intpend_id[8 * ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))))+:8 * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))] = {{16 {1'b1}}, intpend_id[8 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:8 * pt[44-:13]]};
+			for (l = 0; l < NUM_LEVELS; l = l + 1) begin : LEVEL
+				for (m = 0; m <= (pt[44-:13] / (2 ** (l + 1))); m = m + 1) begin : COMPARE
+					if (m == (pt[44-:13] / (2 ** (l + 1)))) begin
+						assign level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4] = {4 {1'sb0}};
+						assign level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8] = {8 {1'sb0}};
+					end
+					eb1_cmp_and_mux #(
+						.ID_BITS(ID_BITS),
+						.INTPRIORITY_BITS(INTPRIORITY_BITS)
+					) cmp_l1(
+						.a_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]),
+						.a_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]),
+						.b_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]),
+						.b_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]),
+						.out_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]),
+						.out_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4])
+					);
+				end
+			end
+			assign claimid_in[7:0] = level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8];
+			assign selected_int_priority[3:0] = level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + pt[44-:13]) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4];
+		end
+	endgenerate
+	assign config_reg_we = waddr_config_pic_match & picm_wren_ff;
+	assign config_reg_re = raddr_config_pic_match & picm_rden_ff;
+	assign config_reg_in = picm_wr_data_ff[0];
+	rvdffs #(.WIDTH(1)) config_reg_ff(
+		.rst_l(rst_l),
+		.clk(free_clk),
+		.en(config_reg_we),
+		.din(config_reg_in),
+		.dout(config_reg)
+	);
+	assign intpriord = config_reg;
+	assign pl_in_q[3:0] = (intpriord ? ~pl_in : pl_in);
+	rvdff #(.WIDTH(ID_BITS)) claimid_ff(
+		.rst_l(rst_l),
+		.din(claimid_in[7:0]),
+		.dout(claimid[7:0]),
+		.clk(free_clk)
+	);
+	rvdff #(.WIDTH(INTPRIORITY_BITS)) pl_ff(
+		.rst_l(rst_l),
+		.din(pl_in_q[3:0]),
+		.dout(pl[3:0]),
+		.clk(free_clk)
+	);
+	wire [3:0] meipt_inv;
+	wire [3:0] meicurpl_inv;
+	assign meipt_inv[3:0] = (intpriord ? ~meipt[3:0] : meipt[3:0]);
+	assign meicurpl_inv[3:0] = (intpriord ? ~meicurpl[3:0] : meicurpl[3:0]);
+	assign mexintpend_in = (selected_int_priority[3:0] > meipt_inv[3:0]) & (selected_int_priority[3:0] > meicurpl_inv[3:0]);
+	rvdff #(.WIDTH(1)) mexintpend_ff(
+		.rst_l(rst_l),
+		.clk(free_clk),
+		.din(mexintpend_in),
+		.dout(mexintpend)
+	);
+	assign maxint[3:0] = (intpriord ? 0 : 15);
+	assign mhwakeup_in = pl_in_q[3:0] == maxint;
+	rvdff #(.WIDTH(1)) wake_up_ff(
+		.rst_l(rst_l),
+		.clk(free_clk),
+		.din(mhwakeup_in),
+		.dout(mhwakeup)
+	);
+	assign intpend_reg_read = addr_intpend_base_match & picm_rden_ff;
+	assign intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff;
+	assign intenable_reg_read = raddr_intenable_base_match & picm_rden_ff;
+	assign gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff;
+	assign intpend_reg_extended[INTPEND_SIZE - 1:0] = {{INTPEND_SIZE - pt[44-:13] {1'b0}}, extintsrc_req_gw[pt[44-:13] - 1:0]};
+	generate
+		for (i = 0; i < INT_GRPS; i = i + 1) assign intpend_rd_part_out[i * 32+:32] = {32 {intpend_reg_read & (picm_raddr_ff[5:2] == i)}} & intpend_reg_extended[(32 * i) + 31:32 * i];
+	endgenerate
+	always @(*) begin : INTPEND_RD
+		intpend_rd_out = {32 {1'sb0}};
+		begin : sv2v_autoblock_34
+			reg signed [31:0] i;
+			for (i = 0; i < INT_GRPS; i = i + 1)
+				intpend_rd_out = intpend_rd_out | intpend_rd_part_out[i * 32+:32];
+		end
+	end
+	always @(*) begin : INTEN_RD
+		intenable_rd_out = 1'b0;
+		intpriority_rd_out = {4 {1'sb0}};
+		gw_config_rd_out = {2 {1'sb0}};
+		begin : sv2v_autoblock_35
+			reg signed [31:0] i;
+			for (i = 0; i < pt[44-:13]; i = i + 1)
+				begin
+					if (intenable_reg_re[i])
+						intenable_rd_out = intenable_reg[i];
+					if (intpriority_reg_re[i])
+						intpriority_rd_out = intpriority_reg[i * 4+:4];
+					if (gw_config_reg_re[i])
+						gw_config_rd_out = gw_config_reg[i * 2+:2];
+				end
+		end
+	end
+	assign picm_rd_data_in[31:0] = (((((((({32 {intpend_reg_read}} & intpend_rd_out) | ({32 {intpriority_reg_read}} & {{28 {1'b0}}, intpriority_rd_out})) | ({32 {intenable_reg_read}} & {31'b0000000000000000000000000000000, intenable_rd_out})) | ({32 {gw_config_reg_read}} & {30'b000000000000000000000000000000, gw_config_rd_out})) | ({32 {config_reg_re}} & {31'b0000000000000000000000000000000, config_reg})) | ({32 {picm_mken_ff & mask[3]}} & 32'b00000000000000000000000000000011)) | ({32 {picm_mken_ff & mask[2]}} & 32'b00000000000000000000000000000001)) | ({32 {picm_mken_ff & mask[1]}} & 32'b00000000000000000000000000001111)) | ({32 {picm_mken_ff & mask[0]}} & 32'b00000000000000000000000000000000);
+	assign picm_rd_data[31:0] = (picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0]);
+	wire [14:0] address;
+	assign address[14:0] = picm_raddr_ff[14:0];
+	always @(*)
+		case (address[14:0])
+			15'b011000000000000: mask[3:0] = 4'b0100;
+			15'b100000000000100: mask[3:0] = 4'b1000;
+			15'b100000000001000: mask[3:0] = 4'b1000;
+			15'b100000000001100: mask[3:0] = 4'b1000;
+			15'b100000000010000: mask[3:0] = 4'b1000;
+			15'b100000000010100: mask[3:0] = 4'b1000;
+			15'b100000000011000: mask[3:0] = 4'b1000;
+			15'b100000000011100: mask[3:0] = 4'b1000;
+			15'b100000000100000: mask[3:0] = 4'b1000;
+			15'b100000000100100: mask[3:0] = 4'b1000;
+			15'b100000000101000: mask[3:0] = 4'b1000;
+			15'b100000000101100: mask[3:0] = 4'b1000;
+			15'b100000000110000: mask[3:0] = 4'b1000;
+			15'b100000000110100: mask[3:0] = 4'b1000;
+			15'b100000000111000: mask[3:0] = 4'b1000;
+			15'b100000000111100: mask[3:0] = 4'b1000;
+			15'b100000001000000: mask[3:0] = 4'b1000;
+			15'b100000001000100: mask[3:0] = 4'b1000;
+			15'b100000001001000: mask[3:0] = 4'b1000;
+			15'b100000001001100: mask[3:0] = 4'b1000;
+			15'b100000001010000: mask[3:0] = 4'b1000;
+			15'b100000001010100: mask[3:0] = 4'b1000;
+			15'b100000001011000: mask[3:0] = 4'b1000;
+			15'b100000001011100: mask[3:0] = 4'b1000;
+			15'b100000001100000: mask[3:0] = 4'b1000;
+			15'b100000001100100: mask[3:0] = 4'b1000;
+			15'b100000001101000: mask[3:0] = 4'b1000;
+			15'b100000001101100: mask[3:0] = 4'b1000;
+			15'b100000001110000: mask[3:0] = 4'b1000;
+			15'b100000001110100: mask[3:0] = 4'b1000;
+			15'b100000001111000: mask[3:0] = 4'b1000;
+			15'b100000001111100: mask[3:0] = 4'b1000;
+			15'b010000000000100: mask[3:0] = 4'b0100;
+			15'b010000000001000: mask[3:0] = 4'b0100;
+			15'b010000000001100: mask[3:0] = 4'b0100;
+			15'b010000000010000: mask[3:0] = 4'b0100;
+			15'b010000000010100: mask[3:0] = 4'b0100;
+			15'b010000000011000: mask[3:0] = 4'b0100;
+			15'b010000000011100: mask[3:0] = 4'b0100;
+			15'b010000000100000: mask[3:0] = 4'b0100;
+			15'b010000000100100: mask[3:0] = 4'b0100;
+			15'b010000000101000: mask[3:0] = 4'b0100;
+			15'b010000000101100: mask[3:0] = 4'b0100;
+			15'b010000000110000: mask[3:0] = 4'b0100;
+			15'b010000000110100: mask[3:0] = 4'b0100;
+			15'b010000000111000: mask[3:0] = 4'b0100;
+			15'b010000000111100: mask[3:0] = 4'b0100;
+			15'b010000001000000: mask[3:0] = 4'b0100;
+			15'b010000001000100: mask[3:0] = 4'b0100;
+			15'b010000001001000: mask[3:0] = 4'b0100;
+			15'b010000001001100: mask[3:0] = 4'b0100;
+			15'b010000001010000: mask[3:0] = 4'b0100;
+			15'b010000001010100: mask[3:0] = 4'b0100;
+			15'b010000001011000: mask[3:0] = 4'b0100;
+			15'b010000001011100: mask[3:0] = 4'b0100;
+			15'b010000001100000: mask[3:0] = 4'b0100;
+			15'b010000001100100: mask[3:0] = 4'b0100;
+			15'b010000001101000: mask[3:0] = 4'b0100;
+			15'b010000001101100: mask[3:0] = 4'b0100;
+			15'b010000001110000: mask[3:0] = 4'b0100;
+			15'b010000001110100: mask[3:0] = 4'b0100;
+			15'b010000001111000: mask[3:0] = 4'b0100;
+			15'b010000001111100: mask[3:0] = 4'b0100;
+			15'b000000000000100: mask[3:0] = 4'b0010;
+			15'b000000000001000: mask[3:0] = 4'b0010;
+			15'b000000000001100: mask[3:0] = 4'b0010;
+			15'b000000000010000: mask[3:0] = 4'b0010;
+			15'b000000000010100: mask[3:0] = 4'b0010;
+			15'b000000000011000: mask[3:0] = 4'b0010;
+			15'b000000000011100: mask[3:0] = 4'b0010;
+			15'b000000000100000: mask[3:0] = 4'b0010;
+			15'b000000000100100: mask[3:0] = 4'b0010;
+			15'b000000000101000: mask[3:0] = 4'b0010;
+			15'b000000000101100: mask[3:0] = 4'b0010;
+			15'b000000000110000: mask[3:0] = 4'b0010;
+			15'b000000000110100: mask[3:0] = 4'b0010;
+			15'b000000000111000: mask[3:0] = 4'b0010;
+			15'b000000000111100: mask[3:0] = 4'b0010;
+			15'b000000001000000: mask[3:0] = 4'b0010;
+			15'b000000001000100: mask[3:0] = 4'b0010;
+			15'b000000001001000: mask[3:0] = 4'b0010;
+			15'b000000001001100: mask[3:0] = 4'b0010;
+			15'b000000001010000: mask[3:0] = 4'b0010;
+			15'b000000001010100: mask[3:0] = 4'b0010;
+			15'b000000001011000: mask[3:0] = 4'b0010;
+			15'b000000001011100: mask[3:0] = 4'b0010;
+			15'b000000001100000: mask[3:0] = 4'b0010;
+			15'b000000001100100: mask[3:0] = 4'b0010;
+			15'b000000001101000: mask[3:0] = 4'b0010;
+			15'b000000001101100: mask[3:0] = 4'b0010;
+			15'b000000001110000: mask[3:0] = 4'b0010;
+			15'b000000001110100: mask[3:0] = 4'b0010;
+			15'b000000001111000: mask[3:0] = 4'b0010;
+			15'b000000001111100: mask[3:0] = 4'b0010;
+			default: mask[3:0] = 4'b0001;
+		endcase
+endmodule
+module eb1_cmp_and_mux (
+	a_id,
+	a_priority,
+	b_id,
+	b_priority,
+	out_id,
+	out_priority
+);
+	parameter ID_BITS = 8;
+	parameter INTPRIORITY_BITS = 4;
+	input wire [ID_BITS - 1:0] a_id;
+	input wire [INTPRIORITY_BITS - 1:0] a_priority;
+	input wire [ID_BITS - 1:0] b_id;
+	input wire [INTPRIORITY_BITS - 1:0] b_priority;
+	output wire [ID_BITS - 1:0] out_id;
+	output wire [INTPRIORITY_BITS - 1:0] out_priority;
+	wire a_is_lt_b;
+	assign a_is_lt_b = a_priority[INTPRIORITY_BITS - 1:0] < b_priority[INTPRIORITY_BITS - 1:0];
+	assign out_id[ID_BITS - 1:0] = (a_is_lt_b ? b_id[ID_BITS - 1:0] : a_id[ID_BITS - 1:0]);
+	assign out_priority[INTPRIORITY_BITS - 1:0] = (a_is_lt_b ? b_priority[INTPRIORITY_BITS - 1:0] : a_priority[INTPRIORITY_BITS - 1:0]);
+endmodule
+module eb1_configurable_gw (
+	gw_clk,
+	rawclk,
+	clken,
+	rst_l,
+	extintsrc_req_sync,
+	meigwctrl_polarity,
+	meigwctrl_type,
+	meigwclr,
+	extintsrc_req_config
+);
+	input wire gw_clk;
+	input wire rawclk;
+	input wire clken;
+	input wire rst_l;
+	input wire extintsrc_req_sync;
+	input wire meigwctrl_polarity;
+	input wire meigwctrl_type;
+	input wire meigwclr;
+	output wire extintsrc_req_config;
+	wire gw_int_pending_in;
+	wire gw_int_pending;
+	assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr);
+	rvdff_fpga #(.WIDTH(1)) int_pend_ff(
+		.rst_l(rst_l),
+		.clk(gw_clk),
+		.rawclk(rawclk),
+		.clken(clken),
+		.din(gw_int_pending_in),
+		.dout(gw_int_pending)
+	);
+	assign extintsrc_req_config = (meigwctrl_type ? (extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending : extintsrc_req_sync ^ meigwctrl_polarity);
+endmodule
+module ahb_to_axi4 (
+	clk,
+	rst_l,
+	scan_mode,
+	bus_clk_en,
+	clk_override,
+	axi_awvalid,
+	axi_awready,
+	axi_awid,
+	axi_awaddr,
+	axi_awsize,
+	axi_awprot,
+	axi_awlen,
+	axi_awburst,
+	axi_wvalid,
+	axi_wready,
+	axi_wdata,
+	axi_wstrb,
+	axi_wlast,
+	axi_bvalid,
+	axi_bready,
+	axi_bresp,
+	axi_bid,
+	axi_arvalid,
+	axi_arready,
+	axi_arid,
+	axi_araddr,
+	axi_arsize,
+	axi_arprot,
+	axi_arlen,
+	axi_arburst,
+	axi_rvalid,
+	axi_rready,
+	axi_rid,
+	axi_rdata,
+	axi_rresp,
+	ahb_haddr,
+	ahb_hburst,
+	ahb_hmastlock,
+	ahb_hprot,
+	ahb_hsize,
+	ahb_htrans,
+	ahb_hwrite,
+	ahb_hwdata,
+	ahb_hsel,
+	ahb_hreadyin,
+	ahb_hrdata,
+	ahb_hreadyout,
+	ahb_hresp
+);
+	parameter TAG = 1;
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input clk;
+	input rst_l;
+	input scan_mode;
+	input bus_clk_en;
+	input clk_override;
+	output wire axi_awvalid;
+	input wire axi_awready;
+	output wire [TAG - 1:0] axi_awid;
+	output wire [31:0] axi_awaddr;
+	output wire [2:0] axi_awsize;
+	output wire [2:0] axi_awprot;
+	output wire [7:0] axi_awlen;
+	output wire [1:0] axi_awburst;
+	output wire axi_wvalid;
+	input wire axi_wready;
+	output wire [63:0] axi_wdata;
+	output wire [7:0] axi_wstrb;
+	output wire axi_wlast;
+	input wire axi_bvalid;
+	output wire axi_bready;
+	input wire [1:0] axi_bresp;
+	input wire [TAG - 1:0] axi_bid;
+	output wire axi_arvalid;
+	input wire axi_arready;
+	output wire [TAG - 1:0] axi_arid;
+	output wire [31:0] axi_araddr;
+	output wire [2:0] axi_arsize;
+	output wire [2:0] axi_arprot;
+	output wire [7:0] axi_arlen;
+	output wire [1:0] axi_arburst;
+	input wire axi_rvalid;
+	output wire axi_rready;
+	input wire [TAG - 1:0] axi_rid;
+	input wire [63:0] axi_rdata;
+	input wire [1:0] axi_rresp;
+	input wire [31:0] ahb_haddr;
+	input wire [2:0] ahb_hburst;
+	input wire ahb_hmastlock;
+	input wire [3:0] ahb_hprot;
+	input wire [2:0] ahb_hsize;
+	input wire [1:0] ahb_htrans;
+	input wire ahb_hwrite;
+	input wire [63:0] ahb_hwdata;
+	input wire ahb_hsel;
+	input wire ahb_hreadyin;
+	output wire [63:0] ahb_hrdata;
+	output wire ahb_hreadyout;
+	output wire ahb_hresp;
+	wire [7:0] master_wstrb;
+	wire [1:0] buf_state;
+	reg [1:0] buf_nxtstate;
+	reg buf_state_en;
+	reg buf_read_error_in;
+	wire buf_read_error;
+	wire [63:0] buf_rdata;
+	wire ahb_hready;
+	wire ahb_hready_q;
+	wire [1:0] ahb_htrans_in;
+	wire [1:0] ahb_htrans_q;
+	wire [2:0] ahb_hsize_q;
+	wire ahb_hwrite_q;
+	wire [31:0] ahb_haddr_q;
+	wire [63:0] ahb_hwdata_q;
+	wire ahb_hresp_q;
+	wire ahb_addr_in_dccm;
+	wire ahb_addr_in_iccm;
+	wire ahb_addr_in_pic;
+	wire ahb_addr_in_dccm_region_nc;
+	wire ahb_addr_in_iccm_region_nc;
+	wire ahb_addr_in_pic_region_nc;
+	reg buf_rdata_en;
+	wire ahb_addr_clk_en;
+	wire buf_rdata_clk_en;
+	wire bus_clk;
+	wire ahb_addr_clk;
+	wire buf_rdata_clk;
+	reg cmdbuf_wr_en;
+	wire cmdbuf_rst;
+	wire cmdbuf_full;
+	wire cmdbuf_vld;
+	wire cmdbuf_write;
+	wire [1:0] cmdbuf_size;
+	wire [7:0] cmdbuf_wstrb;
+	wire [31:0] cmdbuf_addr;
+	wire [63:0] cmdbuf_wdata;
+	localparam [1:0] IDLE = 2'b00;
+	localparam [1:0] PEND = 2'b11;
+	localparam [1:0] RD = 2'b10;
+	localparam [1:0] WR = 2'b01;
+	always @(*) begin
+		buf_nxtstate = IDLE;
+		buf_state_en = 1'b0;
+		buf_rdata_en = 1'b0;
+		buf_read_error_in = 1'b0;
+		cmdbuf_wr_en = 1'b0;
+		case (buf_state)
+			IDLE: begin
+				buf_nxtstate = (ahb_hwrite ? WR : RD);
+				buf_state_en = (ahb_hready & ahb_htrans[1]) & ahb_hsel;
+			end
+			WR: begin
+				buf_nxtstate = ((ahb_hresp | (ahb_htrans[1:0] == 2'b00)) | ~ahb_hsel ? IDLE : (ahb_hwrite ? WR : RD));
+				buf_state_en = ~cmdbuf_full | ahb_hresp;
+				cmdbuf_wr_en = ~cmdbuf_full & ~(ahb_hresp | ((ahb_htrans[1:0] == 2'b01) & ahb_hsel));
+			end
+			RD: begin
+				buf_nxtstate = (ahb_hresp ? IDLE : PEND);
+				buf_state_en = ~cmdbuf_full | ahb_hresp;
+				cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full;
+			end
+			PEND: begin
+				buf_nxtstate = IDLE;
+				buf_state_en = axi_rvalid & ~cmdbuf_write;
+				buf_rdata_en = buf_state_en;
+				buf_read_error_in = buf_state_en & |axi_rresp[1:0];
+			end
+		endcase
+	end
+	rvdffs_fpga #(.WIDTH(2)) state_reg(
+		.rst_l(rst_l),
+		.din(buf_nxtstate),
+		.dout({buf_state}),
+		.en(buf_state_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk)
+	);
+	assign master_wstrb[7:0] = ((({8 {ahb_hsize_q[2:0] == 3'b000}} & (8'b00000001 << ahb_haddr_q[2:0])) | ({8 {ahb_hsize_q[2:0] == 3'b001}} & (8'b00000011 << ahb_haddr_q[2:0]))) | ({8 {ahb_hsize_q[2:0] == 3'b010}} & (8'b00001111 << ahb_haddr_q[2:0]))) | ({8 {ahb_hsize_q[2:0] == 3'b011}} & 8'b11111111);
+	assign ahb_hreadyout = (ahb_hresp ? ahb_hresp_q & ~ahb_hready_q : ((~cmdbuf_full | (buf_state == IDLE)) & ~((buf_state == RD) | (buf_state == PEND))) & ~buf_read_error);
+	assign ahb_hready = ahb_hreadyout & ahb_hreadyin;
+	assign ahb_htrans_in[1:0] = {2 {ahb_hsel}} & ahb_htrans[1:0];
+	assign ahb_hrdata[63:0] = buf_rdata[63:0];
+	assign ahb_hresp = ((((ahb_htrans_q[1:0] != 2'b00) & (buf_state != IDLE)) & ((((~(ahb_addr_in_dccm | ahb_addr_in_iccm) | ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11)))) | ((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0])) | ((ahb_hsize_q[2:0] == 3'h2) & |ahb_haddr_q[1:0])) | ((ahb_hsize_q[2:0] == 3'h3) & |ahb_haddr_q[2:0]))) | buf_read_error) | (ahb_hresp_q & ~ahb_hready_q);
+	rvdff_fpga #(.WIDTH(64)) buf_rdata_ff(
+		.din(axi_rdata[63:0]),
+		.dout(buf_rdata[63:0]),
+		.clk(buf_rdata_clk),
+		.clken(buf_rdata_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) buf_read_error_ff(
+		.din(buf_read_error_in),
+		.dout(buf_read_error),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hresp_ff(
+		.din(ahb_hresp),
+		.dout(ahb_hresp_q),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hready_ff(
+		.din(ahb_hready),
+		.dout(ahb_hready_q),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(2)) htrans_ff(
+		.din(ahb_htrans_in[1:0]),
+		.dout(ahb_htrans_q[1:0]),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(3)) hsize_ff(
+		.din(ahb_hsize[2:0]),
+		.dout(ahb_hsize_q[2:0]),
+		.clk(ahb_addr_clk),
+		.clken(ahb_addr_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hwrite_ff(
+		.din(ahb_hwrite),
+		.dout(ahb_hwrite_q),
+		.clk(ahb_addr_clk),
+		.clken(ahb_addr_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(32)) haddr_ff(
+		.din(ahb_haddr[31:0]),
+		.dout(ahb_haddr_q[31:0]),
+		.clk(ahb_addr_clk),
+		.clken(ahb_addr_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvrangecheck #(
+		.CCM_SADR(pt[1325-:36]),
+		.CCM_SIZE(pt[1289-:14])
+	) addr_dccm_rangecheck(
+		.addr(ahb_haddr_q[31:0]),
+		.in_range(ahb_addr_in_dccm),
+		.in_region(ahb_addr_in_dccm_region_nc)
+	);
+	generate
+		if (pt[927-:5] == 1) begin : GenICCM
+			rvrangecheck #(
+				.CCM_SADR(pt[887-:36]),
+				.CCM_SIZE(pt[851-:14])
+			) addr_iccm_rangecheck(
+				.addr(ahb_haddr_q[31:0]),
+				.in_range(ahb_addr_in_iccm),
+				.in_region(ahb_addr_in_iccm_region_nc)
+			);
+		end
+		else begin : GenNoICCM
+			assign ahb_addr_in_iccm = 1'b0;
+			assign ahb_addr_in_iccm_region_nc = 1'b0;
+		end
+	endgenerate
+	rvrangecheck #(
+		.CCM_SADR(pt[130-:36]),
+		.CCM_SIZE(pt[69-:13])
+	) addr_pic_rangecheck(
+		.addr(ahb_haddr_q[31:0]),
+		.in_range(ahb_addr_in_pic),
+		.in_region(ahb_addr_in_pic_region_nc)
+	);
+	assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write);
+	assign cmdbuf_full = cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready));
+	rvdffsc_fpga #(.WIDTH(1)) cmdbuf_vldff(
+		.din(1'b1),
+		.dout(cmdbuf_vld),
+		.en(cmdbuf_wr_en),
+		.clear(cmdbuf_rst),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) cmdbuf_writeff(
+		.din(ahb_hwrite_q),
+		.dout(cmdbuf_write),
+		.en(cmdbuf_wr_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(2)) cmdbuf_sizeff(
+		.din(ahb_hsize_q[1:0]),
+		.dout(cmdbuf_size[1:0]),
+		.en(cmdbuf_wr_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(8)) cmdbuf_wstrbff(
+		.din(master_wstrb[7:0]),
+		.dout(cmdbuf_wstrb[7:0]),
+		.en(cmdbuf_wr_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) cmdbuf_addrff(
+		.din(ahb_haddr_q[31:0]),
+		.dout(cmdbuf_addr[31:0]),
+		.en(cmdbuf_wr_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffe #(.WIDTH(64)) cmdbuf_wdataff(
+		.din(ahb_hwdata[63:0]),
+		.dout(cmdbuf_wdata[63:0]),
+		.en(cmdbuf_wr_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	assign axi_awvalid = cmdbuf_vld & cmdbuf_write;
+	assign axi_awid[TAG - 1:0] = {TAG {1'sb0}};
+	assign axi_awaddr[31:0] = cmdbuf_addr[31:0];
+	assign axi_awsize[2:0] = {1'b0, cmdbuf_size[1:0]};
+	assign axi_awprot[2:0] = 3'b000;
+	assign axi_awlen[7:0] = {8 {1'sb0}};
+	assign axi_awburst[1:0] = 2'b01;
+	assign axi_wvalid = cmdbuf_vld & cmdbuf_write;
+	assign axi_wdata[63:0] = cmdbuf_wdata[63:0];
+	assign axi_wstrb[7:0] = cmdbuf_wstrb[7:0];
+	assign axi_wlast = 1'b1;
+	assign axi_bready = 1'b1;
+	assign axi_arvalid = cmdbuf_vld & ~cmdbuf_write;
+	assign axi_arid[TAG - 1:0] = {TAG {1'sb0}};
+	assign axi_araddr[31:0] = cmdbuf_addr[31:0];
+	assign axi_arsize[2:0] = {1'b0, cmdbuf_size[1:0]};
+	assign axi_arprot = 3'b000;
+	assign axi_arlen[7:0] = {8 {1'sb0}};
+	assign axi_arburst[1:0] = 2'b01;
+	assign axi_rready = 1'b1;
+	assign ahb_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);
+	assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;
+	rvclkhdr bus_cgc(
+		.en(bus_clk_en),
+		.l1clk(bus_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr ahb_addr_cgc(
+		.en(ahb_addr_clk_en),
+		.l1clk(ahb_addr_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr buf_rdata_cgc(
+		.en(buf_rdata_clk_en),
+		.l1clk(buf_rdata_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+endmodule
+module dmi_jtag_to_core_sync (
+	rd_en,
+	wr_en,
+	rst_n,
+	clk,
+	reg_en,
+	reg_wr_en
+);
+	input rd_en;
+	input wr_en;
+	input rst_n;
+	input clk;
+	output reg_en;
+	output reg_wr_en;
+	wire c_rd_en;
+	wire c_wr_en;
+	reg [2:0] rden;
+	reg [2:0] wren;
+	assign reg_en = c_wr_en | c_rd_en;
+	assign reg_wr_en = c_wr_en;
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			rden <= {3 {1'sb0}};
+			wren <= {3 {1'sb0}};
+		end
+		else begin
+			rden <= {rden[1:0], rd_en};
+			wren <= {wren[1:0], wr_en};
+		end
+	assign c_rd_en = rden[1] & ~rden[2];
+	assign c_wr_en = wren[1] & ~wren[2];
+endmodule
+module axi4_to_ahb (
+	clk,
+	free_clk,
+	rst_l,
+	scan_mode,
+	bus_clk_en,
+	clk_override,
+	dec_tlu_force_halt,
+	axi_awvalid,
+	axi_awready,
+	axi_awid,
+	axi_awaddr,
+	axi_awsize,
+	axi_awprot,
+	axi_wvalid,
+	axi_wready,
+	axi_wdata,
+	axi_wstrb,
+	axi_wlast,
+	axi_bvalid,
+	axi_bready,
+	axi_bresp,
+	axi_bid,
+	axi_arvalid,
+	axi_arready,
+	axi_arid,
+	axi_araddr,
+	axi_arsize,
+	axi_arprot,
+	axi_rvalid,
+	axi_rready,
+	axi_rid,
+	axi_rdata,
+	axi_rresp,
+	axi_rlast,
+	ahb_haddr,
+	ahb_hburst,
+	ahb_hmastlock,
+	ahb_hprot,
+	ahb_hsize,
+	ahb_htrans,
+	ahb_hwrite,
+	ahb_hwdata,
+	ahb_hrdata,
+	ahb_hready,
+	ahb_hresp
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	parameter TAG = 1;
+	input clk;
+	input free_clk;
+	input rst_l;
+	input scan_mode;
+	input bus_clk_en;
+	input clk_override;
+	input dec_tlu_force_halt;
+	input wire axi_awvalid;
+	output wire axi_awready;
+	input wire [TAG - 1:0] axi_awid;
+	input wire [31:0] axi_awaddr;
+	input wire [2:0] axi_awsize;
+	input wire [2:0] axi_awprot;
+	input wire axi_wvalid;
+	output wire axi_wready;
+	input wire [63:0] axi_wdata;
+	input wire [7:0] axi_wstrb;
+	input wire axi_wlast;
+	output wire axi_bvalid;
+	input wire axi_bready;
+	output wire [1:0] axi_bresp;
+	output wire [TAG - 1:0] axi_bid;
+	input wire axi_arvalid;
+	output wire axi_arready;
+	input wire [TAG - 1:0] axi_arid;
+	input wire [31:0] axi_araddr;
+	input wire [2:0] axi_arsize;
+	input wire [2:0] axi_arprot;
+	output wire axi_rvalid;
+	input wire axi_rready;
+	output wire [TAG - 1:0] axi_rid;
+	output wire [63:0] axi_rdata;
+	output wire [1:0] axi_rresp;
+	output wire axi_rlast;
+	output wire [31:0] ahb_haddr;
+	output wire [2:0] ahb_hburst;
+	output wire ahb_hmastlock;
+	output wire [3:0] ahb_hprot;
+	output wire [2:0] ahb_hsize;
+	output reg [1:0] ahb_htrans;
+	output wire ahb_hwrite;
+	output wire [63:0] ahb_hwdata;
+	input wire [63:0] ahb_hrdata;
+	input wire ahb_hready;
+	input wire ahb_hresp;
+	localparam ID = 1;
+	localparam PRTY = 1;
+	wire [2:0] buf_state;
+	reg [2:0] buf_nxtstate;
+	wire slave_valid;
+	wire slave_ready;
+	wire [TAG - 1:0] slave_tag;
+	wire [63:0] slave_rdata;
+	wire [3:0] slave_opc;
+	wire wrbuf_en;
+	wire wrbuf_data_en;
+	wire wrbuf_cmd_sent;
+	wire wrbuf_rst;
+	wire wrbuf_vld;
+	wire wrbuf_data_vld;
+	wire [TAG - 1:0] wrbuf_tag;
+	wire [2:0] wrbuf_size;
+	wire [31:0] wrbuf_addr;
+	wire [63:0] wrbuf_data;
+	wire [7:0] wrbuf_byteen;
+	wire master_valid;
+	reg master_ready;
+	wire [TAG - 1:0] master_tag;
+	wire [31:0] master_addr;
+	wire [63:0] master_wdata;
+	wire [2:0] master_size;
+	wire [2:0] master_opc;
+	wire [7:0] master_byteen;
+	wire [31:0] buf_addr;
+	wire [1:0] buf_size;
+	wire buf_write;
+	wire [7:0] buf_byteen;
+	wire buf_aligned;
+	wire [63:0] buf_data;
+	wire [TAG - 1:0] buf_tag;
+	wire buf_rst;
+	wire [TAG - 1:0] buf_tag_in;
+	wire [31:0] buf_addr_in;
+	wire [7:0] buf_byteen_in;
+	wire [63:0] buf_data_in;
+	reg buf_write_in;
+	wire buf_aligned_in;
+	wire [2:0] buf_size_in;
+	reg buf_state_en;
+	reg buf_wr_en;
+	reg buf_data_wr_en;
+	reg slvbuf_error_en;
+	wire wr_cmd_vld;
+	wire cmd_done_rst;
+	reg cmd_done;
+	wire cmd_doneQ;
+	reg trxn_done;
+	reg [2:0] buf_cmd_byte_ptr;
+	wire [2:0] buf_cmd_byte_ptrQ;
+	wire [2:0] buf_cmd_nxtbyte_ptr;
+	reg buf_cmd_byte_ptr_en;
+	wire found;
+	reg slave_valid_pre;
+	wire ahb_hready_q;
+	wire ahb_hresp_q;
+	wire [1:0] ahb_htrans_q;
+	wire ahb_hwrite_q;
+	wire [63:0] ahb_hrdata_q;
+	wire slvbuf_write;
+	wire slvbuf_error;
+	wire [TAG - 1:0] slvbuf_tag;
+	reg slvbuf_error_in;
+	reg slvbuf_wr_en;
+	reg bypass_en;
+	reg rd_bypass_idle;
+	wire last_addr_en;
+	wire [31:0] last_bus_addr;
+	wire buf_clken;
+	wire ahbm_data_clken;
+	wire buf_clk;
+	wire bus_clk;
+	wire ahbm_data_clk;
+	wire dec_tlu_force_halt_bus;
+	wire dec_tlu_force_halt_bus_ns;
+	wire dec_tlu_force_halt_bus_q;
+	function automatic [1:0] get_write_size;
+		input reg [7:0] byteen;
+		reg [1:0] size;
+		begin
+			size[1:0] = ((2'b11 & {2 {byteen[7:0] == 8'hff}}) | (2'b10 & {2 {(byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h0f)}})) | (2'b01 & {2 {(((byteen[7:0] == 8'hc0) | (byteen[7:0] == 8'h30)) | (byteen[7:0] == 8'h0c)) | (byteen[7:0] == 8'h03)}});
+			get_write_size = size[1:0];
+		end
+	endfunction
+	function automatic [2:0] get_write_addr;
+		input reg [7:0] byteen;
+		reg [2:0] addr;
+		begin
+			addr[2:0] = (((3'h0 & {3 {((byteen[7:0] == 8'hff) | (byteen[7:0] == 8'h0f)) | (byteen[7:0] == 8'h03)}}) | (3'h2 & {3 {byteen[7:0] == 8'h0c}})) | (3'h4 & {3 {(byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h03)}})) | (3'h6 & {3 {byteen[7:0] == 8'hc0}});
+			get_write_addr = addr[2:0];
+		end
+	endfunction
+	function automatic signed [2:0] sv2v_cast_3_signed;
+		input reg signed [2:0] inp;
+		sv2v_cast_3_signed = inp;
+	endfunction
+	function automatic [2:0] get_nxtbyte_ptr;
+		input reg [2:0] current_byte_ptr;
+		input reg [7:0] byteen;
+		input reg get_next;
+		reg [2:0] start_ptr;
+		reg found;
+		begin
+			found = 1'b0;
+			start_ptr[2:0] = (get_next ? current_byte_ptr[2:0] + 3'b001 : current_byte_ptr[2:0]);
+			begin : sv2v_autoblock_36
+				reg signed [31:0] j;
+				for (j = 0; j < 8; j = j + 1)
+					if (~found) begin
+						get_nxtbyte_ptr[2:0] = sv2v_cast_3_signed(j);
+						found = found | (byteen[j] & (sv2v_cast_3_signed(j) >= start_ptr[2:0]));
+					end
+			end
+		end
+	endfunction
+	assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;
+	assign dec_tlu_force_halt_bus_ns = ~bus_clk_en & dec_tlu_force_halt_bus;
+	rvdff #(.WIDTH(1)) force_halt_busff(
+		.din(dec_tlu_force_halt_bus_ns),
+		.dout(dec_tlu_force_halt_bus_q),
+		.clk(free_clk),
+		.rst_l(rst_l)
+	);
+	assign wrbuf_en = (axi_awvalid & axi_awready) & master_ready;
+	assign wrbuf_data_en = (axi_wvalid & axi_wready) & master_ready;
+	assign wrbuf_cmd_sent = (master_valid & master_ready) & (master_opc[2:1] == 2'b01);
+	assign wrbuf_rst = (wrbuf_cmd_sent & ~wrbuf_en) | dec_tlu_force_halt_bus;
+	assign axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent) & master_ready;
+	assign axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent) & master_ready;
+	assign axi_arready = ~(wrbuf_vld & wrbuf_data_vld) & master_ready;
+	assign axi_rlast = 1'b1;
+	assign wr_cmd_vld = wrbuf_vld & wrbuf_data_vld;
+	assign master_valid = wr_cmd_vld | axi_arvalid;
+	assign master_tag[TAG - 1:0] = (wr_cmd_vld ? wrbuf_tag[TAG - 1:0] : axi_arid[TAG - 1:0]);
+	assign master_opc[2:0] = (wr_cmd_vld ? 3'b011 : 3'b000);
+	assign master_addr[31:0] = (wr_cmd_vld ? wrbuf_addr[31:0] : axi_araddr[31:0]);
+	assign master_size[2:0] = (wr_cmd_vld ? wrbuf_size[2:0] : axi_arsize[2:0]);
+	assign master_byteen[7:0] = wrbuf_byteen[7:0];
+	assign master_wdata[63:0] = wrbuf_data[63:0];
+	assign axi_bvalid = (slave_valid & slave_ready) & slave_opc[3];
+	assign axi_bresp[1:0] = (slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b00));
+	assign axi_bid[TAG - 1:0] = slave_tag[TAG - 1:0];
+	assign axi_rvalid = (slave_valid & slave_ready) & (slave_opc[3:2] == 2'b00);
+	assign axi_rresp[1:0] = (slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b00));
+	assign axi_rid[TAG - 1:0] = slave_tag[TAG - 1:0];
+	assign axi_rdata[63:0] = slave_rdata[63:0];
+	assign slave_ready = axi_bready & axi_rready;
+	localparam [2:0] CMD_RD = 3'b001;
+	localparam [2:0] CMD_WR = 3'b010;
+	localparam [2:0] DATA_RD = 3'b011;
+	localparam [2:0] DATA_WR = 3'b100;
+	localparam [2:0] DONE = 3'b101;
+	localparam [2:0] IDLE = 3'b000;
+	localparam [2:0] STREAM_ERR_RD = 3'b111;
+	localparam [2:0] STREAM_RD = 3'b110;
+	always @(*) begin
+		buf_nxtstate = IDLE;
+		buf_state_en = 1'b0;
+		buf_wr_en = 1'b0;
+		buf_data_wr_en = 1'b0;
+		slvbuf_error_in = 1'b0;
+		slvbuf_error_en = 1'b0;
+		buf_write_in = 1'b0;
+		cmd_done = 1'b0;
+		trxn_done = 1'b0;
+		buf_cmd_byte_ptr_en = 1'b0;
+		buf_cmd_byte_ptr[2:0] = {3 {1'sb0}};
+		slave_valid_pre = 1'b0;
+		master_ready = 1'b0;
+		ahb_htrans[1:0] = 2'b00;
+		slvbuf_wr_en = 1'b0;
+		bypass_en = 1'b0;
+		rd_bypass_idle = 1'b0;
+		case (buf_state)
+			IDLE: begin
+				master_ready = 1'b1;
+				buf_write_in = master_opc[2:1] == 2'b01;
+				buf_nxtstate = (buf_write_in ? CMD_WR : CMD_RD);
+				buf_state_en = master_valid & master_ready;
+				buf_wr_en = buf_state_en;
+				buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
+				buf_cmd_byte_ptr_en = buf_state_en;
+				buf_cmd_byte_ptr[2:0] = (buf_write_in ? get_nxtbyte_ptr(3'b000, buf_byteen_in[7:0], 1'b0) : master_addr[2:0]);
+				bypass_en = buf_state_en;
+				rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD);
+				ahb_htrans[1:0] = {2 {bypass_en}} & 2'b10;
+			end
+			CMD_RD: begin
+				buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000) ? STREAM_RD : DATA_RD);
+				buf_state_en = (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b00)) & ~ahb_hwrite_q;
+				cmd_done = buf_state_en & ~master_valid;
+				slvbuf_wr_en = buf_state_en;
+				master_ready = buf_state_en & (buf_nxtstate == STREAM_RD);
+				buf_wr_en = master_ready;
+				bypass_en = master_ready & master_valid;
+				buf_cmd_byte_ptr[2:0] = (bypass_en ? master_addr[2:0] : buf_addr[2:0]);
+				ahb_htrans[1:0] = 2'b10 & {2 {~buf_state_en | bypass_en}};
+			end
+			STREAM_RD: begin
+				master_ready = (ahb_hready_q & ~ahb_hresp_q) & ~(master_valid & (master_opc[2:1] == 2'b01));
+				buf_wr_en = (master_valid & master_ready) & (master_opc[2:0] == 3'b000);
+				buf_nxtstate = (ahb_hresp_q ? STREAM_ERR_RD : (buf_wr_en ? STREAM_RD : DATA_RD));
+				buf_state_en = ahb_hready_q | ahb_hresp_q;
+				buf_data_wr_en = buf_state_en;
+				slvbuf_error_in = ahb_hresp_q;
+				slvbuf_error_en = buf_state_en;
+				slave_valid_pre = buf_state_en & ~ahb_hresp_q;
+				cmd_done = buf_state_en & ~master_valid;
+				bypass_en = ((master_ready & master_valid) & (buf_nxtstate == STREAM_RD)) & buf_state_en;
+				buf_cmd_byte_ptr[2:0] = (bypass_en ? master_addr[2:0] : buf_addr[2:0]);
+				ahb_htrans[1:0] = 2'b10 & {2 {~((buf_nxtstate != STREAM_RD) & buf_state_en)}};
+				slvbuf_wr_en = buf_wr_en;
+			end
+			STREAM_ERR_RD: begin
+				buf_nxtstate = DATA_RD;
+				buf_state_en = (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b00)) & ~ahb_hwrite_q;
+				slave_valid_pre = buf_state_en;
+				slvbuf_wr_en = buf_state_en;
+				buf_cmd_byte_ptr[2:0] = buf_addr[2:0];
+				ahb_htrans[1:0] = 2'b10 & {2 {~buf_state_en}};
+			end
+			DATA_RD: begin
+				buf_nxtstate = DONE;
+				buf_state_en = ahb_hready_q | ahb_hresp_q;
+				buf_data_wr_en = buf_state_en;
+				slvbuf_error_in = ahb_hresp_q;
+				slvbuf_error_en = buf_state_en;
+				slvbuf_wr_en = buf_state_en;
+			end
+			CMD_WR: begin
+				buf_nxtstate = DATA_WR;
+				trxn_done = (ahb_hready_q & ahb_hwrite_q) & (ahb_htrans_q[1:0] != 2'b00);
+				buf_state_en = trxn_done;
+				buf_cmd_byte_ptr_en = buf_state_en;
+				slvbuf_wr_en = buf_state_en;
+				buf_cmd_byte_ptr = (trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1) : buf_cmd_byte_ptrQ);
+				cmd_done = trxn_done & ((buf_aligned | (buf_cmd_byte_ptrQ == 3'b111)) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1)] == 1'b0));
+				ahb_htrans[1:0] = {2 {~(cmd_done | cmd_doneQ)}} & 2'b10;
+			end
+			DATA_WR: begin
+				buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q;
+				master_ready = (buf_state_en & ~ahb_hresp_q) & slave_ready;
+				buf_nxtstate = (ahb_hresp_q | ~slave_ready ? DONE : (master_valid & master_ready ? (master_opc[2:1] == 2'b01 ? CMD_WR : CMD_RD) : IDLE));
+				slvbuf_error_in = ahb_hresp_q;
+				slvbuf_error_en = buf_state_en;
+				buf_write_in = master_opc[2:1] == 2'b01;
+				buf_wr_en = buf_state_en & ((buf_nxtstate == CMD_WR) | (buf_nxtstate == CMD_RD));
+				buf_data_wr_en = buf_wr_en;
+				cmd_done = ahb_hresp_q | ((ahb_hready_q & (ahb_htrans_q[1:0] != 2'b00)) & ((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1)] == 1'b0)));
+				bypass_en = (buf_state_en & buf_write_in) & (buf_nxtstate == CMD_WR);
+				ahb_htrans[1:0] = {2 {~(cmd_done | cmd_doneQ) | bypass_en}} & 2'b10;
+				slave_valid_pre = buf_state_en & (buf_nxtstate != DONE);
+				trxn_done = (ahb_hready_q & ahb_hwrite_q) & (ahb_htrans_q[1:0] != 2'b00);
+				buf_cmd_byte_ptr_en = trxn_done | bypass_en;
+				buf_cmd_byte_ptr = (bypass_en ? get_nxtbyte_ptr(3'b000, buf_byteen_in[7:0], 1'b0) : (trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0], buf_byteen[7:0], 1'b1) : buf_cmd_byte_ptrQ));
+			end
+			DONE: begin
+				buf_nxtstate = IDLE;
+				buf_state_en = slave_ready;
+				slvbuf_error_en = 1'b1;
+				slave_valid_pre = 1'b1;
+			end
+		endcase
+	end
+	assign buf_rst = dec_tlu_force_halt_bus;
+	assign cmd_done_rst = slave_valid_pre;
+	assign buf_addr_in[31:3] = master_addr[31:3];
+	assign buf_addr_in[2:0] = (buf_aligned_in & (master_opc[2:1] == 2'b01) ? get_write_addr(master_byteen[7:0]) : master_addr[2:0]);
+	assign buf_tag_in[TAG - 1:0] = master_tag[TAG - 1:0];
+	assign buf_byteen_in[7:0] = wrbuf_byteen[7:0];
+	assign buf_data_in[63:0] = (buf_state == DATA_RD ? ahb_hrdata_q[63:0] : master_wdata[63:0]);
+	assign buf_size_in[1:0] = ((buf_aligned_in & (master_size[1:0] == 2'b11)) & (master_opc[2:1] == 2'b01) ? get_write_size(master_byteen[7:0]) : master_size[1:0]);
+	assign buf_aligned_in = ((((master_opc[2:0] == 3'b000) | (master_size[1:0] == 2'b00)) | (master_size[1:0] == 2'b01)) | (master_size[1:0] == 2'b10)) | ((master_size[1:0] == 2'b11) & (((((((master_byteen[7:0] == 8'h03) | (master_byteen[7:0] == 8'h0c)) | (master_byteen[7:0] == 8'h30)) | (master_byteen[7:0] == 8'hc0)) | (master_byteen[7:0] == 8'h0f)) | (master_byteen[7:0] == 8'hf0)) | (master_byteen[7:0] == 8'hff)));
+	assign ahb_haddr[31:3] = (bypass_en ? master_addr[31:3] : buf_addr[31:3]);
+	assign ahb_haddr[2:0] = {3 {ahb_htrans == 2'b10}} & buf_cmd_byte_ptr[2:0];
+	assign ahb_hsize[2:0] = (bypass_en ? {1'b0, {2 {buf_aligned_in}} & buf_size_in[1:0]} : {1'b0, {2 {buf_aligned}} & buf_size[1:0]});
+	assign ahb_hburst[2:0] = 3'b000;
+	assign ahb_hmastlock = 1'b0;
+	assign ahb_hprot[3:0] = {3'b001, ~axi_arprot[2]};
+	assign ahb_hwrite = (bypass_en ? master_opc[2:1] == 2'b01 : buf_write);
+	assign ahb_hwdata[63:0] = buf_data[63:0];
+	assign slave_valid = slave_valid_pre;
+	assign slave_opc[3:2] = (slvbuf_write ? 2'b11 : 2'b00);
+	assign slave_opc[1:0] = {2 {slvbuf_error}} & 2'b10;
+	assign slave_rdata[63:0] = (slvbuf_error ? {2 {last_bus_addr[31:0]}} : (buf_state == DONE ? buf_data[63:0] : ahb_hrdata_q[63:0]));
+	assign slave_tag[TAG - 1:0] = slvbuf_tag[TAG - 1:0];
+	assign last_addr_en = ((ahb_htrans[1:0] != 2'b00) & ahb_hready) & ahb_hwrite;
+	rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff(
+		.din(1'b1),
+		.dout(wrbuf_vld),
+		.en(wrbuf_en),
+		.clear(wrbuf_rst),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff(
+		.din(1'b1),
+		.dout(wrbuf_data_vld),
+		.en(wrbuf_data_en),
+		.clear(wrbuf_rst),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(TAG)) wrbuf_tagff(
+		.din(axi_awid[TAG - 1:0]),
+		.dout(wrbuf_tag[TAG - 1:0]),
+		.en(wrbuf_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(3)) wrbuf_sizeff(
+		.din(axi_awsize[2:0]),
+		.dout(wrbuf_size[2:0]),
+		.en(wrbuf_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) wrbuf_addrff(
+		.din(axi_awaddr[31:0]),
+		.dout(wrbuf_addr[31:0]),
+		.en(wrbuf_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffe #(.WIDTH(64)) wrbuf_dataff(
+		.din(axi_wdata[63:0]),
+		.dout(wrbuf_data[63:0]),
+		.en(wrbuf_data_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff(
+		.din(axi_wstrb[7:0]),
+		.dout(wrbuf_byteen[7:0]),
+		.en(wrbuf_data_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(32)) last_bus_addrff(
+		.din(ahb_haddr[31:0]),
+		.dout(last_bus_addr[31:0]),
+		.en(last_addr_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffsc_fpga #(.WIDTH(3)) buf_state_ff(
+		.din(buf_nxtstate),
+		.dout({buf_state}),
+		.en(buf_state_en),
+		.clear(buf_rst),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) buf_writeff(
+		.din(buf_write_in),
+		.dout(buf_write),
+		.en(buf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(TAG)) buf_tagff(
+		.din(buf_tag_in[TAG - 1:0]),
+		.dout(buf_tag[TAG - 1:0]),
+		.en(buf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) buf_addrff(
+		.din(buf_addr_in[31:0]),
+		.dout(buf_addr[31:0]),
+		.en(buf_wr_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffs_fpga #(.WIDTH(2)) buf_sizeff(
+		.din(buf_size_in[1:0]),
+		.dout(buf_size[1:0]),
+		.en(buf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) buf_alignedff(
+		.din(buf_aligned_in),
+		.dout(buf_aligned),
+		.en(buf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(8)) buf_byteenff(
+		.din(buf_byteen_in[7:0]),
+		.dout(buf_byteen[7:0]),
+		.en(buf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(64)) buf_dataff(
+		.din(buf_data_in[63:0]),
+		.dout(buf_data[63:0]),
+		.en(buf_data_wr_en & bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffs_fpga #(.WIDTH(1)) slvbuf_writeff(
+		.din(buf_write),
+		.dout(slvbuf_write),
+		.en(slvbuf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(TAG)) slvbuf_tagff(
+		.din(buf_tag[TAG - 1:0]),
+		.dout(slvbuf_tag[TAG - 1:0]),
+		.en(slvbuf_wr_en),
+		.clk(buf_clk),
+		.clken(buf_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) slvbuf_errorff(
+		.din(slvbuf_error_in),
+		.dout(slvbuf_error),
+		.en(slvbuf_error_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff(
+		.din(1'b1),
+		.dout(cmd_doneQ),
+		.en(cmd_done),
+		.clear(cmd_done_rst),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(3)) buf_cmd_byte_ptrff(
+		.din(buf_cmd_byte_ptr[2:0]),
+		.dout(buf_cmd_byte_ptrQ[2:0]),
+		.en(buf_cmd_byte_ptr_en),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hready_ff(
+		.din(ahb_hready),
+		.dout(ahb_hready_q),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(2)) htrans_ff(
+		.din(ahb_htrans[1:0]),
+		.dout(ahb_htrans_q[1:0]),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hwrite_ff(
+		.din(ahb_hwrite),
+		.dout(ahb_hwrite_q),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) hresp_ff(
+		.din(ahb_hresp),
+		.dout(ahb_hresp_q),
+		.clk(bus_clk),
+		.clken(bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(64)) hrdata_ff(
+		.din(ahb_hrdata[63:0]),
+		.dout(ahb_hrdata_q[63:0]),
+		.clk(ahbm_data_clk),
+		.clken(ahbm_data_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	assign buf_clken = bus_clk_en & ((buf_wr_en | slvbuf_wr_en) | clk_override);
+	assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);
+	rvclkhdr bus_cgc(
+		.en(bus_clk_en),
+		.l1clk(bus_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr buf_cgc(
+		.en(buf_clken),
+		.l1clk(buf_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr ahbm_data_cgc(
+		.en(ahbm_data_clken),
+		.l1clk(ahbm_data_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+endmodule
+module eb1_dbg (
+	dbg_cmd_addr,
+	dbg_cmd_wrdata,
+	dbg_cmd_valid,
+	dbg_cmd_write,
+	dbg_cmd_type,
+	dbg_cmd_size,
+	dbg_core_rst_l,
+	core_dbg_rddata,
+	core_dbg_cmd_done,
+	core_dbg_cmd_fail,
+	dbg_dma_bubble,
+	dma_dbg_ready,
+	dbg_halt_req,
+	dbg_resume_req,
+	dec_tlu_debug_mode,
+	dec_tlu_dbg_halted,
+	dec_tlu_mpc_halted_only,
+	dec_tlu_resume_ack,
+	dmi_reg_en,
+	dmi_reg_addr,
+	dmi_reg_wr_en,
+	dmi_reg_wdata,
+	dmi_reg_rdata,
+	sb_axi_awvalid,
+	sb_axi_awready,
+	sb_axi_awid,
+	sb_axi_awaddr,
+	sb_axi_awregion,
+	sb_axi_awlen,
+	sb_axi_awsize,
+	sb_axi_awburst,
+	sb_axi_awlock,
+	sb_axi_awcache,
+	sb_axi_awprot,
+	sb_axi_awqos,
+	sb_axi_wvalid,
+	sb_axi_wready,
+	sb_axi_wdata,
+	sb_axi_wstrb,
+	sb_axi_wlast,
+	sb_axi_bvalid,
+	sb_axi_bready,
+	sb_axi_bresp,
+	sb_axi_arvalid,
+	sb_axi_arready,
+	sb_axi_arid,
+	sb_axi_araddr,
+	sb_axi_arregion,
+	sb_axi_arlen,
+	sb_axi_arsize,
+	sb_axi_arburst,
+	sb_axi_arlock,
+	sb_axi_arcache,
+	sb_axi_arprot,
+	sb_axi_arqos,
+	sb_axi_rvalid,
+	sb_axi_rready,
+	sb_axi_rdata,
+	sb_axi_rresp,
+	dbg_bus_clk_en,
+	clk,
+	rst_l,
+	dbg_rst_l,
+	clk_override,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	output wire [31:0] dbg_cmd_addr;
+	output wire [31:0] dbg_cmd_wrdata;
+	output wire dbg_cmd_valid;
+	output wire dbg_cmd_write;
+	output wire [1:0] dbg_cmd_type;
+	output wire [1:0] dbg_cmd_size;
+	output wire dbg_core_rst_l;
+	input wire [31:0] core_dbg_rddata;
+	input wire core_dbg_cmd_done;
+	input wire core_dbg_cmd_fail;
+	output wire dbg_dma_bubble;
+	input wire dma_dbg_ready;
+	output reg dbg_halt_req;
+	output reg dbg_resume_req;
+	input wire dec_tlu_debug_mode;
+	input wire dec_tlu_dbg_halted;
+	input wire dec_tlu_mpc_halted_only;
+	input wire dec_tlu_resume_ack;
+	input wire dmi_reg_en;
+	input wire [6:0] dmi_reg_addr;
+	input wire dmi_reg_wr_en;
+	input wire [31:0] dmi_reg_wdata;
+	output wire [31:0] dmi_reg_rdata;
+	output wire sb_axi_awvalid;
+	input wire sb_axi_awready;
+	output wire [pt[12-:8] - 1:0] sb_axi_awid;
+	output wire [31:0] sb_axi_awaddr;
+	output wire [3:0] sb_axi_awregion;
+	output wire [7:0] sb_axi_awlen;
+	output wire [2:0] sb_axi_awsize;
+	output wire [1:0] sb_axi_awburst;
+	output wire sb_axi_awlock;
+	output wire [3:0] sb_axi_awcache;
+	output wire [2:0] sb_axi_awprot;
+	output wire [3:0] sb_axi_awqos;
+	output wire sb_axi_wvalid;
+	input wire sb_axi_wready;
+	output wire [63:0] sb_axi_wdata;
+	output wire [7:0] sb_axi_wstrb;
+	output wire sb_axi_wlast;
+	input wire sb_axi_bvalid;
+	output wire sb_axi_bready;
+	input wire [1:0] sb_axi_bresp;
+	output wire sb_axi_arvalid;
+	input wire sb_axi_arready;
+	output wire [pt[12-:8] - 1:0] sb_axi_arid;
+	output wire [31:0] sb_axi_araddr;
+	output wire [3:0] sb_axi_arregion;
+	output wire [7:0] sb_axi_arlen;
+	output wire [2:0] sb_axi_arsize;
+	output wire [1:0] sb_axi_arburst;
+	output wire sb_axi_arlock;
+	output wire [3:0] sb_axi_arcache;
+	output wire [2:0] sb_axi_arprot;
+	output wire [3:0] sb_axi_arqos;
+	input wire sb_axi_rvalid;
+	output wire sb_axi_rready;
+	input wire [63:0] sb_axi_rdata;
+	input wire [1:0] sb_axi_rresp;
+	input wire dbg_bus_clk_en;
+	input wire clk;
+	input wire rst_l;
+	input wire dbg_rst_l;
+	input wire clk_override;
+	input wire scan_mode;
+	wire [3:0] dbg_state;
+	reg [3:0] dbg_nxtstate;
+	reg dbg_state_en;
+	wire [31:0] dmstatus_reg;
+	wire [31:0] dmcontrol_reg;
+	wire [31:0] command_reg;
+	wire [31:0] abstractcs_reg;
+	wire [31:0] haltsum0_reg;
+	wire [31:0] data0_reg;
+	wire [31:0] data1_reg;
+	wire [31:0] data0_din;
+	wire data0_reg_wren;
+	wire data0_reg_wren0;
+	wire data0_reg_wren1;
+	reg data0_reg_wren2;
+	wire [31:0] data1_din;
+	wire data1_reg_wren;
+	wire data1_reg_wren0;
+	wire data1_reg_wren1;
+	reg abstractcs_busy_wren;
+	reg abstractcs_busy_din;
+	wire [2:0] abstractcs_error_din;
+	wire abstractcs_error_sel0;
+	wire abstractcs_error_sel1;
+	wire abstractcs_error_seb1;
+	wire abstractcs_error_sel3;
+	wire abstractcs_error_sel4;
+	wire abstractcs_error_sel5;
+	wire abstractcs_error_sel6;
+	reg dbg_sb_bus_error;
+	wire abstractauto_reg_wren;
+	wire [1:0] abstractauto_reg;
+	wire dmstatus_resumeack_wren;
+	wire dmstatus_resumeack_din;
+	wire dmstatus_haveresetn_wren;
+	wire dmstatus_resumeack;
+	wire dmstatus_unavail;
+	wire dmstatus_running;
+	wire dmstatus_halted;
+	wire dmstatus_havereset;
+	wire dmstatus_haveresetn;
+	wire resumereq;
+	wire dmcontrol_wren;
+	wire dmcontrol_wren_Q;
+	wire execute_command_ns;
+	wire execute_command;
+	wire command_wren;
+	wire command_regno_wren;
+	wire command_transfer_din;
+	wire command_postexec_din;
+	wire [31:0] command_din;
+	wire [3:0] dbg_cmd_addr_incr;
+	wire [31:0] dbg_cmd_curr_addr;
+	wire [31:0] dbg_cmd_next_addr;
+	wire [31:0] dmi_reg_rdata_din;
+	wire [3:0] sb_state;
+	reg [3:0] sb_nxtstate;
+	reg sb_state_en;
+	wire sbcs_wren;
+	reg sbcs_sbbusy_wren;
+	reg sbcs_sbbusy_din;
+	wire sbcs_sbbusyerror_wren;
+	wire sbcs_sbbusyerror_din;
+	reg sbcs_sberror_wren;
+	reg [2:0] sbcs_sberror_din;
+	wire sbcs_unaligned;
+	wire sbcs_illegal_size;
+	wire [19:15] sbcs_reg_int;
+	wire sbdata0_reg_wren0;
+	wire sbdata0_reg_wren1;
+	wire sbdata0_reg_wren;
+	wire [31:0] sbdata0_din;
+	wire sbdata1_reg_wren0;
+	wire sbdata1_reg_wren1;
+	wire sbdata1_reg_wren;
+	wire [31:0] sbdata1_din;
+	wire sbaddress0_reg_wren0;
+	reg sbaddress0_reg_wren1;
+	wire sbaddress0_reg_wren;
+	wire [31:0] sbaddress0_reg_din;
+	wire [3:0] sbaddress0_incr;
+	wire sbreadonaddr_access;
+	wire sbreadondata_access;
+	wire sbdata0wr_access;
+	reg sb_abmem_cmd_done_in;
+	reg sb_abmem_data_done_in;
+	reg sb_abmem_cmd_done_en;
+	reg sb_abmem_data_done_en;
+	wire sb_abmem_cmd_done;
+	wire sb_abmem_data_done;
+	wire [31:0] abmem_addr;
+	wire abmem_addr_in_dccm_region;
+	wire abmem_addr_in_iccm_region;
+	wire abmem_addr_in_pic_region;
+	wire abmem_addr_core_local;
+	wire abmem_addr_external;
+	wire sb_cmd_pending;
+	wire sb_abmem_cmd_pending;
+	wire sb_abmem_cmd_write;
+	wire [2:0] sb_abmem_cmd_size;
+	wire [31:0] sb_abmem_cmd_addr;
+	wire [31:0] sb_abmem_cmd_wdata;
+	wire [2:0] sb_cmd_size;
+	wire [31:0] sb_cmd_addr;
+	wire [63:0] sb_cmd_wdata;
+	wire sb_bus_cmd_read;
+	wire sb_bus_cmd_write_addr;
+	wire sb_bus_cmd_write_data;
+	wire sb_bus_rsp_read;
+	wire sb_bus_rsp_write;
+	wire sb_bus_rsp_error;
+	wire [63:0] sb_bus_rdata;
+	wire [31:0] sbcs_reg;
+	wire [31:0] sbaddress0_reg;
+	wire [31:0] sbdata0_reg;
+	wire [31:0] sbdata1_reg;
+	wire sb_abmem_cmd_arvalid;
+	wire sb_abmem_cmd_awvalid;
+	wire sb_abmem_cmd_wvalid;
+	wire sb_abmem_read_pend;
+	wire sb_cmd_awvalid;
+	wire sb_cmd_wvalid;
+	wire sb_cmd_arvalid;
+	wire sb_read_pend;
+	wire [31:0] sb_axi_addr;
+	wire [63:0] sb_axi_wrdata;
+	wire [2:0] sb_axi_size;
+	wire dbg_dm_rst_l;
+	wire dbg_free_clken;
+	wire dbg_free_clk;
+	wire sb_free_clken;
+	wire sb_free_clk;
+	localparam [3:0] IDLE = 4'h0;
+	assign dbg_free_clken = (((((((dmi_reg_en | execute_command) | (dbg_state != IDLE)) | dbg_state_en) | dec_tlu_dbg_halted) | dec_tlu_mpc_halted_only) | dec_tlu_debug_mode) | dbg_halt_req) | clk_override;
+	localparam [3:0] SBIDLE = 4'h0;
+	assign sb_free_clken = (((dmi_reg_en | execute_command) | sb_state_en) | (sb_state != SBIDLE)) | clk_override;
+	rvoclkhdr dbg_free_cgc(
+		.en(dbg_free_clken),
+		.l1clk(dbg_free_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr sb_free_cgc(
+		.en(sb_free_clken),
+		.l1clk(sb_free_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode);
+	assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;
+	assign sbcs_reg[31:29] = 3'b001;
+	assign sbcs_reg[28:23] = {6 {1'sb0}};
+	assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]};
+	assign sbcs_reg[11:5] = 7'h20;
+	assign sbcs_reg[4:0] = 5'b01111;
+	assign sbcs_wren = (((dmi_reg_addr == 7'h38) & dmi_reg_en) & dmi_reg_wr_en) & (sb_state == SBIDLE);
+	assign sbcs_sbbusyerror_wren = (sbcs_wren & dmi_reg_wdata[22]) | ((sbcs_reg[21] & dmi_reg_en) & (((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c)) | (dmi_reg_addr == 7'h3d)));
+	assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]);
+	rvdffs #(.WIDTH(1)) sbcs_sbbusyerror_reg(
+		.din(sbcs_sbbusyerror_din),
+		.dout(sbcs_reg[22]),
+		.en(sbcs_sbbusyerror_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	rvdffs #(.WIDTH(1)) sbcs_sbbusy_reg(
+		.din(sbcs_sbbusy_din),
+		.dout(sbcs_reg[21]),
+		.en(sbcs_sbbusy_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	rvdffs #(.WIDTH(1)) sbcs_sbreadonaddr_reg(
+		.din(dmi_reg_wdata[20]),
+		.dout(sbcs_reg[20]),
+		.en(sbcs_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	rvdffs #(.WIDTH(5)) sbcs_misc_reg(
+		.din({dmi_reg_wdata[19], ~dmi_reg_wdata[18], dmi_reg_wdata[17:15]}),
+		.dout(sbcs_reg_int[19:15]),
+		.en(sbcs_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	rvdffs #(.WIDTH(3)) sbcs_error_reg(
+		.din(sbcs_sberror_din[2:0]),
+		.dout(sbcs_reg[14:12]),
+		.en(sbcs_sberror_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	assign sbcs_unaligned = (((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) | ((sbcs_reg[19:17] == 3'b010) & |sbaddress0_reg[1:0])) | ((sbcs_reg[19:17] == 3'b011) & |sbaddress0_reg[2:0]);
+	assign sbcs_illegal_size = sbcs_reg[19];
+	assign sbaddress0_incr[3:0] = ((({4 {sbcs_reg[19:17] == 3'h0}} & 4'b0001) | ({4 {sbcs_reg[19:17] == 3'h1}} & 4'b0010)) | ({4 {sbcs_reg[19:17] == 3'h2}} & 4'b0100)) | ({4 {sbcs_reg[19:17] == 3'h3}} & 4'b1000);
+	assign sbdata0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c);
+	localparam [3:0] RSP_RD = 4'h7;
+	assign sbdata0_reg_wren1 = ((sb_state == RSP_RD) & sb_state_en) & ~sbcs_sberror_wren;
+	assign sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1;
+	assign sbdata1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3d);
+	assign sbdata1_reg_wren1 = ((sb_state == RSP_RD) & sb_state_en) & ~sbcs_sberror_wren;
+	assign sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1;
+	assign sbdata0_din[31:0] = ({32 {sbdata0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbdata0_reg_wren1}} & sb_bus_rdata[31:0]);
+	assign sbdata1_din[31:0] = ({32 {sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbdata1_reg_wren1}} & sb_bus_rdata[63:32]);
+	rvdffe #(.WIDTH(32)) dbg_sbdata0_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(sbdata0_din[31:0]),
+		.dout(sbdata0_reg[31:0]),
+		.en(sbdata0_reg_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	rvdffe #(.WIDTH(32)) dbg_sbdata1_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(sbdata1_din[31:0]),
+		.dout(sbdata1_reg[31:0]),
+		.en(sbdata1_reg_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	assign sbaddress0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h39);
+	assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;
+	assign sbaddress0_reg_din[31:0] = ({32 {sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbaddress0_reg_wren1}} & (sbaddress0_reg[31:0] + {28'b0000000000000000000000000000, sbaddress0_incr[3:0]}));
+	rvdffe #(.WIDTH(32)) dbg_sbaddress0_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(sbaddress0_reg_din[31:0]),
+		.dout(sbaddress0_reg[31:0]),
+		.en(sbaddress0_reg_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	assign sbreadonaddr_access = ((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h39)) & sbcs_reg[20];
+	assign sbreadondata_access = ((dmi_reg_en & ~dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c)) & sbcs_reg[15];
+	assign sbdata0wr_access = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c);
+	assign dmcontrol_wren = ((dmi_reg_addr == 7'h10) & dmi_reg_en) & dmi_reg_wr_en;
+	assign dmcontrol_reg[29] = 1'b0;
+	assign dmcontrol_reg[27:2] = {26 {1'sb0}};
+	assign resumereq = (dmcontrol_reg[30] & ~dmcontrol_reg[31]) & dmcontrol_wren_Q;
+	rvdffs #(.WIDTH(4)) dmcontrolff(
+		.din({dmi_reg_wdata[31:30], dmi_reg_wdata[28], dmi_reg_wdata[1]}),
+		.dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}),
+		.en(dmcontrol_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdffs #(.WIDTH(1)) dmcontrol_dmactive_ff(
+		.din(dmi_reg_wdata[0]),
+		.dout(dmcontrol_reg[0]),
+		.en(dmcontrol_wren),
+		.rst_l(dbg_rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdff #(.WIDTH(1)) dmcontrol_wrenff(
+		.din(dmcontrol_wren),
+		.dout(dmcontrol_wren_Q),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	assign dmstatus_reg[31:20] = {12 {1'sb0}};
+	assign dmstatus_reg[19:18] = {2 {dmstatus_havereset}};
+	assign dmstatus_reg[15:14] = {2 {1'sb0}};
+	assign dmstatus_reg[7] = 1'b1;
+	assign dmstatus_reg[6:4] = {3 {1'sb0}};
+	assign dmstatus_reg[17:16] = {2 {dmstatus_resumeack}};
+	assign dmstatus_reg[13:12] = {2 {dmstatus_unavail}};
+	assign dmstatus_reg[11:10] = {2 {dmstatus_running}};
+	assign dmstatus_reg[9:8] = {2 {dmstatus_halted}};
+	assign dmstatus_reg[3:0] = 4'h2;
+	localparam [3:0] RESUMING = 4'h9;
+	assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | ((dmstatus_resumeack & resumereq) & dmstatus_halted);
+	assign dmstatus_resumeack_din = (dbg_state == RESUMING) & dec_tlu_resume_ack;
+	assign dmstatus_haveresetn_wren = ((((dmi_reg_addr == 7'h10) & dmi_reg_wdata[28]) & dmi_reg_en) & dmi_reg_wr_en) & dmcontrol_reg[0];
+	assign dmstatus_havereset = ~dmstatus_haveresetn;
+	assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l;
+	assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);
+	rvdffs #(.WIDTH(1)) dmstatus_resumeack_reg(
+		.din(dmstatus_resumeack_din),
+		.dout(dmstatus_resumeack),
+		.en(dmstatus_resumeack_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdff #(.WIDTH(1)) dmstatus_halted_reg(
+		.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only),
+		.dout(dmstatus_halted),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdffs #(.WIDTH(1)) dmstatus_haveresetn_reg(
+		.din(1'b1),
+		.dout(dmstatus_haveresetn),
+		.en(dmstatus_haveresetn_wren),
+		.rst_l(rst_l),
+		.clk(dbg_free_clk)
+	);
+	assign haltsum0_reg[31:1] = {31 {1'sb0}};
+	assign haltsum0_reg[0] = dmstatus_halted;
+	assign abstractcs_reg[31:13] = {19 {1'sb0}};
+	assign abstractcs_reg[11] = 1'b0;
+	assign abstractcs_reg[7:4] = {4 {1'sb0}};
+	assign abstractcs_reg[3:0] = 4'h2;
+	assign abstractcs_error_sel0 = ((abstractcs_reg[12] & ~(|abstractcs_reg[10:8])) & dmi_reg_en) & ((((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17))) | (dmi_reg_addr == 7'h18)) | (dmi_reg_addr == 7'h04)) | (dmi_reg_addr == 7'h05));
+	assign abstractcs_error_sel1 = (execute_command & ~(|abstractcs_reg[10:8])) & (((~((command_reg[31:24] == 8'b00000000) | (command_reg[31:24] == 8'h02)) | (((command_reg[22:20] == 3'b011) | command_reg[22]) & (command_reg[31:24] == 8'h02))) | ((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h00) & command_reg[17]))) | ((command_reg[31:24] == 8'h00) & command_reg[18]));
+	assign abstractcs_error_seb1 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | ((execute_command & (command_reg[31:24] == 8'h00)) & (((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]);
+	localparam [3:0] HALTED = 4'h2;
+	assign abstractcs_error_sel3 = (execute_command & (dbg_state != HALTED)) & ~(|abstractcs_reg[10:8]);
+	assign abstractcs_error_sel4 = (dbg_sb_bus_error & dbg_bus_clk_en) & ~(|abstractcs_reg[10:8]);
+	assign abstractcs_error_sel5 = ((execute_command & (command_reg[31:24] == 8'h02)) & ~(|abstractcs_reg[10:8])) & (((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & |data1_reg[1:0]));
+	assign abstractcs_error_sel6 = ((dmi_reg_addr == 7'h16) & dmi_reg_en) & dmi_reg_wr_en;
+	assign abstractcs_error_din[2:0] = (abstractcs_error_sel0 ? 3'b001 : (abstractcs_error_sel1 ? 3'b010 : (abstractcs_error_seb1 ? 3'b011 : (abstractcs_error_sel3 ? 3'b100 : (abstractcs_error_sel4 ? 3'b101 : (abstractcs_error_sel5 ? 3'b111 : (abstractcs_error_sel6 ? ~dmi_reg_wdata[10:8] & abstractcs_reg[10:8] : abstractcs_reg[10:8])))))));
+	rvdffs #(.WIDTH(1)) dmabstractcs_busy_reg(
+		.din(abstractcs_busy_din),
+		.dout(abstractcs_reg[12]),
+		.en(abstractcs_busy_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdff #(.WIDTH(3)) dmabstractcs_error_reg(
+		.din(abstractcs_error_din[2:0]),
+		.dout(abstractcs_reg[10:8]),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	assign abstractauto_reg_wren = ((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h18)) & ~abstractcs_reg[12];
+	rvdffs #(.WIDTH(2)) dbg_abstractauto_reg(
+		.din(dmi_reg_wdata[1:0]),
+		.dout(abstractauto_reg[1:0]),
+		.en(abstractauto_reg_wren),
+		.rst_l(dbg_dm_rst_l),
+		.clk(dbg_free_clk)
+	);
+	assign execute_command_ns = command_wren | ((dmi_reg_en & ~abstractcs_reg[12]) & (((dmi_reg_addr == 7'h04) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h05) & abstractauto_reg[1])));
+	assign command_wren = ((dmi_reg_addr == 7'h17) & dmi_reg_en) & dmi_reg_wr_en;
+	localparam [3:0] CMD_DONE = 4'h8;
+	assign command_regno_wren = command_wren | ((((command_reg[31:24] == 8'h00) & command_reg[19]) & (dbg_state == CMD_DONE)) & ~(|abstractcs_reg[10:8]));
+	assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h00) & dmi_reg_wdata[18];
+	assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h00) & dmi_reg_wdata[17];
+	assign command_din[31:16] = {dmi_reg_wdata[31:24], 1'b0, dmi_reg_wdata[22:19], command_postexec_din, command_transfer_din, dmi_reg_wdata[16]};
+	assign command_din[15:0] = (command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]);
+	rvdff #(.WIDTH(1)) execute_commandff(
+		.din(execute_command_ns),
+		.dout(execute_command),
+		.clk(dbg_free_clk),
+		.rst_l(dbg_dm_rst_l)
+	);
+	rvdffe #(.WIDTH(16)) dmcommand_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(command_din[31:16]),
+		.dout(command_reg[31:16]),
+		.en(command_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	rvdffe #(.WIDTH(16)) dmcommand_regno_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(command_din[15:0]),
+		.dout(command_reg[15:0]),
+		.en(command_regno_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	assign data0_reg_wren0 = (((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h04)) & (dbg_state == HALTED)) & ~abstractcs_reg[12];
+	localparam [3:0] CORE_CMD_WAIT = 4'h4;
+	assign data0_reg_wren1 = (core_dbg_cmd_done & (dbg_state == CORE_CMD_WAIT)) & ~command_reg[16];
+	assign data0_reg_wren = (data0_reg_wren0 | data0_reg_wren1) | data0_reg_wren2;
+	assign data0_din[31:0] = (({32 {data0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {data0_reg_wren1}} & core_dbg_rddata[31:0])) | ({32 {data0_reg_wren2}} & sb_bus_rdata[31:0]);
+	rvdffe #(.WIDTH(32)) dbg_data0_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(data0_din[31:0]),
+		.dout(data0_reg[31:0]),
+		.en(data0_reg_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	assign data1_reg_wren0 = (((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h05)) & (dbg_state == HALTED)) & ~abstractcs_reg[12];
+	assign data1_reg_wren1 = (((dbg_state == CMD_DONE) & (command_reg[31:24] == 8'h02)) & command_reg[19]) & ~(|abstractcs_reg[10:8]);
+	assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1;
+	assign data1_din[31:0] = ({32 {data1_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {data1_reg_wren1}} & dbg_cmd_next_addr[31:0]);
+	rvdffe #(.WIDTH(32)) dbg_data1_reg(
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.din(data1_din[31:0]),
+		.dout(data1_reg[31:0]),
+		.en(data1_reg_wren),
+		.rst_l(dbg_dm_rst_l)
+	);
+	rvdffs #(.WIDTH(1)) sb_abmem_cmd_doneff(
+		.din(sb_abmem_cmd_done_in),
+		.dout(sb_abmem_cmd_done),
+		.en(sb_abmem_cmd_done_en),
+		.clk(dbg_free_clk),
+		.rst_l(dbg_dm_rst_l)
+	);
+	rvdffs #(.WIDTH(1)) sb_abmem_data_doneff(
+		.din(sb_abmem_data_done_in),
+		.dout(sb_abmem_data_done),
+		.en(sb_abmem_data_done_en),
+		.clk(dbg_free_clk),
+		.rst_l(dbg_dm_rst_l)
+	);
+	localparam [3:0] CORE_CMD_START = 4'h3;
+	localparam [3:0] HALTING = 4'h1;
+	localparam [3:0] SB_CMD_RESP = 4'h7;
+	localparam [3:0] SB_CMD_SEND = 4'h6;
+	localparam [3:0] SB_CMD_START = 4'h5;
+	always @(*) begin
+		dbg_nxtstate = IDLE;
+		dbg_state_en = 1'b0;
+		abstractcs_busy_wren = 1'b0;
+		abstractcs_busy_din = 1'b0;
+		dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31];
+		dbg_resume_req = 1'b0;
+		dbg_sb_bus_error = 1'b0;
+		data0_reg_wren2 = 1'b0;
+		sb_abmem_cmd_done_in = 1'b0;
+		sb_abmem_data_done_in = 1'b0;
+		sb_abmem_cmd_done_en = 1'b0;
+		sb_abmem_data_done_en = 1'b0;
+		case (dbg_state)
+			IDLE: begin
+				dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only ? HALTED : HALTING);
+				dbg_state_en = (dmcontrol_reg[31] | dmstatus_reg[9]) | dec_tlu_mpc_halted_only;
+				dbg_halt_req = dmcontrol_reg[31];
+			end
+			HALTING: begin
+				dbg_nxtstate = HALTED;
+				dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only;
+			end
+			HALTED: begin
+				dbg_nxtstate = (dmstatus_reg[9] ? (resumereq ? RESUMING : ((command_reg[31:24] == 8'h02) & abmem_addr_external ? SB_CMD_START : CORE_CMD_START)) : (dmcontrol_reg[31] ? HALTING : IDLE));
+				dbg_state_en = ((dmstatus_reg[9] & resumereq) | execute_command) | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
+				abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START));
+				abstractcs_busy_din = 1'b1;
+				dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING);
+			end
+			CORE_CMD_START: begin
+				dbg_nxtstate = (|abstractcs_reg[10:8] | ((command_reg[31:24] == 8'h00) & ~command_reg[17]) ? CMD_DONE : CORE_CMD_WAIT);
+				dbg_state_en = (dbg_cmd_valid | |abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h00) & ~command_reg[17]);
+			end
+			CORE_CMD_WAIT: begin
+				dbg_nxtstate = CMD_DONE;
+				dbg_state_en = core_dbg_cmd_done;
+			end
+			SB_CMD_START: begin
+				dbg_nxtstate = (|abstractcs_reg[10:8] ? CMD_DONE : SB_CMD_SEND);
+				dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | |abstractcs_reg[10:8];
+			end
+			SB_CMD_SEND: begin
+				sb_abmem_cmd_done_in = 1'b1;
+				sb_abmem_data_done_in = 1'b1;
+				sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en;
+				sb_abmem_data_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en;
+				dbg_nxtstate = SB_CMD_RESP;
+				dbg_state_en = ((sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en)) & dbg_bus_clk_en;
+			end
+			SB_CMD_RESP: begin
+				dbg_nxtstate = CMD_DONE;
+				dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en;
+				dbg_sb_bus_error = ((sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error) & dbg_bus_clk_en;
+				data0_reg_wren2 = (dbg_state_en & ~sb_abmem_cmd_write) & ~dbg_sb_bus_error;
+			end
+			CMD_DONE: begin
+				dbg_nxtstate = HALTED;
+				dbg_state_en = 1'b1;
+				abstractcs_busy_wren = dbg_state_en;
+				abstractcs_busy_din = 1'b0;
+				sb_abmem_cmd_done_in = 1'b0;
+				sb_abmem_data_done_in = 1'b0;
+				sb_abmem_cmd_done_en = 1'b1;
+				sb_abmem_data_done_en = 1'b1;
+			end
+			RESUMING: begin
+				dbg_nxtstate = IDLE;
+				dbg_state_en = dmstatus_reg[17];
+			end
+			default: begin
+				dbg_nxtstate = IDLE;
+				dbg_state_en = 1'b0;
+				abstractcs_busy_wren = 1'b0;
+				abstractcs_busy_din = 1'b0;
+				dbg_halt_req = 1'b0;
+				dbg_resume_req = 1'b0;
+				dbg_sb_bus_error = 1'b0;
+				data0_reg_wren2 = 1'b0;
+				sb_abmem_cmd_done_in = 1'b0;
+				sb_abmem_data_done_in = 1'b0;
+				sb_abmem_cmd_done_en = 1'b0;
+				sb_abmem_data_done_en = 1'b0;
+			end
+		endcase
+	end
+	assign dmi_reg_rdata_din[31:0] = ((((((((((({32 {dmi_reg_addr == 7'h04}} & data0_reg[31:0]) | ({32 {dmi_reg_addr == 7'h05}} & data1_reg[31:0])) | ({32 {dmi_reg_addr == 7'h10}} & {2'b00, dmcontrol_reg[29], 1'b0, dmcontrol_reg[27:0]})) | ({32 {dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0])) | ({32 {dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0])) | ({32 {dmi_reg_addr == 7'h17}} & command_reg[31:0])) | ({32 {dmi_reg_addr == 7'h18}} & {30'h00000000, abstractauto_reg[1:0]})) | ({32 {dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h38}} & sbcs_reg[31:0])) | ({32 {dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);
+	rvdffs #(.WIDTH(4)) dbg_state_reg(
+		.din(dbg_nxtstate),
+		.dout({dbg_state}),
+		.en(dbg_state_en),
+		.rst_l(dbg_dm_rst_l & rst_l),
+		.clk(dbg_free_clk)
+	);
+	rvdffe #(.WIDTH(32)) dmi_rddata_reg(
+		.din(dmi_reg_rdata_din[31:0]),
+		.dout(dmi_reg_rdata[31:0]),
+		.en(dmi_reg_en),
+		.rst_l(dbg_dm_rst_l),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign abmem_addr[31:0] = data1_reg[31:0];
+	assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region) | abmem_addr_in_pic_region;
+	assign abmem_addr_external = ~abmem_addr_core_local;
+	assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == pt[1333-:8]) & pt[1365-:5];
+	assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == pt[895-:8]) & pt[927-:5];
+	assign abmem_addr_in_pic_region = abmem_addr[31:28] == pt[77-:8];
+	assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h02 ? data1_reg[31:0] : {20'b00000000000000000000, command_reg[11:0]});
+	assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];
+	assign dbg_cmd_valid = ((dbg_state == CORE_CMD_START) & ~((|abstractcs_reg[10:8] | ((command_reg[31:24] == 8'h00) & ~command_reg[17])) | ((command_reg[31:24] == 8'h02) & abmem_addr_external))) & dma_dbg_ready;
+	assign dbg_cmd_write = command_reg[16];
+	assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h02 ? 2'b10 : {1'b0, command_reg[15:12] == 4'b0000});
+	assign dbg_cmd_size[1:0] = command_reg[21:20];
+	assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h02 ? 4'h1 << sb_abmem_cmd_size[1:0] : 4'h1);
+	assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h02 ? data1_reg[31:0] : {16'b0000000000000000, command_reg[15:0]});
+	assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0000000, dbg_cmd_addr_incr[3:0]};
+	assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT);
+	localparam [3:0] CMD_RD = 4'h3;
+	localparam [3:0] CMD_WR = 4'h4;
+	localparam [3:0] CMD_WR_ADDR = 4'h5;
+	localparam [3:0] CMD_WR_DATA = 4'h6;
+	localparam [3:0] RSP_WR = 4'h8;
+	assign sb_cmd_pending = (((((sb_state == CMD_RD) | (sb_state == CMD_WR)) | (sb_state == CMD_WR_ADDR)) | (sb_state == CMD_WR_DATA)) | (sb_state == RSP_RD)) | (sb_state == RSP_WR);
+	assign sb_abmem_cmd_pending = ((dbg_state == SB_CMD_START) | (dbg_state == SB_CMD_SEND)) | (dbg_state == SB_CMD_RESP);
+	localparam [3:0] DONE = 4'h9;
+	localparam [3:0] WAIT_RD = 4'h1;
+	localparam [3:0] WAIT_WR = 4'h2;
+	always @(*) begin
+		sb_nxtstate = SBIDLE;
+		sb_state_en = 1'b0;
+		sbcs_sbbusy_wren = 1'b0;
+		sbcs_sbbusy_din = 1'b0;
+		sbcs_sberror_wren = 1'b0;
+		sbcs_sberror_din[2:0] = 3'b000;
+		sbaddress0_reg_wren1 = 1'b0;
+		case (sb_state)
+			SBIDLE: begin
+				sb_nxtstate = (sbdata0wr_access ? WAIT_WR : WAIT_RD);
+				sb_state_en = (((sbdata0wr_access | sbreadondata_access) | sbreadonaddr_access) & ~(|sbcs_reg[14:12])) & ~sbcs_reg[22];
+				sbcs_sbbusy_wren = sb_state_en;
+				sbcs_sbbusy_din = 1'b1;
+				sbcs_sberror_wren = sbcs_wren & |dmi_reg_wdata[14:12];
+				sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
+			end
+			WAIT_RD: begin
+				sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size ? DONE : CMD_RD);
+				sb_state_en = ((dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned) | sbcs_illegal_size;
+				sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
+				sbcs_sberror_din[2:0] = (sbcs_unaligned ? 3'b011 : 3'b100);
+			end
+			WAIT_WR: begin
+				sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size ? DONE : CMD_WR);
+				sb_state_en = ((dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned) | sbcs_illegal_size;
+				sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
+				sbcs_sberror_din[2:0] = (sbcs_unaligned ? 3'b011 : 3'b100);
+			end
+			CMD_RD: begin
+				sb_nxtstate = RSP_RD;
+				sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en;
+			end
+			CMD_WR: begin
+				sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA));
+				sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en;
+			end
+			CMD_WR_ADDR: begin
+				sb_nxtstate = RSP_WR;
+				sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en;
+			end
+			CMD_WR_DATA: begin
+				sb_nxtstate = RSP_WR;
+				sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en;
+			end
+			RSP_RD: begin
+				sb_nxtstate = DONE;
+				sb_state_en = sb_bus_rsp_read & dbg_bus_clk_en;
+				sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;
+				sbcs_sberror_din[2:0] = 3'b010;
+			end
+			RSP_WR: begin
+				sb_nxtstate = DONE;
+				sb_state_en = sb_bus_rsp_write & dbg_bus_clk_en;
+				sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;
+				sbcs_sberror_din[2:0] = 3'b010;
+			end
+			DONE: begin
+				sb_nxtstate = SBIDLE;
+				sb_state_en = 1'b1;
+				sbcs_sbbusy_wren = 1'b1;
+				sbcs_sbbusy_din = 1'b0;
+				sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b000);
+			end
+			default: begin
+				sb_nxtstate = SBIDLE;
+				sb_state_en = 1'b0;
+				sbcs_sbbusy_wren = 1'b0;
+				sbcs_sbbusy_din = 1'b0;
+				sbcs_sberror_wren = 1'b0;
+				sbcs_sberror_din[2:0] = 3'b000;
+				sbaddress0_reg_wren1 = 1'b0;
+			end
+		endcase
+	end
+	rvdffs #(.WIDTH(4)) sb_state_reg(
+		.din(sb_nxtstate),
+		.dout({sb_state}),
+		.en(sb_state_en),
+		.rst_l(dbg_dm_rst_l),
+		.clk(sb_free_clk)
+	);
+	assign sb_abmem_cmd_write = command_reg[16];
+	assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]};
+	assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0];
+	assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0];
+	assign sb_cmd_size[2:0] = sbcs_reg[19:17];
+	assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]};
+	assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0];
+	assign sb_abmem_cmd_awvalid = ((dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write) & ~sb_abmem_cmd_done;
+	assign sb_abmem_cmd_wvalid = ((dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write) & ~sb_abmem_data_done;
+	assign sb_abmem_cmd_arvalid = (((dbg_state == SB_CMD_SEND) & ~sb_abmem_cmd_write) & ~sb_abmem_cmd_done) & ~sb_abmem_data_done;
+	assign sb_abmem_read_pend = (dbg_state == SB_CMD_RESP) & ~sb_abmem_cmd_write;
+	assign sb_cmd_awvalid = (sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR);
+	assign sb_cmd_wvalid = (sb_state == CMD_WR) | (sb_state == CMD_WR_DATA);
+	assign sb_cmd_arvalid = sb_state == CMD_RD;
+	assign sb_read_pend = sb_state == RSP_RD;
+	assign sb_axi_size[2:0] = (((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) | sb_abmem_cmd_arvalid) | sb_abmem_read_pend ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0]);
+	assign sb_axi_addr[31:0] = (((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) | sb_abmem_cmd_arvalid) | sb_abmem_read_pend ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0]);
+	assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid ? {2 {sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0]);
+	assign sb_bus_cmd_read = sb_axi_arvalid & sb_axi_arready;
+	assign sb_bus_cmd_write_addr = sb_axi_awvalid & sb_axi_awready;
+	assign sb_bus_cmd_write_data = sb_axi_wvalid & sb_axi_wready;
+	assign sb_bus_rsp_read = sb_axi_rvalid & sb_axi_rready;
+	assign sb_bus_rsp_write = sb_axi_bvalid & sb_axi_bready;
+	assign sb_bus_rsp_error = (sb_bus_rsp_read & |sb_axi_rresp[1:0]) | (sb_bus_rsp_write & |sb_axi_bresp[1:0]);
+	assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid;
+	assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0];
+	assign sb_axi_awid[pt[12-:8] - 1:0] = {pt[12-:8] {1'sb0}};
+	assign sb_axi_awsize[2:0] = sb_axi_size[2:0];
+	assign sb_axi_awprot[2:0] = 3'b001;
+	assign sb_axi_awcache[3:0] = 4'b1111;
+	assign sb_axi_awregion[3:0] = sb_axi_addr[31:28];
+	assign sb_axi_awlen[7:0] = {8 {1'sb0}};
+	assign sb_axi_awburst[1:0] = 2'b01;
+	assign sb_axi_awqos[3:0] = {4 {1'sb0}};
+	assign sb_axi_awlock = 1'b0;
+	assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid;
+	assign sb_axi_wdata[63:0] = ((({64 {sb_axi_size[2:0] == 3'h0}} & {8 {sb_axi_wrdata[7:0]}}) | ({64 {sb_axi_size[2:0] == 3'h1}} & {4 {sb_axi_wrdata[15:0]}})) | ({64 {sb_axi_size[2:0] == 3'h2}} & {2 {sb_axi_wrdata[31:0]}})) | ({64 {sb_axi_size[2:0] == 3'h3}} & {sb_axi_wrdata[63:0]});
+	assign sb_axi_wstrb[7:0] = ((({8 {sb_axi_size[2:0] == 3'h0}} & (8'h01 << sb_axi_addr[2:0])) | ({8 {sb_axi_size[2:0] == 3'h1}} & (8'h03 << {sb_axi_addr[2:1], 1'b0}))) | ({8 {sb_axi_size[2:0] == 3'h2}} & (8'h0f << {sb_axi_addr[2], 2'b00}))) | ({8 {sb_axi_size[2:0] == 3'h3}} & 8'hff);
+	assign sb_axi_wlast = 1'b1;
+	assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid;
+	assign sb_axi_araddr[31:0] = sb_axi_addr[31:0];
+	assign sb_axi_arid[pt[12-:8] - 1:0] = {pt[12-:8] {1'sb0}};
+	assign sb_axi_arsize[2:0] = sb_axi_size[2:0];
+	assign sb_axi_arprot[2:0] = 3'b001;
+	assign sb_axi_arcache[3:0] = 4'b0000;
+	assign sb_axi_arregion[3:0] = sb_axi_addr[31:28];
+	assign sb_axi_arlen[7:0] = {8 {1'sb0}};
+	assign sb_axi_arburst[1:0] = 2'b01;
+	assign sb_axi_arqos[3:0] = {4 {1'sb0}};
+	assign sb_axi_arlock = 1'b0;
+	assign sb_axi_bready = 1'b1;
+	assign sb_axi_rready = 1'b1;
+	assign sb_bus_rdata[63:0] = ((({64 {sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> (8 * sb_axi_addr[2:0])) & 64'h00000000000000ff)) | ({64 {sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> (16 * sb_axi_addr[2:1])) & 64'h000000000000ffff))) | ({64 {sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> (32 * sb_axi_addr[2])) & 64'h00000000ffffffff))) | ({64 {sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]);
+endmodule
+module eb1_dec (
+	clk,
+	active_clk,
+	free_clk,
+	free_l2clk,
+	lsu_fastint_stall_any,
+	dec_extint_stall,
+	dec_i0_decode_d,
+	dec_pause_state_cg,
+	dec_tlu_core_empty,
+	rst_l,
+	rst_vec,
+	nmi_int,
+	nmi_vec,
+	i_cpu_halt_req,
+	i_cpu_run_req,
+	o_cpu_halt_status,
+	o_cpu_halt_ack,
+	o_cpu_run_ack,
+	o_debug_mode_status,
+	core_id,
+	mpc_debug_halt_req,
+	mpc_debug_run_req,
+	mpc_reset_run_req,
+	mpc_debug_halt_ack,
+	mpc_debug_run_ack,
+	debug_brkpt_status,
+	exu_pmu_i0_br_misp,
+	exu_pmu_i0_br_ataken,
+	exu_pmu_i0_pc4,
+	lsu_nonblock_load_valid_m,
+	lsu_nonblock_load_tag_m,
+	lsu_nonblock_load_inv_r,
+	lsu_nonblock_load_inv_tag_r,
+	lsu_nonblock_load_data_valid,
+	lsu_nonblock_load_data_error,
+	lsu_nonblock_load_data_tag,
+	lsu_nonblock_load_data,
+	lsu_pmu_bus_trxn,
+	lsu_pmu_bus_misaligned,
+	lsu_pmu_bus_error,
+	lsu_pmu_bus_busy,
+	lsu_pmu_misaligned_m,
+	lsu_pmu_load_external_m,
+	lsu_pmu_store_external_m,
+	dma_pmu_dccm_read,
+	dma_pmu_dccm_write,
+	dma_pmu_any_read,
+	dma_pmu_any_write,
+	lsu_fir_addr,
+	lsu_fir_error,
+	ifu_pmu_instr_aligned,
+	ifu_pmu_fetch_stall,
+	ifu_pmu_ic_miss,
+	ifu_pmu_ic_hit,
+	ifu_pmu_bus_error,
+	ifu_pmu_bus_busy,
+	ifu_pmu_bus_trxn,
+	ifu_ic_error_start,
+	ifu_iccm_rd_ecc_single_err,
+	lsu_trigger_match_m,
+	dbg_cmd_valid,
+	dbg_cmd_write,
+	dbg_cmd_type,
+	dbg_cmd_addr,
+	dbg_cmd_wrdata,
+	ifu_i0_icaf,
+	ifu_i0_icaf_type,
+	ifu_i0_icaf_second,
+	ifu_i0_dbecc,
+	lsu_idle_any,
+	i0_brp,
+	ifu_i0_bp_index,
+	ifu_i0_bp_fghr,
+	ifu_i0_bp_btag,
+	ifu_i0_fa_index,
+	lsu_error_pkt_r,
+	lsu_single_ecc_error_incr,
+	lsu_imprecise_error_load_any,
+	lsu_imprecise_error_store_any,
+	lsu_imprecise_error_addr_any,
+	exu_div_result,
+	exu_div_wren,
+	exu_csr_rs1_x,
+	lsu_result_m,
+	lsu_result_corr_r,
+	lsu_load_stall_any,
+	lsu_store_stall_any,
+	dma_dccm_stall_any,
+	dma_iccm_stall_any,
+	iccm_dma_sb_error,
+	exu_flush_final,
+	exu_npc_r,
+	exu_i0_result_x,
+	ifu_i0_valid,
+	ifu_i0_instr,
+	ifu_i0_pc,
+	ifu_i0_pc4,
+	exu_i0_pc_x,
+	mexintpend,
+	timer_int,
+	soft_int,
+	pic_claimid,
+	pic_pl,
+	mhwakeup,
+	dec_tlu_meicurpl,
+	dec_tlu_meipt,
+	ifu_ic_debug_rd_data,
+	ifu_ic_debug_rd_data_valid,
+	dec_tlu_ic_diag_pkt,
+	dbg_halt_req,
+	dbg_resume_req,
+	ifu_miss_state_idle,
+	dec_tlu_dbg_halted,
+	dec_tlu_debug_mode,
+	dec_tlu_resume_ack,
+	dec_tlu_flush_noredir_r,
+	dec_tlu_mpc_halted_only,
+	dec_tlu_flush_leak_one_r,
+	dec_tlu_flush_err_r,
+	dec_tlu_meihap,
+	dec_debug_wdata_rs1_d,
+	dec_dbg_rddata,
+	dec_dbg_cmd_done,
+	dec_dbg_cmd_fail,
+	trigger_pkt_any,
+	dec_tlu_force_halt,
+	exu_i0_br_hist_r,
+	exu_i0_br_error_r,
+	exu_i0_br_start_error_r,
+	exu_i0_br_valid_r,
+	exu_i0_br_mp_r,
+	exu_i0_br_middle_r,
+	exu_i0_br_way_r,
+	dec_i0_rs1_en_d,
+	dec_i0_rs2_en_d,
+	gpr_i0_rs1_d,
+	gpr_i0_rs2_d,
+	dec_i0_immed_d,
+	dec_i0_br_immed_d,
+	i0_ap,
+	dec_i0_alu_decode_d,
+	dec_i0_branch_d,
+	dec_i0_select_pc_d,
+	dec_i0_pc_d,
+	dec_i0_rs1_bypass_en_d,
+	dec_i0_rs2_bypass_en_d,
+	dec_i0_result_r,
+	lsu_p,
+	dec_qual_lsu_d,
+	mul_p,
+	div_p,
+	dec_div_cancel,
+	dec_lsu_offset_d,
+	dec_csr_ren_d,
+	dec_csr_rddata_d,
+	dec_tlu_flush_lower_r,
+	dec_tlu_flush_lower_wb,
+	dec_tlu_flush_path_r,
+	dec_tlu_i0_kill_writeb_r,
+	dec_tlu_fence_i_r,
+	pred_correct_npc_x,
+	dec_tlu_br0_r_pkt,
+	dec_tlu_perfcnt0,
+	dec_tlu_perfcnt1,
+	dec_tlu_perfcnt2,
+	dec_tlu_perfcnt3,
+	dec_i0_predict_p_d,
+	i0_predict_fghr_d,
+	i0_predict_index_d,
+	i0_predict_btag_d,
+	dec_fa_error_index,
+	dec_lsu_valid_raw_d,
+	dec_tlu_mrac_ff,
+	dec_data_en,
+	dec_ctl_en,
+	ifu_i0_cinst,
+	trace_rv_trace_pkt,
+	dec_tlu_external_ldfwd_disable,
+	dec_tlu_sideeffect_posted_disable,
+	dec_tlu_core_ecc_disable,
+	dec_tlu_bpred_disable,
+	dec_tlu_wb_coalescing_disable,
+	dec_tlu_dma_qos_prty,
+	dec_tlu_misc_clk_override,
+	dec_tlu_ifu_clk_override,
+	dec_tlu_lsu_clk_override,
+	dec_tlu_bus_clk_override,
+	dec_tlu_pic_clk_override,
+	dec_tlu_picio_clk_override,
+	dec_tlu_dccm_clk_override,
+	dec_tlu_icm_clk_override,
+	dec_tlu_i0_commit_cmt,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire active_clk;
+	input wire free_clk;
+	input wire free_l2clk;
+	input wire lsu_fastint_stall_any;
+	output wire dec_extint_stall;
+	output wire dec_i0_decode_d;
+	output wire dec_pause_state_cg;
+	output wire dec_tlu_core_empty;
+	input wire rst_l;
+	input wire [31:1] rst_vec;
+	input wire nmi_int;
+	input wire [31:1] nmi_vec;
+	input wire i_cpu_halt_req;
+	input wire i_cpu_run_req;
+	output wire o_cpu_halt_status;
+	output wire o_cpu_halt_ack;
+	output wire o_cpu_run_ack;
+	output wire o_debug_mode_status;
+	input wire [31:4] core_id;
+	input wire mpc_debug_halt_req;
+	input wire mpc_debug_run_req;
+	input wire mpc_reset_run_req;
+	output wire mpc_debug_halt_ack;
+	output wire mpc_debug_run_ack;
+	output wire debug_brkpt_status;
+	input wire exu_pmu_i0_br_misp;
+	input wire exu_pmu_i0_br_ataken;
+	input wire exu_pmu_i0_pc4;
+	input wire lsu_nonblock_load_valid_m;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	input wire lsu_nonblock_load_inv_r;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	input wire lsu_nonblock_load_data_valid;
+	input wire lsu_nonblock_load_data_error;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	input wire [31:0] lsu_nonblock_load_data;
+	input wire lsu_pmu_bus_trxn;
+	input wire lsu_pmu_bus_misaligned;
+	input wire lsu_pmu_bus_error;
+	input wire lsu_pmu_bus_busy;
+	input wire lsu_pmu_misaligned_m;
+	input wire lsu_pmu_load_external_m;
+	input wire lsu_pmu_store_external_m;
+	input wire dma_pmu_dccm_read;
+	input wire dma_pmu_dccm_write;
+	input wire dma_pmu_any_read;
+	input wire dma_pmu_any_write;
+	input wire [31:1] lsu_fir_addr;
+	input wire [1:0] lsu_fir_error;
+	input wire ifu_pmu_instr_aligned;
+	input wire ifu_pmu_fetch_stall;
+	input wire ifu_pmu_ic_miss;
+	input wire ifu_pmu_ic_hit;
+	input wire ifu_pmu_bus_error;
+	input wire ifu_pmu_bus_busy;
+	input wire ifu_pmu_bus_trxn;
+	input wire ifu_ic_error_start;
+	input wire ifu_iccm_rd_ecc_single_err;
+	input wire [3:0] lsu_trigger_match_m;
+	input wire dbg_cmd_valid;
+	input wire dbg_cmd_write;
+	input wire [1:0] dbg_cmd_type;
+	input wire [31:0] dbg_cmd_addr;
+	input wire [1:0] dbg_cmd_wrdata;
+	input wire ifu_i0_icaf;
+	input wire [1:0] ifu_i0_icaf_type;
+	input wire ifu_i0_icaf_second;
+	input wire ifu_i0_dbecc;
+	input wire lsu_idle_any;
+	input wire [50:0] i0_brp;
+	input wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index;
+	input wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr;
+	input wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag;
+	input wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index;
+	input wire [39:0] lsu_error_pkt_r;
+	input wire lsu_single_ecc_error_incr;
+	input wire lsu_imprecise_error_load_any;
+	input wire lsu_imprecise_error_store_any;
+	input wire [31:0] lsu_imprecise_error_addr_any;
+	input wire [31:0] exu_div_result;
+	input wire exu_div_wren;
+	input wire [31:0] exu_csr_rs1_x;
+	input wire [31:0] lsu_result_m;
+	input wire [31:0] lsu_result_corr_r;
+	input wire lsu_load_stall_any;
+	input wire lsu_store_stall_any;
+	input wire dma_dccm_stall_any;
+	input wire dma_iccm_stall_any;
+	input wire iccm_dma_sb_error;
+	input wire exu_flush_final;
+	input wire [31:1] exu_npc_r;
+	input wire [31:0] exu_i0_result_x;
+	input wire ifu_i0_valid;
+	input wire [31:0] ifu_i0_instr;
+	input wire [31:1] ifu_i0_pc;
+	input wire ifu_i0_pc4;
+	input wire [31:1] exu_i0_pc_x;
+	input wire mexintpend;
+	input wire timer_int;
+	input wire soft_int;
+	input wire [7:0] pic_claimid;
+	input wire [3:0] pic_pl;
+	input wire mhwakeup;
+	output wire [3:0] dec_tlu_meicurpl;
+	output wire [3:0] dec_tlu_meipt;
+	input wire [70:0] ifu_ic_debug_rd_data;
+	input wire ifu_ic_debug_rd_data_valid;
+	output wire [89:0] dec_tlu_ic_diag_pkt;
+	input wire dbg_halt_req;
+	input wire dbg_resume_req;
+	input wire ifu_miss_state_idle;
+	output wire dec_tlu_dbg_halted;
+	output wire dec_tlu_debug_mode;
+	output wire dec_tlu_resume_ack;
+	output wire dec_tlu_flush_noredir_r;
+	output wire dec_tlu_mpc_halted_only;
+	output wire dec_tlu_flush_leak_one_r;
+	output wire dec_tlu_flush_err_r;
+	output wire [31:2] dec_tlu_meihap;
+	output wire dec_debug_wdata_rs1_d;
+	output wire [31:0] dec_dbg_rddata;
+	output wire dec_dbg_cmd_done;
+	output wire dec_dbg_cmd_fail;
+	output wire [151:0] trigger_pkt_any;
+	output wire dec_tlu_force_halt;
+	input wire [1:0] exu_i0_br_hist_r;
+	input wire exu_i0_br_error_r;
+	input wire exu_i0_br_start_error_r;
+	input wire exu_i0_br_valid_r;
+	input wire exu_i0_br_mp_r;
+	input wire exu_i0_br_middle_r;
+	input wire exu_i0_br_way_r;
+	output wire dec_i0_rs1_en_d;
+	output wire dec_i0_rs2_en_d;
+	output wire [31:0] gpr_i0_rs1_d;
+	output wire [31:0] gpr_i0_rs2_d;
+	output wire [31:0] dec_i0_immed_d;
+	output wire [12:1] dec_i0_br_immed_d;
+	output wire [43:0] i0_ap;
+	output wire dec_i0_alu_decode_d;
+	output wire dec_i0_branch_d;
+	output wire dec_i0_select_pc_d;
+	output wire [31:1] dec_i0_pc_d;
+	output wire [3:0] dec_i0_rs1_bypass_en_d;
+	output wire [3:0] dec_i0_rs2_bypass_en_d;
+	output wire [31:0] dec_i0_result_r;
+	output wire [13:0] lsu_p;
+	output wire dec_qual_lsu_d;
+	output wire [19:0] mul_p;
+	output wire [2:0] div_p;
+	output wire dec_div_cancel;
+	output wire [11:0] dec_lsu_offset_d;
+	output wire dec_csr_ren_d;
+	output wire [31:0] dec_csr_rddata_d;
+	output wire dec_tlu_flush_lower_r;
+	output wire dec_tlu_flush_lower_wb;
+	output wire [31:1] dec_tlu_flush_path_r;
+	output wire dec_tlu_i0_kill_writeb_r;
+	output wire dec_tlu_fence_i_r;
+	output wire [31:1] pred_correct_npc_x;
+	output wire [6:0] dec_tlu_br0_r_pkt;
+	output wire dec_tlu_perfcnt0;
+	output wire dec_tlu_perfcnt1;
+	output wire dec_tlu_perfcnt2;
+	output wire dec_tlu_perfcnt3;
+	output wire [55:0] dec_i0_predict_p_d;
+	output wire [pt[2236-:8] - 1:0] i0_predict_fghr_d;
+	output wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d;
+	output wire [pt[2139-:9] - 1:0] i0_predict_btag_d;
+	output wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index;
+	output wire dec_lsu_valid_raw_d;
+	output wire [31:0] dec_tlu_mrac_ff;
+	output wire [1:0] dec_data_en;
+	output wire [1:0] dec_ctl_en;
+	input wire [15:0] ifu_i0_cinst;
+	output wire [103:0] trace_rv_trace_pkt;
+	output wire dec_tlu_external_ldfwd_disable;
+	output wire dec_tlu_sideeffect_posted_disable;
+	output wire dec_tlu_core_ecc_disable;
+	output wire dec_tlu_bpred_disable;
+	output wire dec_tlu_wb_coalescing_disable;
+	output wire [2:0] dec_tlu_dma_qos_prty;
+	output wire dec_tlu_misc_clk_override;
+	output wire dec_tlu_ifu_clk_override;
+	output wire dec_tlu_lsu_clk_override;
+	output wire dec_tlu_bus_clk_override;
+	output wire dec_tlu_pic_clk_override;
+	output wire dec_tlu_picio_clk_override;
+	output wire dec_tlu_dccm_clk_override;
+	output wire dec_tlu_icm_clk_override;
+	output wire dec_tlu_i0_commit_cmt;
+	input wire scan_mode;
+	wire dec_tlu_dec_clk_override;
+	wire clk_override;
+	wire dec_ib0_valid_d;
+	wire dec_pmu_instr_decoded;
+	wire dec_pmu_decode_stall;
+	wire dec_pmu_presync_stall;
+	wire dec_pmu_postsync_stall;
+	wire dec_tlu_wr_pause_r;
+	wire [4:0] dec_i0_rs1_d;
+	wire [4:0] dec_i0_rs2_d;
+	wire [31:0] dec_i0_instr_d;
+	wire dec_tlu_trace_disable;
+	wire dec_tlu_pipelining_disable;
+	wire [4:0] dec_i0_waddr_r;
+	wire dec_i0_wen_r;
+	wire [31:0] dec_i0_wdata_r;
+	wire dec_csr_wen_r;
+	wire [11:0] dec_csr_wraddr_r;
+	wire [31:0] dec_csr_wrdata_r;
+	wire [11:0] dec_csr_rdaddr_d;
+	wire dec_csr_legal_d;
+	wire dec_csr_wen_unq_d;
+	wire dec_csr_any_unq_d;
+	wire dec_csr_stall_int_ff;
+	wire [16:0] dec_tlu_packet_r;
+	wire dec_i0_pc4_d;
+	wire dec_tlu_presync_d;
+	wire dec_tlu_postsync_d;
+	wire dec_tlu_debug_stall;
+	wire [31:0] dec_illegal_inst;
+	wire dec_i0_icaf_d;
+	wire dec_i0_dbecc_d;
+	wire dec_i0_icaf_second_d;
+	wire [3:0] dec_i0_trigger_match_d;
+	wire dec_debug_fence_d;
+	wire dec_nonblock_load_wen;
+	wire [4:0] dec_nonblock_load_waddr;
+	wire dec_tlu_flush_pause_r;
+	wire [50:0] dec_i0_brp;
+	wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index;
+	wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr;
+	wire [pt[2139-:9] - 1:0] dec_i0_bp_btag;
+	wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index;
+	wire [31:1] dec_tlu_i0_pc_r;
+	wire dec_tlu_i0_kill_writeb_wb;
+	wire dec_tlu_i0_valid_r;
+	wire dec_pause_state;
+	wire [1:0] dec_i0_icaf_type_d;
+	wire dec_tlu_flush_extint;
+	wire [31:0] dec_i0_inst_wb;
+	wire [31:1] dec_i0_pc_wb;
+	wire dec_tlu_i0_valid_wb1;
+	wire dec_tlu_int_valid_wb1;
+	wire [4:0] dec_tlu_exc_cause_wb1;
+	wire [31:0] dec_tlu_mtval_wb1;
+	wire dec_tlu_i0_exc_valid_wb1;
+	wire [4:0] div_waddr_wb;
+	wire dec_div_active;
+	wire dec_debug_valid_d;
+	assign clk_override = dec_tlu_dec_clk_override;
+	assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0];
+	eb1_dec_ib_ctl #(.pt(pt)) instbuff(
+		.dbg_cmd_valid(dbg_cmd_valid),
+		.dbg_cmd_write(dbg_cmd_write),
+		.dbg_cmd_type(dbg_cmd_type),
+		.dbg_cmd_addr(dbg_cmd_addr),
+		.i0_brp(i0_brp),
+		.ifu_i0_bp_index(ifu_i0_bp_index),
+		.ifu_i0_bp_fghr(ifu_i0_bp_fghr),
+		.ifu_i0_bp_btag(ifu_i0_bp_btag),
+		.ifu_i0_fa_index(ifu_i0_fa_index),
+		.ifu_i0_pc4(ifu_i0_pc4),
+		.ifu_i0_valid(ifu_i0_valid),
+		.ifu_i0_icaf(ifu_i0_icaf),
+		.ifu_i0_icaf_type(ifu_i0_icaf_type),
+		.ifu_i0_icaf_second(ifu_i0_icaf_second),
+		.ifu_i0_dbecc(ifu_i0_dbecc),
+		.ifu_i0_instr(ifu_i0_instr),
+		.ifu_i0_pc(ifu_i0_pc),
+		.dec_ib0_valid_d(dec_ib0_valid_d),
+		.dec_debug_valid_d(dec_debug_valid_d),
+		.dec_i0_instr_d(dec_i0_instr_d),
+		.dec_i0_pc_d(dec_i0_pc_d),
+		.dec_i0_pc4_d(dec_i0_pc4_d),
+		.dec_i0_brp(dec_i0_brp),
+		.dec_i0_bp_index(dec_i0_bp_index),
+		.dec_i0_bp_fghr(dec_i0_bp_fghr),
+		.dec_i0_bp_btag(dec_i0_bp_btag),
+		.dec_i0_bp_fa_index(dec_i0_bp_fa_index),
+		.dec_i0_icaf_d(dec_i0_icaf_d),
+		.dec_i0_icaf_second_d(dec_i0_icaf_second_d),
+		.dec_i0_icaf_type_d(dec_i0_icaf_type_d),
+		.dec_i0_dbecc_d(dec_i0_dbecc_d),
+		.dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d),
+		.dec_debug_fence_d(dec_debug_fence_d)
+	);
+	eb1_dec_decode_ctl #(.pt(pt)) decode(
+		.dec_tlu_trace_disable(dec_tlu_trace_disable),
+		.dec_debug_valid_d(dec_debug_valid_d),
+		.dec_tlu_flush_extint(dec_tlu_flush_extint),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.dec_extint_stall(dec_extint_stall),
+		.ifu_i0_cinst(ifu_i0_cinst),
+		.dec_i0_inst_wb(dec_i0_inst_wb),
+		.dec_i0_pc_wb(dec_i0_pc_wb),
+		.lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m),
+		.lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m),
+		.lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r),
+		.lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r),
+		.lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid),
+		.lsu_nonblock_load_data_error(lsu_nonblock_load_data_error),
+		.lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag),
+		.dec_i0_trigger_match_d(dec_i0_trigger_match_d),
+		.dec_tlu_wr_pause_r(dec_tlu_wr_pause_r),
+		.dec_tlu_pipelining_disable(dec_tlu_pipelining_disable),
+		.lsu_trigger_match_m(lsu_trigger_match_m),
+		.lsu_pmu_misaligned_m(lsu_pmu_misaligned_m),
+		.dec_tlu_debug_stall(dec_tlu_debug_stall),
+		.dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r),
+		.dec_debug_fence_d(dec_debug_fence_d),
+		.dbg_cmd_wrdata(dbg_cmd_wrdata),
+		.dec_i0_icaf_d(dec_i0_icaf_d),
+		.dec_i0_icaf_second_d(dec_i0_icaf_second_d),
+		.dec_i0_icaf_type_d(dec_i0_icaf_type_d),
+		.dec_i0_dbecc_d(dec_i0_dbecc_d),
+		.dec_i0_brp(dec_i0_brp),
+		.dec_i0_bp_index(dec_i0_bp_index),
+		.dec_i0_bp_fghr(dec_i0_bp_fghr),
+		.dec_i0_bp_btag(dec_i0_bp_btag),
+		.dec_i0_bp_fa_index(dec_i0_bp_fa_index),
+		.lsu_idle_any(lsu_idle_any),
+		.lsu_load_stall_any(lsu_load_stall_any),
+		.lsu_store_stall_any(lsu_store_stall_any),
+		.dma_dccm_stall_any(dma_dccm_stall_any),
+		.exu_div_wren(exu_div_wren),
+		.dec_tlu_i0_kill_writeb_wb(dec_tlu_i0_kill_writeb_wb),
+		.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb),
+		.dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
+		.dec_tlu_flush_lower_r(dec_tlu_flush_lower_r),
+		.dec_tlu_flush_pause_r(dec_tlu_flush_pause_r),
+		.dec_tlu_presync_d(dec_tlu_presync_d),
+		.dec_tlu_postsync_d(dec_tlu_postsync_d),
+		.dec_i0_pc4_d(dec_i0_pc4_d),
+		.dec_csr_rddata_d(dec_csr_rddata_d),
+		.dec_csr_legal_d(dec_csr_legal_d),
+		.exu_csr_rs1_x(exu_csr_rs1_x),
+		.lsu_result_m(lsu_result_m),
+		.lsu_result_corr_r(lsu_result_corr_r),
+		.exu_flush_final(exu_flush_final),
+		.exu_i0_pc_x(exu_i0_pc_x),
+		.dec_i0_instr_d(dec_i0_instr_d),
+		.dec_ib0_valid_d(dec_ib0_valid_d),
+		.exu_i0_result_x(exu_i0_result_x),
+		.clk(clk),
+		.active_clk(active_clk),
+		.free_l2clk(free_l2clk),
+		.clk_override(clk_override),
+		.rst_l(rst_l),
+		.dec_i0_rs1_en_d(dec_i0_rs1_en_d),
+		.dec_i0_rs2_en_d(dec_i0_rs2_en_d),
+		.dec_i0_rs1_d(dec_i0_rs1_d),
+		.dec_i0_rs2_d(dec_i0_rs2_d),
+		.dec_i0_immed_d(dec_i0_immed_d),
+		.dec_i0_br_immed_d(dec_i0_br_immed_d),
+		.i0_ap(i0_ap),
+		.dec_i0_decode_d(dec_i0_decode_d),
+		.dec_i0_alu_decode_d(dec_i0_alu_decode_d),
+		.dec_i0_branch_d(dec_i0_branch_d),
+		.dec_i0_waddr_r(dec_i0_waddr_r),
+		.dec_i0_wen_r(dec_i0_wen_r),
+		.dec_i0_wdata_r(dec_i0_wdata_r),
+		.dec_i0_select_pc_d(dec_i0_select_pc_d),
+		.dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d),
+		.dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d),
+		.dec_i0_result_r(dec_i0_result_r),
+		.lsu_p(lsu_p),
+		.dec_qual_lsu_d(dec_qual_lsu_d),
+		.mul_p(mul_p),
+		.div_p(div_p),
+		.div_waddr_wb(div_waddr_wb),
+		.dec_div_cancel(dec_div_cancel),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.dec_lsu_offset_d(dec_lsu_offset_d),
+		.dec_csr_ren_d(dec_csr_ren_d),
+		.dec_csr_wen_unq_d(dec_csr_wen_unq_d),
+		.dec_csr_any_unq_d(dec_csr_any_unq_d),
+		.dec_csr_rdaddr_d(dec_csr_rdaddr_d),
+		.dec_csr_wen_r(dec_csr_wen_r),
+		.dec_csr_wraddr_r(dec_csr_wraddr_r),
+		.dec_csr_wrdata_r(dec_csr_wrdata_r),
+		.dec_csr_stall_int_ff(dec_csr_stall_int_ff),
+		.dec_tlu_i0_valid_r(dec_tlu_i0_valid_r),
+		.dec_tlu_packet_r(dec_tlu_packet_r),
+		.dec_tlu_i0_pc_r(dec_tlu_i0_pc_r),
+		.dec_illegal_inst(dec_illegal_inst),
+		.pred_correct_npc_x(pred_correct_npc_x),
+		.dec_i0_predict_p_d(dec_i0_predict_p_d),
+		.i0_predict_fghr_d(i0_predict_fghr_d),
+		.i0_predict_index_d(i0_predict_index_d),
+		.i0_predict_btag_d(i0_predict_btag_d),
+		.dec_fa_error_index(dec_fa_error_index),
+		.dec_data_en(dec_data_en),
+		.dec_ctl_en(dec_ctl_en),
+		.dec_pmu_instr_decoded(dec_pmu_instr_decoded),
+		.dec_pmu_decode_stall(dec_pmu_decode_stall),
+		.dec_pmu_presync_stall(dec_pmu_presync_stall),
+		.dec_pmu_postsync_stall(dec_pmu_postsync_stall),
+		.dec_nonblock_load_wen(dec_nonblock_load_wen),
+		.dec_nonblock_load_waddr(dec_nonblock_load_waddr),
+		.dec_pause_state(dec_pause_state),
+		.dec_pause_state_cg(dec_pause_state_cg),
+		.dec_div_active(dec_div_active),
+		.scan_mode(scan_mode)
+	);
+	eb1_dec_tlu_ctl #(.pt(pt)) tlu(
+		.clk(clk),
+		.free_clk(free_clk),
+		.free_l2clk(free_l2clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.rst_vec(rst_vec),
+		.nmi_int(nmi_int),
+		.nmi_vec(nmi_vec),
+		.i_cpu_halt_req(i_cpu_halt_req),
+		.i_cpu_run_req(i_cpu_run_req),
+		.lsu_fastint_stall_any(lsu_fastint_stall_any),
+		.ifu_pmu_instr_aligned(ifu_pmu_instr_aligned),
+		.ifu_pmu_fetch_stall(ifu_pmu_fetch_stall),
+		.ifu_pmu_ic_miss(ifu_pmu_ic_miss),
+		.ifu_pmu_ic_hit(ifu_pmu_ic_hit),
+		.ifu_pmu_bus_error(ifu_pmu_bus_error),
+		.ifu_pmu_bus_busy(ifu_pmu_bus_busy),
+		.ifu_pmu_bus_trxn(ifu_pmu_bus_trxn),
+		.dec_pmu_instr_decoded(dec_pmu_instr_decoded),
+		.dec_pmu_decode_stall(dec_pmu_decode_stall),
+		.dec_pmu_presync_stall(dec_pmu_presync_stall),
+		.dec_pmu_postsync_stall(dec_pmu_postsync_stall),
+		.lsu_store_stall_any(lsu_store_stall_any),
+		.dma_dccm_stall_any(dma_dccm_stall_any),
+		.dma_iccm_stall_any(dma_iccm_stall_any),
+		.exu_pmu_i0_br_misp(exu_pmu_i0_br_misp),
+		.exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken),
+		.exu_pmu_i0_pc4(exu_pmu_i0_pc4),
+		.lsu_pmu_bus_trxn(lsu_pmu_bus_trxn),
+		.lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned),
+		.lsu_pmu_bus_error(lsu_pmu_bus_error),
+		.lsu_pmu_bus_busy(lsu_pmu_bus_busy),
+		.lsu_pmu_load_external_m(lsu_pmu_load_external_m),
+		.lsu_pmu_store_external_m(lsu_pmu_store_external_m),
+		.dma_pmu_dccm_read(dma_pmu_dccm_read),
+		.dma_pmu_dccm_write(dma_pmu_dccm_write),
+		.dma_pmu_any_read(dma_pmu_any_read),
+		.dma_pmu_any_write(dma_pmu_any_write),
+		.lsu_fir_addr(lsu_fir_addr),
+		.lsu_fir_error(lsu_fir_error),
+		.iccm_dma_sb_error(iccm_dma_sb_error),
+		.lsu_error_pkt_r(lsu_error_pkt_r),
+		.lsu_single_ecc_error_incr(lsu_single_ecc_error_incr),
+		.dec_pause_state(dec_pause_state),
+		.lsu_imprecise_error_store_any(lsu_imprecise_error_store_any),
+		.lsu_imprecise_error_load_any(lsu_imprecise_error_load_any),
+		.lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any),
+		.dec_csr_wen_unq_d(dec_csr_wen_unq_d),
+		.dec_csr_any_unq_d(dec_csr_any_unq_d),
+		.dec_csr_rdaddr_d(dec_csr_rdaddr_d),
+		.dec_csr_wen_r(dec_csr_wen_r),
+		.dec_csr_wraddr_r(dec_csr_wraddr_r),
+		.dec_csr_wrdata_r(dec_csr_wrdata_r),
+		.dec_csr_stall_int_ff(dec_csr_stall_int_ff),
+		.dec_tlu_i0_valid_r(dec_tlu_i0_valid_r),
+		.exu_npc_r(exu_npc_r),
+		.dec_tlu_i0_pc_r(dec_tlu_i0_pc_r),
+		.dec_tlu_packet_r(dec_tlu_packet_r),
+		.dec_illegal_inst(dec_illegal_inst),
+		.dec_i0_decode_d(dec_i0_decode_d),
+		.exu_i0_br_hist_r(exu_i0_br_hist_r),
+		.exu_i0_br_error_r(exu_i0_br_error_r),
+		.exu_i0_br_start_error_r(exu_i0_br_start_error_r),
+		.exu_i0_br_valid_r(exu_i0_br_valid_r),
+		.exu_i0_br_mp_r(exu_i0_br_mp_r),
+		.exu_i0_br_middle_r(exu_i0_br_middle_r),
+		.exu_i0_br_way_r(exu_i0_br_way_r),
+		.dec_tlu_core_empty(dec_tlu_core_empty),
+		.dec_dbg_cmd_done(dec_dbg_cmd_done),
+		.dec_dbg_cmd_fail(dec_dbg_cmd_fail),
+		.dec_tlu_dbg_halted(dec_tlu_dbg_halted),
+		.dec_tlu_debug_mode(dec_tlu_debug_mode),
+		.dec_tlu_resume_ack(dec_tlu_resume_ack),
+		.dec_tlu_debug_stall(dec_tlu_debug_stall),
+		.dec_tlu_flush_noredir_r(dec_tlu_flush_noredir_r),
+		.dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only),
+		.dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r),
+		.dec_tlu_flush_err_r(dec_tlu_flush_err_r),
+		.dec_tlu_flush_extint(dec_tlu_flush_extint),
+		.dec_tlu_meihap(dec_tlu_meihap),
+		.dbg_halt_req(dbg_halt_req),
+		.dbg_resume_req(dbg_resume_req),
+		.ifu_miss_state_idle(ifu_miss_state_idle),
+		.lsu_idle_any(lsu_idle_any),
+		.dec_div_active(dec_div_active),
+		.trigger_pkt_any(trigger_pkt_any),
+		.ifu_ic_error_start(ifu_ic_error_start),
+		.ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err),
+		.ifu_ic_debug_rd_data(ifu_ic_debug_rd_data),
+		.ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid),
+		.dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt),
+		.pic_claimid(pic_claimid),
+		.pic_pl(pic_pl),
+		.mhwakeup(mhwakeup),
+		.mexintpend(mexintpend),
+		.timer_int(timer_int),
+		.soft_int(soft_int),
+		.o_cpu_halt_status(o_cpu_halt_status),
+		.o_cpu_halt_ack(o_cpu_halt_ack),
+		.o_cpu_run_ack(o_cpu_run_ack),
+		.o_debug_mode_status(o_debug_mode_status),
+		.core_id(core_id),
+		.mpc_debug_halt_req(mpc_debug_halt_req),
+		.mpc_debug_run_req(mpc_debug_run_req),
+		.mpc_reset_run_req(mpc_reset_run_req),
+		.mpc_debug_halt_ack(mpc_debug_halt_ack),
+		.mpc_debug_run_ack(mpc_debug_run_ack),
+		.debug_brkpt_status(debug_brkpt_status),
+		.dec_tlu_meicurpl(dec_tlu_meicurpl),
+		.dec_tlu_meipt(dec_tlu_meipt),
+		.dec_csr_rddata_d(dec_csr_rddata_d),
+		.dec_csr_legal_d(dec_csr_legal_d),
+		.dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt),
+		.dec_tlu_i0_kill_writeb_wb(dec_tlu_i0_kill_writeb_wb),
+		.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb),
+		.dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt),
+		.dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
+		.dec_tlu_flush_lower_r(dec_tlu_flush_lower_r),
+		.dec_tlu_flush_path_r(dec_tlu_flush_path_r),
+		.dec_tlu_fence_i_r(dec_tlu_fence_i_r),
+		.dec_tlu_wr_pause_r(dec_tlu_wr_pause_r),
+		.dec_tlu_flush_pause_r(dec_tlu_flush_pause_r),
+		.dec_tlu_presync_d(dec_tlu_presync_d),
+		.dec_tlu_postsync_d(dec_tlu_postsync_d),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.dec_tlu_perfcnt0(dec_tlu_perfcnt0),
+		.dec_tlu_perfcnt1(dec_tlu_perfcnt1),
+		.dec_tlu_perfcnt2(dec_tlu_perfcnt2),
+		.dec_tlu_perfcnt3(dec_tlu_perfcnt3),
+		.dec_tlu_i0_exc_valid_wb1(dec_tlu_i0_exc_valid_wb1),
+		.dec_tlu_i0_valid_wb1(dec_tlu_i0_valid_wb1),
+		.dec_tlu_int_valid_wb1(dec_tlu_int_valid_wb1),
+		.dec_tlu_exc_cause_wb1(dec_tlu_exc_cause_wb1),
+		.dec_tlu_mtval_wb1(dec_tlu_mtval_wb1),
+		.dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable),
+		.dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.dec_tlu_bpred_disable(dec_tlu_bpred_disable),
+		.dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable),
+		.dec_tlu_pipelining_disable(dec_tlu_pipelining_disable),
+		.dec_tlu_trace_disable(dec_tlu_trace_disable),
+		.dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty),
+		.dec_tlu_misc_clk_override(dec_tlu_misc_clk_override),
+		.dec_tlu_dec_clk_override(dec_tlu_dec_clk_override),
+		.dec_tlu_ifu_clk_override(dec_tlu_ifu_clk_override),
+		.dec_tlu_lsu_clk_override(dec_tlu_lsu_clk_override),
+		.dec_tlu_bus_clk_override(dec_tlu_bus_clk_override),
+		.dec_tlu_pic_clk_override(dec_tlu_pic_clk_override),
+		.dec_tlu_picio_clk_override(dec_tlu_picio_clk_override),
+		.dec_tlu_dccm_clk_override(dec_tlu_dccm_clk_override),
+		.dec_tlu_icm_clk_override(dec_tlu_icm_clk_override)
+	);
+	eb1_dec_gpr_ctl #(.pt(pt)) arf(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.raddr0(dec_i0_rs1_d[4:0]),
+		.raddr1(dec_i0_rs2_d[4:0]),
+		.wen0(dec_i0_wen_r),
+		.waddr0(dec_i0_waddr_r[4:0]),
+		.wd0(dec_i0_wdata_r[31:0]),
+		.wen1(dec_nonblock_load_wen),
+		.waddr1(dec_nonblock_load_waddr[4:0]),
+		.wd1(lsu_nonblock_load_data[31:0]),
+		.wen2(exu_div_wren),
+		.waddr2(div_waddr_wb),
+		.wd2(exu_div_result[31:0]),
+		.rd0(gpr_i0_rs1_d[31:0]),
+		.rd1(gpr_i0_rs2_d[31:0])
+	);
+	eb1_dec_trigger #(.pt(pt)) dec_trigger(
+		.trigger_pkt_any(trigger_pkt_any),
+		.dec_i0_pc_d(dec_i0_pc_d),
+		.dec_i0_trigger_match_d(dec_i0_trigger_match_d)
+	);
+	assign trace_rv_trace_pkt[102-:32] = dec_i0_inst_wb[31:0];
+	assign trace_rv_trace_pkt[70-:32] = {dec_i0_pc_wb[31:1], 1'b0};
+	assign trace_rv_trace_pkt[103] = (dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1) | dec_tlu_i0_exc_valid_wb1;
+	assign trace_rv_trace_pkt[38] = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
+	assign trace_rv_trace_pkt[37-:5] = dec_tlu_exc_cause_wb1[4:0];
+	assign trace_rv_trace_pkt[32] = dec_tlu_int_valid_wb1;
+	assign trace_rv_trace_pkt[31-:32] = dec_tlu_mtval_wb1[31:0];
+endmodule
+module eb1_dec_decode_ctl (
+	dec_tlu_trace_disable,
+	dec_debug_valid_d,
+	dec_tlu_flush_extint,
+	dec_tlu_force_halt,
+	dec_extint_stall,
+	ifu_i0_cinst,
+	dec_i0_inst_wb,
+	dec_i0_pc_wb,
+	lsu_nonblock_load_valid_m,
+	lsu_nonblock_load_tag_m,
+	lsu_nonblock_load_inv_r,
+	lsu_nonblock_load_inv_tag_r,
+	lsu_nonblock_load_data_valid,
+	lsu_nonblock_load_data_error,
+	lsu_nonblock_load_data_tag,
+	dec_i0_trigger_match_d,
+	dec_tlu_wr_pause_r,
+	dec_tlu_pipelining_disable,
+	lsu_trigger_match_m,
+	lsu_pmu_misaligned_m,
+	dec_tlu_debug_stall,
+	dec_tlu_flush_leak_one_r,
+	dec_debug_fence_d,
+	dbg_cmd_wrdata,
+	dec_i0_icaf_d,
+	dec_i0_icaf_second_d,
+	dec_i0_icaf_type_d,
+	dec_i0_dbecc_d,
+	dec_i0_brp,
+	dec_i0_bp_index,
+	dec_i0_bp_fghr,
+	dec_i0_bp_btag,
+	dec_i0_bp_fa_index,
+	lsu_idle_any,
+	lsu_load_stall_any,
+	lsu_store_stall_any,
+	dma_dccm_stall_any,
+	exu_div_wren,
+	dec_tlu_i0_kill_writeb_wb,
+	dec_tlu_flush_lower_wb,
+	dec_tlu_i0_kill_writeb_r,
+	dec_tlu_flush_lower_r,
+	dec_tlu_flush_pause_r,
+	dec_tlu_presync_d,
+	dec_tlu_postsync_d,
+	dec_i0_pc4_d,
+	dec_csr_rddata_d,
+	dec_csr_legal_d,
+	exu_csr_rs1_x,
+	lsu_result_m,
+	lsu_result_corr_r,
+	exu_flush_final,
+	exu_i0_pc_x,
+	dec_i0_instr_d,
+	dec_ib0_valid_d,
+	exu_i0_result_x,
+	clk,
+	active_clk,
+	free_l2clk,
+	clk_override,
+	rst_l,
+	dec_i0_rs1_en_d,
+	dec_i0_rs2_en_d,
+	dec_i0_rs1_d,
+	dec_i0_rs2_d,
+	dec_i0_immed_d,
+	dec_i0_br_immed_d,
+	i0_ap,
+	dec_i0_decode_d,
+	dec_i0_alu_decode_d,
+	dec_i0_branch_d,
+	dec_i0_waddr_r,
+	dec_i0_wen_r,
+	dec_i0_wdata_r,
+	dec_i0_select_pc_d,
+	dec_i0_rs1_bypass_en_d,
+	dec_i0_rs2_bypass_en_d,
+	dec_i0_result_r,
+	lsu_p,
+	dec_qual_lsu_d,
+	mul_p,
+	div_p,
+	div_waddr_wb,
+	dec_div_cancel,
+	dec_lsu_valid_raw_d,
+	dec_lsu_offset_d,
+	dec_csr_ren_d,
+	dec_csr_wen_unq_d,
+	dec_csr_any_unq_d,
+	dec_csr_rdaddr_d,
+	dec_csr_wen_r,
+	dec_csr_wraddr_r,
+	dec_csr_wrdata_r,
+	dec_csr_stall_int_ff,
+	dec_tlu_i0_valid_r,
+	dec_tlu_packet_r,
+	dec_tlu_i0_pc_r,
+	dec_illegal_inst,
+	pred_correct_npc_x,
+	dec_i0_predict_p_d,
+	i0_predict_fghr_d,
+	i0_predict_index_d,
+	i0_predict_btag_d,
+	dec_fa_error_index,
+	dec_data_en,
+	dec_ctl_en,
+	dec_pmu_instr_decoded,
+	dec_pmu_decode_stall,
+	dec_pmu_presync_stall,
+	dec_pmu_postsync_stall,
+	dec_nonblock_load_wen,
+	dec_nonblock_load_waddr,
+	dec_pause_state,
+	dec_pause_state_cg,
+	dec_div_active,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire dec_tlu_trace_disable;
+	input wire dec_debug_valid_d;
+	input wire dec_tlu_flush_extint;
+	input wire dec_tlu_force_halt;
+	output wire dec_extint_stall;
+	input wire [15:0] ifu_i0_cinst;
+	output wire [31:0] dec_i0_inst_wb;
+	output wire [31:1] dec_i0_pc_wb;
+	input wire lsu_nonblock_load_valid_m;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	input wire lsu_nonblock_load_inv_r;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	input wire lsu_nonblock_load_data_valid;
+	input wire lsu_nonblock_load_data_error;
+	input wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	input wire [3:0] dec_i0_trigger_match_d;
+	input wire dec_tlu_wr_pause_r;
+	input wire dec_tlu_pipelining_disable;
+	input wire [3:0] lsu_trigger_match_m;
+	input wire lsu_pmu_misaligned_m;
+	input wire dec_tlu_debug_stall;
+	input wire dec_tlu_flush_leak_one_r;
+	input wire dec_debug_fence_d;
+	input wire [1:0] dbg_cmd_wrdata;
+	input wire dec_i0_icaf_d;
+	input wire dec_i0_icaf_second_d;
+	input wire [1:0] dec_i0_icaf_type_d;
+	input wire dec_i0_dbecc_d;
+	input wire [50:0] dec_i0_brp;
+	input wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index;
+	input wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr;
+	input wire [pt[2139-:9] - 1:0] dec_i0_bp_btag;
+	input wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index;
+	input wire lsu_idle_any;
+	input wire lsu_load_stall_any;
+	input wire lsu_store_stall_any;
+	input wire dma_dccm_stall_any;
+	input wire exu_div_wren;
+	input wire dec_tlu_i0_kill_writeb_wb;
+	input wire dec_tlu_flush_lower_wb;
+	input wire dec_tlu_i0_kill_writeb_r;
+	input wire dec_tlu_flush_lower_r;
+	input wire dec_tlu_flush_pause_r;
+	input wire dec_tlu_presync_d;
+	input wire dec_tlu_postsync_d;
+	input wire dec_i0_pc4_d;
+	input wire [31:0] dec_csr_rddata_d;
+	input wire dec_csr_legal_d;
+	input wire [31:0] exu_csr_rs1_x;
+	input wire [31:0] lsu_result_m;
+	input wire [31:0] lsu_result_corr_r;
+	input wire exu_flush_final;
+	input wire [31:1] exu_i0_pc_x;
+	input wire [31:0] dec_i0_instr_d;
+	input wire dec_ib0_valid_d;
+	input wire [31:0] exu_i0_result_x;
+	input wire clk;
+	input wire active_clk;
+	input wire free_l2clk;
+	input wire clk_override;
+	input wire rst_l;
+	output wire dec_i0_rs1_en_d;
+	output wire dec_i0_rs2_en_d;
+	output wire [4:0] dec_i0_rs1_d;
+	output wire [4:0] dec_i0_rs2_d;
+	output wire [31:0] dec_i0_immed_d;
+	output wire [12:1] dec_i0_br_immed_d;
+	output wire [43:0] i0_ap;
+	output wire dec_i0_decode_d;
+	output wire dec_i0_alu_decode_d;
+	output wire dec_i0_branch_d;
+	output wire [4:0] dec_i0_waddr_r;
+	output wire dec_i0_wen_r;
+	output wire [31:0] dec_i0_wdata_r;
+	output wire dec_i0_select_pc_d;
+	output wire [3:0] dec_i0_rs1_bypass_en_d;
+	output wire [3:0] dec_i0_rs2_bypass_en_d;
+	output wire [31:0] dec_i0_result_r;
+	output reg [13:0] lsu_p;
+	output wire dec_qual_lsu_d;
+	output wire [19:0] mul_p;
+	output wire [2:0] div_p;
+	output wire [4:0] div_waddr_wb;
+	output wire dec_div_cancel;
+	output wire dec_lsu_valid_raw_d;
+	output wire [11:0] dec_lsu_offset_d;
+	output wire dec_csr_ren_d;
+	output wire dec_csr_wen_unq_d;
+	output wire dec_csr_any_unq_d;
+	output wire [11:0] dec_csr_rdaddr_d;
+	output wire dec_csr_wen_r;
+	output wire [11:0] dec_csr_wraddr_r;
+	output wire [31:0] dec_csr_wrdata_r;
+	output wire dec_csr_stall_int_ff;
+	output dec_tlu_i0_valid_r;
+	output reg [16:0] dec_tlu_packet_r;
+	output wire [31:1] dec_tlu_i0_pc_r;
+	output wire [31:0] dec_illegal_inst;
+	output wire [31:1] pred_correct_npc_x;
+	output reg [55:0] dec_i0_predict_p_d;
+	output wire [pt[2236-:8] - 1:0] i0_predict_fghr_d;
+	output wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d;
+	output wire [pt[2139-:9] - 1:0] i0_predict_btag_d;
+	output wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index;
+	output wire [1:0] dec_data_en;
+	output wire [1:0] dec_ctl_en;
+	output wire dec_pmu_instr_decoded;
+	output wire dec_pmu_decode_stall;
+	output wire dec_pmu_presync_stall;
+	output wire dec_pmu_postsync_stall;
+	output wire dec_nonblock_load_wen;
+	output reg [4:0] dec_nonblock_load_waddr;
+	output wire dec_pause_state;
+	output wire dec_pause_state_cg;
+	output wire dec_div_active;
+	input wire scan_mode;
+	wire [94:0] i0_dp_raw;
+	reg [94:0] i0_dp;
+	wire [31:0] i0;
+	wire i0_valid_d;
+	wire [31:0] i0_result_r;
+	wire [2:0] i0_rs1bypass;
+	wire [2:0] i0_rs2bypass;
+	wire i0_jalimm20;
+	wire i0_uiimm20;
+	wire lsu_decode_d;
+	wire [31:0] i0_immed_d;
+	wire i0_presync;
+	wire i0_postsync;
+	wire postsync_stall;
+	wire ps_stall;
+	wire prior_inflight;
+	wire prior_inflight_wb;
+	wire csr_clr_d;
+	wire csr_set_d;
+	wire csr_write_d;
+	wire csr_clr_x;
+	wire csr_set_x;
+	wire csr_write_x;
+	wire csr_imm_x;
+	wire [31:0] csr_mask_x;
+	wire [31:0] write_csr_data_x;
+	wire [31:0] write_csr_data_in;
+	wire [31:0] write_csr_data;
+	wire csr_data_wen;
+	wire [4:0] csrimm_x;
+	wire [31:0] csr_rddata_x;
+	wire mul_decode_d;
+	wire div_decode_d;
+	wire div_e1_to_r;
+	wire div_flush;
+	wire div_active_in;
+	wire div_active;
+	wire i0_nonblock_div_stall;
+	wire i0_div_prior_div_stall;
+	wire nonblock_div_cancel;
+	wire i0_legal;
+	wire shift_illegal;
+	wire illegal_inst_en;
+	wire illegal_lockout_in;
+	wire illegal_lockout;
+	wire i0_legal_decode_d;
+	wire i0_exulegal_decode_d;
+	wire i0_exudecode_d;
+	wire i0_exublock_d;
+	wire [12:1] last_br_immed_d;
+	wire i0_rs1_depend_i0_x;
+	wire i0_rs1_depend_i0_r;
+	wire i0_rs2_depend_i0_x;
+	wire i0_rs2_depend_i0_r;
+	wire i0_div_decode_d;
+	wire i0_load_block_d;
+	wire [1:0] i0_rs1_depth_d;
+	wire [1:0] i0_rs2_depth_d;
+	wire i0_load_stall_d;
+	wire i0_store_stall_d;
+	wire i0_predict_nt;
+	wire i0_predict_t;
+	wire i0_notbr_error;
+	wire i0_br_toffset_error;
+	wire i0_ret_error;
+	wire i0_br_error;
+	wire i0_br_error_all;
+	wire [11:0] i0_br_offset;
+	wire [20:1] i0_pcall_imm;
+	wire i0_pcall_12b_offset;
+	wire i0_pcall_raw;
+	wire i0_pcall_case;
+	wire i0_pcall;
+	wire i0_pja_raw;
+	wire i0_pja_case;
+	wire i0_pja;
+	wire i0_pret_case;
+	wire i0_pret_raw;
+	wire i0_pret;
+	wire i0_jal;
+	wire i0_predict_br;
+	wire store_data_bypass_d;
+	wire store_data_bypass_m;
+	wire [2:0] i0_rs1_class_d;
+	wire [2:0] i0_rs2_class_d;
+	wire [2:0] i0_d_c;
+	wire [2:0] i0_x_c;
+	wire [2:0] i0_r_c;
+	wire i0_ap_pc2;
+	wire i0_ap_pc4;
+	wire i0_rd_en_d;
+	wire load_ldst_bypass_d;
+	wire leak1_i0_stall_in;
+	wire leak1_i0_stall;
+	wire leak1_i1_stall_in;
+	wire leak1_i1_stall;
+	wire leak1_mode;
+	wire i0_csr_write_only_d;
+	wire prior_inflight_x;
+	wire prior_inflight_eff;
+	wire any_csr_d;
+	wire prior_csr_write;
+	wire [3:0] i0_pipe_en;
+	wire i0_r_ctl_en;
+	wire i0_x_ctl_en;
+	wire i0_wb_ctl_en;
+	wire i0_x_data_en;
+	wire i0_r_data_en;
+	wire i0_wb_data_en;
+	wire debug_fence_i;
+	wire debug_fence;
+	wire i0_csr_write;
+	wire presync_stall;
+	wire i0_instr_error;
+	wire i0_icaf_d;
+	wire clear_pause;
+	wire pause_state_in;
+	wire pause_state;
+	wire pause_stall;
+	wire i0_brp_valid;
+	wire nonblock_load_cancel;
+	wire lsu_idle;
+	wire lsu_pmu_misaligned_r;
+	wire csr_ren_qual_d;
+	wire csr_read_x;
+	wire i0_block_d;
+	wire i0_block_raw_d;
+	wire ps_stall_in;
+	wire [31:0] i0_result_x;
+	wire [23:0] d_d;
+	wire [23:0] x_d;
+	wire [23:0] r_d;
+	wire [23:0] wbd;
+	reg [23:0] x_d_in;
+	reg [23:0] r_d_in;
+	wire [16:0] d_t;
+	wire [16:0] x_t;
+	reg [16:0] x_t_in;
+	reg [16:0] r_t_in;
+	wire [16:0] r_t;
+	wire [3:0] lsu_trigger_match_r;
+	wire [31:1] dec_i0_pc_r;
+	wire csr_read;
+	wire csr_write;
+	wire i0_br_unpred;
+	wire nonblock_load_valid_m_delay;
+	wire i0_wen_r;
+	wire tlu_wr_pause_r1;
+	wire tlu_wr_pause_r2;
+	wire flush_final_r;
+	wire bitmanip_zbb_legal;
+	wire bitmanip_zbs_legal;
+	wire bitmanip_zbe_legal;
+	wire bitmanip_zbc_legal;
+	wire bitmanip_zbp_legal;
+	wire bitmanip_zbr_legal;
+	wire bitmanip_zbf_legal;
+	wire bitmanip_zba_legal;
+	wire bitmanip_zbb_zbp_legal;
+	wire bitmanip_legal;
+	wire data_gate_en;
+	wire data_gate_clk;
+	localparam NBLOAD_SIZE = pt[173-:9];
+	function automatic signed [31:0] sv2v_cast_32_signed;
+		input reg signed [31:0] inp;
+		sv2v_cast_32_signed = inp;
+	endfunction
+	localparam NBLOAD_SIZE_MSB = sv2v_cast_32_signed(pt[173-:9]) - 1;
+	localparam NBLOAD_TAG_MSB = pt[164-:7] - 1;
+	wire cam_write;
+	wire cam_inv_reset;
+	wire cam_data_reset;
+	wire [NBLOAD_TAG_MSB:0] cam_write_tag;
+	wire [NBLOAD_TAG_MSB:0] cam_inv_reset_tag;
+	wire [NBLOAD_TAG_MSB:0] cam_data_reset_tag;
+	reg [NBLOAD_SIZE_MSB:0] cam_wen;
+	wire [NBLOAD_TAG_MSB:0] load_data_tag;
+	wire [NBLOAD_SIZE_MSB:0] nonblock_load_write;
+	reg [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam;
+	reg [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam_in;
+	wire [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam_raw;
+	wire [4:0] nonblock_load_rd;
+	reg i0_nonblock_load_stall;
+	wire i0_nonblock_boundary_stall;
+	wire i0_rs1_nonblock_load_bypass_en_d;
+	wire i0_rs2_nonblock_load_bypass_en_d;
+	wire i0_load_kill_wen_r;
+	reg found;
+	wire [NBLOAD_SIZE_MSB:0] cam_inv_reset_val;
+	wire [NBLOAD_SIZE_MSB:0] cam_data_reset_val;
+	wire debug_fence_raw;
+	wire [31:0] i0_result_r_raw;
+	wire [31:0] i0_result_corr_r;
+	wire [12:1] last_br_immed_x;
+	wire [31:0] i0_inst_d;
+	wire [31:0] i0_inst_x;
+	wire [31:0] i0_inst_r;
+	wire [31:0] i0_inst_wb_in;
+	wire [31:0] i0_inst_wb;
+	wire [31:1] i0_pc_wb;
+	wire i0_wb_en;
+	wire trace_enable;
+	wire debug_valid_x;
+	reg [3:0] i0_itype;
+	wire [14:0] i0r;
+	rvdffie #(.WIDTH(8)) misc1ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({leak1_i1_stall_in, leak1_i0_stall_in, dec_tlu_flush_extint, pause_state_in, dec_tlu_wr_pause_r, tlu_wr_pause_r1, illegal_lockout_in, ps_stall_in}),
+		.dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1, tlu_wr_pause_r2, illegal_lockout, ps_stall})
+	);
+	rvdffie #(.WIDTH(8)) misc2ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({lsu_trigger_match_m[3:0], lsu_pmu_misaligned_m, div_active_in, exu_flush_final, dec_debug_valid_d}),
+		.dout({lsu_trigger_match_r[3:0], lsu_pmu_misaligned_r, div_active, flush_final_r, debug_valid_x})
+	);
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign i0_brp_valid = (dec_i0_brp[50] & ~leak1_mode) & ~i0_icaf_d;
+			wire [1:1] sv2v_tmp_123E1;
+			assign sv2v_tmp_123E1 = 1'b0;
+			always @(*) dec_i0_predict_p_d[55] = sv2v_tmp_123E1;
+			wire [1:1] sv2v_tmp_D766F;
+			assign sv2v_tmp_D766F = 1'b0;
+			always @(*) dec_i0_predict_p_d[54] = sv2v_tmp_D766F;
+			wire [1:1] sv2v_tmp_EE665;
+			assign sv2v_tmp_EE665 = 1'b0;
+			always @(*) dec_i0_predict_p_d[53] = sv2v_tmp_EE665;
+			wire [1:1] sv2v_tmp_4A5D3;
+			assign sv2v_tmp_4A5D3 = i0_pcall;
+			always @(*) dec_i0_predict_p_d[34] = sv2v_tmp_4A5D3;
+			wire [1:1] sv2v_tmp_C4472;
+			assign sv2v_tmp_C4472 = i0_pja;
+			always @(*) dec_i0_predict_p_d[33] = sv2v_tmp_C4472;
+			wire [1:1] sv2v_tmp_BC36C;
+			assign sv2v_tmp_BC36C = i0_pret;
+			always @(*) dec_i0_predict_p_d[31] = sv2v_tmp_BC36C;
+			wire [31:1] sv2v_tmp_16255;
+			assign sv2v_tmp_16255 = dec_i0_brp[32:2];
+			always @(*) dec_i0_predict_p_d[30:0] = sv2v_tmp_16255;
+			wire [1:1] sv2v_tmp_CF546;
+			assign sv2v_tmp_CF546 = dec_i0_pc4_d;
+			always @(*) dec_i0_predict_p_d[52] = sv2v_tmp_CF546;
+			wire [2:1] sv2v_tmp_1B1F0;
+			assign sv2v_tmp_1B1F0 = dec_i0_brp[37:36];
+			always @(*) dec_i0_predict_p_d[51:50] = sv2v_tmp_1B1F0;
+			wire [1:1] sv2v_tmp_3FDDA;
+			assign sv2v_tmp_3FDDA = i0_brp_valid & i0_legal_decode_d;
+			always @(*) dec_i0_predict_p_d[37] = sv2v_tmp_3FDDA;
+			assign i0_notbr_error = i0_brp_valid & ~(((i0_dp_raw[28] | i0_pcall_raw) | i0_pja_raw) | i0_pret_raw);
+			assign i0_br_toffset_error = ((i0_brp_valid & dec_i0_brp[37]) & (dec_i0_brp[49:38] != i0_br_offset[11:0])) & ~i0_pret_raw;
+			assign i0_ret_error = i0_brp_valid & (dec_i0_brp[0] ^ i0_pret_raw);
+			assign i0_br_error = ((dec_i0_brp[35] | i0_notbr_error) | i0_br_toffset_error) | i0_ret_error;
+			wire [1:1] sv2v_tmp_75A7E;
+			assign sv2v_tmp_75A7E = (i0_br_error & i0_legal_decode_d) & ~leak1_mode;
+			always @(*) dec_i0_predict_p_d[36] = sv2v_tmp_75A7E;
+			wire [1:1] sv2v_tmp_6E7A2;
+			assign sv2v_tmp_6E7A2 = (dec_i0_brp[34] & i0_legal_decode_d) & ~leak1_mode;
+			always @(*) dec_i0_predict_p_d[35] = sv2v_tmp_6E7A2;
+			assign i0_predict_index_d[pt[2172-:9]:pt[2163-:6]] = dec_i0_bp_index;
+			assign i0_predict_btag_d[pt[2139-:9] - 1:0] = dec_i0_bp_btag[pt[2139-:9] - 1:0];
+			assign i0_br_error_all = (i0_br_error | dec_i0_brp[34]) & ~leak1_mode;
+			wire [12:1] sv2v_tmp_AC6BD;
+			assign sv2v_tmp_AC6BD = i0_br_offset[11:0];
+			always @(*) dec_i0_predict_p_d[49:38] = sv2v_tmp_AC6BD;
+			assign i0_predict_fghr_d[pt[2236-:8] - 1:0] = dec_i0_bp_fghr[pt[2236-:8] - 1:0];
+			wire [1:1] sv2v_tmp_11732;
+			assign sv2v_tmp_11732 = dec_i0_brp[1];
+			always @(*) dec_i0_predict_p_d[32] = sv2v_tmp_11732;
+			if (pt[2120-:5]) begin
+				wire btb_error_found;
+				wire btb_error_found_f;
+				wire [$clog2(pt[2061-:14]) - 1:0] fa_error_index_ns;
+				assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r;
+				assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f ? dec_i0_bp_fa_index : dec_fa_error_index);
+				rvdff #(.WIDTH($clog2(pt[2061-:14]) + 1)) btberrorfa_f(
+					.rst_l(rst_l),
+					.clk(active_clk),
+					.din({btb_error_found, fa_error_index_ns}),
+					.dout({btb_error_found_f, dec_fa_error_index})
+				);
+			end
+			else assign dec_fa_error_index = 'b0;
+		end
+		else begin
+			always @(*) begin
+				dec_i0_predict_p_d = {56 {1'sb0}};
+				dec_i0_predict_p_d[34] = i0_pcall;
+				dec_i0_predict_p_d[33] = i0_pja;
+				dec_i0_predict_p_d[31] = i0_pret;
+				dec_i0_predict_p_d[52] = dec_i0_pc4_d;
+			end
+			assign i0_br_error_all = 1'b0;
+			assign i0_predict_index_d = {(pt[2172-:9] >= pt[2163-:6] ? (pt[2172-:9] - pt[2163-:6]) + 1 : (pt[2163-:6] - pt[2172-:9]) + 1) {1'sb0}};
+			assign i0_predict_btag_d = {pt[2139-:9] {1'sb0}};
+			assign i0_predict_fghr_d = {pt[2236-:8] {1'sb0}};
+			assign i0_brp_valid = 1'b0;
+		end
+	endgenerate
+	assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d;
+	assign i0_instr_error = i0_icaf_d;
+	always @(*) begin
+		i0_dp = i0_dp_raw;
+		if (i0_br_error_all | i0_instr_error) begin
+			i0_dp = {95 {1'sb0}};
+			i0_dp[49] = 1'b1;
+			i0_dp[48] = 1'b1;
+			i0_dp[47] = 1'b1;
+			i0_dp[35] = 1'b1;
+			i0_dp[0] = 1'b1;
+			i0_dp[13] = 1'b1;
+		end
+	end
+	assign i0[31:0] = dec_i0_instr_d[31:0];
+	assign dec_i0_select_pc_d = i0_dp[42];
+	assign i0_predict_br = ((i0_dp[28] | i0_pcall) | i0_pja) | i0_pret;
+	assign i0_predict_nt = ~(dec_i0_brp[37] & i0_brp_valid) & i0_predict_br;
+	assign i0_predict_t = (dec_i0_brp[37] & i0_brp_valid) & i0_predict_br;
+	assign i0_ap[8] = i0_dp[38];
+	assign i0_ap[7] = i0_dp[37];
+	assign i0_ap[18] = i0_dp[36];
+	assign i0_ap[17] = i0_dp[35];
+	assign i0_ap[16] = i0_dp[34];
+	assign i0_ap[15] = i0_dp[33];
+	assign i0_ap[14] = i0_dp[31];
+	assign i0_ap[13] = i0_dp[32];
+	assign i0_ap[6] = i0_dp[30];
+	assign i0_ap[5] = i0_dp[29];
+	assign i0_ap[12] = i0_dp[27];
+	assign i0_ap[11] = i0_dp[26];
+	assign i0_ap[10] = i0_dp[24];
+	assign i0_ap[9] = i0_dp[25];
+	assign i0_ap[43] = i0_dp[94];
+	assign i0_ap[42] = i0_dp[93];
+	assign i0_ap[41] = i0_dp[92];
+	assign i0_ap[40] = i0_dp[91];
+	assign i0_ap[39] = i0_dp[90];
+	assign i0_ap[22] = i0_dp[53];
+	assign i0_ap[21] = i0_dp[52];
+	assign i0_ap[20] = i0_dp[51];
+	assign i0_ap[19] = i0_dp[50];
+	assign i0_ap[38] = i0_dp[89];
+	assign i0_ap[37] = i0_dp[88];
+	assign i0_ap[36] = i0_dp[87];
+	assign i0_ap[35] = i0_dp[86];
+	assign i0_ap[34] = i0_dp[85];
+	assign i0_ap[33] = i0_dp[84];
+	assign i0_ap[32] = i0_dp[83];
+	assign i0_ap[31] = i0_dp[82];
+	assign i0_ap[30] = i0_dp[81];
+	assign i0_ap[29] = i0_dp[80];
+	assign i0_ap[28] = i0_dp[79];
+	assign i0_ap[27] = i0_dp[78];
+	assign i0_ap[26] = i0_dp[77];
+	assign i0_ap[25] = i0_dp[76];
+	assign i0_ap[24] = i0_dp[75];
+	assign i0_ap[23] = i0_dp[74];
+	assign i0_ap[1] = i0_csr_write_only_d;
+	assign i0_ap[0] = i0_dp[15];
+	assign i0_ap[4] = i0_jal;
+	assign i0_ap_pc2 = ~dec_i0_pc4_d;
+	assign i0_ap_pc4 = dec_i0_pc4_d;
+	assign i0_ap[2] = i0_predict_nt;
+	assign i0_ap[3] = i0_predict_t;
+	always @(*) begin
+		found = 0;
+		cam_wen[NBLOAD_SIZE_MSB:0] = {(NBLOAD_SIZE_MSB >= 0 ? NBLOAD_SIZE_MSB + 1 : 1 - NBLOAD_SIZE_MSB) {1'sb0}};
+		begin : sv2v_autoblock_37
+			reg signed [31:0] i;
+			for (i = 0; i < NBLOAD_SIZE; i = i + 1)
+				if (~found) begin
+					if (~cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) begin
+						cam_wen[i] = cam_write;
+						found = 1'b1;
+					end
+					else
+						cam_wen[i] = 0;
+				end
+				else
+					cam_wen[i] = 0;
+		end
+	end
+	assign cam_write = lsu_nonblock_load_valid_m;
+	assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0];
+	assign cam_inv_reset = lsu_nonblock_load_inv_r;
+	assign cam_inv_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0];
+	assign cam_data_reset = lsu_nonblock_load_data_valid | lsu_nonblock_load_data_error;
+	assign cam_data_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
+	assign nonblock_load_rd[4:0] = (x_d[3] ? x_d[8:4] : 5'b00000);
+	generate
+		genvar i;
+		for (i = 0; i < NBLOAD_SIZE; i = i + 1) begin : cam_array
+			assign cam_inv_reset_val[i] = (cam_inv_reset & (cam_inv_reset_tag[NBLOAD_TAG_MSB:0] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9];
+			assign cam_data_reset_val[i] = (cam_data_reset & (cam_data_reset_tag[NBLOAD_TAG_MSB:0] == cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9];
+			always @(*) begin
+				cam[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = cam_raw[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10];
+				if (cam_data_reset_val[i])
+					cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0;
+				cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = {10 {1'sb0}};
+				if (cam_wen[i]) begin
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b1;
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8] = 1'b0;
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))] = cam_write_tag[NBLOAD_TAG_MSB:0];
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] = nonblock_load_rd[4:0];
+				end
+				else if (cam_inv_reset_val[i] | ((i0_wen_r & (r_d_in[8:4] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8]))
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0;
+				else
+					cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = cam[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10];
+				if ((nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9])
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8] = 1'b1;
+				if (dec_tlu_force_halt)
+					cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0;
+			end
+			rvdffie #(.WIDTH(10)) cam_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10]),
+				.dout(cam_raw[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10])
+			);
+			assign nonblock_load_write[i] = (load_data_tag[NBLOAD_TAG_MSB:0] == cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))]) & cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9];
+		end
+	endgenerate
+	assign load_data_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
+	assign nonblock_load_cancel = (r_d_in[8:4] == dec_nonblock_load_waddr[4:0]) & i0_wen_r;
+	assign dec_nonblock_load_wen = (lsu_nonblock_load_data_valid & |nonblock_load_write[NBLOAD_SIZE_MSB:0]) & ~nonblock_load_cancel;
+	always @(*) begin
+		dec_nonblock_load_waddr[4:0] = {5 {1'sb0}};
+		i0_nonblock_load_stall = i0_nonblock_boundary_stall;
+		begin : sv2v_autoblock_38
+			reg signed [31:0] i;
+			for (i = 0; i < NBLOAD_SIZE; i = i + 1)
+				begin
+					dec_nonblock_load_waddr[4:0] = dec_nonblock_load_waddr[4:0] | ({5 {nonblock_load_write[i]}} & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5]);
+					i0_nonblock_load_stall = i0_nonblock_load_stall | ((dec_i0_rs1_en_d & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) & (cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] == i0r[14:10]));
+					i0_nonblock_load_stall = i0_nonblock_load_stall | ((dec_i0_rs2_en_d & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) & (cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] == i0r[9:5]));
+				end
+		end
+	end
+	assign i0_nonblock_boundary_stall = (((nonblock_load_rd[4:0] == i0r[14:10]) & lsu_nonblock_load_valid_m) & dec_i0_rs1_en_d) | (((nonblock_load_rd[4:0] == i0r[9:5]) & lsu_nonblock_load_valid_m) & dec_i0_rs2_en_d);
+	rvdffs #(.WIDTH(1)) wbnbloaddelayff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(i0_r_ctl_en),
+		.din(lsu_nonblock_load_valid_m),
+		.dout(nonblock_load_valid_m_delay)
+	);
+	assign i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d[3];
+	assign csr_read = csr_ren_qual_d;
+	assign csr_write = dec_csr_wen_unq_d;
+	assign i0_br_unpred = i0_dp[23] & ~i0_predict_br;
+	localparam [3:0] eb1_pkg_ALU = 4'b0100;
+	localparam [3:0] eb1_pkg_BITMANIPU = 4'b1111;
+	localparam [3:0] eb1_pkg_CONDBR = 4'b1101;
+	localparam [3:0] eb1_pkg_CSRREAD = 4'b0101;
+	localparam [3:0] eb1_pkg_CSRRW = 4'b0111;
+	localparam [3:0] eb1_pkg_CSRWRITE = 4'b0110;
+	localparam [3:0] eb1_pkg_EBREAK = 4'b1000;
+	localparam [3:0] eb1_pkg_ECALL = 4'b1001;
+	localparam [3:0] eb1_pkg_FENCE = 4'b1010;
+	localparam [3:0] eb1_pkg_FENCEI = 4'b1011;
+	localparam [3:0] eb1_pkg_JAL = 4'b1110;
+	localparam [3:0] eb1_pkg_LOAD = 4'b0010;
+	localparam [3:0] eb1_pkg_MRET = 4'b1100;
+	localparam [3:0] eb1_pkg_MUL = 4'b0001;
+	localparam [3:0] eb1_pkg_NULL = 4'b0000;
+	localparam [3:0] eb1_pkg_STORE = 4'b0011;
+	always @(*) begin
+		i0_itype = eb1_pkg_NULL;
+		if (i0_legal_decode_d) begin
+			if (i0_dp[9])
+				i0_itype = eb1_pkg_MUL;
+			if (i0_dp[41])
+				i0_itype = eb1_pkg_LOAD;
+			if (i0_dp[40])
+				i0_itype = eb1_pkg_STORE;
+			if (i0_dp[1])
+				i0_itype = eb1_pkg_ALU;
+			if (((((((i0_dp[78] | i0_dp[73]) | i0_dp[70]) | i0_dp[66]) | i0_dp[63]) | i0_dp[56]) | i0_dp[54]) | i0_dp[50])
+				i0_itype = eb1_pkg_BITMANIPU;
+			if (csr_read & ~csr_write)
+				i0_itype = eb1_pkg_CSRREAD;
+			if (~csr_read & csr_write)
+				i0_itype = eb1_pkg_CSRWRITE;
+			if (csr_read & csr_write)
+				i0_itype = eb1_pkg_CSRRW;
+			if (i0_dp[12])
+				i0_itype = eb1_pkg_EBREAK;
+			if (i0_dp[11])
+				i0_itype = eb1_pkg_ECALL;
+			if (i0_dp[3])
+				i0_itype = eb1_pkg_FENCE;
+			if (i0_dp[2])
+				i0_itype = eb1_pkg_FENCEI;
+			if (i0_dp[10])
+				i0_itype = eb1_pkg_MRET;
+			if (i0_dp[28])
+				i0_itype = eb1_pkg_CONDBR;
+			if (i0_dp[23])
+				i0_itype = eb1_pkg_JAL;
+		end
+	end
+	eb1_dec_dec_ctl i0_dec(
+		.inst(i0[31:0]),
+		.out(i0_dp_raw)
+	);
+	rvdff #(.WIDTH(1)) lsu_idle_ff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din(lsu_idle_any),
+		.dout(lsu_idle)
+	);
+	assign leak1_i1_stall_in = dec_tlu_flush_leak_one_r | (leak1_i1_stall & ~dec_tlu_flush_lower_r);
+	assign leak1_mode = leak1_i1_stall;
+	assign leak1_i0_stall_in = (dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & ~dec_tlu_flush_lower_r);
+	assign i0_pcall_imm[20:1] = {i0[31], i0[19:12], i0[20], i0[30:21]};
+	assign i0_pcall_12b_offset = (i0_pcall_imm[12] ? i0_pcall_imm[20:13] == 8'hff : i0_pcall_imm[20:13] == 8'h00);
+	assign i0_pcall_case = (i0_pcall_12b_offset & i0_dp_raw[43]) & ((i0r[4:0] == 5'd1) | (i0r[4:0] == 5'd5));
+	assign i0_pja_case = (i0_pcall_12b_offset & i0_dp_raw[43]) & ~((i0r[4:0] == 5'd1) | (i0r[4:0] == 5'd5));
+	assign i0_pcall_raw = i0_dp_raw[23] & i0_pcall_case;
+	assign i0_pcall = i0_dp[23] & i0_pcall_case;
+	assign i0_pja_raw = i0_dp_raw[23] & i0_pja_case;
+	assign i0_pja = i0_dp[23] & i0_pja_case;
+	assign i0_br_offset[11:0] = (i0_pcall_raw | i0_pja_raw ? i0_pcall_imm[12:1] : {i0[31], i0[7], i0[30:25], i0[11:8]});
+	assign i0_pret_case = ((i0_dp_raw[23] & i0_dp_raw[46]) & (i0r[4:0] == 5'b00000)) & ((i0r[14:10] == 5'd1) | (i0r[14:10] == 5'd5));
+	assign i0_pret_raw = i0_dp_raw[23] & i0_pret_case;
+	assign i0_pret = i0_dp[23] & i0_pret_case;
+	assign i0_jal = ((i0_dp[23] & ~i0_pcall_case) & ~i0_pja_case) & ~i0_pret_case;
+	assign dec_lsu_offset_d[11:0] = ({12 {(~dec_extint_stall & i0_dp[39]) & i0_dp[41]}} & i0[31:20]) | ({12 {(~dec_extint_stall & i0_dp[39]) & i0_dp[40]}} & {i0[31:25], i0[11:7]});
+	assign div_p[2] = div_decode_d;
+	assign div_p[1] = i0_dp[29];
+	assign div_p[0] = i0_dp[4];
+	assign mul_p[19] = mul_decode_d;
+	assign mul_p[18] = i0_dp[8];
+	assign mul_p[17] = i0_dp[7];
+	assign mul_p[16] = i0_dp[6];
+	assign mul_p[15] = i0_dp[72];
+	assign mul_p[14] = i0_dp[71];
+	assign mul_p[13] = i0_dp[69];
+	assign mul_p[12] = i0_dp[68];
+	assign mul_p[11] = i0_dp[67];
+	assign mul_p[10] = i0_dp[80];
+	assign mul_p[9] = i0_dp[79];
+	assign mul_p[8] = i0_dp[65];
+	assign mul_p[7] = i0_dp[64];
+	assign mul_p[6] = i0_dp[62];
+	assign mul_p[5] = i0_dp[61];
+	assign mul_p[4] = i0_dp[60];
+	assign mul_p[3] = i0_dp[59];
+	assign mul_p[2] = i0_dp[58];
+	assign mul_p[1] = i0_dp[57];
+	assign mul_p[0] = i0_dp[55];
+	always @(*) begin
+		lsu_p = {14 {1'sb0}};
+		if (dec_extint_stall) begin
+			lsu_p[7] = 1'b1;
+			lsu_p[9] = 1'b1;
+			lsu_p[13] = 1'b1;
+			lsu_p[0] = 1'b1;
+		end
+		else begin
+			lsu_p[0] = lsu_decode_d;
+			lsu_p[7] = i0_dp[41];
+			lsu_p[6] = i0_dp[40];
+			lsu_p[11] = i0_dp[22];
+			lsu_p[10] = i0_dp[21];
+			lsu_p[9] = i0_dp[20];
+			lsu_p[12] = i0r[14:10] == 5'd2;
+			lsu_p[2] = load_ldst_bypass_d;
+			lsu_p[3] = store_data_bypass_d;
+			lsu_p[1] = store_data_bypass_m;
+			lsu_p[5] = i0_dp[29];
+		end
+	end
+	assign dec_lsu_valid_raw_d = (((i0_valid_d & (i0_dp_raw[41] | i0_dp_raw[40])) & ~dma_dccm_stall_any) & ~i0_block_raw_d) | dec_extint_stall;
+	assign i0r[14:10] = i0[19:15];
+	assign i0r[9:5] = i0[24:20];
+	assign i0r[4:0] = i0[11:7];
+	assign dec_i0_rs1_en_d = i0_dp[48] & (i0r[14:10] != 5'd0);
+	assign dec_i0_rs2_en_d = i0_dp[47] & (i0r[9:5] != 5'd0);
+	assign i0_rd_en_d = i0_dp[45] & (i0r[4:0] != 5'd0);
+	assign dec_i0_rs1_d[4:0] = i0r[14:10];
+	assign dec_i0_rs2_d[4:0] = i0r[9:5];
+	assign i0_jalimm20 = i0_dp[23] & i0_dp[43];
+	assign i0_uiimm20 = ~i0_dp[23] & i0_dp[43];
+	assign dec_csr_ren_d = i0_dp[19] & i0_valid_d;
+	assign csr_ren_qual_d = i0_dp[19] & i0_legal_decode_d;
+	assign csr_clr_d = i0_dp[18] & i0_legal_decode_d;
+	assign csr_set_d = i0_dp[17] & i0_legal_decode_d;
+	assign csr_write_d = i0_csr_write & i0_legal_decode_d;
+	assign i0_csr_write_only_d = i0_csr_write & ~i0_dp[19];
+	assign dec_csr_wen_unq_d = ((i0_dp[18] | i0_dp[17]) | i0_csr_write) & i0_valid_d;
+	assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;
+	assign dec_csr_rdaddr_d[11:0] = {12 {dec_csr_any_unq_d}} & i0[31:20];
+	assign dec_csr_wraddr_r[11:0] = {12 {r_d[22] & r_d[0]}} & r_d[20:9];
+	assign dec_csr_wen_r = (r_d[22] & r_d[0]) & ~dec_tlu_i0_kill_writeb_r;
+	assign dec_csr_stall_int_ff = ((((r_d[20:9] == 12'h300) | (r_d[20:9] == 12'h304)) & r_d[22]) & r_d[0]) & ~dec_tlu_i0_kill_writeb_wb;
+	rvdff #(.WIDTH(5)) csrmiscff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din({csr_ren_qual_d, csr_clr_d, csr_set_d, csr_write_d, i0_dp[15]}),
+		.dout({csr_read_x, csr_clr_x, csr_set_x, csr_write_x, csr_imm_x})
+	);
+	rvdffe #(.WIDTH(37)) csr_rddata_x_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_data_en & any_csr_d),
+		.din({i0[19:15], dec_csr_rddata_d[31:0]}),
+		.dout({csrimm_x[4:0], csr_rddata_x[31:0]})
+	);
+	assign csr_mask_x[31:0] = ({32 {csr_imm_x}} & {27'b000000000000000000000000000, csrimm_x[4:0]}) | ({32 {~csr_imm_x}} & exu_csr_rs1_x[31:0]);
+	assign write_csr_data_x[31:0] = (({32 {csr_clr_x}} & (csr_rddata_x[31:0] & ~csr_mask_x[31:0])) | ({32 {csr_set_x}} & (csr_rddata_x[31:0] | csr_mask_x[31:0]))) | ({32 {csr_write_x}} & csr_mask_x[31:0]);
+	assign clear_pause = (dec_tlu_flush_lower_r & ~dec_tlu_flush_pause_r) | (pause_state & (write_csr_data[31:1] == 31'b0000000000000000000000000000000));
+	assign pause_state_in = (dec_tlu_wr_pause_r | pause_state) & ~clear_pause;
+	assign dec_pause_state = pause_state;
+	assign dec_pause_state_cg = (pause_state & ~tlu_wr_pause_r1) & ~tlu_wr_pause_r2;
+	assign csr_data_wen = ((((csr_clr_x | csr_set_x) | csr_write_x) & csr_read_x) | dec_tlu_wr_pause_r) | pause_state;
+	assign write_csr_data_in[31:0] = (pause_state ? write_csr_data[31:0] - 32'b00000000000000000000000000000001 : (dec_tlu_wr_pause_r ? dec_csr_wrdata_r[31:0] : write_csr_data_x[31:0]));
+	rvdffe #(.WIDTH(32)) write_csr_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(csr_data_wen),
+		.din(write_csr_data_in[31:0]),
+		.dout(write_csr_data[31:0])
+	);
+	assign pause_stall = pause_state;
+	assign dec_csr_wrdata_r[31:0] = (r_d[21] & r_d[0] ? i0_result_corr_r[31:0] : write_csr_data[31:0]);
+	assign dec_i0_immed_d[31:0] = i0_immed_d[31:0];
+	assign i0_immed_d[31:0] = (((({32 {i0_dp[46]}} & {{20 {i0[31]}}, i0[31:20]}) | ({32 {i0_dp[44]}} & {27'b000000000000000000000000000, i0[24:20]})) | ({32 {i0_jalimm20}} & {{12 {i0[31]}}, i0[19:12], i0[20], i0[30:21], 1'b0})) | ({32 {i0_uiimm20}} & {i0[31:12], 12'b000000000000})) | ({32 {i0_csr_write_only_d & i0_dp[15]}} & {27'b000000000000000000000000000, i0[19:15]});
+	assign dec_i0_br_immed_d[12:1] = (i0_ap[2] & ~i0_dp[23] ? i0_br_offset[11:0] : {10'b0000000000, i0_ap_pc4, i0_ap_pc2});
+	assign last_br_immed_d[12:1] = (i0_ap[2] ? {10'b0000000000, i0_ap_pc4, i0_ap_pc2} : i0_br_offset[11:0]);
+	assign i0_valid_d = dec_ib0_valid_d;
+	assign i0_load_stall_d = i0_dp[41] & (lsu_load_stall_any | dma_dccm_stall_any);
+	assign i0_store_stall_d = i0_dp[40] & (lsu_store_stall_any | dma_dccm_stall_any);
+	assign i0_presync = (((i0_dp[14] | dec_tlu_presync_d) | debug_fence_i) | debug_fence_raw) | dec_tlu_pipelining_disable;
+	assign i0_postsync = ((i0_dp[13] | dec_tlu_postsync_d) | debug_fence_i) | (i0_csr_write_only_d & (i0[31:20] == 12'h7c2));
+	assign debug_fence_i = dec_debug_fence_d & dbg_cmd_wrdata[0];
+	assign debug_fence_raw = dec_debug_fence_d & dbg_cmd_wrdata[1];
+	assign debug_fence = debug_fence_raw | debug_fence_i;
+	assign i0_csr_write = i0_dp[16] & ~dec_debug_fence_d;
+	assign presync_stall = i0_presync & prior_inflight_eff;
+	assign prior_inflight_eff = (i0_dp[5] ? prior_inflight_x : prior_inflight);
+	assign i0_div_prior_div_stall = i0_dp[5] & div_active;
+	assign i0_block_raw_d = (((((((((((i0_dp[19] & prior_csr_write) | dec_extint_stall) | pause_stall) | leak1_i0_stall) | dec_tlu_debug_stall) | postsync_stall) | presync_stall) | ((i0_dp[3] | debug_fence) & ~lsu_idle)) | i0_nonblock_load_stall) | i0_load_block_d) | i0_nonblock_div_stall) | i0_div_prior_div_stall;
+	assign i0_block_d = (i0_block_raw_d | i0_store_stall_d) | i0_load_stall_d;
+	assign i0_exublock_d = i0_block_raw_d;
+	assign prior_csr_write = (x_d[21] | r_d[21]) | wbd[21];
+	generate
+		if (pt[2207-:5] == 1) begin
+			assign bitmanip_zbb_legal = 1'b1;
+		end
+		else assign bitmanip_zbb_legal = ~(i0_dp[78] & ~i0_dp[63]);
+	endgenerate
+	generate
+		if (pt[2177-:5] == 1) begin
+			assign bitmanip_zbs_legal = 1'b1;
+		end
+		else assign bitmanip_zbs_legal = ~i0_dp[73];
+	endgenerate
+	generate
+		if (pt[2197-:5] == 1) begin
+			assign bitmanip_zbe_legal = 1'b1;
+		end
+		else assign bitmanip_zbe_legal = ~i0_dp[70];
+	endgenerate
+	generate
+		if (pt[2202-:5] == 1) begin
+			assign bitmanip_zbc_legal = 1'b1;
+		end
+		else assign bitmanip_zbc_legal = ~i0_dp[66];
+	endgenerate
+	generate
+		if (pt[2187-:5] == 1) begin
+			assign bitmanip_zbp_legal = 1'b1;
+		end
+		else assign bitmanip_zbp_legal = ~(i0_dp[63] & ~i0_dp[78]);
+	endgenerate
+	generate
+		if (pt[2182-:5] == 1) begin
+			assign bitmanip_zbr_legal = 1'b1;
+		end
+		else assign bitmanip_zbr_legal = ~i0_dp[56];
+	endgenerate
+	generate
+		if (pt[2192-:5] == 1) begin
+			assign bitmanip_zbf_legal = 1'b1;
+		end
+		else assign bitmanip_zbf_legal = ~i0_dp[54];
+	endgenerate
+	generate
+		if (pt[2212-:5] == 1) begin
+			assign bitmanip_zba_legal = 1'b1;
+		end
+		else assign bitmanip_zba_legal = ~i0_dp[50];
+	endgenerate
+	generate
+		if ((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) begin
+			assign bitmanip_zbb_zbp_legal = 1'b1;
+		end
+		else assign bitmanip_zbb_zbp_legal = ~(i0_dp[78] & i0_dp[63]);
+	endgenerate
+	assign any_csr_d = i0_dp[19] | i0_csr_write;
+	assign bitmanip_legal = (((((((bitmanip_zbb_legal & bitmanip_zbs_legal) & bitmanip_zbe_legal) & bitmanip_zbc_legal) & bitmanip_zbp_legal) & bitmanip_zbr_legal) & bitmanip_zbf_legal) & bitmanip_zba_legal) & bitmanip_zbb_zbp_legal;
+	assign i0_legal = (i0_dp[0] & (~any_csr_d | dec_csr_legal_d)) & bitmanip_legal;
+	assign shift_illegal = dec_i0_decode_d & ~i0_legal;
+	assign illegal_inst_en = shift_illegal & ~illegal_lockout;
+	rvdffe #(.WIDTH(32)) illegal_any_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(illegal_inst_en),
+		.din(i0_inst_d[31:0]),
+		.dout(dec_illegal_inst[31:0])
+	);
+	assign illegal_lockout_in = (shift_illegal | illegal_lockout) & ~flush_final_r;
+	assign dec_i0_decode_d = ((i0_valid_d & ~i0_block_d) & ~dec_tlu_flush_lower_r) & ~flush_final_r;
+	assign i0_exudecode_d = ((i0_valid_d & ~i0_exublock_d) & ~dec_tlu_flush_lower_r) & ~flush_final_r;
+	assign i0_legal_decode_d = dec_i0_decode_d & i0_legal;
+	assign i0_exulegal_decode_d = i0_exudecode_d & i0_legal;
+	assign dec_pmu_instr_decoded = dec_i0_decode_d;
+	assign dec_pmu_decode_stall = i0_valid_d & ~dec_i0_decode_d;
+	assign dec_pmu_postsync_stall = postsync_stall & i0_valid_d;
+	assign dec_pmu_presync_stall = presync_stall & i0_valid_d;
+	assign ps_stall_in = (dec_i0_decode_d & (i0_postsync | ~i0_legal)) | (ps_stall & prior_inflight_x);
+	assign postsync_stall = ps_stall;
+	assign prior_inflight_x = x_d[0];
+	assign prior_inflight_wb = r_d[0];
+	assign prior_inflight = prior_inflight_x | prior_inflight_wb;
+	assign dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp[49];
+	assign dec_i0_branch_d = (i0_dp[28] | i0_dp[23]) | i0_br_error_all;
+	assign lsu_decode_d = i0_legal_decode_d & i0_dp[39];
+	assign mul_decode_d = i0_exulegal_decode_d & i0_dp[9];
+	assign div_decode_d = i0_exulegal_decode_d & i0_dp[5];
+	assign dec_qual_lsu_d = i0_dp[39];
+	assign i0_rs1_depend_i0_x = (dec_i0_rs1_en_d & x_d[1]) & (x_d[8:4] == i0r[14:10]);
+	assign i0_rs1_depend_i0_r = (dec_i0_rs1_en_d & r_d[1]) & (r_d[8:4] == i0r[14:10]);
+	assign i0_rs2_depend_i0_x = (dec_i0_rs2_en_d & x_d[1]) & (x_d[8:4] == i0r[9:5]);
+	assign i0_rs2_depend_i0_r = (dec_i0_rs2_en_d & r_d[1]) & (r_d[8:4] == i0r[9:5]);
+	assign {i0_rs1_class_d, i0_rs1_depth_d[1:0]} = (i0_rs1_depend_i0_x ? {i0_x_c, 2'd1} : (i0_rs1_depend_i0_r ? {i0_r_c, 2'd2} : {5 {1'sb0}}));
+	assign {i0_rs2_class_d, i0_rs2_depth_d[1:0]} = (i0_rs2_depend_i0_x ? {i0_x_c, 2'd1} : (i0_rs2_depend_i0_r ? {i0_r_c, 2'd2} : {5 {1'sb0}}));
+	generate
+		if (pt[202-:5] == 1) begin : genblock
+			assign i0_load_block_d = (i0_rs1_class_d[1] & i0_rs1_depth_d[0]) | ((i0_rs2_class_d[1] & i0_rs2_depth_d[0]) & ~i0_dp[40]);
+			assign load_ldst_bypass_d = ((i0_dp[41] | i0_dp[40]) & i0_rs1_depth_d[1]) & i0_rs1_class_d[1];
+			assign store_data_bypass_d = (i0_dp[40] & i0_rs2_depth_d[1]) & i0_rs2_class_d[1];
+			assign store_data_bypass_m = (i0_dp[40] & i0_rs2_depth_d[0]) & i0_rs2_class_d[1];
+		end
+		else begin : genblock
+			assign i0_load_block_d = 1'b0;
+			assign load_ldst_bypass_d = ((i0_dp[41] | i0_dp[40]) & i0_rs1_depth_d[0]) & i0_rs1_class_d[1];
+			assign store_data_bypass_d = (i0_dp[40] & i0_rs2_depth_d[0]) & i0_rs2_class_d[1];
+			assign store_data_bypass_m = 1'b0;
+		end
+	endgenerate
+	assign dec_tlu_i0_valid_r = r_d[0] & ~dec_tlu_flush_lower_wb;
+	assign d_t[5] = i0_legal_decode_d;
+	assign d_t[16] = i0_icaf_d & i0_legal_decode_d;
+	assign d_t[15] = dec_i0_icaf_second_d & i0_legal_decode_d;
+	assign d_t[14:13] = dec_i0_icaf_type_d[1:0];
+	assign d_t[12] = (i0_dp[2] | debug_fence_i) & i0_legal_decode_d;
+	assign d_t[3-:4] = i0_itype;
+	assign d_t[7] = i0_br_unpred;
+	assign d_t[6] = 1'b0;
+	assign d_t[4] = 1'b0;
+	assign d_t[11:8] = dec_i0_trigger_match_d[3:0] & {4 {dec_i0_decode_d}};
+	rvdfflie #(
+		.WIDTH(17),
+		.LEFT(9)
+	) trap_xff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_ctl_en),
+		.din(d_t),
+		.dout(x_t)
+	);
+	always @(*) begin
+		x_t_in = x_t;
+		x_t_in[11:8] = x_t[11-:4] & ~{4 {dec_tlu_flush_lower_wb}};
+	end
+	rvdfflie #(
+		.WIDTH(17),
+		.LEFT(9)
+	) trap_r_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_ctl_en),
+		.din(x_t_in),
+		.dout(r_t)
+	);
+	always @(*) begin
+		r_t_in = r_t;
+		r_t_in[11:8] = ({4 {r_d[3] | r_d[2]}} & lsu_trigger_match_r[3:0]) | r_t[11:8];
+		r_t_in[4] = lsu_pmu_misaligned_r;
+		if (dec_tlu_flush_lower_wb)
+			r_t_in = {17 {1'sb0}};
+	end
+	always @(*) begin
+		dec_tlu_packet_r = r_t_in;
+		dec_tlu_packet_r[6] = r_d[23] & r_d[0];
+	end
+	assign i0_d_c[2] = i0_dp[9] & i0_legal_decode_d;
+	assign i0_d_c[1] = i0_dp[41] & i0_legal_decode_d;
+	assign i0_d_c[0] = i0_dp[49] & i0_legal_decode_d;
+	rvdffs #(.WIDTH(3)) i0_x_c_ff(
+		.rst_l(rst_l),
+		.en(i0_x_ctl_en),
+		.clk(active_clk),
+		.din(i0_d_c),
+		.dout(i0_x_c)
+	);
+	rvdffs #(.WIDTH(3)) i0_r_c_ff(
+		.rst_l(rst_l),
+		.en(i0_r_ctl_en),
+		.clk(active_clk),
+		.din(i0_x_c),
+		.dout(i0_r_c)
+	);
+	assign d_d[8:4] = i0r[4:0];
+	assign d_d[1] = i0_rd_en_d & i0_legal_decode_d;
+	assign d_d[0] = dec_i0_decode_d;
+	assign d_d[3] = i0_dp[41] & i0_legal_decode_d;
+	assign d_d[2] = i0_dp[40] & i0_legal_decode_d;
+	assign d_d[23] = i0_dp[5] & i0_legal_decode_d;
+	assign d_d[22] = dec_csr_wen_unq_d & i0_legal_decode_d;
+	assign d_d[21] = i0_csr_write_only_d & dec_i0_decode_d;
+	assign d_d[20:9] = (d_d[22] ? i0[31:20] : {12 {1'sb0}});
+	rvdff #(.WIDTH(3)) i0cgff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din(i0_pipe_en[3:1]),
+		.dout(i0_pipe_en[2:0])
+	);
+	assign i0_pipe_en[3] = dec_i0_decode_d;
+	assign i0_x_ctl_en = |i0_pipe_en[3:2] | clk_override;
+	assign i0_r_ctl_en = |i0_pipe_en[2:1] | clk_override;
+	assign i0_wb_ctl_en = |i0_pipe_en[1:0] | clk_override;
+	assign i0_x_data_en = i0_pipe_en[3] | clk_override;
+	assign i0_r_data_en = i0_pipe_en[2] | clk_override;
+	assign i0_wb_data_en = i0_pipe_en[1] | clk_override;
+	assign dec_data_en[1:0] = {i0_x_data_en, i0_r_data_en};
+	assign dec_ctl_en[1:0] = {i0_x_ctl_en, i0_r_ctl_en};
+	rvdfflie #(
+		.WIDTH(24),
+		.LEFT(15)
+	) e1ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_ctl_en),
+		.din(d_d),
+		.dout(x_d)
+	);
+	always @(*) begin
+		x_d_in = x_d;
+		x_d_in[1] = (x_d[1] & ~dec_tlu_flush_lower_wb) & ~dec_tlu_flush_lower_r;
+		x_d_in[0] = (x_d[0] & ~dec_tlu_flush_lower_wb) & ~dec_tlu_flush_lower_r;
+	end
+	rvdfflie #(
+		.WIDTH(24),
+		.LEFT(15)
+	) r_d_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_r_ctl_en),
+		.din(x_d_in),
+		.dout(r_d)
+	);
+	always @(*) begin
+		r_d_in = r_d;
+		r_d_in[8:4] = r_d[8:4];
+		r_d_in[1] = r_d[1] & ~dec_tlu_flush_lower_wb;
+		r_d_in[0] = r_d[0] & ~dec_tlu_flush_lower_wb;
+		r_d_in[3] = r_d[3] & ~dec_tlu_flush_lower_wb;
+		r_d_in[2] = r_d[2] & ~dec_tlu_flush_lower_wb;
+	end
+	rvdfflie #(
+		.WIDTH(24),
+		.LEFT(15)
+	) wbff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_wb_ctl_en),
+		.din(r_d_in),
+		.dout(wbd)
+	);
+	assign dec_i0_waddr_r[4:0] = r_d_in[8:4];
+	assign i0_wen_r = r_d_in[1] & ~dec_tlu_i0_kill_writeb_r;
+	assign dec_i0_wen_r = (i0_wen_r & ~r_d_in[23]) & ~i0_load_kill_wen_r;
+	assign dec_i0_wdata_r[31:0] = i0_result_corr_r[31:0];
+	assign div_e1_to_r = (x_d[23] & x_d[0]) | (r_d[23] & r_d[0]);
+	assign div_active_in = i0_div_decode_d | ((div_active & ~exu_div_wren) & ~nonblock_div_cancel);
+	assign dec_div_active = div_active;
+	assign i0_nonblock_div_stall = ((dec_i0_rs1_en_d & div_active) & (div_waddr_wb[4:0] == i0r[14:10])) | ((dec_i0_rs2_en_d & div_active) & (div_waddr_wb[4:0] == i0r[9:5]));
+	assign div_flush = (((x_d[23] & x_d[0]) & (x_d[8:4] == 5'b00000)) | ((x_d[23] & x_d[0]) & dec_tlu_flush_lower_r)) | (((r_d[23] & r_d[0]) & dec_tlu_flush_lower_r) & dec_tlu_i0_kill_writeb_r);
+	assign nonblock_div_cancel = (div_active & div_flush) | (((div_active & ~div_e1_to_r) & (r_d[8:4] == div_waddr_wb[4:0])) & i0_wen_r);
+	assign dec_div_cancel = nonblock_div_cancel;
+	assign i0_div_decode_d = i0_legal_decode_d & i0_dp[5];
+	generate
+		if (pt[202-:5] == 1) begin : genblock1
+			assign i0_result_x[31:0] = exu_i0_result_x[31:0];
+			assign i0_result_r[31:0] = (r_d[1] & r_d[3] ? lsu_result_m[31:0] : i0_result_r_raw[31:0]);
+		end
+		else begin : genblock1
+			assign i0_result_x[31:0] = (x_d[1] & x_d[3] ? lsu_result_m[31:0] : exu_i0_result_x[31:0]);
+			assign i0_result_r[31:0] = i0_result_r_raw[31:0];
+		end
+	endgenerate
+	rvdffe #(.WIDTH(32)) i0_result_r_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_r_data_en & ((x_d[1] | x_d[22]) | debug_valid_x)),
+		.din(i0_result_x[31:0]),
+		.dout(i0_result_r_raw[31:0])
+	);
+	assign i0_result_corr_r[31:0] = (r_d[1] & r_d[3] ? lsu_result_corr_r[31:0] : i0_result_r_raw[31:0]);
+	rvdffe #(.WIDTH(12)) e1brpcff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_data_en),
+		.din(last_br_immed_d[12:1]),
+		.dout(last_br_immed_x[12:1])
+	);
+	assign i0_wb_en = i0_wb_data_en;
+	assign i0_inst_wb_in[31:0] = i0_inst_r[31:0];
+	assign i0_inst_d[31:0] = (dec_i0_pc4_d ? i0[31:0] : {16'b0000000000000000, ifu_i0_cinst[15:0]});
+	assign trace_enable = ~dec_tlu_trace_disable;
+	rvdffe #(
+		.WIDTH(5),
+		.OVERRIDE(1)
+	) i0rdff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_div_decode_d),
+		.din(i0r[4:0]),
+		.dout(div_waddr_wb[4:0])
+	);
+	rvdffe #(.WIDTH(32)) i0xinstff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_x_data_en & trace_enable),
+		.din(i0_inst_d[31:0]),
+		.dout(i0_inst_x[31:0])
+	);
+	rvdffe #(.WIDTH(32)) i0cinstff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_r_data_en & trace_enable),
+		.din(i0_inst_x[31:0]),
+		.dout(i0_inst_r[31:0])
+	);
+	rvdffe #(.WIDTH(32)) i0wbinstff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_wb_en & trace_enable),
+		.din(i0_inst_wb_in[31:0]),
+		.dout(i0_inst_wb[31:0])
+	);
+	rvdffe #(.WIDTH(31)) i0wbpcff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_wb_en & trace_enable),
+		.din(dec_tlu_i0_pc_r[31:1]),
+		.dout(i0_pc_wb[31:1])
+	);
+	assign dec_i0_inst_wb[31:0] = i0_inst_wb[31:0];
+	assign dec_i0_pc_wb[31:1] = i0_pc_wb[31:1];
+	rvdffpcie #(.WIDTH(31)) i0_pc_r_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(i0_r_data_en),
+		.din(exu_i0_pc_x[31:1]),
+		.dout(dec_i0_pc_r[31:1])
+	);
+	assign dec_tlu_i0_pc_r[31:1] = dec_i0_pc_r[31:1];
+	rvbradder ibradder_correct(
+		.pc(exu_i0_pc_x[31:1]),
+		.offset(last_br_immed_x[12:1]),
+		.dout(pred_correct_npc_x[31:1])
+	);
+	assign i0_rs1_nonblock_load_bypass_en_d = (dec_i0_rs1_en_d & dec_nonblock_load_wen) & (dec_nonblock_load_waddr[4:0] == i0r[14:10]);
+	assign i0_rs2_nonblock_load_bypass_en_d = (dec_i0_rs2_en_d & dec_nonblock_load_wen) & (dec_nonblock_load_waddr[4:0] == i0r[9:5]);
+	assign i0_rs1bypass[2] = i0_rs1_depth_d[0] & (i0_rs1_class_d[0] | i0_rs1_class_d[2]);
+	assign i0_rs1bypass[1] = i0_rs1_depth_d[0] & i0_rs1_class_d[1];
+	assign i0_rs1bypass[0] = i0_rs1_depth_d[1] & ((i0_rs1_class_d[0] | i0_rs1_class_d[2]) | i0_rs1_class_d[1]);
+	assign i0_rs2bypass[2] = i0_rs2_depth_d[0] & (i0_rs2_class_d[0] | i0_rs2_class_d[2]);
+	assign i0_rs2bypass[1] = i0_rs2_depth_d[0] & i0_rs2_class_d[1];
+	assign i0_rs2bypass[0] = i0_rs2_depth_d[1] & ((i0_rs2_class_d[0] | i0_rs2_class_d[2]) | i0_rs2_class_d[1]);
+	assign dec_i0_rs1_bypass_en_d[3] = ((i0_rs1_nonblock_load_bypass_en_d & ~i0_rs1bypass[0]) & ~i0_rs1bypass[1]) & ~i0_rs1bypass[2];
+	assign dec_i0_rs1_bypass_en_d[2] = i0_rs1bypass[2];
+	assign dec_i0_rs1_bypass_en_d[1] = i0_rs1bypass[1];
+	assign dec_i0_rs1_bypass_en_d[0] = i0_rs1bypass[0];
+	assign dec_i0_rs2_bypass_en_d[3] = ((i0_rs2_nonblock_load_bypass_en_d & ~i0_rs2bypass[0]) & ~i0_rs2bypass[1]) & ~i0_rs2bypass[2];
+	assign dec_i0_rs2_bypass_en_d[2] = i0_rs2bypass[2];
+	assign dec_i0_rs2_bypass_en_d[1] = i0_rs2bypass[1];
+	assign dec_i0_rs2_bypass_en_d[0] = i0_rs2bypass[0];
+	assign dec_i0_result_r[31:0] = i0_result_r[31:0];
+endmodule
+module eb1_dec_dec_ctl (
+	inst,
+	out
+);
+	input wire [31:0] inst;
+	output wire [94:0] out;
+	wire [31:0] i;
+	assign i[31:0] = inst[31:0];
+	assign out[49] = (((((((((((((((((((((((i[30] & i[24]) & i[23]) & !i[22]) & !i[21]) & !i[20]) & i[14]) & !i[5]) & i[4]) | (((i[29] & !i[27]) & !i[24]) & i[4])) | (((!i[25] & !i[13]) & !i[12]) & i[4])) | (((!i[30] & !i[25]) & i[13]) & i[12])) | (((i[27] & i[25]) & i[14]) & i[4])) | (((i[29] & i[27]) & !i[14]) & i[4])) | (((i[29] & !i[14]) & i[5]) & i[4])) | (((!i[27] & !i[25]) & i[14]) & i[4])) | (((i[30] & !i[29]) & !i[13]) & i[4])) | (((!i[30] & !i[27]) & !i[25]) & i[4])) | ((i[13] & !i[5]) & i[4])) | ((!i[12] & !i[5]) & i[4])) | i[2]) | i[6]) | (((((((i[30] & i[24]) & i[23]) & i[22]) & i[21]) & i[20]) & !i[5]) & i[4])) | ((((((((!i[30] & i[29]) & !i[24]) & !i[23]) & i[22]) & i[21]) & i[20]) & !i[5]) & i[4])) | (((((((!i[30] & i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[20]) & !i[5]) & i[4]);
+	assign out[48] = (((((((((((((!i[14] & !i[13]) & !i[2]) | ((!i[13] & i[11]) & !i[2])) | ((i[19] & i[13]) & !i[2])) | ((!i[13] & i[10]) & !i[2])) | ((i[18] & i[13]) & !i[2])) | ((!i[13] & i[9]) & !i[2])) | ((i[17] & i[13]) & !i[2])) | ((!i[13] & i[8]) & !i[2])) | ((i[16] & i[13]) & !i[2])) | ((!i[13] & i[7]) & !i[2])) | ((i[15] & i[13]) & !i[2])) | (!i[4] & !i[3])) | (!i[6] & !i[2]);
+	assign out[47] = ((i[5] & !i[4]) & !i[2]) | ((!i[6] & i[5]) & !i[2]);
+	assign out[46] = ((((!i[4] & !i[3]) & i[2]) | (((i[13] & !i[5]) & i[4]) & !i[2])) | (((!i[13] & !i[12]) & i[6]) & i[4])) | (((!i[12] & !i[5]) & i[4]) & !i[2]);
+	assign out[45] = ((!i[5] & !i[2]) | (i[5] & i[2])) | i[4];
+	assign out[44] = ((((((i[27] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | (((((!i[30] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[14] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]);
+	assign out[43] = (i[5] & i[3]) | (i[4] & i[2]);
+	assign out[42] = ((!i[5] & !i[3]) & i[2]) | (i[5] & i[3]);
+	assign out[41] = (!i[5] & !i[4]) & !i[2];
+	assign out[40] = (!i[6] & i[5]) & !i[4];
+	assign out[39] = (!i[6] & !i[4]) & !i[2];
+	assign out[38] = (((((!i[14] & !i[13]) & !i[12]) & !i[5]) & i[4]) | ((!i[5] & !i[3]) & i[2])) | (((((((!i[30] & !i[25]) & !i[14]) & !i[13]) & !i[12]) & !i[6]) & i[4]) & !i[2]);
+	assign out[37] = (((((((((i[30] & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]) | ((((((!i[29] & !i[25]) & !i[14]) & i[13]) & !i[6]) & i[4]) & !i[2])) | (((((i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2])) | ((((!i[14] & i[13]) & !i[5]) & i[4]) & !i[2])) | ((i[6] & !i[4]) & !i[2]);
+	assign out[36] = ((((((!i[27] & !i[25]) & i[14]) & i[13]) & i[12]) & !i[6]) & !i[2]) | ((((i[14] & i[13]) & i[12]) & !i[5]) & !i[2]);
+	assign out[35] = ((((!i[6] & i[3]) | (((((((!i[29] & !i[27]) & !i[25]) & i[14]) & i[13]) & !i[12]) & !i[6]) & !i[2])) | ((i[5] & i[4]) & i[2])) | (((!i[13] & !i[12]) & i[6]) & i[4])) | ((((i[14] & i[13]) & !i[12]) & !i[5]) & !i[2]);
+	assign out[34] = (((((((!i[29] & !i[27]) & !i[25]) & i[14]) & !i[13]) & !i[12]) & i[4]) & !i[2]) | (((((i[14] & !i[13]) & !i[12]) & !i[5]) & i[4]) & !i[2]);
+	assign out[33] = (((((((!i[29] & !i[27]) & !i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[32] = ((((((i[30] & !i[29]) & !i[27]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[31] = ((((((((!i[30] & !i[29]) & !i[27]) & !i[25]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[30] = ((((((!i[29] & !i[25]) & !i[14]) & i[13]) & !i[6]) & i[4]) & !i[2]) | ((((!i[14] & i[13]) & !i[5]) & i[4]) & !i[2]);
+	assign out[29] = ((((((((((!i[27] & i[25]) & i[14]) & i[12]) & !i[6]) & i[5]) & !i[2]) | ((((!i[14] & i[13]) & i[12]) & !i[5]) & !i[2])) | (((i[13] & i[6]) & !i[4]) & !i[2])) | ((i[14] & !i[5]) & !i[4])) | (((((!i[25] & !i[14]) & i[13]) & i[12]) & !i[6]) & !i[2])) | ((((((i[27] & i[25]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2]);
+	assign out[28] = (i[6] & !i[4]) & !i[2];
+	assign out[27] = (((!i[14] & !i[12]) & i[6]) & !i[4]) & !i[2];
+	assign out[26] = (((!i[14] & i[12]) & i[6]) & !i[4]) & !i[2];
+	assign out[25] = (((i[14] & i[12]) & i[5]) & !i[4]) & !i[2];
+	assign out[24] = (((i[14] & !i[12]) & i[5]) & !i[4]) & !i[2];
+	assign out[23] = i[6] & i[2];
+	assign out[22] = (((!i[13] & !i[12]) & !i[6]) & !i[4]) & !i[2];
+	assign out[21] = ((i[12] & !i[6]) & !i[4]) & !i[2];
+	assign out[20] = (i[13] & !i[6]) & !i[4];
+	assign out[19] = ((((((i[13] & i[6]) & i[4]) | ((i[7] & i[6]) & i[4])) | ((i[8] & i[6]) & i[4])) | ((i[9] & i[6]) & i[4])) | ((i[10] & i[6]) & i[4])) | ((i[11] & i[6]) & i[4]);
+	assign out[18] = (((((((i[15] & i[13]) & i[12]) & i[6]) & i[4]) | ((((i[16] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[17] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[18] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[19] & i[13]) & i[12]) & i[6]) & i[4]);
+	assign out[17] = ((((((i[15] & !i[12]) & i[6]) & i[4]) | (((i[16] & !i[12]) & i[6]) & i[4])) | (((i[17] & !i[12]) & i[6]) & i[4])) | (((i[18] & !i[12]) & i[6]) & i[4])) | (((i[19] & !i[12]) & i[6]) & i[4]);
+	assign out[16] = ((!i[13] & i[12]) & i[6]) & i[4];
+	assign out[15] = (((((((i[14] & !i[13]) & i[6]) & i[4]) | (((i[15] & i[14]) & i[6]) & i[4])) | (((i[16] & i[14]) & i[6]) & i[4])) | (((i[17] & i[14]) & i[6]) & i[4])) | (((i[18] & i[14]) & i[6]) & i[4])) | (((i[19] & i[14]) & i[6]) & i[4]);
+	assign out[14] = ((((((((((!i[5] & i[3]) | (((!i[13] & i[7]) & i[6]) & i[4])) | (((!i[13] & i[8]) & i[6]) & i[4])) | (((!i[13] & i[9]) & i[6]) & i[4])) | (((!i[13] & i[10]) & i[6]) & i[4])) | (((!i[13] & i[11]) & i[6]) & i[4])) | (((i[15] & i[13]) & i[6]) & i[4])) | (((i[16] & i[13]) & i[6]) & i[4])) | (((i[17] & i[13]) & i[6]) & i[4])) | (((i[18] & i[13]) & i[6]) & i[4])) | (((i[19] & i[13]) & i[6]) & i[4]);
+	assign out[13] = ((((((((((((i[12] & !i[5]) & i[3]) | ((((!i[22] & !i[13]) & !i[12]) & i[6]) & i[4])) | (((!i[13] & i[7]) & i[6]) & i[4])) | (((!i[13] & i[8]) & i[6]) & i[4])) | (((!i[13] & i[9]) & i[6]) & i[4])) | (((!i[13] & i[10]) & i[6]) & i[4])) | (((!i[13] & i[11]) & i[6]) & i[4])) | (((i[15] & i[13]) & i[6]) & i[4])) | (((i[16] & i[13]) & i[6]) & i[4])) | (((i[17] & i[13]) & i[6]) & i[4])) | (((i[18] & i[13]) & i[6]) & i[4])) | (((i[19] & i[13]) & i[6]) & i[4]);
+	assign out[12] = ((((!i[22] & i[20]) & !i[13]) & !i[12]) & i[6]) & i[4];
+	assign out[11] = ((((!i[21] & !i[20]) & !i[13]) & !i[12]) & i[6]) & i[4];
+	assign out[10] = (((i[29] & !i[13]) & !i[12]) & i[6]) & i[4];
+	assign out[9] = (((((((((((((((((((((!i[30] & i[27]) & i[24]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | (((((((((i[29] & i[27]) & !i[24]) & i[23]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[24]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((i[27] & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[30] & i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & i[22]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[21]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[22]) & i[21]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[30] & i[29]) & i[27]) & !i[23]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & i[27]) & i[23]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2])) | (((((i[25] & !i[14]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((i[30] & !i[27]) & i[24]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[29] & i[27]) & i[14]) & !i[6]) & i[5]) & !i[2]);
+	assign out[8] = ((((((((!i[27] & i[25]) & !i[14]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]) | (((((((!i[27] & i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]);
+	assign out[7] = ((((((!i[27] & i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[6] = (((((i[25] & !i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2];
+	assign out[5] = ((((!i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2];
+	assign out[4] = (((((!i[27] & i[25]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2];
+	assign out[3] = !i[5] & i[3];
+	assign out[2] = (i[12] & !i[5]) & i[3];
+	assign out[94] = ((((((((((i[30] & !i[27]) & !i[24]) & !i[22]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[93] = (((((((((i[30] & !i[27]) & !i[24]) & !i[22]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[92] = ((((((((i[30] & !i[27]) & !i[24]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[91] = ((((((((i[30] & !i[27]) & i[22]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[90] = ((((((((i[30] & !i[27]) & i[22]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[89] = (((((((!i[30] & i[29]) & !i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[88] = (((((((!i[30] & i[29]) & !i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[87] = (((((i[27] & i[25]) & i[14]) & !i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[86] = (((((i[27] & i[25]) & i[14]) & i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[85] = ((((((!i[30] & i[27]) & !i[25]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2];
+	assign out[84] = (((((i[30] & i[27]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2];
+	assign out[83] = ((((((!i[30] & i[27]) & !i[25]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[82] = ((((((i[30] & !i[27]) & !i[14]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[81] = (((((((i[30] & i[29]) & !i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[78] = ((((((((((((((((((i[30] & !i[27]) & !i[24]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | (((((((!i[30] & i[27]) & i[14]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2])) | ((((((((i[30] & i[29]) & !i[27]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[27] & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2])) | ((((((i[30] & i[14]) & !i[13]) & !i[12]) & !i[6]) & i[5]) & !i[2])) | ((((((i[30] & !i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[30] & i[29]) & !i[27]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((((((i[30] & i[29]) & i[24]) & i[23]) & i[22]) & i[21]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((((((!i[30] & i[29]) & i[27]) & !i[24]) & !i[23]) & i[22]) & i[21]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((((((!i[30] & i[27]) & i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((((((i[30] & i[29]) & i[24]) & i[23]) & !i[22]) & !i[21]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2]);
+	assign out[77] = (((((((!i[30] & i[29]) & i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[76] = ((((((i[30] & !i[29]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[75] = (((((((i[30] & i[29]) & i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[74] = (((((((i[30] & !i[29]) & i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[73] = (((((((i[29] & i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]) | (((((((i[30] & !i[29]) & i[27]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]);
+	assign out[72] = (((((((!i[30] & i[27]) & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[71] = ((((((i[30] & i[27]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[70] = ((((((i[27] & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[69] = ((((((i[27] & i[25]) & !i[14]) & !i[13]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[68] = (((((i[27] & !i[14]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[67] = (((((i[27] & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[66] = (((((i[27] & i[25]) & !i[14]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[80] = (((((((i[30] & i[29]) & i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[79] = (((((((!i[30] & i[29]) & i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[65] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[64] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2];
+	assign out[63] = (((((((((((((!i[30] & i[29]) & !i[27]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | (((((((!i[30] & !i[29]) & i[27]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((i[30] & !i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[27] & !i[25]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2])) | ((((((i[30] & i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2])) | ((((((i[29] & !i[27]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[29] & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]);
+	assign out[62] = ((((((((((i[30] & !i[27]) & i[24]) & !i[23]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[61] = (((((((((i[30] & !i[27]) & i[24]) & !i[23]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[60] = (((((((((i[30] & !i[27]) & i[24]) & !i[23]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[59] = (((((((((i[30] & !i[27]) & i[23]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[58] = ((((((((i[30] & !i[27]) & i[23]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[57] = ((((((((i[30] & !i[27]) & i[23]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[56] = (((((((i[30] & !i[27]) & i[24]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2];
+	assign out[55] = (((((i[30] & i[27]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[54] = (((((i[30] & i[27]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2];
+	assign out[53] = (((((i[29] & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[52] = (((((i[29] & i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2];
+	assign out[51] = ((((i[29] & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2];
+	assign out[50] = ((((i[29] & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2];
+	assign out[1] = (((((((((i[28] & i[22]) & !i[13]) & !i[12]) & i[4]) | (((((!i[30] & !i[29]) & !i[27]) & !i[25]) & !i[6]) & i[4])) | ((((((!i[29] & !i[27]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4])) | (((((!i[29] & !i[27]) & !i[25]) & !i[14]) & !i[6]) & i[4])) | ((i[13] & !i[5]) & i[4])) | (i[4] & i[2])) | ((!i[12] & !i[5]) & i[4]);
+	assign out[0] = (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & i[22]) & !i[21]) & i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0]) | (((((((((((((((((((((((((((((!i[31] & !i[30]) & i[29]) & i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & i[21]) & !i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((((!i[31] & i[29]) & !i[28]) & !i[26]) & !i[25]) & i[24]) & !i[22]) & !i[20]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((((!i[31] & i[29]) & !i[28]) & !i[26]) & !i[25]) & i[24]) & !i[22]) & !i[21]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((((!i[31] & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[23]) & !i[22]) & !i[20]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((((!i[31] & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[21]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & i[25]) & i[13]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[28]) & !i[26]) & !i[25]) & !i[24]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[30]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & i[14]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[30]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[13]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[28]) & !i[27]) & !i[26]) & !i[25]) & i[14]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & !i[13]) & i[12]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & i[14]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & i[30]) & !i[28]) & i[27]) & !i[26]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & i[29]) & !i[28]) & i[27]) & !i[26]) & !i[25]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((!i[14] & !i[13]) & !i[12]) & i[6]) & i[5]) & !i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[29]) & !i[28]) & !i[26]) & !i[25]) & i[14]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[13]) & i[12]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((i[14] & i[6]) & i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((!i[14] & !i[13]) & i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((!i[12] & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((!i[13] & i[12]) & i[6]) & i[5]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[13]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[13]) & !i[12]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((i[13] & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((i[6] & i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((!i[14] & !i[12]) & !i[6]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((!i[13] & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((i[13] & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((!i[6] & i[4]) & !i[3]) & i[2]) & i[1]) & i[0]);
+endmodule
+module eb1_dec_gpr_ctl (
+	raddr0,
+	raddr1,
+	wen0,
+	waddr0,
+	wd0,
+	wen1,
+	waddr1,
+	wd1,
+	wen2,
+	waddr2,
+	wd2,
+	clk,
+	rst_l,
+	rd0,
+	rd1,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [4:0] raddr0;
+	input wire [4:0] raddr1;
+	input wire wen0;
+	input wire [4:0] waddr0;
+	input wire [31:0] wd0;
+	input wire wen1;
+	input wire [4:0] waddr1;
+	input wire [31:0] wd1;
+	input wire wen2;
+	input wire [4:0] waddr2;
+	input wire [31:0] wd2;
+	input wire clk;
+	input wire rst_l;
+	output reg [31:0] rd0;
+	output reg [31:0] rd1;
+	input wire scan_mode;
+	wire [1023:32] gpr_out;
+	reg [1023:32] gpr_in;
+	reg [31:1] w0v;
+	reg [31:1] w1v;
+	reg [31:1] w2v;
+	wire [31:1] gpr_wr_en;
+	assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1]) | w2v[31:1];
+	generate
+		genvar j;
+		for (j = 1; j < 32; j = j + 1) begin : gpr
+			rvdffe #(.WIDTH(32)) gprff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(gpr_wr_en[j]),
+				.din(gpr_in[(j * 32) + 31-:32]),
+				.dout(gpr_out[(j * 32) + 31-:32])
+			);
+		end
+	endgenerate
+	function automatic signed [4:0] sv2v_cast_5_signed;
+		input reg signed [4:0] inp;
+		sv2v_cast_5_signed = inp;
+	endfunction
+	always @(*) begin
+		rd0[31:0] = 32'b00000000000000000000000000000000;
+		rd1[31:0] = 32'b00000000000000000000000000000000;
+		w0v[31:1] = 31'b0000000000000000000000000000000;
+		w1v[31:1] = 31'b0000000000000000000000000000000;
+		w2v[31:1] = 31'b0000000000000000000000000000000;
+		gpr_in[32+:992] = {992 {1'sb0}};
+		begin : sv2v_autoblock_39
+			reg signed [31:0] j;
+			for (j = 1; j < 32; j = j + 1)
+				begin
+					rd0[31:0] = rd0[31:0] | ({32 {raddr0[4:0] == sv2v_cast_5_signed(j)}} & gpr_out[(j * 32) + 31-:32]);
+					rd1[31:0] = rd1[31:0] | ({32 {raddr1[4:0] == sv2v_cast_5_signed(j)}} & gpr_out[(j * 32) + 31-:32]);
+				end
+		end
+		begin : sv2v_autoblock_40
+			reg signed [31:0] j;
+			for (j = 1; j < 32; j = j + 1)
+				begin
+					w0v[j] = wen0 & (waddr0[4:0] == sv2v_cast_5_signed(j));
+					w1v[j] = wen1 & (waddr1[4:0] == sv2v_cast_5_signed(j));
+					w2v[j] = wen2 & (waddr2[4:0] == sv2v_cast_5_signed(j));
+					gpr_in[j * 32+:32] = (({32 {w0v[j]}} & wd0[31:0]) | ({32 {w1v[j]}} & wd1[31:0])) | ({32 {w2v[j]}} & wd2[31:0]);
+				end
+		end
+	end
+endmodule
+module eb1_dec_ib_ctl (
+	dbg_cmd_valid,
+	dbg_cmd_write,
+	dbg_cmd_type,
+	dbg_cmd_addr,
+	i0_brp,
+	ifu_i0_bp_index,
+	ifu_i0_bp_fghr,
+	ifu_i0_bp_btag,
+	ifu_i0_fa_index,
+	ifu_i0_pc4,
+	ifu_i0_valid,
+	ifu_i0_icaf,
+	ifu_i0_icaf_type,
+	ifu_i0_icaf_second,
+	ifu_i0_dbecc,
+	ifu_i0_instr,
+	ifu_i0_pc,
+	dec_ib0_valid_d,
+	dec_debug_valid_d,
+	dec_i0_instr_d,
+	dec_i0_pc_d,
+	dec_i0_pc4_d,
+	dec_i0_brp,
+	dec_i0_bp_index,
+	dec_i0_bp_fghr,
+	dec_i0_bp_btag,
+	dec_i0_bp_fa_index,
+	dec_i0_icaf_d,
+	dec_i0_icaf_second_d,
+	dec_i0_icaf_type_d,
+	dec_i0_dbecc_d,
+	dec_debug_wdata_rs1_d,
+	dec_debug_fence_d
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire dbg_cmd_valid;
+	input wire dbg_cmd_write;
+	input wire [1:0] dbg_cmd_type;
+	input wire [31:0] dbg_cmd_addr;
+	input wire [50:0] i0_brp;
+	input wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index;
+	input wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr;
+	input wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag;
+	input wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index;
+	input wire ifu_i0_pc4;
+	input wire ifu_i0_valid;
+	input wire ifu_i0_icaf;
+	input wire [1:0] ifu_i0_icaf_type;
+	input wire ifu_i0_icaf_second;
+	input wire ifu_i0_dbecc;
+	input wire [31:0] ifu_i0_instr;
+	input wire [31:1] ifu_i0_pc;
+	output wire dec_ib0_valid_d;
+	output wire dec_debug_valid_d;
+	output wire [31:0] dec_i0_instr_d;
+	output wire [31:1] dec_i0_pc_d;
+	output wire dec_i0_pc4_d;
+	output wire [50:0] dec_i0_brp;
+	output wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index;
+	output wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr;
+	output wire [pt[2139-:9] - 1:0] dec_i0_bp_btag;
+	output wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index;
+	output wire dec_i0_icaf_d;
+	output wire dec_i0_icaf_second_d;
+	output wire [1:0] dec_i0_icaf_type_d;
+	output wire dec_i0_dbecc_d;
+	output wire dec_debug_wdata_rs1_d;
+	output wire dec_debug_fence_d;
+	wire debug_valid;
+	wire [4:0] dreg;
+	wire [11:0] dcsr;
+	wire [31:0] ib0;
+	wire [31:0] ib0_debug_in;
+	wire debug_read;
+	wire debug_write;
+	wire debug_read_gpr;
+	wire debug_write_gpr;
+	wire debug_read_csr;
+	wire debug_write_csr;
+	wire [34:0] ifu_i0_pcdata;
+	wire [34:0] pc0;
+	assign ifu_i0_pcdata[34:0] = {ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf, ifu_i0_pc[31:1], ifu_i0_pc4};
+	assign pc0[34:0] = ifu_i0_pcdata[34:0];
+	assign dec_i0_icaf_second_d = pc0[34];
+	assign dec_i0_dbecc_d = pc0[33];
+	assign dec_i0_icaf_d = pc0[32];
+	assign dec_i0_pc_d[31:1] = pc0[31:1];
+	assign dec_i0_pc4_d = pc0[0];
+	assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0];
+	assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2);
+	assign debug_read = debug_valid & ~dbg_cmd_write;
+	assign debug_write = debug_valid & dbg_cmd_write;
+	assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0] == 2'h0);
+	assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0] == 2'h0);
+	assign debug_read_csr = debug_read & (dbg_cmd_type[1:0] == 2'h1);
+	assign debug_write_csr = debug_write & (dbg_cmd_type[1:0] == 2'h1);
+	assign dreg[4:0] = dbg_cmd_addr[4:0];
+	assign dcsr[11:0] = dbg_cmd_addr[11:0];
+	assign ib0_debug_in[31:0] = ((({32 {debug_read_gpr}} & {12'b000000000000, dreg[4:0], 15'b110000000110011}) | ({32 {debug_write_gpr}} & {20'b00000000000000000110, dreg[4:0], 7'b0110011})) | ({32 {debug_read_csr}} & {dcsr[11:0], 20'b00000010000001110011})) | ({32 {debug_write_csr}} & {dcsr[11:0], 20'b00000001000001110011});
+	assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr;
+	assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4);
+	assign ib0[31:0] = (debug_valid ? ib0_debug_in[31:0] : ifu_i0_instr[31:0]);
+	assign dec_ib0_valid_d = ifu_i0_valid | debug_valid;
+	assign dec_debug_valid_d = debug_valid;
+	assign dec_i0_instr_d[31:0] = ib0[31:0];
+	assign dec_i0_brp = i0_brp;
+	assign dec_i0_bp_index = ifu_i0_bp_index;
+	assign dec_i0_bp_fghr = ifu_i0_bp_fghr;
+	assign dec_i0_bp_btag = ifu_i0_bp_btag;
+	assign dec_i0_bp_fa_index = ifu_i0_fa_index;
+endmodule
+module eb1_dec_tlu_ctl (
+	clk,
+	free_clk,
+	free_l2clk,
+	rst_l,
+	scan_mode,
+	rst_vec,
+	nmi_int,
+	nmi_vec,
+	i_cpu_halt_req,
+	i_cpu_run_req,
+	lsu_fastint_stall_any,
+	ifu_pmu_instr_aligned,
+	ifu_pmu_fetch_stall,
+	ifu_pmu_ic_miss,
+	ifu_pmu_ic_hit,
+	ifu_pmu_bus_error,
+	ifu_pmu_bus_busy,
+	ifu_pmu_bus_trxn,
+	dec_pmu_instr_decoded,
+	dec_pmu_decode_stall,
+	dec_pmu_presync_stall,
+	dec_pmu_postsync_stall,
+	lsu_store_stall_any,
+	dma_dccm_stall_any,
+	dma_iccm_stall_any,
+	exu_pmu_i0_br_misp,
+	exu_pmu_i0_br_ataken,
+	exu_pmu_i0_pc4,
+	lsu_pmu_bus_trxn,
+	lsu_pmu_bus_misaligned,
+	lsu_pmu_bus_error,
+	lsu_pmu_bus_busy,
+	lsu_pmu_load_external_m,
+	lsu_pmu_store_external_m,
+	dma_pmu_dccm_read,
+	dma_pmu_dccm_write,
+	dma_pmu_any_read,
+	dma_pmu_any_write,
+	lsu_fir_addr,
+	lsu_fir_error,
+	iccm_dma_sb_error,
+	lsu_error_pkt_r,
+	lsu_single_ecc_error_incr,
+	dec_pause_state,
+	lsu_imprecise_error_store_any,
+	lsu_imprecise_error_load_any,
+	lsu_imprecise_error_addr_any,
+	dec_csr_wen_unq_d,
+	dec_csr_any_unq_d,
+	dec_csr_rdaddr_d,
+	dec_csr_wen_r,
+	dec_csr_wraddr_r,
+	dec_csr_wrdata_r,
+	dec_csr_stall_int_ff,
+	dec_tlu_i0_valid_r,
+	exu_npc_r,
+	dec_tlu_i0_pc_r,
+	dec_tlu_packet_r,
+	dec_illegal_inst,
+	dec_i0_decode_d,
+	exu_i0_br_hist_r,
+	exu_i0_br_error_r,
+	exu_i0_br_start_error_r,
+	exu_i0_br_valid_r,
+	exu_i0_br_mp_r,
+	exu_i0_br_middle_r,
+	exu_i0_br_way_r,
+	dec_tlu_core_empty,
+	dec_dbg_cmd_done,
+	dec_dbg_cmd_fail,
+	dec_tlu_dbg_halted,
+	dec_tlu_debug_mode,
+	dec_tlu_resume_ack,
+	dec_tlu_debug_stall,
+	dec_tlu_flush_noredir_r,
+	dec_tlu_mpc_halted_only,
+	dec_tlu_flush_leak_one_r,
+	dec_tlu_flush_err_r,
+	dec_tlu_flush_extint,
+	dec_tlu_meihap,
+	dbg_halt_req,
+	dbg_resume_req,
+	ifu_miss_state_idle,
+	lsu_idle_any,
+	dec_div_active,
+	trigger_pkt_any,
+	ifu_ic_error_start,
+	ifu_iccm_rd_ecc_single_err,
+	ifu_ic_debug_rd_data,
+	ifu_ic_debug_rd_data_valid,
+	dec_tlu_ic_diag_pkt,
+	pic_claimid,
+	pic_pl,
+	mhwakeup,
+	mexintpend,
+	timer_int,
+	soft_int,
+	o_cpu_halt_status,
+	o_cpu_halt_ack,
+	o_cpu_run_ack,
+	o_debug_mode_status,
+	core_id,
+	mpc_debug_halt_req,
+	mpc_debug_run_req,
+	mpc_reset_run_req,
+	mpc_debug_halt_ack,
+	mpc_debug_run_ack,
+	debug_brkpt_status,
+	dec_tlu_meicurpl,
+	dec_tlu_meipt,
+	dec_csr_rddata_d,
+	dec_csr_legal_d,
+	dec_tlu_br0_r_pkt,
+	dec_tlu_i0_kill_writeb_wb,
+	dec_tlu_flush_lower_wb,
+	dec_tlu_i0_commit_cmt,
+	dec_tlu_i0_kill_writeb_r,
+	dec_tlu_flush_lower_r,
+	dec_tlu_flush_path_r,
+	dec_tlu_fence_i_r,
+	dec_tlu_wr_pause_r,
+	dec_tlu_flush_pause_r,
+	dec_tlu_presync_d,
+	dec_tlu_postsync_d,
+	dec_tlu_mrac_ff,
+	dec_tlu_force_halt,
+	dec_tlu_perfcnt0,
+	dec_tlu_perfcnt1,
+	dec_tlu_perfcnt2,
+	dec_tlu_perfcnt3,
+	dec_tlu_i0_exc_valid_wb1,
+	dec_tlu_i0_valid_wb1,
+	dec_tlu_int_valid_wb1,
+	dec_tlu_exc_cause_wb1,
+	dec_tlu_mtval_wb1,
+	dec_tlu_external_ldfwd_disable,
+	dec_tlu_sideeffect_posted_disable,
+	dec_tlu_core_ecc_disable,
+	dec_tlu_bpred_disable,
+	dec_tlu_wb_coalescing_disable,
+	dec_tlu_pipelining_disable,
+	dec_tlu_trace_disable,
+	dec_tlu_dma_qos_prty,
+	dec_tlu_misc_clk_override,
+	dec_tlu_dec_clk_override,
+	dec_tlu_ifu_clk_override,
+	dec_tlu_lsu_clk_override,
+	dec_tlu_bus_clk_override,
+	dec_tlu_pic_clk_override,
+	dec_tlu_picio_clk_override,
+	dec_tlu_dccm_clk_override,
+	dec_tlu_icm_clk_override
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire free_clk;
+	input wire free_l2clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire [31:1] rst_vec;
+	input wire nmi_int;
+	input wire [31:1] nmi_vec;
+	input wire i_cpu_halt_req;
+	input wire i_cpu_run_req;
+	input wire lsu_fastint_stall_any;
+	input wire ifu_pmu_instr_aligned;
+	input wire ifu_pmu_fetch_stall;
+	input wire ifu_pmu_ic_miss;
+	input wire ifu_pmu_ic_hit;
+	input wire ifu_pmu_bus_error;
+	input wire ifu_pmu_bus_busy;
+	input wire ifu_pmu_bus_trxn;
+	input wire dec_pmu_instr_decoded;
+	input wire dec_pmu_decode_stall;
+	input wire dec_pmu_presync_stall;
+	input wire dec_pmu_postsync_stall;
+	input wire lsu_store_stall_any;
+	input wire dma_dccm_stall_any;
+	input wire dma_iccm_stall_any;
+	input wire exu_pmu_i0_br_misp;
+	input wire exu_pmu_i0_br_ataken;
+	input wire exu_pmu_i0_pc4;
+	input wire lsu_pmu_bus_trxn;
+	input wire lsu_pmu_bus_misaligned;
+	input wire lsu_pmu_bus_error;
+	input wire lsu_pmu_bus_busy;
+	input wire lsu_pmu_load_external_m;
+	input wire lsu_pmu_store_external_m;
+	input wire dma_pmu_dccm_read;
+	input wire dma_pmu_dccm_write;
+	input wire dma_pmu_any_read;
+	input wire dma_pmu_any_write;
+	input wire [31:1] lsu_fir_addr;
+	input wire [1:0] lsu_fir_error;
+	input wire iccm_dma_sb_error;
+	input wire [39:0] lsu_error_pkt_r;
+	input wire lsu_single_ecc_error_incr;
+	input wire dec_pause_state;
+	input wire lsu_imprecise_error_store_any;
+	input wire lsu_imprecise_error_load_any;
+	input wire [31:0] lsu_imprecise_error_addr_any;
+	input wire dec_csr_wen_unq_d;
+	input wire dec_csr_any_unq_d;
+	input wire [11:0] dec_csr_rdaddr_d;
+	input wire dec_csr_wen_r;
+	input wire [11:0] dec_csr_wraddr_r;
+	input wire [31:0] dec_csr_wrdata_r;
+	input wire dec_csr_stall_int_ff;
+	input wire dec_tlu_i0_valid_r;
+	input wire [31:1] exu_npc_r;
+	input wire [31:1] dec_tlu_i0_pc_r;
+	input wire [16:0] dec_tlu_packet_r;
+	input wire [31:0] dec_illegal_inst;
+	input wire dec_i0_decode_d;
+	input wire [1:0] exu_i0_br_hist_r;
+	input wire exu_i0_br_error_r;
+	input wire exu_i0_br_start_error_r;
+	input wire exu_i0_br_valid_r;
+	input wire exu_i0_br_mp_r;
+	input wire exu_i0_br_middle_r;
+	input wire exu_i0_br_way_r;
+	output wire dec_tlu_core_empty;
+	output wire dec_dbg_cmd_done;
+	output wire dec_dbg_cmd_fail;
+	output wire dec_tlu_dbg_halted;
+	output wire dec_tlu_debug_mode;
+	output wire dec_tlu_resume_ack;
+	output wire dec_tlu_debug_stall;
+	output wire dec_tlu_flush_noredir_r;
+	output wire dec_tlu_mpc_halted_only;
+	output wire dec_tlu_flush_leak_one_r;
+	output wire dec_tlu_flush_err_r;
+	output wire dec_tlu_flush_extint;
+	output wire [31:2] dec_tlu_meihap;
+	input wire dbg_halt_req;
+	input wire dbg_resume_req;
+	input wire ifu_miss_state_idle;
+	input wire lsu_idle_any;
+	input wire dec_div_active;
+	output wire [151:0] trigger_pkt_any;
+	input wire ifu_ic_error_start;
+	input wire ifu_iccm_rd_ecc_single_err;
+	input wire [70:0] ifu_ic_debug_rd_data;
+	input wire ifu_ic_debug_rd_data_valid;
+	output wire [89:0] dec_tlu_ic_diag_pkt;
+	input wire [7:0] pic_claimid;
+	input wire [3:0] pic_pl;
+	input wire mhwakeup;
+	input wire mexintpend;
+	input wire timer_int;
+	input wire soft_int;
+	output wire o_cpu_halt_status;
+	output wire o_cpu_halt_ack;
+	output wire o_cpu_run_ack;
+	output wire o_debug_mode_status;
+	input wire [31:4] core_id;
+	input wire mpc_debug_halt_req;
+	input wire mpc_debug_run_req;
+	input wire mpc_reset_run_req;
+	output wire mpc_debug_halt_ack;
+	output wire mpc_debug_run_ack;
+	output wire debug_brkpt_status;
+	output wire [3:0] dec_tlu_meicurpl;
+	output wire [3:0] dec_tlu_meipt;
+	output wire [31:0] dec_csr_rddata_d;
+	output wire dec_csr_legal_d;
+	output wire [6:0] dec_tlu_br0_r_pkt;
+	output wire dec_tlu_i0_kill_writeb_wb;
+	output wire dec_tlu_flush_lower_wb;
+	output wire dec_tlu_i0_commit_cmt;
+	output wire dec_tlu_i0_kill_writeb_r;
+	output wire dec_tlu_flush_lower_r;
+	output wire [31:1] dec_tlu_flush_path_r;
+	output wire dec_tlu_fence_i_r;
+	output wire dec_tlu_wr_pause_r;
+	output wire dec_tlu_flush_pause_r;
+	output wire dec_tlu_presync_d;
+	output wire dec_tlu_postsync_d;
+	output wire [31:0] dec_tlu_mrac_ff;
+	output wire dec_tlu_force_halt;
+	output wire dec_tlu_perfcnt0;
+	output wire dec_tlu_perfcnt1;
+	output wire dec_tlu_perfcnt2;
+	output wire dec_tlu_perfcnt3;
+	output wire dec_tlu_i0_exc_valid_wb1;
+	output wire dec_tlu_i0_valid_wb1;
+	output wire dec_tlu_int_valid_wb1;
+	output wire [4:0] dec_tlu_exc_cause_wb1;
+	output wire [31:0] dec_tlu_mtval_wb1;
+	output wire dec_tlu_external_ldfwd_disable;
+	output wire dec_tlu_sideeffect_posted_disable;
+	output wire dec_tlu_core_ecc_disable;
+	output wire dec_tlu_bpred_disable;
+	output wire dec_tlu_wb_coalescing_disable;
+	output wire dec_tlu_pipelining_disable;
+	output wire dec_tlu_trace_disable;
+	output wire [2:0] dec_tlu_dma_qos_prty;
+	output wire dec_tlu_misc_clk_override;
+	output wire dec_tlu_dec_clk_override;
+	output wire dec_tlu_ifu_clk_override;
+	output wire dec_tlu_lsu_clk_override;
+	output wire dec_tlu_bus_clk_override;
+	output wire dec_tlu_pic_clk_override;
+	output wire dec_tlu_picio_clk_override;
+	output wire dec_tlu_dccm_clk_override;
+	output wire dec_tlu_icm_clk_override;
+	wire clk_override;
+	wire e4e5_int_clk;
+	wire nmi_fir_type;
+	wire nmi_lsu_load_type;
+	wire nmi_lsu_store_type;
+	wire nmi_int_detected_f;
+	wire nmi_lsu_load_type_f;
+	wire nmi_lsu_store_type_f;
+	wire allow_dbg_halt_csr_write;
+	wire dbg_cmd_done_ns;
+	wire i_cpu_run_req_d1_raw;
+	wire debug_mode_status;
+	wire lsu_single_ecc_error_r_d1;
+	wire sel_npc_r;
+	wire sel_npc_resume;
+	wire ce_int;
+	wire nmi_in_debug_mode;
+	wire dpc_capture_npc;
+	wire dpc_capture_pc;
+	wire tdata_load;
+	wire tdata_opcode;
+	wire tdata_action;
+	wire perfcnt_halted;
+	wire tdata_chain;
+	wire tdata_kill_write;
+	wire reset_delayed;
+	wire reset_detect;
+	wire reset_detected;
+	wire wr_mstatus_r;
+	wire wr_mtvec_r;
+	wire wr_mcyclel_r;
+	wire wr_mcycleh_r;
+	wire wr_minstretl_r;
+	wire wr_minstreth_r;
+	wire wr_mscratch_r;
+	wire wr_mepc_r;
+	wire wr_mcause_r;
+	wire wr_mscause_r;
+	wire wr_mtval_r;
+	wire wr_mrac_r;
+	wire wr_meihap_r;
+	wire wr_meicurpl_r;
+	wire wr_meipt_r;
+	wire wr_dcsr_r;
+	wire wr_dpc_r;
+	wire wr_meicidpl_r;
+	wire wr_meivt_r;
+	wire wr_meicpct_r;
+	wire wr_micect_r;
+	wire wr_miccmect_r;
+	wire wr_mfdht_r;
+	wire wr_mfdhs_r;
+	wire wr_mdccmect_r;
+	wire wr_mhpme3_r;
+	wire wr_mhpme4_r;
+	wire wr_mhpme5_r;
+	wire wr_mhpme6_r;
+	wire wr_mpmc_r;
+	wire [1:1] mpmc_b_ns;
+	wire [1:1] mpmc;
+	wire [1:1] mpmc_b;
+	wire set_mie_pmu_fw_halt;
+	wire fw_halted_ns;
+	wire fw_halted;
+	wire wr_mcountinhibit_r;
+	wire [6:0] mcountinhibit;
+	wire wr_mtsel_r;
+	wire wr_mtdata1_t0_r;
+	wire wr_mtdata1_t1_r;
+	wire wr_mtdata1_t2_r;
+	wire wr_mtdata1_t3_r;
+	wire wr_mtdata2_t0_r;
+	wire wr_mtdata2_t1_r;
+	wire wr_mtdata2_t2_r;
+	wire wr_mtdata2_t3_r;
+	wire [31:0] mtdata2_t0;
+	wire [31:0] mtdata2_t1;
+	wire [31:0] mtdata2_t2;
+	wire [31:0] mtdata2_t3;
+	wire [31:0] mtdata2_tsel_out;
+	wire [31:0] mtdata1_tsel_out;
+	wire [9:0] mtdata1_t0_ns;
+	wire [9:0] mtdata1_t0;
+	wire [9:0] mtdata1_t1_ns;
+	wire [9:0] mtdata1_t1;
+	wire [9:0] mtdata1_t2_ns;
+	wire [9:0] mtdata1_t2;
+	wire [9:0] mtdata1_t3_ns;
+	wire [9:0] mtdata1_t3;
+	wire [9:0] tdata_wrdata_r;
+	wire [1:0] mtsel_ns;
+	wire [1:0] mtsel;
+	wire tlu_i0_kill_writeb_r;
+	wire [1:0] mstatus_ns;
+	wire [1:0] mstatus;
+	wire [1:0] mfdhs_ns;
+	wire [1:0] mfdhs;
+	wire [31:0] force_halt_ctr;
+	wire [31:0] force_halt_ctr_f;
+	wire force_halt;
+	wire [5:0] mfdht;
+	wire [5:0] mfdht_ns;
+	wire mstatus_mie_ns;
+	wire [30:0] mtvec_ns;
+	wire [30:0] mtvec;
+	wire [15:2] dcsr_ns;
+	wire [15:2] dcsr;
+	wire [5:0] mip_ns;
+	wire [5:0] mip;
+	wire [5:0] mie_ns;
+	wire [5:0] mie;
+	wire [31:0] mcyclel_ns;
+	wire [31:0] mcyclel;
+	wire [31:0] mcycleh_ns;
+	wire [31:0] mcycleh;
+	wire [31:0] minstretl_ns;
+	wire [31:0] minstretl;
+	wire [31:0] minstreth_ns;
+	wire [31:0] minstreth;
+	wire [31:0] micect_ns;
+	wire [31:0] micect;
+	wire [31:0] miccmect_ns;
+	wire [31:0] miccmect;
+	wire [31:0] mdccmect_ns;
+	wire [31:0] mdccmect;
+	wire [26:0] micect_inc;
+	wire [26:0] miccmect_inc;
+	wire [26:0] mdccmect_inc;
+	wire [31:0] mscratch;
+	wire [31:0] mhpmc3;
+	wire [31:0] mhpmc3_ns;
+	wire [31:0] mhpmc4;
+	wire [31:0] mhpmc4_ns;
+	wire [31:0] mhpmc5;
+	wire [31:0] mhpmc5_ns;
+	wire [31:0] mhpmc6;
+	wire [31:0] mhpmc6_ns;
+	wire [31:0] mhpmc3h;
+	wire [31:0] mhpmc3h_ns;
+	wire [31:0] mhpmc4h;
+	wire [31:0] mhpmc4h_ns;
+	wire [31:0] mhpmc5h;
+	wire [31:0] mhpmc5h_ns;
+	wire [31:0] mhpmc6h;
+	wire [31:0] mhpmc6h_ns;
+	wire [9:0] mhpme3;
+	wire [9:0] mhpme4;
+	wire [9:0] mhpme5;
+	wire [9:0] mhpme6;
+	wire [31:0] mrac;
+	wire [9:2] meihap;
+	wire [31:10] meivt;
+	wire [3:0] meicurpl_ns;
+	wire [3:0] meicurpl;
+	wire [3:0] meicidpl_ns;
+	wire [3:0] meicidpl;
+	wire [3:0] meipt_ns;
+	wire [3:0] meipt;
+	wire [31:0] mdseac;
+	wire mdseac_locked_ns;
+	wire mdseac_locked_f;
+	wire mdseac_en;
+	wire nmi_lsu_detected;
+	wire [31:1] mepc_ns;
+	wire [31:1] mepc;
+	wire [31:1] dpc_ns;
+	wire [31:1] dpc;
+	wire [31:0] mcause_ns;
+	wire [31:0] mcause;
+	wire [3:0] mscause_ns;
+	wire [3:0] mscause;
+	wire [3:0] mscause_type;
+	wire [31:0] mtval_ns;
+	wire [31:0] mtval;
+	wire dec_pause_state_f;
+	wire dec_tlu_wr_pause_r_d1;
+	wire pause_expired_r;
+	wire pause_expired_wb;
+	wire tlu_flush_lower_r;
+	wire tlu_flush_lower_r_d1;
+	wire [31:1] tlu_flush_path_r;
+	wire [31:1] tlu_flush_path_r_d1;
+	wire i0_valid_wb;
+	wire tlu_i0_commit_cmt;
+	wire [31:1] vectored_path;
+	wire [31:1] interrupt_path;
+	wire [16:0] dicawics_ns;
+	wire [16:0] dicawics;
+	wire wr_dicawics_r;
+	wire wr_dicad0_r;
+	wire wr_dicad1_r;
+	wire wr_dicad0h_r;
+	wire [31:0] dicad0_ns;
+	wire [31:0] dicad0;
+	wire [31:0] dicad0h_ns;
+	wire [31:0] dicad0h;
+	wire [6:0] dicad1_ns;
+	wire [6:0] dicad1_raw;
+	wire [31:0] dicad1;
+	wire ebreak_r;
+	wire ebreak_to_debug_mode_r;
+	wire ecall_r;
+	wire illegal_r;
+	wire mret_r;
+	wire inst_acc_r;
+	wire fence_i_r;
+	wire ic_perr_r;
+	wire iccm_sbecc_r;
+	wire ebreak_to_debug_mode_r_d1;
+	wire kill_ebreak_count_r;
+	wire inst_acc_second_r;
+	wire ce_int_ready;
+	wire ext_int_ready;
+	wire timer_int_ready;
+	wire soft_int_ready;
+	wire int_timer0_int_ready;
+	wire int_timer1_int_ready;
+	wire mhwakeup_ready;
+	wire take_ext_int;
+	wire take_ce_int;
+	wire take_timer_int;
+	wire take_soft_int;
+	wire take_int_timer0_int;
+	wire take_int_timer1_int;
+	wire take_nmi;
+	wire take_nmi_r_d1;
+	wire int_timer0_int_possible;
+	wire int_timer1_int_possible;
+	wire i0_exception_valid_r;
+	wire interrupt_valid_r;
+	wire i0_exception_valid_r_d1;
+	wire interrupt_valid_r_d1;
+	wire exc_or_int_valid_r;
+	wire exc_or_int_valid_r_d1;
+	wire mdccme_ce_req;
+	wire miccme_ce_req;
+	wire mice_ce_req;
+	wire synchronous_flush_r;
+	wire [4:0] exc_cause_r;
+	wire [4:0] exc_cause_wb;
+	wire mcyclel_cout;
+	wire mcyclel_cout_f;
+	wire mcyclela_cout;
+	wire [31:0] mcyclel_inc;
+	wire [31:0] mcycleh_inc;
+	wire minstretl_cout;
+	wire minstretl_cout_f;
+	wire minstret_enable;
+	wire minstretl_cout_ns;
+	wire minstretl_couta;
+	wire [31:0] minstretl_inc;
+	wire [31:0] minstretl_read;
+	wire [31:0] minstreth_inc;
+	wire [31:0] minstreth_read;
+	wire [31:1] pc_r;
+	wire [31:1] pc_r_d1;
+	wire [31:1] npc_r;
+	wire [31:1] npc_r_d1;
+	wire valid_csr;
+	wire rfpc_i0_r;
+	wire lsu_i0_rfnpc_r;
+	wire dec_tlu_br0_error_r;
+	wire dec_tlu_br0_start_error_r;
+	wire dec_tlu_br0_v_r;
+	wire lsu_i0_exc_r;
+	wire lsu_i0_exc_r_raw;
+	wire lsu_exc_ma_r;
+	wire lsu_exc_acc_r;
+	wire lsu_exc_st_r;
+	wire lsu_exc_valid_r;
+	wire lsu_exc_valid_r_raw;
+	wire lsu_exc_valid_r_d1;
+	wire lsu_i0_exc_r_d1;
+	wire block_interrupts;
+	wire i0_trigger_eval_r;
+	wire request_debug_mode_r;
+	wire request_debug_mode_r_d1;
+	wire request_debug_mode_done;
+	wire request_debug_mode_done_f;
+	wire take_halt;
+	wire halt_taken;
+	wire halt_taken_f;
+	wire internal_dbg_halt_mode;
+	wire dbg_tlu_halted_f;
+	wire take_reset;
+	wire dbg_tlu_halted;
+	wire core_empty;
+	wire lsu_idle_any_f;
+	wire ifu_miss_state_idle_f;
+	wire resume_ack_ns;
+	wire debug_halt_req_f;
+	wire debug_resume_req_f_raw;
+	wire debug_resume_req_f;
+	wire enter_debug_halt_req;
+	wire dcsr_single_step_done;
+	wire dcsr_single_step_done_f;
+	wire debug_halt_req_d1;
+	wire debug_halt_req_ns;
+	wire dcsr_single_step_running;
+	wire dcsr_single_step_running_f;
+	wire internal_dbg_halt_timers;
+	wire [3:0] i0_trigger_r;
+	wire [3:0] trigger_action;
+	wire [3:0] trigger_enabled;
+	wire [3:0] i0_trigger_chain_masked_r;
+	wire i0_trigger_hit_r;
+	wire i0_trigger_hit_raw_r;
+	wire i0_trigger_action_r;
+	wire trigger_hit_r_d1;
+	wire mepc_trigger_hit_sel_pc_r;
+	wire [3:0] update_hit_bit_r;
+	wire [3:0] i0_iside_trigger_has_pri_r;
+	wire [3:0] i0trigger_qual_r;
+	wire [3:0] i0_lsu_trigger_has_pri_r;
+	wire cpu_halt_status;
+	wire cpu_halt_ack;
+	wire cpu_run_ack;
+	wire ext_halt_pulse;
+	wire i_cpu_halt_req_d1;
+	wire i_cpu_run_req_d1;
+	wire inst_acc_r_raw;
+	wire trigger_hit_dmode_r;
+	wire trigger_hit_dmode_r_d1;
+	wire [9:0] mcgc;
+	wire [9:0] mcgc_ns;
+	wire [9:0] mcgc_int;
+	wire [18:0] mfdc;
+	wire i_cpu_halt_req_sync_qual;
+	wire i_cpu_run_req_sync_qual;
+	wire pmu_fw_halt_req_ns;
+	wire pmu_fw_halt_req_f;
+	wire int_timer_stalled;
+	wire fw_halt_req;
+	wire enter_pmu_fw_halt_req;
+	wire pmu_fw_tlu_halted;
+	wire pmu_fw_tlu_halted_f;
+	wire internal_pmu_fw_halt_mode;
+	wire internal_pmu_fw_halt_mode_f;
+	wire int_timer0_int_hold;
+	wire int_timer1_int_hold;
+	wire int_timer0_int_hold_f;
+	wire int_timer1_int_hold_f;
+	wire nmi_int_delayed;
+	wire nmi_int_detected;
+	wire [3:0] trigger_execute;
+	wire [3:0] trigger_data;
+	wire [3:0] trigger_store;
+	wire dec_tlu_pmu_fw_halted;
+	wire mpc_run_state_ns;
+	wire debug_brkpt_status_ns;
+	wire mpc_debug_halt_ack_ns;
+	wire mpc_debug_run_ack_ns;
+	wire dbg_halt_state_ns;
+	wire dbg_run_state_ns;
+	wire dbg_halt_state_f;
+	wire mpc_debug_halt_req_sync_f;
+	wire mpc_debug_run_req_sync_f;
+	wire mpc_halt_state_f;
+	wire mpc_halt_state_ns;
+	wire mpc_run_state_f;
+	wire debug_brkpt_status_f;
+	wire mpc_debug_halt_ack_f;
+	wire mpc_debug_run_ack_f;
+	wire dbg_run_state_f;
+	wire mpc_debug_halt_req_sync_pulse;
+	wire mpc_debug_run_req_sync_pulse;
+	wire debug_brkpt_valid;
+	wire debug_halt_req;
+	wire debug_resume_req;
+	wire dec_tlu_mpc_halted_only_ns;
+	wire take_ext_int_start;
+	wire ext_int_freeze;
+	wire take_ext_int_start_d1;
+	wire take_ext_int_start_d2;
+	wire take_ext_int_start_d3;
+	wire ext_int_freeze_d1;
+	wire csr_meicpct;
+	wire ignore_ext_int_due_to_lsu_stall;
+	wire mcause_sel_nmi_store;
+	wire mcause_sel_nmi_load;
+	wire mcause_sel_nmi_ext;
+	wire fast_int_meicpct;
+	wire [1:0] mcause_fir_error_type;
+	wire dbg_halt_req_held_ns;
+	wire dbg_halt_req_held;
+	wire dbg_halt_req_final;
+	wire iccm_repair_state_ns;
+	wire iccm_repair_state_d1;
+	wire iccm_repair_state_rfnpc;
+	wire [31:0] dec_timer_rddata_d;
+	wire dec_timer_read_d;
+	wire dec_timer_t0_pulse;
+	wire dec_timer_t1_pulse;
+	wire csr_mitctl0;
+	wire csr_mitctl1;
+	wire csr_mitb0;
+	wire csr_mitb1;
+	wire csr_mitcnt0;
+	wire csr_mitcnt1;
+	wire nmi_int_sync;
+	wire timer_int_sync;
+	wire soft_int_sync;
+	wire i_cpu_halt_req_sync;
+	wire i_cpu_run_req_sync;
+	wire mpc_debug_halt_req_sync;
+	wire mpc_debug_run_req_sync;
+	wire mpc_debug_halt_req_sync_raw;
+	wire csr_wr_clk;
+	wire e4e5_clk;
+	wire e4_valid;
+	wire e5_valid;
+	wire e4e5_valid;
+	wire internal_dbg_halt_mode_f;
+	wire internal_dbg_halt_mode_f2;
+	wire lsu_pmu_load_external_r;
+	wire lsu_pmu_store_external_r;
+	wire dec_tlu_flush_noredir_r_d1;
+	wire dec_tlu_flush_pause_r_d1;
+	wire lsu_single_ecc_error_r;
+	wire [31:0] lsu_error_pkt_addr_r;
+	wire mcyclel_cout_in;
+	wire i0_valid_no_ebreak_ecall_r;
+	wire minstret_enable_f;
+	wire sel_exu_npc_r;
+	wire sel_flush_npc_r;
+	wire sel_hold_npc_r;
+	wire pc0_valid_r;
+	wire [15:0] mfdc_int;
+	wire [15:0] mfdc_ns;
+	wire [31:0] mrac_in;
+	wire [31:27] csr_sat;
+	wire [8:6] dcsr_cause;
+	wire enter_debug_halt_req_le;
+	wire dcsr_cause_upgradeable;
+	wire icache_rd_valid;
+	wire icache_wr_valid;
+	wire icache_rd_valid_f;
+	wire icache_wr_valid_f;
+	wire [3:0] mhpmc_inc_r;
+	wire [3:0] mhpmc_inc_r_d1;
+	wire [39:0] mhpme_vec;
+	wire mhpmc3_wr_en0;
+	wire mhpmc3_wr_en1;
+	wire mhpmc3_wr_en;
+	wire mhpmc4_wr_en0;
+	wire mhpmc4_wr_en1;
+	wire mhpmc4_wr_en;
+	wire mhpmc5_wr_en0;
+	wire mhpmc5_wr_en1;
+	wire mhpmc5_wr_en;
+	wire mhpmc6_wr_en0;
+	wire mhpmc6_wr_en1;
+	wire mhpmc6_wr_en;
+	wire mhpmc3h_wr_en0;
+	wire mhpmc3h_wr_en;
+	wire mhpmc4h_wr_en0;
+	wire mhpmc4h_wr_en;
+	wire mhpmc5h_wr_en0;
+	wire mhpmc5h_wr_en;
+	wire mhpmc6h_wr_en0;
+	wire mhpmc6h_wr_en;
+	wire [63:0] mhpmc3_incr;
+	wire [63:0] mhpmc4_incr;
+	wire [63:0] mhpmc5_incr;
+	wire [63:0] mhpmc6_incr;
+	wire perfcnt_halted_d1;
+	wire zero_event_r;
+	wire [3:0] perfcnt_during_sleep;
+	wire [9:0] event_r;
+	wire [3:0] pmu_i0_itype_qual;
+	wire csr_mfdht;
+	wire csr_mfdhs;
+	wire csr_misa;
+	wire csr_mvendorid;
+	wire csr_marchid;
+	wire csr_mimpid;
+	wire csr_mhartid;
+	wire csr_mstatus;
+	wire csr_mtvec;
+	wire csr_mip;
+	wire csr_mie;
+	wire csr_mcyclel;
+	wire csr_mcycleh;
+	wire csr_minstretl;
+	wire csr_minstreth;
+	wire csr_mscratch;
+	wire csr_mepc;
+	wire csr_mcause;
+	wire csr_mscause;
+	wire csr_mtval;
+	wire csr_mrac;
+	wire csr_dmst;
+	wire csr_mdseac;
+	wire csr_meihap;
+	wire csr_meivt;
+	wire csr_meipt;
+	wire csr_meicurpl;
+	wire csr_meicidpl;
+	wire csr_dcsr;
+	wire csr_mcgc;
+	wire csr_mfdc;
+	wire csr_dpc;
+	wire csr_mtsel;
+	wire csr_mtdata1;
+	wire csr_mtdata2;
+	wire csr_mhpmc3;
+	wire csr_mhpmc4;
+	wire csr_mhpmc5;
+	wire csr_mhpmc6;
+	wire csr_mhpmc3h;
+	wire csr_mhpmc4h;
+	wire csr_mhpmc5h;
+	wire csr_mhpmc6h;
+	wire csr_mhpme3;
+	wire csr_mhpme4;
+	wire csr_mhpme5;
+	wire csr_mhpme6;
+	wire csr_mcountinhibit;
+	wire csr_mpmc;
+	wire csr_micect;
+	wire csr_miccmect;
+	wire csr_mdccmect;
+	wire csr_dicawics;
+	wire csr_dicad0h;
+	wire csr_dicad0;
+	wire csr_dicad1;
+	wire csr_dicago;
+	wire presync;
+	wire postsync;
+	wire legal;
+	wire dec_csr_wen_r_mod;
+	wire flush_clkvalid;
+	wire sel_fir_addr;
+	wire wr_mie_r;
+	wire mtval_capture_pc_r;
+	wire mtval_capture_pc_plus2_r;
+	wire mtval_capture_inst_r;
+	wire mtval_capture_lsu_r;
+	wire mtval_clear_r;
+	wire wr_mcgc_r;
+	wire wr_mfdc_r;
+	wire wr_mdeau_r;
+	wire trigger_hit_for_dscr_cause_r_d1;
+	wire conditionally_illegal;
+	wire [3:0] ifu_mscause;
+	wire ifu_ic_error_start_f;
+	wire ifu_iccm_rd_ecc_single_err_f;
+	eb1_dec_timer_ctl #(.pt(pt)) int_timers(
+		.clk(clk),
+		.free_l2clk(free_l2clk),
+		.csr_wr_clk(csr_wr_clk),
+		.rst_l(rst_l),
+		.dec_csr_wen_r_mod(dec_csr_wen_r_mod),
+		.dec_csr_wraddr_r(dec_csr_wraddr_r),
+		.dec_csr_wrdata_r(dec_csr_wrdata_r),
+		.csr_mitctl0(csr_mitctl0),
+		.csr_mitctl1(csr_mitctl1),
+		.csr_mitb0(csr_mitb0),
+		.csr_mitb1(csr_mitb1),
+		.csr_mitcnt0(csr_mitcnt0),
+		.csr_mitcnt1(csr_mitcnt1),
+		.dec_pause_state(dec_pause_state),
+		.dec_tlu_pmu_fw_halted(dec_tlu_pmu_fw_halted),
+		.internal_dbg_halt_timers(internal_dbg_halt_timers),
+		.dec_timer_rddata_d(dec_timer_rddata_d),
+		.dec_timer_read_d(dec_timer_read_d),
+		.dec_timer_t0_pulse(dec_timer_t0_pulse),
+		.dec_timer_t1_pulse(dec_timer_t1_pulse),
+		.scan_mode(scan_mode)
+	);
+	assign clk_override = dec_tlu_dec_clk_override;
+	rvsyncss #(.WIDTH(7)) syncro_ff(
+		.rst_l(rst_l),
+		.clk(free_clk),
+		.din({nmi_int, timer_int, soft_int, i_cpu_halt_req, i_cpu_run_req, mpc_debug_halt_req, mpc_debug_run_req}),
+		.dout({nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync_raw, mpc_debug_run_req_sync})
+	);
+	rvoclkhdr csrwr_r_cgc(
+		.en(dec_csr_wen_r_mod | clk_override),
+		.l1clk(csr_wr_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign e4_valid = dec_tlu_i0_valid_r;
+	assign e4e5_valid = e4_valid | e5_valid;
+	assign flush_clkvalid = ((((((((internal_dbg_halt_mode_f | i_cpu_run_req_d1) | interrupt_valid_r) | interrupt_valid_r_d1) | reset_delayed) | pause_expired_r) | pause_expired_wb) | ic_perr_r) | iccm_sbecc_r) | clk_override;
+	rvoclkhdr e4e5_cgc(
+		.en(e4e5_valid | clk_override),
+		.l1clk(e4e5_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr e4e5_int_cgc(
+		.en(e4e5_valid | flush_clkvalid),
+		.l1clk(e4e5_int_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvdffie #(.WIDTH(11)) freeff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({ifu_ic_error_start, ifu_iccm_rd_ecc_single_err, iccm_repair_state_ns, e4_valid, internal_dbg_halt_mode, lsu_pmu_load_external_m, lsu_pmu_store_external_m, tlu_flush_lower_r, tlu_i0_kill_writeb_r, internal_dbg_halt_mode_f, force_halt}),
+		.dout({ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f, iccm_repair_state_d1, e5_valid, internal_dbg_halt_mode_f, lsu_pmu_load_external_r, lsu_pmu_store_external_r, tlu_flush_lower_r_d1, dec_tlu_i0_kill_writeb_wb, internal_dbg_halt_mode_f2, dec_tlu_force_halt})
+	);
+	assign dec_tlu_i0_kill_writeb_r = tlu_i0_kill_writeb_r;
+	assign nmi_int_detected = (((nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected) | (nmi_int_detected_f & ~take_nmi_r_d1)) | nmi_fir_type;
+	assign nmi_lsu_load_type = ((nmi_lsu_detected & lsu_imprecise_error_load_any) & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1);
+	assign nmi_lsu_store_type = ((nmi_lsu_detected & lsu_imprecise_error_store_any) & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_store_type_f & ~take_nmi_r_d1);
+	assign nmi_fir_type = (~nmi_int_detected_f & take_ext_int_start_d3) & |lsu_fir_error[1:0];
+	assign nmi_lsu_detected = (~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any)) & ~nmi_fir_type;
+	localparam MSTATUS_MIE = 0;
+	localparam MIP_MCEIP = 5;
+	localparam MIP_MITIP0 = 4;
+	localparam MIP_MITIP1 = 3;
+	localparam MIP_MEIP = 2;
+	localparam MIP_MTIP = 1;
+	localparam MIP_MSIP = 0;
+	localparam MIE_MCEIE = 5;
+	localparam MIE_MITIE0 = 4;
+	localparam MIE_MITIE1 = 3;
+	localparam MIE_MEIE = 2;
+	localparam MIE_MTIE = 1;
+	localparam MIE_MSIE = 0;
+	localparam DCSR_EBREAKM = 15;
+	localparam DCSR_STEPIE = 11;
+	localparam DCSR_STOPC = 10;
+	localparam DCSR_STEP = 2;
+	assign reset_delayed = reset_detect ^ reset_detected;
+	assign mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1;
+	rvdffie #(.WIDTH(16)) mpvhalt_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({1'b1, reset_detect, nmi_int_sync, nmi_int_detected, nmi_lsu_load_type, nmi_lsu_store_type, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_halt_state_ns, mpc_run_state_ns, debug_brkpt_status_ns, mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, dbg_halt_state_ns, dbg_run_state_ns, dec_tlu_mpc_halted_only_ns}),
+		.dout({reset_detect, reset_detected, nmi_int_delayed, nmi_int_detected_f, nmi_lsu_load_type_f, nmi_lsu_store_type_f, mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, mpc_halt_state_f, mpc_run_state_f, debug_brkpt_status_f, mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_halt_state_f, dbg_run_state_f, dec_tlu_mpc_halted_only})
+	);
+	assign mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f;
+	assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f;
+	assign mpc_halt_state_ns = ((mpc_halt_state_f | mpc_debug_halt_req_sync_pulse) | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync;
+	assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);
+	assign dbg_halt_state_ns = (dbg_halt_state_f | (((dbg_halt_req_final | dcsr_single_step_done_f) | trigger_hit_dmode_r_d1) | ebreak_to_debug_mode_r_d1)) & ~dbg_resume_req;
+	assign dbg_run_state_ns = (dbg_run_state_f | dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);
+	assign dec_tlu_mpc_halted_only_ns = ~dbg_halt_state_f & mpc_halt_state_f;
+	assign debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1;
+	assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f);
+	assign mpc_debug_halt_ack_ns = ((mpc_halt_state_f & internal_dbg_halt_mode_f) & mpc_debug_halt_req_sync) & core_empty;
+	assign mpc_debug_run_ack_ns = ((mpc_debug_run_req_sync & ~dbg_halt_state_ns) & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync);
+	assign mpc_debug_halt_ack = mpc_debug_halt_ack_f;
+	assign mpc_debug_run_ack = mpc_debug_run_ack_f;
+	assign debug_brkpt_status = debug_brkpt_status_f;
+	assign dbg_halt_req_held_ns = (dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1;
+	assign dbg_halt_req_final = (dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1;
+	assign debug_halt_req = (((dbg_halt_req_final | mpc_debug_halt_req_sync) | (reset_delayed & ~mpc_reset_run_req)) & ~internal_dbg_halt_mode_f) & ~ext_int_freeze_d1;
+	assign debug_resume_req = ~debug_resume_req_f & ((mpc_run_state_ns & ~dbg_halt_state_ns) | (dbg_run_state_ns & ~mpc_halt_state_ns));
+	assign take_halt = (((((debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r) & ~mret_r) & ~halt_taken_f) & ~dec_tlu_flush_noredir_r_d1) & ~take_reset;
+	assign halt_taken = ((dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1) & ~take_ext_int_start_d1) | (((halt_taken_f & ~dbg_tlu_halted_f) & ~pmu_fw_tlu_halted_f) & ~interrupt_valid_r_d1);
+	assign core_empty = force_halt | ((((((lsu_idle_any & lsu_idle_any_f) & ifu_miss_state_idle) & ifu_miss_state_idle_f) & ~debug_halt_req) & ~debug_halt_req_d1) & ~dec_div_active);
+	assign dec_tlu_core_empty = core_empty;
+	assign enter_debug_halt_req = (((~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f) | trigger_hit_dmode_r_d1) | ebreak_to_debug_mode_r_d1;
+	assign internal_dbg_halt_mode = debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr[DCSR_STEP]));
+	assign allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f;
+	assign debug_halt_req_ns = enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted);
+	assign dbg_tlu_halted = ((debug_halt_req_f & core_empty) & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f);
+	assign resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f) & dbg_run_state_ns;
+	assign dcsr_single_step_done = ((dec_tlu_i0_valid_r & ~dec_tlu_dbg_halted) & dcsr[DCSR_STEP]) & ~rfpc_i0_r;
+	assign dcsr_single_step_running = (debug_resume_req_f & dcsr[DCSR_STEP]) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f);
+	assign dbg_cmd_done_ns = dec_tlu_i0_valid_r & dec_tlu_dbg_halted;
+	assign request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~dec_tlu_flush_lower_wb);
+	assign request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f;
+	rvdffie #(.WIDTH(18)) halt_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({dec_tlu_flush_noredir_r, halt_taken, lsu_idle_any, ifu_miss_state_idle, dbg_tlu_halted, resume_ack_ns, debug_halt_req_ns, debug_resume_req, trigger_hit_dmode_r, dcsr_single_step_done, debug_halt_req, dec_tlu_wr_pause_r, dec_pause_state, request_debug_mode_r, request_debug_mode_done, dcsr_single_step_running, dec_tlu_flush_pause_r, dbg_halt_req_held_ns}),
+		.dout({dec_tlu_flush_noredir_r_d1, halt_taken_f, lsu_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f, dec_tlu_resume_ack, debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_r_d1, dcsr_single_step_done_f, debug_halt_req_d1, dec_tlu_wr_pause_r_d1, dec_pause_state_f, request_debug_mode_r_d1, request_debug_mode_done_f, dcsr_single_step_running_f, dec_tlu_flush_pause_r_d1, dbg_halt_req_held})
+	);
+	assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req;
+	assign dec_tlu_debug_stall = debug_halt_req_f;
+	assign dec_tlu_dbg_halted = dbg_tlu_halted_f;
+	assign dec_tlu_debug_mode = internal_dbg_halt_mode_f;
+	assign dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f;
+	assign dec_tlu_flush_noredir_r = (((take_halt | (fence_i_r & internal_dbg_halt_mode)) | dec_tlu_flush_pause_r) | (i0_trigger_hit_r & trigger_hit_dmode_r)) | take_ext_int_start;
+	assign dec_tlu_flush_extint = take_ext_int_start;
+	assign dec_tlu_flush_pause_r = (dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r) & ~take_ext_int_start;
+	assign pause_expired_r = (((((~dec_pause_state & dec_pause_state_f) & ~(((((((ext_int_ready | ce_int_ready) | timer_int_ready) | soft_int_ready) | int_timer0_int_hold_f) | int_timer1_int_hold_f) | nmi_int_detected) | ext_int_freeze_d1)) & ~interrupt_valid_r_d1) & ~debug_halt_req_f) & ~pmu_fw_halt_req_f) & ~halt_taken_f;
+	assign dec_tlu_flush_leak_one_r = ((dec_tlu_flush_lower_r & dcsr[DCSR_STEP]) & (dec_tlu_resume_ack | dcsr_single_step_running)) & ~dec_tlu_flush_noredir_r;
+	assign dec_tlu_flush_err_r = dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r);
+	assign dec_dbg_cmd_done = dbg_cmd_done_ns;
+	assign dec_dbg_cmd_fail = illegal_r & dec_dbg_cmd_done;
+	localparam MTDATA1_DMODE = 9;
+	localparam MTDATA1_SEL = 7;
+	localparam MTDATA1_ACTION = 6;
+	localparam MTDATA1_CHAIN = 5;
+	localparam MTDATA1_MATCH = 4;
+	localparam MTDATA1_M_ENABLED = 3;
+	localparam MTDATA1_EXE = 2;
+	localparam MTDATA1_ST = 1;
+	localparam MTDATA1_LD = 0;
+	assign trigger_execute[3:0] = {mtdata1_t3[MTDATA1_EXE], mtdata1_t2[MTDATA1_EXE], mtdata1_t1[MTDATA1_EXE], mtdata1_t0[MTDATA1_EXE]};
+	assign trigger_data[3:0] = {mtdata1_t3[MTDATA1_SEL], mtdata1_t2[MTDATA1_SEL], mtdata1_t1[MTDATA1_SEL], mtdata1_t0[MTDATA1_SEL]};
+	assign trigger_store[3:0] = {mtdata1_t3[MTDATA1_ST], mtdata1_t2[MTDATA1_ST], mtdata1_t1[MTDATA1_ST], mtdata1_t0[MTDATA1_ST]};
+	assign trigger_enabled[3:0] = {(mtdata1_t3[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t3[MTDATA1_M_ENABLED], (mtdata1_t2[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t2[MTDATA1_M_ENABLED], (mtdata1_t1[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t1[MTDATA1_M_ENABLED], (mtdata1_t0[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t0[MTDATA1_M_ENABLED]};
+	assign i0_iside_trigger_has_pri_r[3:0] = ~(((trigger_execute[3:0] & trigger_data[3:0]) & {4 {inst_acc_r_raw}}) | {4 {exu_i0_br_error_r | exu_i0_br_start_error_r}});
+	assign i0_lsu_trigger_has_pri_r[3:0] = ~((trigger_store[3:0] & trigger_data[3:0]) & {4 {lsu_i0_exc_r_raw}});
+	assign i0_trigger_eval_r = dec_tlu_i0_valid_r;
+	assign i0trigger_qual_r[3:0] = ((({4 {i0_trigger_eval_r}} & dec_tlu_packet_r[11:8]) & i0_iside_trigger_has_pri_r[3:0]) & i0_lsu_trigger_has_pri_r[3:0]) & trigger_enabled[3:0];
+	assign i0_trigger_r[3:0] = ~{4 {dec_tlu_flush_lower_wb | dec_tlu_dbg_halted}} & i0trigger_qual_r[3:0];
+	assign i0_trigger_chain_masked_r[3:0] = {i0_trigger_r[3] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[2]), i0_trigger_r[2] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[3]), i0_trigger_r[1] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[0]), i0_trigger_r[0] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[1])};
+	assign i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r[3:0];
+	assign i0_trigger_hit_r = i0_trigger_hit_raw_r;
+	assign trigger_action[3:0] = {mtdata1_t3[MTDATA1_ACTION] & mtdata1_t3[MTDATA1_DMODE], (mtdata1_t2[MTDATA1_ACTION] & mtdata1_t2[MTDATA1_DMODE]) & ~mtdata1_t2[MTDATA1_CHAIN], mtdata1_t1[MTDATA1_ACTION] & mtdata1_t1[MTDATA1_DMODE], (mtdata1_t0[MTDATA1_ACTION] & mtdata1_t0[MTDATA1_DMODE]) & ~mtdata1_t0[MTDATA1_CHAIN]};
+	assign update_hit_bit_r[3:0] = {4 {|i0_trigger_r[3:0] & ~rfpc_i0_r}} & {i0_trigger_chain_masked_r[3], i0_trigger_r[2], i0_trigger_chain_masked_r[1], i0_trigger_r[0]};
+	assign i0_trigger_action_r = |(i0_trigger_chain_masked_r[3:0] & trigger_action[3:0]);
+	assign trigger_hit_dmode_r = i0_trigger_hit_r & i0_trigger_action_r;
+	assign mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r;
+	assign i_cpu_halt_req_sync_qual = (i_cpu_halt_req_sync & ~dec_tlu_debug_mode) & ~ext_int_freeze_d1;
+	assign i_cpu_run_req_sync_qual = ((i_cpu_run_req_sync & ~dec_tlu_debug_mode) & pmu_fw_tlu_halted_f) & ~ext_int_freeze_d1;
+	rvdffie #(.WIDTH(10)) exthaltff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, cpu_halt_status, cpu_halt_ack, cpu_run_ack, internal_pmu_fw_halt_mode, pmu_fw_halt_req_ns, pmu_fw_tlu_halted, int_timer0_int_hold, int_timer1_int_hold}),
+		.dout({i_cpu_halt_req_d1, i_cpu_run_req_d1_raw, o_cpu_halt_status, o_cpu_halt_ack, o_cpu_run_ack, internal_pmu_fw_halt_mode_f, pmu_fw_halt_req_f, pmu_fw_tlu_halted_f, int_timer0_int_hold_f, int_timer1_int_hold_f})
+	);
+	assign ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1;
+	assign enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req;
+	assign pmu_fw_halt_req_ns = (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f;
+	assign internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | ((internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1) & ~debug_halt_req_f);
+	assign pmu_fw_tlu_halted = ((((pmu_fw_halt_req_f & core_empty) & halt_taken) & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f;
+	assign cpu_halt_ack = (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (o_cpu_halt_ack & i_cpu_halt_req_sync);
+	assign cpu_halt_status = (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | ((o_cpu_halt_status & ~i_cpu_run_req_d1) & ~internal_dbg_halt_mode_f);
+	assign cpu_run_ack = ((~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (o_cpu_halt_status & i_cpu_run_req_d1_raw)) | (o_cpu_run_ack & i_cpu_run_req_sync);
+	assign debug_mode_status = internal_dbg_halt_mode_f;
+	assign o_debug_mode_status = debug_mode_status;
+	assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | (((((((nmi_int_detected | timer_int_ready) | soft_int_ready) | int_timer0_int_hold_f) | int_timer1_int_hold_f) | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status) & ~i_cpu_halt_req_d1);
+	assign lsu_single_ecc_error_r = lsu_single_ecc_error_incr;
+	assign lsu_error_pkt_addr_r[31:0] = lsu_error_pkt_r[33:2];
+	assign lsu_exc_valid_r_raw = lsu_error_pkt_r[0] & ~dec_tlu_flush_lower_wb;
+	assign lsu_i0_exc_r_raw = lsu_error_pkt_r[0];
+	assign lsu_i0_exc_r = ((lsu_i0_exc_r_raw & lsu_exc_valid_r_raw) & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	assign lsu_exc_valid_r = lsu_i0_exc_r;
+	assign lsu_exc_ma_r = lsu_i0_exc_r & ~lsu_error_pkt_r[38];
+	assign lsu_exc_acc_r = lsu_i0_exc_r & lsu_error_pkt_r[38];
+	assign lsu_exc_st_r = lsu_i0_exc_r & lsu_error_pkt_r[39];
+	assign lsu_i0_rfnpc_r = (dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & (~lsu_error_pkt_r[39] & lsu_error_pkt_r[1]);
+	assign tlu_i0_commit_cmt = (((((dec_tlu_i0_valid_r & ~rfpc_i0_r) & ~lsu_i0_exc_r) & ~inst_acc_r) & ~dec_tlu_dbg_halted) & ~request_debug_mode_r_d1) & ~i0_trigger_hit_r;
+	assign tlu_i0_kill_writeb_r = (((rfpc_i0_r | lsu_i0_exc_r) | inst_acc_r) | (illegal_r & dec_tlu_dbg_halted)) | i0_trigger_hit_r;
+	assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt;
+	assign rfpc_i0_r = ((((dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1) & (exu_i0_br_error_r | exu_i0_br_start_error_r)) | ((ic_perr_r | iccm_sbecc_r) & ~ext_int_freeze_d1)) & ~i0_trigger_hit_r) & ~lsu_i0_rfnpc_r;
+	assign iccm_repair_state_ns = iccm_sbecc_r | (iccm_repair_state_d1 & ~dec_tlu_flush_lower_r);
+	localparam MCPC = 12'h7c2;
+	assign iccm_repair_state_rfnpc = (tlu_i0_commit_cmt & iccm_repair_state_d1) & ~(((((ebreak_r | ecall_r) | mret_r) | take_reset) | illegal_r) | (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC)));
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign dec_tlu_br0_error_r = (exu_i0_br_error_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1;
+			assign dec_tlu_br0_start_error_r = (exu_i0_br_start_error_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1;
+			assign dec_tlu_br0_v_r = ((exu_i0_br_valid_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1) & (~exu_i0_br_mp_r | ~exu_pmu_i0_br_ataken);
+			assign dec_tlu_br0_r_pkt[5:4] = exu_i0_br_hist_r[1:0];
+			assign dec_tlu_br0_r_pkt[3] = dec_tlu_br0_error_r;
+			assign dec_tlu_br0_r_pkt[2] = dec_tlu_br0_start_error_r;
+			assign dec_tlu_br0_r_pkt[6] = dec_tlu_br0_v_r;
+			assign dec_tlu_br0_r_pkt[1] = exu_i0_br_way_r;
+			assign dec_tlu_br0_r_pkt[0] = exu_i0_br_middle_r;
+		end
+		else begin
+			assign dec_tlu_br0_error_r = 1'b0;
+			assign dec_tlu_br0_start_error_r = 1'b0;
+			assign dec_tlu_br0_v_r = 1'b0;
+			assign dec_tlu_br0_r_pkt = {7 {1'sb0}};
+		end
+	endgenerate
+	localparam [3:0] eb1_pkg_EBREAK = 4'b1000;
+	assign ebreak_r = ((((dec_tlu_packet_r[3-:4] == eb1_pkg_EBREAK) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~dcsr[DCSR_EBREAKM]) & ~rfpc_i0_r;
+	localparam [3:0] eb1_pkg_ECALL = 4'b1001;
+	assign ecall_r = (((dec_tlu_packet_r[3-:4] == eb1_pkg_ECALL) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	assign illegal_r = ((~dec_tlu_packet_r[5] & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	localparam [3:0] eb1_pkg_MRET = 4'b1100;
+	assign mret_r = (((dec_tlu_packet_r[3-:4] == eb1_pkg_MRET) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	assign fence_i_r = ((dec_tlu_packet_r[12] & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	assign ic_perr_r = ((ifu_ic_error_start_f & ~ext_int_freeze_d1) & (~internal_dbg_halt_mode_f | dcsr_single_step_running)) & ~internal_pmu_fw_halt_mode_f;
+	assign iccm_sbecc_r = ((ifu_iccm_rd_ecc_single_err_f & ~ext_int_freeze_d1) & (~internal_dbg_halt_mode_f | dcsr_single_step_running)) & ~internal_pmu_fw_halt_mode_f;
+	assign inst_acc_r_raw = dec_tlu_packet_r[16] & dec_tlu_i0_valid_r;
+	assign inst_acc_r = (inst_acc_r_raw & ~rfpc_i0_r) & ~i0_trigger_hit_r;
+	assign inst_acc_second_r = dec_tlu_packet_r[15];
+	assign ebreak_to_debug_mode_r = ((((dec_tlu_packet_r[3-:4] == eb1_pkg_EBREAK) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & dcsr[DCSR_EBREAKM]) & ~rfpc_i0_r;
+	rvdff #(.WIDTH(1)) exctype_wb_ff(
+		.rst_l(rst_l),
+		.clk(e4e5_clk),
+		.din(ebreak_to_debug_mode_r),
+		.dout(ebreak_to_debug_mode_r_d1)
+	);
+	assign dec_tlu_fence_i_r = fence_i_r;
+	assign i0_exception_valid_r = ((((ebreak_r | ecall_r) | illegal_r) | inst_acc_r) & ~rfpc_i0_r) & ~dec_tlu_dbg_halted;
+	assign exc_cause_r[4:0] = (((((((((((((({5 {take_ext_int}} & 5'h0b) | ({5 {take_timer_int}} & 5'h07)) | ({5 {take_soft_int}} & 5'h03)) | ({5 {take_int_timer0_int}} & 5'h1d)) | ({5 {take_int_timer1_int}} & 5'h1c)) | ({5 {take_ce_int}} & 5'h1e)) | ({5 {illegal_r}} & 5'h02)) | ({5 {ecall_r}} & 5'h0b)) | ({5 {inst_acc_r}} & 5'h01)) | ({5 {ebreak_r | i0_trigger_hit_r}} & 5'h03)) | ({5 {lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04)) | ({5 {lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05)) | ({5 {lsu_exc_ma_r & lsu_exc_st_r}} & 5'h06)) | ({5 {lsu_exc_acc_r & lsu_exc_st_r}} & 5'h07)) & ~{5 {take_nmi}};
+	assign mhwakeup_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MEIP]) & mie_ns[MIE_MEIE];
+	assign ext_int_ready = (((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MEIP]) & mie_ns[MIE_MEIE]) & ~ignore_ext_int_due_to_lsu_stall;
+	assign ce_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MCEIP]) & mie_ns[MIE_MCEIE];
+	assign soft_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MSIP]) & mie_ns[MIE_MSIE];
+	assign timer_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MTIP]) & mie_ns[MIE_MTIE];
+	assign int_timer0_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE0];
+	assign int_timer0_int_ready = mip[MIP_MITIP0] & int_timer0_int_possible;
+	assign int_timer1_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE1];
+	assign int_timer1_int_ready = mip[MIP_MITIP1] & int_timer1_int_possible;
+	assign int_timer_stalled = ((dec_csr_stall_int_ff | synchronous_flush_r) | exc_or_int_valid_r_d1) | mret_r;
+	assign int_timer0_int_hold = (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | ((((int_timer0_int_possible & int_timer0_int_hold_f) & ~interrupt_valid_r) & ~take_ext_int_start) & ~internal_dbg_halt_mode_f);
+	assign int_timer1_int_hold = (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | ((((int_timer1_int_possible & int_timer1_int_hold_f) & ~interrupt_valid_r) & ~take_ext_int_start) & ~internal_dbg_halt_mode_f);
+	assign internal_dbg_halt_timers = internal_dbg_halt_mode_f & ~dcsr_single_step_running;
+	assign block_interrupts = ((((((((internal_dbg_halt_mode & (~dcsr_single_step_running | dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode) | i_cpu_halt_req_d1) | take_nmi) | ebreak_to_debug_mode_r) | synchronous_flush_r) | exc_or_int_valid_r_d1) | mret_r) | ext_int_freeze_d1;
+	generate
+		if (pt[1227-:5]) begin
+			assign take_ext_int_start = ext_int_ready & ~block_interrupts;
+			assign ext_int_freeze = ((take_ext_int_start | take_ext_int_start_d1) | take_ext_int_start_d2) | take_ext_int_start_d3;
+			assign take_ext_int = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];
+			assign fast_int_meicpct = csr_meicpct & dec_csr_any_unq_d;
+			assign ignore_ext_int_due_to_lsu_stall = lsu_fastint_stall_any;
+		end
+		else begin
+			assign take_ext_int_start = 1'b0;
+			assign ext_int_freeze = 1'b0;
+			assign ext_int_freeze_d1 = 1'b0;
+			assign take_ext_int_start_d1 = 1'b0;
+			assign take_ext_int_start_d2 = 1'b0;
+			assign take_ext_int_start_d3 = 1'b0;
+			assign fast_int_meicpct = 1'b0;
+			assign ignore_ext_int_due_to_lsu_stall = 1'b0;
+			assign take_ext_int = ext_int_ready & ~block_interrupts;
+		end
+	endgenerate
+	assign take_ce_int = (ce_int_ready & ~ext_int_ready) & ~block_interrupts;
+	assign take_soft_int = ((soft_int_ready & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts;
+	assign take_timer_int = (((timer_int_ready & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts;
+	assign take_int_timer0_int = (((((((int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible) & ~dec_csr_stall_int_ff) & ~timer_int_ready) & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts;
+	assign take_int_timer1_int = ((((((((int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible) & ~dec_csr_stall_int_ff) & ~(int_timer0_int_ready | int_timer0_int_hold_f)) & ~timer_int_ready) & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts;
+	assign take_reset = reset_delayed & mpc_reset_run_req;
+	assign take_nmi = ((((((nmi_int_detected & ~internal_pmu_fw_halt_mode) & (~internal_dbg_halt_mode | (((dcsr_single_step_running_f & dcsr[DCSR_STEPIE]) & ~dec_tlu_i0_valid_r) & ~dcsr_single_step_done_f))) & ~synchronous_flush_r) & ~mret_r) & ~take_reset) & ~ebreak_to_debug_mode_r) & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & |lsu_fir_error[1:0]));
+	assign interrupt_valid_r = (((((take_ext_int | take_timer_int) | take_soft_int) | take_nmi) | take_ce_int) | take_int_timer0_int) | take_int_timer1_int;
+	assign vectored_path[31:1] = {mtvec[30:1], 1'b0} + {25'b0000000000000000000000000, exc_cause_r[4:0], 1'b0};
+	assign interrupt_path[31:1] = (take_nmi ? nmi_vec[31:1] : (mtvec[0] == 1'b1 ? vectored_path[31:1] : {mtvec[30:1], 1'b0}));
+	assign sel_npc_r = (((lsu_i0_rfnpc_r | fence_i_r) | iccm_repair_state_rfnpc) | (i_cpu_run_req_d1 & ~interrupt_valid_r)) | (rfpc_i0_r & ~dec_tlu_i0_valid_r);
+	assign sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r;
+	assign sel_fir_addr = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];
+	assign synchronous_flush_r = ((((((((i0_exception_valid_r | rfpc_i0_r) | lsu_exc_valid_r) | fence_i_r) | lsu_i0_rfnpc_r) | iccm_repair_state_rfnpc) | debug_resume_req_f) | sel_npc_resume) | dec_tlu_wr_pause_r_d1) | i0_trigger_hit_r;
+	assign tlu_flush_lower_r = ((((interrupt_valid_r | mret_r) | synchronous_flush_r) | take_halt) | take_reset) | take_ext_int_start;
+	assign tlu_flush_path_r[31:1] = (take_reset ? rst_vec[31:1] : ((((((({31 {sel_fir_addr}} & lsu_fir_addr[31:1]) | ({31 {~take_nmi & sel_npc_r}} & npc_r[31:1])) | ({31 {((~take_nmi & rfpc_i0_r) & dec_tlu_i0_valid_r) & ~sel_npc_r}} & dec_tlu_i0_pc_r[31:1])) | ({31 {interrupt_valid_r & ~sel_fir_addr}} & interrupt_path[31:1])) | ({31 {(((i0_exception_valid_r | lsu_exc_valid_r) | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r) & ~sel_fir_addr}} & {mtvec[30:1], 1'b0})) | ({31 {~take_nmi & mret_r}} & mepc[31:1])) | ({31 {~take_nmi & debug_resume_req_f}} & dpc[31:1])) | ({31 {~take_nmi & sel_npc_resume}} & npc_r_d1[31:1]));
+	rvdffpcie #(.WIDTH(31)) flush_lower_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(tlu_flush_lower_r),
+		.din({tlu_flush_path_r[31:1]}),
+		.dout({tlu_flush_path_r_d1[31:1]})
+	);
+	assign dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1;
+	assign dec_tlu_flush_lower_r = tlu_flush_lower_r;
+	assign dec_tlu_flush_path_r[31:1] = tlu_flush_path_r[31:1];
+	assign exc_or_int_valid_r = ((lsu_exc_valid_r | i0_exception_valid_r) | interrupt_valid_r) | (i0_trigger_hit_r & ~trigger_hit_dmode_r);
+	rvdffie #(.WIDTH(12)) excinfo_wb_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din({interrupt_valid_r, i0_exception_valid_r, exc_or_int_valid_r, exc_cause_r[4:0], tlu_i0_commit_cmt & ~illegal_r, i0_trigger_hit_r, take_nmi, pause_expired_r}),
+		.dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1, exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1, take_nmi_r_d1, pause_expired_wb})
+	);
+	localparam MISA = 12'h301;
+	localparam MVENDORID = 12'hf11;
+	localparam MARCHID = 12'hf12;
+	localparam MIMPID = 12'hf13;
+	localparam MHARTID = 12'hf14;
+	localparam MSTATUS = 12'h300;
+	assign dec_csr_wen_r_mod = (dec_csr_wen_r & ~i0_trigger_hit_r) & ~rfpc_i0_r;
+	assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS);
+	assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req;
+	assign mstatus_ns[1:0] = ((((({2 {~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) | ({2 {wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0})) | ({2 {mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[1]})) | ({2 {set_mie_pmu_fw_halt}} & {mstatus[1], 1'b1})) | ({2 {wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]})) | ({2 {((~wr_mstatus_r & ~exc_or_int_valid_r) & ~mret_r) & ~set_mie_pmu_fw_halt}} & mstatus[1:0]);
+	assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]);
+	localparam MTVEC = 12'h305;
+	assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC);
+	assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]};
+	rvdffe #(.WIDTH(31)) mtvec_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mtvec_r),
+		.din(mtvec_ns[30:0]),
+		.dout(mtvec[30:0])
+	);
+	localparam MIP = 12'h344;
+	assign ce_int = (mdccme_ce_req | miccme_ce_req) | mice_ce_req;
+	assign mip_ns[5:0] = {ce_int, dec_timer_t0_pulse, dec_timer_t1_pulse, mexintpend, timer_int_sync, soft_int_sync};
+	localparam MIE = 12'h304;
+	assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE);
+	assign mie_ns[5:0] = (wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0]);
+	rvdff #(.WIDTH(6)) mie_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.din(mie_ns[5:0]),
+		.dout(mie[5:0])
+	);
+	localparam MCYCLEL = 12'hb00;
+	assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC];
+	assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL);
+	assign mcyclel_cout_in = ~(((kill_ebreak_count_r | (dec_tlu_dbg_halted & dcsr[DCSR_STOPC])) | dec_tlu_pmu_fw_halted) | mcountinhibit[0]);
+	assign {mcyclela_cout, mcyclel_inc[7:0]} = mcyclel[7:0] + 8'b00000001;
+	assign {mcyclel_cout, mcyclel_inc[31:8]} = mcyclel[31:8] + {23'b00000000000000000000000, mcyclela_cout};
+	assign mcyclel_ns[31:0] = (wr_mcyclel_r ? dec_csr_wrdata_r[31:0] : mcyclel_inc[31:0]);
+	rvdffe #(.WIDTH(24)) mcyclel_bff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(wr_mcyclel_r | (mcyclela_cout & mcyclel_cout_in)),
+		.din(mcyclel_ns[31:8]),
+		.dout(mcyclel[31:8])
+	);
+	rvdffe #(.WIDTH(8)) mcyclel_aff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(wr_mcyclel_r | mcyclel_cout_in),
+		.din(mcyclel_ns[7:0]),
+		.dout(mcyclel[7:0])
+	);
+	localparam MCYCLEH = 12'hb80;
+	assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH);
+	assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0000000000000000000000000000000, mcyclel_cout_f};
+	assign mcycleh_ns[31:0] = (wr_mcycleh_r ? dec_csr_wrdata_r[31:0] : mcycleh_inc[31:0]);
+	rvdffe #(.WIDTH(32)) mcycleh_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(wr_mcycleh_r | mcyclel_cout_f),
+		.din(mcycleh_ns[31:0]),
+		.dout(mcycleh[31:0])
+	);
+	localparam MINSTRETL = 12'hb02;
+	assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~((((ebreak_r | ecall_r) | ebreak_to_debug_mode_r) | illegal_r) | mcountinhibit[2]);
+	assign wr_minstretl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETL);
+	assign {minstretl_couta, minstretl_inc[7:0]} = minstretl[7:0] + 8'b00000001;
+	assign {minstretl_cout, minstretl_inc[31:8]} = minstretl[31:8] + {23'b00000000000000000000000, minstretl_couta};
+	assign minstret_enable = (i0_valid_no_ebreak_ecall_r & tlu_i0_commit_cmt) | wr_minstretl_r;
+	assign minstretl_cout_ns = ((minstretl_cout & ~wr_minstreth_r) & i0_valid_no_ebreak_ecall_r) & ~dec_tlu_dbg_halted;
+	assign minstretl_ns[31:0] = (wr_minstretl_r ? dec_csr_wrdata_r[31:0] : minstretl_inc[31:0]);
+	rvdffe #(.WIDTH(24)) minstretl_bff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_minstretl_r | (minstretl_couta & minstret_enable)),
+		.din(minstretl_ns[31:8]),
+		.dout(minstretl[31:8])
+	);
+	rvdffe #(.WIDTH(8)) minstretl_aff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(minstret_enable),
+		.din(minstretl_ns[7:0]),
+		.dout(minstretl[7:0])
+	);
+	assign minstretl_read[31:0] = minstretl[31:0];
+	localparam MINSTRETH = 12'hb82;
+	assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH);
+	assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0000000000000000000000000000000, minstretl_cout_f};
+	assign minstreth_ns[31:0] = (wr_minstreth_r ? dec_csr_wrdata_r[31:0] : minstreth_inc[31:0]);
+	rvdffe #(.WIDTH(32)) minstreth_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((minstret_enable_f & minstretl_cout_f) | wr_minstreth_r),
+		.din(minstreth_ns[31:0]),
+		.dout(minstreth[31:0])
+	);
+	assign minstreth_read[31:0] = minstreth_inc[31:0];
+	localparam MSCRATCH = 12'h340;
+	assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH);
+	rvdffe #(.WIDTH(32)) mscratch_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mscratch_r),
+		.din(dec_csr_wrdata_r[31:0]),
+		.dout(mscratch[31:0])
+	);
+	localparam MEPC = 12'h341;
+	assign sel_exu_npc_r = (~dec_tlu_dbg_halted & ~tlu_flush_lower_r_d1) & dec_tlu_i0_valid_r;
+	assign sel_flush_npc_r = (~dec_tlu_dbg_halted & tlu_flush_lower_r_d1) & ~dec_tlu_flush_noredir_r_d1;
+	assign sel_hold_npc_r = ~sel_exu_npc_r & ~sel_flush_npc_r;
+	assign npc_r[31:1] = ((({31 {sel_exu_npc_r}} & exu_npc_r[31:1]) | ({31 {~mpc_reset_run_req & reset_delayed}} & rst_vec[31:1])) | ({31 {sel_flush_npc_r}} & tlu_flush_path_r_d1[31:1])) | ({31 {sel_hold_npc_r}} & npc_r_d1[31:1]);
+	rvdffpcie #(.WIDTH(31)) npwbc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((sel_exu_npc_r | sel_flush_npc_r) | reset_delayed),
+		.din(npc_r[31:1]),
+		.dout(npc_r_d1[31:1])
+	);
+	assign pc0_valid_r = ~dec_tlu_dbg_halted & dec_tlu_i0_valid_r;
+	assign pc_r[31:1] = ({31 {pc0_valid_r}} & dec_tlu_i0_pc_r[31:1]) | ({31 {~pc0_valid_r}} & pc_r_d1[31:1]);
+	rvdffpcie #(.WIDTH(31)) pwbc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(pc0_valid_r),
+		.din(pc_r[31:1]),
+		.dout(pc_r_d1[31:1])
+	);
+	assign wr_mepc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEPC);
+	assign mepc_ns[31:1] = ((({31 {(i0_exception_valid_r | lsu_exc_valid_r) | mepc_trigger_hit_sel_pc_r}} & pc_r[31:1]) | ({31 {interrupt_valid_r}} & npc_r[31:1])) | ({31 {wr_mepc_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:1])) | ({31 {~wr_mepc_r & ~exc_or_int_valid_r}} & mepc[31:1]);
+	rvdffe #(.WIDTH(31)) mepc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((((i0_exception_valid_r | lsu_exc_valid_r) | mepc_trigger_hit_sel_pc_r) | interrupt_valid_r) | wr_mepc_r),
+		.din(mepc_ns[31:1]),
+		.dout(mepc[31:1])
+	);
+	localparam MCAUSE = 12'h342;
+	assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE);
+	assign mcause_sel_nmi_store = (exc_or_int_valid_r & take_nmi) & nmi_lsu_store_type;
+	assign mcause_sel_nmi_load = (exc_or_int_valid_r & take_nmi) & nmi_lsu_load_type;
+	assign mcause_sel_nmi_ext = (((exc_or_int_valid_r & take_nmi) & take_ext_int_start_d3) & |lsu_fir_error[1:0]) & ~nmi_int_detected_f;
+	assign mcause_fir_error_type[1:0] = {&lsu_fir_error[1:0], lsu_fir_error[1] & ~lsu_fir_error[0]};
+	assign mcause_ns[31:0] = ((((({32 {mcause_sel_nmi_store}} & 32'hf0000000) | ({32 {mcause_sel_nmi_load}} & 32'hf0000001)) | ({32 {mcause_sel_nmi_ext}} & {30'b111100000000000000010000000000, mcause_fir_error_type[1:0]})) | ({32 {exc_or_int_valid_r & ~take_nmi}} & {interrupt_valid_r, 26'b00000000000000000000000000, exc_cause_r[4:0]})) | ({32 {wr_mcause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:0])) | ({32 {~wr_mcause_r & ~exc_or_int_valid_r}} & mcause[31:0]);
+	rvdffe #(.WIDTH(32)) mcause_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(exc_or_int_valid_r | wr_mcause_r),
+		.din(mcause_ns[31:0]),
+		.dout(mcause[31:0])
+	);
+	localparam MSCAUSE = 12'h7ff;
+	assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE);
+	assign ifu_mscause[3:0] = (dec_tlu_packet_r[14:13] == 2'b00 ? 4'b1001 : {2'b00, dec_tlu_packet_r[14:13]});
+	assign mscause_type[3:0] = ((({4 {lsu_i0_exc_r}} & lsu_error_pkt_r[37:34]) | ({4 {i0_trigger_hit_r}} & 4'b0001)) | ({4 {ebreak_r}} & 4'b0010)) | ({4 {inst_acc_r}} & ifu_mscause[3:0]);
+	assign mscause_ns[3:0] = (({4 {exc_or_int_valid_r}} & mscause_type[3:0]) | ({4 {wr_mscause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[3:0])) | ({4 {~wr_mscause_r & ~exc_or_int_valid_r}} & mscause[3:0]);
+	rvdff #(.WIDTH(4)) mscause_ff(
+		.rst_l(rst_l),
+		.clk(e4e5_int_clk),
+		.din(mscause_ns[3:0]),
+		.dout(mscause[3:0])
+	);
+	localparam MTVAL = 12'h343;
+	assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL);
+	assign mtval_capture_pc_r = (exc_or_int_valid_r & ((ebreak_r | (inst_acc_r & ~inst_acc_second_r)) | mepc_trigger_hit_sel_pc_r)) & ~take_nmi;
+	assign mtval_capture_pc_plus2_r = (exc_or_int_valid_r & (inst_acc_r & inst_acc_second_r)) & ~take_nmi;
+	assign mtval_capture_inst_r = (exc_or_int_valid_r & illegal_r) & ~take_nmi;
+	assign mtval_capture_lsu_r = (exc_or_int_valid_r & lsu_exc_valid_r) & ~take_nmi;
+	assign mtval_clear_r = (((exc_or_int_valid_r & ~mtval_capture_pc_r) & ~mtval_capture_inst_r) & ~mtval_capture_lsu_r) & ~mepc_trigger_hit_sel_pc_r;
+	assign mtval_ns[31:0] = ((((({32 {mtval_capture_pc_r}} & {pc_r[31:1], 1'b0}) | ({32 {mtval_capture_pc_plus2_r}} & {pc_r[31:1] + 31'b0000000000000000000000000000001, 1'b0})) | ({32 {mtval_capture_inst_r}} & dec_illegal_inst[31:0])) | ({32 {mtval_capture_lsu_r}} & lsu_error_pkt_addr_r[31:0])) | ({32 {wr_mtval_r & ~interrupt_valid_r}} & dec_csr_wrdata_r[31:0])) | ({32 {((((~take_nmi & ~wr_mtval_r) & ~mtval_capture_pc_r) & ~mtval_capture_inst_r) & ~mtval_clear_r) & ~mtval_capture_lsu_r}} & mtval[31:0]);
+	rvdffe #(.WIDTH(32)) mtval_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(tlu_flush_lower_r | wr_mtval_r),
+		.din(mtval_ns[31:0]),
+		.dout(mtval[31:0])
+	);
+	localparam MCGC = 12'h7f8;
+	assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC);
+	assign mcgc_ns[9:0] = (wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0]);
+	rvdffe #(.WIDTH(10)) mcgc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mcgc_r),
+		.din(mcgc_ns[9:0]),
+		.dout(mcgc_int[9:0])
+	);
+	assign mcgc[9:0] = {~mcgc_int[9], mcgc_int[8:0]};
+	assign dec_tlu_picio_clk_override = mcgc[9];
+	assign dec_tlu_misc_clk_override = mcgc[8];
+	assign dec_tlu_dec_clk_override = mcgc[7];
+	assign dec_tlu_ifu_clk_override = mcgc[5];
+	assign dec_tlu_lsu_clk_override = mcgc[4];
+	assign dec_tlu_bus_clk_override = mcgc[3];
+	assign dec_tlu_pic_clk_override = mcgc[2];
+	assign dec_tlu_dccm_clk_override = mcgc[1];
+	assign dec_tlu_icm_clk_override = mcgc[0];
+	localparam MFDC = 12'h7f9;
+	assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC);
+	rvdffe #(.WIDTH(16)) mfdc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mfdc_r),
+		.din({mfdc_ns[15:0]}),
+		.dout(mfdc_int[15:0])
+	);
+	generate
+		if (pt[2037-:5] == 1) begin : axi4
+			assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12], dec_csr_wrdata_r[11:7], ~dec_csr_wrdata_r[6], dec_csr_wrdata_r[5:0]};
+			assign mfdc[18:0] = {~mfdc_int[15:13], 3'b000, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0]};
+		end
+		else begin
+			assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12:0]};
+			assign mfdc[18:0] = {~mfdc_int[15:13], 3'b000, mfdc_int[12:0]};
+		end
+	endgenerate
+	assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16];
+	assign dec_tlu_trace_disable = mfdc[12];
+	assign dec_tlu_external_ldfwd_disable = mfdc[11];
+	assign dec_tlu_core_ecc_disable = 1'b1;
+	assign dec_tlu_sideeffect_posted_disable = mfdc[6];
+	assign dec_tlu_bpred_disable = mfdc[3];
+	assign dec_tlu_wb_coalescing_disable = mfdc[2];
+	assign dec_tlu_pipelining_disable = mfdc[0];
+	assign dec_tlu_wr_pause_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC)) & ~interrupt_valid_r) & ~take_ext_int_start;
+	localparam MRAC = 12'h7c0;
+	assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC);
+	assign mrac_in[31:0] = {dec_csr_wrdata_r[31], dec_csr_wrdata_r[30] & ~dec_csr_wrdata_r[31], dec_csr_wrdata_r[29], dec_csr_wrdata_r[28] & ~dec_csr_wrdata_r[29], dec_csr_wrdata_r[27], dec_csr_wrdata_r[26] & ~dec_csr_wrdata_r[27], dec_csr_wrdata_r[25], dec_csr_wrdata_r[24] & ~dec_csr_wrdata_r[25], dec_csr_wrdata_r[23], dec_csr_wrdata_r[22] & ~dec_csr_wrdata_r[23], dec_csr_wrdata_r[21], dec_csr_wrdata_r[20] & ~dec_csr_wrdata_r[21], dec_csr_wrdata_r[19], dec_csr_wrdata_r[18] & ~dec_csr_wrdata_r[19], dec_csr_wrdata_r[17], dec_csr_wrdata_r[16] & ~dec_csr_wrdata_r[17], dec_csr_wrdata_r[15], dec_csr_wrdata_r[14] & ~dec_csr_wrdata_r[15], dec_csr_wrdata_r[13], dec_csr_wrdata_r[12] & ~dec_csr_wrdata_r[13], dec_csr_wrdata_r[11], dec_csr_wrdata_r[10] & ~dec_csr_wrdata_r[11], dec_csr_wrdata_r[9], dec_csr_wrdata_r[8] & ~dec_csr_wrdata_r[9], dec_csr_wrdata_r[7], dec_csr_wrdata_r[6] & ~dec_csr_wrdata_r[7], dec_csr_wrdata_r[5], dec_csr_wrdata_r[4] & ~dec_csr_wrdata_r[5], dec_csr_wrdata_r[3], dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[3], dec_csr_wrdata_r[1], dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[1]};
+	rvdffe #(.WIDTH(32)) mrac_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mrac_r),
+		.din(mrac_in[31:0]),
+		.dout(mrac[31:0])
+	);
+	assign dec_tlu_mrac_ff[31:0] = mrac[31:0];
+	localparam MDEAU = 12'hbc0;
+	assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU);
+	localparam MDSEAC = 12'hfc0;
+	assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r);
+	assign mdseac_en = ((lsu_imprecise_error_store_any | lsu_imprecise_error_load_any) & ~nmi_int_detected_f) & ~mdseac_locked_f;
+	rvdffe #(.WIDTH(32)) mdseac_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(mdseac_en),
+		.din(lsu_imprecise_error_addr_any[31:0]),
+		.dout(mdseac[31:0])
+	);
+	localparam MPMC = 12'h7c6;
+	assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC);
+	assign fw_halt_req = ((wr_mpmc_r & dec_csr_wrdata_r[0]) & ~internal_dbg_halt_mode_f2) & ~ext_int_freeze_d1;
+	assign fw_halted_ns = (fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt;
+	assign mpmc_b_ns[1] = (wr_mpmc_r ? ~dec_csr_wrdata_r[1] : ~mpmc[1]);
+	rvdff #(.WIDTH(1)) mpmc_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.din(mpmc_b_ns[1]),
+		.dout(mpmc_b[1])
+	);
+	assign mpmc[1] = ~mpmc_b[1];
+	localparam MICECT = 12'h7f0;
+	assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26 ? 5'd26 : dec_csr_wrdata_r[31:27]);
+	assign wr_micect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICECT);
+	assign micect_inc[26:0] = micect[26:0] + {26'b00000000000000000000000000, ic_perr_r};
+	assign micect_ns = (wr_micect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {micect[31:27], micect_inc[26:0]});
+	rvdffe #(.WIDTH(32)) micect_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_micect_r | ic_perr_r),
+		.din(micect_ns[31:0]),
+		.dout(micect[31:0])
+	);
+	assign mice_ce_req = |({32'hffffffff << micect[31:27]} & {5'b00000, micect[26:0]});
+	localparam MICCMECT = 12'h7f1;
+	assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT);
+	assign miccmect_inc[26:0] = miccmect[26:0] + {26'b00000000000000000000000000, iccm_sbecc_r | iccm_dma_sb_error};
+	assign miccmect_ns = (wr_miccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {miccmect[31:27], miccmect_inc[26:0]});
+	rvdffe #(.WIDTH(32)) miccmect_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en((wr_miccmect_r | iccm_sbecc_r) | iccm_dma_sb_error),
+		.din(miccmect_ns[31:0]),
+		.dout(miccmect[31:0])
+	);
+	assign miccme_ce_req = |({32'hffffffff << miccmect[31:27]} & {5'b00000, miccmect[26:0]});
+	localparam MDCCMECT = 12'h7f2;
+	assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT);
+	assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b00000000000000000000000000, lsu_single_ecc_error_r_d1};
+	assign mdccmect_ns = (wr_mdccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {mdccmect[31:27], mdccmect_inc[26:0]});
+	rvdffe #(.WIDTH(32)) mdccmect_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(wr_mdccmect_r | lsu_single_ecc_error_r_d1),
+		.din(mdccmect_ns[31:0]),
+		.dout(mdccmect[31:0])
+	);
+	assign mdccme_ce_req = |({32'hffffffff << mdccmect[31:27]} & {5'b00000, mdccmect[26:0]});
+	localparam MFDHT = 12'h7ce;
+	assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT);
+	assign mfdht_ns[5:0] = (wr_mfdht_r ? dec_csr_wrdata_r[5:0] : mfdht[5:0]);
+	rvdffs #(.WIDTH(6)) mfdht_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.en(wr_mfdht_r),
+		.din(mfdht_ns[5:0]),
+		.dout(mfdht[5:0])
+	);
+	localparam MFDHS = 12'h7cf;
+	assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS);
+	assign mfdhs_ns[1:0] = (wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : (dbg_tlu_halted & ~dbg_tlu_halted_f ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0]));
+	rvdffs #(.WIDTH(2)) mfdhs_ff(
+		.rst_l(rst_l),
+		.clk(free_clk),
+		.en(wr_mfdhs_r | dbg_tlu_halted),
+		.din(mfdhs_ns[1:0]),
+		.dout(mfdhs[1:0])
+	);
+	assign force_halt_ctr[31:0] = (debug_halt_req_f ? force_halt_ctr_f[31:0] + 32'b00000000000000000000000000000001 : (dbg_tlu_halted_f ? 32'b00000000000000000000000000000000 : force_halt_ctr_f[31:0]));
+	rvdffe #(.WIDTH(32)) forcehaltctr_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(mfdht[0]),
+		.din(force_halt_ctr[31:0]),
+		.dout(force_halt_ctr_f[31:0])
+	);
+	assign force_halt = mfdht[0] & |(force_halt_ctr_f[31:0] & (32'hffffffff << mfdht[5:1]));
+	localparam MEIVT = 12'hbc8;
+	assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT);
+	rvdffe #(.WIDTH(22)) meivt_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_meivt_r),
+		.din(dec_csr_wrdata_r[31:10]),
+		.dout(meivt[31:10])
+	);
+	localparam MEIHAP = 12'hfc8;
+	assign wr_meihap_r = wr_meicpct_r;
+	rvdffe #(.WIDTH(8)) meihap_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_meihap_r),
+		.din(pic_claimid[7:0]),
+		.dout(meihap[9:2])
+	);
+	assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]};
+	localparam MEICURPL = 12'hbcc;
+	assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL);
+	assign meicurpl_ns[3:0] = (wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0]);
+	rvdff #(.WIDTH(4)) meicurpl_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.din(meicurpl_ns[3:0]),
+		.dout(meicurpl[3:0])
+	);
+	assign dec_tlu_meicurpl[3:0] = meicurpl[3:0];
+	localparam MEICIDPL = 12'hbcb;
+	assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start;
+	assign meicidpl_ns[3:0] = (wr_meicpct_r ? pic_pl[3:0] : (wr_meicidpl_r ? dec_csr_wrdata_r[3:0] : meicidpl[3:0]));
+	localparam MEICPCT = 12'hbca;
+	assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start;
+	localparam MEIPT = 12'hbc9;
+	assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT);
+	assign meipt_ns[3:0] = (wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0]);
+	rvdff #(.WIDTH(4)) meipt_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.din(meipt_ns[3:0]),
+		.dout(meipt[3:0])
+	);
+	assign dec_tlu_meipt[3:0] = meipt[3:0];
+	localparam DCSR = 12'h7b0;
+	assign trigger_hit_for_dscr_cause_r_d1 = trigger_hit_dmode_r_d1 | (trigger_hit_r_d1 & dcsr_single_step_done_f);
+	assign dcsr_cause[8:6] = ((({3 {((dcsr_single_step_done_f & ~ebreak_to_debug_mode_r_d1) & ~trigger_hit_for_dscr_cause_r_d1) & ~debug_halt_req}} & 3'b100) | ({3 {(debug_halt_req & ~ebreak_to_debug_mode_r_d1) & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b011)) | ({3 {ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b001)) | ({3 {trigger_hit_for_dscr_cause_r_d1}} & 3'b010);
+	assign wr_dcsr_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DCSR);
+	assign dcsr_cause_upgradeable = internal_dbg_halt_mode_f & (dcsr[8:6] == 3'b011);
+	assign enter_debug_halt_req_le = enter_debug_halt_req & (~dbg_tlu_halted | dcsr_cause_upgradeable);
+	assign nmi_in_debug_mode = nmi_int_detected_f & internal_dbg_halt_mode_f;
+	assign dcsr_ns[15:2] = (enter_debug_halt_req_le ? {dcsr[15:9], dcsr_cause[8:6], dcsr[5:2]} : (wr_dcsr_r ? {dec_csr_wrdata_r[15], 3'b000, dec_csr_wrdata_r[11:10], 1'b0, dcsr[8:6], 2'b00, nmi_in_debug_mode | dcsr[3], dec_csr_wrdata_r[2]} : {dcsr[15:4], nmi_in_debug_mode, dcsr[2]}));
+	rvdffe #(.WIDTH(14)) dcsr_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(((enter_debug_halt_req_le | wr_dcsr_r) | internal_dbg_halt_mode) | take_nmi),
+		.din(dcsr_ns[15:2]),
+		.dout(dcsr[15:2])
+	);
+	localparam DPC = 12'h7b1;
+	assign wr_dpc_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DPC);
+	assign dpc_capture_npc = (dbg_tlu_halted & ~dbg_tlu_halted_f) & ~request_debug_mode_done;
+	assign dpc_capture_pc = request_debug_mode_r;
+	assign dpc_ns[31:1] = (({31 {(~dpc_capture_pc & ~dpc_capture_npc) & wr_dpc_r}} & dec_csr_wrdata_r[31:1]) | ({31 {dpc_capture_pc}} & pc_r[31:1])) | ({31 {~dpc_capture_pc & dpc_capture_npc}} & npc_r[31:1]);
+	rvdffe #(.WIDTH(31)) dpc_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((wr_dpc_r | dpc_capture_pc) | dpc_capture_npc),
+		.din(dpc_ns[31:1]),
+		.dout(dpc[31:1])
+	);
+	localparam DICAWICS = 12'h7c8;
+	assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]};
+	assign wr_dicawics_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAWICS);
+	rvdffe #(.WIDTH(17)) dicawics_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_dicawics_r),
+		.din(dicawics_ns[16:0]),
+		.dout(dicawics[16:0])
+	);
+	localparam DICAD0 = 12'h7c9;
+	assign dicad0_ns[31:0] = (wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0]);
+	assign wr_dicad0_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD0);
+	rvdffe #(.WIDTH(32)) dicad0_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_dicad0_r | ifu_ic_debug_rd_data_valid),
+		.din(dicad0_ns[31:0]),
+		.dout(dicad0[31:0])
+	);
+	localparam DICAD0H = 12'h7cc;
+	assign dicad0h_ns[31:0] = (wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32]);
+	assign wr_dicad0h_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD0H);
+	rvdffe #(.WIDTH(32)) dicad0h_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid),
+		.din(dicad0h_ns[31:0]),
+		.dout(dicad0h[31:0])
+	);
+	generate
+		if (pt[1125-:5] == 1) begin
+			localparam DICAD1 = 12'h7ca;
+			assign dicad1_ns[6:0] = (wr_dicad1_r ? dec_csr_wrdata_r[6:0] : ifu_ic_debug_rd_data[70:64]);
+			assign wr_dicad1_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD1);
+			rvdffe #(
+				.WIDTH(7),
+				.OVERRIDE(1)
+			) dicad1_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(wr_dicad1_r | ifu_ic_debug_rd_data_valid),
+				.din(dicad1_ns[6:0]),
+				.dout(dicad1_raw[6:0])
+			);
+			assign dicad1[31:0] = {25'b0000000000000000000000000, dicad1_raw[6:0]};
+		end
+		else begin
+			localparam DICAD1 = 12'h7ca;
+			assign dicad1_ns[3:0] = (wr_dicad1_r ? dec_csr_wrdata_r[3:0] : ifu_ic_debug_rd_data[67:64]);
+			assign wr_dicad1_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD1);
+			rvdffs #(.WIDTH(4)) dicad1_ff(
+				.rst_l(rst_l),
+				.clk(free_clk),
+				.en(wr_dicad1_r | ifu_ic_debug_rd_data_valid),
+				.din(dicad1_ns[3:0]),
+				.dout(dicad1_raw[3:0])
+			);
+			assign dicad1[31:0] = {28'b0000000000000000000000000000, dicad1_raw[3:0]};
+		end
+	endgenerate
+	localparam DICAGO = 12'h7cb;
+	generate
+		if (pt[1125-:5] == 1) begin
+			assign dec_tlu_ic_diag_pkt[89:19] = {dicad1[6:0], dicad0h[31:0], dicad0[31:0]};
+		end
+		else assign dec_tlu_ic_diag_pkt[89:19] = {3'b000, dicad1[3:0], dicad0h[31:0], dicad0[31:0]};
+	endgenerate
+	assign dec_tlu_ic_diag_pkt[18:2] = dicawics[16:0];
+	assign icache_rd_valid = (((allow_dbg_halt_csr_write & dec_csr_any_unq_d) & dec_i0_decode_d) & ~dec_csr_wen_unq_d) & (dec_csr_rdaddr_d[11:0] == DICAGO);
+	assign icache_wr_valid = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAGO);
+	assign dec_tlu_ic_diag_pkt[1] = icache_rd_valid_f;
+	assign dec_tlu_ic_diag_pkt[0] = icache_wr_valid_f;
+	localparam MTSEL = 12'h7a0;
+	assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL);
+	assign mtsel_ns[1:0] = (wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0]);
+	rvdff #(.WIDTH(2)) mtsel_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.din(mtsel_ns[1:0]),
+		.dout(mtsel[1:0])
+	);
+	localparam MTDATA1 = 12'h7a1;
+	assign tdata_load = dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[19];
+	assign tdata_opcode = dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[19];
+	assign tdata_action = (dec_csr_wrdata_r[27] & dbg_tlu_halted_f) & dec_csr_wrdata_r[12];
+	assign tdata_chain = (mtsel[0] ? 1'b0 : (mtsel[1] ? dec_csr_wrdata_r[11] & ~(mtdata1_t3[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]) : dec_csr_wrdata_r[11] & ~(mtdata1_t1[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27])));
+	assign tdata_kill_write = (mtsel[1] ? dec_csr_wrdata_r[27] & (~mtdata1_t2[MTDATA1_DMODE] & mtdata1_t2[MTDATA1_CHAIN]) : dec_csr_wrdata_r[27] & (~mtdata1_t0[MTDATA1_DMODE] & mtdata1_t0[MTDATA1_CHAIN]));
+	assign tdata_wrdata_r[9:0] = {dec_csr_wrdata_r[27] & dbg_tlu_halted_f, dec_csr_wrdata_r[20:19], tdata_action, tdata_chain, dec_csr_wrdata_r[7:6], tdata_opcode, dec_csr_wrdata_r[1], tdata_load};
+	assign wr_mtdata1_t0_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b00)) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	assign mtdata1_t0_ns[9:0] = (wr_mtdata1_t0_r ? tdata_wrdata_r[9:0] : {mtdata1_t0[9], update_hit_bit_r[0] | mtdata1_t0[8], mtdata1_t0[7:0]});
+	assign wr_mtdata1_t1_r = (((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b01)) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f)) & ~tdata_kill_write;
+	assign mtdata1_t1_ns[9:0] = (wr_mtdata1_t1_r ? tdata_wrdata_r[9:0] : {mtdata1_t1[9], update_hit_bit_r[1] | mtdata1_t1[8], mtdata1_t1[7:0]});
+	assign wr_mtdata1_t2_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b10)) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	assign mtdata1_t2_ns[9:0] = (wr_mtdata1_t2_r ? tdata_wrdata_r[9:0] : {mtdata1_t2[9], update_hit_bit_r[2] | mtdata1_t2[8], mtdata1_t2[7:0]});
+	assign wr_mtdata1_t3_r = (((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b11)) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f)) & ~tdata_kill_write;
+	assign mtdata1_t3_ns[9:0] = (wr_mtdata1_t3_r ? tdata_wrdata_r[9:0] : {mtdata1_t3[9], update_hit_bit_r[3] | mtdata1_t3[8], mtdata1_t3[7:0]});
+	rvdffe #(.WIDTH(10)) mtdata1_t0_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(trigger_enabled[0] | wr_mtdata1_t0_r),
+		.din(mtdata1_t0_ns[9:0]),
+		.dout(mtdata1_t0[9:0])
+	);
+	rvdffe #(.WIDTH(10)) mtdata1_t1_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(trigger_enabled[1] | wr_mtdata1_t1_r),
+		.din(mtdata1_t1_ns[9:0]),
+		.dout(mtdata1_t1[9:0])
+	);
+	rvdffe #(.WIDTH(10)) mtdata1_t2_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(trigger_enabled[2] | wr_mtdata1_t2_r),
+		.din(mtdata1_t2_ns[9:0]),
+		.dout(mtdata1_t2[9:0])
+	);
+	rvdffe #(.WIDTH(10)) mtdata1_t3_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(trigger_enabled[3] | wr_mtdata1_t3_r),
+		.din(mtdata1_t3_ns[9:0]),
+		.dout(mtdata1_t3[9:0])
+	);
+	assign mtdata1_tsel_out[31:0] = ((({32 {mtsel[1:0] == 2'b00}} & {4'h2, mtdata1_t0[9], 6'b011111, mtdata1_t0[8:7], 6'b000000, mtdata1_t0[6:5], 3'b000, mtdata1_t0[4:3], 3'b000, mtdata1_t0[2:0]}) | ({32 {mtsel[1:0] == 2'b01}} & {4'h2, mtdata1_t1[9], 6'b011111, mtdata1_t1[8:7], 6'b000000, mtdata1_t1[6:5], 3'b000, mtdata1_t1[4:3], 3'b000, mtdata1_t1[2:0]})) | ({32 {mtsel[1:0] == 2'b10}} & {4'h2, mtdata1_t2[9], 6'b011111, mtdata1_t2[8:7], 6'b000000, mtdata1_t2[6:5], 3'b000, mtdata1_t2[4:3], 3'b000, mtdata1_t2[2:0]})) | ({32 {mtsel[1:0] == 2'b11}} & {4'h2, mtdata1_t3[9], 6'b011111, mtdata1_t3[8:7], 6'b000000, mtdata1_t3[6:5], 3'b000, mtdata1_t3[4:3], 3'b000, mtdata1_t3[2:0]});
+	assign trigger_pkt_any[37] = mtdata1_t0[MTDATA1_SEL];
+	assign trigger_pkt_any[36] = mtdata1_t0[MTDATA1_MATCH];
+	assign trigger_pkt_any[35] = mtdata1_t0[MTDATA1_ST];
+	assign trigger_pkt_any[34] = mtdata1_t0[MTDATA1_LD];
+	assign trigger_pkt_any[33] = mtdata1_t0[MTDATA1_EXE];
+	assign trigger_pkt_any[32] = mtdata1_t0[MTDATA1_M_ENABLED];
+	assign trigger_pkt_any[75] = mtdata1_t1[MTDATA1_SEL];
+	assign trigger_pkt_any[74] = mtdata1_t1[MTDATA1_MATCH];
+	assign trigger_pkt_any[73] = mtdata1_t1[MTDATA1_ST];
+	assign trigger_pkt_any[72] = mtdata1_t1[MTDATA1_LD];
+	assign trigger_pkt_any[71] = mtdata1_t1[MTDATA1_EXE];
+	assign trigger_pkt_any[70] = mtdata1_t1[MTDATA1_M_ENABLED];
+	assign trigger_pkt_any[113] = mtdata1_t2[MTDATA1_SEL];
+	assign trigger_pkt_any[112] = mtdata1_t2[MTDATA1_MATCH];
+	assign trigger_pkt_any[111] = mtdata1_t2[MTDATA1_ST];
+	assign trigger_pkt_any[110] = mtdata1_t2[MTDATA1_LD];
+	assign trigger_pkt_any[109] = mtdata1_t2[MTDATA1_EXE];
+	assign trigger_pkt_any[108] = mtdata1_t2[MTDATA1_M_ENABLED];
+	assign trigger_pkt_any[151] = mtdata1_t3[MTDATA1_SEL];
+	assign trigger_pkt_any[150] = mtdata1_t3[MTDATA1_MATCH];
+	assign trigger_pkt_any[149] = mtdata1_t3[MTDATA1_ST];
+	assign trigger_pkt_any[148] = mtdata1_t3[MTDATA1_LD];
+	assign trigger_pkt_any[147] = mtdata1_t3[MTDATA1_EXE];
+	assign trigger_pkt_any[146] = mtdata1_t3[MTDATA1_M_ENABLED];
+	localparam MTDATA2 = 12'h7a2;
+	assign wr_mtdata2_t0_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b00)) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	assign wr_mtdata2_t1_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b01)) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	assign wr_mtdata2_t2_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b10)) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	assign wr_mtdata2_t3_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b11)) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f);
+	rvdffe #(.WIDTH(32)) mtdata2_t0_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mtdata2_t0_r),
+		.din(dec_csr_wrdata_r[31:0]),
+		.dout(mtdata2_t0[31:0])
+	);
+	rvdffe #(.WIDTH(32)) mtdata2_t1_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mtdata2_t1_r),
+		.din(dec_csr_wrdata_r[31:0]),
+		.dout(mtdata2_t1[31:0])
+	);
+	rvdffe #(.WIDTH(32)) mtdata2_t2_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mtdata2_t2_r),
+		.din(dec_csr_wrdata_r[31:0]),
+		.dout(mtdata2_t2[31:0])
+	);
+	rvdffe #(.WIDTH(32)) mtdata2_t3_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mtdata2_t3_r),
+		.din(dec_csr_wrdata_r[31:0]),
+		.dout(mtdata2_t3[31:0])
+	);
+	assign mtdata2_tsel_out[31:0] = ((({32 {mtsel[1:0] == 2'b00}} & mtdata2_t0[31:0]) | ({32 {mtsel[1:0] == 2'b01}} & mtdata2_t1[31:0])) | ({32 {mtsel[1:0] == 2'b10}} & mtdata2_t2[31:0])) | ({32 {mtsel[1:0] == 2'b11}} & mtdata2_t3[31:0]);
+	assign trigger_pkt_any[31-:32] = mtdata2_t0[31:0];
+	assign trigger_pkt_any[69-:32] = mtdata2_t1[31:0];
+	assign trigger_pkt_any[107-:32] = mtdata2_t2[31:0];
+	assign trigger_pkt_any[145-:32] = mtdata2_t3[31:0];
+	localparam MHPME_NOEVENT = 10'd0;
+	localparam MHPME_CLK_ACTIVE = 10'd1;
+	localparam MHPME_ICACHE_HIT = 10'd2;
+	localparam MHPME_ICACHE_MISS = 10'd3;
+	localparam MHPME_INST_COMMIT = 10'd4;
+	localparam MHPME_INST_COMMIT_16B = 10'd5;
+	localparam MHPME_INST_COMMIT_32B = 10'd6;
+	localparam MHPME_INST_ALIGNED = 10'd7;
+	localparam MHPME_INST_DECODED = 10'd8;
+	localparam MHPME_INST_MUL = 10'd9;
+	localparam MHPME_INST_DIV = 10'd10;
+	localparam MHPME_INST_LOAD = 10'd11;
+	localparam MHPME_INST_STORE = 10'd12;
+	localparam MHPME_INST_MALOAD = 10'd13;
+	localparam MHPME_INST_MASTORE = 10'd14;
+	localparam MHPME_INST_ALU = 10'd15;
+	localparam MHPME_INST_CSRREAD = 10'd16;
+	localparam MHPME_INST_CSRRW = 10'd17;
+	localparam MHPME_INST_CSRWRITE = 10'd18;
+	localparam MHPME_INST_EBREAK = 10'd19;
+	localparam MHPME_INST_ECALL = 10'd20;
+	localparam MHPME_INST_FENCE = 10'd21;
+	localparam MHPME_INST_FENCEI = 10'd22;
+	localparam MHPME_INST_MRET = 10'd23;
+	localparam MHPME_INST_BRANCH = 10'd24;
+	localparam MHPME_BRANCH_MP = 10'd25;
+	localparam MHPME_BRANCH_TAKEN = 10'd26;
+	localparam MHPME_BRANCH_NOTP = 10'd27;
+	localparam MHPME_FETCH_STALL = 10'd28;
+	localparam MHPME_DECODE_STALL = 10'd30;
+	localparam MHPME_POSTSYNC_STALL = 10'd31;
+	localparam MHPME_PRESYNC_STALL = 10'd32;
+	localparam MHPME_LSU_SB_WB_STALL = 10'd34;
+	localparam MHPME_DMA_DCCM_STALL = 10'd35;
+	localparam MHPME_DMA_ICCM_STALL = 10'd36;
+	localparam MHPME_EXC_TAKEN = 10'd37;
+	localparam MHPME_TIMER_INT_TAKEN = 10'd38;
+	localparam MHPME_EXT_INT_TAKEN = 10'd39;
+	localparam MHPME_FLUSH_LOWER = 10'd40;
+	localparam MHPME_BR_ERROR = 10'd41;
+	localparam MHPME_IBUS_TRANS = 10'd42;
+	localparam MHPME_DBUS_TRANS = 10'd43;
+	localparam MHPME_DBUS_MA_TRANS = 10'd44;
+	localparam MHPME_IBUS_ERROR = 10'd45;
+	localparam MHPME_DBUS_ERROR = 10'd46;
+	localparam MHPME_IBUS_STALL = 10'd47;
+	localparam MHPME_DBUS_STALL = 10'd48;
+	localparam MHPME_INT_DISABLED = 10'd49;
+	localparam MHPME_INT_STALLED = 10'd50;
+	localparam MHPME_INST_BITMANIP = 10'd54;
+	localparam MHPME_DBUS_LOAD = 10'd55;
+	localparam MHPME_DBUS_STORE = 10'd56;
+	localparam MHPME_SLEEP_CYC = 10'd512;
+	localparam MHPME_DMA_READ_ALL = 10'd513;
+	localparam MHPME_DMA_WRITE_ALL = 10'd514;
+	localparam MHPME_DMA_READ_DCCM = 10'd515;
+	localparam MHPME_DMA_WRITE_DCCM = 10'd516;
+	assign mhpme_vec[9-:10] = mhpme3[9:0];
+	assign mhpme_vec[19-:10] = mhpme4[9:0];
+	assign mhpme_vec[29-:10] = mhpme5[9:0];
+	assign mhpme_vec[39-:10] = mhpme6[9:0];
+	assign pmu_i0_itype_qual[3:0] = dec_tlu_packet_r[3:0] & {4 {tlu_i0_commit_cmt}};
+	localparam [3:0] eb1_pkg_ALU = 4'b0100;
+	localparam [3:0] eb1_pkg_BITMANIPU = 4'b1111;
+	localparam [3:0] eb1_pkg_CONDBR = 4'b1101;
+	localparam [3:0] eb1_pkg_CSRREAD = 4'b0101;
+	localparam [3:0] eb1_pkg_CSRRW = 4'b0111;
+	localparam [3:0] eb1_pkg_CSRWRITE = 4'b0110;
+	localparam [3:0] eb1_pkg_FENCE = 4'b1010;
+	localparam [3:0] eb1_pkg_FENCEI = 4'b1011;
+	localparam [3:0] eb1_pkg_JAL = 4'b1110;
+	localparam [3:0] eb1_pkg_LOAD = 4'b0010;
+	localparam [3:0] eb1_pkg_MUL = 4'b0001;
+	localparam [3:0] eb1_pkg_STORE = 4'b0011;
+	generate
+		genvar i;
+		for (i = 0; i < 4; i = i + 1) assign mhpmc_inc_r[i] = {~mcountinhibit[i + 3]} & ((((((((((((((((((((((((((((((((((((((((((((((((((((((((({mhpme_vec[(i * 10) + 9-:10] == MHPME_CLK_ACTIVE} & 1'b1) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_ICACHE_HIT} & {ifu_pmu_ic_hit})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_ICACHE_MISS} & {ifu_pmu_ic_miss})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT} & {tlu_i0_commit_cmt & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT_16B} & {(tlu_i0_commit_cmt & ~exu_pmu_i0_pc4) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT_32B} & {(tlu_i0_commit_cmt & exu_pmu_i0_pc4) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ALIGNED} & ifu_pmu_instr_aligned)) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_DECODED} & dec_pmu_instr_decoded)) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DECODE_STALL} & {dec_pmu_decode_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MUL} & {pmu_i0_itype_qual == eb1_pkg_MUL})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_DIV} & {(dec_tlu_packet_r[6] & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_LOAD} & {pmu_i0_itype_qual == eb1_pkg_LOAD})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_STORE} & {pmu_i0_itype_qual == eb1_pkg_STORE})) | (({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MALOAD} & {pmu_i0_itype_qual == eb1_pkg_LOAD}) & {dec_tlu_packet_r[4]})) | (({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MASTORE} & {pmu_i0_itype_qual == eb1_pkg_STORE}) & {dec_tlu_packet_r[4]})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ALU} & {pmu_i0_itype_qual == eb1_pkg_ALU})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRREAD} & {pmu_i0_itype_qual == eb1_pkg_CSRREAD})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRWRITE} & {pmu_i0_itype_qual == eb1_pkg_CSRWRITE})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRRW} & {pmu_i0_itype_qual == eb1_pkg_CSRRW})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_EBREAK} & {pmu_i0_itype_qual == eb1_pkg_EBREAK})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ECALL} & {pmu_i0_itype_qual == eb1_pkg_ECALL})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_FENCE} & {pmu_i0_itype_qual == eb1_pkg_FENCE})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_FENCEI} & {pmu_i0_itype_qual == eb1_pkg_FENCEI})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MRET} & {pmu_i0_itype_qual == eb1_pkg_MRET})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_BRANCH} & {(pmu_i0_itype_qual == eb1_pkg_CONDBR) | (pmu_i0_itype_qual == eb1_pkg_JAL)})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_MP} & {(exu_pmu_i0_br_misp & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_TAKEN} & {(exu_pmu_i0_br_ataken & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_NOTP} & {(dec_tlu_packet_r[7] & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_FETCH_STALL} & {ifu_pmu_fetch_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DECODE_STALL} & {dec_pmu_decode_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_POSTSYNC_STALL} & {dec_pmu_postsync_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_PRESYNC_STALL} & {dec_pmu_presync_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_LSU_SB_WB_STALL} & {lsu_store_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_DCCM_STALL} & {dma_dccm_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_ICCM_STALL} & {dma_iccm_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_EXC_TAKEN} & {(i0_exception_valid_r | i0_trigger_hit_r) | lsu_exc_valid_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_TIMER_INT_TAKEN} & {(take_timer_int | take_int_timer0_int) | take_int_timer1_int})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_EXT_INT_TAKEN} & {take_ext_int})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_FLUSH_LOWER} & {tlu_flush_lower_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BR_ERROR} & {(dec_tlu_br0_error_r | dec_tlu_br0_start_error_r) & rfpc_i0_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_TRANS} & {ifu_pmu_bus_trxn})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_TRANS} & {lsu_pmu_bus_trxn})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_MA_TRANS} & {lsu_pmu_bus_misaligned})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_ERROR} & {ifu_pmu_bus_error})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_ERROR} & {lsu_pmu_bus_error})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_STALL} & {ifu_pmu_bus_busy})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_STALL} & {lsu_pmu_bus_busy})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INT_DISABLED} & {~mstatus[MSTATUS_MIE]})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INT_STALLED} & {~mstatus[MSTATUS_MIE] & |(mip[5:0] & mie[5:0])})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_BITMANIP} & {pmu_i0_itype_qual == eb1_pkg_BITMANIPU})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_LOAD} & {(tlu_i0_commit_cmt & lsu_pmu_load_external_r) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_STORE} & {(tlu_i0_commit_cmt & lsu_pmu_store_external_r) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_SLEEP_CYC} & {dec_tlu_pmu_fw_halted})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_READ_ALL} & {dma_pmu_any_read})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_WRITE_ALL} & {dma_pmu_any_write})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_READ_DCCM} & {dma_pmu_dccm_read})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_WRITE_DCCM} & {dma_pmu_dccm_write}));
+	endgenerate
+	generate
+		if (pt[1227-:5]) begin
+			rvdffie #(.WIDTH(31)) mstatus_ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(free_l2clk),
+				.din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze, mip_ns[5:0], (mcyclel_cout & ~wr_mcycleh_r) & mcyclel_cout_in, minstret_enable, minstretl_cout_ns, fw_halted_ns, meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, mstatus_ns[1:0]}),
+				.dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1, mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]})
+			);
+		end
+		else rvdffie #(.WIDTH(27)) mstatus_ff(
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.clk(free_l2clk),
+			.din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, mip_ns[5:0], (mcyclel_cout & ~wr_mcycleh_r) & mcyclel_cout_in, minstret_enable, minstretl_cout_ns, fw_halted_ns, meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, mstatus_ns[1:0]}),
+			.dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]})
+		);
+	endgenerate
+	assign perfcnt_halted = (dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted;
+	assign perfcnt_during_sleep[3:0] = {4 {~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[39], mhpme_vec[29], mhpme_vec[19], mhpme_vec[9]};
+	assign dec_tlu_perfcnt0 = mhpmc_inc_r_d1[0] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[0]);
+	assign dec_tlu_perfcnt1 = mhpmc_inc_r_d1[1] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[1]);
+	assign dec_tlu_perfcnt2 = mhpmc_inc_r_d1[2] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[2]);
+	assign dec_tlu_perfcnt3 = mhpmc_inc_r_d1[3] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[3]);
+	localparam MHPMC3 = 12'hb03;
+	localparam MHPMC3H = 12'hb83;
+	assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3);
+	assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & |mhpmc_inc_r[0];
+	assign mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1;
+	assign mhpmc3_incr[63:0] = {mhpmc3h[31:0], mhpmc3[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001;
+	assign mhpmc3_ns[31:0] = (mhpmc3_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[31:0]);
+	rvdffe #(.WIDTH(32)) mhpmc3_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc3_wr_en),
+		.din(mhpmc3_ns[31:0]),
+		.dout(mhpmc3[31:0])
+	);
+	assign mhpmc3h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3H);
+	assign mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1;
+	assign mhpmc3h_ns[31:0] = (mhpmc3h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[63:32]);
+	rvdffe #(.WIDTH(32)) mhpmc3h_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc3h_wr_en),
+		.din(mhpmc3h_ns[31:0]),
+		.dout(mhpmc3h[31:0])
+	);
+	localparam MHPMC4 = 12'hb04;
+	localparam MHPMC4H = 12'hb84;
+	assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4);
+	assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & |mhpmc_inc_r[1];
+	assign mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1;
+	assign mhpmc4_incr[63:0] = {mhpmc4h[31:0], mhpmc4[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001;
+	assign mhpmc4_ns[31:0] = (mhpmc4_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[31:0]);
+	rvdffe #(.WIDTH(32)) mhpmc4_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc4_wr_en),
+		.din(mhpmc4_ns[31:0]),
+		.dout(mhpmc4[31:0])
+	);
+	assign mhpmc4h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4H);
+	assign mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1;
+	assign mhpmc4h_ns[31:0] = (mhpmc4h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[63:32]);
+	rvdffe #(.WIDTH(32)) mhpmc4h_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc4h_wr_en),
+		.din(mhpmc4h_ns[31:0]),
+		.dout(mhpmc4h[31:0])
+	);
+	localparam MHPMC5 = 12'hb05;
+	localparam MHPMC5H = 12'hb85;
+	assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5);
+	assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & |mhpmc_inc_r[2];
+	assign mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1;
+	assign mhpmc5_incr[63:0] = {mhpmc5h[31:0], mhpmc5[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001;
+	assign mhpmc5_ns[31:0] = (mhpmc5_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[31:0]);
+	rvdffe #(.WIDTH(32)) mhpmc5_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc5_wr_en),
+		.din(mhpmc5_ns[31:0]),
+		.dout(mhpmc5[31:0])
+	);
+	assign mhpmc5h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5H);
+	assign mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1;
+	assign mhpmc5h_ns[31:0] = (mhpmc5h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[63:32]);
+	rvdffe #(.WIDTH(32)) mhpmc5h_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc5h_wr_en),
+		.din(mhpmc5h_ns[31:0]),
+		.dout(mhpmc5h[31:0])
+	);
+	localparam MHPMC6 = 12'hb06;
+	localparam MHPMC6H = 12'hb86;
+	assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6);
+	assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & |mhpmc_inc_r[3];
+	assign mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1;
+	assign mhpmc6_incr[63:0] = {mhpmc6h[31:0], mhpmc6[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001;
+	assign mhpmc6_ns[31:0] = (mhpmc6_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[31:0]);
+	rvdffe #(.WIDTH(32)) mhpmc6_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc6_wr_en),
+		.din(mhpmc6_ns[31:0]),
+		.dout(mhpmc6[31:0])
+	);
+	assign mhpmc6h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6H);
+	assign mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1;
+	assign mhpmc6h_ns[31:0] = (mhpmc6h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[63:32]);
+	rvdffe #(.WIDTH(32)) mhpmc6h_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en(mhpmc6h_wr_en),
+		.din(mhpmc6h_ns[31:0]),
+		.dout(mhpmc6h[31:0])
+	);
+	localparam MHPME3 = 12'h323;
+	assign zero_event_r = (((((dec_csr_wrdata_r[9:0] > 10'd516) | |dec_csr_wrdata_r[31:10]) | ((dec_csr_wrdata_r[9:0] < 10'd512) & (dec_csr_wrdata_r[9:0] > 10'd56))) | ((dec_csr_wrdata_r[9:0] < 10'd54) & (dec_csr_wrdata_r[9:0] > 10'd50))) | (dec_csr_wrdata_r[9:0] == 10'd29)) | (dec_csr_wrdata_r[9:0] == 10'd33);
+	assign event_r[9:0] = (zero_event_r ? {10 {1'sb0}} : dec_csr_wrdata_r[9:0]);
+	assign wr_mhpme3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME3);
+	rvdffe #(.WIDTH(10)) mhpme3_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mhpme3_r),
+		.din(event_r[9:0]),
+		.dout(mhpme3[9:0])
+	);
+	localparam MHPME4 = 12'h324;
+	assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4);
+	rvdffe #(.WIDTH(10)) mhpme4_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mhpme4_r),
+		.din(event_r[9:0]),
+		.dout(mhpme4[9:0])
+	);
+	localparam MHPME5 = 12'h325;
+	assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5);
+	rvdffe #(.WIDTH(10)) mhpme5_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mhpme5_r),
+		.din(event_r[9:0]),
+		.dout(mhpme5[9:0])
+	);
+	localparam MHPME6 = 12'h326;
+	assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6);
+	rvdffe #(.WIDTH(10)) mhpme6_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mhpme6_r),
+		.din(event_r[9:0]),
+		.dout(mhpme6[9:0])
+	);
+	localparam MCOUNTINHIBIT = 12'h320;
+	assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT);
+	rvdffs #(.WIDTH(6)) mcountinhibit_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.en(wr_mcountinhibit_r),
+		.din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}),
+		.dout({mcountinhibit[6:2], mcountinhibit[0]})
+	);
+	assign mcountinhibit[1] = 1'b0;
+	wire [4:0] dec_tlu_exc_cause_wb1_raw;
+	wire [4:0] dec_tlu_exc_cause_wb2;
+	wire dec_tlu_int_valid_wb1_raw;
+	wire dec_tlu_int_valid_wb2;
+	assign {dec_tlu_i0_valid_wb1, dec_tlu_i0_exc_valid_wb1, dec_tlu_exc_cause_wb1_raw[4:0], dec_tlu_int_valid_wb1_raw} = {8 {~dec_tlu_trace_disable}} & {i0_valid_wb, (i0_exception_valid_r_d1 | lsu_i0_exc_r_d1) | (trigger_hit_r_d1 & ~trigger_hit_dmode_r_d1), exc_cause_wb[4:0], interrupt_valid_r_d1};
+	rvdffie #(
+		.WIDTH(6),
+		.OVERRIDE(1)
+	) traceskidff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din({dec_tlu_exc_cause_wb1_raw[4:0], dec_tlu_int_valid_wb1_raw}),
+		.dout({dec_tlu_exc_cause_wb2[4:0], dec_tlu_int_valid_wb2})
+	);
+	assign dec_tlu_exc_cause_wb1[4:0] = (dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2[4:0] : dec_tlu_exc_cause_wb1_raw[4:0]);
+	assign dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2;
+	assign dec_tlu_mtval_wb1 = mtval[31:0];
+	assign csr_misa = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_mvendorid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_marchid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mimpid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mhartid = (dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[2];
+	assign csr_mstatus = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0];
+	assign csr_mtvec = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_mip = (!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[2];
+	assign csr_mie = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0];
+	assign csr_mcyclel = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1];
+	assign csr_mcycleh = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1];
+	assign csr_minstretl = (((((!dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_minstreth = (((((!dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mscratch = (((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mepc = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mcause = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mscause = (dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2];
+	assign csr_mtval = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mrac = ((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1];
+	assign csr_dmst = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1];
+	assign csr_mdseac = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3];
+	assign csr_meihap = (dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[3];
+	assign csr_meivt = ((((!dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_meipt = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_meicurpl = (dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[2];
+	assign csr_meicidpl = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_dcsr = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[0];
+	assign csr_mcgc = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[0];
+	assign csr_mfdc = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_dpc = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[0];
+	assign csr_mtsel = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mtdata1 = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0];
+	assign csr_mtdata2 = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[1];
+	assign csr_mhpmc3 = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpmc4 = (((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mhpmc5 = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpmc6 = (((((!dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mhpmc3h = ((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpmc4h = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mhpmc5h = ((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpmc6h = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mhpme3 = ((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpme4 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mhpme5 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mhpme6 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mcountinhibit = ((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0];
+	assign csr_mitctl0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mitctl1 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mitb0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_mitb1 = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mitcnt0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0];
+	assign csr_mitcnt1 = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_mpmc = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1];
+	assign csr_meicpct = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_micect = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_miccmect = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0];
+	assign csr_mdccmect = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mfdht = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_mfdhs = ((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0];
+	assign csr_dicawics = ((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_dicad0h = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1];
+	assign csr_dicad0 = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign csr_dicad1 = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0];
+	assign csr_dicago = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0];
+	assign presync = ((((((((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]) | (((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | (((((!dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1])) | ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]);
+	assign postsync = (((((((((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]) | ((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0])) | (((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0])) | ((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | (((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1])) | ((((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]);
+	assign legal = (((((((((((((((((((((((((((((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[0])) | (((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2])) | ((((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | ((((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | (((((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | ((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1])) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]);
+	assign dec_tlu_presync_d = (presync & dec_csr_any_unq_d) & ~dec_csr_wen_unq_d;
+	assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d;
+	assign conditionally_illegal = (((((csr_mitcnt0 | csr_mitcnt1) | csr_mitb0) | csr_mitb1) | csr_mitctl0) | csr_mitctl1) & !pt[4-:5];
+	assign valid_csr = ((legal & (~(((((((csr_dcsr | csr_dpc) | csr_dmst) | csr_dicawics) | csr_dicad0) | csr_dicad0h) | csr_dicad1) | csr_dicago) | dbg_tlu_halted_f)) & ~fast_int_meicpct) & ~conditionally_illegal;
+	assign dec_csr_legal_d = (dec_csr_any_unq_d & valid_csr) & ~(dec_csr_wen_unq_d & (((((csr_mvendorid | csr_marchid) | csr_mimpid) | csr_mhartid) | csr_mdseac) | csr_meihap));
+	assign dec_csr_rddata_d[31:0] = ((((((((((((((((((((((((((((((((((((((((((((((((((((((({32 {csr_misa}} & 32'h40201104) | ({32 {csr_mvendorid}} & 32'h00000045)) | ({32 {csr_marchid}} & 32'h00000010)) | ({32 {csr_mimpid}} & 32'h00000003)) | ({32 {csr_mhartid}} & {core_id[31:4], 4'b0000})) | ({32 {csr_mstatus}} & {{15 {1'b0}}, 2'b01, 2'b00, 2'b11, 3'b000, mstatus[1], 3'b000, mstatus[0], 3'b000})) | ({32 {csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]})) | ({32 {csr_mip}} & {1'b0, mip[5:3], 16'b0000000000000000, mip[2], 3'b000, mip[1], 3'b000, mip[0], 3'b000})) | ({32 {csr_mie}} & {1'b0, mie[5:3], 16'b0000000000000000, mie[2], 3'b000, mie[1], 3'b000, mie[0], 3'b000})) | ({32 {csr_mcyclel}} & mcyclel[31:0])) | ({32 {csr_mcycleh}} & mcycleh_inc[31:0])) | ({32 {csr_minstretl}} & minstretl_read[31:0])) | ({32 {csr_minstreth}} & minstreth_read[31:0])) | ({32 {csr_mscratch}} & mscratch[31:0])) | ({32 {csr_mepc}} & {mepc[31:1], 1'b0})) | ({32 {csr_mcause}} & mcause[31:0])) | ({32 {csr_mscause}} & {28'b0000000000000000000000000000, mscause[3:0]})) | ({32 {csr_mtval}} & mtval[31:0])) | ({32 {csr_mrac}} & mrac[31:0])) | ({32 {csr_mdseac}} & mdseac[31:0])) | ({32 {csr_meivt}} & {meivt[31:10], 10'b0000000000})) | ({32 {csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b00})) | ({32 {csr_meicurpl}} & {28'b0000000000000000000000000000, meicurpl[3:0]})) | ({32 {csr_meicidpl}} & {28'b0000000000000000000000000000, meicidpl[3:0]})) | ({32 {csr_meipt}} & {28'b0000000000000000000000000000, meipt[3:0]})) | ({32 {csr_mcgc}} & {22'b0000000000000000000000, mcgc[9:0]})) | ({32 {csr_mfdc}} & {13'b0000000000000, mfdc[18:0]})) | ({32 {csr_dcsr}} & {16'h4000, dcsr[15:2], 2'b11})) | ({32 {csr_dpc}} & {dpc[31:1], 1'b0})) | ({32 {csr_dicad0}} & dicad0[31:0])) | ({32 {csr_dicad0h}} & dicad0h[31:0])) | ({32 {csr_dicad1}} & dicad1[31:0])) | ({32 {csr_dicawics}} & {7'b0000000, dicawics[16], 2'b00, dicawics[15:14], 3'b000, dicawics[13:0], 3'b000})) | ({32 {csr_mtsel}} & {30'b000000000000000000000000000000, mtsel[1:0]})) | ({32 {csr_mtdata1}} & {mtdata1_tsel_out[31:0]})) | ({32 {csr_mtdata2}} & {mtdata2_tsel_out[31:0]})) | ({32 {csr_micect}} & {micect[31:0]})) | ({32 {csr_miccmect}} & {miccmect[31:0]})) | ({32 {csr_mdccmect}} & {mdccmect[31:0]})) | ({32 {csr_mhpmc3}} & mhpmc3[31:0])) | ({32 {csr_mhpmc4}} & mhpmc4[31:0])) | ({32 {csr_mhpmc5}} & mhpmc5[31:0])) | ({32 {csr_mhpmc6}} & mhpmc6[31:0])) | ({32 {csr_mhpmc3h}} & mhpmc3h[31:0])) | ({32 {csr_mhpmc4h}} & mhpmc4h[31:0])) | ({32 {csr_mhpmc5h}} & mhpmc5h[31:0])) | ({32 {csr_mhpmc6h}} & mhpmc6h[31:0])) | ({32 {csr_mfdht}} & {26'b00000000000000000000000000, mfdht[5:0]})) | ({32 {csr_mfdhs}} & {30'b000000000000000000000000000000, mfdhs[1:0]})) | ({32 {csr_mhpme3}} & {22'b0000000000000000000000, mhpme3[9:0]})) | ({32 {csr_mhpme4}} & {22'b0000000000000000000000, mhpme4[9:0]})) | ({32 {csr_mhpme5}} & {22'b0000000000000000000000, mhpme5[9:0]})) | ({32 {csr_mhpme6}} & {22'b0000000000000000000000, mhpme6[9:0]})) | ({32 {csr_mcountinhibit}} & {25'b0000000000000000000000000, mcountinhibit[6:0]})) | ({32 {csr_mpmc}} & {30'b000000000000000000000000000000, mpmc[1], 1'b0})) | ({32 {dec_timer_read_d}} & dec_timer_rddata_d[31:0]);
+endmodule
+module eb1_dec_timer_ctl (
+	clk,
+	free_l2clk,
+	csr_wr_clk,
+	rst_l,
+	dec_csr_wen_r_mod,
+	dec_csr_wraddr_r,
+	dec_csr_wrdata_r,
+	csr_mitctl0,
+	csr_mitctl1,
+	csr_mitb0,
+	csr_mitb1,
+	csr_mitcnt0,
+	csr_mitcnt1,
+	dec_pause_state,
+	dec_tlu_pmu_fw_halted,
+	internal_dbg_halt_timers,
+	dec_timer_rddata_d,
+	dec_timer_read_d,
+	dec_timer_t0_pulse,
+	dec_timer_t1_pulse,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire free_l2clk;
+	input wire csr_wr_clk;
+	input wire rst_l;
+	input wire dec_csr_wen_r_mod;
+	input wire [11:0] dec_csr_wraddr_r;
+	input wire [31:0] dec_csr_wrdata_r;
+	input wire csr_mitctl0;
+	input wire csr_mitctl1;
+	input wire csr_mitb0;
+	input wire csr_mitb1;
+	input wire csr_mitcnt0;
+	input wire csr_mitcnt1;
+	input wire dec_pause_state;
+	input wire dec_tlu_pmu_fw_halted;
+	input wire internal_dbg_halt_timers;
+	output wire [31:0] dec_timer_rddata_d;
+	output wire dec_timer_read_d;
+	output wire dec_timer_t0_pulse;
+	output wire dec_timer_t1_pulse;
+	input wire scan_mode;
+	localparam MITCTL_ENABLE = 0;
+	localparam MITCTL_ENABLE_HALTED = 1;
+	localparam MITCTL_ENABLE_PAUSED = 2;
+	wire [31:0] mitcnt0_ns;
+	wire [31:0] mitcnt0;
+	wire [31:0] mitcnt1_ns;
+	wire [31:0] mitcnt1;
+	wire [31:0] mitb0;
+	wire [31:0] mitb1;
+	wire [31:0] mitb0_b;
+	wire [31:0] mitb1_b;
+	wire [31:0] mitcnt0_inc;
+	wire [31:0] mitcnt1_inc;
+	wire [2:0] mitctl0_ns;
+	wire [2:0] mitctl0;
+	wire [3:0] mitctl1_ns;
+	wire [3:0] mitctl1;
+	wire wr_mitcnt0_r;
+	wire wr_mitcnt1_r;
+	wire wr_mitb0_r;
+	wire wr_mitb1_r;
+	wire wr_mitctl0_r;
+	wire wr_mitctl1_r;
+	wire mitcnt0_inc_ok;
+	wire mitcnt1_inc_ok;
+	wire mitcnt0_inc_cout;
+	wire mitcnt1_inc_cout;
+	wire mit0_match_ns;
+	wire mit1_match_ns;
+	wire mitctl0_0_b_ns;
+	wire mitctl0_0_b;
+	wire mitctl1_0_b_ns;
+	wire mitctl1_0_b;
+	assign mit0_match_ns = mitcnt0[31:0] >= mitb0[31:0];
+	assign mit1_match_ns = mitcnt1[31:0] >= mitb1[31:0];
+	assign dec_timer_t0_pulse = mit0_match_ns;
+	assign dec_timer_t1_pulse = mit1_match_ns;
+	localparam MITCNT0 = 12'h7d2;
+	assign wr_mitcnt0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT0);
+	assign mitcnt0_inc_ok = ((mitctl0[MITCTL_ENABLE] & (~dec_pause_state | mitctl0[MITCTL_ENABLE_PAUSED])) & (~dec_tlu_pmu_fw_halted | mitctl0[MITCTL_ENABLE_HALTED])) & ~internal_dbg_halt_timers;
+	assign {mitcnt0_inc_cout, mitcnt0_inc[7:0]} = mitcnt0[7:0] + 8'b00000001;
+	assign mitcnt0_inc[31:8] = mitcnt0[31:8] + {23'b00000000000000000000000, mitcnt0_inc_cout};
+	assign mitcnt0_ns[31:0] = (wr_mitcnt0_r ? dec_csr_wrdata_r[31:0] : (mit0_match_ns ? 'b0 : mitcnt0_inc[31:0]));
+	rvdffe #(.WIDTH(24)) mitcnt0_ffb(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en((wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout)) | mit0_match_ns),
+		.din(mitcnt0_ns[31:8]),
+		.dout(mitcnt0[31:8])
+	);
+	rvdffe #(.WIDTH(8)) mitcnt0_ffa(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en((wr_mitcnt0_r | mitcnt0_inc_ok) | mit0_match_ns),
+		.din(mitcnt0_ns[7:0]),
+		.dout(mitcnt0[7:0])
+	);
+	localparam MITCNT1 = 12'h7d5;
+	assign wr_mitcnt1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT1);
+	assign mitcnt1_inc_ok = (((mitctl1[MITCTL_ENABLE] & (~dec_pause_state | mitctl1[MITCTL_ENABLE_PAUSED])) & (~dec_tlu_pmu_fw_halted | mitctl1[MITCTL_ENABLE_HALTED])) & ~internal_dbg_halt_timers) & (~mitctl1[3] | mit0_match_ns);
+	assign {mitcnt1_inc_cout, mitcnt1_inc[7:0]} = mitcnt1[7:0] + 8'b00000001;
+	assign mitcnt1_inc[31:8] = mitcnt1[31:8] + {23'b00000000000000000000000, mitcnt1_inc_cout};
+	assign mitcnt1_ns[31:0] = (wr_mitcnt1_r ? dec_csr_wrdata_r[31:0] : (mit1_match_ns ? 'b0 : mitcnt1_inc[31:0]));
+	rvdffe #(.WIDTH(24)) mitcnt1_ffb(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en((wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout)) | mit1_match_ns),
+		.din(mitcnt1_ns[31:8]),
+		.dout(mitcnt1[31:8])
+	);
+	rvdffe #(.WIDTH(8)) mitcnt1_ffa(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.en((wr_mitcnt1_r | mitcnt1_inc_ok) | mit1_match_ns),
+		.din(mitcnt1_ns[7:0]),
+		.dout(mitcnt1[7:0])
+	);
+	localparam MITB0 = 12'h7d3;
+	assign wr_mitb0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB0);
+	rvdffe #(.WIDTH(32)) mitb0_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mitb0_r),
+		.din(~dec_csr_wrdata_r[31:0]),
+		.dout(mitb0_b[31:0])
+	);
+	assign mitb0[31:0] = ~mitb0_b[31:0];
+	localparam MITB1 = 12'h7d6;
+	assign wr_mitb1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB1);
+	rvdffe #(.WIDTH(32)) mitb1_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(wr_mitb1_r),
+		.din(~dec_csr_wrdata_r[31:0]),
+		.dout(mitb1_b[31:0])
+	);
+	assign mitb1[31:0] = ~mitb1_b[31:0];
+	localparam MITCTL0 = 12'h7d4;
+	assign wr_mitctl0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL0);
+	assign mitctl0_ns[2:0] = (wr_mitctl0_r ? {dec_csr_wrdata_r[2:0]} : {mitctl0[2:0]});
+	assign mitctl0_0_b_ns = ~mitctl0_ns[0];
+	rvdffs #(.WIDTH(3)) mitctl0_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.en(wr_mitctl0_r),
+		.din({mitctl0_ns[2:1], mitctl0_0_b_ns}),
+		.dout({mitctl0[2:1], mitctl0_0_b})
+	);
+	assign mitctl0[0] = ~mitctl0_0_b;
+	localparam MITCTL1 = 12'h7d7;
+	assign wr_mitctl1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL1);
+	assign mitctl1_ns[3:0] = (wr_mitctl1_r ? {dec_csr_wrdata_r[3:0]} : {mitctl1[3:0]});
+	assign mitctl1_0_b_ns = ~mitctl1_ns[0];
+	rvdffs #(.WIDTH(4)) mitctl1_ff(
+		.rst_l(rst_l),
+		.clk(csr_wr_clk),
+		.en(wr_mitctl1_r),
+		.din({mitctl1_ns[3:1], mitctl1_0_b_ns}),
+		.dout({mitctl1[3:1], mitctl1_0_b})
+	);
+	assign mitctl1[0] = ~mitctl1_0_b;
+	assign dec_timer_read_d = ((((csr_mitcnt1 | csr_mitcnt0) | csr_mitb1) | csr_mitb0) | csr_mitctl0) | csr_mitctl1;
+	assign dec_timer_rddata_d[31:0] = ((((({32 {csr_mitcnt0}} & mitcnt0[31:0]) | ({32 {csr_mitcnt1}} & mitcnt1[31:0])) | ({32 {csr_mitb0}} & mitb0[31:0])) | ({32 {csr_mitb1}} & mitb1[31:0])) | ({32 {csr_mitctl0}} & {29'b00000000000000000000000000000, mitctl0[2:0]})) | ({32 {csr_mitctl1}} & {28'b0000000000000000000000000000, mitctl1[3:0]});
+endmodule
+module eb1_dec_trigger (
+	trigger_pkt_any,
+	dec_i0_pc_d,
+	dec_i0_trigger_match_d
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [151:0] trigger_pkt_any;
+	input wire [31:1] dec_i0_pc_d;
+	output wire [3:0] dec_i0_trigger_match_d;
+	wire [127:0] dec_i0_match_data;
+	wire [3:0] dec_i0_trigger_data_match;
+	generate
+		genvar i;
+		for (i = 0; i < 4; i = i + 1) begin
+			assign dec_i0_match_data[(i * 32) + 31-:32] = {32 {~trigger_pkt_any[(i * 38) + 37] & trigger_pkt_any[(i * 38) + 33]}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i * 38]};
+			rvmaskandmatch trigger_i0_match(
+				.mask(trigger_pkt_any[(i * 38) + 31-:32]),
+				.data(dec_i0_match_data[(i * 32) + 31-:32]),
+				.masken(trigger_pkt_any[(i * 38) + 36]),
+				.match(dec_i0_trigger_data_match[i])
+			);
+			assign dec_i0_trigger_match_d[i] = (trigger_pkt_any[(i * 38) + 33] & trigger_pkt_any[(i * 38) + 32]) & dec_i0_trigger_data_match[i];
+		end
+	endgenerate
+endmodule
+module eb1_exu (
+	clk,
+	rst_l,
+	scan_mode,
+	dec_data_en,
+	dec_ctl_en,
+	dbg_cmd_wrdata,
+	i0_ap,
+	dec_debug_wdata_rs1_d,
+	dec_i0_predict_p_d,
+	i0_predict_fghr_d,
+	i0_predict_index_d,
+	i0_predict_btag_d,
+	lsu_result_m,
+	lsu_nonblock_load_data,
+	dec_i0_rs1_en_d,
+	dec_i0_rs2_en_d,
+	gpr_i0_rs1_d,
+	gpr_i0_rs2_d,
+	dec_i0_immed_d,
+	dec_i0_result_r,
+	dec_i0_br_immed_d,
+	dec_i0_alu_decode_d,
+	dec_i0_branch_d,
+	dec_i0_select_pc_d,
+	dec_i0_pc_d,
+	dec_i0_rs1_bypass_en_d,
+	dec_i0_rs2_bypass_en_d,
+	dec_csr_ren_d,
+	dec_csr_rddata_d,
+	dec_qual_lsu_d,
+	mul_p,
+	div_p,
+	dec_div_cancel,
+	pred_correct_npc_x,
+	dec_tlu_flush_lower_r,
+	dec_tlu_flush_path_r,
+	dec_extint_stall,
+	dec_tlu_meihap,
+	exu_lsu_rs1_d,
+	exu_lsu_rs2_d,
+	exu_flush_final,
+	exu_flush_path_final,
+	exu_i0_result_x,
+	exu_i0_pc_x,
+	exu_csr_rs1_x,
+	exu_npc_r,
+	exu_i0_br_hist_r,
+	exu_i0_br_error_r,
+	exu_i0_br_start_error_r,
+	exu_i0_br_index_r,
+	exu_i0_br_valid_r,
+	exu_i0_br_mp_r,
+	exu_i0_br_middle_r,
+	exu_i0_br_fghr_r,
+	exu_i0_br_way_r,
+	exu_mp_pkt,
+	exu_mp_eghr,
+	exu_mp_fghr,
+	exu_mp_index,
+	exu_mp_btag,
+	exu_pmu_i0_br_misp,
+	exu_pmu_i0_br_ataken,
+	exu_pmu_i0_pc4,
+	exu_div_result,
+	exu_div_wren
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire [1:0] dec_data_en;
+	input wire [1:0] dec_ctl_en;
+	input wire [31:0] dbg_cmd_wrdata;
+	input wire [43:0] i0_ap;
+	input wire dec_debug_wdata_rs1_d;
+	input wire [55:0] dec_i0_predict_p_d;
+	input wire [pt[2236-:8] - 1:0] i0_predict_fghr_d;
+	input wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d;
+	input wire [pt[2139-:9] - 1:0] i0_predict_btag_d;
+	input wire [31:0] lsu_result_m;
+	input wire [31:0] lsu_nonblock_load_data;
+	input wire dec_i0_rs1_en_d;
+	input wire dec_i0_rs2_en_d;
+	input wire [31:0] gpr_i0_rs1_d;
+	input wire [31:0] gpr_i0_rs2_d;
+	input wire [31:0] dec_i0_immed_d;
+	input wire [31:0] dec_i0_result_r;
+	input wire [12:1] dec_i0_br_immed_d;
+	input wire dec_i0_alu_decode_d;
+	input wire dec_i0_branch_d;
+	input wire dec_i0_select_pc_d;
+	input wire [31:1] dec_i0_pc_d;
+	input wire [3:0] dec_i0_rs1_bypass_en_d;
+	input wire [3:0] dec_i0_rs2_bypass_en_d;
+	input wire dec_csr_ren_d;
+	input wire [31:0] dec_csr_rddata_d;
+	input wire dec_qual_lsu_d;
+	input wire [19:0] mul_p;
+	input wire [2:0] div_p;
+	input wire dec_div_cancel;
+	input wire [31:1] pred_correct_npc_x;
+	input wire dec_tlu_flush_lower_r;
+	input wire [31:1] dec_tlu_flush_path_r;
+	input wire dec_extint_stall;
+	input wire [31:2] dec_tlu_meihap;
+	output wire [31:0] exu_lsu_rs1_d;
+	output wire [31:0] exu_lsu_rs2_d;
+	output wire exu_flush_final;
+	output wire [31:1] exu_flush_path_final;
+	output wire [31:0] exu_i0_result_x;
+	output wire [31:1] exu_i0_pc_x;
+	output wire [31:0] exu_csr_rs1_x;
+	output wire [31:1] exu_npc_r;
+	output wire [1:0] exu_i0_br_hist_r;
+	output wire exu_i0_br_error_r;
+	output wire exu_i0_br_start_error_r;
+	output wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r;
+	output wire exu_i0_br_valid_r;
+	output wire exu_i0_br_mp_r;
+	output wire exu_i0_br_middle_r;
+	output wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r;
+	output wire exu_i0_br_way_r;
+	output wire [55:0] exu_mp_pkt;
+	output wire [pt[2236-:8] - 1:0] exu_mp_eghr;
+	output wire [pt[2236-:8] - 1:0] exu_mp_fghr;
+	output wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index;
+	output wire [pt[2139-:9] - 1:0] exu_mp_btag;
+	output wire exu_pmu_i0_br_misp;
+	output wire exu_pmu_i0_br_ataken;
+	output wire exu_pmu_i0_pc4;
+	output wire [31:0] exu_div_result;
+	output wire exu_div_wren;
+	wire [31:0] i0_rs1_bypass_data_d;
+	wire [31:0] i0_rs2_bypass_data_d;
+	wire i0_rs1_bypass_en_d;
+	wire i0_rs2_bypass_en_d;
+	wire [31:0] i0_rs1_d;
+	wire [31:0] i0_rs2_d;
+	wire [31:0] muldiv_rs1_d;
+	wire [31:1] pred_correct_npc_r;
+	wire i0_pred_correct_upper_r;
+	wire [31:1] i0_flush_path_upper_r;
+	wire x_data_en;
+	wire x_data_en_q1;
+	wire x_data_en_q2;
+	wire r_data_en;
+	wire r_data_en_q2;
+	wire x_ctl_en;
+	wire r_ctl_en;
+	wire [pt[2236-:8] - 1:0] ghr_d_ns;
+	wire [pt[2236-:8] - 1:0] ghr_d;
+	wire [pt[2236-:8] - 1:0] ghr_x_ns;
+	wire [pt[2236-:8] - 1:0] ghr_x;
+	wire i0_taken_d;
+	wire i0_taken_x;
+	wire i0_valid_d;
+	wire i0_valid_x;
+	wire [pt[2236-:8] - 1:0] after_flush_eghr;
+	wire [55:0] final_predict_mp;
+	reg [55:0] i0_predict_newp_d;
+	wire flush_in_d;
+	wire [31:0] alu_result_x;
+	wire mul_valid_x;
+	wire [31:0] mul_result_x;
+	wire [55:0] i0_pp_r;
+	wire i0_flush_upper_d;
+	wire [31:1] i0_flush_path_d;
+	wire [55:0] i0_predict_p_d;
+	wire i0_pred_correct_upper_d;
+	wire i0_flush_upper_x;
+	wire [31:1] i0_flush_path_x;
+	wire [55:0] i0_predict_p_x;
+	wire i0_pred_correct_upper_x;
+	wire i0_branch_x;
+	localparam PREDPIPESIZE = (((pt[2172-:9] - pt[2163-:6]) + 1) + pt[2236-:8]) + pt[2139-:9];
+	wire [PREDPIPESIZE - 1:0] predpipe_d;
+	wire [PREDPIPESIZE - 1:0] predpipe_x;
+	wire [PREDPIPESIZE - 1:0] predpipe_r;
+	wire [PREDPIPESIZE - 1:0] final_predpipe_mp;
+	rvdffpcie #(.WIDTH(31)) i_flush_path_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(x_data_en),
+		.din(i0_flush_path_d[31:1]),
+		.dout(i0_flush_path_x[31:1])
+	);
+	rvdffe #(.WIDTH(32)) i_csr_rs1_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(x_data_en_q1),
+		.din(i0_rs1_d[31:0]),
+		.dout(exu_csr_rs1_x[31:0])
+	);
+	rvdffppe #(.WIDTH(56)) i_predictpacket_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(x_data_en),
+		.din(i0_predict_p_d),
+		.dout(i0_predict_p_x)
+	);
+	rvdffe #(.WIDTH(PREDPIPESIZE)) i_predpipe_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(x_data_en_q2),
+		.din(predpipe_d),
+		.dout(predpipe_x)
+	);
+	rvdffe #(.WIDTH(PREDPIPESIZE)) i_predpipe_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(r_data_en_q2),
+		.din(predpipe_x),
+		.dout(predpipe_r)
+	);
+	rvdffe #(.WIDTH(4 + pt[2236-:8])) i_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(x_ctl_en),
+		.din({i0_valid_d, i0_taken_d, i0_flush_upper_d, i0_pred_correct_upper_d, ghr_x_ns[pt[2236-:8] - 1:0]}),
+		.dout({i0_valid_x, i0_taken_x, i0_flush_upper_x, i0_pred_correct_upper_x, ghr_x[pt[2236-:8] - 1:0]})
+	);
+	rvdffppe #(.WIDTH(57)) i_r_ff0(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(r_ctl_en),
+		.din({i0_pred_correct_upper_x, i0_predict_p_x}),
+		.dout({i0_pred_correct_upper_r, i0_pp_r})
+	);
+	rvdffpcie #(.WIDTH(31)) i_flush_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(r_data_en),
+		.din(i0_flush_path_x[31:1]),
+		.dout(i0_flush_path_upper_r[31:1])
+	);
+	rvdffpcie #(.WIDTH(31)) i_npc_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(r_data_en),
+		.din(pred_correct_npc_x[31:1]),
+		.dout(pred_correct_npc_r[31:1])
+	);
+	rvdffie #(
+		.WIDTH(pt[2236-:8] + 2),
+		.OVERRIDE(1)
+	) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din({ghr_d_ns[pt[2236-:8] - 1:0], mul_p[19], dec_i0_branch_d}),
+		.dout({ghr_d[pt[2236-:8] - 1:0], mul_valid_x, i0_branch_x})
+	);
+	assign predpipe_d[PREDPIPESIZE - 1:0] = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};
+	assign i0_rs1_bypass_en_d = ((dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1]) | dec_i0_rs1_bypass_en_d[2]) | dec_i0_rs1_bypass_en_d[3];
+	assign i0_rs2_bypass_en_d = ((dec_i0_rs2_bypass_en_d[0] | dec_i0_rs2_bypass_en_d[1]) | dec_i0_rs2_bypass_en_d[2]) | dec_i0_rs2_bypass_en_d[3];
+	assign i0_rs1_bypass_data_d[31:0] = ((({32 {dec_i0_rs1_bypass_en_d[0]}} & dec_i0_result_r[31:0]) | ({32 {dec_i0_rs1_bypass_en_d[1]}} & lsu_result_m[31:0])) | ({32 {dec_i0_rs1_bypass_en_d[2]}} & exu_i0_result_x[31:0])) | ({32 {dec_i0_rs1_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
+	assign i0_rs2_bypass_data_d[31:0] = ((({32 {dec_i0_rs2_bypass_en_d[0]}} & dec_i0_result_r[31:0]) | ({32 {dec_i0_rs2_bypass_en_d[1]}} & lsu_result_m[31:0])) | ({32 {dec_i0_rs2_bypass_en_d[2]}} & exu_i0_result_x[31:0])) | ({32 {dec_i0_rs2_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
+	assign i0_rs1_d[31:0] = ((({32 {i0_rs1_bypass_en_d}} & i0_rs1_bypass_data_d[31:0]) | ({32 {~i0_rs1_bypass_en_d & dec_i0_select_pc_d}} & {dec_i0_pc_d[31:1], 1'b0})) | ({32 {~i0_rs1_bypass_en_d & dec_debug_wdata_rs1_d}} & dbg_cmd_wrdata[31:0])) | ({32 {(~i0_rs1_bypass_en_d & ~dec_debug_wdata_rs1_d) & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0]);
+	assign i0_rs2_d[31:0] = (({32 {~i0_rs2_bypass_en_d & dec_i0_rs2_en_d}} & gpr_i0_rs2_d[31:0]) | ({32 {~i0_rs2_bypass_en_d}} & dec_i0_immed_d[31:0])) | ({32 {i0_rs2_bypass_en_d}} & i0_rs2_bypass_data_d[31:0]);
+	assign exu_lsu_rs1_d[31:0] = (({32 {((~i0_rs1_bypass_en_d & ~dec_extint_stall) & dec_i0_rs1_en_d) & dec_qual_lsu_d}} & gpr_i0_rs1_d[31:0]) | ({32 {(i0_rs1_bypass_en_d & ~dec_extint_stall) & dec_qual_lsu_d}} & i0_rs1_bypass_data_d[31:0])) | ({32 {dec_extint_stall & dec_qual_lsu_d}} & {dec_tlu_meihap[31:2], 2'b00});
+	assign exu_lsu_rs2_d[31:0] = ({32 {((~i0_rs2_bypass_en_d & ~dec_extint_stall) & dec_i0_rs2_en_d) & dec_qual_lsu_d}} & gpr_i0_rs2_d[31:0]) | ({32 {(i0_rs2_bypass_en_d & ~dec_extint_stall) & dec_qual_lsu_d}} & i0_rs2_bypass_data_d[31:0]);
+	assign muldiv_rs1_d[31:0] = ({32 {~i0_rs1_bypass_en_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0]) | ({32 {i0_rs1_bypass_en_d}} & i0_rs1_bypass_data_d[31:0]);
+	assign x_data_en = dec_data_en[1];
+	assign x_data_en_q1 = dec_data_en[1] & dec_csr_ren_d;
+	assign x_data_en_q2 = dec_data_en[1] & dec_i0_branch_d;
+	assign r_data_en = dec_data_en[0];
+	assign r_data_en_q2 = dec_data_en[0] & i0_branch_x;
+	assign x_ctl_en = dec_ctl_en[1];
+	assign r_ctl_en = dec_ctl_en[0];
+	eb1_exu_alu_ctl #(.pt(pt)) i_alu(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.enable(x_data_en),
+		.pp_in(i0_predict_newp_d),
+		.valid_in(dec_i0_alu_decode_d),
+		.flush_upper_x(i0_flush_upper_x),
+		.flush_lower_r(dec_tlu_flush_lower_r),
+		.a_in(i0_rs1_d[31:0]),
+		.b_in(i0_rs2_d[31:0]),
+		.pc_in(dec_i0_pc_d[31:1]),
+		.brimm_in(dec_i0_br_immed_d[12:1]),
+		.ap(i0_ap),
+		.csr_ren_in(dec_csr_ren_d),
+		.csr_rddata_in(dec_csr_rddata_d[31:0]),
+		.result_ff(alu_result_x[31:0]),
+		.flush_upper_out(i0_flush_upper_d),
+		.flush_final_out(exu_flush_final),
+		.flush_path_out(i0_flush_path_d[31:1]),
+		.predict_p_out(i0_predict_p_d),
+		.pred_correct_out(i0_pred_correct_upper_d),
+		.pc_ff(exu_i0_pc_x[31:1])
+	);
+	eb1_exu_mul_ctl #(.pt(pt)) i_mul(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.mul_p(mul_p & {20 {mul_p[19]}}),
+		.rs1_in(muldiv_rs1_d[31:0] & {32 {mul_p[19]}}),
+		.rs2_in(i0_rs2_d[31:0] & {32 {mul_p[19]}}),
+		.result_x(mul_result_x[31:0])
+	);
+	eb1_exu_div_ctl #(.pt(pt)) i_div(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.cancel(dec_div_cancel),
+		.dp(div_p),
+		.dividend(muldiv_rs1_d[31:0]),
+		.divisor(i0_rs2_d[31:0]),
+		.finish_dly(exu_div_wren),
+		.out(exu_div_result[31:0])
+	);
+	assign exu_i0_result_x[31:0] = (mul_valid_x ? mul_result_x[31:0] : alu_result_x[31:0]);
+	always @(*) begin
+		i0_predict_newp_d = dec_i0_predict_p_d;
+		i0_predict_newp_d[53] = dec_i0_pc_d[1];
+	end
+	assign exu_pmu_i0_br_misp = i0_pp_r[55];
+	assign exu_pmu_i0_br_ataken = i0_pp_r[54];
+	assign exu_pmu_i0_pc4 = i0_pp_r[52];
+	assign i0_valid_d = (i0_predict_p_d[37] & dec_i0_alu_decode_d) & ~dec_tlu_flush_lower_r;
+	assign i0_taken_d = i0_predict_p_d[54] & dec_i0_alu_decode_d;
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign ghr_d_ns[pt[2236-:8] - 1:0] = (({pt[2236-:8] {~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt[2236-:8] - 2:0], i0_taken_d}) | ({pt[2236-:8] {~dec_tlu_flush_lower_r & ~i0_valid_d}} & ghr_d[pt[2236-:8] - 1:0])) | ({pt[2236-:8] {dec_tlu_flush_lower_r}} & ghr_x[pt[2236-:8] - 1:0]);
+			assign ghr_x_ns[pt[2236-:8] - 1:0] = ({pt[2236-:8] {i0_valid_x}} & {ghr_x[pt[2236-:8] - 2:0], i0_taken_x}) | ({pt[2236-:8] {~i0_valid_x}} & ghr_x[pt[2236-:8] - 1:0]);
+			assign exu_i0_br_valid_r = i0_pp_r[37];
+			assign exu_i0_br_mp_r = i0_pp_r[55];
+			assign exu_i0_br_way_r = i0_pp_r[32];
+			assign exu_i0_br_hist_r[1:0] = {2 {i0_pp_r[37]}} & i0_pp_r[51:50];
+			assign exu_i0_br_error_r = i0_pp_r[36];
+			assign exu_i0_br_middle_r = i0_pp_r[52] ^ i0_pp_r[53];
+			assign exu_i0_br_start_error_r = i0_pp_r[35];
+			assign {exu_i0_br_fghr_r[pt[2236-:8] - 1:0], exu_i0_br_index_r[pt[2172-:9]:pt[2163-:6]]} = predpipe_r[PREDPIPESIZE - 1:pt[2139-:9]];
+			assign final_predict_mp = (i0_flush_upper_x ? i0_predict_p_x : {56 {1'sb0}});
+			assign final_predpipe_mp[PREDPIPESIZE - 1:0] = (i0_flush_upper_x ? predpipe_x : {PREDPIPESIZE {1'sb0}});
+			assign after_flush_eghr[pt[2236-:8] - 1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r ? ghr_d[pt[2236-:8] - 1:0] : ghr_x[pt[2236-:8] - 1:0]);
+			assign exu_mp_pkt[37] = final_predict_mp[37];
+			assign exu_mp_pkt[32] = final_predict_mp[32];
+			assign exu_mp_pkt[55] = final_predict_mp[55];
+			assign exu_mp_pkt[34] = final_predict_mp[34];
+			assign exu_mp_pkt[33] = final_predict_mp[33];
+			assign exu_mp_pkt[31] = final_predict_mp[31];
+			assign exu_mp_pkt[54] = final_predict_mp[54];
+			assign exu_mp_pkt[53] = final_predict_mp[53];
+			assign exu_mp_pkt[52] = final_predict_mp[52];
+			assign exu_mp_pkt[51:50] = final_predict_mp[51:50];
+			assign exu_mp_pkt[49:38] = final_predict_mp[49:38];
+			assign exu_mp_fghr[pt[2236-:8] - 1:0] = after_flush_eghr[pt[2236-:8] - 1:0];
+			assign {exu_mp_index[pt[2172-:9]:pt[2163-:6]], exu_mp_btag[pt[2139-:9] - 1:0]} = final_predpipe_mp[(PREDPIPESIZE - pt[2236-:8]) - 1:0];
+			assign exu_mp_eghr[pt[2236-:8] - 1:0] = final_predpipe_mp[PREDPIPESIZE - 1:((pt[2172-:9] - pt[2163-:6]) + pt[2139-:9]) + 1];
+		end
+		else begin
+			assign ghr_d_ns = {pt[2236-:8] {1'sb0}};
+			assign ghr_x_ns = {pt[2236-:8] {1'sb0}};
+			assign exu_mp_pkt = {56 {1'sb0}};
+			assign exu_mp_eghr = {pt[2236-:8] {1'sb0}};
+			assign exu_mp_fghr = {pt[2236-:8] {1'sb0}};
+			assign exu_mp_index = {(pt[2172-:9] >= pt[2163-:6] ? (pt[2172-:9] - pt[2163-:6]) + 1 : (pt[2163-:6] - pt[2172-:9]) + 1) {1'sb0}};
+			assign exu_mp_btag = {pt[2139-:9] {1'sb0}};
+			assign exu_i0_br_hist_r = {2 {1'sb0}};
+			assign exu_i0_br_error_r = 1'b0;
+			assign exu_i0_br_start_error_r = 1'b0;
+			assign exu_i0_br_index_r = {(pt[2172-:9] >= pt[2163-:6] ? (pt[2172-:9] - pt[2163-:6]) + 1 : (pt[2163-:6] - pt[2172-:9]) + 1) {1'sb0}};
+			assign exu_i0_br_valid_r = 1'b0;
+			assign exu_i0_br_mp_r = 1'b0;
+			assign exu_i0_br_middle_r = 1'b0;
+			assign exu_i0_br_fghr_r = {pt[2236-:8] {1'sb0}};
+			assign exu_i0_br_way_r = 1'b0;
+		end
+	endgenerate
+	assign exu_flush_path_final[31:1] = ({31 {dec_tlu_flush_lower_r}} & dec_tlu_flush_path_r[31:1]) | ({31 {~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1]);
+	assign exu_npc_r[31:1] = (i0_pred_correct_upper_r ? pred_correct_npc_r[31:1] : i0_flush_path_upper_r[31:1]);
+endmodule
+module eb1_dma_ctrl (
+	clk,
+	free_clk,
+	rst_l,
+	dma_bus_clk_en,
+	clk_override,
+	scan_mode,
+	dbg_cmd_addr,
+	dbg_cmd_wrdata,
+	dbg_cmd_valid,
+	dbg_cmd_write,
+	dbg_cmd_type,
+	dbg_cmd_size,
+	dbg_dma_bubble,
+	dma_dbg_ready,
+	dma_dbg_cmd_done,
+	dma_dbg_cmd_fail,
+	dma_dbg_rddata,
+	dma_dccm_req,
+	dma_iccm_req,
+	dma_mem_tag,
+	dma_mem_addr,
+	dma_mem_sz,
+	dma_mem_write,
+	dma_mem_wdata,
+	dccm_dma_rvalid,
+	dccm_dma_ecc_error,
+	dccm_dma_rtag,
+	dccm_dma_rdata,
+	iccm_dma_rvalid,
+	iccm_dma_ecc_error,
+	iccm_dma_rtag,
+	iccm_dma_rdata,
+	dma_active,
+	dma_dccm_stall_any,
+	dma_iccm_stall_any,
+	dccm_ready,
+	iccm_ready,
+	dec_tlu_dma_qos_prty,
+	dma_pmu_dccm_read,
+	dma_pmu_dccm_write,
+	dma_pmu_any_read,
+	dma_pmu_any_write,
+	dma_axi_awvalid,
+	dma_axi_awready,
+	dma_axi_awid,
+	dma_axi_awaddr,
+	dma_axi_awsize,
+	dma_axi_wvalid,
+	dma_axi_wready,
+	dma_axi_wdata,
+	dma_axi_wstrb,
+	dma_axi_bvalid,
+	dma_axi_bready,
+	dma_axi_bresp,
+	dma_axi_bid,
+	dma_axi_arvalid,
+	dma_axi_arready,
+	dma_axi_arid,
+	dma_axi_araddr,
+	dma_axi_arsize,
+	dma_axi_rvalid,
+	dma_axi_rready,
+	dma_axi_rid,
+	dma_axi_rdata,
+	dma_axi_rresp,
+	dma_axi_rlast
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire free_clk;
+	input wire rst_l;
+	input wire dma_bus_clk_en;
+	input wire clk_override;
+	input wire scan_mode;
+	input wire [31:0] dbg_cmd_addr;
+	input wire [31:0] dbg_cmd_wrdata;
+	input wire dbg_cmd_valid;
+	input wire dbg_cmd_write;
+	input wire [1:0] dbg_cmd_type;
+	input wire [1:0] dbg_cmd_size;
+	input wire dbg_dma_bubble;
+	output wire dma_dbg_ready;
+	output wire dma_dbg_cmd_done;
+	output wire dma_dbg_cmd_fail;
+	output wire [31:0] dma_dbg_rddata;
+	output wire dma_dccm_req;
+	output wire dma_iccm_req;
+	output wire [2:0] dma_mem_tag;
+	output wire [31:0] dma_mem_addr;
+	output wire [2:0] dma_mem_sz;
+	output wire dma_mem_write;
+	output wire [63:0] dma_mem_wdata;
+	input wire dccm_dma_rvalid;
+	input wire dccm_dma_ecc_error;
+	input wire [2:0] dccm_dma_rtag;
+	input wire [63:0] dccm_dma_rdata;
+	input wire iccm_dma_rvalid;
+	input wire iccm_dma_ecc_error;
+	input wire [2:0] iccm_dma_rtag;
+	input wire [63:0] iccm_dma_rdata;
+	output wire dma_active;
+	output wire dma_dccm_stall_any;
+	output wire dma_iccm_stall_any;
+	input wire dccm_ready;
+	input wire iccm_ready;
+	input wire [2:0] dec_tlu_dma_qos_prty;
+	output wire dma_pmu_dccm_read;
+	output wire dma_pmu_dccm_write;
+	output wire dma_pmu_any_read;
+	output wire dma_pmu_any_write;
+	input wire dma_axi_awvalid;
+	output wire dma_axi_awready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_awid;
+	input wire [31:0] dma_axi_awaddr;
+	input wire [2:0] dma_axi_awsize;
+	input wire dma_axi_wvalid;
+	output wire dma_axi_wready;
+	input wire [63:0] dma_axi_wdata;
+	input wire [7:0] dma_axi_wstrb;
+	output wire dma_axi_bvalid;
+	input wire dma_axi_bready;
+	output wire [1:0] dma_axi_bresp;
+	output wire [pt[1235-:8] - 1:0] dma_axi_bid;
+	input wire dma_axi_arvalid;
+	output wire dma_axi_arready;
+	input wire [pt[1235-:8] - 1:0] dma_axi_arid;
+	input wire [31:0] dma_axi_araddr;
+	input wire [2:0] dma_axi_arsize;
+	output wire dma_axi_rvalid;
+	input wire dma_axi_rready;
+	output wire [pt[1235-:8] - 1:0] dma_axi_rid;
+	output wire [63:0] dma_axi_rdata;
+	output wire [1:0] dma_axi_rresp;
+	output wire dma_axi_rlast;
+	localparam DEPTH = pt[1257-:7];
+	localparam DEPTH_PTR = $clog2(DEPTH);
+	localparam NACK_COUNT = 7;
+	wire [DEPTH - 1:0] fifo_valid;
+	wire [(DEPTH * 2) - 1:0] fifo_error;
+	wire [DEPTH - 1:0] fifo_error_bus;
+	wire [DEPTH - 1:0] fifo_rpend;
+	wire [DEPTH - 1:0] fifo_done;
+	wire [DEPTH - 1:0] fifo_done_bus;
+	wire [(DEPTH * 32) - 1:0] fifo_addr;
+	wire [(DEPTH * 3) - 1:0] fifo_sz;
+	wire [(DEPTH * 8) - 1:0] fifo_byteen;
+	wire [DEPTH - 1:0] fifo_write;
+	wire [DEPTH - 1:0] fifo_posted_write;
+	wire [DEPTH - 1:0] fifo_dbg;
+	wire [(DEPTH * 64) - 1:0] fifo_data;
+	wire [(DEPTH * pt[1235-:8]) - 1:0] fifo_tag;
+	wire [(DEPTH * pt[1250-:9]) - 1:0] fifo_mid;
+	wire [(DEPTH * pt[1241-:6]) - 1:0] fifo_prty;
+	wire [DEPTH - 1:0] fifo_cmd_en;
+	wire [DEPTH - 1:0] fifo_data_en;
+	wire [DEPTH - 1:0] fifo_pend_en;
+	wire [DEPTH - 1:0] fifo_done_en;
+	wire [DEPTH - 1:0] fifo_done_bus_en;
+	wire [DEPTH - 1:0] fifo_error_en;
+	wire [DEPTH - 1:0] fifo_error_bus_en;
+	wire [DEPTH - 1:0] fifo_reset;
+	wire [(DEPTH * 2) - 1:0] fifo_error_in;
+	wire [(DEPTH * 64) - 1:0] fifo_data_in;
+	wire fifo_write_in;
+	wire fifo_posted_write_in;
+	wire fifo_dbg_in;
+	wire [31:0] fifo_addr_in;
+	wire [2:0] fifo_sz_in;
+	wire [7:0] fifo_byteen_in;
+	wire [DEPTH_PTR - 1:0] RspPtr;
+	wire [DEPTH_PTR - 1:0] NxtRspPtr;
+	wire [DEPTH_PTR - 1:0] WrPtr;
+	wire [DEPTH_PTR - 1:0] NxtWrPtr;
+	wire [DEPTH_PTR - 1:0] RdPtr;
+	wire [DEPTH_PTR - 1:0] NxtRdPtr;
+	wire WrPtrEn;
+	wire RdPtrEn;
+	wire RspPtrEn;
+	wire [1:0] dma_dbg_sz;
+	wire [1:0] dma_dbg_addr;
+	wire [31:0] dma_dbg_mem_rddata;
+	wire [31:0] dma_dbg_mem_wrdata;
+	wire dma_dbg_cmd_error;
+	wire dma_dbg_cmd_done_q;
+	wire fifo_full;
+	wire fifo_full_spec;
+	wire fifo_empty;
+	wire dma_address_error;
+	wire dma_alignment_error;
+	reg [3:0] num_fifo_vld;
+	wire dma_mem_req;
+	wire [31:0] dma_mem_addr_int;
+	wire [2:0] dma_mem_sz_int;
+	wire [7:0] dma_mem_byteen;
+	wire dma_mem_addr_in_dccm;
+	wire dma_mem_addr_in_iccm;
+	wire dma_mem_addr_in_pic;
+	wire dma_mem_addr_in_pic_region_nc;
+	wire dma_mem_addr_in_dccm_region_nc;
+	wire dma_mem_addr_in_iccm_region_nc;
+	wire [2:0] dma_nack_count;
+	wire [2:0] dma_nack_count_d;
+	wire [2:0] dma_nack_count_csr;
+	wire dma_buffer_c1_clken;
+	wire dma_free_clken;
+	wire dma_buffer_c1_clk;
+	wire dma_free_clk;
+	wire dma_bus_clk;
+	wire bus_rsp_valid;
+	wire bus_rsp_sent;
+	wire bus_cmd_valid;
+	wire bus_cmd_sent;
+	wire bus_cmd_write;
+	wire bus_cmd_posted_write;
+	wire [7:0] bus_cmd_byteen;
+	wire [2:0] bus_cmd_sz;
+	wire [31:0] bus_cmd_addr;
+	wire [63:0] bus_cmd_wdata;
+	wire [pt[1235-:8] - 1:0] bus_cmd_tag;
+	wire [pt[1250-:9] - 1:0] bus_cmd_mid;
+	wire [pt[1241-:6] - 1:0] bus_cmd_prty;
+	wire bus_posted_write_done;
+	wire fifo_full_spec_bus;
+	wire dbg_dma_bubble_bus;
+	wire stall_dma_in;
+	wire dma_fifo_ready;
+	wire wrbuf_en;
+	wire wrbuf_data_en;
+	wire wrbuf_cmd_sent;
+	wire wrbuf_rst;
+	wire wrbuf_data_rst;
+	wire wrbuf_vld;
+	wire wrbuf_data_vld;
+	wire [pt[1235-:8] - 1:0] wrbuf_tag;
+	wire [2:0] wrbuf_sz;
+	wire [31:0] wrbuf_addr;
+	wire [63:0] wrbuf_data;
+	wire [7:0] wrbuf_byteen;
+	wire rdbuf_en;
+	wire rdbuf_cmd_sent;
+	wire rdbuf_rst;
+	wire rdbuf_vld;
+	wire [pt[1235-:8] - 1:0] rdbuf_tag;
+	wire [2:0] rdbuf_sz;
+	wire [31:0] rdbuf_addr;
+	wire axi_mstr_prty_in;
+	wire axi_mstr_prty_en;
+	wire axi_mstr_priority;
+	wire axi_mstr_sel;
+	wire axi_rsp_valid;
+	wire axi_rsp_sent;
+	wire axi_rsp_write;
+	wire [pt[1235-:8] - 1:0] axi_rsp_tag;
+	wire [1:0] axi_rsp_error;
+	wire [63:0] axi_rsp_rdata;
+	assign fifo_addr_in[31:0] = (dbg_cmd_valid ? dbg_cmd_addr[31:0] : bus_cmd_addr[31:0]);
+	assign fifo_byteen_in[7:0] = {8 {~dbg_cmd_valid}} & bus_cmd_byteen[7:0];
+	assign fifo_sz_in[2:0] = (dbg_cmd_valid ? {1'b0, dbg_cmd_size[1:0]} : bus_cmd_sz[2:0]);
+	assign fifo_write_in = (dbg_cmd_valid ? dbg_cmd_write : bus_cmd_write);
+	assign fifo_posted_write_in = ~dbg_cmd_valid & bus_cmd_posted_write;
+	assign fifo_dbg_in = dbg_cmd_valid;
+	generate
+		genvar i;
+		for (i = 0; i < DEPTH; i = i + 1) begin : GenFifo
+			assign fifo_cmd_en[i] = ((bus_cmd_sent & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1])) & (i == WrPtr[DEPTH_PTR - 1:0]);
+			function automatic [DEPTH_PTR - 1:0] sv2v_cast_87E0F;
+				input reg [DEPTH_PTR - 1:0] inp;
+				sv2v_cast_87E0F = inp;
+			endfunction
+			assign fifo_data_en[i] = ((((((bus_cmd_sent & fifo_write_in) & dma_bus_clk_en) | ((dbg_cmd_valid & dbg_cmd_type[1]) & dbg_cmd_write)) & (i == WrPtr[DEPTH_PTR - 1:0])) | ((dma_address_error | dma_alignment_error) & (i == RdPtr[DEPTH_PTR - 1:0]))) | (dccm_dma_rvalid & (i == sv2v_cast_87E0F(dccm_dma_rtag[2:0])))) | (iccm_dma_rvalid & (i == sv2v_cast_87E0F(iccm_dma_rtag[2:0])));
+			assign fifo_pend_en[i] = ((dma_dccm_req | dma_iccm_req) & ~dma_mem_write) & (i == RdPtr[DEPTH_PTR - 1:0]);
+			assign fifo_error_en[i] = ((((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error) & (i == RdPtr[DEPTH_PTR - 1:0])) | ((dccm_dma_rvalid & dccm_dma_ecc_error) & (i == sv2v_cast_87E0F(dccm_dma_rtag[2:0])))) | ((iccm_dma_rvalid & iccm_dma_ecc_error) & (i == sv2v_cast_87E0F(iccm_dma_rtag[2:0])));
+			assign fifo_error_bus_en[i] = ((|fifo_error_in[(i * 2) + 1-:2] & fifo_error_en[i]) | |fifo_error[i * 2+:2]) & dma_bus_clk_en;
+			assign fifo_done_en[i] = ((((|fifo_error[i * 2+:2] | fifo_error_en[i]) | ((dma_dccm_req | dma_iccm_req) & dma_mem_write)) & (i == RdPtr[DEPTH_PTR - 1:0])) | (dccm_dma_rvalid & (i == sv2v_cast_87E0F(dccm_dma_rtag[2:0])))) | (iccm_dma_rvalid & (i == sv2v_cast_87E0F(iccm_dma_rtag[2:0])));
+			assign fifo_done_bus_en[i] = (fifo_done_en[i] | fifo_done[i]) & dma_bus_clk_en;
+			assign fifo_reset[i] = (((bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en) | dma_dbg_cmd_done) & (i == RspPtr[DEPTH_PTR - 1:0]);
+			assign fifo_error_in[i * 2+:2] = (dccm_dma_rvalid & (i == sv2v_cast_87E0F(dccm_dma_rtag[2:0])) ? {1'b0, dccm_dma_ecc_error} : (iccm_dma_rvalid & (i == sv2v_cast_87E0F(iccm_dma_rtag[2:0])) ? {1'b0, iccm_dma_ecc_error} : {(dma_address_error | dma_alignment_error) | dma_dbg_cmd_error, dma_alignment_error}));
+			assign fifo_data_in[i * 64+:64] = (fifo_error_en[i] & |fifo_error_in[i * 2+:2] ? {32'b00000000000000000000000000000000, fifo_addr[i * 32+:32]} : (dccm_dma_rvalid & (i == sv2v_cast_87E0F(dccm_dma_rtag[2:0])) ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid & (i == sv2v_cast_87E0F(iccm_dma_rtag[2:0])) ? iccm_dma_rdata[63:0] : (dbg_cmd_valid ? {2 {dma_dbg_mem_wrdata[31:0]}} : bus_cmd_wdata[63:0]))));
+			rvdffsc #(.WIDTH(1)) fifo_valid_dff(
+				.din(1'b1),
+				.dout(fifo_valid[i]),
+				.en(fifo_cmd_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffsc #(.WIDTH(2)) fifo_error_dff(
+				.din(fifo_error_in[i * 2+:2]),
+				.dout(fifo_error[i * 2+:2]),
+				.en(fifo_error_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffsc #(.WIDTH(1)) fifo_error_bus_dff(
+				.din(1'b1),
+				.dout(fifo_error_bus[i]),
+				.en(fifo_error_bus_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffsc #(.WIDTH(1)) fifo_rpend_dff(
+				.din(1'b1),
+				.dout(fifo_rpend[i]),
+				.en(fifo_pend_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffsc #(.WIDTH(1)) fifo_done_dff(
+				.din(1'b1),
+				.dout(fifo_done[i]),
+				.en(fifo_done_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffsc #(.WIDTH(1)) fifo_done_bus_dff(
+				.din(1'b1),
+				.dout(fifo_done_bus[i]),
+				.en(fifo_done_bus_en[i]),
+				.clear(fifo_reset[i]),
+				.clk(dma_free_clk),
+				.rst_l(rst_l)
+			);
+			rvdffe #(.WIDTH(32)) fifo_addr_dff(
+				.din(fifo_addr_in[31:0]),
+				.dout(fifo_addr[i * 32+:32]),
+				.en(fifo_cmd_en[i]),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+			rvdffs #(.WIDTH(3)) fifo_sz_dff(
+				.din(fifo_sz_in[2:0]),
+				.dout(fifo_sz[i * 3+:3]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(8)) fifo_byteen_dff(
+				.din(fifo_byteen_in[7:0]),
+				.dout(fifo_byteen[i * 8+:8]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) fifo_write_dff(
+				.din(fifo_write_in),
+				.dout(fifo_write[i]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) fifo_posted_write_dff(
+				.din(fifo_posted_write_in),
+				.dout(fifo_posted_write[i]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) fifo_dbg_dff(
+				.din(fifo_dbg_in),
+				.dout(fifo_dbg[i]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffe #(.WIDTH(64)) fifo_data_dff(
+				.din(fifo_data_in[i * 64+:64]),
+				.dout(fifo_data[i * 64+:64]),
+				.en(fifo_data_en[i]),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+			rvdffs #(.WIDTH(pt[1235-:8])) fifo_tag_dff(
+				.din(bus_cmd_tag[pt[1235-:8] - 1:0]),
+				.dout(fifo_tag[(i * pt[1235-:8]) + (pt[1235-:8] - 1)-:pt[1235-:8]]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(pt[1250-:9])) fifo_mid_dff(
+				.din(bus_cmd_mid[pt[1250-:9] - 1:0]),
+				.dout(fifo_mid[(i * pt[1250-:9]) + (pt[1250-:9] - 1)-:pt[1250-:9]]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(pt[1241-:6])) fifo_prty_dff(
+				.din(bus_cmd_prty[pt[1241-:6] - 1:0]),
+				.dout(fifo_prty[(i * pt[1241-:6]) + (pt[1241-:6] - 1)-:pt[1241-:6]]),
+				.en(fifo_cmd_en[i]),
+				.clk(dma_buffer_c1_clk),
+				.rst_l(rst_l)
+			);
+		end
+	endgenerate
+	assign NxtWrPtr[DEPTH_PTR - 1:0] = (WrPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR {1'sb0}} : WrPtr[DEPTH_PTR - 1:0] + 1'b1);
+	assign NxtRdPtr[DEPTH_PTR - 1:0] = (RdPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR {1'sb0}} : RdPtr[DEPTH_PTR - 1:0] + 1'b1);
+	assign NxtRspPtr[DEPTH_PTR - 1:0] = (RspPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR {1'sb0}} : RspPtr[DEPTH_PTR - 1:0] + 1'b1);
+	assign WrPtrEn = |fifo_cmd_en[DEPTH - 1:0];
+	assign RdPtrEn = (dma_dccm_req | dma_iccm_req) | ((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error);
+	assign RspPtrEn = dma_dbg_cmd_done | ((bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en);
+	rvdffs #(.WIDTH(DEPTH_PTR)) WrPtr_dff(
+		.din(NxtWrPtr[DEPTH_PTR - 1:0]),
+		.dout(WrPtr[DEPTH_PTR - 1:0]),
+		.en(WrPtrEn),
+		.clk(dma_free_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(DEPTH_PTR)) RdPtr_dff(
+		.din(NxtRdPtr[DEPTH_PTR - 1:0]),
+		.dout(RdPtr[DEPTH_PTR - 1:0]),
+		.en(RdPtrEn),
+		.clk(dma_free_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(DEPTH_PTR)) RspPtr_dff(
+		.din(NxtRspPtr[DEPTH_PTR - 1:0]),
+		.dout(RspPtr[DEPTH_PTR - 1:0]),
+		.en(RspPtrEn),
+		.clk(dma_free_clk),
+		.rst_l(rst_l)
+	);
+	assign fifo_full = fifo_full_spec_bus;
+	always @(*) begin
+		num_fifo_vld[3:0] = {3'b000, bus_cmd_sent} - {3'b000, bus_rsp_sent};
+		begin : sv2v_autoblock_41
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				num_fifo_vld[3:0] = num_fifo_vld[3:0] + {3'b000, fifo_valid[i]};
+		end
+	end
+	assign fifo_full_spec = num_fifo_vld[3:0] >= DEPTH;
+	assign dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus);
+	assign dma_address_error = ((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & ~fifo_dbg[RdPtr]) & ~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm);
+	assign dma_alignment_error = (((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & ~fifo_dbg[RdPtr]) & ~dma_address_error) & ((((((((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | ((dma_mem_sz_int[2:0] == 3'h2) & |dma_mem_addr_int[1:0])) | ((dma_mem_sz_int[2:0] == 3'h3) & |dma_mem_addr_int[2:0])) | (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))) | ((dma_mem_addr_in_dccm & dma_mem_write) & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))) | ((dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2)) & (dma_mem_byteen[dma_mem_addr_int[2:0]+:4] != 4'hf))) | ((dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3)) & ~(((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0)) | (dma_mem_byteen[7:0] == 8'hff))));
+	assign dma_dbg_ready = fifo_empty & dbg_dma_bubble;
+	assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr]) & fifo_done[RspPtr];
+	assign dma_dbg_cmd_fail = |fifo_error[RspPtr * 2+:2];
+	assign dma_dbg_sz[1:0] = fifo_sz[(RspPtr * 3) + 1-:2];
+	assign dma_dbg_addr[1:0] = fifo_addr[(RspPtr * 32) + 1-:2];
+	assign dma_dbg_mem_rddata[31:0] = (fifo_addr[(RspPtr * 32) + 2] ? fifo_data[(RspPtr * 64) + 63-:32] : fifo_data[(RspPtr * 64) + 31-:32]);
+	assign dma_dbg_rddata[31:0] = (({32 {dma_dbg_sz[1:0] == 2'h0}} & ((dma_dbg_mem_rddata[31:0] >> (8 * dma_dbg_addr[1:0])) & 32'h000000ff)) | ({32 {dma_dbg_sz[1:0] == 2'h1}} & ((dma_dbg_mem_rddata[31:0] >> (16 * dma_dbg_addr[1])) & 32'h0000ffff))) | ({32 {dma_dbg_sz[1:0] == 2'h2}} & dma_dbg_mem_rddata[31:0]);
+	assign dma_dbg_cmd_error = ((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & fifo_dbg[RdPtr]) & (~((dma_mem_addr_in_dccm | dma_mem_addr_in_iccm) | dma_mem_addr_in_pic) | ((dma_mem_addr_in_iccm | dma_mem_addr_in_pic) & (dma_mem_sz_int[1:0] != 2'b10)));
+	assign dma_dbg_mem_wrdata[31:0] = (({32 {dbg_cmd_size[1:0] == 2'h0}} & {4 {dbg_cmd_wrdata[7:0]}}) | ({32 {dbg_cmd_size[1:0] == 2'h1}} & {2 {dbg_cmd_wrdata[15:0]}})) | ({32 {dbg_cmd_size[1:0] == 2'h2}} & dbg_cmd_wrdata[31:0]);
+	assign dma_dccm_stall_any = (dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic)) & (dma_nack_count >= dma_nack_count_csr);
+	assign dma_iccm_stall_any = (dma_mem_req & dma_mem_addr_in_iccm) & (dma_nack_count >= dma_nack_count_csr);
+	assign fifo_empty = ~(|fifo_valid[DEPTH - 1:0] | bus_cmd_sent);
+	assign dma_nack_count_csr[2:0] = dec_tlu_dma_qos_prty[2:0];
+	assign dma_nack_count_d[2:0] = (dma_nack_count[2:0] >= dma_nack_count_csr[2:0] ? {3 {~(dma_dccm_req | dma_iccm_req)}} & dma_nack_count[2:0] : (dma_mem_req & ~(dma_dccm_req | dma_iccm_req) ? dma_nack_count[2:0] + 1'b1 : 3'b000));
+	rvdffs #(.WIDTH(3)) nack_count_dff(
+		.din(dma_nack_count_d[2:0]),
+		.dout(dma_nack_count[2:0]),
+		.en(dma_mem_req),
+		.clk(dma_free_clk),
+		.rst_l(rst_l)
+	);
+	assign dma_mem_req = ((fifo_valid[RdPtr] & ~fifo_rpend[RdPtr]) & ~fifo_done[RdPtr]) & ~((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error);
+	assign dma_dccm_req = (dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic)) & dccm_ready;
+	assign dma_iccm_req = (dma_mem_req & dma_mem_addr_in_iccm) & iccm_ready;
+	function automatic [2:0] sv2v_cast_3;
+		input reg [2:0] inp;
+		sv2v_cast_3 = inp;
+	endfunction
+	assign dma_mem_tag[2:0] = sv2v_cast_3(RdPtr);
+	assign dma_mem_addr_int[31:0] = fifo_addr[RdPtr * 32+:32];
+	assign dma_mem_sz_int[2:0] = fifo_sz[RdPtr * 3+:3];
+	assign dma_mem_addr[31:0] = ((dma_mem_write & ~fifo_dbg[RdPtr]) & (dma_mem_byteen[7:0] == 8'hf0) ? {dma_mem_addr_int[31:3], 1'b1, dma_mem_addr_int[1:0]} : dma_mem_addr_int[31:0]);
+	assign dma_mem_sz[2:0] = ((dma_mem_write & ~fifo_dbg[RdPtr]) & ((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0)) ? 3'h2 : dma_mem_sz_int[2:0]);
+	assign dma_mem_byteen[7:0] = fifo_byteen[RdPtr * 8+:8];
+	assign dma_mem_write = fifo_write[RdPtr];
+	assign dma_mem_wdata[63:0] = fifo_data[RdPtr * 64+:64];
+	assign dma_pmu_dccm_read = dma_dccm_req & ~dma_mem_write;
+	assign dma_pmu_dccm_write = dma_dccm_req & dma_mem_write;
+	assign dma_pmu_any_read = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write;
+	assign dma_pmu_any_write = (dma_dccm_req | dma_iccm_req) & dma_mem_write;
+	generate
+		if (pt[1365-:5]) begin : Gen_dccm_enable
+			rvrangecheck #(
+				.CCM_SADR(pt[1325-:36]),
+				.CCM_SIZE(pt[1289-:14])
+			) addr_dccm_rangecheck(
+				.addr(dma_mem_addr_int[31:0]),
+				.in_range(dma_mem_addr_in_dccm),
+				.in_region(dma_mem_addr_in_dccm_region_nc)
+			);
+		end
+		else begin : Gen_dccm_disable
+			assign dma_mem_addr_in_dccm = 1'b0;
+			assign dma_mem_addr_in_dccm_region_nc = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[927-:5]) begin : Gen_iccm_enable
+			rvrangecheck #(
+				.CCM_SADR(pt[887-:36]),
+				.CCM_SIZE(pt[851-:14])
+			) addr_iccm_rangecheck(
+				.addr(dma_mem_addr_int[31:0]),
+				.in_range(dma_mem_addr_in_iccm),
+				.in_region(dma_mem_addr_in_iccm_region_nc)
+			);
+		end
+		else begin : Gen_iccm_disable
+			assign dma_mem_addr_in_iccm = 1'b0;
+			assign dma_mem_addr_in_iccm_region_nc = 1'b0;
+		end
+	endgenerate
+	rvrangecheck #(
+		.CCM_SADR(pt[130-:36]),
+		.CCM_SIZE(pt[69-:13])
+	) addr_pic_rangecheck(
+		.addr(dma_mem_addr_int[31:0]),
+		.in_range(dma_mem_addr_in_pic),
+		.in_region(dma_mem_addr_in_pic_region_nc)
+	);
+	rvdff_fpga #(.WIDTH(1)) fifo_full_bus_ff(
+		.din(fifo_full_spec),
+		.dout(fifo_full_spec_bus),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) dbg_dma_bubble_ff(
+		.din(dbg_dma_bubble),
+		.dout(dbg_dma_bubble_bus),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) dma_dbg_cmd_doneff(
+		.din(dma_dbg_cmd_done),
+		.dout(dma_dbg_cmd_done_q),
+		.clk(free_clk),
+		.rst_l(rst_l)
+	);
+	assign dma_buffer_c1_clken = ((bus_cmd_valid & dma_bus_clk_en) | dbg_cmd_valid) | clk_override;
+	assign dma_free_clken = (((((bus_cmd_valid | bus_rsp_valid) | dbg_cmd_valid) | dma_dbg_cmd_done) | dma_dbg_cmd_done_q) | |fifo_valid[DEPTH - 1:0]) | clk_override;
+	rvoclkhdr dma_buffer_c1cgc(
+		.en(dma_buffer_c1_clken),
+		.l1clk(dma_buffer_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr dma_free_cgc(
+		.en(dma_free_clken),
+		.l1clk(dma_free_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr dma_bus_cgc(
+		.en(dma_bus_clk_en),
+		.l1clk(dma_bus_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign wrbuf_en = dma_axi_awvalid & dma_axi_awready;
+	assign wrbuf_data_en = dma_axi_wvalid & dma_axi_wready;
+	assign wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write;
+	assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en;
+	assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;
+	rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff(
+		.din(1'b1),
+		.dout(wrbuf_vld),
+		.en(wrbuf_en),
+		.clear(wrbuf_rst),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff(
+		.din(1'b1),
+		.dout(wrbuf_data_vld),
+		.en(wrbuf_data_en),
+		.clear(wrbuf_data_rst),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(pt[1235-:8])) wrbuf_tagff(
+		.din(dma_axi_awid[pt[1235-:8] - 1:0]),
+		.dout(wrbuf_tag[pt[1235-:8] - 1:0]),
+		.en(wrbuf_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(3)) wrbuf_szff(
+		.din(dma_axi_awsize[2:0]),
+		.dout(wrbuf_sz[2:0]),
+		.en(wrbuf_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) wrbuf_addrff(
+		.din(dma_axi_awaddr[31:0]),
+		.dout(wrbuf_addr[31:0]),
+		.en(wrbuf_en & dma_bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffe #(.WIDTH(64)) wrbuf_dataff(
+		.din(dma_axi_wdata[63:0]),
+		.dout(wrbuf_data[63:0]),
+		.en(wrbuf_data_en & dma_bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff(
+		.din(dma_axi_wstrb[7:0]),
+		.dout(wrbuf_byteen[7:0]),
+		.en(wrbuf_data_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	assign rdbuf_en = dma_axi_arvalid & dma_axi_arready;
+	assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write;
+	assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en;
+	rvdffsc_fpga #(.WIDTH(1)) rdbuf_vldff(
+		.din(1'b1),
+		.dout(rdbuf_vld),
+		.en(rdbuf_en),
+		.clear(rdbuf_rst),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(pt[1235-:8])) rdbuf_tagff(
+		.din(dma_axi_arid[pt[1235-:8] - 1:0]),
+		.dout(rdbuf_tag[pt[1235-:8] - 1:0]),
+		.en(rdbuf_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(3)) rdbuf_szff(
+		.din(dma_axi_arsize[2:0]),
+		.dout(rdbuf_sz[2:0]),
+		.en(rdbuf_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) rdbuf_addrff(
+		.din(dma_axi_araddr[31:0]),
+		.dout(rdbuf_addr[31:0]),
+		.en(rdbuf_en & dma_bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent);
+	assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent);
+	assign dma_axi_arready = ~(rdbuf_vld & ~rdbuf_cmd_sent);
+	assign bus_cmd_valid = (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld;
+	assign bus_cmd_sent = bus_cmd_valid & dma_fifo_ready;
+	assign bus_cmd_write = axi_mstr_sel;
+	assign bus_cmd_posted_write = 1'b0;
+	assign bus_cmd_addr[31:0] = (axi_mstr_sel ? wrbuf_addr[31:0] : rdbuf_addr[31:0]);
+	assign bus_cmd_sz[2:0] = (axi_mstr_sel ? wrbuf_sz[2:0] : rdbuf_sz[2:0]);
+	assign bus_cmd_wdata[63:0] = wrbuf_data[63:0];
+	assign bus_cmd_byteen[7:0] = wrbuf_byteen[7:0];
+	assign bus_cmd_tag[pt[1235-:8] - 1:0] = (axi_mstr_sel ? wrbuf_tag[pt[1235-:8] - 1:0] : rdbuf_tag[pt[1235-:8] - 1:0]);
+	assign bus_cmd_mid[pt[1250-:9] - 1:0] = {pt[1250-:9] {1'sb0}};
+	assign bus_cmd_prty[pt[1241-:6] - 1:0] = {pt[1241-:6] {1'sb0}};
+	assign axi_mstr_sel = ((wrbuf_vld & wrbuf_data_vld) & rdbuf_vld ? axi_mstr_priority : wrbuf_vld & wrbuf_data_vld);
+	assign axi_mstr_prty_in = ~axi_mstr_priority;
+	assign axi_mstr_prty_en = bus_cmd_sent;
+	rvdffs_fpga #(.WIDTH(1)) mstr_prtyff(
+		.din(axi_mstr_prty_in),
+		.dout(axi_mstr_priority),
+		.en(axi_mstr_prty_en),
+		.clk(dma_bus_clk),
+		.clken(dma_bus_clk_en),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	assign axi_rsp_valid = (fifo_valid[RspPtr] & ~fifo_dbg[RspPtr]) & fifo_done_bus[RspPtr];
+	assign axi_rsp_rdata[63:0] = fifo_data[RspPtr * 64+:64];
+	assign axi_rsp_write = fifo_write[RspPtr];
+	assign axi_rsp_error[1:0] = (fifo_error[RspPtr * 2] ? 2'b10 : (fifo_error[(RspPtr * 2) + 1] ? 2'b11 : 2'b00));
+	assign axi_rsp_tag[pt[1235-:8] - 1:0] = fifo_tag[RspPtr * pt[1235-:8]+:pt[1235-:8]];
+	assign dma_axi_bvalid = axi_rsp_valid & axi_rsp_write;
+	assign dma_axi_bresp[1:0] = axi_rsp_error[1:0];
+	assign dma_axi_bid[pt[1235-:8] - 1:0] = axi_rsp_tag[pt[1235-:8] - 1:0];
+	assign dma_axi_rvalid = axi_rsp_valid & ~axi_rsp_write;
+	assign dma_axi_rresp[1:0] = axi_rsp_error;
+	assign dma_axi_rdata[63:0] = axi_rsp_rdata[63:0];
+	assign dma_axi_rlast = 1'b1;
+	assign dma_axi_rid[pt[1235-:8] - 1:0] = axi_rsp_tag[pt[1235-:8] - 1:0];
+	assign bus_posted_write_done = 1'b0;
+	assign bus_rsp_valid = dma_axi_bvalid | dma_axi_rvalid;
+	assign bus_rsp_sent = (dma_axi_bvalid & dma_axi_bready) | (dma_axi_rvalid & dma_axi_rready);
+	assign dma_active = (wrbuf_vld | rdbuf_vld) | |fifo_valid[DEPTH - 1:0];
+endmodule
+module eb1_exu_alu_ctl (
+	clk,
+	rst_l,
+	scan_mode,
+	flush_upper_x,
+	flush_lower_r,
+	enable,
+	valid_in,
+	ap,
+	csr_ren_in,
+	csr_rddata_in,
+	a_in,
+	b_in,
+	pc_in,
+	pp_in,
+	brimm_in,
+	result_ff,
+	flush_upper_out,
+	flush_final_out,
+	flush_path_out,
+	pc_ff,
+	pred_correct_out,
+	predict_p_out
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire flush_upper_x;
+	input wire flush_lower_r;
+	input wire enable;
+	input wire valid_in;
+	input wire [43:0] ap;
+	input wire csr_ren_in;
+	input wire [31:0] csr_rddata_in;
+	input wire signed [31:0] a_in;
+	input wire [31:0] b_in;
+	input wire [31:1] pc_in;
+	input wire [55:0] pp_in;
+	input wire [12:1] brimm_in;
+	output wire [31:0] result_ff;
+	output wire flush_upper_out;
+	output wire flush_final_out;
+	output wire [31:1] flush_path_out;
+	output wire [31:1] pc_ff;
+	output wire pred_correct_out;
+	output reg [55:0] predict_p_out;
+	wire [31:0] zba_a_in;
+	wire [31:0] aout;
+	wire cout;
+	wire ov;
+	wire neg;
+	wire [31:0] lout;
+	wire [31:0] sout;
+	wire sel_shift;
+	wire sel_adder;
+	wire slt_one;
+	wire actual_taken;
+	wire [31:1] pcout;
+	wire cond_mispredict;
+	wire target_mispredict;
+	wire eq;
+	wire ne;
+	wire lt;
+	wire ge;
+	wire any_jal;
+	wire [1:0] newhist;
+	wire sel_pc;
+	wire [31:0] csr_write_data;
+	wire [31:0] result;
+	wire ap_clz;
+	wire ap_ctz;
+	wire ap_pcnt;
+	wire ap_sext_b;
+	wire ap_sext_h;
+	wire ap_min;
+	wire ap_max;
+	wire ap_pack;
+	wire ap_packu;
+	wire ap_packh;
+	wire ap_rol;
+	wire ap_ror;
+	wire ap_rev;
+	wire ap_rev8;
+	wire ap_orc_b;
+	wire ap_orc16;
+	wire ap_zbb;
+	wire ap_sbset;
+	wire ap_sbclr;
+	wire ap_sbinv;
+	wire ap_sbext;
+	wire ap_slo;
+	wire ap_sro;
+	wire ap_sh1add;
+	wire ap_sh2add;
+	wire ap_sh3add;
+	wire ap_zba;
+	generate
+		if (pt[2207-:5] == 1) begin
+			assign ap_clz = ap[43];
+			assign ap_ctz = ap[42];
+			assign ap_pcnt = ap[41];
+			assign ap_sext_b = ap[40];
+			assign ap_sext_h = ap[39];
+			assign ap_min = ap[36];
+			assign ap_max = ap[35];
+		end
+		else begin
+			assign ap_clz = 1'b0;
+			assign ap_ctz = 1'b0;
+			assign ap_pcnt = 1'b0;
+			assign ap_sext_b = 1'b0;
+			assign ap_sext_h = 1'b0;
+			assign ap_min = 1'b0;
+			assign ap_max = 1'b0;
+		end
+	endgenerate
+	generate
+		if ((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) begin
+			assign ap_pack = ap[34];
+			assign ap_packu = ap[33];
+			assign ap_packh = ap[32];
+			assign ap_rol = ap[31];
+			assign ap_ror = ap[30];
+			assign ap_rev = ap[29] & (b_in[4:0] == 5'b11111);
+			assign ap_rev8 = ap[29] & (b_in[4:0] == 5'b11000);
+			assign ap_orc_b = ap[28] & (b_in[4:0] == 5'b00111);
+			assign ap_orc16 = ap[28] & (b_in[4:0] == 5'b10000);
+			assign ap_zbb = ap[27];
+		end
+		else begin
+			assign ap_pack = 1'b0;
+			assign ap_packu = 1'b0;
+			assign ap_packh = 1'b0;
+			assign ap_rol = 1'b0;
+			assign ap_ror = 1'b0;
+			assign ap_rev = 1'b0;
+			assign ap_rev8 = 1'b0;
+			assign ap_orc_b = 1'b0;
+			assign ap_orc16 = 1'b0;
+			assign ap_zbb = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2177-:5] == 1) begin
+			assign ap_sbset = ap[26];
+			assign ap_sbclr = ap[25];
+			assign ap_sbinv = ap[24];
+			assign ap_sbext = ap[23];
+		end
+		else begin
+			assign ap_sbset = 1'b0;
+			assign ap_sbclr = 1'b0;
+			assign ap_sbinv = 1'b0;
+			assign ap_sbext = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2187-:5] == 1) begin
+			assign ap_slo = ap[38];
+			assign ap_sro = ap[37];
+		end
+		else begin
+			assign ap_slo = 1'b0;
+			assign ap_sro = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2212-:5] == 1) begin
+			assign ap_sh1add = ap[22];
+			assign ap_sh2add = ap[21];
+			assign ap_sh3add = ap[20];
+			assign ap_zba = ap[19];
+		end
+		else begin
+			assign ap_sh1add = 1'b0;
+			assign ap_sh2add = 1'b0;
+			assign ap_sh3add = 1'b0;
+			assign ap_zba = 1'b0;
+		end
+	endgenerate
+	rvdffpcie #(.WIDTH(31)) i_pc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(enable),
+		.din(pc_in[31:1]),
+		.dout(pc_ff[31:1])
+	);
+	rvdffe #(.WIDTH(32)) i_result_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(enable & valid_in),
+		.din(result[31:0]),
+		.dout(result_ff[31:0])
+	);
+	assign zba_a_in[31:0] = ((({32 {ap_sh1add}} & {a_in[30:0], 1'b0}) | ({32 {ap_sh2add}} & {a_in[29:0], 2'b00})) | ({32 {ap_sh3add}} & {a_in[28:0], 3'b000})) | ({32 {~ap_zba}} & a_in[31:0]);
+	wire [31:0] bm;
+	assign bm[31:0] = (ap[7] ? ~b_in[31:0] : b_in[31:0]);
+	assign {cout, aout[31:0]} = ({1'b0, zba_a_in[31:0]} + {1'b0, bm[31:0]}) + {32'b00000000000000000000000000000000, ap[7]};
+	assign ov = ((~a_in[31] & ~bm[31]) & aout[31]) | ((a_in[31] & bm[31]) & ~aout[31]);
+	assign lt = (~ap[5] & (neg ^ ov)) | (ap[5] & ~cout);
+	assign eq = a_in[31:0] == b_in[31:0];
+	assign ne = ~eq;
+	assign neg = aout[31];
+	assign ge = ~lt;
+	assign lout[31:0] = (((((({32 {csr_ren_in}} & csr_rddata_in[31:0]) | (({32 {ap[18] & ~ap_zbb}} & a_in[31:0]) & b_in[31:0])) | ({32 {ap[17] & ~ap_zbb}} & (a_in[31:0] | b_in[31:0]))) | ({32 {ap[16] & ~ap_zbb}} & (a_in[31:0] ^ b_in[31:0]))) | (({32 {ap[18] & ap_zbb}} & a_in[31:0]) & ~b_in[31:0])) | ({32 {ap[17] & ap_zbb}} & (a_in[31:0] | ~b_in[31:0]))) | ({32 {ap[16] & ap_zbb}} & (a_in[31:0] ^ ~b_in[31:0]));
+	wire [5:0] shift_amount;
+	wire [31:0] shift_mask;
+	wire [62:0] shift_extend;
+	wire [62:0] shift_long;
+	assign shift_amount[5:0] = ((((((({6 {ap[15]}} & (6'd32 - {1'b0, b_in[4:0]})) | ({6 {ap[14]}} & {1'b0, b_in[4:0]})) | ({6 {ap[13]}} & {1'b0, b_in[4:0]})) | ({6 {ap_rol}} & (6'd32 - {1'b0, b_in[4:0]}))) | ({6 {ap_ror}} & {1'b0, b_in[4:0]})) | ({6 {ap_slo}} & (6'd32 - {1'b0, b_in[4:0]}))) | ({6 {ap_sro}} & {1'b0, b_in[4:0]})) | ({6 {ap_sbext}} & {1'b0, b_in[4:0]});
+	assign shift_mask[31:0] = 32'hffffffff << ({5 {ap[15] | ap_slo}} & b_in[4:0]);
+	assign shift_extend[31:0] = a_in[31:0];
+	assign shift_extend[62:32] = ((((({31 {ap[13]}} & {31 {a_in[31]}}) | ({31 {ap[15]}} & a_in[30:0])) | ({31 {ap_rol}} & a_in[30:0])) | ({31 {ap_ror}} & a_in[30:0])) | ({31 {ap_slo}} & a_in[30:0])) | ({31 {ap_sro}} & {31 {1'b1}});
+	assign shift_long[62:0] = shift_extend[62:0] >> shift_amount[4:0];
+	assign sout[31:0] = (shift_long[31:0] & shift_mask[31:0]) | ({32 {ap_slo}} & ~shift_mask[31:0]);
+	wire bitmanip_clz_ctz_sel;
+	wire [31:0] bitmanip_a_reverse_ff;
+	wire [31:0] bitmanip_lzd_in;
+	reg [5:0] bitmanip_dw_lzd_enc;
+	wire [5:0] bitmanip_clz_ctz_result;
+	assign bitmanip_clz_ctz_sel = ap_clz | ap_ctz;
+	assign bitmanip_a_reverse_ff[31:0] = {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7], a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15], a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23], a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]};
+	assign bitmanip_lzd_in[31:0] = ({32 {ap_clz}} & a_in[31:0]) | ({32 {ap_ctz}} & bitmanip_a_reverse_ff[31:0]);
+	reg [31:0] bitmanip_lzd_os;
+	integer i;
+	reg found;
+	always @(*) begin
+		bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0];
+		bitmanip_dw_lzd_enc[5:0] = 6'b000000;
+		found = 1'b0;
+		begin : sv2v_autoblock_42
+			reg signed [31:0] i;
+			for (i = 0; (i < 32); i = i + 1)
+				if(found == 0) begin
+					if (bitmanip_lzd_os[31] == 1'b0) begin
+						bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b000001;
+						bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1;
+					end
+					else
+						found = 1'b1;
+				end
+		end
+	end
+	assign bitmanip_clz_ctz_result[5:0] = {6 {bitmanip_clz_ctz_sel}} & {bitmanip_dw_lzd_enc[5], {5 {~bitmanip_dw_lzd_enc[5]}} & bitmanip_dw_lzd_enc[4:0]};
+	reg [5:0] bitmanip_pcnt;
+	wire [5:0] bitmanip_pcnt_result;
+	integer bitmanip_pcnt_i;
+	always @(*) begin
+		bitmanip_pcnt[5:0] = 6'b000000;
+		for (bitmanip_pcnt_i = 0; bitmanip_pcnt_i < 32; bitmanip_pcnt_i = bitmanip_pcnt_i + 1)
+			bitmanip_pcnt[5:0] = bitmanip_pcnt[5:0] + {5'b00000, a_in[bitmanip_pcnt_i]};
+	end
+	assign bitmanip_pcnt_result[5:0] = {6 {ap_pcnt}} & bitmanip_pcnt[5:0];
+	wire [31:0] bitmanip_sext_result;
+	assign bitmanip_sext_result[31:0] = ({32 {ap_sext_b}} & {{24 {a_in[7]}}, a_in[7:0]}) | ({32 {ap_sext_h}} & {{16 {a_in[15]}}, a_in[15:0]});
+	wire bitmanip_minmax_sel;
+	wire [31:0] bitmanip_minmax_result;
+	assign bitmanip_minmax_sel = ap_min | ap_max;
+	wire bitmanip_minmax_sel_a;
+	assign bitmanip_minmax_sel_a = ge ^ ap_min;
+	assign bitmanip_minmax_result[31:0] = ({32 {bitmanip_minmax_sel & bitmanip_minmax_sel_a}} & a_in[31:0]) | ({32 {bitmanip_minmax_sel & ~bitmanip_minmax_sel_a}} & b_in[31:0]);
+	wire [31:0] bitmanip_pack_result;
+	wire [31:0] bitmanip_packu_result;
+	wire [31:0] bitmanip_packh_result;
+	assign bitmanip_pack_result[31:0] = {32 {ap_pack}} & {b_in[15:0], a_in[15:0]};
+	assign bitmanip_packu_result[31:0] = {32 {ap_packu}} & {b_in[31:16], a_in[31:16]};
+	assign bitmanip_packh_result[31:0] = {32 {ap_packh}} & {16'b0000000000000000, b_in[7:0], a_in[7:0]};
+	wire [31:0] bitmanip_rev_result;
+	wire [31:0] bitmanip_rev8_result;
+	wire [31:0] bitmanip_orc_b_result;
+	wire [31:0] bitmanip_orc16_result;
+	assign bitmanip_rev_result[31:0] = {32 {ap_rev}} & {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7], a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15], a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23], a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]};
+	assign bitmanip_rev8_result[31:0] = {32 {ap_rev8}} & {a_in[7:0], a_in[15:8], a_in[23:16], a_in[31:24]};
+	assign bitmanip_orc_b_result[31:0] = {32 {ap_orc_b}} & {{8 {|a_in[31:24]}}, {8 {|a_in[23:16]}}, {8 {|a_in[15:8]}}, {8 {|a_in[7:0]}}};
+	assign bitmanip_orc16_result[31:0] = {32 {ap_orc16}} & {{a_in[31:16] | a_in[15:0]}, {a_in[31:16] | a_in[15:0]}};
+	wire [31:0] bitmanip_sb_1hot;
+	wire [31:0] bitmanip_sb_data;
+	assign bitmanip_sb_1hot[31:0] = 32'h00000001 << b_in[4:0];
+	assign bitmanip_sb_data[31:0] = (({32 {ap_sbset}} & (a_in[31:0] | bitmanip_sb_1hot[31:0])) | ({32 {ap_sbclr}} & (a_in[31:0] & ~bitmanip_sb_1hot[31:0]))) | ({32 {ap_sbinv}} & (a_in[31:0] ^ bitmanip_sb_1hot[31:0]));
+	assign sel_shift = (((((ap[15] | ap[14]) | ap[13]) | ap_slo) | ap_sro) | ap_rol) | ap_ror;
+	assign sel_adder = ((((ap[8] | ap[7]) | ap_zba) & ~ap[6]) & ~ap_min) & ~ap_max;
+	assign sel_pc = ((ap[4] | pp_in[34]) | pp_in[33]) | pp_in[31];
+	assign csr_write_data[31:0] = (ap[0] ? b_in[31:0] : a_in[31:0]);
+	assign slt_one = ap[6] & lt;
+	assign result[31:0] = (((((((((((((((((lout[31:0] | ({32 {sel_shift}} & sout[31:0])) | ({32 {sel_adder}} & aout[31:0])) | ({32 {sel_pc}} & {pcout[31:1], 1'b0})) | ({32 {ap[1]}} & csr_write_data[31:0])) | {31'b0000000000000000000000000000000, slt_one}) | ({32 {ap_sbext}} & {31'b0000000000000000000000000000000, sout[0]})) | {26'b00000000000000000000000000, bitmanip_clz_ctz_result[5:0]}) | {26'b00000000000000000000000000, bitmanip_pcnt_result[5:0]}) | bitmanip_sext_result[31:0]) | bitmanip_minmax_result[31:0]) | bitmanip_pack_result[31:0]) | bitmanip_packu_result[31:0]) | bitmanip_packh_result[31:0]) | bitmanip_rev_result[31:0]) | bitmanip_rev8_result[31:0]) | bitmanip_orc_b_result[31:0]) | bitmanip_orc16_result[31:0]) | bitmanip_sb_data[31:0];
+	assign any_jal = ((ap[4] | pp_in[34]) | pp_in[33]) | pp_in[31];
+	assign actual_taken = ((((ap[12] & eq) | (ap[11] & ne)) | (ap[10] & lt)) | (ap[9] & ge)) | any_jal;
+	rvbradder ibradder(
+		.pc(pc_in[31:1]),
+		.offset(brimm_in[12:1]),
+		.dout(pcout[31:1])
+	);
+	assign pred_correct_out = (((valid_in & ap[2]) & ~actual_taken) & ~any_jal) | (((valid_in & ap[3]) & actual_taken) & ~any_jal);
+	assign flush_path_out[31:1] = (any_jal ? aout[31:1] : pcout[31:1]);
+	assign cond_mispredict = (ap[3] & ~actual_taken) | (ap[2] & actual_taken);
+	assign target_mispredict = pp_in[31] & (pp_in[30:0] != aout[31:1]);
+	assign flush_upper_out = ((((ap[4] | cond_mispredict) | target_mispredict) & valid_in) & ~flush_upper_x) & ~flush_lower_r;
+	assign flush_final_out = ((((ap[4] | cond_mispredict) | target_mispredict) & valid_in) & ~flush_upper_x) | flush_lower_r;
+	assign newhist[1] = (pp_in[51] & pp_in[50]) | (~pp_in[50] & actual_taken);
+	assign newhist[0] = (~pp_in[51] & ~actual_taken) | (pp_in[51] & actual_taken);
+	always @(*) begin
+		predict_p_out = pp_in;
+		predict_p_out[55] = (~flush_upper_x & ~flush_lower_r) & (cond_mispredict | target_mispredict);
+		predict_p_out[54] = actual_taken;
+		predict_p_out[51] = newhist[1];
+		predict_p_out[50] = newhist[0];
+	end
+endmodule
+module eb1_exu_div_ctl (
+	clk,
+	rst_l,
+	scan_mode,
+	dp,
+	dividend,
+	divisor,
+	cancel,
+	finish_dly,
+	out
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire [2:0] dp;
+	input wire [31:0] dividend;
+	input wire [31:0] divisor;
+	input wire cancel;
+	output wire finish_dly;
+	output wire [31:0] out;
+	wire [31:0] out_raw;
+	assign out[31:0] = {32 {finish_dly}} & out_raw[31:0];
+	generate
+		if (pt[1262-:5] == 0) eb1_exu_div_existing_1bit_cheapshortq i_existing_1bit_div_cheapshortq(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.cancel(cancel),
+			.valid_in(dp[2]),
+			.signed_in(~dp[1]),
+			.rem_in(dp[0]),
+			.dividend_in(dividend[31:0]),
+			.divisor_in(divisor[31:0]),
+			.valid_out(finish_dly),
+			.data_out(out_raw[31:0])
+		);
+	endgenerate
+	generate
+		if ((pt[1262-:5] == 1) & (pt[1269-:7] == 1)) eb1_exu_div_new_1bit_fullshortq i_new_1bit_div_fullshortq(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.cancel(cancel),
+			.valid_in(dp[2]),
+			.signed_in(~dp[1]),
+			.rem_in(dp[0]),
+			.dividend_in(dividend[31:0]),
+			.divisor_in(divisor[31:0]),
+			.valid_out(finish_dly),
+			.data_out(out_raw[31:0])
+		);
+	endgenerate
+	generate
+		if ((pt[1262-:5] == 1) & (pt[1269-:7] == 2)) eb1_exu_div_new_2bit_fullshortq i_new_2bit_div_fullshortq(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.cancel(cancel),
+			.valid_in(dp[2]),
+			.signed_in(~dp[1]),
+			.rem_in(dp[0]),
+			.dividend_in(dividend[31:0]),
+			.divisor_in(divisor[31:0]),
+			.valid_out(finish_dly),
+			.data_out(out_raw[31:0])
+		);
+	endgenerate
+	generate
+		if ((pt[1262-:5] == 1) & (pt[1269-:7] == 3)) eb1_exu_div_new_3bit_fullshortq i_new_3bit_div_fullshortq(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.cancel(cancel),
+			.valid_in(dp[2]),
+			.signed_in(~dp[1]),
+			.rem_in(dp[0]),
+			.dividend_in(dividend[31:0]),
+			.divisor_in(divisor[31:0]),
+			.valid_out(finish_dly),
+			.data_out(out_raw[31:0])
+		);
+	endgenerate
+	generate
+		if ((pt[1262-:5] == 1) & (pt[1269-:7] == 4)) eb1_exu_div_new_4bit_fullshortq i_new_4bit_div_fullshortq(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.cancel(cancel),
+			.valid_in(dp[2]),
+			.signed_in(~dp[1]),
+			.rem_in(dp[0]),
+			.dividend_in(dividend[31:0]),
+			.divisor_in(divisor[31:0]),
+			.valid_out(finish_dly),
+			.data_out(out_raw[31:0])
+		);
+	endgenerate
+endmodule
+module eb1_exu_div_existing_1bit_cheapshortq (
+	clk,
+	rst_l,
+	scan_mode,
+	cancel,
+	valid_in,
+	signed_in,
+	rem_in,
+	dividend_in,
+	divisor_in,
+	valid_out,
+	data_out
+);
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire cancel;
+	input wire valid_in;
+	input wire signed_in;
+	input wire rem_in;
+	input wire [31:0] dividend_in;
+	input wire [31:0] divisor_in;
+	output wire valid_out;
+	output wire [31:0] data_out;
+	wire div_clken;
+	wire run_in;
+	wire run_state;
+	wire [5:0] count_in;
+	wire [5:0] count;
+	wire [32:0] m_ff;
+	wire qff_enable;
+	wire aff_enable;
+	wire [32:0] q_in;
+	wire [32:0] q_ff;
+	wire [32:0] a_in;
+	wire [32:0] a_ff;
+	wire [32:0] m_eff;
+	wire [32:0] a_shift;
+	wire dividend_neg_ff;
+	wire divisor_neg_ff;
+	wire [31:0] dividend_comp;
+	wire [31:0] dividend_eff;
+	wire [31:0] q_ff_comp;
+	wire [31:0] q_ff_eff;
+	wire [31:0] a_ff_comp;
+	wire [31:0] a_ff_eff;
+	wire sign_ff;
+	wire sign_eff;
+	wire rem_ff;
+	wire add;
+	wire [32:0] a_eff;
+	wire [64:0] a_eff_shift;
+	wire rem_correct;
+	wire valid_ff_x;
+	wire valid_x;
+	wire finish;
+	wire finish_ff;
+	wire smallnum_case;
+	wire smallnum_case_ff;
+	wire [3:0] smallnum;
+	wire [3:0] smallnum_ff;
+	wire m_already_comp;
+	wire [4:0] a_cls;
+	wire [4:0] b_cls;
+	wire [5:0] shortq_shift;
+	wire [5:0] shortq_shift_ff;
+	wire [5:0] shortq;
+	wire shortq_enable;
+	wire shortq_enable_ff;
+	wire [32:0] short_dividend;
+	wire [3:0] shortq_raw;
+	wire [3:0] shortq_shift_xx;
+	rvdffe #(.WIDTH(23)) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(div_clken),
+		.din({valid_in & ~cancel, finish & ~cancel, run_in, count_in[5:0], (valid_in & dividend_in[31]) | (~valid_in & dividend_neg_ff), (valid_in & divisor_in[31]) | (~valid_in & divisor_neg_ff), (valid_in & sign_eff) | (~valid_in & sign_ff), (valid_in & rem_in) | (~valid_in & rem_ff), smallnum_case, smallnum[3:0], shortq_enable, shortq_shift[3:0]}),
+		.dout({valid_ff_x, finish_ff, run_state, count[5:0], dividend_neg_ff, divisor_neg_ff, sign_ff, rem_ff, smallnum_case_ff, smallnum_ff[3:0], shortq_enable_ff, shortq_shift_xx[3:0]})
+	);
+	rvdffe #(.WIDTH(33)) mff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(valid_in),
+		.din({signed_in & divisor_in[31], divisor_in[31:0]}),
+		.dout(m_ff[32:0])
+	);
+	rvdffe #(.WIDTH(33)) qff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qff_enable),
+		.din(q_in[32:0]),
+		.dout(q_ff[32:0])
+	);
+	rvdffe #(.WIDTH(33)) aff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(aff_enable),
+		.din(a_in[32:0]),
+		.dout(a_ff[32:0])
+	);
+	rvtwoscomp #(.WIDTH(32)) i_dividend_comp(
+		.din(q_ff[31:0]),
+		.dout(dividend_comp[31:0])
+	);
+	rvtwoscomp #(.WIDTH(32)) i_q_ff_comp(
+		.din(q_ff[31:0]),
+		.dout(q_ff_comp[31:0])
+	);
+	rvtwoscomp #(.WIDTH(32)) i_a_ff_comp(
+		.din(a_ff[31:0]),
+		.dout(a_ff_comp[31:0])
+	);
+	assign valid_x = valid_ff_x & ~cancel;
+	assign smallnum_case = (((((q_ff[31:4] == 28'b0000000000000000000000000000) & (m_ff[31:4] == 28'b0000000000000000000000000000)) & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & ~rem_ff) & valid_x) | ((((q_ff[31:0] == 32'b00000000000000000000000000000000) & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & ~rem_ff) & valid_x);
+	assign smallnum[3] = ((q_ff[3] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1];
+	assign smallnum[2] = ((((q_ff[3] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0]) | (((q_ff[2] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[2]) & ~m_ff[3]) & ~m_ff[2]);
+	assign smallnum[1] = ((((((((((q_ff[2] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0]) | (((q_ff[1] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & ~m_ff[3]) & ~m_ff[1]) & ~m_ff[0])) | (((((q_ff[3] & ~q_ff[2]) & ~m_ff[3]) & ~m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & ~m_ff[2])) | (((q_ff[3] & q_ff[2]) & ~m_ff[3]) & ~m_ff[0])) | ((((q_ff[3] & q_ff[2]) & ~m_ff[3]) & m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[1]) & ~m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[2]);
+	assign smallnum[0] = ((((((((((((((((((((((((((((q_ff[2] & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[1]) | (((((q_ff[3] & ~q_ff[2]) & q_ff[0]) & ~m_ff[3]) & m_ff[1]) & m_ff[0])) | (((q_ff[2] & ~m_ff[3]) & ~m_ff[1]) & ~m_ff[0])) | (((q_ff[1] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0])) | (((q_ff[0] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | ((((((~q_ff[3] & q_ff[2]) & ~q_ff[1]) & ~m_ff[3]) & ~m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & ~m_ff[0])) | (((q_ff[3] & ~m_ff[2]) & ~m_ff[1]) & ~m_ff[0])) | ((((q_ff[3] & ~q_ff[2]) & ~m_ff[3]) & m_ff[2]) & m_ff[1])) | (((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[2]) & ~m_ff[1])) | ((((~q_ff[3] & q_ff[2]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[1])) | (((((q_ff[3] & ~q_ff[2]) & ~q_ff[1]) & ~m_ff[3]) & m_ff[2]) & m_ff[0])) | ((((~q_ff[2] & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[2])) | (((q_ff[3] & q_ff[2]) & ~m_ff[1]) & ~m_ff[0])) | (((q_ff[3] & q_ff[1]) & ~m_ff[2]) & ~m_ff[0])) | (((((~q_ff[3] & q_ff[2]) & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & m_ff[2])) | (((q_ff[3] & q_ff[2]) & m_ff[3]) & ~m_ff[2])) | ((((q_ff[3] & q_ff[1]) & m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[0]) & ~m_ff[2]) & ~m_ff[1])) | (((((q_ff[3] & ~q_ff[1]) & ~m_ff[3]) & m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & m_ff[3]) & ~m_ff[0])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & q_ff[2]) & q_ff[0]) & m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & ~q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[1])) | (((q_ff[3] & q_ff[1]) & q_ff[0]) & ~m_ff[2])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & q_ff[0]) & m_ff[3]);
+	assign short_dividend[31:0] = q_ff[31:0];
+	assign short_dividend[32] = sign_ff & q_ff[31];
+	assign a_cls[4:3] = 2'b00;
+	assign a_cls[2] = (~short_dividend[32] & (short_dividend[31:24] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[31:23] != {9 {1'b1}}));
+	assign a_cls[1] = (~short_dividend[32] & (short_dividend[23:16] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[22:15] != {8 {1'b1}}));
+	assign a_cls[0] = (~short_dividend[32] & (short_dividend[15:8] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[14:7] != {8 {1'b1}}));
+	assign b_cls[4:3] = 2'b00;
+	assign b_cls[2] = (~m_ff[32] & (m_ff[31:24] != {8 {1'b0}})) | (m_ff[32] & (m_ff[31:24] != {8 {1'b1}}));
+	assign b_cls[1] = (~m_ff[32] & (m_ff[23:16] != {8 {1'b0}})) | (m_ff[32] & (m_ff[23:16] != {8 {1'b1}}));
+	assign b_cls[0] = (~m_ff[32] & (m_ff[15:8] != {8 {1'b0}})) | (m_ff[32] & (m_ff[15:8] != {8 {1'b1}}));
+	assign shortq_raw[3] = ((((((a_cls[2:1] == 2'b01) & (b_cls[2] == 1'b1)) | ((a_cls[2:0] == 3'b001) & (b_cls[2] == 1'b1))) | ((a_cls[2:0] == 3'b000) & (b_cls[2] == 1'b1))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b001));
+	assign shortq_raw[2] = ((((a_cls[2] == 1'b1) & (b_cls[2] == 1'b1)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b001))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b000));
+	assign shortq_raw[1] = (((a_cls[2] == 1'b1) & (b_cls[2:1] == 2'b01)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:0] == 3'b001))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b000));
+	assign shortq_raw[0] = ((a_cls[2] == 1'b1) & (b_cls[2:0] == 3'b001)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:0] == 3'b000));
+	assign shortq_enable = (valid_ff_x & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & (shortq_raw[3:0] != 4'b0000);
+	assign shortq_shift[3:0] = {4 {shortq_enable}} & shortq_raw[3:0];
+	assign shortq[5:0] = 6'b000000;
+	assign shortq_shift[5:4] = 2'b00;
+	assign shortq_shift_ff[5] = 1'b0;
+	assign shortq_shift_ff[4:0] = ((({5 {shortq_shift_xx[3]}} & 5'b11111) | ({5 {shortq_shift_xx[2]}} & 5'b11000)) | ({5 {shortq_shift_xx[1]}} & 5'b10000)) | ({5 {shortq_shift_xx[0]}} & 5'b01000);
+	assign div_clken = ((valid_in | run_state) | finish) | finish_ff;
+	assign run_in = ((valid_in | run_state) & ~finish) & ~cancel;
+	assign count_in[5:0] = {6 {((run_state & ~finish) & ~cancel) & ~shortq_enable}} & ((count[5:0] + {1'b0, shortq_shift_ff[4:0]}) + 6'd1);
+	assign finish = smallnum_case | (~rem_ff ? count[5:0] == 6'd32 : count[5:0] == 6'd33);
+	assign valid_out = finish_ff & ~cancel;
+	assign sign_eff = signed_in & (divisor_in[31:0] != 32'b00000000000000000000000000000000);
+	assign q_in[32:0] = (({33 {~run_state}} & {1'b0, dividend_in[31:0]}) | ({33 {run_state & (valid_ff_x | shortq_enable_ff)}} & ({dividend_eff[31:0], ~a_in[32]} << shortq_shift_ff[4:0]))) | ({33 {run_state & ~(valid_ff_x | shortq_enable_ff)}} & {q_ff[31:0], ~a_in[32]});
+	assign qff_enable = valid_in | (run_state & ~shortq_enable);
+	assign dividend_eff[31:0] = (sign_ff & dividend_neg_ff ? dividend_comp[31:0] : q_ff[31:0]);
+	assign m_eff[32:0] = (add ? m_ff[32:0] : ~m_ff[32:0]);
+	assign a_eff_shift[64:0] = {33'b000000000000000000000000000000000, dividend_eff[31:0]} << shortq_shift_ff[4:0];
+	assign a_eff[32:0] = (({33 {rem_correct}} & a_ff[32:0]) | ({33 {~rem_correct & ~shortq_enable_ff}} & {a_ff[31:0], q_ff[32]})) | ({33 {~rem_correct & shortq_enable_ff}} & a_eff_shift[64:32]);
+	assign a_shift[32:0] = {33 {run_state}} & a_eff[32:0];
+	assign a_in[32:0] = {33 {run_state}} & ((a_shift[32:0] + m_eff[32:0]) + {32'b00000000000000000000000000000000, ~add});
+	assign aff_enable = (valid_in | ((run_state & ~shortq_enable) & (count[5:0] != 6'd33))) | rem_correct;
+	assign m_already_comp = divisor_neg_ff & sign_ff;
+	assign add = (a_ff[32] | rem_correct) ^ m_already_comp;
+	assign rem_correct = ((count[5:0] == 6'd33) & rem_ff) & a_ff[32];
+	assign q_ff_eff[31:0] = (sign_ff & (dividend_neg_ff ^ divisor_neg_ff) ? q_ff_comp[31:0] : q_ff[31:0]);
+	assign a_ff_eff[31:0] = (sign_ff & dividend_neg_ff ? a_ff_comp[31:0] : a_ff[31:0]);
+	assign data_out[31:0] = (({32 {smallnum_case_ff}} & {28'b0000000000000000000000000000, smallnum_ff[3:0]}) | ({32 {rem_ff}} & a_ff_eff[31:0])) | ({32 {~smallnum_case_ff & ~rem_ff}} & q_ff_eff[31:0]);
+endmodule
+module eb1_exu_div_new_1bit_fullshortq (
+	clk,
+	rst_l,
+	scan_mode,
+	cancel,
+	valid_in,
+	signed_in,
+	rem_in,
+	dividend_in,
+	divisor_in,
+	valid_out,
+	data_out
+);
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire cancel;
+	input wire valid_in;
+	input wire signed_in;
+	input wire rem_in;
+	input wire [31:0] dividend_in;
+	input wire [31:0] divisor_in;
+	output wire valid_out;
+	output wire [31:0] data_out;
+	wire valid_ff_in;
+	wire valid_ff;
+	wire finish_raw;
+	wire finish;
+	wire finish_ff;
+	wire running_state;
+	wire misc_enable;
+	wire [2:0] control_in;
+	wire [2:0] control_ff;
+	wire dividend_sign_ff;
+	wire divisor_sign_ff;
+	wire rem_ff;
+	wire count_enable;
+	wire [6:0] count_in;
+	wire [6:0] count_ff;
+	wire smallnum_case;
+	wire [3:0] smallnum;
+	wire a_enable;
+	wire a_shift;
+	wire [31:0] a_in;
+	wire [31:0] a_ff;
+	wire b_enable;
+	wire b_twos_comp;
+	wire [32:0] b_in;
+	wire [32:0] b_ff;
+	wire [31:0] q_in;
+	wire [31:0] q_ff;
+	wire rq_enable;
+	wire r_sign_sel;
+	wire r_restore_sel;
+	wire r_adder_sel;
+	wire [31:0] r_in;
+	wire [31:0] r_ff;
+	wire twos_comp_q_sel;
+	wire twos_comp_b_sel;
+	wire [31:0] twos_comp_in;
+	wire [31:0] twos_comp_out;
+	wire quotient_set;
+	wire [32:0] adder_out;
+	wire [63:0] ar_shifted;
+	wire [5:0] shortq;
+	wire [4:0] shortq_shift;
+	wire [4:0] shortq_shift_ff;
+	wire shortq_enable;
+	wire shortq_enable_ff;
+	wire [32:0] shortq_dividend;
+	wire by_zero_case;
+	wire by_zero_case_ff;
+	rvdffe #(.WIDTH(19)) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(misc_enable),
+		.din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),
+		.dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]})
+	);
+	rvdffe #(.WIDTH(32)) i_a_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(a_enable),
+		.din(a_in[31:0]),
+		.dout(a_ff[31:0])
+	);
+	rvdffe #(.WIDTH(33)) i_b_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(b_enable),
+		.din(b_in[32:0]),
+		.dout(b_ff[32:0])
+	);
+	rvdffe #(.WIDTH(32)) i_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(r_in[31:0]),
+		.dout(r_ff[31:0])
+	);
+	rvdffe #(.WIDTH(32)) i_q_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(q_in[31:0]),
+		.dout(q_ff[31:0])
+	);
+	assign valid_ff_in = valid_in & ~cancel;
+	assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]);
+	assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]);
+	assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);
+	assign dividend_sign_ff = control_ff[2];
+	assign divisor_sign_ff = control_ff[1];
+	assign rem_ff = control_ff[0];
+	assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000);
+	assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff;
+	assign running_state = |count_ff[6:0] | shortq_enable_ff;
+	assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32);
+	assign finish = finish_raw & ~cancel;
+	assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable;
+	assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000001) + {2'b00, shortq_shift_ff[4:0]});
+	assign a_enable = valid_in | running_state;
+	assign a_shift = running_state & ~shortq_enable_ff;
+	assign ar_shifted[63:0] = {{32 {dividend_sign_ff}}, a_ff[31:0]} << shortq_shift_ff[4:0];
+	assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[30:0], 1'b0})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]);
+	assign b_enable = valid_in | b_twos_comp;
+	assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]});
+	assign rq_enable = (valid_in | valid_ff) | running_state;
+	assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case;
+	assign r_restore_sel = (running_state & ~quotient_set) & ~shortq_enable_ff;
+	assign r_adder_sel = (running_state & quotient_set) & ~shortq_enable_ff;
+	assign r_in[31:0] = (((({32 {r_sign_sel}} & 32'hffffffff) | ({32 {r_restore_sel}} & {r_ff[30:0], a_ff[31]})) | ({32 {r_adder_sel}} & adder_out[31:0])) | ({32 {shortq_enable_ff}} & ar_shifted[63:32])) | ({32 {by_zero_case}} & a_ff[31:0]);
+	assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[30:0], quotient_set}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}});
+	assign adder_out[32:0] = {r_ff[31:0], a_ff[31]} + {b_ff[32:0]};
+	assign quotient_set = (~adder_out[32] ^ dividend_sign_ff) | ((a_ff[30:0] == 31'b0000000000000000000000000000000) & (adder_out[32:0] == 33'b000000000000000000000000000000000));
+	assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff;
+	assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]);
+	rvtwoscomp #(.WIDTH(32)) i_twos_comp(
+		.din(twos_comp_in[31:0]),
+		.dout(twos_comp_out[31:0])
+	);
+	assign valid_out = finish_ff & ~cancel;
+	assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]);
+	assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel);
+	assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1];
+	assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]);
+	assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]);
+	assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]);
+	assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]};
+	wire [5:0] dw_a_enc;
+	wire [5:0] dw_b_enc;
+	wire [6:0] dw_shortq_raw;
+	eb1_exu_div_cls i_a_cls(
+		.operand(shortq_dividend[32:0]),
+		.cls(dw_a_enc[4:0])
+	);
+	eb1_exu_div_cls i_b_cls(
+		.operand(b_ff[32:0]),
+		.cls(dw_b_enc[4:0])
+	);
+	assign dw_a_enc[5] = 1'b0;
+	assign dw_b_enc[5] = 1'b0;
+	assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1;
+	assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]);
+	assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:1] == 4'b1111)) & ~cancel;
+	assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : 5'b11111 - shortq[4:0]);
+endmodule
+module eb1_exu_div_new_2bit_fullshortq (
+	clk,
+	rst_l,
+	scan_mode,
+	cancel,
+	valid_in,
+	signed_in,
+	rem_in,
+	dividend_in,
+	divisor_in,
+	valid_out,
+	data_out
+);
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire cancel;
+	input wire valid_in;
+	input wire signed_in;
+	input wire rem_in;
+	input wire [31:0] dividend_in;
+	input wire [31:0] divisor_in;
+	output wire valid_out;
+	output wire [31:0] data_out;
+	wire valid_ff_in;
+	wire valid_ff;
+	wire finish_raw;
+	wire finish;
+	wire finish_ff;
+	wire running_state;
+	wire misc_enable;
+	wire [2:0] control_in;
+	wire [2:0] control_ff;
+	wire dividend_sign_ff;
+	wire divisor_sign_ff;
+	wire rem_ff;
+	wire count_enable;
+	wire [6:0] count_in;
+	wire [6:0] count_ff;
+	wire smallnum_case;
+	wire [3:0] smallnum;
+	wire a_enable;
+	wire a_shift;
+	wire [31:0] a_in;
+	wire [31:0] a_ff;
+	wire b_enable;
+	wire b_twos_comp;
+	wire [32:0] b_in;
+	wire [34:0] b_ff;
+	wire [31:0] q_in;
+	wire [31:0] q_ff;
+	wire rq_enable;
+	wire r_sign_sel;
+	wire r_restore_sel;
+	wire r_adder1_sel;
+	wire r_adder2_sel;
+	wire r_adder3_sel;
+	wire [31:0] r_in;
+	wire [31:0] r_ff;
+	wire twos_comp_q_sel;
+	wire twos_comp_b_sel;
+	wire [31:0] twos_comp_in;
+	wire [31:0] twos_comp_out;
+	wire [3:1] quotient_raw;
+	wire [1:0] quotient_new;
+	wire [32:0] adder1_out;
+	wire [33:0] adder2_out;
+	wire [34:0] adder3_out;
+	wire [63:0] ar_shifted;
+	wire [5:0] shortq;
+	wire [4:0] shortq_shift;
+	wire [4:1] shortq_shift_ff;
+	wire shortq_enable;
+	wire shortq_enable_ff;
+	wire [32:0] shortq_dividend;
+	wire by_zero_case;
+	wire by_zero_case_ff;
+	rvdffe #(.WIDTH(18)) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(misc_enable),
+		.din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:1], finish, count_in[6:0]}),
+		.dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:1], finish_ff, count_ff[6:0]})
+	);
+	rvdffe #(.WIDTH(32)) i_a_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(a_enable),
+		.din(a_in[31:0]),
+		.dout(a_ff[31:0])
+	);
+	rvdffe #(.WIDTH(33)) i_b_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(b_enable),
+		.din(b_in[32:0]),
+		.dout(b_ff[32:0])
+	);
+	rvdffe #(.WIDTH(32)) i_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(r_in[31:0]),
+		.dout(r_ff[31:0])
+	);
+	rvdffe #(.WIDTH(32)) i_q_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(q_in[31:0]),
+		.dout(q_ff[31:0])
+	);
+	assign valid_ff_in = valid_in & ~cancel;
+	assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]);
+	assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]);
+	assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);
+	assign dividend_sign_ff = control_ff[2];
+	assign divisor_sign_ff = control_ff[1];
+	assign rem_ff = control_ff[0];
+	assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000);
+	assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff;
+	assign running_state = |count_ff[6:0] | shortq_enable_ff;
+	assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32);
+	assign finish = finish_raw & ~cancel;
+	assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable;
+	assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000010) + {2'b00, shortq_shift_ff[4:1], 1'b0});
+	assign a_enable = valid_in | running_state;
+	assign a_shift = running_state & ~shortq_enable_ff;
+	assign ar_shifted[63:0] = {{32 {dividend_sign_ff}}, a_ff[31:0]} << {shortq_shift_ff[4:1], 1'b0};
+	assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[29:0], 2'b00})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]);
+	assign b_enable = valid_in | b_twos_comp;
+	assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]});
+	assign rq_enable = (valid_in | valid_ff) | running_state;
+	assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case;
+	assign r_restore_sel = (running_state & (quotient_new[1:0] == 2'b00)) & ~shortq_enable_ff;
+	assign r_adder1_sel = (running_state & (quotient_new[1:0] == 2'b01)) & ~shortq_enable_ff;
+	assign r_adder2_sel = (running_state & (quotient_new[1:0] == 2'b10)) & ~shortq_enable_ff;
+	assign r_adder3_sel = (running_state & (quotient_new[1:0] == 2'b11)) & ~shortq_enable_ff;
+	assign r_in[31:0] = (((((({32 {r_sign_sel}} & 32'hffffffff) | ({32 {r_restore_sel}} & {r_ff[29:0], a_ff[31:30]})) | ({32 {r_adder1_sel}} & adder1_out[31:0])) | ({32 {r_adder2_sel}} & adder2_out[31:0])) | ({32 {r_adder3_sel}} & adder3_out[31:0])) | ({32 {shortq_enable_ff}} & ar_shifted[63:32])) | ({32 {by_zero_case}} & a_ff[31:0]);
+	assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[29:0], quotient_new[1:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}});
+	assign b_ff[34:33] = {b_ff[32], b_ff[32]};
+	assign adder1_out[32:0] = {r_ff[30:0], a_ff[31:30]} + b_ff[32:0];
+	assign adder2_out[33:0] = {r_ff[31:0], a_ff[31:30]} + {b_ff[32:0], 1'b0};
+	assign adder3_out[34:0] = ({r_ff[31], r_ff[31:0], a_ff[31:30]} + {b_ff[33:0], 1'b0}) + b_ff[34:0];
+	assign quotient_raw[1] = (~adder1_out[32] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder1_out[32:0] == 33'b000000000000000000000000000000000));
+	assign quotient_raw[2] = (~adder2_out[33] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder2_out[33:0] == 34'b0000000000000000000000000000000000));
+	assign quotient_raw[3] = (~adder3_out[34] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder3_out[34:0] == 35'b00000000000000000000000000000000000));
+	assign quotient_new[1] = quotient_raw[3] | quotient_raw[2];
+	assign quotient_new[0] = quotient_raw[3] | (~quotient_raw[2] & quotient_raw[1]);
+	assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff;
+	assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]);
+	rvtwoscomp #(.WIDTH(32)) i_twos_comp(
+		.din(twos_comp_in[31:0]),
+		.dout(twos_comp_out[31:0])
+	);
+	assign valid_out = finish_ff & ~cancel;
+	assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]);
+	assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel);
+	assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1];
+	assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]);
+	assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]);
+	assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]);
+	assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]};
+	wire [5:0] dw_a_enc;
+	wire [5:0] dw_b_enc;
+	wire [6:0] dw_shortq_raw;
+	eb1_exu_div_cls i_a_cls(
+		.operand(shortq_dividend[32:0]),
+		.cls(dw_a_enc[4:0])
+	);
+	eb1_exu_div_cls i_b_cls(
+		.operand(b_ff[32:0]),
+		.cls(dw_b_enc[4:0])
+	);
+	assign dw_a_enc[5] = 1'b0;
+	assign dw_b_enc[5] = 1'b0;
+	assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1;
+	assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]);
+	assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:1] == 4'b1111)) & ~cancel;
+	assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : 5'b11111 - shortq[4:0]);
+endmodule
+module eb1_exu_div_new_3bit_fullshortq (
+	clk,
+	rst_l,
+	scan_mode,
+	cancel,
+	valid_in,
+	signed_in,
+	rem_in,
+	dividend_in,
+	divisor_in,
+	valid_out,
+	data_out
+);
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire cancel;
+	input wire valid_in;
+	input wire signed_in;
+	input wire rem_in;
+	input wire [31:0] dividend_in;
+	input wire [31:0] divisor_in;
+	output wire valid_out;
+	output wire [31:0] data_out;
+	wire valid_ff_in;
+	wire valid_ff;
+	wire finish_raw;
+	wire finish;
+	wire finish_ff;
+	wire running_state;
+	wire misc_enable;
+	wire [2:0] control_in;
+	wire [2:0] control_ff;
+	wire dividend_sign_ff;
+	wire divisor_sign_ff;
+	wire rem_ff;
+	wire count_enable;
+	wire [6:0] count_in;
+	wire [6:0] count_ff;
+	wire smallnum_case;
+	wire [3:0] smallnum;
+	wire a_enable;
+	wire a_shift;
+	wire [32:0] a_in;
+	wire [32:0] a_ff;
+	wire b_enable;
+	wire b_twos_comp;
+	wire [32:0] b_in;
+	wire [36:0] b_ff;
+	wire [31:0] q_in;
+	wire [31:0] q_ff;
+	wire rq_enable;
+	wire r_sign_sel;
+	wire r_restore_sel;
+	wire r_adder1_sel;
+	wire r_adder2_sel;
+	wire r_adder3_sel;
+	wire r_adder4_sel;
+	wire r_adder5_sel;
+	wire r_adder6_sel;
+	wire r_adder7_sel;
+	wire [32:0] r_in;
+	wire [32:0] r_ff;
+	wire twos_comp_q_sel;
+	wire twos_comp_b_sel;
+	wire [31:0] twos_comp_in;
+	wire [31:0] twos_comp_out;
+	wire [7:1] quotient_raw;
+	wire [2:0] quotient_new;
+	wire [33:0] adder1_out;
+	wire [34:0] adder2_out;
+	wire [35:0] adder3_out;
+	wire [36:0] adder4_out;
+	wire [36:0] adder5_out;
+	wire [36:0] adder6_out;
+	wire [36:0] adder7_out;
+	wire [65:0] ar_shifted;
+	wire [5:0] shortq;
+	wire [4:0] shortq_shift;
+	wire [4:0] shortq_decode;
+	wire [4:0] shortq_shift_ff;
+	wire shortq_enable;
+	wire shortq_enable_ff;
+	wire [32:0] shortq_dividend;
+	wire by_zero_case;
+	wire by_zero_case_ff;
+	rvdffe #(.WIDTH(19)) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(misc_enable),
+		.din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),
+		.dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]})
+	);
+	rvdffe #(.WIDTH(33)) i_a_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(a_enable),
+		.din(a_in[32:0]),
+		.dout(a_ff[32:0])
+	);
+	rvdffe #(.WIDTH(33)) i_b_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(b_enable),
+		.din(b_in[32:0]),
+		.dout(b_ff[32:0])
+	);
+	rvdffe #(.WIDTH(33)) i_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(r_in[32:0]),
+		.dout(r_ff[32:0])
+	);
+	rvdffe #(.WIDTH(32)) i_q_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(q_in[31:0]),
+		.dout(q_ff[31:0])
+	);
+	assign valid_ff_in = valid_in & ~cancel;
+	assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]);
+	assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]);
+	assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);
+	assign dividend_sign_ff = control_ff[2];
+	assign divisor_sign_ff = control_ff[1];
+	assign rem_ff = control_ff[0];
+	assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000);
+	assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff;
+	assign running_state = |count_ff[6:0] | shortq_enable_ff;
+	assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd33);
+	assign finish = finish_raw & ~cancel;
+	assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable;
+	assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000011) + {2'b00, shortq_shift_ff[4:0]});
+	assign a_enable = valid_in | running_state;
+	assign a_shift = running_state & ~shortq_enable_ff;
+	assign ar_shifted[65:0] = {{33 {dividend_sign_ff}}, a_ff[32:0]} << {shortq_shift_ff[4:0]};
+	assign a_in[32:0] = (({33 {~a_shift & ~shortq_enable_ff}} & {signed_in & dividend_in[31], dividend_in[31:0]}) | ({33 {a_shift}} & {a_ff[29:0], 3'b000})) | ({33 {shortq_enable_ff}} & ar_shifted[32:0]);
+	assign b_enable = valid_in | b_twos_comp;
+	assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]});
+	assign rq_enable = (valid_in | valid_ff) | running_state;
+	assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case;
+	assign r_restore_sel = (running_state & (quotient_new[2:0] == 3'b000)) & ~shortq_enable_ff;
+	assign r_adder1_sel = (running_state & (quotient_new[2:0] == 3'b001)) & ~shortq_enable_ff;
+	assign r_adder2_sel = (running_state & (quotient_new[2:0] == 3'b010)) & ~shortq_enable_ff;
+	assign r_adder3_sel = (running_state & (quotient_new[2:0] == 3'b011)) & ~shortq_enable_ff;
+	assign r_adder4_sel = (running_state & (quotient_new[2:0] == 3'b100)) & ~shortq_enable_ff;
+	assign r_adder5_sel = (running_state & (quotient_new[2:0] == 3'b101)) & ~shortq_enable_ff;
+	assign r_adder6_sel = (running_state & (quotient_new[2:0] == 3'b110)) & ~shortq_enable_ff;
+	assign r_adder7_sel = (running_state & (quotient_new[2:0] == 3'b111)) & ~shortq_enable_ff;
+	assign r_in[32:0] = (((((((((({33 {r_sign_sel}} & {33 {1'b1}}) | ({33 {r_restore_sel}} & {r_ff[29:0], a_ff[32:30]})) | ({33 {r_adder1_sel}} & adder1_out[32:0])) | ({33 {r_adder2_sel}} & adder2_out[32:0])) | ({33 {r_adder3_sel}} & adder3_out[32:0])) | ({33 {r_adder4_sel}} & adder4_out[32:0])) | ({33 {r_adder5_sel}} & adder5_out[32:0])) | ({33 {r_adder6_sel}} & adder6_out[32:0])) | ({33 {r_adder7_sel}} & adder7_out[32:0])) | ({33 {shortq_enable_ff}} & ar_shifted[65:33])) | ({33 {by_zero_case}} & {1'b0, a_ff[31:0]});
+	assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[28:0], quotient_new[2:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}});
+	assign b_ff[36:33] = {b_ff[32], b_ff[32], b_ff[32], b_ff[32]};
+	assign adder1_out[33:0] = {r_ff[30:0], a_ff[32:30]} + b_ff[33:0];
+	assign adder2_out[34:0] = {r_ff[31:0], a_ff[32:30]} + {b_ff[33:0], 1'b0};
+	assign adder3_out[35:0] = ({r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 1'b0}) + b_ff[35:0];
+	assign adder4_out[36:0] = {r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00};
+	assign adder5_out[36:0] = ({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + b_ff[36:0];
+	assign adder6_out[36:0] = ({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + {b_ff[35:0], 1'b0};
+	assign adder7_out[36:0] = (({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + {b_ff[35:0], 1'b0}) + b_ff[36:0];
+	assign quotient_raw[1] = (~adder1_out[33] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder1_out[33:0] == 34'b0000000000000000000000000000000000));
+	assign quotient_raw[2] = (~adder2_out[34] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder2_out[34:0] == 35'b00000000000000000000000000000000000));
+	assign quotient_raw[3] = (~adder3_out[35] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder3_out[35:0] == 36'b000000000000000000000000000000000000));
+	assign quotient_raw[4] = (~adder4_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder4_out[36:0] == 37'b0000000000000000000000000000000000000));
+	assign quotient_raw[5] = (~adder5_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder5_out[36:0] == 37'b0000000000000000000000000000000000000));
+	assign quotient_raw[6] = (~adder6_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder6_out[36:0] == 37'b0000000000000000000000000000000000000));
+	assign quotient_raw[7] = (~adder7_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder7_out[36:0] == 37'b0000000000000000000000000000000000000));
+	assign quotient_new[2] = ((quotient_raw[7] | quotient_raw[6]) | quotient_raw[5]) | quotient_raw[4];
+	assign quotient_new[1] = ((quotient_raw[7] | quotient_raw[6]) | (~quotient_raw[4] & quotient_raw[3])) | (~quotient_raw[3] & quotient_raw[2]);
+	assign quotient_new[0] = ((quotient_raw[7] | (~quotient_raw[6] & quotient_raw[5])) | (~quotient_raw[4] & quotient_raw[3])) | (~quotient_raw[2] & quotient_raw[1]);
+	assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff;
+	assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]);
+	rvtwoscomp #(.WIDTH(32)) i_twos_comp(
+		.din(twos_comp_in[31:0]),
+		.dout(twos_comp_out[31:0])
+	);
+	assign valid_out = finish_ff & ~cancel;
+	assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]);
+	assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel);
+	assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1];
+	assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]);
+	assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]);
+	assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]);
+	assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]};
+	wire [5:0] dw_a_enc;
+	wire [5:0] dw_b_enc;
+	wire [6:0] dw_shortq_raw;
+	eb1_exu_div_cls i_a_cls(
+		.operand(shortq_dividend[32:0]),
+		.cls(dw_a_enc[4:0])
+	);
+	eb1_exu_div_cls i_b_cls(
+		.operand(b_ff[32:0]),
+		.cls(dw_b_enc[4:0])
+	);
+	assign dw_a_enc[5] = 1'b0;
+	assign dw_b_enc[5] = 1'b0;
+	assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1;
+	assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]);
+	assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:2] == 3'b111)) & ~cancel;
+	assign shortq_decode[4:0] = ((((((((((((((((((((((((((((((({5 {shortq[4:0] == 5'd31}} & 5'd0) | ({5 {shortq[4:0] == 5'd30}} & 5'd0)) | ({5 {shortq[4:0] == 5'd29}} & 5'd0)) | ({5 {shortq[4:0] == 5'd28}} & 5'd0)) | ({5 {shortq[4:0] == 5'd27}} & 5'd3)) | ({5 {shortq[4:0] == 5'd26}} & 5'd6)) | ({5 {shortq[4:0] == 5'd25}} & 5'd6)) | ({5 {shortq[4:0] == 5'd24}} & 5'd6)) | ({5 {shortq[4:0] == 5'd23}} & 5'd9)) | ({5 {shortq[4:0] == 5'd22}} & 5'd9)) | ({5 {shortq[4:0] == 5'd21}} & 5'd9)) | ({5 {shortq[4:0] == 5'd20}} & 5'd12)) | ({5 {shortq[4:0] == 5'd19}} & 5'd12)) | ({5 {shortq[4:0] == 5'd18}} & 5'd12)) | ({5 {shortq[4:0] == 5'd17}} & 5'd15)) | ({5 {shortq[4:0] == 5'd16}} & 5'd15)) | ({5 {shortq[4:0] == 5'd15}} & 5'd15)) | ({5 {shortq[4:0] == 5'd14}} & 5'd18)) | ({5 {shortq[4:0] == 5'd13}} & 5'd18)) | ({5 {shortq[4:0] == 5'd12}} & 5'd18)) | ({5 {shortq[4:0] == 5'd11}} & 5'd21)) | ({5 {shortq[4:0] == 5'd10}} & 5'd21)) | ({5 {shortq[4:0] == 5'd9}} & 5'd21)) | ({5 {shortq[4:0] == 5'd8}} & 5'd24)) | ({5 {shortq[4:0] == 5'd7}} & 5'd24)) | ({5 {shortq[4:0] == 5'd6}} & 5'd24)) | ({5 {shortq[4:0] == 5'd5}} & 5'd27)) | ({5 {shortq[4:0] == 5'd4}} & 5'd27)) | ({5 {shortq[4:0] == 5'd3}} & 5'd27)) | ({5 {shortq[4:0] == 5'd2}} & 5'd27)) | ({5 {shortq[4:0] == 5'd1}} & 5'd27)) | ({5 {shortq[4:0] == 5'd0}} & 5'd27);
+	assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : shortq_decode[4:0]);
+endmodule
+module eb1_exu_div_new_4bit_fullshortq (
+	clk,
+	rst_l,
+	scan_mode,
+	cancel,
+	valid_in,
+	signed_in,
+	rem_in,
+	dividend_in,
+	divisor_in,
+	valid_out,
+	data_out
+);
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire cancel;
+	input wire valid_in;
+	input wire signed_in;
+	input wire rem_in;
+	input wire [31:0] dividend_in;
+	input wire [31:0] divisor_in;
+	output wire valid_out;
+	output wire [31:0] data_out;
+	wire valid_ff_in;
+	wire valid_ff;
+	wire finish_raw;
+	wire finish;
+	wire finish_ff;
+	wire running_state;
+	wire misc_enable;
+	wire [2:0] control_in;
+	wire [2:0] control_ff;
+	wire dividend_sign_ff;
+	wire divisor_sign_ff;
+	wire rem_ff;
+	wire count_enable;
+	wire [6:0] count_in;
+	wire [6:0] count_ff;
+	wire smallnum_case;
+	wire [3:0] smallnum;
+	wire a_enable;
+	wire a_shift;
+	wire [31:0] a_in;
+	wire [31:0] a_ff;
+	wire b_enable;
+	wire b_twos_comp;
+	wire [32:0] b_in;
+	wire [37:0] b_ff;
+	wire [31:0] q_in;
+	wire [31:0] q_ff;
+	wire rq_enable;
+	wire r_sign_sel;
+	wire r_restore_sel;
+	wire r_adder01_sel;
+	wire r_adder02_sel;
+	wire r_adder03_sel;
+	wire r_adder04_sel;
+	wire r_adder05_sel;
+	wire r_adder06_sel;
+	wire r_adder07_sel;
+	wire r_adder08_sel;
+	wire r_adder09_sel;
+	wire r_adder10_sel;
+	wire r_adder11_sel;
+	wire r_adder12_sel;
+	wire r_adder13_sel;
+	wire r_adder14_sel;
+	wire r_adder15_sel;
+	wire [32:0] r_in;
+	wire [32:0] r_ff;
+	wire twos_comp_q_sel;
+	wire twos_comp_b_sel;
+	wire [31:0] twos_comp_in;
+	wire [31:0] twos_comp_out;
+	wire [15:1] quotient_raw;
+	wire [3:0] quotient_new;
+	wire [34:0] adder01_out;
+	wire [35:0] adder02_out;
+	wire [36:0] adder03_out;
+	wire [37:0] adder04_out;
+	wire [37:0] adder05_out;
+	wire [37:0] adder06_out;
+	wire [37:0] adder07_out;
+	wire [37:0] adder08_out;
+	wire [37:0] adder09_out;
+	wire [37:0] adder10_out;
+	wire [37:0] adder11_out;
+	wire [37:0] adder12_out;
+	wire [37:0] adder13_out;
+	wire [37:0] adder14_out;
+	wire [37:0] adder15_out;
+	wire [64:0] ar_shifted;
+	wire [5:0] shortq;
+	wire [4:0] shortq_shift;
+	wire [4:0] shortq_decode;
+	wire [4:0] shortq_shift_ff;
+	wire shortq_enable;
+	wire shortq_enable_ff;
+	wire [32:0] shortq_dividend;
+	wire by_zero_case;
+	wire by_zero_case_ff;
+	rvdffe #(.WIDTH(19)) i_misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(misc_enable),
+		.din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),
+		.dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]})
+	);
+	rvdffe #(.WIDTH(32)) i_a_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(a_enable),
+		.din(a_in[31:0]),
+		.dout(a_ff[31:0])
+	);
+	rvdffe #(.WIDTH(33)) i_b_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(b_enable),
+		.din(b_in[32:0]),
+		.dout(b_ff[32:0])
+	);
+	rvdffe #(.WIDTH(33)) i_r_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(r_in[32:0]),
+		.dout(r_ff[32:0])
+	);
+	rvdffe #(.WIDTH(32)) i_q_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(rq_enable),
+		.din(q_in[31:0]),
+		.dout(q_ff[31:0])
+	);
+	assign valid_ff_in = valid_in & ~cancel;
+	assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]);
+	assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]);
+	assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);
+	assign dividend_sign_ff = control_ff[2];
+	assign divisor_sign_ff = control_ff[1];
+	assign rem_ff = control_ff[0];
+	assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000);
+	assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff;
+	assign running_state = |count_ff[6:0] | shortq_enable_ff;
+	assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32);
+	assign finish = finish_raw & ~cancel;
+	assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable;
+	assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'd4) + {2'b00, shortq_shift_ff[4:0]});
+	assign a_enable = valid_in | running_state;
+	assign a_shift = running_state & ~shortq_enable_ff;
+	assign ar_shifted[64:0] = {{33 {dividend_sign_ff}}, a_ff[31:0]} << {shortq_shift_ff[4:0]};
+	assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[27:0], 4'b0000})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]);
+	assign b_enable = valid_in | b_twos_comp;
+	assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]});
+	assign rq_enable = (valid_in | valid_ff) | running_state;
+	assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case;
+	assign r_restore_sel = (running_state & (quotient_new[3:0] == 4'd0)) & ~shortq_enable_ff;
+	assign r_adder01_sel = (running_state & (quotient_new[3:0] == 4'd1)) & ~shortq_enable_ff;
+	assign r_adder02_sel = (running_state & (quotient_new[3:0] == 4'd2)) & ~shortq_enable_ff;
+	assign r_adder03_sel = (running_state & (quotient_new[3:0] == 4'd3)) & ~shortq_enable_ff;
+	assign r_adder04_sel = (running_state & (quotient_new[3:0] == 4'd4)) & ~shortq_enable_ff;
+	assign r_adder05_sel = (running_state & (quotient_new[3:0] == 4'd5)) & ~shortq_enable_ff;
+	assign r_adder06_sel = (running_state & (quotient_new[3:0] == 4'd6)) & ~shortq_enable_ff;
+	assign r_adder07_sel = (running_state & (quotient_new[3:0] == 4'd7)) & ~shortq_enable_ff;
+	assign r_adder08_sel = (running_state & (quotient_new[3:0] == 4'd8)) & ~shortq_enable_ff;
+	assign r_adder09_sel = (running_state & (quotient_new[3:0] == 4'd9)) & ~shortq_enable_ff;
+	assign r_adder10_sel = (running_state & (quotient_new[3:0] == 4'd10)) & ~shortq_enable_ff;
+	assign r_adder11_sel = (running_state & (quotient_new[3:0] == 4'd11)) & ~shortq_enable_ff;
+	assign r_adder12_sel = (running_state & (quotient_new[3:0] == 4'd12)) & ~shortq_enable_ff;
+	assign r_adder13_sel = (running_state & (quotient_new[3:0] == 4'd13)) & ~shortq_enable_ff;
+	assign r_adder14_sel = (running_state & (quotient_new[3:0] == 4'd14)) & ~shortq_enable_ff;
+	assign r_adder15_sel = (running_state & (quotient_new[3:0] == 4'd15)) & ~shortq_enable_ff;
+	assign r_in[32:0] = (((((((((((((((((({33 {r_sign_sel}} & {33 {1'b1}}) | ({33 {r_restore_sel}} & {r_ff[28:0], a_ff[31:28]})) | ({33 {r_adder01_sel}} & adder01_out[32:0])) | ({33 {r_adder02_sel}} & adder02_out[32:0])) | ({33 {r_adder03_sel}} & adder03_out[32:0])) | ({33 {r_adder04_sel}} & adder04_out[32:0])) | ({33 {r_adder05_sel}} & adder05_out[32:0])) | ({33 {r_adder06_sel}} & adder06_out[32:0])) | ({33 {r_adder07_sel}} & adder07_out[32:0])) | ({33 {r_adder08_sel}} & adder08_out[32:0])) | ({33 {r_adder09_sel}} & adder09_out[32:0])) | ({33 {r_adder10_sel}} & adder10_out[32:0])) | ({33 {r_adder11_sel}} & adder11_out[32:0])) | ({33 {r_adder12_sel}} & adder12_out[32:0])) | ({33 {r_adder13_sel}} & adder13_out[32:0])) | ({33 {r_adder14_sel}} & adder14_out[32:0])) | ({33 {r_adder15_sel}} & adder15_out[32:0])) | ({33 {shortq_enable_ff}} & ar_shifted[64:32])) | ({33 {by_zero_case}} & {1'b0, a_ff[31:0]});
+	assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[27:0], quotient_new[3:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}});
+	assign b_ff[37:33] = {b_ff[32], b_ff[32], b_ff[32], b_ff[32], b_ff[32]};
+	assign adder01_out[34:0] = {r_ff[30:0], a_ff[31:28]} + b_ff[34:0];
+	assign adder02_out[35:0] = {r_ff[31:0], a_ff[31:28]} + {b_ff[34:0], 1'b0};
+	assign adder03_out[36:0] = ({r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 1'b0}) + b_ff[36:0];
+	assign adder04_out[37:0] = {r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00};
+	assign adder05_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + b_ff[37:0];
+	assign adder06_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0};
+	assign adder07_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}) + b_ff[37:0];
+	assign adder08_out[37:0] = {r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000};
+	assign adder09_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + b_ff[37:0];
+	assign adder10_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[36:0], 1'b0};
+	assign adder11_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[36:0], 1'b0}) + b_ff[37:0];
+	assign adder12_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00};
+	assign adder13_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + b_ff[37:0];
+	assign adder14_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0};
+	assign adder15_out[37:0] = ((({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}) + b_ff[37:0];
+	assign quotient_raw[1] = (~adder01_out[34] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder01_out[34:0] == 35'b00000000000000000000000000000000000));
+	assign quotient_raw[2] = (~adder02_out[35] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder02_out[35:0] == 36'b000000000000000000000000000000000000));
+	assign quotient_raw[3] = (~adder03_out[36] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder03_out[36:0] == 37'b0000000000000000000000000000000000000));
+	assign quotient_raw[4] = (~adder04_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder04_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[5] = (~adder05_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder05_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[6] = (~adder06_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder06_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[7] = (~adder07_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder07_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[8] = (~adder08_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder08_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[9] = (~adder09_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder09_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[10] = (~adder10_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder10_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[11] = (~adder11_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder11_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[12] = (~adder12_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder12_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[13] = (~adder13_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder13_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[14] = (~adder14_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder14_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_raw[15] = (~adder15_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder15_out[37:0] == 38'b00000000000000000000000000000000000000));
+	assign quotient_new[0] = (((((((quotient_raw[15:1] == 15'b000000000000001) | (quotient_raw[15:3] == 13'b0000000000001)) | (quotient_raw[15:5] == 11'b00000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:9] == 7'b0000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15] == 1'b1);
+	assign quotient_new[1] = (((((((quotient_raw[15:2] == 14'b00000000000001) | (quotient_raw[15:3] == 13'b0000000000001)) | (quotient_raw[15:6] == 10'b0000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:10] == 6'b000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1);
+	assign quotient_new[2] = (((((((quotient_raw[15:4] == 12'b000000000001) | (quotient_raw[15:5] == 11'b00000000001)) | (quotient_raw[15:6] == 10'b0000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:12] == 4'b0001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1);
+	assign quotient_new[3] = (((((((quotient_raw[15:8] == 8'b00000001) | (quotient_raw[15:9] == 7'b0000001)) | (quotient_raw[15:10] == 6'b000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:12] == 4'b0001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1);
+	assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);
+	assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff;
+	assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]);
+	rvtwoscomp #(.WIDTH(32)) i_twos_comp(
+		.din(twos_comp_in[31:0]),
+		.dout(twos_comp_out[31:0])
+	);
+	assign valid_out = finish_ff & ~cancel;
+	assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]);
+	assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel);
+	assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1];
+	assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]);
+	assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]);
+	assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]);
+	assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]};
+	wire [5:0] dw_a_enc;
+	wire [5:0] dw_b_enc;
+	wire [6:0] dw_shortq_raw;
+	eb1_exu_div_cls i_a_cls(
+		.operand(shortq_dividend[32:0]),
+		.cls(dw_a_enc[4:0])
+	);
+	eb1_exu_div_cls i_b_cls(
+		.operand(b_ff[32:0]),
+		.cls(dw_b_enc[4:0])
+	);
+	assign dw_a_enc[5] = 1'b0;
+	assign dw_b_enc[5] = 1'b0;
+	assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1;
+	assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]);
+	assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:2] == 3'b111)) & ~cancel;
+	assign shortq_decode[4:0] = ((((((((((((((((((((((((((((((({5 {shortq[4:0] == 5'd31}} & 5'd0) | ({5 {shortq[4:0] == 5'd30}} & 5'd0)) | ({5 {shortq[4:0] == 5'd29}} & 5'd0)) | ({5 {shortq[4:0] == 5'd28}} & 5'd0)) | ({5 {shortq[4:0] == 5'd27}} & 5'd4)) | ({5 {shortq[4:0] == 5'd26}} & 5'd4)) | ({5 {shortq[4:0] == 5'd25}} & 5'd4)) | ({5 {shortq[4:0] == 5'd24}} & 5'd4)) | ({5 {shortq[4:0] == 5'd23}} & 5'd8)) | ({5 {shortq[4:0] == 5'd22}} & 5'd8)) | ({5 {shortq[4:0] == 5'd21}} & 5'd8)) | ({5 {shortq[4:0] == 5'd20}} & 5'd8)) | ({5 {shortq[4:0] == 5'd19}} & 5'd12)) | ({5 {shortq[4:0] == 5'd18}} & 5'd12)) | ({5 {shortq[4:0] == 5'd17}} & 5'd12)) | ({5 {shortq[4:0] == 5'd16}} & 5'd12)) | ({5 {shortq[4:0] == 5'd15}} & 5'd16)) | ({5 {shortq[4:0] == 5'd14}} & 5'd16)) | ({5 {shortq[4:0] == 5'd13}} & 5'd16)) | ({5 {shortq[4:0] == 5'd12}} & 5'd16)) | ({5 {shortq[4:0] == 5'd11}} & 5'd20)) | ({5 {shortq[4:0] == 5'd10}} & 5'd20)) | ({5 {shortq[4:0] == 5'd9}} & 5'd20)) | ({5 {shortq[4:0] == 5'd8}} & 5'd20)) | ({5 {shortq[4:0] == 5'd7}} & 5'd24)) | ({5 {shortq[4:0] == 5'd6}} & 5'd24)) | ({5 {shortq[4:0] == 5'd5}} & 5'd24)) | ({5 {shortq[4:0] == 5'd4}} & 5'd24)) | ({5 {shortq[4:0] == 5'd3}} & 5'd28)) | ({5 {shortq[4:0] == 5'd2}} & 5'd28)) | ({5 {shortq[4:0] == 5'd1}} & 5'd28)) | ({5 {shortq[4:0] == 5'd0}} & 5'd28);
+	assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : shortq_decode[4:0]);
+endmodule
+module eb1_exu_div_cls (
+	operand,
+	cls
+);
+	input wire [32:0] operand;
+	output wire [4:0] cls;
+	wire [4:0] cls_zeros;
+	wire [4:0] cls_ones;
+	assign cls_zeros[4:0] = (((((((((((((((((((((((((((((((({5 {operand[31] == 1'b1}} & 5'd0) | ({5 {operand[31:30] == 2'b01}} & 5'd1)) | ({5 {operand[31:29] == {{2 {1'b0}}, 1'b1}}} & 5'd2)) | ({5 {operand[31:28] == {{3 {1'b0}}, 1'b1}}} & 5'd3)) | ({5 {operand[31:27] == {{4 {1'b0}}, 1'b1}}} & 5'd4)) | ({5 {operand[31:26] == {{5 {1'b0}}, 1'b1}}} & 5'd5)) | ({5 {operand[31:25] == {{6 {1'b0}}, 1'b1}}} & 5'd6)) | ({5 {operand[31:24] == {{7 {1'b0}}, 1'b1}}} & 5'd7)) | ({5 {operand[31:23] == {{8 {1'b0}}, 1'b1}}} & 5'd8)) | ({5 {operand[31:22] == {{9 {1'b0}}, 1'b1}}} & 5'd9)) | ({5 {operand[31:21] == {{10 {1'b0}}, 1'b1}}} & 5'd10)) | ({5 {operand[31:20] == {{11 {1'b0}}, 1'b1}}} & 5'd11)) | ({5 {operand[31:19] == {{12 {1'b0}}, 1'b1}}} & 5'd12)) | ({5 {operand[31:18] == {{13 {1'b0}}, 1'b1}}} & 5'd13)) | ({5 {operand[31:17] == {{14 {1'b0}}, 1'b1}}} & 5'd14)) | ({5 {operand[31:16] == {{15 {1'b0}}, 1'b1}}} & 5'd15)) | ({5 {operand[31:15] == {{16 {1'b0}}, 1'b1}}} & 5'd16)) | ({5 {operand[31:14] == {{17 {1'b0}}, 1'b1}}} & 5'd17)) | ({5 {operand[31:13] == {{18 {1'b0}}, 1'b1}}} & 5'd18)) | ({5 {operand[31:12] == {{19 {1'b0}}, 1'b1}}} & 5'd19)) | ({5 {operand[31:11] == {{20 {1'b0}}, 1'b1}}} & 5'd20)) | ({5 {operand[31:10] == {{21 {1'b0}}, 1'b1}}} & 5'd21)) | ({5 {operand[31:9] == {{22 {1'b0}}, 1'b1}}} & 5'd22)) | ({5 {operand[31:8] == {{23 {1'b0}}, 1'b1}}} & 5'd23)) | ({5 {operand[31:7] == {{24 {1'b0}}, 1'b1}}} & 5'd24)) | ({5 {operand[31:6] == {{25 {1'b0}}, 1'b1}}} & 5'd25)) | ({5 {operand[31:5] == {{26 {1'b0}}, 1'b1}}} & 5'd26)) | ({5 {operand[31:4] == {{27 {1'b0}}, 1'b1}}} & 5'd27)) | ({5 {operand[31:3] == {{28 {1'b0}}, 1'b1}}} & 5'd28)) | ({5 {operand[31:2] == {{29 {1'b0}}, 1'b1}}} & 5'd29)) | ({5 {operand[31:1] == {{30 {1'b0}}, 1'b1}}} & 5'd30)) | ({5 {operand[31:0] == {{31 {1'b0}}, 1'b1}}} & 5'd31)) | ({5 {operand[31:0] == {32 {1'b0}}}} & 5'd0);
+	assign cls_ones[4:0] = ((((((((((((((((((((((((((((((({5 {operand[31:30] == 2'b10}} & 5'd0) | ({5 {operand[31:29] == {{2 {1'b1}}, 1'b0}}} & 5'd1)) | ({5 {operand[31:28] == {{3 {1'b1}}, 1'b0}}} & 5'd2)) | ({5 {operand[31:27] == {{4 {1'b1}}, 1'b0}}} & 5'd3)) | ({5 {operand[31:26] == {{5 {1'b1}}, 1'b0}}} & 5'd4)) | ({5 {operand[31:25] == {{6 {1'b1}}, 1'b0}}} & 5'd5)) | ({5 {operand[31:24] == {{7 {1'b1}}, 1'b0}}} & 5'd6)) | ({5 {operand[31:23] == {{8 {1'b1}}, 1'b0}}} & 5'd7)) | ({5 {operand[31:22] == {{9 {1'b1}}, 1'b0}}} & 5'd8)) | ({5 {operand[31:21] == {{10 {1'b1}}, 1'b0}}} & 5'd9)) | ({5 {operand[31:20] == {{11 {1'b1}}, 1'b0}}} & 5'd10)) | ({5 {operand[31:19] == {{12 {1'b1}}, 1'b0}}} & 5'd11)) | ({5 {operand[31:18] == {{13 {1'b1}}, 1'b0}}} & 5'd12)) | ({5 {operand[31:17] == {{14 {1'b1}}, 1'b0}}} & 5'd13)) | ({5 {operand[31:16] == {{15 {1'b1}}, 1'b0}}} & 5'd14)) | ({5 {operand[31:15] == {{16 {1'b1}}, 1'b0}}} & 5'd15)) | ({5 {operand[31:14] == {{17 {1'b1}}, 1'b0}}} & 5'd16)) | ({5 {operand[31:13] == {{18 {1'b1}}, 1'b0}}} & 5'd17)) | ({5 {operand[31:12] == {{19 {1'b1}}, 1'b0}}} & 5'd18)) | ({5 {operand[31:11] == {{20 {1'b1}}, 1'b0}}} & 5'd19)) | ({5 {operand[31:10] == {{21 {1'b1}}, 1'b0}}} & 5'd20)) | ({5 {operand[31:9] == {{22 {1'b1}}, 1'b0}}} & 5'd21)) | ({5 {operand[31:8] == {{23 {1'b1}}, 1'b0}}} & 5'd22)) | ({5 {operand[31:7] == {{24 {1'b1}}, 1'b0}}} & 5'd23)) | ({5 {operand[31:6] == {{25 {1'b1}}, 1'b0}}} & 5'd24)) | ({5 {operand[31:5] == {{26 {1'b1}}, 1'b0}}} & 5'd25)) | ({5 {operand[31:4] == {{27 {1'b1}}, 1'b0}}} & 5'd26)) | ({5 {operand[31:3] == {{28 {1'b1}}, 1'b0}}} & 5'd27)) | ({5 {operand[31:2] == {{29 {1'b1}}, 1'b0}}} & 5'd28)) | ({5 {operand[31:1] == {{30 {1'b1}}, 1'b0}}} & 5'd29)) | ({5 {operand[31:0] == {{31 {1'b1}}, 1'b0}}} & 5'd30)) | ({5 {operand[31:0] == {32 {1'b1}}}} & 5'd31);
+	assign cls[4:0] = (operand[32] ? cls_ones[4:0] : cls_zeros[4:0]);
+endmodule
+module eb1_exu_mul_ctl (
+	clk,
+	rst_l,
+	scan_mode,
+	mul_p,
+	rs1_in,
+	rs2_in,
+	result_x
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire [19:0] mul_p;
+	input wire [31:0] rs1_in;
+	input wire [31:0] rs2_in;
+	output wire [31:0] result_x;
+	wire mul_x_enable;
+	wire bit_x_enable;
+	wire signed [32:0] rs1_ext_in;
+	wire signed [32:0] rs2_ext_in;
+	wire [65:0] prod_x;
+	wire low_x;
+	wire bitmanip_sel_d;
+	wire bitmanip_sel_x;
+	wire [31:0] bitmanip_d;
+	wire [31:0] bitmanip_x;
+	wire ap_bext;
+	wire ap_bdep;
+	wire ap_clmul;
+	wire ap_clmulh;
+	wire ap_clmulr;
+	wire ap_grev;
+	wire ap_gorc;
+	wire ap_shfl;
+	wire ap_unshfl;
+	wire ap_crc32_b;
+	wire ap_crc32_h;
+	wire ap_crc32_w;
+	wire ap_crc32c_b;
+	wire ap_crc32c_h;
+	wire ap_crc32c_w;
+	wire ap_bfp;
+	generate
+		if (pt[2197-:5] == 1) begin
+			assign ap_bext = mul_p[15];
+			assign ap_bdep = mul_p[14];
+		end
+		else begin
+			assign ap_bext = 1'b0;
+			assign ap_bdep = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2202-:5] == 1) begin
+			assign ap_clmul = mul_p[13];
+			assign ap_clmulh = mul_p[12];
+			assign ap_clmulr = mul_p[11];
+		end
+		else begin
+			assign ap_clmul = 1'b0;
+			assign ap_clmulh = 1'b0;
+			assign ap_clmulr = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2187-:5] == 1) begin
+			assign ap_grev = mul_p[10];
+			assign ap_gorc = mul_p[9];
+			assign ap_shfl = mul_p[8];
+			assign ap_unshfl = mul_p[7];
+		end
+		else begin
+			assign ap_grev = 1'b0;
+			assign ap_gorc = 1'b0;
+			assign ap_shfl = 1'b0;
+			assign ap_unshfl = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2182-:5] == 1) begin
+			assign ap_crc32_b = mul_p[6];
+			assign ap_crc32_h = mul_p[5];
+			assign ap_crc32_w = mul_p[4];
+			assign ap_crc32c_b = mul_p[3];
+			assign ap_crc32c_h = mul_p[2];
+			assign ap_crc32c_w = mul_p[1];
+		end
+		else begin
+			assign ap_crc32_b = 1'b0;
+			assign ap_crc32_h = 1'b0;
+			assign ap_crc32_w = 1'b0;
+			assign ap_crc32c_b = 1'b0;
+			assign ap_crc32c_h = 1'b0;
+			assign ap_crc32c_w = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[2192-:5] == 1) begin
+			assign ap_bfp = mul_p[0];
+		end
+		else assign ap_bfp = 1'b0;
+	endgenerate
+	assign mul_x_enable = mul_p[19];
+	assign bit_x_enable = mul_p[19];
+	assign rs1_ext_in[32] = mul_p[18] & rs1_in[31];
+	assign rs2_ext_in[32] = mul_p[17] & rs2_in[31];
+	assign rs1_ext_in[31:0] = rs1_in[31:0];
+	assign rs2_ext_in[31:0] = rs2_in[31:0];
+	wire signed [32:0] rs1_x;
+	wire signed [32:0] rs2_x;
+	rvdffe #(.WIDTH(34)) i_a_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din({mul_p[16], rs1_ext_in[32:0]}),
+		.dout({low_x, rs1_x[32:0]}),
+		.en(mul_x_enable)
+	);
+	rvdffe #(.WIDTH(33)) i_b_x_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din(rs2_ext_in[32:0]),
+		.dout(rs2_x[32:0]),
+		.en(mul_x_enable)
+	);
+	assign prod_x[65:0] = rs1_x * rs2_x;
+	reg [31:0] bext_d;
+	reg bext_test_bit_d;
+	integer bext_i;
+	integer bext_j;
+	always @(*) begin
+		bext_j = 0;
+		bext_test_bit_d = 1'b0;
+		bext_d[31:0] = 32'b00000000000000000000000000000000;
+		for (bext_i = 0; bext_i < 32; bext_i = bext_i + 1)
+			begin
+				bext_test_bit_d = rs2_in[bext_i];
+				if (bext_test_bit_d) begin
+					bext_d[bext_j] = rs1_in[bext_i];
+					bext_j = bext_j + 1;
+				end
+			end
+	end
+	reg [31:0] bdep_d;
+	reg bdep_test_bit_d;
+	integer bdep_i;
+	integer bdep_j;
+	always @(*) begin
+		bdep_j = 0;
+		bdep_test_bit_d = 1'b0;
+		bdep_d[31:0] = 32'b00000000000000000000000000000000;
+		for (bdep_i = 0; bdep_i < 32; bdep_i = bdep_i + 1)
+			begin
+				bdep_test_bit_d = rs2_in[bdep_i];
+				if (bdep_test_bit_d) begin
+					bdep_d[bdep_i] = rs1_in[bdep_j];
+					bdep_j = bdep_j + 1;
+				end
+			end
+	end
+	wire [62:0] clmul_raw_d;
+	assign clmul_raw_d[62:0] = ((((((((((((((((((((((((((((((({63 {rs2_in[0]}} & {31'b0000000000000000000000000000000, rs1_in[31:0]}) ^ ({63 {rs2_in[1]}} & {30'b000000000000000000000000000000, rs1_in[31:0], 1'b0})) ^ ({63 {rs2_in[2]}} & {29'b00000000000000000000000000000, rs1_in[31:0], 2'b00})) ^ ({63 {rs2_in[3]}} & {28'b0000000000000000000000000000, rs1_in[31:0], 3'b000})) ^ ({63 {rs2_in[4]}} & {27'b000000000000000000000000000, rs1_in[31:0], 4'b0000})) ^ ({63 {rs2_in[5]}} & {26'b00000000000000000000000000, rs1_in[31:0], 5'b00000})) ^ ({63 {rs2_in[6]}} & {25'b0000000000000000000000000, rs1_in[31:0], 6'b000000})) ^ ({63 {rs2_in[7]}} & {24'b000000000000000000000000, rs1_in[31:0], 7'b0000000})) ^ ({63 {rs2_in[8]}} & {23'b00000000000000000000000, rs1_in[31:0], 8'b00000000})) ^ ({63 {rs2_in[9]}} & {22'b0000000000000000000000, rs1_in[31:0], 9'b000000000})) ^ ({63 {rs2_in[10]}} & {21'b000000000000000000000, rs1_in[31:0], 10'b0000000000})) ^ ({63 {rs2_in[11]}} & {20'b00000000000000000000, rs1_in[31:0], 11'b00000000000})) ^ ({63 {rs2_in[12]}} & {19'b0000000000000000000, rs1_in[31:0], 12'b000000000000})) ^ ({63 {rs2_in[13]}} & {18'b000000000000000000, rs1_in[31:0], 13'b0000000000000})) ^ ({63 {rs2_in[14]}} & {17'b00000000000000000, rs1_in[31:0], 14'b00000000000000})) ^ ({63 {rs2_in[15]}} & {16'b0000000000000000, rs1_in[31:0], 15'b000000000000000})) ^ ({63 {rs2_in[16]}} & {15'b000000000000000, rs1_in[31:0], 16'b0000000000000000})) ^ ({63 {rs2_in[17]}} & {14'b00000000000000, rs1_in[31:0], 17'b00000000000000000})) ^ ({63 {rs2_in[18]}} & {13'b0000000000000, rs1_in[31:0], 18'b000000000000000000})) ^ ({63 {rs2_in[19]}} & {12'b000000000000, rs1_in[31:0], 19'b0000000000000000000})) ^ ({63 {rs2_in[20]}} & {11'b00000000000, rs1_in[31:0], 20'b00000000000000000000})) ^ ({63 {rs2_in[21]}} & {10'b0000000000, rs1_in[31:0], 21'b000000000000000000000})) ^ ({63 {rs2_in[22]}} & {9'b000000000, rs1_in[31:0], 22'b0000000000000000000000})) ^ ({63 {rs2_in[23]}} & {8'b00000000, rs1_in[31:0], 23'b00000000000000000000000})) ^ ({63 {rs2_in[24]}} & {7'b0000000, rs1_in[31:0], 24'b000000000000000000000000})) ^ ({63 {rs2_in[25]}} & {6'b000000, rs1_in[31:0], 25'b0000000000000000000000000})) ^ ({63 {rs2_in[26]}} & {5'b00000, rs1_in[31:0], 26'b00000000000000000000000000})) ^ ({63 {rs2_in[27]}} & {4'b0000, rs1_in[31:0], 27'b000000000000000000000000000})) ^ ({63 {rs2_in[28]}} & {3'b000, rs1_in[31:0], 28'b0000000000000000000000000000})) ^ ({63 {rs2_in[29]}} & {2'b00, rs1_in[31:0], 29'b00000000000000000000000000000})) ^ ({63 {rs2_in[30]}} & {1'b0, rs1_in[31:0], 30'b000000000000000000000000000000})) ^ ({63 {rs2_in[31]}} & {rs1_in[31:0], 31'b0000000000000000000000000000000});
+	wire [31:0] grev1_d;
+	wire [31:0] grev2_d;
+	wire [31:0] grev4_d;
+	wire [31:0] grev8_d;
+	wire [31:0] grev_d;
+	assign grev1_d[31:0] = (rs2_in[0] ? {rs1_in[30], rs1_in[31], rs1_in[28], rs1_in[29], rs1_in[26], rs1_in[27], rs1_in[24], rs1_in[25], rs1_in[22], rs1_in[23], rs1_in[20], rs1_in[21], rs1_in[18], rs1_in[19], rs1_in[16], rs1_in[17], rs1_in[14], rs1_in[15], rs1_in[12], rs1_in[13], rs1_in[10], rs1_in[11], rs1_in[8], rs1_in[9], rs1_in[6], rs1_in[7], rs1_in[4], rs1_in[5], rs1_in[2], rs1_in[3], rs1_in[0], rs1_in[1]} : rs1_in[31:0]);
+	assign grev2_d[31:0] = (rs2_in[1] ? {grev1_d[29:28], grev1_d[31:30], grev1_d[25:24], grev1_d[27:26], grev1_d[21:20], grev1_d[23:22], grev1_d[17:16], grev1_d[19:18], grev1_d[13:12], grev1_d[15:14], grev1_d[9:8], grev1_d[11:10], grev1_d[5:4], grev1_d[7:6], grev1_d[1:0], grev1_d[3:2]} : grev1_d[31:0]);
+	assign grev4_d[31:0] = (rs2_in[2] ? {grev2_d[27:24], grev2_d[31:28], grev2_d[19:16], grev2_d[23:20], grev2_d[11:8], grev2_d[15:12], grev2_d[3:0], grev2_d[7:4]} : grev2_d[31:0]);
+	assign grev8_d[31:0] = (rs2_in[3] ? {grev4_d[23:16], grev4_d[31:24], grev4_d[7:0], grev4_d[15:8]} : grev4_d[31:0]);
+	assign grev_d[31:0] = (rs2_in[4] ? {grev8_d[15:0], grev8_d[31:16]} : grev8_d[31:0]);
+	wire [31:0] gorc1_d;
+	wire [31:0] gorc2_d;
+	wire [31:0] gorc4_d;
+	wire [31:0] gorc8_d;
+	wire [31:0] gorc_d;
+	assign gorc1_d[31:0] = ({32 {rs2_in[0]}} & {rs1_in[30], rs1_in[31], rs1_in[28], rs1_in[29], rs1_in[26], rs1_in[27], rs1_in[24], rs1_in[25], rs1_in[22], rs1_in[23], rs1_in[20], rs1_in[21], rs1_in[18], rs1_in[19], rs1_in[16], rs1_in[17], rs1_in[14], rs1_in[15], rs1_in[12], rs1_in[13], rs1_in[10], rs1_in[11], rs1_in[8], rs1_in[9], rs1_in[6], rs1_in[7], rs1_in[4], rs1_in[5], rs1_in[2], rs1_in[3], rs1_in[0], rs1_in[1]}) | rs1_in[31:0];
+	assign gorc2_d[31:0] = ({32 {rs2_in[1]}} & {gorc1_d[29:28], gorc1_d[31:30], gorc1_d[25:24], gorc1_d[27:26], gorc1_d[21:20], gorc1_d[23:22], gorc1_d[17:16], gorc1_d[19:18], gorc1_d[13:12], gorc1_d[15:14], gorc1_d[9:8], gorc1_d[11:10], gorc1_d[5:4], gorc1_d[7:6], gorc1_d[1:0], gorc1_d[3:2]}) | gorc1_d[31:0];
+	assign gorc4_d[31:0] = ({32 {rs2_in[2]}} & {gorc2_d[27:24], gorc2_d[31:28], gorc2_d[19:16], gorc2_d[23:20], gorc2_d[11:8], gorc2_d[15:12], gorc2_d[3:0], gorc2_d[7:4]}) | gorc2_d[31:0];
+	assign gorc8_d[31:0] = ({32 {rs2_in[3]}} & {gorc4_d[23:16], gorc4_d[31:24], gorc4_d[7:0], gorc4_d[15:8]}) | gorc4_d[31:0];
+	assign gorc_d[31:0] = ({32 {rs2_in[4]}} & {gorc8_d[15:0], gorc8_d[31:16]}) | gorc8_d[31:0];
+	wire [31:0] shfl8_d;
+	wire [31:0] shfl4_d;
+	wire [31:0] shfl2_d;
+	wire [31:0] shfl_d;
+	assign shfl8_d[31:0] = (rs2_in[3] ? {rs1_in[31:24], rs1_in[15:8], rs1_in[23:16], rs1_in[7:0]} : rs1_in[31:0]);
+	assign shfl4_d[31:0] = (rs2_in[2] ? {shfl8_d[31:28], shfl8_d[23:20], shfl8_d[27:24], shfl8_d[19:16], shfl8_d[15:12], shfl8_d[7:4], shfl8_d[11:8], shfl8_d[3:0]} : shfl8_d[31:0]);
+	assign shfl2_d[31:0] = (rs2_in[1] ? {shfl4_d[31:30], shfl4_d[27:26], shfl4_d[29:28], shfl4_d[25:24], shfl4_d[23:22], shfl4_d[19:18], shfl4_d[21:20], shfl4_d[17:16], shfl4_d[15:14], shfl4_d[11:10], shfl4_d[13:12], shfl4_d[9:8], shfl4_d[7:6], shfl4_d[3:2], shfl4_d[5:4], shfl4_d[1:0]} : shfl4_d[31:0]);
+	assign shfl_d[31:0] = (rs2_in[0] ? {shfl2_d[31], shfl2_d[29], shfl2_d[30], shfl2_d[28], shfl2_d[27], shfl2_d[25], shfl2_d[26], shfl2_d[24], shfl2_d[23], shfl2_d[21], shfl2_d[22], shfl2_d[20], shfl2_d[19], shfl2_d[17], shfl2_d[18], shfl2_d[16], shfl2_d[15], shfl2_d[13], shfl2_d[14], shfl2_d[12], shfl2_d[11], shfl2_d[9], shfl2_d[10], shfl2_d[8], shfl2_d[7], shfl2_d[5], shfl2_d[6], shfl2_d[4], shfl2_d[3], shfl2_d[1], shfl2_d[2], shfl2_d[0]} : shfl2_d[31:0]);
+	wire [31:0] unshfl1_d;
+	wire [31:0] unshfl2_d;
+	wire [31:0] unshfl4_d;
+	wire [31:0] unshfl_d;
+	assign unshfl1_d[31:0] = (rs2_in[0] ? {rs1_in[31], rs1_in[29], rs1_in[30], rs1_in[28], rs1_in[27], rs1_in[25], rs1_in[26], rs1_in[24], rs1_in[23], rs1_in[21], rs1_in[22], rs1_in[20], rs1_in[19], rs1_in[17], rs1_in[18], rs1_in[16], rs1_in[15], rs1_in[13], rs1_in[14], rs1_in[12], rs1_in[11], rs1_in[9], rs1_in[10], rs1_in[8], rs1_in[7], rs1_in[5], rs1_in[6], rs1_in[4], rs1_in[3], rs1_in[1], rs1_in[2], rs1_in[0]} : rs1_in[31:0]);
+	assign unshfl2_d[31:0] = (rs2_in[1] ? {unshfl1_d[31:30], unshfl1_d[27:26], unshfl1_d[29:28], unshfl1_d[25:24], unshfl1_d[23:22], unshfl1_d[19:18], unshfl1_d[21:20], unshfl1_d[17:16], unshfl1_d[15:14], unshfl1_d[11:10], unshfl1_d[13:12], unshfl1_d[9:8], unshfl1_d[7:6], unshfl1_d[3:2], unshfl1_d[5:4], unshfl1_d[1:0]} : unshfl1_d[31:0]);
+	assign unshfl4_d[31:0] = (rs2_in[2] ? {unshfl2_d[31:28], unshfl2_d[23:20], unshfl2_d[27:24], unshfl2_d[19:16], unshfl2_d[15:12], unshfl2_d[7:4], unshfl2_d[11:8], unshfl2_d[3:0]} : unshfl2_d[31:0]);
+	assign unshfl_d[31:0] = (rs2_in[3] ? {unshfl4_d[31:24], unshfl4_d[15:8], unshfl4_d[23:16], unshfl4_d[7:0]} : unshfl4_d[31:0]);
+	wire crc32_all;
+	wire [31:0] crc32_poly_rev;
+	wire [31:0] crc32c_poly_rev;
+	integer crc32_bi;
+	integer crc32_hi;
+	integer crc32_wi;
+	integer crc32c_bi;
+	integer crc32c_hi;
+	integer crc32c_wi;
+	reg [31:0] crc32_bd;
+	reg [31:0] crc32_hd;
+	reg [31:0] crc32_wd;
+	reg [31:0] crc32c_bd;
+	reg [31:0] crc32c_hd;
+	reg [31:0] crc32c_wd;
+	assign crc32_all = ((((ap_crc32_b | ap_crc32_h) | ap_crc32_w) | ap_crc32c_b) | ap_crc32c_h) | ap_crc32c_w;
+	assign crc32_poly_rev[31:0] = 32'hedb88320;
+	assign crc32c_poly_rev[31:0] = 32'h82f63b78;
+	always @(*) begin
+		crc32_bd[31:0] = rs1_in[31:0];
+		for (crc32_bi = 0; crc32_bi < 8; crc32_bi = crc32_bi + 1)
+			crc32_bd[31:0] = (crc32_bd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_bd[0]}});
+	end
+	always @(*) begin
+		crc32_hd[31:0] = rs1_in[31:0];
+		for (crc32_hi = 0; crc32_hi < 16; crc32_hi = crc32_hi + 1)
+			crc32_hd[31:0] = (crc32_hd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_hd[0]}});
+	end
+	always @(*) begin
+		crc32_wd[31:0] = rs1_in[31:0];
+		for (crc32_wi = 0; crc32_wi < 32; crc32_wi = crc32_wi + 1)
+			crc32_wd[31:0] = (crc32_wd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_wd[0]}});
+	end
+	always @(*) begin
+		crc32c_bd[31:0] = rs1_in[31:0];
+		for (crc32c_bi = 0; crc32c_bi < 8; crc32c_bi = crc32c_bi + 1)
+			crc32c_bd[31:0] = (crc32c_bd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_bd[0]}});
+	end
+	always @(*) begin
+		crc32c_hd[31:0] = rs1_in[31:0];
+		for (crc32c_hi = 0; crc32c_hi < 16; crc32c_hi = crc32c_hi + 1)
+			crc32c_hd[31:0] = (crc32c_hd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_hd[0]}});
+	end
+	always @(*) begin
+		crc32c_wd[31:0] = rs1_in[31:0];
+		for (crc32c_wi = 0; crc32c_wi < 32; crc32c_wi = crc32c_wi + 1)
+			crc32c_wd[31:0] = (crc32c_wd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_wd[0]}});
+	end
+	wire [4:0] bfp_len;
+	wire [4:0] bfp_off;
+	wire [31:0] bfp_len_mask_;
+	wire [15:0] bfp_preshift_data;
+	wire [63:0] bfp_shift_data;
+	wire [63:0] bfp_shift_mask;
+	wire [31:0] bfp_result_d;
+	assign bfp_len[3:0] = rs2_in[27:24];
+	assign bfp_len[4] = bfp_len[3:0] == 4'b0000;
+	assign bfp_off[4:0] = rs2_in[20:16];
+	assign bfp_len_mask_[31:0] = 32'hffffffff << bfp_len[4:0];
+	assign bfp_preshift_data[15:0] = rs2_in[15:0] & ~bfp_len_mask_[15:0];
+	assign bfp_shift_data[63:0] = {16'b0000000000000000, bfp_preshift_data[15:0], 16'b0000000000000000, bfp_preshift_data[15:0]} << bfp_off[4:0];
+	assign bfp_shift_mask[63:0] = {bfp_len_mask_[31:0], bfp_len_mask_[31:0]} << bfp_off[4:0];
+	assign bfp_result_d[31:0] = bfp_shift_data[63:32] | (rs1_in[31:0] & bfp_shift_mask[63:32]);
+	assign bitmanip_sel_d = (((((((((ap_bext | ap_bdep) | ap_clmul) | ap_clmulh) | ap_clmulr) | ap_grev) | ap_gorc) | ap_shfl) | ap_unshfl) | crc32_all) | ap_bfp;
+	assign bitmanip_d[31:0] = ((((((((((((((({32 {ap_bext}} & bext_d[31:0]) | ({32 {ap_bdep}} & bdep_d[31:0])) | ({32 {ap_clmul}} & clmul_raw_d[31:0])) | ({32 {ap_clmulh}} & {1'b0, clmul_raw_d[62:32]})) | ({32 {ap_clmulr}} & clmul_raw_d[62:31])) | ({32 {ap_grev}} & grev_d[31:0])) | ({32 {ap_gorc}} & gorc_d[31:0])) | ({32 {ap_shfl}} & shfl_d[31:0])) | ({32 {ap_unshfl}} & unshfl_d[31:0])) | ({32 {ap_crc32_b}} & crc32_bd[31:0])) | ({32 {ap_crc32_h}} & crc32_hd[31:0])) | ({32 {ap_crc32_w}} & crc32_wd[31:0])) | ({32 {ap_crc32c_b}} & crc32c_bd[31:0])) | ({32 {ap_crc32c_h}} & crc32c_hd[31:0])) | ({32 {ap_crc32c_w}} & crc32c_wd[31:0])) | ({32 {ap_bfp}} & bfp_result_d[31:0]);
+	rvdffe #(.WIDTH(33)) i_bitmanip_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din({bitmanip_sel_d, bitmanip_d[31:0]}),
+		.dout({bitmanip_sel_x, bitmanip_x[31:0]}),
+		.en(bit_x_enable)
+	);
+	assign result_x[31:0] = (({32 {~bitmanip_sel_x & ~low_x}} & prod_x[63:32]) | ({32 {~bitmanip_sel_x & low_x}} & prod_x[31:0])) | bitmanip_x[31:0];
+endmodule
+module eb1_ifu (
+	free_l2clk,
+	active_clk,
+	clk,
+	rst_l,
+	dec_i0_decode_d,
+	exu_flush_final,
+	dec_tlu_i0_commit_cmt,
+	dec_tlu_flush_err_wb,
+	dec_tlu_flush_noredir_wb,
+	exu_flush_path_final,
+	dec_tlu_mrac_ff,
+	dec_tlu_fence_i_wb,
+	dec_tlu_flush_leak_one_wb,
+	dec_tlu_bpred_disable,
+	dec_tlu_core_ecc_disable,
+	dec_tlu_force_halt,
+	ifu_axi_awvalid,
+	ifu_axi_awid,
+	ifu_axi_awaddr,
+	ifu_axi_awregion,
+	ifu_axi_awlen,
+	ifu_axi_awsize,
+	ifu_axi_awburst,
+	ifu_axi_awlock,
+	ifu_axi_awcache,
+	ifu_axi_awprot,
+	ifu_axi_awqos,
+	ifu_axi_wvalid,
+	ifu_axi_wdata,
+	ifu_axi_wstrb,
+	ifu_axi_wlast,
+	ifu_axi_bready,
+	ifu_axi_arvalid,
+	ifu_axi_arready,
+	ifu_axi_arid,
+	ifu_axi_araddr,
+	ifu_axi_arregion,
+	ifu_axi_arlen,
+	ifu_axi_arsize,
+	ifu_axi_arburst,
+	ifu_axi_arlock,
+	ifu_axi_arcache,
+	ifu_axi_arprot,
+	ifu_axi_arqos,
+	ifu_axi_rvalid,
+	ifu_axi_rready,
+	ifu_axi_rid,
+	ifu_axi_rdata,
+	ifu_axi_rresp,
+	ifu_bus_clk_en,
+	dma_iccm_req,
+	dma_mem_addr,
+	dma_mem_sz,
+	dma_mem_write,
+	dma_mem_wdata,
+	dma_mem_tag,
+	dma_iccm_stall_any,
+	iccm_dma_ecc_error,
+	iccm_dma_rvalid,
+	iccm_dma_rdata,
+	iccm_dma_rtag,
+	iccm_ready,
+	ifu_pmu_instr_aligned,
+	ifu_pmu_fetch_stall,
+	ifu_ic_error_start,
+	ic_rw_addr,
+	ic_wr_en,
+	ic_rd_en,
+	ic_wr_data,
+	ic_rd_data,
+	ic_debug_rd_data,
+	ictag_debug_rd_data,
+	ic_debug_wr_data,
+	ifu_ic_debug_rd_data,
+	ic_eccerr,
+	ic_parerr,
+	ic_premux_data,
+	ic_sel_premux_data,
+	ic_debug_addr,
+	ic_debug_rd_en,
+	ic_debug_wr_en,
+	ic_debug_tag_array,
+	ic_debug_way,
+	ic_tag_valid,
+	ic_rd_hit,
+	ic_tag_perr,
+	iccm_rw_addr,
+	iccm_wren,
+	iccm_rden,
+	iccm_wr_data,
+	iccm_wr_size,
+	iccm_rd_data,
+	iccm_rd_data_ecc,
+	ifu_iccm_rd_ecc_single_err,
+	ifu_pmu_ic_miss,
+	ifu_pmu_ic_hit,
+	ifu_pmu_bus_error,
+	ifu_pmu_bus_busy,
+	ifu_pmu_bus_trxn,
+	ifu_i0_icaf,
+	ifu_i0_icaf_type,
+	ifu_i0_valid,
+	ifu_i0_icaf_second,
+	ifu_i0_dbecc,
+	iccm_dma_sb_error,
+	ifu_i0_instr,
+	ifu_i0_pc,
+	ifu_i0_pc4,
+	ifu_miss_state_idle,
+	i0_brp,
+	ifu_i0_bp_index,
+	ifu_i0_bp_fghr,
+	ifu_i0_bp_btag,
+	ifu_i0_fa_index,
+	exu_mp_pkt,
+	exu_mp_eghr,
+	exu_mp_fghr,
+	exu_mp_index,
+	exu_mp_btag,
+	dec_tlu_br0_r_pkt,
+	exu_i0_br_fghr_r,
+	exu_i0_br_index_r,
+	dec_fa_error_index,
+	dec_tlu_flush_lower_wb,
+	ifu_i0_cinst,
+	dec_tlu_ic_diag_pkt,
+	ifu_ic_debug_rd_data_valid,
+	iccm_buf_correct_ecc,
+	iccm_correction_state,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire free_l2clk;
+	input wire active_clk;
+	input wire clk;
+	input wire rst_l;
+	input wire dec_i0_decode_d;
+	input wire exu_flush_final;
+	input wire dec_tlu_i0_commit_cmt;
+	input wire dec_tlu_flush_err_wb;
+	input wire dec_tlu_flush_noredir_wb;
+	input wire [31:1] exu_flush_path_final;
+	input wire [31:0] dec_tlu_mrac_ff;
+	input wire dec_tlu_fence_i_wb;
+	input wire dec_tlu_flush_leak_one_wb;
+	input wire dec_tlu_bpred_disable;
+	input wire dec_tlu_core_ecc_disable;
+	input wire dec_tlu_force_halt;
+	output wire ifu_axi_awvalid;
+	output wire [pt[826-:8] - 1:0] ifu_axi_awid;
+	output wire [31:0] ifu_axi_awaddr;
+	output wire [3:0] ifu_axi_awregion;
+	output wire [7:0] ifu_axi_awlen;
+	output wire [2:0] ifu_axi_awsize;
+	output wire [1:0] ifu_axi_awburst;
+	output wire ifu_axi_awlock;
+	output wire [3:0] ifu_axi_awcache;
+	output wire [2:0] ifu_axi_awprot;
+	output wire [3:0] ifu_axi_awqos;
+	output wire ifu_axi_wvalid;
+	output wire [63:0] ifu_axi_wdata;
+	output wire [7:0] ifu_axi_wstrb;
+	output wire ifu_axi_wlast;
+	output wire ifu_axi_bready;
+	output wire ifu_axi_arvalid;
+	input wire ifu_axi_arready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_arid;
+	output wire [31:0] ifu_axi_araddr;
+	output wire [3:0] ifu_axi_arregion;
+	output wire [7:0] ifu_axi_arlen;
+	output wire [2:0] ifu_axi_arsize;
+	output wire [1:0] ifu_axi_arburst;
+	output wire ifu_axi_arlock;
+	output wire [3:0] ifu_axi_arcache;
+	output wire [2:0] ifu_axi_arprot;
+	output wire [3:0] ifu_axi_arqos;
+	input wire ifu_axi_rvalid;
+	output wire ifu_axi_rready;
+	input wire [pt[826-:8] - 1:0] ifu_axi_rid;
+	input wire [63:0] ifu_axi_rdata;
+	input wire [1:0] ifu_axi_rresp;
+	input wire ifu_bus_clk_en;
+	input wire dma_iccm_req;
+	input wire [31:0] dma_mem_addr;
+	input wire [2:0] dma_mem_sz;
+	input wire dma_mem_write;
+	input wire [63:0] dma_mem_wdata;
+	input wire [2:0] dma_mem_tag;
+	input wire dma_iccm_stall_any;
+	output wire iccm_dma_ecc_error;
+	output wire iccm_dma_rvalid;
+	output wire [63:0] iccm_dma_rdata;
+	output wire [2:0] iccm_dma_rtag;
+	output wire iccm_ready;
+	output wire ifu_pmu_instr_aligned;
+	output wire ifu_pmu_fetch_stall;
+	output wire ifu_ic_error_start;
+	output wire [31:1] ic_rw_addr;
+	output wire [pt[1060-:7] - 1:0] ic_wr_en;
+	output wire ic_rd_en;
+	output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data;
+	input wire [63:0] ic_rd_data;
+	input wire [70:0] ic_debug_rd_data;
+	input wire [25:0] ictag_debug_rd_data;
+	output wire [70:0] ic_debug_wr_data;
+	output wire [70:0] ifu_ic_debug_rd_data;
+	input wire [pt[1189-:7] - 1:0] ic_eccerr;
+	input wire [pt[1189-:7] - 1:0] ic_parerr;
+	output wire [63:0] ic_premux_data;
+	output wire ic_sel_premux_data;
+	output wire [pt[1104-:9]:3] ic_debug_addr;
+	output wire ic_debug_rd_en;
+	output wire ic_debug_wr_en;
+	output wire ic_debug_tag_array;
+	output wire [pt[1060-:7] - 1:0] ic_debug_way;
+	output wire [pt[1060-:7] - 1:0] ic_tag_valid;
+	input wire [pt[1060-:7] - 1:0] ic_rd_hit;
+	input wire ic_tag_perr;
+	output wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	output wire iccm_wren;
+	output wire iccm_rden;
+	output wire [77:0] iccm_wr_data;
+	output wire [2:0] iccm_wr_size;
+	input wire [63:0] iccm_rd_data;
+	input wire [77:0] iccm_rd_data_ecc;
+	output wire ifu_iccm_rd_ecc_single_err;
+	output wire ifu_pmu_ic_miss;
+	output wire ifu_pmu_ic_hit;
+	output wire ifu_pmu_bus_error;
+	output wire ifu_pmu_bus_busy;
+	output wire ifu_pmu_bus_trxn;
+	output wire ifu_i0_icaf;
+	output wire [1:0] ifu_i0_icaf_type;
+	output wire ifu_i0_valid;
+	output wire ifu_i0_icaf_second;
+	output wire ifu_i0_dbecc;
+	output wire iccm_dma_sb_error;
+	output wire [31:0] ifu_i0_instr;
+	output wire [31:1] ifu_i0_pc;
+	output wire ifu_i0_pc4;
+	output wire ifu_miss_state_idle;
+	output wire [50:0] i0_brp;
+	output wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index;
+	output wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr;
+	output wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag;
+	output wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index;
+	input wire [55:0] exu_mp_pkt;
+	input wire [pt[2236-:8] - 1:0] exu_mp_eghr;
+	input wire [pt[2236-:8] - 1:0] exu_mp_fghr;
+	input wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index;
+	input wire [pt[2139-:9] - 1:0] exu_mp_btag;
+	input wire [6:0] dec_tlu_br0_r_pkt;
+	input wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r;
+	input wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r;
+	input wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index;
+	input dec_tlu_flush_lower_wb;
+	output wire [15:0] ifu_i0_cinst;
+	input wire [89:0] dec_tlu_ic_diag_pkt;
+	output wire ifu_ic_debug_rd_data_valid;
+	output wire iccm_buf_correct_ecc;
+	output wire iccm_correction_state;
+	input wire scan_mode;
+	localparam TAGWIDTH = 2;
+	localparam IDWIDTH = 2;
+	wire ifu_fb_consume1;
+	wire ifu_fb_consume2;
+	wire [31:1] ifc_fetch_addr_f;
+	wire [31:1] ifc_fetch_addr_bf;
+	wire [1:0] ifu_fetch_val;
+	wire [31:1] ifu_fetch_pc;
+	wire iccm_rd_ecc_single_err;
+	wire ic_error_start;
+	assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
+	assign ifu_ic_error_start = ic_error_start;
+	wire ic_write_stall;
+	wire ic_dma_active;
+	wire ifc_dma_access_ok;
+	wire [1:0] ic_access_fault_f;
+	wire [1:0] ic_access_fault_type_f;
+	wire ifu_ic_mb_empty;
+	wire ic_hit_f;
+	wire [1:0] ifu_bp_way_f;
+	wire ifu_bp_hit_taken_f;
+	wire [31:1] ifu_bp_btb_target_f;
+	wire ifu_bp_inst_mask_f;
+	wire [1:0] ifu_bp_hist1_f;
+	wire [1:0] ifu_bp_hist0_f;
+	wire [11:0] ifu_bp_poffset_f;
+	wire [1:0] ifu_bp_ret_f;
+	wire [1:0] ifu_bp_pc4_f;
+	wire [1:0] ifu_bp_valid_f;
+	wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f;
+	wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f;
+	wire ifc_fetch_req_bf;
+	wire ifc_fetch_req_bf_raw;
+	wire ifc_fetch_req_f;
+	wire ifc_fetch_uncacheable_bf;
+	wire ifc_iccm_access_bf;
+	wire ifc_region_acc_fault_bf;
+	eb1_ifu_ifc_ctl #(.pt(pt)) ifc(
+		.clk(clk),
+		.free_l2clk(free_l2clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.ic_hit_f(ic_hit_f),
+		.ifu_ic_mb_empty(ifu_ic_mb_empty),
+		.ifu_fb_consume1(ifu_fb_consume1),
+		.ifu_fb_consume2(ifu_fb_consume2),
+		.dec_tlu_flush_noredir_wb(dec_tlu_flush_noredir_wb),
+		.exu_flush_final(exu_flush_final),
+		.exu_flush_path_final(exu_flush_path_final),
+		.ifu_bp_hit_taken_f(ifu_bp_hit_taken_f),
+		.ifu_bp_btb_target_f(ifu_bp_btb_target_f),
+		.ic_dma_active(ic_dma_active),
+		.ic_write_stall(ic_write_stall),
+		.dma_iccm_stall_any(dma_iccm_stall_any),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.ifc_fetch_addr_f(ifc_fetch_addr_f),
+		.ifc_fetch_addr_bf(ifc_fetch_addr_bf),
+		.ifc_fetch_req_f(ifc_fetch_req_f),
+		.ifu_pmu_fetch_stall(ifu_pmu_fetch_stall),
+		.ifc_fetch_uncacheable_bf(ifc_fetch_uncacheable_bf),
+		.ifc_fetch_req_bf(ifc_fetch_req_bf),
+		.ifc_fetch_req_bf_raw(ifc_fetch_req_bf_raw),
+		.ifc_iccm_access_bf(ifc_iccm_access_bf),
+		.ifc_region_acc_fault_bf(ifc_region_acc_fault_bf),
+		.ifc_dma_access_ok(ifc_dma_access_ok)
+	);
+	generate
+		if (pt[2130-:5] == 1) begin : bpred
+			eb1_ifu_bp_ctl #(.pt(pt)) bp(
+				.clk(clk),
+				.rst_l(rst_l),
+				.ic_hit_f(ic_hit_f),
+				.ifc_fetch_addr_f(ifc_fetch_addr_f),
+				.ifc_fetch_req_f(ifc_fetch_req_f),
+				.dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt),
+				.exu_i0_br_fghr_r(exu_i0_br_fghr_r),
+				.exu_i0_br_index_r(exu_i0_br_index_r),
+				.dec_fa_error_index(dec_fa_error_index),
+				.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb),
+				.dec_tlu_flush_leak_one_wb(dec_tlu_flush_leak_one_wb),
+				.dec_tlu_bpred_disable(dec_tlu_bpred_disable),
+				.exu_mp_pkt(exu_mp_pkt),
+				.exu_mp_eghr(exu_mp_eghr),
+				.exu_mp_fghr(exu_mp_fghr),
+				.exu_mp_index(exu_mp_index),
+				.exu_mp_btag(exu_mp_btag),
+				.exu_flush_final(exu_flush_final),
+				.ifu_bp_hit_taken_f(ifu_bp_hit_taken_f),
+				.ifu_bp_btb_target_f(ifu_bp_btb_target_f),
+				.ifu_bp_inst_mask_f(ifu_bp_inst_mask_f),
+				.ifu_bp_fghr_f(ifu_bp_fghr_f),
+				.ifu_bp_way_f(ifu_bp_way_f),
+				.ifu_bp_ret_f(ifu_bp_ret_f),
+				.ifu_bp_hist1_f(ifu_bp_hist1_f),
+				.ifu_bp_hist0_f(ifu_bp_hist0_f),
+				.ifu_bp_pc4_f(ifu_bp_pc4_f),
+				.ifu_bp_valid_f(ifu_bp_valid_f),
+				.ifu_bp_poffset_f(ifu_bp_poffset_f),
+				.ifu_bp_fa_index_f(ifu_bp_fa_index_f),
+				.scan_mode(scan_mode)
+			);
+		end
+		else begin : bpred
+			assign ifu_bp_hit_taken_f = 1'b0;
+			wire btb_wr_en_way0;
+			wire btb_wr_en_way1;
+			wire dec_tlu_error_wb;
+			wire [16 + pt[2139-:9]:0] btb_wr_data;
+			assign btb_wr_en_way0 = 1'b0;
+			assign btb_wr_en_way1 = 1'b0;
+			assign btb_wr_data = {((16 + pt[2139-:9]) >= 0 ? (16 + pt[2139-:9]) + 1 : 1 - (16 + pt[2139-:9])) {1'sb0}};
+			assign dec_tlu_error_wb = 1'b0;
+			assign ifu_bp_inst_mask_f = 1'b1;
+		end
+	endgenerate
+	wire [1:0] ic_fetch_val_f;
+	wire [31:0] ic_data_f;
+	wire [31:0] ifu_fetch_data_f;
+	wire ifc_fetch_req_f_raw;
+	wire [1:0] iccm_rd_ecc_double_err;
+	wire ifu_async_error_start;
+	assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
+	assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
+	assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
+	eb1_ifu_aln_ctl #(.pt(pt)) aln(
+		.scan_mode(scan_mode),
+		.rst_l(rst_l),
+		.clk(clk),
+		.active_clk(active_clk),
+		.ifu_async_error_start(ifu_async_error_start),
+		.iccm_rd_ecc_double_err(iccm_rd_ecc_double_err),
+		.ic_access_fault_f(ic_access_fault_f),
+		.ic_access_fault_type_f(ic_access_fault_type_f),
+		.exu_flush_final(exu_flush_final),
+		.dec_i0_decode_d(dec_i0_decode_d),
+		.ifu_fetch_data_f(ifu_fetch_data_f),
+		.ifu_fetch_val(ifu_fetch_val),
+		.ifu_fetch_pc(ifu_fetch_pc),
+		.ifu_i0_valid(ifu_i0_valid),
+		.ifu_i0_icaf(ifu_i0_icaf),
+		.ifu_i0_icaf_type(ifu_i0_icaf_type),
+		.ifu_i0_icaf_second(ifu_i0_icaf_second),
+		.ifu_i0_dbecc(ifu_i0_dbecc),
+		.ifu_i0_instr(ifu_i0_instr),
+		.ifu_i0_pc(ifu_i0_pc),
+		.ifu_i0_pc4(ifu_i0_pc4),
+		.ifu_fb_consume1(ifu_fb_consume1),
+		.ifu_fb_consume2(ifu_fb_consume2),
+		.ifu_bp_fghr_f(ifu_bp_fghr_f),
+		.ifu_bp_btb_target_f(ifu_bp_btb_target_f),
+		.ifu_bp_poffset_f(ifu_bp_poffset_f),
+		.ifu_bp_fa_index_f(ifu_bp_fa_index_f),
+		.ifu_bp_hist0_f(ifu_bp_hist0_f),
+		.ifu_bp_hist1_f(ifu_bp_hist1_f),
+		.ifu_bp_pc4_f(ifu_bp_pc4_f),
+		.ifu_bp_way_f(ifu_bp_way_f),
+		.ifu_bp_valid_f(ifu_bp_valid_f),
+		.ifu_bp_ret_f(ifu_bp_ret_f),
+		.i0_brp(i0_brp),
+		.ifu_i0_bp_index(ifu_i0_bp_index),
+		.ifu_i0_bp_fghr(ifu_i0_bp_fghr),
+		.ifu_i0_bp_btag(ifu_i0_bp_btag),
+		.ifu_i0_fa_index(ifu_i0_fa_index),
+		.ifu_pmu_instr_aligned(ifu_pmu_instr_aligned),
+		.ifu_i0_cinst(ifu_i0_cinst)
+	);
+	eb1_ifu_mem_ctl #(.pt(pt)) mem_ctl(
+		.clk(clk),
+		.active_clk(active_clk),
+		.free_l2clk(free_l2clk),
+		.rst_l(rst_l),
+		.exu_flush_final(exu_flush_final),
+		.dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb),
+		.dec_tlu_flush_err_wb(dec_tlu_flush_err_wb),
+		.dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.ifc_fetch_addr_bf(ifc_fetch_addr_bf),
+		.ifc_fetch_uncacheable_bf(ifc_fetch_uncacheable_bf),
+		.ifc_fetch_req_bf(ifc_fetch_req_bf),
+		.ifc_fetch_req_bf_raw(ifc_fetch_req_bf_raw),
+		.ifc_iccm_access_bf(ifc_iccm_access_bf),
+		.ifc_region_acc_fault_bf(ifc_region_acc_fault_bf),
+		.ifc_dma_access_ok(ifc_dma_access_ok),
+		.dec_tlu_fence_i_wb(dec_tlu_fence_i_wb),
+		.ifu_bp_hit_taken_f(ifu_bp_hit_taken_f),
+		.ifu_bp_inst_mask_f(ifu_bp_inst_mask_f),
+		.ifu_miss_state_idle(ifu_miss_state_idle),
+		.ifu_ic_mb_empty(ifu_ic_mb_empty),
+		.ic_dma_active(ic_dma_active),
+		.ic_write_stall(ic_write_stall),
+		.ifu_pmu_ic_miss(ifu_pmu_ic_miss),
+		.ifu_pmu_ic_hit(ifu_pmu_ic_hit),
+		.ifu_pmu_bus_error(ifu_pmu_bus_error),
+		.ifu_pmu_bus_busy(ifu_pmu_bus_busy),
+		.ifu_pmu_bus_trxn(ifu_pmu_bus_trxn),
+		.ifu_axi_awvalid(ifu_axi_awvalid),
+		.ifu_axi_awid(ifu_axi_awid),
+		.ifu_axi_awaddr(ifu_axi_awaddr),
+		.ifu_axi_awregion(ifu_axi_awregion),
+		.ifu_axi_awlen(ifu_axi_awlen),
+		.ifu_axi_awsize(ifu_axi_awsize),
+		.ifu_axi_awburst(ifu_axi_awburst),
+		.ifu_axi_awlock(ifu_axi_awlock),
+		.ifu_axi_awcache(ifu_axi_awcache),
+		.ifu_axi_awprot(ifu_axi_awprot),
+		.ifu_axi_awqos(ifu_axi_awqos),
+		.ifu_axi_wvalid(ifu_axi_wvalid),
+		.ifu_axi_wdata(ifu_axi_wdata),
+		.ifu_axi_wstrb(ifu_axi_wstrb),
+		.ifu_axi_wlast(ifu_axi_wlast),
+		.ifu_axi_bready(ifu_axi_bready),
+		.ifu_axi_arvalid(ifu_axi_arvalid),
+		.ifu_axi_arready(ifu_axi_arready),
+		.ifu_axi_arid(ifu_axi_arid),
+		.ifu_axi_araddr(ifu_axi_araddr),
+		.ifu_axi_arregion(ifu_axi_arregion),
+		.ifu_axi_arlen(ifu_axi_arlen),
+		.ifu_axi_arsize(ifu_axi_arsize),
+		.ifu_axi_arburst(ifu_axi_arburst),
+		.ifu_axi_arlock(ifu_axi_arlock),
+		.ifu_axi_arcache(ifu_axi_arcache),
+		.ifu_axi_arprot(ifu_axi_arprot),
+		.ifu_axi_arqos(ifu_axi_arqos),
+		.ifu_axi_rvalid(ifu_axi_rvalid),
+		.ifu_axi_rready(ifu_axi_rready),
+		.ifu_axi_rid(ifu_axi_rid),
+		.ifu_axi_rdata(ifu_axi_rdata),
+		.ifu_axi_rresp(ifu_axi_rresp),
+		.ifu_bus_clk_en(ifu_bus_clk_en),
+		.dma_iccm_req(dma_iccm_req),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_sz(dma_mem_sz),
+		.dma_mem_write(dma_mem_write),
+		.dma_mem_wdata(dma_mem_wdata),
+		.dma_mem_tag(dma_mem_tag),
+		.iccm_dma_ecc_error(iccm_dma_ecc_error),
+		.iccm_dma_rvalid(iccm_dma_rvalid),
+		.iccm_dma_rdata(iccm_dma_rdata),
+		.iccm_dma_rtag(iccm_dma_rtag),
+		.iccm_ready(iccm_ready),
+		.ic_rw_addr(ic_rw_addr),
+		.ic_wr_en(ic_wr_en),
+		.ic_rd_en(ic_rd_en),
+		.ic_wr_data(ic_wr_data),
+		.ic_rd_data(ic_rd_data),
+		.ic_debug_rd_data(ic_debug_rd_data),
+		.ictag_debug_rd_data(ictag_debug_rd_data),
+		.ic_debug_wr_data(ic_debug_wr_data),
+		.ifu_ic_debug_rd_data(ifu_ic_debug_rd_data),
+		.ic_eccerr(ic_eccerr),
+		.ic_parerr(ic_parerr),
+		.ic_debug_addr(ic_debug_addr),
+		.ic_debug_rd_en(ic_debug_rd_en),
+		.ic_debug_wr_en(ic_debug_wr_en),
+		.ic_debug_tag_array(ic_debug_tag_array),
+		.ic_debug_way(ic_debug_way),
+		.ic_tag_valid(ic_tag_valid),
+		.ic_rd_hit(ic_rd_hit),
+		.ic_tag_perr(ic_tag_perr),
+		.iccm_rw_addr(iccm_rw_addr),
+		.iccm_wren(iccm_wren),
+		.iccm_rden(iccm_rden),
+		.iccm_wr_data(iccm_wr_data),
+		.iccm_wr_size(iccm_wr_size),
+		.iccm_rd_data(iccm_rd_data),
+		.iccm_rd_data_ecc(iccm_rd_data_ecc),
+		.ifu_fetch_val(ifu_fetch_val),
+		.ic_hit_f(ic_hit_f),
+		.ic_access_fault_f(ic_access_fault_f),
+		.ic_access_fault_type_f(ic_access_fault_type_f),
+		.iccm_rd_ecc_single_err(iccm_rd_ecc_single_err),
+		.iccm_rd_ecc_double_err(iccm_rd_ecc_double_err),
+		.ic_error_start(ic_error_start),
+		.ifu_async_error_start(ifu_async_error_start),
+		.iccm_dma_sb_error(iccm_dma_sb_error),
+		.ic_fetch_val_f(ic_fetch_val_f),
+		.ic_premux_data(ic_premux_data),
+		.ic_sel_premux_data(ic_sel_premux_data),
+		.dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid),
+		.iccm_buf_correct_ecc(iccm_buf_correct_ecc),
+		.iccm_correction_state(iccm_correction_state),
+		.scan_mode(scan_mode),
+		.ic_data_f(ic_data_f[31:0])
+	);
+endmodule
+module eb1_ifu_aln_ctl (
+	scan_mode,
+	rst_l,
+	clk,
+	active_clk,
+	ifu_async_error_start,
+	iccm_rd_ecc_double_err,
+	ic_access_fault_f,
+	ic_access_fault_type_f,
+	exu_flush_final,
+	dec_i0_decode_d,
+	ifu_fetch_data_f,
+	ifu_fetch_val,
+	ifu_fetch_pc,
+	ifu_i0_valid,
+	ifu_i0_icaf,
+	ifu_i0_icaf_type,
+	ifu_i0_icaf_second,
+	ifu_i0_dbecc,
+	ifu_i0_instr,
+	ifu_i0_pc,
+	ifu_i0_pc4,
+	ifu_fb_consume1,
+	ifu_fb_consume2,
+	ifu_bp_fghr_f,
+	ifu_bp_btb_target_f,
+	ifu_bp_poffset_f,
+	ifu_bp_fa_index_f,
+	ifu_bp_hist0_f,
+	ifu_bp_hist1_f,
+	ifu_bp_pc4_f,
+	ifu_bp_way_f,
+	ifu_bp_valid_f,
+	ifu_bp_ret_f,
+	i0_brp,
+	ifu_i0_bp_index,
+	ifu_i0_bp_fghr,
+	ifu_i0_bp_btag,
+	ifu_i0_fa_index,
+	ifu_pmu_instr_aligned,
+	ifu_i0_cinst
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire scan_mode;
+	input wire rst_l;
+	input wire clk;
+	input wire active_clk;
+	input wire ifu_async_error_start;
+	input wire [1:0] iccm_rd_ecc_double_err;
+	input wire [1:0] ic_access_fault_f;
+	input wire [1:0] ic_access_fault_type_f;
+	input wire exu_flush_final;
+	input wire dec_i0_decode_d;
+	input wire [31:0] ifu_fetch_data_f;
+	input wire [1:0] ifu_fetch_val;
+	input wire [31:1] ifu_fetch_pc;
+	output wire ifu_i0_valid;
+	output wire ifu_i0_icaf;
+	output wire [1:0] ifu_i0_icaf_type;
+	output wire ifu_i0_icaf_second;
+	output wire ifu_i0_dbecc;
+	output wire [31:0] ifu_i0_instr;
+	output wire [31:1] ifu_i0_pc;
+	output wire ifu_i0_pc4;
+	output wire ifu_fb_consume1;
+	output wire ifu_fb_consume2;
+	input wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f;
+	input wire [31:1] ifu_bp_btb_target_f;
+	input wire [11:0] ifu_bp_poffset_f;
+	input wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f;
+	input wire [1:0] ifu_bp_hist0_f;
+	input wire [1:0] ifu_bp_hist1_f;
+	input wire [1:0] ifu_bp_pc4_f;
+	input wire [1:0] ifu_bp_way_f;
+	input wire [1:0] ifu_bp_valid_f;
+	input wire [1:0] ifu_bp_ret_f;
+	output reg [50:0] i0_brp;
+	output wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index;
+	output wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr;
+	output wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag;
+	output reg [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index;
+	output wire ifu_pmu_instr_aligned;
+	output wire [15:0] ifu_i0_cinst;
+	wire ifvalid;
+	wire shift_f1_f0;
+	wire shift_f2_f0;
+	wire shift_f2_f1;
+	wire fetch_to_f0;
+	wire fetch_to_f1;
+	wire fetch_to_f2;
+	wire [1:0] f2val_in;
+	wire [1:0] f2val;
+	wire [1:0] f1val_in;
+	wire [1:0] f1val;
+	wire [1:0] f0val_in;
+	wire [1:0] f0val;
+	wire [1:0] sf1val;
+	wire [1:0] sf0val;
+	wire [31:0] aligndata;
+	wire first4B;
+	wire first2B;
+	wire [31:0] uncompress0;
+	wire i0_shift;
+	wire shift_2B;
+	wire shift_4B;
+	wire f1_shift_2B;
+	wire f2_valid;
+	wire sf1_valid;
+	wire sf0_valid;
+	wire [31:0] ifirst;
+	wire [1:0] alignval;
+	wire [31:1] firstpc;
+	wire [31:1] secondpc;
+	wire [11:0] f1poffset;
+	wire [11:0] f0poffset;
+	wire [pt[2236-:8] - 1:0] f1fghr;
+	wire [pt[2236-:8] - 1:0] f0fghr;
+	wire [1:0] f1hist1;
+	wire [1:0] f0hist1;
+	wire [1:0] f1hist0;
+	wire [1:0] f0hist0;
+	wire [(2 * $clog2(pt[2061-:14])) - 1:0] f0index;
+	wire [(2 * $clog2(pt[2061-:14])) - 1:0] f1index;
+	wire [(2 * $clog2(pt[2061-:14])) - 1:0] alignindex;
+	wire [1:0] f1ictype;
+	wire [1:0] f0ictype;
+	wire [1:0] f1pc4;
+	wire [1:0] f0pc4;
+	wire [1:0] f1ret;
+	wire [1:0] f0ret;
+	wire [1:0] f1way;
+	wire [1:0] f0way;
+	wire [1:0] f1brend;
+	wire [1:0] f0brend;
+	wire [1:0] alignbrend;
+	wire [1:0] alignpc4;
+	wire [1:0] alignret;
+	wire [1:0] alignway;
+	wire [1:0] alignhist1;
+	wire [1:0] alignhist0;
+	wire [1:1] alignfromf1;
+	reg i0_ends_f1;
+	reg i0_br_start_error;
+	wire [31:1] f1prett;
+	wire [31:1] f0prett;
+	wire [1:0] f1dbecc;
+	wire [1:0] f0dbecc;
+	wire [1:0] f1icaf;
+	wire [1:0] f0icaf;
+	wire [1:0] aligndbecc;
+	wire [1:0] alignicaf;
+	reg i0_brp_pc4;
+	wire [pt[2172-:9]:pt[2163-:6]] firstpc_hash;
+	wire [pt[2172-:9]:pt[2163-:6]] secondpc_hash;
+	wire first_legal;
+	wire [1:0] wrptr;
+	wire [1:0] wrptr_in;
+	wire [1:0] rdptr;
+	wire [1:0] rdptr_in;
+	wire [2:0] qwen;
+	wire [31:0] q2;
+	wire [31:0] q1;
+	wire [31:0] q0;
+	wire q2off_in;
+	wire q2off;
+	wire q1off_in;
+	wire q1off;
+	wire q0off_in;
+	wire q0off;
+	wire f0_shift_2B;
+	wire [31:0] q0eff;
+	wire [31:0] q0final;
+	wire q0ptr;
+	wire [1:0] q0sel;
+	wire [31:0] q1eff;
+	wire [15:0] q1final;
+	wire q1ptr;
+	wire [1:0] q1sel;
+	wire [2:0] qren;
+	wire consume_fb1;
+	wire consume_fb0;
+	wire [1:0] icaf_eff;
+	localparam BRDATA_SIZE = (pt[2130-:5] ? 16 + (($clog2(pt[2061-:14]) * 2) * pt[2120-:5]) : 2);
+	localparam BRDATA_WIDTH = (pt[2130-:5] ? 8 + ($clog2(pt[2061-:14]) * pt[2120-:5]) : 1);
+	wire [BRDATA_SIZE - 1:0] brdata_in;
+	wire [BRDATA_SIZE - 1:0] brdata2;
+	wire [BRDATA_SIZE - 1:0] brdata1;
+	wire [BRDATA_SIZE - 1:0] brdata0;
+	wire [BRDATA_SIZE - 1:0] brdata1eff;
+	wire [BRDATA_SIZE - 1:0] brdata0eff;
+	wire [BRDATA_SIZE - 1:0] brdata1final;
+	wire [BRDATA_SIZE - 1:0] brdata0final;
+	localparam MHI = 1 + (pt[2130-:5] * (43 + pt[2236-:8]));
+	localparam MSIZE = 2 + (pt[2130-:5] * (43 + pt[2236-:8]));
+	wire [MHI:0] misc_data_in;
+	wire [MHI:0] misc2;
+	wire [MHI:0] misc1;
+	wire [MHI:0] misc0;
+	wire [MHI:0] misc1eff;
+	wire [MHI:0] misc0eff;
+	wire [pt[2139-:9] - 1:0] firstbrtag_hash;
+	wire [pt[2139-:9] - 1:0] secondbrtag_hash;
+	wire error_stall_in;
+	wire error_stall;
+	assign error_stall_in = (error_stall | ifu_async_error_start) & ~exu_flush_final;
+	rvdff #(.WIDTH(7)) bundle1ff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din({wrptr_in[1:0], rdptr_in[1:0], q2off_in, q1off_in, q0off_in}),
+		.dout({wrptr[1:0], rdptr[1:0], q2off, q1off, q0off})
+	);
+	rvdffie #(
+		.WIDTH(7),
+		.OVERRIDE(1)
+	) bundle2ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din({error_stall_in, f2val_in[1:0], f1val_in[1:0], f0val_in[1:0]}),
+		.dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0]})
+	);
+	generate
+		if (pt[2130-:5] == 1) begin
+			rvdffe #(.WIDTH(BRDATA_SIZE)) brdata2ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[2]),
+				.din(brdata_in[BRDATA_SIZE - 1:0]),
+				.dout(brdata2[BRDATA_SIZE - 1:0])
+			);
+			rvdffe #(.WIDTH(BRDATA_SIZE)) brdata1ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[1]),
+				.din(brdata_in[BRDATA_SIZE - 1:0]),
+				.dout(brdata1[BRDATA_SIZE - 1:0])
+			);
+			rvdffe #(.WIDTH(BRDATA_SIZE)) brdata0ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[0]),
+				.din(brdata_in[BRDATA_SIZE - 1:0]),
+				.dout(brdata0[BRDATA_SIZE - 1:0])
+			);
+			rvdffe #(.WIDTH(MSIZE)) misc2ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[2]),
+				.din(misc_data_in[MHI:0]),
+				.dout(misc2[MHI:0])
+			);
+			rvdffe #(.WIDTH(MSIZE)) misc1ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[1]),
+				.din(misc_data_in[MHI:0]),
+				.dout(misc1[MHI:0])
+			);
+			rvdffe #(.WIDTH(MSIZE)) misc0ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(qwen[0]),
+				.din(misc_data_in[MHI:0]),
+				.dout(misc0[MHI:0])
+			);
+		end
+		else rvdffie #(.WIDTH((MSIZE * 3) + (BRDATA_SIZE * 3))) miscff(
+			.clk(clk),
+			.rst_l(rst_l),
+			.scan_mode(scan_mode),
+			.din({(qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE - 1:0]}), (qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE - 1:0]}), (qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE - 1:0]})}),
+			.dout({misc2[MHI:0], misc1[MHI:0], misc0[MHI:0], brdata2[BRDATA_SIZE - 1:0], brdata1[BRDATA_SIZE - 1:0], brdata0[BRDATA_SIZE - 1:0]})
+		);
+	endgenerate
+	wire [31:1] q2pc;
+	wire [31:1] q1pc;
+	wire [31:1] q0pc;
+	rvdffe #(.WIDTH(31)) q2pcff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[2]),
+		.din(ifu_fetch_pc[31:1]),
+		.dout(q2pc[31:1])
+	);
+	rvdffe #(.WIDTH(31)) q1pcff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[1]),
+		.din(ifu_fetch_pc[31:1]),
+		.dout(q1pc[31:1])
+	);
+	rvdffe #(.WIDTH(31)) q0pcff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[0]),
+		.din(ifu_fetch_pc[31:1]),
+		.dout(q0pc[31:1])
+	);
+	rvdffe #(.WIDTH(32)) q2ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[2]),
+		.din(ifu_fetch_data_f[31:0]),
+		.dout(q2[31:0])
+	);
+	rvdffe #(.WIDTH(32)) q1ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[1]),
+		.din(ifu_fetch_data_f[31:0]),
+		.dout(q1[31:0])
+	);
+	rvdffe #(.WIDTH(32)) q0ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.en(qwen[0]),
+		.din(ifu_fetch_data_f[31:0]),
+		.dout(q0[31:0])
+	);
+	assign qren[2:0] = {rdptr[1:0] == 2'b10, rdptr[1:0] == 2'b01, rdptr[1:0] == 2'b00};
+	assign qwen[2:0] = {(wrptr[1:0] == 2'b10) & ifvalid, (wrptr[1:0] == 2'b01) & ifvalid, (wrptr[1:0] == 2'b00) & ifvalid};
+	assign rdptr_in[1:0] = (((((({2 {(qren[0] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b01) | ({2 {(qren[1] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b10)) | ({2 {(qren[2] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b00)) | ({2 {(qren[0] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b10)) | ({2 {(qren[1] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b00)) | ({2 {(qren[2] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b01)) | ({2 {(~ifu_fb_consume1 & ~ifu_fb_consume2) & ~exu_flush_final}} & rdptr[1:0]);
+	assign wrptr_in[1:0] = ((({2 {qwen[0] & ~exu_flush_final}} & 2'b01) | ({2 {qwen[1] & ~exu_flush_final}} & 2'b10)) | ({2 {qwen[2] & ~exu_flush_final}} & 2'b00)) | ({2 {~ifvalid & ~exu_flush_final}} & wrptr[1:0]);
+	assign q2off_in = (((~qwen[2] & (rdptr[1:0] == 2'd2)) & (q2off | f0_shift_2B)) | ((~qwen[2] & (rdptr[1:0] == 2'd1)) & (q2off | f1_shift_2B))) | ((~qwen[2] & (rdptr[1:0] == 2'd0)) & q2off);
+	assign q1off_in = (((~qwen[1] & (rdptr[1:0] == 2'd1)) & (q1off | f0_shift_2B)) | ((~qwen[1] & (rdptr[1:0] == 2'd0)) & (q1off | f1_shift_2B))) | ((~qwen[1] & (rdptr[1:0] == 2'd2)) & q1off);
+	assign q0off_in = (((~qwen[0] & (rdptr[1:0] == 2'd0)) & (q0off | f0_shift_2B)) | ((~qwen[0] & (rdptr[1:0] == 2'd2)) & (q0off | f1_shift_2B))) | ((~qwen[0] & (rdptr[1:0] == 2'd1)) & q0off);
+	assign q0ptr = (((rdptr[1:0] == 2'b00) & q0off) | ((rdptr[1:0] == 2'b01) & q1off)) | ((rdptr[1:0] == 2'b10) & q2off);
+	assign q1ptr = (((rdptr[1:0] == 2'b00) & q1off) | ((rdptr[1:0] == 2'b01) & q2off)) | ((rdptr[1:0] == 2'b10) & q0off);
+	assign q0sel[1:0] = {q0ptr, ~q0ptr};
+	assign q1sel[1:0] = {q1ptr, ~q1ptr};
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign misc_data_in[MHI:0] = {ic_access_fault_type_f[1:0], ifu_bp_btb_target_f[31:1], ifu_bp_poffset_f[11:0], ifu_bp_fghr_f[pt[2236-:8] - 1:0]};
+		end
+		else assign misc_data_in[MHI:0] = {ic_access_fault_type_f[1:0]};
+	endgenerate
+	assign {misc1eff[MHI:0], misc0eff[MHI:0]} = (({MSIZE * 2 {qren[0]}} & {misc1[MHI:0], misc0[MHI:0]}) | ({MSIZE * 2 {qren[1]}} & {misc2[MHI:0], misc1[MHI:0]})) | ({MSIZE * 2 {qren[2]}} & {misc0[MHI:0], misc2[MHI:0]});
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign {f1ictype[1:0], f1prett[31:1], f1poffset[11:0], f1fghr[pt[2236-:8] - 1:0]} = misc1eff[MHI:0];
+			assign {f0ictype[1:0], f0prett[31:1], f0poffset[11:0], f0fghr[pt[2236-:8] - 1:0]} = misc0eff[MHI:0];
+			if (pt[2120-:5]) begin
+				assign brdata_in[BRDATA_SIZE - 1:0] = {ifu_bp_fa_index_f[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], iccm_rd_ecc_double_err[1], ic_access_fault_f[1], ifu_bp_hist1_f[1], ifu_bp_hist0_f[1], ifu_bp_pc4_f[1], ifu_bp_way_f[1], ifu_bp_valid_f[1], ifu_bp_ret_f[1], ifu_bp_fa_index_f[0+:$clog2(pt[2061-:14])], iccm_rd_ecc_double_err[0], ic_access_fault_f[0], ifu_bp_hist1_f[0], ifu_bp_hist0_f[0], ifu_bp_pc4_f[0], ifu_bp_way_f[0], ifu_bp_valid_f[0], ifu_bp_ret_f[0]};
+				assign {f0index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], f0dbecc[1], f0icaf[1], f0hist1[1], f0hist0[1], f0pc4[1], f0way[1], f0brend[1], f0ret[1], f0index[0+:$clog2(pt[2061-:14])], f0dbecc[0], f0icaf[0], f0hist1[0], f0hist0[0], f0pc4[0], f0way[0], f0brend[0], f0ret[0]} = brdata0final[BRDATA_SIZE - 1:0];
+				assign {f1index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], f1dbecc[1], f1icaf[1], f1hist1[1], f1hist0[1], f1pc4[1], f1way[1], f1brend[1], f1ret[1], f1index[0+:$clog2(pt[2061-:14])], f1dbecc[0], f1icaf[0], f1hist1[0], f1hist0[0], f1pc4[0], f1way[0], f1brend[0], f1ret[0]} = brdata1final[BRDATA_SIZE - 1:0];
+			end
+			else begin
+				assign brdata_in[BRDATA_SIZE - 1:0] = {iccm_rd_ecc_double_err[1], ic_access_fault_f[1], ifu_bp_hist1_f[1], ifu_bp_hist0_f[1], ifu_bp_pc4_f[1], ifu_bp_way_f[1], ifu_bp_valid_f[1], ifu_bp_ret_f[1], iccm_rd_ecc_double_err[0], ic_access_fault_f[0], ifu_bp_hist1_f[0], ifu_bp_hist0_f[0], ifu_bp_pc4_f[0], ifu_bp_way_f[0], ifu_bp_valid_f[0], ifu_bp_ret_f[0]};
+				assign {f0dbecc[1], f0icaf[1], f0hist1[1], f0hist0[1], f0pc4[1], f0way[1], f0brend[1], f0ret[1], f0dbecc[0], f0icaf[0], f0hist1[0], f0hist0[0], f0pc4[0], f0way[0], f0brend[0], f0ret[0]} = brdata0final[BRDATA_SIZE - 1:0];
+				assign {f1dbecc[1], f1icaf[1], f1hist1[1], f1hist0[1], f1pc4[1], f1way[1], f1brend[1], f1ret[1], f1dbecc[0], f1icaf[0], f1hist1[0], f1hist0[0], f1pc4[0], f1way[0], f1brend[0], f1ret[0]} = brdata1final[BRDATA_SIZE - 1:0];
+			end
+			assign {brdata1eff[BRDATA_SIZE - 1:0], brdata0eff[BRDATA_SIZE - 1:0]} = (({BRDATA_SIZE * 2 {qren[0]}} & {brdata1[BRDATA_SIZE - 1:0], brdata0[BRDATA_SIZE - 1:0]}) | ({BRDATA_SIZE * 2 {qren[1]}} & {brdata2[BRDATA_SIZE - 1:0], brdata1[BRDATA_SIZE - 1:0]})) | ({BRDATA_SIZE * 2 {qren[2]}} & {brdata0[BRDATA_SIZE - 1:0], brdata2[BRDATA_SIZE - 1:0]});
+			assign brdata0final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q0sel[0]}} & {brdata0eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q0sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata0eff[BRDATA_SIZE - 1:BRDATA_WIDTH]});
+			assign brdata1final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q1sel[0]}} & {brdata1eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q1sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata1eff[BRDATA_SIZE - 1:BRDATA_WIDTH]});
+		end
+		else begin
+			assign {f1ictype[1:0]} = misc1eff[MHI:0];
+			assign {f0ictype[1:0]} = misc0eff[MHI:0];
+			assign brdata_in[BRDATA_SIZE - 1:0] = {iccm_rd_ecc_double_err[1], ic_access_fault_f[1], iccm_rd_ecc_double_err[0], ic_access_fault_f[0]};
+			assign {f0dbecc[1], f0icaf[1], f0dbecc[0], f0icaf[0]} = brdata0final[BRDATA_SIZE - 1:0];
+			assign {f1dbecc[1], f1icaf[1], f1dbecc[0], f1icaf[0]} = brdata1final[BRDATA_SIZE - 1:0];
+			assign {brdata1eff[BRDATA_SIZE - 1:0], brdata0eff[BRDATA_SIZE - 1:0]} = (({BRDATA_SIZE * 2 {qren[0]}} & {brdata1[BRDATA_SIZE - 1:0], brdata0[BRDATA_SIZE - 1:0]}) | ({BRDATA_SIZE * 2 {qren[1]}} & {brdata2[BRDATA_SIZE - 1:0], brdata1[BRDATA_SIZE - 1:0]})) | ({BRDATA_SIZE * 2 {qren[2]}} & {brdata0[BRDATA_SIZE - 1:0], brdata2[BRDATA_SIZE - 1:0]});
+			assign brdata0final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q0sel[0]}} & {brdata0eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q0sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata0eff[BRDATA_SIZE - 1:BRDATA_WIDTH]});
+			assign brdata1final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q1sel[0]}} & {brdata1eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q1sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata1eff[BRDATA_SIZE - 1:BRDATA_WIDTH]});
+		end
+	endgenerate
+	assign f2_valid = f2val[0];
+	assign sf1_valid = sf1val[0];
+	assign sf0_valid = sf0val[0];
+	assign consume_fb0 = ~sf0val[0] & f0val[0];
+	assign consume_fb1 = ~sf1val[0] & f1val[0];
+	assign ifu_fb_consume1 = (consume_fb0 & ~consume_fb1) & ~exu_flush_final;
+	assign ifu_fb_consume2 = (consume_fb0 & consume_fb1) & ~exu_flush_final;
+	assign ifvalid = ifu_fetch_val[0];
+	assign shift_f1_f0 = ~sf0_valid & sf1_valid;
+	assign shift_f2_f0 = (~sf0_valid & ~sf1_valid) & f2_valid;
+	assign shift_f2_f1 = (~sf0_valid & sf1_valid) & f2_valid;
+	assign fetch_to_f0 = ((~sf0_valid & ~sf1_valid) & ~f2_valid) & ifvalid;
+	assign fetch_to_f1 = ((((~sf0_valid & ~sf1_valid) & f2_valid) & ifvalid) | (((~sf0_valid & sf1_valid) & ~f2_valid) & ifvalid)) | (((sf0_valid & ~sf1_valid) & ~f2_valid) & ifvalid);
+	assign fetch_to_f2 = (((~sf0_valid & sf1_valid) & f2_valid) & ifvalid) | (((sf0_valid & sf1_valid) & ~f2_valid) & ifvalid);
+	assign f2val_in[1:0] = ({2 {fetch_to_f2 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {((~fetch_to_f2 & ~shift_f2_f1) & ~shift_f2_f0) & ~exu_flush_final}} & f2val[1:0]);
+	assign sf1val[1:0] = ({2 {f1_shift_2B}} & {1'b0, f1val[1]}) | ({2 {~f1_shift_2B}} & f1val[1:0]);
+	assign f1val_in[1:0] = (({2 {fetch_to_f1 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {shift_f2_f1 & ~exu_flush_final}} & f2val[1:0])) | ({2 {((~fetch_to_f1 & ~shift_f2_f1) & ~shift_f1_f0) & ~exu_flush_final}} & sf1val[1:0]);
+	assign sf0val[1:0] = ({2 {shift_2B}} & {1'b0, f0val[1]}) | ({2 {~shift_2B & ~shift_4B}} & f0val[1:0]);
+	assign f0val_in[1:0] = ((({2 {fetch_to_f0 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {shift_f2_f0 & ~exu_flush_final}} & f2val[1:0])) | ({2 {shift_f1_f0 & ~exu_flush_final}} & sf1val[1:0])) | ({2 {((~fetch_to_f0 & ~shift_f2_f0) & ~shift_f1_f0) & ~exu_flush_final}} & sf0val[1:0]);
+	assign {q1eff[31:0], q0eff[31:0]} = (({64 {qren[0]}} & {q1[31:0], q0[31:0]}) | ({64 {qren[1]}} & {q2[31:0], q1[31:0]})) | ({64 {qren[2]}} & {q0[31:0], q2[31:0]});
+	assign q0final[31:0] = ({32 {q0sel[0]}} & {q0eff[31:0]}) | ({32 {q0sel[1]}} & {16'b0000000000000000, q0eff[31:16]});
+	assign q1final[15:0] = ({16 {q1sel[0]}} & q1eff[15:0]) | ({16 {q1sel[1]}} & q1eff[31:16]);
+	wire [31:1] q0pceff;
+	wire [31:1] q0pcfinal;
+	wire [31:1] q1pceff;
+	assign {q1pceff[31:1], q0pceff[31:1]} = (({62 {qren[0]}} & {q1pc[31:1], q0pc[31:1]}) | ({62 {qren[1]}} & {q2pc[31:1], q1pc[31:1]})) | ({62 {qren[2]}} & {q0pc[31:1], q2pc[31:1]});
+	assign q0pcfinal[31:1] = ({31 {q0sel[0]}} & q0pceff[31:1]) | ({31 {q0sel[1]}} & (q0pceff[31:1] + 31'd1));
+	assign aligndata[31:0] = ({32 {f0val[1]}} & {q0final[31:0]}) | ({32 {~f0val[1] & f0val[0]}} & {q1final[15:0], q0final[15:0]});
+	assign alignval[1:0] = ({2 {f0val[1]}} & 2'b11) | ({2 {~f0val[1] & f0val[0]}} & {f1val[0], 1'b1});
+	assign alignicaf[1:0] = ({2 {f0val[1]}} & f0icaf[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1icaf[0], f0icaf[0]});
+	assign aligndbecc[1:0] = ({2 {f0val[1]}} & f0dbecc[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1dbecc[0], f0dbecc[0]});
+	generate
+		if (pt[2130-:5] == 1) begin
+			assign alignbrend[1:0] = ({2 {f0val[1]}} & f0brend[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1brend[0], f0brend[0]});
+			assign alignpc4[1:0] = ({2 {f0val[1]}} & f0pc4[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1pc4[0], f0pc4[0]});
+			if (pt[2120-:5]) begin
+				assign alignindex[0+:$clog2(pt[2061-:14])] = f0index[0+:$clog2(pt[2061-:14])];
+				assign alignindex[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] = (f0val[1] ? f0index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] : f1index[0+:$clog2(pt[2061-:14])]);
+			end
+			assign alignret[1:0] = ({2 {f0val[1]}} & f0ret[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1ret[0], f0ret[0]});
+			assign alignway[1:0] = ({2 {f0val[1]}} & f0way[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1way[0], f0way[0]});
+			assign alignhist1[1:0] = ({2 {f0val[1]}} & f0hist1[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1hist1[0], f0hist1[0]});
+			assign alignhist0[1:0] = ({2 {f0val[1]}} & f0hist0[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1hist0[0], f0hist0[0]});
+			assign secondpc[31:1] = ({31 {f0val[1]}} & (q0pceff[31:1] + 31'd1)) | ({31 {~f0val[1] & f0val[0]}} & q1pceff[31:1]);
+			assign firstpc[31:1] = q0pcfinal[31:1];
+		end
+	endgenerate
+	assign alignfromf1[1] = ~f0val[1] & f0val[0];
+	assign ifu_i0_pc[31:1] = q0pcfinal[31:1];
+	assign ifu_i0_pc4 = first4B;
+	assign ifu_i0_cinst[15:0] = aligndata[15:0];
+	assign first4B = aligndata[1:0] == 2'b11;
+	assign first2B = ~first4B;
+	assign ifu_i0_valid = (first4B & alignval[1]) | (first2B & alignval[0]);
+	assign ifu_i0_icaf = (first4B & |alignicaf[1:0]) | (first2B & alignicaf[0]);
+	assign ifu_i0_icaf_type[1:0] = ((((first4B & ~f0val[1]) & f0val[0]) & ~alignicaf[0]) & ~aligndbecc[0] ? f1ictype[1:0] : f0ictype[1:0]);
+	assign icaf_eff[1:0] = alignicaf[1:0] | aligndbecc[1:0];
+	assign ifu_i0_icaf_second = (first4B & ~icaf_eff[0]) & icaf_eff[1];
+	assign ifu_i0_dbecc = (first4B & |aligndbecc[1:0]) | (first2B & aligndbecc[0]);
+	assign ifirst[31:0] = aligndata[31:0];
+	assign ifu_i0_instr[31:0] = ({32 {first4B & alignval[1]}} & ifirst[31:0]) | ({32 {first2B & alignval[0]}} & uncompress0[31:0]);
+	generate
+		if (pt[2130-:5] == 1) begin
+			eb1_btb_addr_hash #(.pt(pt)) firsthash(
+				.pc(firstpc[pt[2079-:9]:pt[2106-:9]]),
+				.hash(firstpc_hash[pt[2172-:9]:pt[2163-:6]])
+			);
+			eb1_btb_addr_hash #(.pt(pt)) secondhash(
+				.pc(secondpc[pt[2079-:9]:pt[2106-:9]]),
+				.hash(secondpc_hash[pt[2172-:9]:pt[2163-:6]])
+			);
+			if (pt[2120-:5]) begin
+				assign firstbrtag_hash = firstpc;
+				assign secondbrtag_hash = secondpc;
+			end
+			else if (pt[2144-:5]) begin : btbfold
+				eb1_btb_tag_hash_fold #(.pt(pt)) first_brhash(
+					.pc(firstpc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]),
+					.hash(firstbrtag_hash[pt[2139-:9] - 1:0])
+				);
+				eb1_btb_tag_hash_fold #(.pt(pt)) second_brhash(
+					.pc(secondpc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]),
+					.hash(secondbrtag_hash[pt[2139-:9] - 1:0])
+				);
+			end
+			else begin
+				eb1_btb_tag_hash #(.pt(pt)) first_brhash(
+					.pc(firstpc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]),
+					.hash(firstbrtag_hash[pt[2139-:9] - 1:0])
+				);
+				eb1_btb_tag_hash #(.pt(pt)) second_brhash(
+					.pc(secondpc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]),
+					.hash(secondbrtag_hash[pt[2139-:9] - 1:0])
+				);
+			end
+			always @(*) begin
+				i0_brp = {51 {1'sb0}};
+				i0_br_start_error = (first4B & alignval[1]) & alignbrend[0];
+				i0_brp[50] = ((first2B & alignbrend[0]) | (first4B & alignbrend[1])) | i0_br_start_error;
+				i0_brp_pc4 = (first2B & alignpc4[0]) | (first4B & alignpc4[1]);
+				i0_brp[0] = (first2B & alignret[0]) | (first4B & alignret[1]);
+				i0_brp[1] = (first2B | alignbrend[0] ? alignway[0] : alignway[1]);
+				i0_brp[37] = (first2B & alignhist1[0]) | (first4B & alignhist1[1]);
+				i0_brp[36] = (first2B & alignhist0[0]) | (first4B & alignhist0[1]);
+				i0_ends_f1 = first4B & alignfromf1[1];
+				i0_brp[49:38] = (i0_ends_f1 ? f1poffset[11:0] : f0poffset[11:0]);
+				i0_brp[32:2] = (i0_ends_f1 ? f1prett[31:1] : f0prett[31:1]);
+				i0_brp[34] = i0_br_start_error;
+				i0_brp[33] = (first2B | alignbrend[0] ? firstpc[1] : secondpc[1]);
+				i0_brp[35] = ((i0_brp[50] & i0_brp_pc4) & first2B) | ((i0_brp[50] & ~i0_brp_pc4) & first4B);
+				if (pt[2120-:5])
+					ifu_i0_fa_index = (first2B | alignbrend[0] ? alignindex[0+:$clog2(pt[2061-:14])] : alignindex[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])]);
+				else
+					ifu_i0_fa_index = {$clog2(pt[2061-:14]) {1'sb0}};
+			end
+			assign ifu_i0_bp_index[pt[2172-:9]:pt[2163-:6]] = (first2B | alignbrend[0] ? firstpc_hash[pt[2172-:9]:pt[2163-:6]] : secondpc_hash[pt[2172-:9]:pt[2163-:6]]);
+			assign ifu_i0_bp_fghr[pt[2236-:8] - 1:0] = (i0_ends_f1 ? f1fghr[pt[2236-:8] - 1:0] : f0fghr[pt[2236-:8] - 1:0]);
+			assign ifu_i0_bp_btag[pt[2139-:9] - 1:0] = (first2B | alignbrend[0] ? firstbrtag_hash[pt[2139-:9] - 1:0] : secondbrtag_hash[pt[2139-:9] - 1:0]);
+		end
+		else begin
+			wire [51:1] sv2v_tmp_B43E9;
+			assign sv2v_tmp_B43E9 = {51 {1'sb0}};
+			always @(*) i0_brp = sv2v_tmp_B43E9;
+			assign ifu_i0_bp_index = {(pt[2172-:9] >= pt[2163-:6] ? (pt[2172-:9] - pt[2163-:6]) + 1 : (pt[2163-:6] - pt[2172-:9]) + 1) {1'sb0}};
+			assign ifu_i0_bp_fghr = {pt[2236-:8] {1'sb0}};
+			assign ifu_i0_bp_btag = {pt[2139-:9] {1'sb0}};
+		end
+	endgenerate
+	eb1_ifu_compress_ctl #(.pt(pt)) compress0(
+		.din((first2B ? aligndata[15:0] : {16 {1'sb0}})),
+		.dout(uncompress0[31:0])
+	);
+	assign i0_shift = dec_i0_decode_d & ~error_stall;
+	assign ifu_pmu_instr_aligned = i0_shift;
+	assign shift_2B = i0_shift & first2B;
+	assign shift_4B = i0_shift & first4B;
+	assign f0_shift_2B = (shift_2B & f0val[0]) | ((shift_4B & f0val[0]) & ~f0val[1]);
+	assign f1_shift_2B = (f0val[0] & ~f0val[1]) & shift_4B;
+endmodule
+module eb1_ifu_bp_ctl (
+	clk,
+	rst_l,
+	ic_hit_f,
+	ifc_fetch_addr_f,
+	ifc_fetch_req_f,
+	dec_tlu_br0_r_pkt,
+	exu_i0_br_fghr_r,
+	exu_i0_br_index_r,
+	dec_fa_error_index,
+	dec_tlu_flush_lower_wb,
+	dec_tlu_flush_leak_one_wb,
+	dec_tlu_bpred_disable,
+	exu_mp_pkt,
+	exu_mp_eghr,
+	exu_mp_fghr,
+	exu_mp_index,
+	exu_mp_btag,
+	exu_flush_final,
+	ifu_bp_hit_taken_f,
+	ifu_bp_btb_target_f,
+	ifu_bp_inst_mask_f,
+	ifu_bp_fghr_f,
+	ifu_bp_way_f,
+	ifu_bp_ret_f,
+	ifu_bp_hist1_f,
+	ifu_bp_hist0_f,
+	ifu_bp_pc4_f,
+	ifu_bp_valid_f,
+	ifu_bp_poffset_f,
+	ifu_bp_fa_index_f,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire ic_hit_f;
+	input wire [31:1] ifc_fetch_addr_f;
+	input wire ifc_fetch_req_f;
+	input wire [6:0] dec_tlu_br0_r_pkt;
+	input wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r;
+	input wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r;
+	input wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index;
+	input wire dec_tlu_flush_lower_wb;
+	input wire dec_tlu_flush_leak_one_wb;
+	input wire dec_tlu_bpred_disable;
+	input wire [55:0] exu_mp_pkt;
+	input wire [pt[2236-:8] - 1:0] exu_mp_eghr;
+	input wire [pt[2236-:8] - 1:0] exu_mp_fghr;
+	input wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index;
+	input wire [pt[2139-:9] - 1:0] exu_mp_btag;
+	input wire exu_flush_final;
+	output wire ifu_bp_hit_taken_f;
+	output wire [31:1] ifu_bp_btb_target_f;
+	output wire ifu_bp_inst_mask_f;
+	output wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f;
+	output wire [1:0] ifu_bp_way_f;
+	output wire [1:0] ifu_bp_ret_f;
+	output wire [1:0] ifu_bp_hist1_f;
+	output wire [1:0] ifu_bp_hist0_f;
+	output wire [1:0] ifu_bp_pc4_f;
+	output wire [1:0] ifu_bp_valid_f;
+	output wire [11:0] ifu_bp_poffset_f;
+	output wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f;
+	input wire scan_mode;
+	localparam BTB_DWIDTH = (pt[2047-:9] + pt[2139-:9]) + 5;
+	function automatic signed [31:0] sv2v_cast_32_signed;
+		input reg signed [31:0] inp;
+		sv2v_cast_32_signed = inp;
+	endfunction
+	localparam BTB_DWIDTH_TOP = (sv2v_cast_32_signed(pt[2047-:9]) + sv2v_cast_32_signed(pt[2139-:9])) + 4;
+	localparam BTB_FA_INDEX = $clog2(pt[2061-:14]) - 1;
+	localparam FA_CMP_LOWER = $clog2(pt[1095-:11]);
+	localparam FA_TAG_END_UPPER = ((5 + sv2v_cast_32_signed(pt[2047-:9])) + FA_CMP_LOWER) - 1;
+	localparam FA_TAG_START_LOWER = (3 + sv2v_cast_32_signed(pt[2047-:9])) + FA_CMP_LOWER;
+	localparam FA_TAG_END_LOWER = 5 + sv2v_cast_32_signed(pt[2047-:9]);
+	localparam TAG_START = BTB_DWIDTH - 1;
+	localparam PC4 = 4;
+	localparam BOFF = 3;
+	localparam CALL = 2;
+	localparam RET = 1;
+	localparam BV = 0;
+	localparam LRU_SIZE = pt[2157-:13];
+	localparam NUM_BHT_LOOP = (pt[2256-:15] > 16 ? 16 : pt[2256-:15]);
+	localparam NUM_BHT_LOOP_INNER_HI = (pt[2256-:15] > 16 ? pt[2262-:6] + 3 : pt[2270-:8]);
+	localparam NUM_BHT_LOOP_OUTER_LO = (pt[2256-:15] > 16 ? pt[2262-:6] + 4 : pt[2262-:6]);
+	localparam BHT_NO_ADDR_MATCH = pt[2256-:15] <= 16;
+	wire exu_mp_valid_write;
+	wire exu_mp_ataken;
+	wire exu_mp_valid;
+	wire exu_mp_boffset;
+	wire exu_mp_pc4;
+	wire exu_mp_call;
+	wire exu_mp_ret;
+	wire exu_mp_ja;
+	wire [1:0] exu_mp_hist;
+	wire [11:0] exu_mp_tgt;
+	wire [pt[2172-:9]:pt[2163-:6]] exu_mp_addr;
+	wire dec_tlu_br0_v_wb;
+	wire [1:0] dec_tlu_br0_hist_wb;
+	wire [pt[2172-:9]:pt[2163-:6]] dec_tlu_br0_addr_wb;
+	wire dec_tlu_br0_error_wb;
+	wire dec_tlu_br0_start_error_wb;
+	wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_wb;
+	wire use_mp_way;
+	wire use_mp_way_p1;
+	wire [(pt[31-:8] * 32) - 1:0] rets_out;
+	wire [(pt[31-:8] * 32) - 1:0] rets_in;
+	wire [pt[31-:8] - 1:0] rsenable;
+	wire [11:0] btb_rd_tgt_f;
+	wire btb_rd_pc4_f;
+	wire btb_rd_call_f;
+	wire btb_rd_ret_f;
+	wire [1:1] bp_total_branch_offset_f;
+	wire [31:1] bp_btb_target_adder_f;
+	wire [31:1] bp_rs_call_target_f;
+	wire rs_push;
+	wire rs_pop;
+	wire rs_hold;
+	wire [pt[2172-:9]:pt[2163-:6]] btb_rd_addr_p1_f;
+	wire [pt[2172-:9]:pt[2163-:6]] btb_wr_addr;
+	wire [pt[2172-:9]:pt[2163-:6]] btb_rd_addr_f;
+	wire [pt[2139-:9] - 1:0] btb_wr_tag;
+	wire [pt[2139-:9] - 1:0] fetch_rd_tag_f;
+	wire [pt[2139-:9] - 1:0] fetch_rd_tag_p1_f;
+	wire [BTB_DWIDTH - 1:0] btb_wr_data;
+	wire btb_wr_en_way0;
+	wire btb_wr_en_way1;
+	wire dec_tlu_error_wb;
+	wire btb_valid;
+	wire dec_tlu_br0_middle_wb;
+	wire [pt[2172-:9]:pt[2163-:6]] btb_error_addr_wb;
+	wire branch_error_collision_f;
+	wire fetch_mp_collision_f;
+	wire branch_error_collision_p1_f;
+	wire fetch_mp_collision_p1_f;
+	wire branch_error_bank_conflict_f;
+	wire [pt[2236-:8] - 1:0] merged_ghr;
+	wire [pt[2236-:8] - 1:0] fghr_ns;
+	wire [pt[2236-:8] - 1:0] fghr;
+	wire [1:0] num_valids;
+	wire [LRU_SIZE - 1:0] btb_lru_b0_f;
+	wire [LRU_SIZE - 1:0] btb_lru_b0_hold;
+	wire [LRU_SIZE - 1:0] btb_lru_b0_ns;
+	wire [LRU_SIZE - 1:0] fetch_wrindex_dec;
+	wire [LRU_SIZE - 1:0] fetch_wrindex_p1_dec;
+	wire [LRU_SIZE - 1:0] fetch_wrlru_b0;
+	wire [LRU_SIZE - 1:0] fetch_wrlru_p1_b0;
+	wire [LRU_SIZE - 1:0] mp_wrindex_dec;
+	wire [LRU_SIZE - 1:0] mp_wrlru_b0;
+	wire btb_lru_rd_f;
+	wire btb_lru_rd_p1_f;
+	wire lru_update_valid_f;
+	wire tag_match_way0_f;
+	wire tag_match_way1_f;
+	wire [1:0] way_raw;
+	wire [1:0] bht_dir_f;
+	wire [1:0] btb_sel_f;
+	wire [1:0] wayhit_f;
+	wire [1:0] vwayhit_f;
+	wire [1:0] wayhit_p1_f;
+	wire [1:0] bht_valid_f;
+	wire [1:0] bht_force_taken_f;
+	wire leak_one_f;
+	wire leak_one_f_d1;
+	wire [(LRU_SIZE * BTB_DWIDTH) - 1:0] btb_bank0_rd_data_way0_out;
+	wire [(LRU_SIZE * BTB_DWIDTH) - 1:0] btb_bank0_rd_data_way1_out;
+	reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way0_f;
+	reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way1_f;
+	reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way0_p1_f;
+	reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way1_p1_f;
+	reg [BTB_DWIDTH - 1:0] btb_vbank0_rd_data_f;
+	reg [BTB_DWIDTH - 1:0] btb_vbank1_rd_data_f;
+	wire final_h;
+	wire btb_fg_crossing_f;
+	wire middle_of_bank;
+	wire [1:0] bht_vbank0_rd_data_f;
+	wire [1:0] bht_vbank1_rd_data_f;
+	wire branch_error_bank_conflict_p1_f;
+	wire tag_match_way0_p1_f;
+	wire tag_match_way1_p1_f;
+	wire [1:0] btb_vlru_rd_f;
+	wire [1:0] fetch_start_f;
+	wire [1:0] tag_match_vway1_expanded_f;
+	wire [1:0] tag_match_way0_expanded_p1_f;
+	wire [1:0] tag_match_way1_expanded_p1_f;
+	wire [31:2] fetch_addr_p1_f;
+	wire exu_mp_way;
+	wire exu_mp_way_f;
+	wire dec_tlu_br0_way_wb;
+	wire dec_tlu_way_wb;
+	wire [BTB_DWIDTH - 1:0] btb_bank0e_rd_data_f;
+	wire [BTB_DWIDTH - 1:0] btb_bank0e_rd_data_p1_f;
+	wire [BTB_DWIDTH - 1:0] btb_bank0o_rd_data_f;
+	wire [1:0] tag_match_way0_expanded_f;
+	wire [1:0] tag_match_way1_expanded_f;
+	reg [1:0] bht_bank0_rd_data_f;
+	reg [1:0] bht_bank1_rd_data_f;
+	reg [1:0] bht_bank0_rd_data_p1_f;
+	genvar j;
+	genvar i;
+	assign exu_mp_valid = exu_mp_pkt[55] & ~leak_one_f;
+	assign exu_mp_boffset = exu_mp_pkt[53];
+	assign exu_mp_pc4 = exu_mp_pkt[52];
+	assign exu_mp_call = exu_mp_pkt[34];
+	assign exu_mp_ret = exu_mp_pkt[31];
+	assign exu_mp_ja = exu_mp_pkt[33];
+	assign exu_mp_way = exu_mp_pkt[32];
+	assign exu_mp_hist[1:0] = exu_mp_pkt[51:50];
+	assign exu_mp_tgt[11:0] = exu_mp_pkt[49:38];
+	assign exu_mp_addr[pt[2172-:9]:pt[2163-:6]] = exu_mp_index[pt[2172-:9]:pt[2163-:6]];
+	assign exu_mp_ataken = exu_mp_pkt[54];
+	assign dec_tlu_br0_v_wb = dec_tlu_br0_r_pkt[6];
+	assign dec_tlu_br0_hist_wb[1:0] = dec_tlu_br0_r_pkt[5:4];
+	assign dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]] = exu_i0_br_index_r[pt[2172-:9]:pt[2163-:6]];
+	assign dec_tlu_br0_error_wb = dec_tlu_br0_r_pkt[3];
+	assign dec_tlu_br0_middle_wb = dec_tlu_br0_r_pkt[0];
+	assign dec_tlu_br0_way_wb = dec_tlu_br0_r_pkt[1];
+	assign dec_tlu_br0_start_error_wb = dec_tlu_br0_r_pkt[2];
+	assign exu_i0_br_fghr_wb[pt[2236-:8] - 1:0] = exu_i0_br_fghr_r[pt[2236-:8] - 1:0];
+	eb1_btb_addr_hash #(.pt(pt)) f1hash(
+		.pc(ifc_fetch_addr_f[pt[2079-:9]:pt[2106-:9]]),
+		.hash(btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]])
+	);
+	assign fetch_addr_p1_f[31:2] = ifc_fetch_addr_f[31:2] + 30'b000000000000000000000000000001;
+	eb1_btb_addr_hash #(.pt(pt)) f1hash_p1(
+		.pc(fetch_addr_p1_f[pt[2079-:9]:pt[2106-:9]]),
+		.hash(btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]])
+	);
+	assign btb_sel_f[1] = ~bht_dir_f[0];
+	assign btb_sel_f[0] = bht_dir_f[0];
+	assign fetch_start_f[1:0] = {ifc_fetch_addr_f[1], ~ifc_fetch_addr_f[1]};
+	assign branch_error_collision_f = dec_tlu_error_wb & (btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]);
+	assign branch_error_collision_p1_f = dec_tlu_error_wb & (btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]);
+	assign branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb;
+	assign branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb;
+	assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);
+	wire exu_flush_final_d1;
+	generate
+		if (!pt[2120-:5]) begin
+			assign fetch_mp_collision_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == fetch_rd_tag_f[pt[2139-:9] - 1:0]) & exu_mp_valid) & ifc_fetch_req_f) & (exu_mp_addr[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]);
+			assign fetch_mp_collision_p1_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]) & exu_mp_valid) & ifc_fetch_req_f) & (exu_mp_addr[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]);
+			assign tag_match_way0_f = (((btb_bank0_rd_data_way0_f[BV] & (btb_bank0_rd_data_way0_f[TAG_START:17] == fetch_rd_tag_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_f)) & ifc_fetch_req_f) & ~leak_one_f;
+			assign tag_match_way1_f = (((btb_bank0_rd_data_way1_f[BV] & (btb_bank0_rd_data_way1_f[TAG_START:17] == fetch_rd_tag_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_f)) & ifc_fetch_req_f) & ~leak_one_f;
+			assign tag_match_way0_p1_f = (((btb_bank0_rd_data_way0_p1_f[BV] & (btb_bank0_rd_data_way0_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f)) & ifc_fetch_req_f) & ~leak_one_f;
+			assign tag_match_way1_p1_f = (((btb_bank0_rd_data_way1_p1_f[BV] & (btb_bank0_rd_data_way1_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f)) & ifc_fetch_req_f) & ~leak_one_f;
+			assign tag_match_way0_expanded_f[1:0] = {tag_match_way0_f & (btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4]), tag_match_way0_f & ~(btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4])};
+			assign tag_match_way1_expanded_f[1:0] = {tag_match_way1_f & (btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4]), tag_match_way1_f & ~(btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4])};
+			assign tag_match_way0_expanded_p1_f[1:0] = {tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4]), tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4])};
+			assign tag_match_way1_expanded_p1_f[1:0] = {tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4]), tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4])};
+			assign wayhit_f[1:0] = tag_match_way0_expanded_f[1:0] | tag_match_way1_expanded_f[1:0];
+			assign wayhit_p1_f[1:0] = tag_match_way0_expanded_p1_f[1:0] | tag_match_way1_expanded_p1_f[1:0];
+			assign btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_f[1]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_f[1]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0]);
+			assign btb_bank0e_rd_data_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_f[0]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_f[0]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0]);
+			assign btb_bank0e_rd_data_p1_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_p1_f[0]}} & btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_p1_f[0]}} & btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0]);
+			wire [BTB_DWIDTH:1] sv2v_tmp_F09CF;
+			assign sv2v_tmp_F09CF = ({17 + pt[2139-:9] {fetch_start_f[0]}} & btb_bank0e_rd_data_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {fetch_start_f[1]}} & btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0]);
+			always @(*) btb_vbank0_rd_data_f[BTB_DWIDTH - 1:0] = sv2v_tmp_F09CF;
+			wire [BTB_DWIDTH:1] sv2v_tmp_BEF15;
+			assign sv2v_tmp_BEF15 = ({17 + pt[2139-:9] {fetch_start_f[0]}} & btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {fetch_start_f[1]}} & btb_bank0e_rd_data_p1_f[BTB_DWIDTH - 1:0]);
+			always @(*) btb_vbank1_rd_data_f[BTB_DWIDTH - 1:0] = sv2v_tmp_BEF15;
+			assign way_raw[1:0] = tag_match_vway1_expanded_f[1:0] | (~vwayhit_f[1:0] & btb_vlru_rd_f[1:0]);
+			assign mp_wrindex_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << exu_mp_addr[pt[2172-:9]:pt[2163-:6]];
+			assign fetch_wrindex_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]];
+			assign fetch_wrindex_p1_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]];
+			assign mp_wrlru_b0[LRU_SIZE - 1:0] = mp_wrindex_dec[LRU_SIZE - 1:0] & {LRU_SIZE {exu_mp_valid}};
+			assign btb_lru_b0_hold[LRU_SIZE - 1:0] = ~mp_wrlru_b0[LRU_SIZE - 1:0] & ~fetch_wrlru_b0[LRU_SIZE - 1:0];
+			assign use_mp_way = fetch_mp_collision_f;
+			assign use_mp_way_p1 = fetch_mp_collision_p1_f;
+			assign lru_update_valid_f = ((vwayhit_f[0] | vwayhit_f[1]) & ifc_fetch_req_f) & ~leak_one_f;
+			assign fetch_wrlru_b0[LRU_SIZE - 1:0] = fetch_wrindex_dec[LRU_SIZE - 1:0] & {LRU_SIZE {lru_update_valid_f}};
+			assign fetch_wrlru_p1_b0[LRU_SIZE - 1:0] = fetch_wrindex_p1_dec[LRU_SIZE - 1:0] & {LRU_SIZE {lru_update_valid_f}};
+			assign btb_lru_b0_ns[LRU_SIZE - 1:0] = (((btb_lru_b0_hold[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0]) | (mp_wrlru_b0[LRU_SIZE - 1:0] & {LRU_SIZE {~exu_mp_way}})) | (fetch_wrlru_b0[LRU_SIZE - 1:0] & {LRU_SIZE {tag_match_way0_f}})) | (fetch_wrlru_p1_b0[LRU_SIZE - 1:0] & {LRU_SIZE {tag_match_way0_p1_f}});
+			assign btb_lru_rd_f = (use_mp_way ? exu_mp_way_f : |(fetch_wrindex_dec[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0]));
+			assign btb_lru_rd_p1_f = (use_mp_way_p1 ? exu_mp_way_f : |(fetch_wrindex_p1_dec[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0]));
+			assign btb_vlru_rd_f[1:0] = ({2 {fetch_start_f[0]}} & {btb_lru_rd_f, btb_lru_rd_f}) | ({2 {fetch_start_f[1]}} & {btb_lru_rd_p1_f, btb_lru_rd_f});
+			assign tag_match_vway1_expanded_f[1:0] = ({2 {fetch_start_f[0]}} & {tag_match_way1_expanded_f[1:0]}) | ({2 {fetch_start_f[1]}} & {tag_match_way1_expanded_p1_f[0], tag_match_way1_expanded_f[1]});
+			rvdffe #(.WIDTH(LRU_SIZE)) btb_lru_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(ifc_fetch_req_f | exu_mp_valid),
+				.din(btb_lru_b0_ns[LRU_SIZE - 1:0]),
+				.dout(btb_lru_b0_f[LRU_SIZE - 1:0])
+			);
+		end
+	endgenerate
+	wire eoc_near;
+	wire eoc_mask;
+	assign eoc_near = &ifc_fetch_addr_f[pt[1182-:8]:3];
+	assign eoc_mask = ~eoc_near | |(~ifc_fetch_addr_f[2:1]);
+	wire [16:1] btb_sel_data_f;
+	assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];
+	assign btb_rd_pc4_f = btb_sel_data_f[4];
+	assign btb_rd_call_f = btb_sel_data_f[2];
+	assign btb_rd_ret_f = btb_sel_data_f[1];
+	assign btb_sel_data_f[16:1] = ({16 {btb_sel_f[1]}} & btb_vbank1_rd_data_f[16:1]) | ({16 {btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]);
+	wire [1:0] hist0_raw;
+	wire [1:0] hist1_raw;
+	wire [1:0] pc4_raw;
+	wire [1:0] pret_raw;
+	assign ifu_bp_hit_taken_f = ((|(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f) & ~leak_one_f_d1) & ~dec_tlu_bpred_disable;
+	assign bht_force_taken_f[1:0] = {btb_vbank1_rd_data_f[CALL] | btb_vbank1_rd_data_f[RET], btb_vbank0_rd_data_f[CALL] | btb_vbank0_rd_data_f[RET]};
+	assign bht_valid_f[1:0] = vwayhit_f[1:0];
+	assign bht_vbank0_rd_data_f[1:0] = ({2 {fetch_start_f[0]}} & bht_bank0_rd_data_f[1:0]) | ({2 {fetch_start_f[1]}} & bht_bank1_rd_data_f[1:0]);
+	assign bht_vbank1_rd_data_f[1:0] = ({2 {fetch_start_f[0]}} & bht_bank1_rd_data_f[1:0]) | ({2 {fetch_start_f[1]}} & bht_bank0_rd_data_p1_f[1:0]);
+	assign bht_dir_f[1:0] = {(bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]) & bht_valid_f[1], (bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]) & bht_valid_f[0]};
+	assign ifu_bp_inst_mask_f = (ifu_bp_hit_taken_f & btb_sel_f[1]) | ~ifu_bp_hit_taken_f;
+	assign hist1_raw[1:0] = bht_force_taken_f[1:0] | {bht_vbank1_rd_data_f[1], bht_vbank0_rd_data_f[1]};
+	assign hist0_raw[1:0] = {bht_vbank1_rd_data_f[0], bht_vbank0_rd_data_f[0]};
+	assign pc4_raw[1:0] = {vwayhit_f[1] & btb_vbank1_rd_data_f[PC4], vwayhit_f[0] & btb_vbank0_rd_data_f[PC4]};
+	assign pret_raw[1:0] = {(vwayhit_f[1] & ~btb_vbank1_rd_data_f[CALL]) & btb_vbank1_rd_data_f[RET], (vwayhit_f[0] & ~btb_vbank0_rd_data_f[CALL]) & btb_vbank0_rd_data_f[RET]};
+	function [1:0] countones;
+		input [1:0] valid;
+		countones[1:0] = {2'b00, valid[1]} + {2'b00, valid[0]};
+	endfunction
+	assign num_valids[1:0] = countones(bht_valid_f[1:0]);
+	assign final_h = |(btb_sel_f[1:0] & bht_dir_f[1:0]);
+	assign merged_ghr[pt[2236-:8] - 1:0] = (({pt[2236-:8] {num_valids[1:0] == 2'h2}} & {fghr[pt[2236-:8] - 3:0], 1'b0, final_h}) | ({pt[2236-:8] {num_valids[1:0] == 2'h1}} & {fghr[pt[2236-:8] - 2:0], final_h})) | ({pt[2236-:8] {num_valids[1:0] == 2'h0}} & {fghr[pt[2236-:8] - 1:0]});
+	wire [pt[2236-:8] - 1:0] exu_flush_ghr;
+	assign exu_flush_ghr[pt[2236-:8] - 1:0] = exu_mp_fghr[pt[2236-:8] - 1:0];
+	assign fghr_ns[pt[2236-:8] - 1:0] = (({pt[2236-:8] {exu_flush_final_d1}} & exu_flush_ghr[pt[2236-:8] - 1:0]) | ({pt[2236-:8] {((~exu_flush_final_d1 & ifc_fetch_req_f) & ic_hit_f) & ~leak_one_f_d1}} & merged_ghr[pt[2236-:8] - 1:0])) | ({pt[2236-:8] {~exu_flush_final_d1 & ~((ifc_fetch_req_f & ic_hit_f) & ~leak_one_f_d1)}} & fghr[pt[2236-:8] - 1:0]);
+	rvdffie #(
+		.WIDTH(pt[2236-:8] + 3),
+		.OVERRIDE(1)
+	) fetchghr(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din({exu_flush_final, exu_mp_way, leak_one_f, fghr_ns[pt[2236-:8] - 1:0]}),
+		.dout({exu_flush_final_d1, exu_mp_way_f, leak_one_f_d1, fghr[pt[2236-:8] - 1:0]})
+	);
+	assign ifu_bp_fghr_f[pt[2236-:8] - 1:0] = fghr[pt[2236-:8] - 1:0];
+	assign ifu_bp_way_f[1:0] = way_raw[1:0];
+	assign ifu_bp_hist1_f[1:0] = hist1_raw[1:0];
+	assign ifu_bp_hist0_f[1:0] = hist0_raw[1:0];
+	assign ifu_bp_pc4_f[1:0] = pc4_raw[1:0];
+	assign ifu_bp_valid_f[1:0] = vwayhit_f[1:0] & ~{2 {dec_tlu_bpred_disable}};
+	assign ifu_bp_ret_f[1:0] = pret_raw[1:0];
+	wire [1:0] bloc_f;
+	wire use_fa_plus;
+	assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0] & fetch_start_f[0]);
+	assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0] & ~fetch_start_f[0]);
+	assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0]) & ~btb_rd_pc4_f;
+	assign btb_fg_crossing_f = (fetch_start_f[0] & btb_sel_f[0]) & btb_rd_pc4_f;
+	assign bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f;
+	wire [31:2] adder_pc_in_f;
+	wire [31:2] ifc_fetch_adder_prior;
+	rvdfflie #(
+		.WIDTH(30),
+		.LEFT(19)
+	) faddrf_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((ifc_fetch_req_f & ~ifu_bp_hit_taken_f) & ic_hit_f),
+		.din(ifc_fetch_addr_f[31:2]),
+		.dout(ifc_fetch_adder_prior[31:2])
+	);
+	assign ifu_bp_poffset_f[11:0] = btb_rd_tgt_f[11:0];
+	assign adder_pc_in_f[31:2] = (({30 {use_fa_plus}} & fetch_addr_p1_f[31:2]) | ({30 {btb_fg_crossing_f}} & ifc_fetch_adder_prior[31:2])) | ({30 {~btb_fg_crossing_f & ~use_fa_plus}} & ifc_fetch_addr_f[31:2]);
+	rvbradder predtgt_addr(
+		.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
+		.offset(btb_rd_tgt_f[11:0]),
+		.dout(bp_btb_target_adder_f[31:1])
+	);
+	assign ifu_bp_btb_target_f[31:1] = ({31 {((btb_rd_ret_f & ~btb_rd_call_f) & rets_out[0]) & ifu_bp_hit_taken_f}} & rets_out[31-:31]) | ({31 {~((btb_rd_ret_f & ~btb_rd_call_f) & rets_out[0]) & ifu_bp_hit_taken_f}} & bp_btb_target_adder_f[31:1]);
+	rvbradder rs_addr(
+		.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),
+		.offset({11'b00000000000, ~btb_rd_pc4_f}),
+		.dout(bp_rs_call_target_f[31:1])
+	);
+	assign rs_push = (btb_rd_call_f & ~btb_rd_ret_f) & ifu_bp_hit_taken_f;
+	assign rs_pop = (btb_rd_ret_f & ~btb_rd_call_f) & ifu_bp_hit_taken_f;
+	assign rs_hold = ~rs_push & ~rs_pop;
+	assign rets_in[31-:32] = ({32 {rs_push}} & {bp_rs_call_target_f[31:1], 1'b1}) | ({32 {rs_pop}} & rets_out[63-:32]);
+	assign rsenable[0] = ~rs_hold;
+	generate
+		for (i = 0; i < pt[31-:8]; i = i + 1) begin : retstack
+			if (i == (pt[31-:8] - 1)) begin
+				assign rets_in[(i * 32) + 31-:32] = rets_out[((i - 1) * 32) + 31-:32];
+				assign rsenable[i] = rs_push;
+			end
+			else if (i > 0) begin
+				assign rets_in[(i * 32) + 31-:32] = ({32 {rs_push}} & rets_out[((i - 1) * 32) + 31-:32]) | ({32 {rs_pop}} & rets_out[((i + 1) * 32) + 31-:32]);
+				assign rsenable[i] = rs_push | rs_pop;
+			end
+			rvdffe #(.WIDTH(32)) rets_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(rsenable[i]),
+				.din(rets_in[(i * 32) + 31-:32]),
+				.dout(rets_out[(i * 32) + 31-:32])
+			);
+		end
+	endgenerate
+	assign dec_tlu_error_wb = dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb;
+	assign btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] = dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]];
+	assign dec_tlu_way_wb = dec_tlu_br0_way_wb;
+	assign btb_valid = exu_mp_valid & ~dec_tlu_error_wb;
+	assign btb_wr_tag[pt[2139-:9] - 1:0] = exu_mp_btag[pt[2139-:9] - 1:0];
+	generate
+		if (!pt[2120-:5]) begin
+			if (pt[2144-:5]) begin : btbfold
+				eb1_btb_tag_hash_fold #(.pt(pt)) rdtagf(
+					.hash(fetch_rd_tag_f[pt[2139-:9] - 1:0]),
+					.pc({ifc_fetch_addr_f[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]})
+				);
+				eb1_btb_tag_hash_fold #(.pt(pt)) rdtagp1f(
+					.hash(fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]),
+					.pc({fetch_addr_p1_f[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]})
+				);
+			end
+			else begin
+				eb1_btb_tag_hash #(.pt(pt)) rdtagf(
+					.hash(fetch_rd_tag_f[pt[2139-:9] - 1:0]),
+					.pc({ifc_fetch_addr_f[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]})
+				);
+				eb1_btb_tag_hash #(.pt(pt)) rdtagp1f(
+					.hash(fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]),
+					.pc({fetch_addr_p1_f[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]})
+				);
+			end
+			assign btb_wr_en_way0 = {(~exu_mp_way & exu_mp_valid_write) & ~dec_tlu_error_wb} | {~dec_tlu_way_wb & dec_tlu_error_wb};
+			assign btb_wr_en_way1 = {(exu_mp_way & exu_mp_valid_write) & ~dec_tlu_error_wb} | {dec_tlu_way_wb & dec_tlu_error_wb};
+			assign btb_wr_addr[pt[2172-:9]:pt[2163-:6]] = (dec_tlu_error_wb ? btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] : exu_mp_addr[pt[2172-:9]:pt[2163-:6]]);
+			assign vwayhit_f[1:0] = (({2 {fetch_start_f[0]}} & {wayhit_f[1:0]}) | ({2 {fetch_start_f[1]}} & {wayhit_p1_f[0], wayhit_f[1]})) & {eoc_mask, 1'b1};
+		end
+	endgenerate
+	assign btb_wr_data[BTB_DWIDTH - 1:0] = {btb_wr_tag[pt[2139-:9] - 1:0], exu_mp_tgt[pt[2047-:9] - 1:0], exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid};
+	assign exu_mp_valid_write = (exu_mp_valid & exu_mp_ataken) & ~exu_mp_pkt[37];
+	wire [1:0] bht_wr_data0;
+	wire [1:0] bht_wr_data2;
+	wire [1:0] bht_wr_en0;
+	wire [1:0] bht_wr_en2;
+	assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;
+	assign bht_wr_en0[1:0] = {2 {((exu_mp_valid & ~exu_mp_call) & ~exu_mp_ret) & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};
+	assign bht_wr_en2[1:0] = {2 {dec_tlu_br0_v_wb}} & {dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb};
+	assign bht_wr_data0[1:0] = exu_mp_hist[1:0];
+	assign bht_wr_data2[1:0] = dec_tlu_br0_hist_wb[1:0];
+	wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_f;
+	wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_p1_f;
+	wire [pt[2270-:8]:pt[2262-:6]] bht_wr_addr0;
+	wire [pt[2270-:8]:pt[2262-:6]] bht_wr_addr2;
+	wire [pt[2270-:8]:pt[2262-:6]] mp_hashed;
+	wire [pt[2270-:8]:pt[2262-:6]] br0_hashed_wb;
+	wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_hashed_f;
+	wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_hashed_p1_f;
+	eb1_btb_ghr_hash #(.pt(pt)) mpghrhs(
+		.hashin(exu_mp_addr[pt[2172-:9]:pt[2163-:6]]),
+		.ghr(exu_mp_eghr[pt[2236-:8] - 1:0]),
+		.hash(mp_hashed[pt[2270-:8]:pt[2262-:6]])
+	);
+	eb1_btb_ghr_hash #(.pt(pt)) br0ghrhs(
+		.hashin(dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]]),
+		.ghr(exu_i0_br_fghr_wb[pt[2236-:8] - 1:0]),
+		.hash(br0_hashed_wb[pt[2270-:8]:pt[2262-:6]])
+	);
+	eb1_btb_ghr_hash #(.pt(pt)) fghrhs(
+		.hashin(btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]),
+		.ghr(fghr[pt[2236-:8] - 1:0]),
+		.hash(bht_rd_addr_hashed_f[pt[2270-:8]:pt[2262-:6]])
+	);
+	eb1_btb_ghr_hash #(.pt(pt)) fghrhs_p1(
+		.hashin(btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]),
+		.ghr(fghr[pt[2236-:8] - 1:0]),
+		.hash(bht_rd_addr_hashed_p1_f[pt[2270-:8]:pt[2262-:6]])
+	);
+	assign bht_wr_addr0[pt[2270-:8]:pt[2262-:6]] = mp_hashed[pt[2270-:8]:pt[2262-:6]];
+	assign bht_wr_addr2[pt[2270-:8]:pt[2262-:6]] = br0_hashed_wb[pt[2270-:8]:pt[2262-:6]];
+	assign bht_rd_addr_f[pt[2270-:8]:pt[2262-:6]] = bht_rd_addr_hashed_f[pt[2270-:8]:pt[2262-:6]];
+	assign bht_rd_addr_p1_f[pt[2270-:8]:pt[2262-:6]] = bht_rd_addr_hashed_p1_f[pt[2270-:8]:pt[2262-:6]];
+	generate
+		if (!pt[2120-:5]) begin
+			for (j = 0; j < LRU_SIZE; j = j + 1) begin : BTB_FLOPS
+				rvdffe #(.WIDTH(17 + pt[2139-:9])) btb_bank0_way0(
+					.clk(clk),
+					.rst_l(rst_l),
+					.scan_mode(scan_mode),
+					.en((btb_wr_addr[pt[2172-:9]:pt[2163-:6]] == j) & btb_wr_en_way0),
+					.din(btb_wr_data[BTB_DWIDTH - 1:0]),
+					.dout(btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH])
+				);
+				rvdffe #(.WIDTH(17 + pt[2139-:9])) btb_bank0_way1(
+					.clk(clk),
+					.rst_l(rst_l),
+					.scan_mode(scan_mode),
+					.en((btb_wr_addr[pt[2172-:9]:pt[2163-:6]] == j) & btb_wr_en_way1),
+					.din(btb_wr_data[BTB_DWIDTH - 1:0]),
+					.dout(btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH])
+				);
+			end
+			function automatic signed [((pt[2172-:9] - pt[2163-:6]) >= 0 ? (pt[2172-:9] - pt[2163-:6]) + 1 : 1 - (pt[2172-:9] - pt[2163-:6])) - 1:0] sv2v_cast_C4842_signed;
+				input reg signed [((pt[2172-:9] - pt[2163-:6]) >= 0 ? (pt[2172-:9] - pt[2163-:6]) + 1 : 1 - (pt[2172-:9] - pt[2163-:6])) - 1:0] inp;
+				sv2v_cast_C4842_signed = inp;
+			endfunction
+			always @(*) begin : BTB_rd_mux
+				btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0] = {BTB_DWIDTH {1'sb0}};
+				btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0] = {BTB_DWIDTH {1'sb0}};
+				btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0] = {BTB_DWIDTH {1'sb0}};
+				btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0] = {BTB_DWIDTH {1'sb0}};
+				begin : sv2v_autoblock_43
+					reg signed [31:0] j;
+					for (j = 0; j < LRU_SIZE; j = j + 1)
+						if (btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]] == j[6:0]) begin
+							btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH];
+							btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH];
+						end
+				end
+				begin : sv2v_autoblock_44
+					reg signed [31:0] j;
+					for (j = 0; j < LRU_SIZE; j = j + 1)
+						if (btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]] == j[6:0]) begin
+							btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH];
+							btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH];
+						end
+				end
+			end
+		end
+	endgenerate
+	generate
+		if (pt[2120-:5]) begin : fa
+			reg found1;
+			reg hit0;
+			reg hit1;
+			wire btb_used_reset;
+			wire write_used;
+			reg [$clog2(pt[2061-:14]) - 1:0] btb_fa_wr_addr0;
+			reg [$clog2(pt[2061-:14]) - 1:0] hit0_index;
+			reg [$clog2(pt[2061-:14]) - 1:0] hit1_index;
+			reg [pt[2061-:14] - 1:0] btb_tag_hit;
+			reg [pt[2061-:14] - 1:0] btb_offset_0;
+			reg [pt[2061-:14] - 1:0] btb_offset_1;
+			wire [pt[2061-:14] - 1:0] btb_used_ns;
+			wire [pt[2061-:14] - 1:0] btb_used;
+			wire [pt[2061-:14] - 1:0] wr0_en;
+			reg [pt[2061-:14] - 1:0] btb_upper_hit;
+			wire [(pt[2061-:14] * BTB_DWIDTH) - 1:0] btbdata;
+			wire [FA_CMP_LOWER - 1:1] ifc_fetch_addr_p1_f;
+			assign ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1] = ifc_fetch_addr_f[FA_CMP_LOWER - 1:1] + 1'b1;
+			assign fetch_mp_collision_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == ifc_fetch_addr_f[31:1]) & exu_mp_valid) & ifc_fetch_req_f) & ~exu_mp_pkt[32];
+			assign fetch_mp_collision_p1_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == {ifc_fetch_addr_f[31:FA_CMP_LOWER], ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1]}) & exu_mp_valid) & ifc_fetch_req_f) & ~exu_mp_pkt[32];
+			function automatic signed [(BTB_FA_INDEX >= 0 ? BTB_FA_INDEX + 1 : 1 - BTB_FA_INDEX) - 1:0] sv2v_cast_50CAB_signed;
+				input reg signed [(BTB_FA_INDEX >= 0 ? BTB_FA_INDEX + 1 : 1 - BTB_FA_INDEX) - 1:0] inp;
+				sv2v_cast_50CAB_signed = inp;
+			endfunction
+			always @(*) begin
+				btb_vbank0_rd_data_f = {BTB_DWIDTH {1'sb0}};
+				btb_vbank1_rd_data_f = {BTB_DWIDTH {1'sb0}};
+				btb_tag_hit = {pt[2061-:14] {1'sb0}};
+				btb_upper_hit = {pt[2061-:14] {1'sb0}};
+				btb_offset_0 = {pt[2061-:14] {1'sb0}};
+				btb_offset_1 = {pt[2061-:14] {1'sb0}};
+				found1 = 1'b0;
+				hit0 = 1'b0;
+				hit1 = 1'b0;
+				hit0_index = {$clog2(pt[2061-:14]) {1'sb0}};
+				hit1_index = {$clog2(pt[2061-:14]) {1'sb0}};
+				btb_fa_wr_addr0 = {$clog2(pt[2061-:14]) {1'sb0}};
+				begin : sv2v_autoblock_45
+					reg signed [31:0] i;
+					for (i = 0; i < pt[2061-:14]; i = i + 1)
+						begin
+							btb_upper_hit[i] = ((btbdata[(i * BTB_DWIDTH) + (BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? BTB_DWIDTH_TOP : (BTB_DWIDTH_TOP + (BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? (BTB_DWIDTH_TOP - FA_TAG_END_UPPER) + 1 : (FA_TAG_END_UPPER - BTB_DWIDTH_TOP) + 1)) - 1)-:(BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? (BTB_DWIDTH_TOP - FA_TAG_END_UPPER) + 1 : (FA_TAG_END_UPPER - BTB_DWIDTH_TOP) + 1)] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i * BTB_DWIDTH]) & ~wr0_en[i];
+							btb_offset_0[i] = (btbdata[(i * BTB_DWIDTH) + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? FA_TAG_START_LOWER : (FA_TAG_START_LOWER + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)) - 1)-:(FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)] == ifc_fetch_addr_f[FA_CMP_LOWER - 1:1]) & btb_upper_hit[i];
+							btb_offset_1[i] = (btbdata[(i * BTB_DWIDTH) + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? FA_TAG_START_LOWER : (FA_TAG_START_LOWER + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)) - 1)-:(FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)] == ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1]) & btb_upper_hit[i];
+							if (~hit0)
+								if (btb_offset_0[i]) begin
+									hit0_index[BTB_FA_INDEX:0] = sv2v_cast_50CAB_signed(i);
+									hit0 = 1'b1;
+								end
+							if (~hit1)
+								if (btb_offset_1[i]) begin
+									hit1_index[BTB_FA_INDEX:0] = sv2v_cast_50CAB_signed(i);
+									hit1 = 1'b1;
+								end
+							if (btb_offset_0[i] == 1'b1)
+								btb_vbank0_rd_data_f[BTB_DWIDTH - 1:0] = (fetch_mp_collision_f ? btb_wr_data : btbdata[i * BTB_DWIDTH+:BTB_DWIDTH]);
+							if (btb_offset_1[i] == 1'b1)
+								btb_vbank1_rd_data_f[BTB_DWIDTH - 1:0] = (fetch_mp_collision_p1_f ? btb_wr_data : btbdata[i * BTB_DWIDTH+:BTB_DWIDTH]);
+							if (~found1)
+								if (~btb_used[i]) begin
+									btb_fa_wr_addr0[BTB_FA_INDEX:0] = i[BTB_FA_INDEX:0];
+									found1 = 1'b1;
+								end
+						end
+				end
+			end
+			assign vwayhit_f[1:0] = {hit1, hit0} & {eoc_mask, 1'b1};
+			assign way_raw[1:0] = vwayhit_f[1:0] | {fetch_mp_collision_p1_f, fetch_mp_collision_f};
+			for (j = 0; j < pt[2061-:14]; j = j + 1) begin : BTB_FAFLOPS
+				assign wr0_en[j] = ((btb_fa_wr_addr0[BTB_FA_INDEX:0] == j) & (exu_mp_valid_write & ~exu_mp_pkt[32])) | ((dec_fa_error_index == j) & dec_tlu_error_wb);
+				rvdffe #(.WIDTH(BTB_DWIDTH)) btb_fa(
+					.rst_l(rst_l),
+					.scan_mode(scan_mode),
+					.clk(clk),
+					.en(wr0_en[j]),
+					.din(btb_wr_data[BTB_DWIDTH - 1:0]),
+					.dout(btbdata[j * BTB_DWIDTH+:BTB_DWIDTH])
+				);
+			end
+			assign ifu_bp_fa_index_f[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] = (hit1 ? hit1_index : {$clog2(pt[2061-:14]) {1'sb0}});
+			assign ifu_bp_fa_index_f[0+:$clog2(pt[2061-:14])] = (hit0 ? hit0_index : {$clog2(pt[2061-:14]) {1'sb0}});
+			assign btb_used_reset = &btb_used[pt[2061-:14] - 1:0];
+			assign btb_used_ns[pt[2061-:14] - 1:0] = ((((({pt[2061-:14] {vwayhit_f[1]}} & (32'b00000000000000000000000000000001 << hit1_index[BTB_FA_INDEX:0])) | ({pt[2061-:14] {vwayhit_f[0]}} & (32'b00000000000000000000000000000001 << hit0_index[BTB_FA_INDEX:0]))) | ({pt[2061-:14] {(exu_mp_valid_write & ~exu_mp_pkt[32]) & ~dec_tlu_error_wb}} & (32'b00000000000000000000000000000001 << btb_fa_wr_addr0[BTB_FA_INDEX:0]))) | ({pt[2061-:14] {btb_used_reset}} & {pt[2061-:14] {1'b0}})) | ({pt[2061-:14] {~btb_used_reset & dec_tlu_error_wb}} & (btb_used[pt[2061-:14] - 1:0] & ~(32'b00000000000000000000000000000001 << dec_fa_error_index[BTB_FA_INDEX:0])))) | (~{pt[2061-:14] {btb_used_reset | dec_tlu_error_wb}} & btb_used[pt[2061-:14] - 1:0]);
+			assign write_used = ((btb_used_reset | ifu_bp_hit_taken_f) | exu_mp_valid_write) | dec_tlu_error_wb;
+			rvdffe #(.WIDTH(pt[2061-:14])) btb_usedf(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(write_used),
+				.din(btb_used_ns[pt[2061-:14] - 1:0]),
+				.dout(btb_used[pt[2061-:14] - 1:0])
+			);
+		end
+	endgenerate
+	wire [(((2 * (pt[2256-:15] / NUM_BHT_LOOP)) * NUM_BHT_LOOP) * 2) - 1:0] bht_bank_wr_data;
+	wire [((2 * pt[2256-:15]) * 2) - 1:0] bht_bank_rd_data_out;
+	wire [(2 * (pt[2256-:15] / NUM_BHT_LOOP)) - 1:0] bht_bank_clken;
+	wire [(2 * (pt[2256-:15] / NUM_BHT_LOOP)) - 1:0] bht_bank_clk;
+	wire [((2 * (pt[2256-:15] / NUM_BHT_LOOP)) * NUM_BHT_LOOP) - 1:0] bht_bank_sel;
+	generate
+		for (i = 0; i < 2; i = i + 1) begin : BANKS
+			genvar k;
+			for (k = 0; k < (pt[2256-:15] / NUM_BHT_LOOP); k = k + 1) begin : BHT_CLK_GROUP
+				assign bht_bank_clken[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH)) | (bht_wr_en2[i] & ((bht_wr_addr2[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH));
+				rvclkhdr bht_bank_grp_cgc(
+					.en(bht_bank_clken[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k]),
+					.l1clk(bht_bank_clk[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k]),
+					.clk(clk),
+					.scan_mode(scan_mode)
+				);
+				for (j = 0; j < NUM_BHT_LOOP; j = j + 1) begin : BHT_FLOPS
+					assign bht_bank_sel[(((i * (pt[2256-:15] / NUM_BHT_LOOP)) + k) * NUM_BHT_LOOP) + j] = ((bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI:pt[2262-:6]] == j)) & ((bht_wr_addr0[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH)) | ((bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt[2262-:6]] == j)) & ((bht_wr_addr2[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH));
+					assign bht_bank_wr_data[((((i * (pt[2256-:15] / NUM_BHT_LOOP)) + k) * NUM_BHT_LOOP) + j) * 2+:2] = ((bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt[2262-:6]] == j)) & ((bht_wr_addr2[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH) ? bht_wr_data2[1:0] : bht_wr_data0[1:0]);
+					rvdffs_fpga #(.WIDTH(2)) bht_bank(
+						.rst_l(rst_l),
+						.clk(bht_bank_clk[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k]),
+						.en(bht_bank_sel[(((i * (pt[2256-:15] / NUM_BHT_LOOP)) + k) * NUM_BHT_LOOP) + j]),
+						.rawclk(clk),
+						.clken(bht_bank_sel[(((i * (pt[2256-:15] / NUM_BHT_LOOP)) + k) * NUM_BHT_LOOP) + j]),
+						.din(bht_bank_wr_data[((((i * (pt[2256-:15] / NUM_BHT_LOOP)) + k) * NUM_BHT_LOOP) + j) * 2+:2]),
+						.dout(bht_bank_rd_data_out[((i * pt[2256-:15]) + ((16 * k) + j)) * 2+:2])
+					);
+				end
+			end
+		end
+	endgenerate
+	function automatic signed [((pt[2270-:8] - pt[2262-:6]) >= 0 ? (pt[2270-:8] - pt[2262-:6]) + 1 : 1 - (pt[2270-:8] - pt[2262-:6])) - 1:0] sv2v_cast_AB44B_signed;
+		input reg signed [((pt[2270-:8] - pt[2262-:6]) >= 0 ? (pt[2270-:8] - pt[2262-:6]) + 1 : 1 - (pt[2270-:8] - pt[2262-:6])) - 1:0] inp;
+		sv2v_cast_AB44B_signed = inp;
+	endfunction
+	always @(*) begin : BHT_rd_mux
+		bht_bank0_rd_data_f[1:0] = {2 {1'sb0}};
+		bht_bank1_rd_data_f[1:0] = {2 {1'sb0}};
+		bht_bank0_rd_data_p1_f[1:0] = {2 {1'sb0}};
+		begin : sv2v_autoblock_46
+			reg signed [31:0] j;
+			for (j = 0; j < pt[2256-:15]; j = j + 1)
+				begin
+					if (bht_rd_addr_f[pt[2270-:8]:pt[2262-:6]] == sv2v_cast_AB44B_signed(j)) begin
+						bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[j * 2+:2];
+						bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[(pt[2256-:15] + j) * 2+:2];
+					end
+					if (bht_rd_addr_p1_f[pt[2270-:8]:pt[2262-:6]] == sv2v_cast_AB44B_signed(j))
+						bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[j * 2+:2];
+				end
+		end
+	end
+endmodule
+module eb1_ifu_compress_ctl (
+	din,
+	dout
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [15:0] din;
+	output wire [31:0] dout;
+	wire legal;
+	wire [15:0] i;
+	wire [31:0] o;
+	wire [31:0] l1;
+	wire [31:0] l2;
+	wire [31:0] l3;
+	assign i[15:0] = din[15:0];
+	wire [4:0] rs2d;
+	wire [4:0] rdd;
+	wire [4:0] rdpd;
+	wire [4:0] rs2pd;
+	wire rdrd;
+	wire rdrs1;
+	wire rs2rs2;
+	wire rdprd;
+	wire rdprs1;
+	wire rs2prs2;
+	wire rs2prd;
+	wire uimm9_2;
+	wire ulwimm6_2;
+	wire ulwspimm7_2;
+	wire rdeq2;
+	wire rdeq1;
+	wire rs1eq2;
+	wire sbroffset8_1;
+	wire simm9_4;
+	wire simm5_0;
+	wire sjaloffset11_1;
+	wire sluimm17_12;
+	wire uimm5_0;
+	wire uswimm6_2;
+	wire uswspimm7_2;
+	assign rs2d[4:0] = i[6:2];
+	assign rdd[4:0] = i[11:7];
+	assign rdpd[4:0] = {2'b01, i[9:7]};
+	assign rs2pd[4:0] = {2'b01, i[4:2]};
+	assign l1[6:0] = o[6:0];
+	assign l1[11:7] = ((((o[11:7] | ({5 {rdrd}} & rdd[4:0])) | ({5 {rdprd}} & rdpd[4:0])) | ({5 {rs2prd}} & rs2pd[4:0])) | ({5 {rdeq1}} & 5'd1)) | ({5 {rdeq2}} & 5'd2);
+	assign l1[14:12] = o[14:12];
+	assign l1[19:15] = ((o[19:15] | ({5 {rdrs1}} & rdd[4:0])) | ({5 {rdprs1}} & rdpd[4:0])) | ({5 {rs1eq2}} & 5'd2);
+	assign l1[24:20] = (o[24:20] | ({5 {rs2rs2}} & rs2d[4:0])) | ({5 {rs2prs2}} & rs2pd[4:0]);
+	assign l1[31:25] = o[31:25];
+	wire [5:0] simm5d;
+	wire [9:2] uimm9d;
+	wire [9:4] simm9d;
+	wire [6:2] ulwimm6d;
+	wire [7:2] ulwspimm7d;
+	wire [5:0] uimm5d;
+	wire [20:1] sjald;
+	wire [31:12] sluimmd;
+	assign simm5d[5:0] = {i[12], i[6:2]};
+	assign uimm9d[9:2] = {i[10:7], i[12:11], i[5], i[6]};
+	assign simm9d[9:4] = {i[12], i[4:3], i[5], i[2], i[6]};
+	assign ulwimm6d[6:2] = {i[5], i[12:10], i[6]};
+	assign ulwspimm7d[7:2] = {i[3:2], i[12], i[6:4]};
+	assign uimm5d[5:0] = {i[12], i[6:2]};
+	assign sjald[11:1] = {i[12], i[8], i[10:9], i[6], i[7], i[2], i[11], i[5:4], i[3]};
+	assign sjald[20:12] = {9 {i[12]}};
+	assign sluimmd[31:12] = {{15 {i[12]}}, i[6:2]};
+	assign l2[31:20] = (((((((l1[31:20] | ({12 {simm5_0}} & {{7 {simm5d[5]}}, simm5d[4:0]})) | ({12 {uimm9_2}} & {2'b00, uimm9d[9:2], 2'b00})) | ({12 {simm9_4}} & {{3 {simm9d[9]}}, simm9d[8:4], 4'b0000})) | ({12 {ulwimm6_2}} & {5'b00000, ulwimm6d[6:2], 2'b00})) | ({12 {ulwspimm7_2}} & {4'b0000, ulwspimm7d[7:2], 2'b00})) | ({12 {uimm5_0}} & {6'b000000, uimm5d[5:0]})) | ({12 {sjaloffset11_1}} & {sjald[20], sjald[10:1], sjald[11]})) | ({12 {sluimm17_12}} & sluimmd[31:20]);
+	assign l2[19:12] = (l1[19:12] | ({8 {sjaloffset11_1}} & sjald[19:12])) | ({8 {sluimm17_12}} & sluimmd[19:12]);
+	assign l2[11:0] = l1[11:0];
+	wire [8:1] sbr8d;
+	wire [6:2] uswimm6d;
+	wire [7:2] uswspimm7d;
+	assign sbr8d[8:1] = {i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3]};
+	assign uswimm6d[6:2] = {i[5], i[12:10], i[6]};
+	assign uswspimm7d[7:2] = {i[8:7], i[12:9]};
+	assign l3[31:25] = ((l2[31:25] | ({7 {sbroffset8_1}} & {{4 {sbr8d[8]}}, sbr8d[7:5]})) | ({7 {uswimm6_2}} & {5'b00000, uswimm6d[6:5]})) | ({7 {uswspimm7_2}} & {4'b0000, uswspimm7d[7:5]});
+	assign l3[24:12] = l2[24:12];
+	assign l3[11:7] = ((l2[11:7] | ({5 {sbroffset8_1}} & {sbr8d[4:1], sbr8d[8]})) | ({5 {uswimm6_2}} & {uswimm6d[4:2], 2'b00})) | ({5 {uswspimm7_2}} & {uswspimm7d[4:2], 2'b00});
+	assign l3[6:0] = l2[6:0];
+	assign dout[31:0] = l3[31:0] & {32 {legal}};
+	assign rdrd = ((((((((((((!i[14] & i[6]) & i[1]) | (((!i[15] & i[14]) & i[11]) & i[0])) | ((!i[14] & i[5]) & i[1])) | (((!i[15] & i[14]) & i[10]) & i[0])) | ((!i[14] & i[4]) & i[1])) | (((!i[15] & i[14]) & i[9]) & i[0])) | ((!i[14] & i[3]) & i[1])) | (((!i[15] & i[14]) & !i[8]) & i[0])) | ((!i[14] & i[2]) & i[1])) | (((!i[15] & i[14]) & i[7]) & i[0])) | (!i[15] & i[1])) | ((!i[15] & !i[13]) & i[0]);
+	assign rdrs1 = ((((((((((((((!i[14] & i[12]) & i[11]) & i[1]) | (((!i[14] & i[12]) & i[10]) & i[1])) | (((!i[14] & i[12]) & i[9]) & i[1])) | (((!i[14] & i[12]) & i[8]) & i[1])) | (((!i[14] & i[12]) & i[7]) & i[1])) | (((((((!i[14] & !i[12]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | (((!i[14] & i[12]) & i[6]) & i[1])) | (((!i[14] & i[12]) & i[5]) & i[1])) | (((!i[14] & i[12]) & i[4]) & i[1])) | (((!i[14] & i[12]) & i[3]) & i[1])) | (((!i[14] & i[12]) & i[2]) & i[1])) | (((!i[15] & !i[14]) & !i[13]) & i[0])) | ((!i[15] & !i[14]) & i[1]);
+	assign rs2rs2 = ((((((i[15] & i[6]) & i[1]) | ((i[15] & i[5]) & i[1])) | ((i[15] & i[4]) & i[1])) | ((i[15] & i[3]) & i[1])) | ((i[15] & i[2]) & i[1])) | ((i[15] & i[14]) & i[1]);
+	assign rdprd = ((i[15] & !i[14]) & !i[13]) & i[0];
+	assign rdprs1 = (((i[15] & !i[13]) & i[0]) | ((i[15] & i[14]) & i[0])) | ((i[14] & !i[1]) & !i[0]);
+	assign rs2prs2 = (((((i[15] & !i[14]) & !i[13]) & i[11]) & i[10]) & i[0]) | ((i[15] & !i[1]) & !i[0]);
+	assign rs2prd = (!i[15] & !i[1]) & !i[0];
+	assign uimm9_2 = (!i[14] & !i[1]) & !i[0];
+	assign ulwimm6_2 = ((!i[15] & i[14]) & !i[1]) & !i[0];
+	assign ulwspimm7_2 = (!i[15] & i[14]) & i[1];
+	assign rdeq2 = ((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7];
+	assign rdeq1 = ((((((((((((!i[14] & i[12]) & i[11]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) | ((((((((!i[14] & i[12]) & i[10]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[9]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[8]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((!i[15] & !i[14]) & i[13]);
+	assign rs1eq2 = ((((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7]) | (i[14] & i[1])) | ((!i[14] & !i[1]) & !i[0]);
+	assign sbroffset8_1 = (i[15] & i[14]) & i[0];
+	assign simm9_4 = ((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7];
+	assign simm5_0 = ((((!i[14] & !i[13]) & i[11]) & !i[10]) & i[0]) | ((!i[15] & !i[13]) & i[0]);
+	assign sjaloffset11_1 = !i[14] & i[13];
+	assign sluimm17_12 = ((((((!i[15] & i[14]) & i[13]) & i[7]) | (((!i[15] & i[14]) & i[13]) & !i[8])) | (((!i[15] & i[14]) & i[13]) & i[9])) | (((!i[15] & i[14]) & i[13]) & i[10])) | (((!i[15] & i[14]) & i[13]) & i[11]);
+	assign uimm5_0 = ((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0]) | ((!i[15] & !i[14]) & i[1]);
+	assign uswimm6_2 = (i[15] & !i[1]) & !i[0];
+	assign uswspimm7_2 = (i[15] & i[14]) & i[1];
+	assign o[31] = 1'b0;
+	assign o[30] = ((((((i[15] & !i[14]) & !i[13]) & i[10]) & !i[6]) & !i[5]) & i[0]) | (((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[10]) & i[0]);
+	assign o[29] = 1'b0;
+	assign o[28] = 1'b0;
+	assign o[27] = 1'b0;
+	assign o[26] = 1'b0;
+	assign o[25] = 1'b0;
+	assign o[24] = 1'b0;
+	assign o[23] = 1'b0;
+	assign o[22] = 1'b0;
+	assign o[21] = 1'b0;
+	assign o[20] = (((((((((((!i[14] & i[12]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1];
+	assign o[19] = 1'b0;
+	assign o[18] = 1'b0;
+	assign o[17] = 1'b0;
+	assign o[16] = 1'b0;
+	assign o[15] = 1'b0;
+	assign o[14] = ((((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0]) | ((((i[15] & !i[14]) & !i[13]) & !i[10]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & i[6]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & i[5]) & i[0]);
+	assign o[13] = ((((((i[15] & !i[14]) & !i[13]) & i[11]) & !i[10]) & i[0]) | (((((i[15] & !i[14]) & !i[13]) & i[11]) & i[6]) & i[0])) | (i[14] & !i[0]);
+	assign o[12] = ((((((((i[15] & !i[14]) & !i[13]) & i[6]) & i[5]) & i[0]) | ((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & !i[10]) & i[0])) | ((!i[15] & !i[14]) & i[1])) | ((i[15] & i[14]) & i[13]);
+	assign o[11] = 1'b0;
+	assign o[10] = 1'b0;
+	assign o[9] = 1'b0;
+	assign o[8] = 1'b0;
+	assign o[7] = 1'b0;
+	assign o[6] = ((((((((i[15] & !i[14]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & !i[0]) | (!i[14] & i[13])) | ((i[15] & i[14]) & i[0]);
+	assign o[5] = ((((((((i[15] & !i[0]) | ((i[15] & i[11]) & i[10])) | (i[13] & !i[8])) | (i[13] & i[7])) | (i[13] & i[9])) | (i[13] & i[10])) | (i[13] & i[11])) | (!i[14] & i[13])) | (i[15] & i[14]);
+	assign o[4] = (((((((((((((!i[14] & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[0]) | ((!i[15] & !i[14]) & !i[0])) | ((!i[14] & i[6]) & !i[0])) | ((!i[15] & i[14]) & i[0])) | ((!i[14] & i[5]) & !i[0])) | ((!i[14] & i[4]) & !i[0])) | ((!i[14] & !i[13]) & i[0])) | ((!i[14] & i[3]) & !i[0])) | ((!i[14] & i[2]) & !i[0]);
+	assign o[3] = !i[14] & i[13];
+	assign o[2] = ((((((((((((((((((!i[14] & i[12]) & i[11]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) | ((((((((!i[14] & i[12]) & i[10]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[9]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[8]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((i[15] & !i[14]) & !i[12]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & !i[0])) | ((!i[15] & i[13]) & !i[8])) | ((!i[15] & i[13]) & i[7])) | ((!i[15] & i[13]) & i[9])) | ((!i[15] & i[13]) & i[10])) | ((!i[15] & i[13]) & i[11])) | (!i[14] & i[13]);
+	assign o[1] = 1'b1;
+	assign o[0] = 1'b1;
+	assign legal = (((((((((((((((((((((((((((((((((!i[13] & !i[12]) & i[11]) & i[1]) & !i[0]) | ((((!i[13] & !i[12]) & i[6]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[11]) & !i[1])) | ((((!i[13] & !i[12]) & i[5]) & i[1]) & !i[0])) | ((((!i[13] & !i[12]) & i[10]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[6]) & !i[1])) | (((i[15] & !i[12]) & !i[1]) & i[0])) | ((((!i[13] & !i[12]) & i[9]) & i[1]) & !i[0])) | (((!i[12] & i[6]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[5]) & !i[1])) | ((((!i[13] & !i[12]) & i[8]) & i[1]) & !i[0])) | (((!i[12] & i[5]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[10]) & !i[1])) | ((((!i[13] & !i[12]) & i[7]) & i[1]) & !i[0])) | ((((i[12] & i[11]) & !i[10]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[9]) & !i[1])) | ((((!i[13] & !i[12]) & i[4]) & i[1]) & !i[0])) | (((i[13] & i[12]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[8]) & !i[1])) | ((((!i[13] & !i[12]) & i[3]) & i[1]) & !i[0])) | (((i[13] & i[4]) & !i[1]) & i[0])) | ((((!i[13] & !i[12]) & i[2]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[7]) & !i[1])) | (((i[13] & i[3]) & !i[1]) & i[0])) | (((i[13] & i[2]) & !i[1]) & i[0])) | ((i[14] & !i[13]) & !i[1])) | (((!i[14] & !i[12]) & !i[1]) & i[0])) | ((((i[15] & !i[13]) & i[12]) & i[1]) & !i[0])) | ((((!i[15] & !i[13]) & !i[12]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[12]) & !i[1])) | ((i[14] & !i[13]) & !i[0]);
+endmodule
+module eb1_ifu_iccm_mem (
+`ifdef USE_POWER_PINS	
+	vccd1,
+	vssd1,
+`endif
+	clk,
+	active_clk,
+	rst_l,
+	clk_override,
+	iccm_wren,
+	iccm_rden,
+	iccm_rw_addr,
+	iccm_buf_correct_ecc,
+	iccm_correction_state,
+	iccm_wr_size,
+	iccm_wr_data,
+	iccm_ext_in_pkt,
+	iccm_rd_data,
+	iccm_rd_data_ecc,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+`ifdef USE_POWER_PINS
+	inout wire vccd1;
+	inout wire vssd1;
+`endif
+	input wire clk;
+	input wire active_clk;
+	input wire rst_l;
+	input wire clk_override;
+	input wire iccm_wren;
+	input wire iccm_rden;
+	input wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	input wire iccm_buf_correct_ecc;
+	input wire iccm_correction_state;
+	input wire [2:0] iccm_wr_size;
+	input wire [77:0] iccm_wr_data;
+	input wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt;
+	output wire [63:0] iccm_rd_data;
+	output wire [77:0] iccm_rd_data_ecc;
+	input wire scan_mode;
+	wire [pt[909-:9] - 1:0] wren_bank;
+	wire [pt[909-:9] - 1:0] rden_bank;
+	wire [pt[909-:9] - 1:0] iccm_clken;
+	wire [((pt[936-:9] - 1) >= pt[945-:9] ? (pt[909-:9] * (((pt[936-:9] - 1) - pt[945-:9]) + 1)) + (pt[945-:9] - 1) : (pt[909-:9] * ((pt[945-:9] - (pt[936-:9] - 1)) + 1)) + (pt[936-:9] - 2)):((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1)] addr_bank;
+	wire [(pt[909-:9] * 39) - 1:0] iccm_bank_dout;
+	wire [(pt[909-:9] * 39) - 1:0] iccm_bank_dout_fn;
+	wire [(pt[909-:9] * 39) - 1:0] iccm_bank_wr_data;
+	wire [pt[936-:9] - 1:1] addr_bank_inc;
+	wire [pt[954-:9]:2] iccm_rd_addr_hi_q;
+	wire [pt[954-:9]:1] iccm_rd_addr_lo_q;
+	wire [63:0] iccm_rd_data_pre;
+	wire [63:0] iccm_data;
+	wire [1:0] addr_incr;
+	wire [(pt[909-:9] * 39) - 1:0] iccm_bank_wr_data_vec;
+	wire [((pt[936-:9] - 1) >= 2 ? (2 * (pt[936-:9] - 2)) + 1 : (2 * (4 - pt[936-:9])) + (pt[936-:9] - 2)):((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] redundant_address;
+	wire [77:0] redundant_data;
+	wire [1:0] redundant_valid;
+	wire [pt[909-:9] - 1:0] sel_red1;
+	wire [pt[909-:9] - 1:0] sel_red0;
+	wire [pt[909-:9] - 1:0] sel_red1_q;
+	wire [pt[909-:9] - 1:0] sel_red0_q;
+	wire [38:0] redundant_data0_in;
+	wire [38:0] redundant_data1_in;
+	wire redundant_lru;
+	wire redundant_lru_in;
+	wire redundant_lru_en;
+	wire redundant_data0_en;
+	wire redundant_data1_en;
+	wire r0_addr_en;
+	wire r1_addr_en;
+	assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11 ? 2'b10 : 2'b01);
+	assign addr_bank_inc[pt[936-:9] - 1:1] = iccm_rw_addr[pt[936-:9] - 1:1] + addr_incr[1:0];
+	generate
+		genvar i;
+		for (i = 0; i < (pt[909-:9] / 2); i = i + 1) begin : mem_bank_data
+			assign iccm_bank_wr_data_vec[(2 * i) * 39+:39] = iccm_wr_data[38:0];
+			assign iccm_bank_wr_data_vec[((2 * i) + 1) * 39+:39] = iccm_wr_data[77:39];
+		end
+	endgenerate
+	generate
+		for (i = 0; i < pt[909-:9]; i = i + 1) begin : mem_bank
+			assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[pt[954-:9]:2] == i) | (addr_bank_inc[pt[954-:9]:2] == i));
+			assign iccm_bank_wr_data[i * 39+:39] = iccm_bank_wr_data_vec[i * 39+:39];
+			assign rden_bank[i] = iccm_rden & ((iccm_rw_addr[pt[954-:9]:2] == i) | (addr_bank_inc[pt[954-:9]:2] == i));
+			assign iccm_clken[i] = (wren_bank[i] | rden_bank[i]) | clk_override;
+			assign addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) : pt[945-:9] - (((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) - (pt[936-:9] - 1))) : (((i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) : pt[945-:9] - (((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1)-:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)] = (wren_bank[i] ? iccm_rw_addr[pt[936-:9] - 1:pt[945-:9]] : (addr_bank_inc[pt[954-:9]:2] == i ? addr_bank_inc[pt[936-:9] - 1:pt[945-:9]] : iccm_rw_addr[pt[936-:9] - 1:pt[945-:9]]));
+			if (pt[917-:8] == 6) begin : iccm
+				ram_64x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 7) begin : iccm
+				ram_128x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 8) begin : iccm
+				/*sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+					`ifdef USE_POWER_PINS 
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(~iccm_clken[i]),
+					.web0(~wren_bank[i]),
+					.wmask0(4'hf),
+					.addr0(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.din0(iccm_bank_wr_data[(i * 39) + 31-:32]),
+					.dout0(iccm_bank_dout[(i * 39) + 31-:32]),
+					.clk1(clk),
+					.csb1(1'b1),
+					.addr1(8'h00),
+					.dout1()
+				);*/
+				DFFRAM iccm
+					(
+					`ifdef USE_POWER_PINS
+    					 .VPWR(vccd1),
+    					 .VGND(vssd1),
+					 `endif
+    					 .CLK(clk),
+    					 .WE({4{wren_bank[i]}}),
+    					 .EN(iccm_clken[i]),
+    					 .Di(iccm_bank_wr_data[(i * 39) + 31-:32]),
+    					 .Do(iccm_bank_dout[(i * 39) + 31-:32]),
+    					 .A(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)])
+					);
+					/*SRAM64x32 iccm(
+						`ifdef USE_POWER_PINS
+    						.VPWR(vccd1),
+    						.VGND(vssd1),
+						`endif
+    						.CLK(clk),
+    						.WE({4{wren_bank[i]}}),
+    						.EN(iccm_clken[i]),
+    						.Di(iccm_bank_wr_data[(i * 39) + 31-:32]),
+    						.Do(iccm_bank_dout[(i * 39) + 31-:32]),
+    						.A(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)])
+);*/
+					
+			end
+			else if (pt[917-:8] == 9) begin : iccm
+				ram_512x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 10) begin : iccm
+				sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+					`ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(~iccm_clken[i]),
+					.web0(~wren_bank[i]),
+					.wmask0(4'hf),
+					.addr0(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.din0(iccm_bank_wr_data[i * 39+:39]),
+					.dout0(iccm_bank_dout[i * 39+:39]),
+					.clk1(clk),
+					.csb1(1'b1),
+					.addr1(8'h00),
+					.dout1()
+				);
+			end
+			else if (pt[917-:8] == 11) begin : iccm
+				ram_2048x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 12) begin : iccm
+				ram_4096x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 13) begin : iccm
+				ram_8192x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else if (pt[917-:8] == 14) begin : iccm
+				ram_16384x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			else begin : iccm
+				ram_32768x39 iccm_bank(
+					.CLK(clk),
+					.ME(iccm_clken[i]),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]),
+					.D(iccm_bank_wr_data[(i * 39) + 38-:39]),
+					.Q(iccm_bank_dout[(i * 39) + 38-:39]),
+					.ROP(),
+					.TEST1(iccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(iccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(iccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(iccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(iccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(iccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(iccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(iccm_ext_in_pkt[i * 12])
+				);
+			end
+			assign sel_red1[i] = redundant_valid[1] & (((iccm_rw_addr[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (addr_bank_inc[3:2] == i)));
+			assign sel_red0[i] = redundant_valid[0] & (((iccm_rw_addr[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : (((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : (((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (addr_bank_inc[3:2] == i)));
+			rvdff #(.WIDTH(1)) selred0(
+				.rst_l(rst_l),
+				.clk(active_clk),
+				.din(sel_red0[i]),
+				.dout(sel_red0_q[i])
+			);
+			rvdff #(.WIDTH(1)) selred1(
+				.rst_l(rst_l),
+				.clk(active_clk),
+				.din(sel_red1[i]),
+				.dout(sel_red1_q[i])
+			);
+			assign iccm_bank_dout_fn[(i * 39) + 38-:39] = (({39 {sel_red1_q[i]}} & redundant_data[77-:39]) | ({39 {sel_red0_q[i]}} & redundant_data[38-:39])) | ({39 {~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[(i * 39) + 38-:39]);
+		end
+	endgenerate
+	assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
+	assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
+	assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[pt[909-:9] - 1:0] | |sel_red1[pt[909-:9] - 1:0]) & iccm_rden) & iccm_correction_state);
+	assign redundant_lru_in = (iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[pt[909-:9] - 1:0] ? 1'b1 : 1'b0));
+	rvdffs red_lru(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(redundant_lru_en),
+		.din(redundant_lru_in),
+		.dout(redundant_lru)
+	);
+	rvdffs #(.WIDTH(pt[936-:9] - 2)) r0_address(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(r0_addr_en),
+		.din(iccm_rw_addr[pt[936-:9] - 1:2]),
+		.dout(redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : (((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])])
+	);
+	rvdffs #(.WIDTH(pt[936-:9] - 2)) r1_address(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(r1_addr_en),
+		.din(iccm_rw_addr[pt[936-:9] - 1:2]),
+		.dout(redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])])
+	);
+	rvdffs #(.WIDTH(1)) r0_valid(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(r0_addr_en),
+		.din(1'b1),
+		.dout(redundant_valid[0])
+	);
+	rvdffs #(.WIDTH(1)) r1_valid(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(r1_addr_en),
+		.din(1'b1),
+		.dout(redundant_valid[1])
+	);
+	assign redundant_data0_en = ((((iccm_rw_addr[pt[936-:9] - 1:3] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : (((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])]) & ((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) | (iccm_wr_size[1:0] == 2'b11))) & redundant_valid[0]) & iccm_wren) | (~redundant_lru & iccm_buf_correct_ecc);
+	assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) & iccm_rw_addr[2]) | (redundant_address[((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] & (iccm_wr_size[1:0] == 2'b11)) ? iccm_wr_data[77:39] : iccm_wr_data[38:0]);
+	rvdffs #(.WIDTH(39)) r0_data(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(redundant_data0_en),
+		.din(redundant_data0_in[38:0]),
+		.dout(redundant_data[38-:39])
+	);
+	assign redundant_data1_en = ((((iccm_rw_addr[pt[936-:9] - 1:3] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])]) & ((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) | (iccm_wr_size[1:0] == 2'b11))) & redundant_valid[1]) & iccm_wren) | (redundant_lru & iccm_buf_correct_ecc);
+	assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) & iccm_rw_addr[2]) | (redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] & (iccm_wr_size[1:0] == 2'b11)) ? iccm_wr_data[77:39] : iccm_wr_data[38:0]);
+	rvdffs #(.WIDTH(39)) r1_data(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.en(redundant_data1_en),
+		.din(redundant_data1_in[38:0]),
+		.dout(redundant_data[77-:39])
+	);
+	rvdffs #(.WIDTH(pt[954-:9])) rd_addr_lo_ff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din(iccm_rw_addr[pt[954-:9]:1]),
+		.dout(iccm_rd_addr_lo_q[pt[954-:9]:1]),
+		.en(1'b1)
+	);
+	rvdffs #(.WIDTH(pt[961-:7])) rd_addr_hi_ff(
+		.rst_l(rst_l),
+		.clk(active_clk),
+		.din(addr_bank_inc[pt[954-:9]:2]),
+		.dout(iccm_rd_addr_hi_q[pt[954-:9]:2]),
+		.en(1'b1)
+	);
+	assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[(iccm_rd_addr_hi_q * 39) + 31-:32], iccm_bank_dout_fn[(iccm_rd_addr_lo_q[pt[954-:9]:2] * 39) + 31-:32]};
+	function automatic [63:0] sv2v_cast_64;
+		input reg [63:0] inp;
+		sv2v_cast_64 = inp;
+	endfunction
+	assign iccm_data[63:0] = sv2v_cast_64({16'b0000000000000000, iccm_rd_data_pre[63:0] >> (16 * iccm_rd_addr_lo_q[1])});
+	assign iccm_rd_data[63:0] = {iccm_data[63:0]};
+	assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[(iccm_rd_addr_hi_q * 39) + 38-:39], iccm_bank_dout_fn[(iccm_rd_addr_lo_q[pt[954-:9]:2] * 39) + 38-:39]};
+endmodule
+module eb1_ifu_ifc_ctl (
+	clk,
+	free_l2clk,
+	rst_l,
+	scan_mode,
+	ic_hit_f,
+	ifu_ic_mb_empty,
+	ifu_fb_consume1,
+	ifu_fb_consume2,
+	dec_tlu_flush_noredir_wb,
+	exu_flush_final,
+	exu_flush_path_final,
+	ifu_bp_hit_taken_f,
+	ifu_bp_btb_target_f,
+	ic_dma_active,
+	ic_write_stall,
+	dma_iccm_stall_any,
+	dec_tlu_mrac_ff,
+	ifc_fetch_addr_f,
+	ifc_fetch_addr_bf,
+	ifc_fetch_req_f,
+	ifu_pmu_fetch_stall,
+	ifc_fetch_uncacheable_bf,
+	ifc_fetch_req_bf,
+	ifc_fetch_req_bf_raw,
+	ifc_iccm_access_bf,
+	ifc_region_acc_fault_bf,
+	ifc_dma_access_ok
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire free_l2clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire ic_hit_f;
+	input wire ifu_ic_mb_empty;
+	input wire ifu_fb_consume1;
+	input wire ifu_fb_consume2;
+	input wire dec_tlu_flush_noredir_wb;
+	input wire exu_flush_final;
+	input wire [31:1] exu_flush_path_final;
+	input wire ifu_bp_hit_taken_f;
+	input wire [31:1] ifu_bp_btb_target_f;
+	input wire ic_dma_active;
+	input wire ic_write_stall;
+	input wire dma_iccm_stall_any;
+	input wire [31:0] dec_tlu_mrac_ff;
+	output wire [31:1] ifc_fetch_addr_f;
+	output wire [31:1] ifc_fetch_addr_bf;
+	output wire ifc_fetch_req_f;
+	output wire ifu_pmu_fetch_stall;
+	output wire ifc_fetch_uncacheable_bf;
+	output wire ifc_fetch_req_bf;
+	output wire ifc_fetch_req_bf_raw;
+	output wire ifc_iccm_access_bf;
+	output wire ifc_region_acc_fault_bf;
+	output wire ifc_dma_access_ok;
+	wire [31:1] fetch_addr_bf;
+	wire [31:1] fetch_addr_next;
+	wire [3:0] fb_write_f;
+	wire [3:0] fb_write_ns;
+	wire fb_full_f_ns;
+	wire fb_full_f;
+	wire fb_right;
+	wire fb_right2;
+	wire fb_left;
+	wire wfm;
+	wire idle;
+	wire sel_last_addr_bf;
+	wire sel_next_addr_bf;
+	wire miss_f;
+	wire miss_a;
+	wire flush_fb;
+	wire dma_iccm_stall_any_f;
+	wire mb_empty_mod;
+	wire goto_idle;
+	wire leave_idle;
+	wire fetch_bf_en;
+	wire line_wrap;
+	wire fetch_addr_next_1;
+	wire [1:0] state;
+	wire [1:0] next_state;
+	wire dma_stall;
+	assign dma_stall = ic_dma_active | dma_iccm_stall_any_f;
+	generate
+		if (pt[2130-:5] == 1) begin
+			wire sel_btb_addr_bf;
+			assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
+			assign sel_btb_addr_bf = ((~exu_flush_final & ifc_fetch_req_f) & ifu_bp_hit_taken_f) & ic_hit_f;
+			assign sel_next_addr_bf = ((~exu_flush_final & ifc_fetch_req_f) & ~ifu_bp_hit_taken_f) & ic_hit_f;
+			assign fetch_addr_bf[31:1] = ((({31 {exu_flush_final}} & exu_flush_path_final[31:1]) | ({31 {sel_last_addr_bf}} & ifc_fetch_addr_f[31:1])) | ({31 {sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]})) | ({31 {sel_next_addr_bf}} & {fetch_addr_next[31:1]});
+		end
+		else begin
+			assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
+			assign sel_next_addr_bf = (~exu_flush_final & ifc_fetch_req_f) & ic_hit_f;
+			assign fetch_addr_bf[31:1] = (({31 {exu_flush_final}} & exu_flush_path_final[31:1]) | ({31 {sel_last_addr_bf}} & ifc_fetch_addr_f[31:1])) | ({31 {sel_next_addr_bf}} & {fetch_addr_next[31:1]});
+		end
+	endgenerate
+	assign fetch_addr_next[31:1] = {{ifc_fetch_addr_f[31:2]} + 31'b0000000000000000000000000000001, fetch_addr_next_1};
+	assign line_wrap = fetch_addr_next[pt[998-:7]] ^ ifc_fetch_addr_f[pt[998-:7]];
+	assign fetch_addr_next_1 = (line_wrap ? 1'b0 : ifc_fetch_addr_f[1]);
+	assign ifc_fetch_req_bf_raw = ~idle;
+	assign ifc_fetch_req_bf = (((ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(ifu_fb_consume2 | ifu_fb_consume1))) & ~dma_stall) & ~ic_write_stall) & ~dec_tlu_flush_noredir_wb;
+	assign fetch_bf_en = exu_flush_final | ifc_fetch_req_f;
+	assign miss_f = (ifc_fetch_req_f & ~ic_hit_f) & ~exu_flush_final;
+	assign mb_empty_mod = (((ifu_ic_mb_empty | exu_flush_final) & ~dma_stall) & ~miss_f) & ~miss_a;
+	assign goto_idle = exu_flush_final & dec_tlu_flush_noredir_wb;
+	assign leave_idle = (exu_flush_final & ~dec_tlu_flush_noredir_wb) & idle;
+	assign next_state[1] = (((~state[1] & state[0]) & miss_f) & ~goto_idle) | ((state[1] & ~mb_empty_mod) & ~goto_idle);
+	assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle);
+	assign flush_fb = exu_flush_final;
+	assign fb_right = ((ifu_fb_consume1 & ~ifu_fb_consume2) & (~ifc_fetch_req_f | miss_f)) | (ifu_fb_consume2 & ifc_fetch_req_f);
+	assign fb_right2 = ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f);
+	assign fb_left = (ifc_fetch_req_f & ~(ifu_fb_consume1 | ifu_fb_consume2)) & ~miss_f;
+	assign fb_write_ns[3:0] = (((({4 {flush_fb}} & 4'b0001) | ({4 {~flush_fb & fb_right}} & {1'b0, fb_write_f[3:1]})) | ({4 {~flush_fb & fb_right2}} & {2'b00, fb_write_f[3:2]})) | ({4 {~flush_fb & fb_left}} & {fb_write_f[2:0], 1'b0})) | ({4 {((~flush_fb & ~fb_right) & ~fb_right2) & ~fb_left}} & fb_write_f[3:0]);
+	assign fb_full_f_ns = fb_write_ns[3];
+	localparam [1:0] IDLE = 2'b00;
+	assign idle = state == IDLE;
+	localparam [1:0] WFM = 2'b11;
+	assign wfm = state == WFM;
+	rvdffie #(.WIDTH(10)) fbwrite_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({dma_iccm_stall_any, miss_f, ifc_fetch_req_bf, next_state[1:0], fb_full_f_ns, fb_write_ns[3:0]}),
+		.dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]})
+	);
+	assign ifu_pmu_fetch_stall = wfm | (ifc_fetch_req_bf_raw & ((fb_full_f & ~((ifu_fb_consume2 | ifu_fb_consume1) | exu_flush_final)) | dma_stall));
+	assign ifc_fetch_addr_bf[31:1] = fetch_addr_bf[31:1];
+	rvdffpcie #(.WIDTH(31)) faddrf1_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(fetch_bf_en),
+		.din(fetch_addr_bf[31:1]),
+		.dout(ifc_fetch_addr_f[31:1])
+	);
+	generate
+		if (pt[927-:5]) begin
+			wire iccm_acc_in_region_bf;
+			wire iccm_acc_in_range_bf;
+			rvrangecheck #(
+				.CCM_SADR(pt[887-:36]),
+				.CCM_SIZE(pt[851-:14])
+			) iccm_rangecheck(
+				.addr({ifc_fetch_addr_bf[31:1], 1'b0}),
+				.in_range(iccm_acc_in_range_bf),
+				.in_region(iccm_acc_in_region_bf)
+			);
+			assign ifc_iccm_access_bf = iccm_acc_in_range_bf;
+			assign ifc_dma_access_ok = ((((~ifc_iccm_access_bf | (fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1))) | (wfm & ~ifc_fetch_req_bf)) | idle) & ~exu_flush_final) | dma_iccm_stall_any_f;
+			assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf;
+		end
+		else begin
+			assign ifc_iccm_access_bf = 1'b0;
+			assign ifc_dma_access_ok = 1'b0;
+			assign ifc_region_acc_fault_bf = 1'b0;
+		end
+	endgenerate
+	assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{ifc_fetch_addr_bf[31:28], 1'b0}];
+endmodule
+module eb1_ifu_mem_ctl (
+	clk,
+	active_clk,
+	free_l2clk,
+	rst_l,
+	exu_flush_final,
+	dec_tlu_flush_lower_wb,
+	dec_tlu_flush_err_wb,
+	dec_tlu_i0_commit_cmt,
+	dec_tlu_force_halt,
+	ifc_fetch_addr_bf,
+	ifc_fetch_uncacheable_bf,
+	ifc_fetch_req_bf,
+	ifc_fetch_req_bf_raw,
+	ifc_iccm_access_bf,
+	ifc_region_acc_fault_bf,
+	ifc_dma_access_ok,
+	dec_tlu_fence_i_wb,
+	ifu_bp_hit_taken_f,
+	ifu_bp_inst_mask_f,
+	ifu_miss_state_idle,
+	ifu_ic_mb_empty,
+	ic_dma_active,
+	ic_write_stall,
+	ifu_pmu_ic_miss,
+	ifu_pmu_ic_hit,
+	ifu_pmu_bus_error,
+	ifu_pmu_bus_busy,
+	ifu_pmu_bus_trxn,
+	ifu_axi_awvalid,
+	ifu_axi_awid,
+	ifu_axi_awaddr,
+	ifu_axi_awregion,
+	ifu_axi_awlen,
+	ifu_axi_awsize,
+	ifu_axi_awburst,
+	ifu_axi_awlock,
+	ifu_axi_awcache,
+	ifu_axi_awprot,
+	ifu_axi_awqos,
+	ifu_axi_wvalid,
+	ifu_axi_wdata,
+	ifu_axi_wstrb,
+	ifu_axi_wlast,
+	ifu_axi_bready,
+	ifu_axi_arvalid,
+	ifu_axi_arready,
+	ifu_axi_arid,
+	ifu_axi_araddr,
+	ifu_axi_arregion,
+	ifu_axi_arlen,
+	ifu_axi_arsize,
+	ifu_axi_arburst,
+	ifu_axi_arlock,
+	ifu_axi_arcache,
+	ifu_axi_arprot,
+	ifu_axi_arqos,
+	ifu_axi_rvalid,
+	ifu_axi_rready,
+	ifu_axi_rid,
+	ifu_axi_rdata,
+	ifu_axi_rresp,
+	ifu_bus_clk_en,
+	dma_iccm_req,
+	dma_mem_addr,
+	dma_mem_sz,
+	dma_mem_write,
+	dma_mem_wdata,
+	dma_mem_tag,
+	iccm_dma_ecc_error,
+	iccm_dma_rvalid,
+	iccm_dma_rdata,
+	iccm_dma_rtag,
+	iccm_ready,
+	ic_rw_addr,
+	ic_wr_en,
+	ic_rd_en,
+	ic_wr_data,
+	ic_rd_data,
+	ic_debug_rd_data,
+	ictag_debug_rd_data,
+	ic_debug_wr_data,
+	ifu_ic_debug_rd_data,
+	ic_eccerr,
+	ic_parerr,
+	ic_debug_addr,
+	ic_debug_rd_en,
+	ic_debug_wr_en,
+	ic_debug_tag_array,
+	ic_debug_way,
+	ic_tag_valid,
+	ic_rd_hit,
+	ic_tag_perr,
+	iccm_rw_addr,
+	iccm_wren,
+	iccm_rden,
+	iccm_wr_data,
+	iccm_wr_size,
+	iccm_rd_data,
+	iccm_rd_data_ecc,
+	ifu_fetch_val,
+	ic_hit_f,
+	ic_access_fault_f,
+	ic_access_fault_type_f,
+	iccm_rd_ecc_single_err,
+	iccm_rd_ecc_double_err,
+	ic_error_start,
+	ifu_async_error_start,
+	iccm_dma_sb_error,
+	ic_fetch_val_f,
+	ic_data_f,
+	ic_premux_data,
+	ic_sel_premux_data,
+	dec_tlu_ic_diag_pkt,
+	dec_tlu_core_ecc_disable,
+	ifu_ic_debug_rd_data_valid,
+	iccm_buf_correct_ecc,
+	iccm_correction_state,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire active_clk;
+	input wire free_l2clk;
+	input wire rst_l;
+	input wire exu_flush_final;
+	input wire dec_tlu_flush_lower_wb;
+	input wire dec_tlu_flush_err_wb;
+	input wire dec_tlu_i0_commit_cmt;
+	input wire dec_tlu_force_halt;
+	input wire [31:1] ifc_fetch_addr_bf;
+	input wire ifc_fetch_uncacheable_bf;
+	input wire ifc_fetch_req_bf;
+	input wire ifc_fetch_req_bf_raw;
+	input wire ifc_iccm_access_bf;
+	input wire ifc_region_acc_fault_bf;
+	input wire ifc_dma_access_ok;
+	input wire dec_tlu_fence_i_wb;
+	input wire ifu_bp_hit_taken_f;
+	input wire ifu_bp_inst_mask_f;
+	output wire ifu_miss_state_idle;
+	output wire ifu_ic_mb_empty;
+	output wire ic_dma_active;
+	output wire ic_write_stall;
+	output wire ifu_pmu_ic_miss;
+	output wire ifu_pmu_ic_hit;
+	output wire ifu_pmu_bus_error;
+	output wire ifu_pmu_bus_busy;
+	output wire ifu_pmu_bus_trxn;
+	output wire ifu_axi_awvalid;
+	output wire [pt[826-:8] - 1:0] ifu_axi_awid;
+	output wire [31:0] ifu_axi_awaddr;
+	output wire [3:0] ifu_axi_awregion;
+	output wire [7:0] ifu_axi_awlen;
+	output wire [2:0] ifu_axi_awsize;
+	output wire [1:0] ifu_axi_awburst;
+	output wire ifu_axi_awlock;
+	output wire [3:0] ifu_axi_awcache;
+	output wire [2:0] ifu_axi_awprot;
+	output wire [3:0] ifu_axi_awqos;
+	output wire ifu_axi_wvalid;
+	output wire [63:0] ifu_axi_wdata;
+	output wire [7:0] ifu_axi_wstrb;
+	output wire ifu_axi_wlast;
+	output wire ifu_axi_bready;
+	output wire ifu_axi_arvalid;
+	input wire ifu_axi_arready;
+	output wire [pt[826-:8] - 1:0] ifu_axi_arid;
+	output wire [31:0] ifu_axi_araddr;
+	output wire [3:0] ifu_axi_arregion;
+	output wire [7:0] ifu_axi_arlen;
+	output wire [2:0] ifu_axi_arsize;
+	output wire [1:0] ifu_axi_arburst;
+	output wire ifu_axi_arlock;
+	output wire [3:0] ifu_axi_arcache;
+	output wire [2:0] ifu_axi_arprot;
+	output wire [3:0] ifu_axi_arqos;
+	input wire ifu_axi_rvalid;
+	output wire ifu_axi_rready;
+	input wire [pt[826-:8] - 1:0] ifu_axi_rid;
+	input wire [63:0] ifu_axi_rdata;
+	input wire [1:0] ifu_axi_rresp;
+	input wire ifu_bus_clk_en;
+	input wire dma_iccm_req;
+	input wire [31:0] dma_mem_addr;
+	input wire [2:0] dma_mem_sz;
+	input wire dma_mem_write;
+	input wire [63:0] dma_mem_wdata;
+	input wire [2:0] dma_mem_tag;
+	output wire iccm_dma_ecc_error;
+	output wire iccm_dma_rvalid;
+	output wire [63:0] iccm_dma_rdata;
+	output wire [2:0] iccm_dma_rtag;
+	output wire iccm_ready;
+	output wire [31:1] ic_rw_addr;
+	output wire [pt[1060-:7] - 1:0] ic_wr_en;
+	output wire ic_rd_en;
+	output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data;
+	input wire [63:0] ic_rd_data;
+	input wire [70:0] ic_debug_rd_data;
+	input wire [25:0] ictag_debug_rd_data;
+	output wire [70:0] ic_debug_wr_data;
+	output wire [70:0] ifu_ic_debug_rd_data;
+	input wire [pt[1189-:7] - 1:0] ic_eccerr;
+	input wire [pt[1189-:7] - 1:0] ic_parerr;
+	output wire [pt[1104-:9]:3] ic_debug_addr;
+	output wire ic_debug_rd_en;
+	output wire ic_debug_wr_en;
+	output wire ic_debug_tag_array;
+	output wire [pt[1060-:7] - 1:0] ic_debug_way;
+	output wire [pt[1060-:7] - 1:0] ic_tag_valid;
+	input wire [pt[1060-:7] - 1:0] ic_rd_hit;
+	input wire ic_tag_perr;
+	output wire [pt[936-:9] - 1:1] iccm_rw_addr;
+	output wire iccm_wren;
+	output wire iccm_rden;
+	output wire [77:0] iccm_wr_data;
+	output wire [2:0] iccm_wr_size;
+	input wire [63:0] iccm_rd_data;
+	input wire [77:0] iccm_rd_data_ecc;
+	input wire [1:0] ifu_fetch_val;
+	output wire ic_hit_f;
+	output wire [1:0] ic_access_fault_f;
+	output wire [1:0] ic_access_fault_type_f;
+	output wire iccm_rd_ecc_single_err;
+	output wire [1:0] iccm_rd_ecc_double_err;
+	output wire ic_error_start;
+	output wire ifu_async_error_start;
+	output wire iccm_dma_sb_error;
+	output wire [1:0] ic_fetch_val_f;
+	output wire [31:0] ic_data_f;
+	output wire [63:0] ic_premux_data;
+	output wire ic_sel_premux_data;
+	input wire [89:0] dec_tlu_ic_diag_pkt;
+	input wire dec_tlu_core_ecc_disable;
+	output wire ifu_ic_debug_rd_data_valid;
+	output wire iccm_buf_correct_ecc;
+	output reg iccm_correction_state;
+	input wire scan_mode;
+	localparam NUM_OF_BEATS = 8;
+	wire [31:3] ifu_ic_req_addr_f;
+	wire uncacheable_miss_in;
+	wire uncacheable_miss_ff;
+	wire bus_ifu_wr_en;
+	wire bus_ifu_wr_en_ff;
+	wire bus_ifu_wr_en_ff_q;
+	wire bus_ifu_wr_en_ff_wo_err;
+	wire [pt[1060-:7] - 1:0] bus_ic_wr_en;
+	wire reset_tag_valid_for_miss;
+	reg [pt[1027-:7] - 1:0] way_status;
+	wire [pt[1027-:7] - 1:0] way_status_mb_in;
+	wire [pt[1027-:7] - 1:0] way_status_rep_new;
+	wire [pt[1027-:7] - 1:0] way_status_mb_ff;
+	wire [pt[1027-:7] - 1:0] way_status_new;
+	wire [pt[1027-:7] - 1:0] way_status_hit_new;
+	wire [pt[1027-:7] - 1:0] way_status_new_w_debug;
+	wire [pt[1060-:7] - 1:0] tagv_mb_in;
+	wire [pt[1060-:7] - 1:0] tagv_mb_ff;
+	wire ifu_wr_data_comb_err;
+	wire ifu_byp_data_err_new;
+	wire [1:0] ifu_byp_data_err_f;
+	wire ifu_wr_cumulative_err_data;
+	wire ifu_wr_cumulative_err;
+	wire ifu_wr_data_comb_err_ff;
+	wire scnd_miss_index_match;
+	wire ifc_dma_access_q_ok;
+	wire ifc_iccm_access_f;
+	wire ifc_region_acc_fault_f;
+	wire ifc_region_acc_fault_final_f;
+	wire [1:0] ifc_bus_acc_fault_f;
+	wire ic_act_miss_f;
+	wire ic_miss_under_miss_f;
+	wire ic_ignore_2nd_miss_f;
+	wire ic_act_hit_f;
+	wire miss_pending;
+	wire [31:1] imb_in;
+	wire [31:1] imb_ff;
+	wire [31:pt[1182-:8] + 1] miss_addr_in;
+	wire [31:pt[1182-:8] + 1] miss_addr;
+	wire miss_wrap_f;
+	wire flush_final_f;
+	wire ifc_fetch_req_f;
+	wire ifc_fetch_req_f_raw;
+	wire fetch_req_f_qual;
+	wire ifc_fetch_req_qual_bf;
+	wire [pt[1060-:7] - 1:0] replace_way_mb_any;
+	wire last_beat;
+	wire reset_beat_cnt;
+	wire [pt[1182-:8]:3] ic_req_addr_bits_hi_3;
+	wire [pt[1182-:8]:3] ic_wr_addr_bits_hi_3;
+	wire [31:1] ifu_fetch_addr_int_f;
+	wire [31:1] ifu_ic_rw_int_addr;
+	wire crit_wd_byp_ok_ff;
+	wire ic_crit_wd_rdy_new_ff;
+	wire [79:0] ic_byp_data_only_pre_new;
+	wire [79:0] ic_byp_data_only_new;
+	wire ic_byp_hit_f;
+	wire ic_valid;
+	wire ic_valid_ff;
+	wire reset_all_tags;
+	wire ic_valid_w_debug;
+	wire [pt[1060-:7] - 1:0] ifu_tag_wren;
+	wire [pt[1060-:7] - 1:0] ifu_tag_wren_ff;
+	wire [pt[1060-:7] - 1:0] ic_debug_tag_wr_en;
+	wire [pt[1060-:7] - 1:0] ifu_tag_wren_w_debug;
+	wire [pt[1060-:7] - 1:0] ic_debug_way_ff;
+	wire ic_debug_rd_en_ff;
+	wire fetch_bf_f_c1_clken;
+	wire fetch_bf_f_c1_clk;
+	wire debug_c1_clken;
+	wire debug_c1_clk;
+	wire reset_ic_in;
+	wire reset_ic_ff;
+	wire [pt[1182-:8]:1] vaddr_f;
+	wire [31:1] ifu_status_wr_addr;
+	wire sel_mb_addr;
+	wire sel_mb_addr_ff;
+	wire sel_mb_status_addr;
+	wire [63:0] ic_final_data;
+	wire [pt[1104-:9]:pt[998-:7]] ifu_ic_rw_int_addr_ff;
+	wire [pt[1104-:9]:pt[998-:7]] ifu_status_wr_addr_ff;
+	wire [pt[1104-:9]:pt[998-:7]] ifu_ic_rw_int_addr_w_debug;
+	wire [pt[1104-:9]:pt[998-:7]] ifu_status_wr_addr_w_debug;
+	wire [pt[1027-:7] - 1:0] way_status_new_ff;
+	wire way_status_wr_en_ff;
+	wire [(pt[1015-:17] * pt[1027-:7]) - 1:0] way_status_out;
+	wire [1:0] ic_debug_way_enc;
+	wire [pt[826-:8] - 1:0] ifu_bus_rid_ff;
+	wire fetch_req_icache_f;
+	wire fetch_req_iccm_f;
+	wire ic_iccm_hit_f;
+	wire fetch_uncacheable_ff;
+	wire way_status_wr_en;
+	wire sel_byp_data;
+	wire sel_ic_data;
+	wire sel_iccm_data;
+	wire ic_rd_parity_final_err;
+	wire ic_act_miss_f_delayed;
+	wire bus_ifu_wr_data_error;
+	wire bus_ifu_wr_data_error_ff;
+	wire way_status_wr_en_w_debug;
+	wire ic_debug_tag_val_rd_out;
+	wire ifu_pmu_ic_miss_in;
+	wire ifu_pmu_ic_hit_in;
+	wire ifu_pmu_bus_error_in;
+	wire ifu_pmu_bus_trxn_in;
+	wire ifu_pmu_bus_busy_in;
+	wire ic_debug_ict_array_sel_in;
+	wire ic_debug_ict_array_sel_ff;
+	wire debug_data_clken;
+	wire last_data_recieved_in;
+	wire last_data_recieved_ff;
+	wire ifu_bus_rvalid;
+	wire ifu_bus_rvalid_ff;
+	wire ifu_bus_rvalid_unq_ff;
+	wire ifu_bus_arready_unq;
+	wire ifu_bus_arready_unq_ff;
+	wire ifu_bus_arvalid;
+	wire ifu_bus_arvalid_ff;
+	wire ifu_bus_arready;
+	wire ifu_bus_arready_ff;
+	wire [63:0] ifu_bus_rdata_ff;
+	wire [1:0] ifu_bus_rresp_ff;
+	wire ifu_bus_rsp_valid;
+	wire ifu_bus_rsp_ready;
+	wire [pt[826-:8] - 1:0] ifu_bus_rsp_tag;
+	wire [63:0] ifu_bus_rsp_rdata;
+	wire [1:0] ifu_bus_rsp_opc;
+	wire [pt[1084-:8] - 1:0] write_fill_data;
+	wire [pt[1084-:8] - 1:0] wr_data_c1_clk;
+	wire [pt[1084-:8] - 1:0] ic_miss_buff_data_valid_in;
+	wire [pt[1084-:8] - 1:0] ic_miss_buff_data_valid;
+	wire [pt[1084-:8] - 1:0] ic_miss_buff_data_error_in;
+	wire [pt[1084-:8] - 1:0] ic_miss_buff_data_error;
+	wire [pt[1182-:8]:1] byp_fetch_index;
+	wire [pt[1182-:8]:2] byp_fetch_index_0;
+	wire [pt[1182-:8]:2] byp_fetch_index_1;
+	wire [pt[1182-:8]:3] byp_fetch_index_inc;
+	wire [pt[1182-:8]:2] byp_fetch_index_inc_0;
+	wire [pt[1182-:8]:2] byp_fetch_index_inc_1;
+	wire miss_buff_hit_unq_f;
+	wire stream_hit_f;
+	wire stream_miss_f;
+	wire stream_eol_f;
+	wire crit_byp_hit_f;
+	wire [pt[826-:8] - 1:0] other_tag;
+	wire [((2 * pt[1084-:8]) * 32) - 1:0] ic_miss_buff_data;
+	wire [63:0] ic_miss_buff_half;
+	wire scnd_miss_req;
+	wire scnd_miss_req_q;
+	wire scnd_miss_req_in;
+	wire [pt[936-:9] - 1:2] iccm_ecc_corr_index_ff;
+	wire [pt[936-:9] - 1:2] iccm_ecc_corr_index_in;
+	wire [38:0] iccm_ecc_corr_data_ff;
+	wire iccm_ecc_write_status;
+	wire iccm_rd_ecc_single_err_ff;
+	wire iccm_error_start;
+	reg perr_state_en;
+	reg miss_state_en;
+	wire busclk;
+	wire busclk_force;
+	wire busclk_reset;
+	wire bus_ifu_bus_clk_en_ff;
+	wire bus_ifu_bus_clk_en;
+	wire ifc_bus_ic_req_ff_in;
+	wire ifu_bus_cmd_valid;
+	wire ifu_bus_cmd_ready;
+	wire bus_inc_data_beat_cnt;
+	wire bus_reset_data_beat_cnt;
+	wire bus_hold_data_beat_cnt;
+	wire bus_inc_cmd_beat_cnt;
+	wire bus_reset_cmd_beat_cnt_0;
+	wire bus_reset_cmd_beat_cnt_secondlast;
+	wire bus_hold_cmd_beat_cnt;
+	wire [pt[1174-:8] - 1:0] bus_new_data_beat_count;
+	wire [pt[1174-:8] - 1:0] bus_data_beat_count;
+	wire [pt[1174-:8] - 1:0] bus_new_cmd_beat_count;
+	wire [pt[1174-:8] - 1:0] bus_cmd_beat_count;
+	wire [pt[1174-:8] - 1:0] bus_new_rd_addr_count;
+	wire [pt[1174-:8] - 1:0] bus_rd_addr_count;
+	wire bus_cmd_sent;
+	wire bus_last_data_beat;
+	wire [pt[1060-:7] - 1:0] bus_wren;
+	wire [pt[1060-:7] - 1:0] bus_wren_last;
+	wire [pt[1060-:7] - 1:0] wren_reset_miss;
+	wire ifc_dma_access_ok_d;
+	wire ifc_dma_access_ok_prev;
+	wire bus_cmd_req_in;
+	wire bus_cmd_req_hold;
+	wire second_half_available;
+	wire write_ic_16_bytes;
+	wire ifc_region_acc_fault_final_bf;
+	wire ifc_region_acc_fault_memory_bf;
+	wire ifc_region_acc_fault_memory_f;
+	wire ifc_region_acc_okay;
+	wire iccm_correct_ecc;
+	wire dma_sb_err_state;
+	wire dma_sb_err_state_ff;
+	wire two_byte_instr;
+	wire [2:0] miss_state;
+	reg [2:0] miss_nxtstate;
+	wire [1:0] err_stop_state;
+	reg [1:0] err_stop_nxtstate;
+	reg err_stop_state_en;
+	reg err_stop_fetch;
+	wire ic_crit_wd_rdy;
+	wire ifu_bp_hit_taken_q_f;
+	wire ifu_bus_rvalid_unq;
+	wire bus_cmd_beat_en;
+	assign fetch_bf_f_c1_clken = (((ifc_fetch_req_bf_raw | ifc_fetch_req_f) | miss_pending) | exu_flush_final) | scnd_miss_req;
+	assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en;
+	rvclkhdr fetch_bf_f_c1_cgc(
+		.en(fetch_bf_f_c1_clken),
+		.l1clk(fetch_bf_f_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr debug_c1_cgc(
+		.en(debug_c1_clken),
+		.l1clk(debug_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	wire [1:0] iccm_single_ecc_error;
+	wire dma_iccm_req_f;
+	assign iccm_dma_sb_error = |iccm_single_ecc_error[1:0] & dma_iccm_req_f;
+	assign ifu_async_error_start = iccm_rd_ecc_single_err | ic_error_start;
+	wire [2:0] perr_state;
+	reg [2:0] perr_nxtstate;
+	localparam [2:0] DMA_SB_ERR = 3'b100;
+	localparam [1:0] ERR_STOP_FETCH = 2'b11;
+	assign ic_dma_active = (((iccm_correct_ecc | (perr_state == DMA_SB_ERR)) | (err_stop_state == ERR_STOP_FETCH)) | err_stop_fetch) | dec_tlu_flush_err_wb;
+	localparam [2:0] SCND_MISS = 3'b101;
+	assign scnd_miss_req_in = (((((ifu_bus_rsp_valid & bus_ifu_bus_clk_en) & ifu_bus_rsp_ready) & &bus_new_data_beat_count[pt[1174-:8] - 1:0]) & ~uncacheable_miss_ff) & ((miss_state == SCND_MISS) | (miss_nxtstate == SCND_MISS))) & ~exu_flush_final;
+	assign ifu_bp_hit_taken_q_f = ifu_bp_hit_taken_f & ic_hit_f;
+	localparam [2:0] CRIT_BYP_OK = 3'b001;
+	localparam [2:0] CRIT_WRD_RDY = 3'b100;
+	localparam [2:0] HIT_U_MISS = 3'b010;
+	localparam [2:0] IDLE = 3'b000;
+	localparam [2:0] MISS_WAIT = 3'b011;
+	localparam [2:0] STALL_SCND_MISS = 3'b111;
+	localparam [2:0] STREAM = 3'b110;
+	always @(*) begin : MISS_SM
+		miss_nxtstate = IDLE;
+		miss_state_en = 1'b0;
+		case (miss_state)
+			IDLE: begin : idle
+				miss_nxtstate = (ic_act_miss_f & ~exu_flush_final ? CRIT_BYP_OK : HIT_U_MISS);
+				miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt;
+			end
+			CRIT_BYP_OK: begin : crit_byp_ok
+				miss_nxtstate = (dec_tlu_force_halt ? IDLE : ((ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat))) & uncacheable_miss_ff ? IDLE : ((ic_byp_hit_f & ~last_data_recieved_ff) & uncacheable_miss_ff ? MISS_WAIT : (((~ic_byp_hit_f & ~exu_flush_final) & (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff ? CRIT_WRD_RDY : ((bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff ? IDLE : ((((ic_byp_hit_f & ~exu_flush_final) & ~(bus_ifu_wr_en_ff & last_beat)) & ~ifu_bp_hit_taken_q_f) & ~uncacheable_miss_ff ? STREAM : ((((bus_ifu_wr_en_ff & ~exu_flush_final) & ~(bus_ifu_wr_en_ff & last_beat)) & ~ifu_bp_hit_taken_q_f) & ~uncacheable_miss_ff ? STREAM : (((~ic_byp_hit_f & ~exu_flush_final) & (bus_ifu_wr_en_ff & last_beat)) & ~uncacheable_miss_ff ? IDLE : ((exu_flush_final | ifu_bp_hit_taken_q_f) & ~(bus_ifu_wr_en_ff & last_beat) ? HIT_U_MISS : IDLE)))))))));
+				miss_state_en = ((((dec_tlu_force_halt | exu_flush_final) | ic_byp_hit_f) | ifu_bp_hit_taken_q_f) | (bus_ifu_wr_en_ff & last_beat)) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff);
+			end
+			CRIT_WRD_RDY: begin : crit_wrd_rdy
+				miss_nxtstate = IDLE;
+				miss_state_en = ((exu_flush_final | flush_final_f) | ic_byp_hit_f) | dec_tlu_force_halt;
+			end
+			STREAM: begin : stream
+				miss_nxtstate = ((((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f) & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? HIT_U_MISS : IDLE);
+				miss_state_en = (((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f) | (bus_ifu_wr_en_ff & last_beat)) | dec_tlu_force_halt;
+			end
+			MISS_WAIT: begin : miss_wait
+				miss_nxtstate = ((exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? HIT_U_MISS : IDLE);
+				miss_state_en = (exu_flush_final | (bus_ifu_wr_en_ff & last_beat)) | dec_tlu_force_halt;
+			end
+			HIT_U_MISS: begin : hit_u_miss
+				miss_nxtstate = ((ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? SCND_MISS : ((ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE));
+				miss_state_en = (((bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f) | ic_ignore_2nd_miss_f) | dec_tlu_force_halt;
+			end
+			SCND_MISS: begin : scnd_miss
+				miss_nxtstate = (dec_tlu_force_halt ? IDLE : (exu_flush_final ? (bus_ifu_wr_en_ff & last_beat ? IDLE : HIT_U_MISS) : CRIT_BYP_OK));
+				miss_state_en = ((bus_ifu_wr_en_ff & last_beat) | exu_flush_final) | dec_tlu_force_halt;
+			end
+			STALL_SCND_MISS: begin : stall_scnd_miss
+				miss_nxtstate = (dec_tlu_force_halt ? IDLE : (exu_flush_final ? (bus_ifu_wr_en_ff & last_beat ? IDLE : HIT_U_MISS) : IDLE));
+				miss_state_en = ((bus_ifu_wr_en_ff & last_beat) | exu_flush_final) | dec_tlu_force_halt;
+			end
+			default: begin : def_case
+				miss_nxtstate = IDLE;
+				miss_state_en = 1'b0;
+			end
+		endcase
+	end
+	rvdffs #(.WIDTH(3)) miss_state_ff(
+		.clk(active_clk),
+		.din(miss_nxtstate),
+		.dout({miss_state}),
+		.en(miss_state_en),
+		.rst_l(rst_l)
+	);
+	wire sel_hold_imb;
+	assign miss_pending = miss_state != IDLE;
+	assign crit_wd_byp_ok_ff = (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);
+	assign sel_hold_imb = ((((miss_pending & ~(bus_ifu_wr_en_ff & last_beat)) & ~((miss_state == CRIT_WRD_RDY) & exu_flush_final)) & ~((miss_state == CRIT_WRD_RDY) & crit_byp_hit_f)) | ic_act_miss_f) | (miss_pending & (miss_nxtstate == CRIT_WRD_RDY));
+	wire sel_hold_imb_scnd;
+	wire [31:1] imb_scnd_in;
+	wire [31:1] imb_scnd_ff;
+	wire uncacheable_miss_scnd_in;
+	wire uncacheable_miss_scnd_ff;
+	wire [pt[1060-:7] - 1:0] tagv_mb_scnd_in;
+	wire [pt[1060-:7] - 1:0] tagv_mb_scnd_ff;
+	wire [pt[1027-:7] - 1:0] way_status_mb_scnd_in;
+	wire [pt[1027-:7] - 1:0] way_status_mb_scnd_ff;
+	assign sel_hold_imb_scnd = ((miss_state == SCND_MISS) | ic_miss_under_miss_f) & ~flush_final_f;
+	assign way_status_mb_scnd_in[pt[1027-:7] - 1:0] = (miss_state == SCND_MISS ? way_status_mb_scnd_ff[pt[1027-:7] - 1:0] : {way_status[pt[1027-:7] - 1:0]});
+	assign tagv_mb_scnd_in[pt[1060-:7] - 1:0] = (miss_state == SCND_MISS ? tagv_mb_scnd_ff[pt[1060-:7] - 1:0] : {ic_tag_valid[pt[1060-:7] - 1:0]} & {pt[1060-:7] {~reset_all_tags & ~exu_flush_final}});
+	assign uncacheable_miss_scnd_in = (sel_hold_imb_scnd ? uncacheable_miss_scnd_ff : ifc_fetch_uncacheable_bf);
+	rvdff_fpga #(.WIDTH(1)) unc_miss_scnd_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din(uncacheable_miss_scnd_in),
+		.dout(uncacheable_miss_scnd_ff)
+	);
+	rvdffpcie #(.WIDTH(31)) imb_f_scnd_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(fetch_bf_f_c1_clken),
+		.din({imb_scnd_in[31:1]}),
+		.dout({imb_scnd_ff[31:1]})
+	);
+	rvdff_fpga #(.WIDTH(pt[1027-:7])) mb_rep_wayf2_scnd_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din({way_status_mb_scnd_in[pt[1027-:7] - 1:0]}),
+		.dout({way_status_mb_scnd_ff[pt[1027-:7] - 1:0]})
+	);
+	rvdff_fpga #(.WIDTH(pt[1060-:7])) mb_tagv_scnd_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din({tagv_mb_scnd_in[pt[1060-:7] - 1:0]}),
+		.dout({tagv_mb_scnd_ff[pt[1060-:7] - 1:0]})
+	);
+	assign ic_req_addr_bits_hi_3[pt[1182-:8]:3] = bus_rd_addr_count[pt[1174-:8] - 1:0];
+	assign ic_wr_addr_bits_hi_3[pt[1182-:8]:3] = ifu_bus_rid_ff[pt[1174-:8] - 1:0] & {pt[1174-:8] {bus_ifu_wr_en_ff}};
+	assign fetch_req_icache_f = (ifc_fetch_req_f & ~ifc_iccm_access_f) & ~ifc_region_acc_fault_final_f;
+	assign fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f;
+	assign ic_iccm_hit_f = fetch_req_iccm_f & ((~miss_pending | (miss_state == HIT_U_MISS)) | (miss_state == STREAM));
+	assign ic_byp_hit_f = ((crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f) & miss_pending;
+	assign ic_act_hit_f = (((|ic_rd_hit[pt[1060-:7] - 1:0] & fetch_req_icache_f) & ~reset_all_tags) & (~miss_pending | (miss_state == HIT_U_MISS))) & ~sel_mb_addr_ff;
+	assign ic_act_miss_f = ((((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & ~miss_pending) | scnd_miss_req) & ~ifc_region_acc_fault_final_f;
+	assign ic_miss_under_miss_f = ((((((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & (miss_state == HIT_U_MISS)) & (imb_ff[31:pt[998-:7]] != ifu_fetch_addr_int_f[31:pt[998-:7]])) & ~uncacheable_miss_ff) & ~sel_mb_addr_ff) & ~ifc_region_acc_fault_final_f;
+	assign ic_ignore_2nd_miss_f = (((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & (miss_state == HIT_U_MISS)) & ((imb_ff[31:pt[998-:7]] == ifu_fetch_addr_int_f[31:pt[998-:7]]) | uncacheable_miss_ff);
+	assign ic_hit_f = ((ic_act_hit_f | ic_byp_hit_f) | ic_iccm_hit_f) | (ifc_region_acc_fault_final_f & ifc_fetch_req_f);
+	assign uncacheable_miss_in = (scnd_miss_req ? uncacheable_miss_scnd_ff : (sel_hold_imb ? uncacheable_miss_ff : ifc_fetch_uncacheable_bf));
+	assign imb_in[31:1] = (scnd_miss_req ? imb_scnd_ff[31:1] : (sel_hold_imb ? imb_ff[31:1] : {ifc_fetch_addr_bf[31:1]}));
+	assign imb_scnd_in[31:1] = (sel_hold_imb_scnd ? imb_scnd_ff[31:1] : {ifc_fetch_addr_bf[31:1]});
+	assign scnd_miss_index_match = ((imb_ff[pt[1104-:9]:pt[998-:7]] == imb_scnd_ff[pt[1104-:9]:pt[998-:7]]) & scnd_miss_req) & ~ifu_wr_cumulative_err_data;
+	assign way_status_mb_in[pt[1027-:7] - 1:0] = (scnd_miss_req & ~scnd_miss_index_match ? way_status_mb_scnd_ff[pt[1027-:7] - 1:0] : (scnd_miss_req & scnd_miss_index_match ? way_status_rep_new[pt[1027-:7] - 1:0] : (miss_pending ? way_status_mb_ff[pt[1027-:7] - 1:0] : {way_status[pt[1027-:7] - 1:0]})));
+	assign tagv_mb_in[pt[1060-:7] - 1:0] = (scnd_miss_req ? tagv_mb_scnd_ff[pt[1060-:7] - 1:0] | ({pt[1060-:7] {scnd_miss_index_match}} & replace_way_mb_any[pt[1060-:7] - 1:0]) : (miss_pending ? tagv_mb_ff[pt[1060-:7] - 1:0] : {ic_tag_valid[pt[1060-:7] - 1:0]} & {pt[1060-:7] {~reset_all_tags & ~exu_flush_final}}));
+	assign reset_ic_in = (miss_pending & ~scnd_miss_req_q) & (reset_all_tags | reset_ic_ff);
+	rvdffpcie #(.WIDTH(31)) ifu_fetch_addr_f_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(fetch_bf_f_c1_clken),
+		.din({ifc_fetch_addr_bf[31:1]}),
+		.dout({ifu_fetch_addr_int_f[31:1]})
+	);
+	assign vaddr_f[pt[1182-:8]:1] = ifu_fetch_addr_int_f[pt[1182-:8]:1];
+	rvdffpcie #(.WIDTH(31)) imb_f_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(fetch_bf_f_c1_clken),
+		.din(imb_in[31:1]),
+		.dout(imb_ff[31:1])
+	);
+	rvdff_fpga #(.WIDTH(1)) unc_miss_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din(uncacheable_miss_in),
+		.dout(uncacheable_miss_ff)
+	);
+	assign miss_addr_in[31:pt[1182-:8] + 1] = (~miss_pending ? imb_ff[31:pt[1182-:8] + 1] : (scnd_miss_req_q ? imb_scnd_ff[31:pt[1182-:8] + 1] : miss_addr[31:pt[1182-:8] + 1]));
+	rvdfflie #(
+		.WIDTH(31 - pt[1182-:8]),
+		.LEFT((31 - pt[1182-:8]) - 8)
+	) miss_f_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt),
+		.din({miss_addr_in[31:pt[1182-:8] + 1]}),
+		.dout({miss_addr[31:pt[1182-:8] + 1]})
+	);
+	rvdff_fpga #(.WIDTH(pt[1027-:7])) mb_rep_wayf2_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din({way_status_mb_in[pt[1027-:7] - 1:0]}),
+		.dout({way_status_mb_ff[pt[1027-:7] - 1:0]})
+	);
+	rvdff_fpga #(.WIDTH(pt[1060-:7])) mb_tagv_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din({tagv_mb_in[pt[1060-:7] - 1:0]}),
+		.dout({tagv_mb_ff[pt[1060-:7] - 1:0]})
+	);
+	assign ifc_fetch_req_qual_bf = (ifc_fetch_req_bf & ~((miss_state == CRIT_WRD_RDY) & flush_final_f)) & ~stream_miss_f;
+	assign ifc_fetch_req_f = ifc_fetch_req_f_raw & ~exu_flush_final;
+	rvdff_fpga #(.WIDTH(1)) ifu_iccm_acc_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din(ifc_iccm_access_bf),
+		.dout(ifc_iccm_access_f)
+	);
+	rvdff_fpga #(.WIDTH(1)) ifu_iccm_reg_acc_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din(ifc_region_acc_fault_final_bf),
+		.dout(ifc_region_acc_fault_final_f)
+	);
+	rvdff_fpga #(.WIDTH(1)) rgn_acc_ff(
+		.rst_l(rst_l),
+		.clk(fetch_bf_f_c1_clk),
+		.clken(fetch_bf_f_c1_clken),
+		.rawclk(clk),
+		.din(ifc_region_acc_fault_bf),
+		.dout(ifc_region_acc_fault_f)
+	);
+	assign ifu_ic_req_addr_f[31:3] = {miss_addr[31:pt[1182-:8] + 1], ic_req_addr_bits_hi_3[pt[1182-:8]:3]};
+	assign ifu_ic_mb_empty = (((miss_state == HIT_U_MISS) | (miss_state == STREAM)) & ~(bus_ifu_wr_en_ff & last_beat)) | ~miss_pending;
+	assign ifu_miss_state_idle = miss_state == IDLE;
+	assign sel_mb_addr = ((miss_pending & write_ic_16_bytes) & ~uncacheable_miss_ff) | reset_tag_valid_for_miss;
+	assign ifu_ic_rw_int_addr[31:1] = ({31 {sel_mb_addr}} & {imb_ff[31:pt[1182-:8] + 1], ic_wr_addr_bits_hi_3[pt[1182-:8]:3], imb_ff[2:1]}) | ({31 {~sel_mb_addr}} & ifc_fetch_addr_bf[31:1]);
+	assign sel_mb_status_addr = ((((miss_pending & write_ic_16_bytes) & ~uncacheable_miss_ff) & last_beat) & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss;
+	assign ifu_status_wr_addr[31:1] = ({31 {sel_mb_status_addr}} & {imb_ff[31:pt[1182-:8] + 1], ic_wr_addr_bits_hi_3[pt[1182-:8]:3], imb_ff[2:1]}) | ({31 {~sel_mb_status_addr}} & ifu_fetch_addr_int_f[31:1]);
+	assign ic_rw_addr[31:1] = ifu_ic_rw_int_addr[31:1];
+	generate
+		if (pt[1125-:5] == 1) begin : icache_ecc_1
+			wire [6:0] ic_wr_ecc;
+			wire [6:0] ic_miss_buff_ecc;
+			wire [141:0] ic_wr_16bytes_data;
+			wire [70:0] ifu_ic_debug_rd_data_in;
+			rvecc_encode_64 ic_ecc_encode_64_bus(
+				.din(ifu_bus_rdata_ff[63:0]),
+				.ecc_out(ic_wr_ecc[6:0])
+			);
+			rvecc_encode_64 ic_ecc_encode_64_buff(
+				.din(ic_miss_buff_half[63:0]),
+				.ecc_out(ic_miss_buff_ecc[6:0])
+			);
+			genvar i;
+			for (i = 0; i < pt[1189-:7]; i = i + 1) begin : ic_wr_data_loop
+				assign ic_wr_data[(i * 71) + 70-:71] = ic_wr_16bytes_data[(71 * i) + 70:71 * i];
+			end
+			assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt[89:19]};
+			assign ic_error_start = (|ic_eccerr[pt[1189-:7] - 1:0] & ic_act_hit_f) | ic_rd_parity_final_err;
+			assign ifu_ic_debug_rd_data_in[70:0] = (ic_debug_ict_array_sel_ff ? {2'b00, ictag_debug_rd_data[25:21], 32'b00000000000000000000000000000000, ictag_debug_rd_data[20:0], {7 - pt[1027-:7] {1'b0}}, way_status[pt[1027-:7] - 1:0], 3'b000, ic_debug_tag_val_rd_out} : ic_debug_rd_data[70:0]);
+			rvdffe #(.WIDTH(71)) ifu_debug_data_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(debug_data_clken),
+				.din({ifu_ic_debug_rd_data_in[70:0]}),
+				.dout({ifu_ic_debug_rd_data[70:0]})
+			);
+			assign ic_wr_16bytes_data[141:0] = (ifu_bus_rid_ff[0] ? {ic_wr_ecc[6:0], ifu_bus_rdata_ff[63:0], ic_miss_buff_ecc[6:0], ic_miss_buff_half[63:0]} : {ic_miss_buff_ecc[6:0], ic_miss_buff_half[63:0], ic_wr_ecc[6:0], ifu_bus_rdata_ff[63:0]});
+		end
+		else begin : icache_parity_1
+			wire [3:0] ic_wr_parity;
+			wire [3:0] ic_miss_buff_parity;
+			wire [135:0] ic_wr_16bytes_data;
+			wire [70:0] ifu_ic_debug_rd_data_in;
+			genvar i;
+			for (i = 0; i < 4; i = i + 1) begin : DATA_PGEN
+				rveven_paritygen #(.WIDTH(16)) par_bus(
+					.data_in(ifu_bus_rdata_ff[(16 * i) + 15:16 * i]),
+					.parity_out(ic_wr_parity[i])
+				);
+				rveven_paritygen #(.WIDTH(16)) par_buff(
+					.data_in(ic_miss_buff_half[(16 * i) + 15:16 * i]),
+					.parity_out(ic_miss_buff_parity[i])
+				);
+			end
+			for (i = 0; i < pt[1189-:7]; i = i + 1) begin : ic_wr_data_loop
+				assign ic_wr_data[(i * 71) + 70-:71] = {3'b000, ic_wr_16bytes_data[(68 * i) + 67:68 * i]};
+			end
+			assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt[89:19]};
+			assign ic_error_start = (|ic_parerr[pt[1189-:7] - 1:0] & ic_act_hit_f) | ic_rd_parity_final_err;
+			assign ifu_ic_debug_rd_data_in[70:0] = (ic_debug_ict_array_sel_ff ? {6'b000000, ictag_debug_rd_data[21], 32'b00000000000000000000000000000000, ictag_debug_rd_data[20:0], {7 - pt[1027-:7] {1'b0}}, way_status[pt[1027-:7] - 1:0], 3'b000, ic_debug_tag_val_rd_out} : ic_debug_rd_data[70:0]);
+			rvdffe #(.WIDTH(71)) ifu_debug_data_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(debug_data_clken),
+				.din({ifu_ic_debug_rd_data_in[70:0]}),
+				.dout({ifu_ic_debug_rd_data[70:0]})
+			);
+			assign ic_wr_16bytes_data[135:0] = (ifu_bus_rid_ff[0] ? {ic_wr_parity[3:0], ifu_bus_rdata_ff[63:0], ic_miss_buff_parity[3:0], ic_miss_buff_half[63:0]} : {ic_miss_buff_parity[3:0], ic_miss_buff_half[63:0], ic_wr_parity[3:0], ifu_bus_rdata_ff[63:0]});
+		end
+	endgenerate
+	assign ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff;
+	assign ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & ~reset_beat_cnt;
+	assign ifu_wr_cumulative_err_data = ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff;
+	assign sel_byp_data = (ic_crit_wd_rdy | (miss_state == STREAM)) | (miss_state == CRIT_BYP_OK);
+	assign sel_ic_data = (~(((ic_crit_wd_rdy | (miss_state == STREAM)) | (miss_state == CRIT_BYP_OK)) | (miss_state == MISS_WAIT)) & ~fetch_req_iccm_f) & ~ifc_region_acc_fault_final_f;
+	generate
+		if (pt[922-:5] == 1) begin : iccm_icache
+			assign sel_iccm_data = fetch_req_iccm_f;
+			assign ic_final_data[63:0] = {64 {(sel_byp_data | sel_iccm_data) | sel_ic_data}} & {ic_rd_data[63:0]};
+			assign ic_premux_data[63:0] = ({64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}) | ({64 {sel_iccm_data}} & {iccm_rd_data[63:0]});
+			assign ic_sel_premux_data = sel_iccm_data | sel_byp_data;
+		end
+	endgenerate
+	generate
+		if (pt[900-:5] == 1) begin : iccm_only
+			assign sel_iccm_data = fetch_req_iccm_f;
+			assign ic_final_data[63:0] = ({64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}) | ({64 {sel_iccm_data}} & {iccm_rd_data[63:0]});
+			assign ic_premux_data = {64 {1'sb0}};
+			assign ic_sel_premux_data = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[1053-:5] == 1) begin : icache_only
+			assign ic_final_data[63:0] = {64 {sel_byp_data | sel_ic_data}} & {ic_rd_data[63:0]};
+			assign ic_premux_data[63:0] = {64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]};
+			assign ic_sel_premux_data = sel_byp_data;
+		end
+	endgenerate
+	generate
+		if (pt[140-:5] == 1) begin : no_iccm_no_icache
+			assign ic_final_data[63:0] = {64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]};
+			assign ic_premux_data = 0;
+			assign ic_sel_premux_data = 1'b0;
+		end
+	endgenerate
+	assign ifc_bus_acc_fault_f[1:0] = {2 {ic_byp_hit_f}} & ifu_byp_data_err_f[1:0];
+	assign ic_data_f[31:0] = ic_final_data[31:0];
+	assign fetch_req_f_qual = ic_hit_f & ~exu_flush_final;
+	assign ic_access_fault_f[1:0] = ({2 {ifc_region_acc_fault_final_f}} | ifc_bus_acc_fault_f[1:0]) & {2 {~exu_flush_final}};
+	assign ic_access_fault_type_f[1:0] = (|iccm_rd_ecc_double_err ? 2'b01 : (ifc_region_acc_fault_f ? 2'b10 : (ifc_region_acc_fault_memory_f ? 2'b11 : 2'b00)));
+	localparam [1:0] ERR_FETCH2 = 2'b10;
+	assign ic_fetch_val_f[1] = ((fetch_req_f_qual & ifu_bp_inst_mask_f) & ~(vaddr_f[pt[1182-:8]:1] == {pt[1182-:8] {1'b1}})) & (err_stop_state != ERR_FETCH2);
+	assign ic_fetch_val_f[0] = fetch_req_f_qual;
+	assign two_byte_instr = ic_data_f[1:0] != 2'b11;
+	wire [63:0] ic_miss_buff_data_in;
+	assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];
+	generate
+		genvar i;
+		for (i = 0; i < pt[1084-:8]; i = i + 1) begin : wr_flop
+			function automatic signed [pt[826-:8] - 1:0] sv2v_cast_ADFF4_signed;
+				input reg signed [pt[826-:8] - 1:0] inp;
+				sv2v_cast_ADFF4_signed = inp;
+			endfunction
+			assign write_fill_data[i] = bus_ifu_wr_en & (sv2v_cast_ADFF4_signed(i) == ifu_bus_rsp_tag[pt[826-:8] - 1:0]);
+			rvdffe #(.WIDTH(32)) byp_data_0_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(write_fill_data[i]),
+				.din(ic_miss_buff_data_in[31:0]),
+				.dout(ic_miss_buff_data[((i * 2) * 32) + 31-:32])
+			);
+			rvdffe #(.WIDTH(32)) byp_data_1_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.en(write_fill_data[i]),
+				.din(ic_miss_buff_data_in[63:32]),
+				.dout(ic_miss_buff_data[(((i * 2) + 1) * 32) + 31-:32])
+			);
+			assign ic_miss_buff_data_valid_in[i] = (write_fill_data[i] ? 1'b1 : ic_miss_buff_data_valid[i] & ~ic_act_miss_f);
+			rvdff #(.WIDTH(1)) byp_data_valid_ff(
+				.rst_l(rst_l),
+				.clk(active_clk),
+				.din(ic_miss_buff_data_valid_in[i]),
+				.dout(ic_miss_buff_data_valid[i])
+			);
+			assign ic_miss_buff_data_error_in[i] = (write_fill_data[i] ? bus_ifu_wr_data_error : ic_miss_buff_data_error[i] & ~ic_act_miss_f);
+			rvdff #(.WIDTH(1)) byp_data_error_ff(
+				.rst_l(rst_l),
+				.clk(active_clk),
+				.din(ic_miss_buff_data_error_in[i]),
+				.dout(ic_miss_buff_data_error[i])
+			);
+		end
+	endgenerate
+	wire [pt[1182-:8]:1] bypass_index;
+	wire [pt[1182-:8]:3] bypass_index_5_3_inc;
+	wire bypass_data_ready_in;
+	wire ic_crit_wd_rdy_new_in;
+	assign bypass_index[pt[1182-:8]:1] = imb_ff[pt[1182-:8]:1];
+	assign bypass_index_5_3_inc[pt[1182-:8]:3] = bypass_index[pt[1182-:8]:3] + 1;
+	assign bypass_data_ready_in = (((((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ~bypass_index[2]) & ~bypass_index[1]) | ((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ~bypass_index[2]) & bypass_index[1])) | ((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & bypass_index[2]) & ~bypass_index[1])) | (((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ic_miss_buff_data_valid_in[bypass_index_5_3_inc[pt[1182-:8]:3]]) & bypass_index[2]) & bypass_index[1])) | (ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & (bypass_index[pt[1182-:8]:3] == {pt[1182-:8] {1'b1}}));
+	assign ic_crit_wd_rdy_new_in = (((((bypass_data_ready_in & crit_wd_byp_ok_ff) & uncacheable_miss_ff) & ~exu_flush_final) & ~ifu_bp_hit_taken_q_f) | (((crit_wd_byp_ok_ff & ~uncacheable_miss_ff) & ~exu_flush_final) & ~ifu_bp_hit_taken_q_f)) | (((ic_crit_wd_rdy_new_ff & ~fetch_req_icache_f) & crit_wd_byp_ok_ff) & ~exu_flush_final);
+	assign byp_fetch_index[pt[1182-:8]:1] = ifu_fetch_addr_int_f[pt[1182-:8]:1];
+	assign byp_fetch_index_0[pt[1182-:8]:2] = {ifu_fetch_addr_int_f[pt[1182-:8]:3], 1'b0};
+	assign byp_fetch_index_1[pt[1182-:8]:2] = {ifu_fetch_addr_int_f[pt[1182-:8]:3], 1'b1};
+	assign byp_fetch_index_inc[pt[1182-:8]:3] = ifu_fetch_addr_int_f[pt[1182-:8]:3] + 1'b1;
+	assign byp_fetch_index_inc_0[pt[1182-:8]:2] = {byp_fetch_index_inc[pt[1182-:8]:3], 1'b0};
+	assign byp_fetch_index_inc_1[pt[1182-:8]:2] = {byp_fetch_index_inc[pt[1182-:8]:3], 1'b1};
+	assign ifu_byp_data_err_new = ((((~ifu_fetch_addr_int_f[2] & ~ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]]) | ((~ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]])) | ((ifu_fetch_addr_int_f[2] & ~ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]])) | ((ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & (ic_miss_buff_data_error[byp_fetch_index_inc[pt[1182-:8]:3]] | ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]]));
+	assign ifu_byp_data_err_f[1:0] = (ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]] ? 2'b11 : (((ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & ~ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]]) & (~miss_wrap_f & ic_miss_buff_data_error[byp_fetch_index_inc[pt[1182-:8]:3]]) ? 2'b10 : 2'b00));
+	assign ic_byp_data_only_pre_new[79:0] = ({80 {~ifu_fetch_addr_int_f[2]}} & {ic_miss_buff_data[(byp_fetch_index_inc_0 * 32) + 15-:16], ic_miss_buff_data[(byp_fetch_index_1 * 32) + 31-:32], ic_miss_buff_data[(byp_fetch_index_0 * 32) + 31-:32]}) | ({80 {ifu_fetch_addr_int_f[2]}} & {ic_miss_buff_data[(byp_fetch_index_inc_1 * 32) + 15-:16], ic_miss_buff_data[(byp_fetch_index_inc_0 * 32) + 31-:32], ic_miss_buff_data[(byp_fetch_index_1 * 32) + 31-:32]});
+	assign ic_byp_data_only_new[79:0] = (~ifu_fetch_addr_int_f[1] ? {ic_byp_data_only_pre_new[79:0]} : {16'b0000000000000000, ic_byp_data_only_pre_new[79:16]});
+	assign miss_wrap_f = imb_ff[pt[998-:7]] != ifu_fetch_addr_int_f[pt[998-:7]];
+	assign miss_buff_hit_unq_f = (((((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ~byp_fetch_index[2]) & ~byp_fetch_index[1]) | ((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ~byp_fetch_index[2]) & byp_fetch_index[1])) | ((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & byp_fetch_index[2]) & ~byp_fetch_index[1])) | (((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ic_miss_buff_data_valid[byp_fetch_index_inc[pt[1182-:8]:3]]) & byp_fetch_index[2]) & byp_fetch_index[1])) | (ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & (byp_fetch_index[pt[1182-:8]:3] == {pt[1174-:8] {1'b1}}));
+	assign stream_hit_f = (miss_buff_hit_unq_f & ~miss_wrap_f) & (miss_state == STREAM);
+	assign stream_miss_f = (~(miss_buff_hit_unq_f & ~miss_wrap_f) & (miss_state == STREAM)) & ifc_fetch_req_f;
+	assign stream_eol_f = ((byp_fetch_index[pt[1182-:8]:2] == {pt[1174-:8] + 1 {1'b1}}) & ifc_fetch_req_f) & stream_hit_f;
+	assign crit_byp_hit_f = miss_buff_hit_unq_f & ((miss_state == CRIT_WRD_RDY) | (miss_state == CRIT_BYP_OK));
+	assign other_tag[pt[826-:8] - 1:0] = {ifu_bus_rid_ff[pt[826-:8] - 1:1], ~ifu_bus_rid_ff[0]};
+	assign second_half_available = ic_miss_buff_data_valid[other_tag];
+	assign write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff;
+	assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag, 1'b1} * 32+:32], ic_miss_buff_data[{other_tag, 1'b0} * 32+:32]};
+	assign ic_rd_parity_final_err = (((ic_tag_perr & ~exu_flush_final) & sel_ic_data) & ~(ifc_region_acc_fault_final_f | |ifc_bus_acc_fault_f)) & (((fetch_req_icache_f & ~reset_all_tags) & (~miss_pending | (miss_state == HIT_U_MISS))) & ~sel_mb_addr_ff);
+	wire [pt[1060-:7] - 1:0] perr_err_inv_way;
+	wire [pt[1104-:9]:pt[998-:7]] perr_ic_index_ff;
+	reg perr_sel_invalidate;
+	reg perr_sb_write_status;
+	rvdffe #(
+		.WIDTH((pt[1104-:9] - pt[998-:7]) + 1),
+		.OVERRIDE(1)
+	) perr_dat_ff(
+		.din(ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]]),
+		.dout(perr_ic_index_ff[pt[1104-:9]:pt[998-:7]]),
+		.en(perr_sb_write_status),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	assign perr_err_inv_way[pt[1060-:7] - 1:0] = {pt[1060-:7] {perr_sel_invalidate}};
+	localparam [2:0] ECC_CORR = 3'b011;
+	assign iccm_correct_ecc = perr_state == ECC_CORR;
+	assign dma_sb_err_state = perr_state == DMA_SB_ERR;
+	assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff;
+	localparam [2:0] ECC_WFF = 3'b010;
+	localparam [2:0] ERR_IDLE = 3'b000;
+	localparam [2:0] IC_WFF = 3'b001;
+	always @(*) begin : ERROR_SM
+		perr_nxtstate = ERR_IDLE;
+		perr_state_en = 1'b0;
+		perr_sb_write_status = 1'b0;
+		perr_sel_invalidate = 1'b0;
+		case (perr_state)
+			ERR_IDLE: begin : err_idle
+				perr_nxtstate = (iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final ? IC_WFF : ECC_WFF));
+				perr_state_en = (((iccm_error_start | ic_error_start) & ~exu_flush_final) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
+				perr_sb_write_status = perr_state_en;
+			end
+			IC_WFF: begin : icache_wff
+				perr_nxtstate = ERR_IDLE;
+				perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt;
+				perr_sel_invalidate = dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb;
+			end
+			ECC_WFF: begin : ecc_wff
+				perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb) | dec_tlu_force_halt ? ERR_IDLE : ECC_CORR);
+				perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt;
+			end
+			DMA_SB_ERR: begin : dma_sb_ecc
+				perr_nxtstate = (dec_tlu_force_halt ? ERR_IDLE : ECC_CORR);
+				perr_state_en = 1'b1;
+			end
+			ECC_CORR: begin : ecc_corr
+				perr_nxtstate = ERR_IDLE;
+				perr_state_en = 1'b1;
+			end
+			default: begin : def_case
+				perr_nxtstate = ERR_IDLE;
+				perr_state_en = 1'b0;
+				perr_sb_write_status = 1'b0;
+				perr_sel_invalidate = 1'b0;
+			end
+		endcase
+	end
+	rvdffs #(.WIDTH(3)) perr_state_ff(
+		.clk(active_clk),
+		.din(perr_nxtstate),
+		.dout({perr_state}),
+		.en(perr_state_en),
+		.rst_l(rst_l)
+	);
+	localparam [1:0] ERR_FETCH1 = 2'b01;
+	localparam [1:0] ERR_STOP_IDLE = 2'b00;
+	always @(*) begin : ERROR_STOP_FETCH
+		err_stop_nxtstate = ERR_STOP_IDLE;
+		err_stop_state_en = 1'b0;
+		err_stop_fetch = 1'b0;
+		iccm_correction_state = 1'b0;
+		case (err_stop_state)
+			ERR_STOP_IDLE: begin : err_stop_idle
+				err_stop_nxtstate = ERR_FETCH1;
+				err_stop_state_en = (dec_tlu_flush_err_wb & (perr_state == ECC_WFF)) & ~dec_tlu_force_halt;
+			end
+			ERR_FETCH1: begin : err_fetch1
+				err_stop_nxtstate = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr) ? ERR_STOP_FETCH : (ifu_fetch_val[0] ? ERR_FETCH2 : ERR_FETCH1)));
+				err_stop_state_en = (((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | ifu_fetch_val[0]) | ifu_bp_hit_taken_q_f) | dec_tlu_force_halt;
+				err_stop_fetch = ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr)) & ~(exu_flush_final | dec_tlu_i0_commit_cmt);
+				iccm_correction_state = 1'b1;
+			end
+			ERR_FETCH2: begin : err_fetch2
+				err_stop_nxtstate = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? ERR_STOP_IDLE : (ifu_fetch_val[0] ? ERR_STOP_FETCH : ERR_FETCH2));
+				err_stop_state_en = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | ifu_fetch_val[0]) | dec_tlu_force_halt;
+				err_stop_fetch = (ifu_fetch_val[0] & ~exu_flush_final) & ~dec_tlu_i0_commit_cmt;
+				iccm_correction_state = 1'b1;
+			end
+			ERR_STOP_FETCH: begin : ecc_wff
+				err_stop_nxtstate = (((dec_tlu_flush_lower_wb & ~dec_tlu_flush_err_wb) | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? ERR_STOP_IDLE : (dec_tlu_flush_err_wb ? ERR_FETCH1 : ERR_STOP_FETCH));
+				err_stop_state_en = (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt;
+				err_stop_fetch = 1'b1;
+				iccm_correction_state = 1'b1;
+			end
+			default: begin : def_case
+				err_stop_nxtstate = ERR_STOP_IDLE;
+				err_stop_state_en = 1'b0;
+				err_stop_fetch = 1'b0;
+				iccm_correction_state = 1'b1;
+			end
+		endcase
+	end
+	rvdffs #(.WIDTH(2)) err_stop_state_ff(
+		.clk(active_clk),
+		.din(err_stop_nxtstate),
+		.dout({err_stop_state}),
+		.en(err_stop_state_en),
+		.rst_l(rst_l)
+	);
+	assign bus_ifu_bus_clk_en = ifu_bus_clk_en;
+	rvclkhdr bus_clk_f(
+		.en(bus_ifu_bus_clk_en),
+		.l1clk(busclk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr bus_clk(
+		.en(bus_ifu_bus_clk_en | dec_tlu_force_halt),
+		.l1clk(busclk_force),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign scnd_miss_req = scnd_miss_req_q & ~exu_flush_final;
+	assign ifc_bus_ic_req_ff_in = (((ic_act_miss_f | bus_cmd_req_hold) | ifu_bus_cmd_valid) & ~dec_tlu_force_halt) & ~((((bus_cmd_beat_count == {pt[1174-:8] {1'b1}}) & ifu_bus_cmd_valid) & ifu_bus_cmd_ready) & miss_pending);
+	rvdff_fpga #(.WIDTH(1)) bus_ic_req_ff2(
+		.rst_l(rst_l),
+		.clk(busclk_force),
+		.clken(bus_ifu_bus_clk_en | dec_tlu_force_halt),
+		.rawclk(clk),
+		.din(ifc_bus_ic_req_ff_in),
+		.dout(ifu_bus_cmd_valid)
+	);
+	assign bus_cmd_req_in = ((ic_act_miss_f | bus_cmd_req_hold) & ~bus_cmd_sent) & ~dec_tlu_force_halt;
+	assign ifu_axi_arvalid = ifu_bus_cmd_valid;
+	function automatic [pt[826-:8] - 1:0] sv2v_cast_ADFF4;
+		input reg [pt[826-:8] - 1:0] inp;
+		sv2v_cast_ADFF4 = inp;
+	endfunction
+	assign ifu_axi_arid[pt[826-:8] - 1:0] = sv2v_cast_ADFF4(bus_rd_addr_count[pt[1174-:8] - 1:0]) & {pt[826-:8] {ifu_bus_cmd_valid}};
+	assign ifu_axi_araddr[31:0] = {ifu_ic_req_addr_f[31:3], 3'b000} & {32 {ifu_bus_cmd_valid}};
+	assign ifu_axi_arsize[2:0] = 3'b011;
+	assign ifu_axi_arprot[2:0] = 3'b101;
+	assign ifu_axi_arcache[3:0] = 4'b1111;
+	assign ifu_axi_arregion[3:0] = ifu_ic_req_addr_f[31:28];
+	assign ifu_axi_arlen[7:0] = {8 {1'sb0}};
+	assign ifu_axi_arburst[1:0] = 2'b01;
+	assign ifu_axi_arqos[3:0] = {4 {1'sb0}};
+	assign ifu_axi_arlock = 1'b0;
+	assign ifu_axi_rready = 1'b1;
+	assign ifu_axi_awvalid = 1'b0;
+	assign ifu_axi_awid[pt[826-:8] - 1:0] = {pt[826-:8] {1'sb0}};
+	assign ifu_axi_awaddr[31:0] = {32 {1'sb0}};
+	assign ifu_axi_awsize[2:0] = {3 {1'sb0}};
+	assign ifu_axi_awprot[2:0] = {3 {1'sb0}};
+	assign ifu_axi_awcache[3:0] = {4 {1'sb0}};
+	assign ifu_axi_awregion[3:0] = {4 {1'sb0}};
+	assign ifu_axi_awlen[7:0] = {8 {1'sb0}};
+	assign ifu_axi_awburst[1:0] = {2 {1'sb0}};
+	assign ifu_axi_awqos[3:0] = {4 {1'sb0}};
+	assign ifu_axi_awlock = 1'b0;
+	assign ifu_axi_wvalid = 1'b0;
+	assign ifu_axi_wstrb[7:0] = {8 {1'sb0}};
+	assign ifu_axi_wdata[63:0] = {64 {1'sb0}};
+	assign ifu_axi_wlast = 1'b0;
+	assign ifu_axi_bready = 1'b0;
+	assign ifu_bus_arready_unq = ifu_axi_arready;
+	assign ifu_bus_rvalid_unq = ifu_axi_rvalid;
+	assign ifu_bus_arvalid = ifu_axi_arvalid;
+	rvdff_fpga #(.WIDTH(1)) bus_rdy_ff(
+		.rst_l(rst_l),
+		.clk(busclk),
+		.clken(bus_ifu_bus_clk_en),
+		.rawclk(clk),
+		.din(ifu_bus_arready_unq),
+		.dout(ifu_bus_arready_unq_ff)
+	);
+	rvdff_fpga #(.WIDTH(1)) bus_rsp_vld_ff(
+		.rst_l(rst_l),
+		.clk(busclk),
+		.clken(bus_ifu_bus_clk_en),
+		.rawclk(clk),
+		.din(ifu_bus_rvalid_unq),
+		.dout(ifu_bus_rvalid_unq_ff)
+	);
+	rvdff_fpga #(.WIDTH(1)) bus_cmd_ff(
+		.rst_l(rst_l),
+		.clk(busclk),
+		.clken(bus_ifu_bus_clk_en),
+		.rawclk(clk),
+		.din(ifu_bus_arvalid),
+		.dout(ifu_bus_arvalid_ff)
+	);
+	rvdff_fpga #(.WIDTH(2)) bus_rsp_cmd_ff(
+		.rst_l(rst_l),
+		.clk(busclk),
+		.clken(bus_ifu_bus_clk_en),
+		.rawclk(clk),
+		.din(ifu_axi_rresp[1:0]),
+		.dout(ifu_bus_rresp_ff[1:0])
+	);
+	rvdff_fpga #(.WIDTH(pt[826-:8])) bus_rsp_tag_ff(
+		.rst_l(rst_l),
+		.clk(busclk),
+		.clken(bus_ifu_bus_clk_en),
+		.rawclk(clk),
+		.din(ifu_axi_rid[pt[826-:8] - 1:0]),
+		.dout(ifu_bus_rid_ff[pt[826-:8] - 1:0])
+	);
+	rvdffe #(.WIDTH(64)) bus_data_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(clk),
+		.din(ifu_axi_rdata[63:0]),
+		.dout(ifu_bus_rdata_ff[63:0]),
+		.en(ifu_bus_clk_en & ifu_axi_rvalid)
+	);
+	assign ifu_bus_cmd_ready = ifu_axi_arready;
+	assign ifu_bus_rsp_valid = ifu_axi_rvalid;
+	assign ifu_bus_rsp_ready = ifu_axi_rready;
+	assign ifu_bus_rsp_tag[pt[826-:8] - 1:0] = ifu_axi_rid[pt[826-:8] - 1:0];
+	assign ifu_bus_rsp_rdata[63:0] = ifu_axi_rdata[63:0];
+	assign ifu_bus_rsp_opc[1:0] = {ifu_axi_rresp[1:0]};
+	assign ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en;
+	assign ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en;
+	assign ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff;
+	assign ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff;
+	assign bus_cmd_sent = ((ifu_bus_arvalid & ifu_bus_arready) & miss_pending) & ~dec_tlu_force_halt;
+	assign bus_inc_data_beat_cnt = (bus_ifu_wr_en_ff & ~bus_last_data_beat) & ~dec_tlu_force_halt;
+	assign bus_reset_data_beat_cnt = (ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat)) | dec_tlu_force_halt;
+	assign bus_hold_data_beat_cnt = ~bus_inc_data_beat_cnt & ~bus_reset_data_beat_cnt;
+	function automatic signed [pt[1174-:8] - 1:0] sv2v_cast_4BA5C_signed;
+		input reg signed [pt[1174-:8] - 1:0] inp;
+		sv2v_cast_4BA5C_signed = inp;
+	endfunction
+	assign bus_new_data_beat_count[pt[1174-:8] - 1:0] = (({pt[1174-:8] {bus_reset_data_beat_cnt}} & sv2v_cast_4BA5C_signed(0)) | ({pt[1174-:8] {bus_inc_data_beat_cnt}} & (bus_data_beat_count[pt[1174-:8] - 1:0] + {{pt[1174-:8] - 1 {1'b0}}, 1'b1}))) | ({pt[1174-:8] {bus_hold_data_beat_cnt}} & bus_data_beat_count[pt[1174-:8] - 1:0]);
+	assign last_data_recieved_in = ((bus_ifu_wr_en_ff & bus_last_data_beat) & ~scnd_miss_req) | (last_data_recieved_ff & ~ic_act_miss_f);
+	assign bus_new_rd_addr_count[pt[1174-:8] - 1:0] = (~miss_pending ? imb_ff[pt[1182-:8]:3] : (scnd_miss_req_q ? imb_scnd_ff[pt[1182-:8]:3] : (bus_cmd_sent ? bus_rd_addr_count[pt[1174-:8] - 1:0] + 3'b001 : bus_rd_addr_count[pt[1174-:8] - 1:0])));
+	rvdff_fpga #(.WIDTH(pt[1174-:8])) bus_rd_addr_ff(
+		.rst_l(rst_l),
+		.clk(busclk_reset),
+		.clken((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt),
+		.rawclk(clk),
+		.din({bus_new_rd_addr_count[pt[1174-:8] - 1:0]}),
+		.dout({bus_rd_addr_count[pt[1174-:8] - 1:0]})
+	);
+	assign bus_inc_cmd_beat_cnt = ((ifu_bus_cmd_valid & ifu_bus_cmd_ready) & miss_pending) & ~dec_tlu_force_halt;
+	assign bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & ~uncacheable_miss_in) | dec_tlu_force_halt;
+	assign bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in;
+	assign bus_hold_cmd_beat_cnt = ~bus_inc_cmd_beat_cnt & ~((ic_act_miss_f | scnd_miss_req) | dec_tlu_force_halt);
+	assign bus_cmd_beat_en = (bus_inc_cmd_beat_cnt | ic_act_miss_f) | dec_tlu_force_halt;
+	function automatic [pt[1174-:8] - 1:0] sv2v_cast_4BA5C;
+		input reg [pt[1174-:8] - 1:0] inp;
+		sv2v_cast_4BA5C = inp;
+	endfunction
+	assign bus_new_cmd_beat_count[pt[1174-:8] - 1:0] = ((({pt[1174-:8] {bus_reset_cmd_beat_cnt_0}} & sv2v_cast_4BA5C_signed(0)) | ({pt[1174-:8] {bus_reset_cmd_beat_cnt_secondlast}} & sv2v_cast_4BA5C(pt[1048-:8]))) | ({pt[1174-:8] {bus_inc_cmd_beat_cnt}} & (bus_cmd_beat_count[pt[1174-:8] - 1:0] + {{pt[1174-:8] - 1 {1'b0}}, 1'b1}))) | ({pt[1174-:8] {bus_hold_cmd_beat_cnt}} & bus_cmd_beat_count[pt[1174-:8] - 1:0]);
+	rvclkhdr bus_clk_reset(
+		.en((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt),
+		.l1clk(busclk_reset),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvdffs_fpga #(.WIDTH(pt[1174-:8])) bus_cmd_beat_ff(
+		.rst_l(rst_l),
+		.clk(busclk_reset),
+		.clken((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt),
+		.rawclk(clk),
+		.en(bus_cmd_beat_en),
+		.din({bus_new_cmd_beat_count[pt[1174-:8] - 1:0]}),
+		.dout({bus_cmd_beat_count[pt[1174-:8] - 1:0]})
+	);
+	assign bus_last_data_beat = (uncacheable_miss_ff ? bus_data_beat_count[pt[1174-:8] - 1:0] == {{pt[1174-:8] - 1 {1'b0}}, 1'b1} : &bus_data_beat_count[pt[1174-:8] - 1:0]);
+	assign bus_ifu_wr_en = ifu_bus_rvalid & miss_pending;
+	assign bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending;
+	assign bus_ifu_wr_en_ff_q = (((ifu_bus_rvalid_ff & miss_pending) & ~uncacheable_miss_ff) & ~(|ifu_bus_rresp_ff[1:0])) & write_ic_16_bytes;
+	assign bus_ifu_wr_en_ff_wo_err = (ifu_bus_rvalid_ff & miss_pending) & ~uncacheable_miss_ff;
+	rvdffie #(.WIDTH(10)) misc_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({ic_act_miss_f, ifu_wr_cumulative_err, exu_flush_final, ic_crit_wd_rdy_new_in, bus_ifu_bus_clk_en, scnd_miss_req_in, bus_cmd_req_in, last_data_recieved_in, ifc_dma_access_ok_d, dma_iccm_req}),
+		.dout({ic_act_miss_f_delayed, ifu_wr_data_comb_err_ff, flush_final_f, ic_crit_wd_rdy_new_ff, bus_ifu_bus_clk_en_ff, scnd_miss_req_q, bus_cmd_req_hold, last_data_recieved_ff, ifc_dma_access_ok_prev, dma_iccm_req_f})
+	);
+	rvdffie #(
+		.WIDTH(pt[1174-:8] + 5),
+		.OVERRIDE(1)
+	) misc1_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({reset_ic_in, sel_mb_addr, bus_new_data_beat_count[pt[1174-:8] - 1:0], ifc_region_acc_fault_memory_bf, ic_debug_rd_en, ic_debug_rd_en_ff}),
+		.dout({reset_ic_ff, sel_mb_addr_ff, bus_data_beat_count[pt[1174-:8] - 1:0], ifc_region_acc_fault_memory_f, ic_debug_rd_en_ff, ifu_ic_debug_rd_data_valid})
+	);
+	assign reset_tag_valid_for_miss = (ic_act_miss_f_delayed & (miss_state == CRIT_BYP_OK)) & ~uncacheable_miss_ff;
+	assign bus_ifu_wr_data_error = (|ifu_bus_rsp_opc[1:0] & ifu_bus_rvalid) & miss_pending;
+	assign bus_ifu_wr_data_error_ff = (|ifu_bus_rresp_ff[1:0] & ifu_bus_rvalid_ff) & miss_pending;
+	assign ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff;
+	assign last_beat = bus_last_data_beat & bus_ifu_wr_en_ff;
+	assign reset_beat_cnt = bus_reset_data_beat_cnt;
+	assign ifc_dma_access_ok_d = (ifc_dma_access_ok & ~iccm_correct_ecc) & ~iccm_dma_sb_error;
+	assign ifc_dma_access_q_ok = (((ifc_dma_access_ok & ~iccm_correct_ecc) & ifc_dma_access_ok_prev) & (perr_state == ERR_IDLE)) & ~iccm_dma_sb_error;
+	assign iccm_ready = ifc_dma_access_q_ok;
+	wire [1:0] iccm_ecc_word_enable;
+	generate
+		if (pt[927-:5] == 1) begin : iccm_enabled
+			wire [3:2] dma_mem_addr_ff;
+			wire iccm_dma_rden;
+			wire iccm_dma_ecc_error_in;
+			wire [13:0] dma_mem_ecc;
+			wire [63:0] iccm_dma_rdata_in;
+			wire [31:0] iccm_dma_rdata_1_muxed;
+			wire [63:0] iccm_corrected_data;
+			wire [13:0] iccm_corrected_ecc;
+			wire [1:0] iccm_double_ecc_error;
+			wire [pt[936-:9] - 1:2] iccm_rw_addr_f;
+			wire [31:0] iccm_corrected_data_f_mux;
+			wire [6:0] iccm_corrected_ecc_f_mux;
+			wire iccm_dma_rvalid_in;
+			wire [77:0] iccm_rdmux_data;
+			wire iccm_rd_ecc_single_err_hold_in;
+			wire [2:0] dma_mem_tag_ff;
+			assign iccm_wren = ((ifc_dma_access_q_ok & dma_iccm_req) & dma_mem_write) | iccm_correct_ecc;
+			assign iccm_rden = ((ifc_dma_access_q_ok & dma_iccm_req) & ~dma_mem_write) | (ifc_iccm_access_bf & ifc_fetch_req_bf);
+			assign iccm_dma_rden = (ifc_dma_access_q_ok & dma_iccm_req) & ~dma_mem_write;
+			assign iccm_wr_size[2:0] = {3 {dma_iccm_req}} & dma_mem_sz[2:0];
+			rvecc_encode iccm_ecc_encode0(
+				.din(dma_mem_wdata[31:0]),
+				.ecc_out(dma_mem_ecc[6:0])
+			);
+			rvecc_encode iccm_ecc_encode1(
+				.din(dma_mem_wdata[63:32]),
+				.ecc_out(dma_mem_ecc[13:7])
+			);
+			assign iccm_wr_data[77:0] = (iccm_correct_ecc & ~(ifc_dma_access_q_ok & dma_iccm_req) ? {iccm_ecc_corr_data_ff[38:0], iccm_ecc_corr_data_ff[38:0]} : {dma_mem_ecc[13:7], dma_mem_wdata[63:32], dma_mem_ecc[6:0], dma_mem_wdata[31:0]});
+			assign iccm_dma_rdata_1_muxed[31:0] = (dma_mem_addr_ff[2] ? iccm_corrected_data[31-:32] : iccm_corrected_data[63-:32]);
+			assign iccm_dma_rdata_in[63:0] = (iccm_dma_ecc_error_in ? {2 {dma_mem_addr[31:0]}} : {iccm_dma_rdata_1_muxed[31:0], iccm_corrected_data[0+:32]});
+			assign iccm_dma_ecc_error_in = |iccm_double_ecc_error[1:0];
+			rvdffe #(.WIDTH(64)) dma_data_ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(clk),
+				.en(iccm_dma_rvalid_in),
+				.din(iccm_dma_rdata_in[63:0]),
+				.dout(iccm_dma_rdata[63:0])
+			);
+			rvdffie #(.WIDTH(11)) dma_misc_bits(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(free_l2clk),
+				.din({dma_mem_tag[2:0], dma_mem_tag_ff[2:0], dma_mem_addr[3:2], iccm_dma_rden, iccm_dma_rvalid_in, iccm_dma_ecc_error_in}),
+				.dout({dma_mem_tag_ff[2:0], iccm_dma_rtag[2:0], dma_mem_addr_ff[3:2], iccm_dma_rvalid_in, iccm_dma_rvalid, iccm_dma_ecc_error})
+			);
+			assign iccm_rw_addr[pt[936-:9] - 1:1] = ((ifc_dma_access_q_ok & dma_iccm_req) & ~iccm_correct_ecc ? dma_mem_addr[pt[936-:9] - 1:1] : (~(ifc_dma_access_q_ok & dma_iccm_req) & iccm_correct_ecc ? {iccm_ecc_corr_index_ff[pt[936-:9] - 1:2], 1'b0} : ifc_fetch_addr_bf[pt[936-:9] - 1:1]));
+			wire [3:0] ic_fetch_val_int_f;
+			wire [3:0] ic_fetch_val_shift_right;
+			assign ic_fetch_val_int_f[3:0] = {2'b00, ic_fetch_val_f[1:0]};
+			assign ic_fetch_val_shift_right[3:0] = {ic_fetch_val_int_f << ifu_fetch_addr_int_f[1]};
+			assign iccm_rdmux_data[77:0] = iccm_rd_data_ecc[77:0];
+			for (i = 0; i < 2; i = i + 1) begin : ICCM_ECC_CHECK
+				assign iccm_ecc_word_enable[i] = (((|ic_fetch_val_shift_right[(2 * i) + 1:2 * i] & ~exu_flush_final) & sel_iccm_data) | iccm_dma_rvalid_in) & ~dec_tlu_core_ecc_disable;
+				rvecc_decode ecc_decode(
+					.en(iccm_ecc_word_enable[i]),
+					.sed_ded(1'b0),
+					.din(iccm_rdmux_data[(39 * i) + 31:39 * i]),
+					.ecc_in(iccm_rdmux_data[(39 * i) + 38:(39 * i) + 32]),
+					.dout(iccm_corrected_data[(i * 32) + 31-:32]),
+					.ecc_out(iccm_corrected_ecc[(i * 7) + 6-:7]),
+					.single_ecc_error(iccm_single_ecc_error[i]),
+					.double_ecc_error(iccm_double_ecc_error[i])
+				);
+			end
+			assign iccm_rd_ecc_single_err = (|iccm_single_ecc_error[1:0] & ifc_iccm_access_f) & ifc_fetch_req_f;
+			assign iccm_rd_ecc_double_err[1:0] = (~ifu_fetch_addr_int_f[1] ? {iccm_double_ecc_error[0], iccm_double_ecc_error[0]} & {2 {ifc_iccm_access_f}} : {iccm_double_ecc_error[1], iccm_double_ecc_error[0]} & {2 {ifc_iccm_access_f}});
+			assign iccm_corrected_data_f_mux[31:0] = (iccm_single_ecc_error[0] ? iccm_corrected_data[0+:32] : iccm_corrected_data[32+:32]);
+			assign iccm_corrected_ecc_f_mux[6:0] = (iccm_single_ecc_error[0] ? iccm_corrected_ecc[0+:7] : iccm_corrected_ecc[7+:7]);
+			assign iccm_ecc_write_status = ((iccm_rd_ecc_single_err & ~iccm_rd_ecc_single_err_ff) & ~exu_flush_final) | iccm_dma_sb_error;
+			assign iccm_rd_ecc_single_err_hold_in = (iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & ~exu_flush_final;
+			assign iccm_error_start = iccm_rd_ecc_single_err;
+			assign iccm_ecc_corr_index_in[pt[936-:9] - 1:2] = (iccm_single_ecc_error[0] ? iccm_rw_addr_f[pt[936-:9] - 1:2] : iccm_rw_addr_f[pt[936-:9] - 1:2] + 1'b1);
+			rvdffie #(.WIDTH(pt[936-:9] - 1)) iccm_index_f(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(free_l2clk),
+				.din({iccm_rw_addr[pt[936-:9] - 1:2], iccm_rd_ecc_single_err_hold_in}),
+				.dout({iccm_rw_addr_f[pt[936-:9] - 1:2], iccm_rd_ecc_single_err_ff})
+			);
+			rvdffe #(.WIDTH(pt[936-:9] + 37)) ecc_dat0_ff(
+				.clk(clk),
+				.din({iccm_corrected_ecc_f_mux[6:0], iccm_corrected_data_f_mux[31:0], iccm_ecc_corr_index_in[pt[936-:9] - 1:2]}),
+				.dout({iccm_ecc_corr_data_ff[38:0], iccm_ecc_corr_index_ff[pt[936-:9] - 1:2]}),
+				.en(iccm_ecc_write_status),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+		end
+		else begin : iccm_disabled
+			assign iccm_dma_rvalid = 1'b0;
+			assign iccm_dma_ecc_error = 1'b0;
+			assign iccm_dma_rdata[63:0] = {64 {1'sb0}};
+			assign iccm_single_ecc_error = {2 {1'sb0}};
+			assign iccm_dma_rtag = {3 {1'sb0}};
+			assign iccm_rd_ecc_single_err = 1'b0;
+			assign iccm_rd_ecc_double_err = {2 {1'sb0}};
+			assign iccm_rd_ecc_single_err_ff = 1'b0;
+			assign iccm_error_start = 1'b0;
+			assign iccm_ecc_corr_index_ff[pt[936-:9] - 1:2] = {((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) {1'sb0}};
+			assign iccm_ecc_corr_data_ff[38:0] = {39 {1'sb0}};
+			assign iccm_ecc_write_status = 1'b0;
+		end
+	endgenerate
+	assign ic_rd_en = (((ifc_fetch_req_bf & ~ifc_fetch_uncacheable_bf) & ~ifc_iccm_access_bf) & ~(((((((miss_state == STREAM) & ~miss_state_en) | ((miss_state == CRIT_BYP_OK) & ~miss_state_en)) | ((miss_state == STALL_SCND_MISS) & ~miss_state_en)) | ((miss_state == MISS_WAIT) & ~miss_state_en)) | ((miss_state == CRIT_WRD_RDY) & ~miss_state_en)) | (((miss_state == CRIT_BYP_OK) & miss_state_en) & (miss_nxtstate == MISS_WAIT)))) | (((ifc_fetch_req_bf & exu_flush_final) & ~ifc_fetch_uncacheable_bf) & ~ifc_iccm_access_bf);
+	wire ic_real_rd_wp_unused;
+	assign ic_real_rd_wp_unused = ((((((ifc_fetch_req_bf & ~ifc_iccm_access_bf) & ~ifc_region_acc_fault_final_bf) & ~dec_tlu_fence_i_wb) & ~stream_miss_f) & ~ic_act_miss_f) & ~(((((((((miss_state == STREAM) & ~miss_state_en) | (((miss_state == CRIT_BYP_OK) & ~miss_state_en) & ~(miss_nxtstate == MISS_WAIT))) | (((miss_state == CRIT_BYP_OK) & miss_state_en) & (miss_nxtstate == MISS_WAIT))) | ((miss_state == MISS_WAIT) & ~miss_state_en)) | ((miss_state == STALL_SCND_MISS) & ~miss_state_en)) | ((miss_state == CRIT_WRD_RDY) & ~miss_state_en)) | ((miss_nxtstate == STREAM) & miss_state_en)) | ((miss_state == SCND_MISS) & ~miss_state_en))) | (((((ifc_fetch_req_bf & ~ifc_iccm_access_bf) & ~ifc_region_acc_fault_final_bf) & ~dec_tlu_fence_i_wb) & ~stream_miss_f) & exu_flush_final);
+	assign ic_wr_en[pt[1060-:7] - 1:0] = bus_ic_wr_en[pt[1060-:7] - 1:0] & {pt[1060-:7] {write_ic_16_bytes}};
+	assign ic_write_stall = write_ic_16_bytes & ~(((miss_state == CRIT_BYP_OK) | ((miss_state == STREAM) & ~((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f))) & ~((bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff));
+	reg [pt[1060-:7] - 1:0] ic_tag_valid_unq;
+	generate
+		if (pt[1120-:5] == 1) begin : icache_enabled
+			assign ic_valid = (~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff)) & ~reset_tag_valid_for_miss;
+			assign ifu_status_wr_addr_w_debug[pt[1104-:9]:pt[998-:7]] = ((ic_debug_rd_en | ic_debug_wr_en) & ic_debug_tag_array ? ic_debug_addr[pt[1104-:9]:pt[998-:7]] : ifu_status_wr_addr[pt[1104-:9]:pt[998-:7]]);
+			assign way_status_wr_en_w_debug = way_status_wr_en | (ic_debug_wr_en & ic_debug_tag_array);
+			assign way_status_new_w_debug[pt[1027-:7] - 1:0] = (ic_debug_wr_en & ic_debug_tag_array ? (pt[1027-:7] == 1 ? ic_debug_wr_data[4] : ic_debug_wr_data[6:4]) : way_status_new[pt[1027-:7] - 1:0]);
+			rvdffie #(
+				.WIDTH(((pt[991-:9] - pt[998-:7]) + 1) + pt[1027-:7]),
+				.OVERRIDE(1)
+			) status_misc_ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(free_l2clk),
+				.din({ifu_status_wr_addr_w_debug[pt[1104-:9]:pt[998-:7]], way_status_wr_en_w_debug, way_status_new_w_debug[pt[1027-:7] - 1:0]}),
+				.dout({ifu_status_wr_addr_ff[pt[1104-:9]:pt[998-:7]], way_status_wr_en_ff, way_status_new_ff[pt[1027-:7] - 1:0]})
+			);
+			wire [(pt[1015-:17] / 8) - 1:0] way_status_clken;
+			wire [(pt[1015-:17] / 8) - 1:0] way_status_clk;
+			for (i = 0; i < (pt[1015-:17] / 8); i = i + 1) begin : CLK_GRP_WAY_STATUS
+				assign way_status_clken[i] = ifu_status_wr_addr_ff[pt[1104-:9]:pt[998-:7] + 3] == i;
+				rvclkhdr way_status_cgc(
+					.en(way_status_clken[i]),
+					.l1clk(way_status_clk[i]),
+					.clk(clk),
+					.scan_mode(scan_mode)
+				);
+				genvar j;
+				for (j = 0; j < 8; j = j + 1) begin : WAY_STATUS
+					rvdffs_fpga #(.WIDTH(pt[1027-:7])) ic_way_status(
+						.rst_l(rst_l),
+						.clk(way_status_clk[i]),
+						.clken(way_status_clken[i]),
+						.rawclk(clk),
+						.en((ifu_status_wr_addr_ff[pt[998-:7] + 2:pt[998-:7]] == j) & way_status_wr_en_ff),
+						.din(way_status_new_ff[pt[1027-:7] - 1:0]),
+						.dout(way_status_out[((8 * i) + j) * pt[1027-:7]+:pt[1027-:7]])
+					);
+				end
+			end
+			function automatic signed [(pt[991-:9] - pt[998-:7]) - 1:0] sv2v_cast_46E4F_signed;
+				input reg signed [(pt[991-:9] - pt[998-:7]) - 1:0] inp;
+				sv2v_cast_46E4F_signed = inp;
+			endfunction
+			always @(*) begin : way_status_out_mux
+				way_status[pt[1027-:7] - 1:0] = {pt[1027-:7] {1'sb0}};
+				begin : sv2v_autoblock_47
+					reg signed [31:0] j;
+					for (j = 0; j < pt[1015-:17]; j = j + 1)
+						begin : status_mux_loop
+							if (ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == sv2v_cast_46E4F_signed(j)) begin : mux_out
+								way_status[pt[1027-:7] - 1:0] = way_status_out[j * pt[1027-:7]+:pt[1027-:7]];
+							end
+						end
+				end
+			end
+			assign ifu_ic_rw_int_addr_w_debug[pt[1104-:9]:pt[998-:7]] = ((ic_debug_rd_en | ic_debug_wr_en) & ic_debug_tag_array ? ic_debug_addr[pt[1104-:9]:pt[998-:7]] : ifu_ic_rw_int_addr[pt[1104-:9]:pt[998-:7]]);
+			assign ifu_tag_wren_w_debug[pt[1060-:7] - 1:0] = ifu_tag_wren[pt[1060-:7] - 1:0] | ic_debug_tag_wr_en[pt[1060-:7] - 1:0];
+			assign ic_valid_w_debug = (ic_debug_wr_en & ic_debug_tag_array ? ic_debug_wr_data[0] : ic_valid);
+			rvdffie #(.WIDTH(((pt[991-:9] - pt[998-:7]) + pt[1060-:7]) + 1)) tag_addr_ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.clk(free_l2clk),
+				.din({ifu_ic_rw_int_addr_w_debug[pt[1104-:9]:pt[998-:7]], ifu_tag_wren_w_debug[pt[1060-:7] - 1:0], ic_valid_w_debug}),
+				.dout({ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]], ifu_tag_wren_ff[pt[1060-:7] - 1:0], ic_valid_ff})
+			);
+			wire [(pt[1060-:7] * pt[1015-:17]) - 1:0] ic_tag_valid_out;
+			wire [((pt[1015-:17] / 32) * pt[1060-:7]) - 1:0] tag_valid_clken;
+			wire [((pt[1015-:17] / 32) * pt[1060-:7]) - 1:0] tag_valid_clk;
+			for (i = 0; i < (pt[1015-:17] / 32); i = i + 1) begin : CLK_GRP_TAG_VALID
+				genvar j;
+				for (j = 0; j < pt[1060-:7]; j = j + 1) begin : way_clken
+					if (pt[1015-:17] == 32) begin
+						assign tag_valid_clken[(i * pt[1060-:7]) + j] = (ifu_tag_wren_ff[j] | perr_err_inv_way[j]) | reset_all_tags;
+					end
+					else assign tag_valid_clken[(i * pt[1060-:7]) + j] = (((ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7] + 5] == i) & ifu_tag_wren_ff[j]) | ((perr_ic_index_ff[pt[1104-:9]:pt[998-:7] + 5] == i) & perr_err_inv_way[j])) | reset_all_tags;
+					rvclkhdr way_status_cgc(
+						.en(tag_valid_clken[(i * pt[1060-:7]) + j]),
+						.l1clk(tag_valid_clk[(i * pt[1060-:7]) + j]),
+						.clk(clk),
+						.scan_mode(scan_mode)
+					);
+					genvar k;
+					for (k = 0; k < 32; k = k + 1) begin : TAG_VALID
+						rvdffs_fpga #(.WIDTH(1)) ic_way_tagvalid_dup(
+							.rst_l(rst_l),
+							.clk(tag_valid_clk[(i * pt[1060-:7]) + j]),
+							.clken(tag_valid_clken[(i * pt[1060-:7]) + j]),
+							.rawclk(clk),
+							.en((((ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == (k + (32 * i))) & ifu_tag_wren_ff[j]) | ((perr_ic_index_ff[pt[1104-:9]:pt[998-:7]] == (k + (32 * i))) & perr_err_inv_way[j])) | reset_all_tags),
+							.din((ic_valid_ff & ~reset_all_tags) & ~perr_sel_invalidate),
+							.dout(ic_tag_valid_out[(j * pt[1015-:17]) + ((32 * i) + k)])
+						);
+					end
+				end
+			end
+			always @(*) begin : tag_valid_out_mux
+				ic_tag_valid_unq[pt[1060-:7] - 1:0] = {pt[1060-:7] {1'sb0}};
+				begin : sv2v_autoblock_48
+					reg signed [31:0] j;
+					for (j = 0; j < pt[1015-:17]; j = j + 1)
+						begin : tag_valid_loop
+							if (ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == sv2v_cast_46E4F_signed(j)) begin : valid_out
+								begin : sv2v_autoblock_49
+									reg signed [31:0] k;
+									for (k = 0; k < pt[1060-:7]; k = k + 1)
+										ic_tag_valid_unq[k] = ic_tag_valid_unq[k] | ic_tag_valid_out[(k * pt[1015-:17]) + j];
+								end
+							end
+						end
+				end
+			end
+			if (pt[1060-:7] == 4) begin : four_way_plru
+				assign replace_way_mb_any[3] = ((way_status_mb_ff[2] & way_status_mb_ff[0]) & &tagv_mb_ff[3:0]) | (((~tagv_mb_ff[3] & tagv_mb_ff[2]) & tagv_mb_ff[1]) & tagv_mb_ff[0]);
+				assign replace_way_mb_any[2] = ((~way_status_mb_ff[2] & way_status_mb_ff[0]) & &tagv_mb_ff[3:0]) | ((~tagv_mb_ff[2] & tagv_mb_ff[1]) & tagv_mb_ff[0]);
+				assign replace_way_mb_any[1] = ((way_status_mb_ff[1] & ~way_status_mb_ff[0]) & &tagv_mb_ff[3:0]) | (~tagv_mb_ff[1] & tagv_mb_ff[0]);
+				assign replace_way_mb_any[0] = ((~way_status_mb_ff[1] & ~way_status_mb_ff[0]) & &tagv_mb_ff[3:0]) | ~tagv_mb_ff[0];
+				assign way_status_hit_new[pt[1027-:7] - 1:0] = ((({3 {~exu_flush_final & ic_rd_hit[0]}} & {way_status[2], 1'b1, 1'b1}) | ({3 {~exu_flush_final & ic_rd_hit[1]}} & {way_status[2], 1'b0, 1'b1})) | ({3 {~exu_flush_final & ic_rd_hit[2]}} & {1'b1, way_status[1], 1'b0})) | ({3 {~exu_flush_final & ic_rd_hit[3]}} & {1'b0, way_status[1], 1'b0});
+				assign way_status_rep_new[pt[1027-:7] - 1:0] = ((({3 {replace_way_mb_any[0]}} & {way_status_mb_ff[2], 1'b1, 1'b1}) | ({3 {replace_way_mb_any[1]}} & {way_status_mb_ff[2], 1'b0, 1'b1})) | ({3 {replace_way_mb_any[2]}} & {1'b1, way_status_mb_ff[1], 1'b0})) | ({3 {replace_way_mb_any[3]}} & {1'b0, way_status_mb_ff[1], 1'b0});
+			end
+			else begin : two_ways_plru
+				assign replace_way_mb_any[0] = ((~way_status_mb_ff & tagv_mb_ff[0]) & tagv_mb_ff[1]) | ~tagv_mb_ff[0];
+				assign replace_way_mb_any[1] = ((way_status_mb_ff & tagv_mb_ff[0]) & tagv_mb_ff[1]) | (~tagv_mb_ff[1] & tagv_mb_ff[0]);
+				assign way_status_hit_new[pt[1027-:7] - 1:0] = ic_rd_hit[0];
+				assign way_status_rep_new[pt[1027-:7] - 1:0] = replace_way_mb_any[0];
+			end
+			assign way_status_new[pt[1027-:7] - 1:0] = (bus_ifu_wr_en_ff_q & last_beat ? way_status_rep_new[pt[1027-:7] - 1:0] : way_status_hit_new[pt[1027-:7] - 1:0]);
+			assign way_status_wr_en = (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f;
+			for (i = 0; i < pt[1060-:7]; i = i + 1) begin : bus_wren_loop
+				assign bus_wren[i] = (bus_ifu_wr_en_ff_q & replace_way_mb_any[i]) & miss_pending;
+				assign bus_wren_last[i] = ((bus_ifu_wr_en_ff_wo_err & replace_way_mb_any[i]) & miss_pending) & bus_last_data_beat;
+				assign ifu_tag_wren[i] = bus_wren_last[i] | wren_reset_miss[i];
+				assign wren_reset_miss[i] = replace_way_mb_any[i] & reset_tag_valid_for_miss;
+			end
+			assign bus_ic_wr_en[pt[1060-:7] - 1:0] = bus_wren[pt[1060-:7] - 1:0];
+		end
+		else begin : icache_disabled
+			wire [pt[1060-:7]:1] sv2v_tmp_602A9;
+			assign sv2v_tmp_602A9 = {pt[1060-:7] {1'sb0}};
+			always @(*) ic_tag_valid_unq[pt[1060-:7] - 1:0] = sv2v_tmp_602A9;
+			wire [pt[1027-:7]:1] sv2v_tmp_89B17;
+			assign sv2v_tmp_89B17 = {pt[1027-:7] {1'sb0}};
+			always @(*) way_status[pt[1027-:7] - 1:0] = sv2v_tmp_89B17;
+			assign replace_way_mb_any[pt[1060-:7] - 1:0] = {pt[1060-:7] {1'sb0}};
+			assign way_status_hit_new[pt[1027-:7] - 1:0] = {pt[1027-:7] {1'sb0}};
+			assign way_status_rep_new[pt[1027-:7] - 1:0] = {pt[1027-:7] {1'sb0}};
+			assign way_status_new[pt[1027-:7] - 1:0] = {pt[1027-:7] {1'sb0}};
+			assign way_status_wr_en = 1'b0;
+			assign bus_wren[pt[1060-:7] - 1:0] = {pt[1060-:7] {1'sb0}};
+		end
+	endgenerate
+	assign ic_tag_valid[pt[1060-:7] - 1:0] = ic_tag_valid_unq[pt[1060-:7] - 1:0] & {pt[1060-:7] {~fetch_uncacheable_ff & ifc_fetch_req_f_raw}};
+	assign ic_debug_tag_val_rd_out = |((ic_tag_valid_unq[pt[1060-:7] - 1:0] & ic_debug_way_ff[pt[1060-:7] - 1:0]) & {pt[1060-:7] {ic_debug_rd_en_ff}});
+	assign ifu_pmu_ic_miss_in = ic_act_miss_f;
+	assign ifu_pmu_ic_hit_in = ic_act_hit_f;
+	assign ifu_pmu_bus_error_in = |ifc_bus_acc_fault_f;
+	assign ifu_pmu_bus_trxn_in = bus_cmd_sent;
+	assign ifu_pmu_bus_busy_in = (ifu_bus_arvalid_ff & ~ifu_bus_arready_ff) & miss_pending;
+	rvdffie #(.WIDTH(9)) ifu_pmu_sigs_ff(
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.clk(free_l2clk),
+		.din({ifc_fetch_uncacheable_bf, ifc_fetch_req_qual_bf, dma_sb_err_state, dec_tlu_fence_i_wb, ifu_pmu_ic_miss_in, ifu_pmu_ic_hit_in, ifu_pmu_bus_error_in, ifu_pmu_bus_busy_in, ifu_pmu_bus_trxn_in}),
+		.dout({fetch_uncacheable_ff, ifc_fetch_req_f_raw, dma_sb_err_state_ff, reset_all_tags, ifu_pmu_ic_miss, ifu_pmu_ic_hit, ifu_pmu_bus_error, ifu_pmu_bus_busy, ifu_pmu_bus_trxn})
+	);
+	assign ic_debug_addr[pt[1104-:9]:3] = dec_tlu_ic_diag_pkt[pt[1104-:9] - 1:2];
+	assign ic_debug_way_enc[1:0] = dec_tlu_ic_diag_pkt[17:16];
+	assign ic_debug_tag_array = dec_tlu_ic_diag_pkt[18];
+	assign ic_debug_rd_en = dec_tlu_ic_diag_pkt[1];
+	assign ic_debug_wr_en = dec_tlu_ic_diag_pkt[0];
+	assign ic_debug_way[pt[1060-:7] - 1:0] = {ic_debug_way_enc[1:0] == 2'b11, ic_debug_way_enc[1:0] == 2'b10, ic_debug_way_enc[1:0] == 2'b01, ic_debug_way_enc[1:0] == 2'b00};
+	assign ic_debug_tag_wr_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0];
+	assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array;
+	rvdff_fpga #(.WIDTH(1 + pt[1060-:7])) ifu_debug_sel_ff(
+		.rst_l(rst_l),
+		.clk(debug_c1_clk),
+		.clken(debug_c1_clken),
+		.rawclk(clk),
+		.din({ic_debug_ict_array_sel_in, ic_debug_way[pt[1060-:7] - 1:0]}),
+		.dout({ic_debug_ict_array_sel_ff, ic_debug_way_ff[pt[1060-:7] - 1:0]})
+	);
+	assign debug_data_clken = ic_debug_rd_en_ff;
+	assign ifc_region_acc_okay = (((((((~(|{pt[530-:5], pt[525-:5], pt[520-:5], pt[515-:5], pt[510-:5], pt[505-:5], pt[500-:5], pt[495-:5]}) | (pt[530-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[490-:36]) == (pt[818-:36] | pt[490-:36])))) | (pt[525-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[454-:36]) == (pt[782-:36] | pt[454-:36])))) | (pt[520-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[418-:36]) == (pt[746-:36] | pt[418-:36])))) | (pt[515-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[382-:36]) == (pt[710-:36] | pt[382-:36])))) | (pt[510-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[346-:36]) == (pt[674-:36] | pt[346-:36])))) | (pt[505-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[310-:36]) == (pt[638-:36] | pt[310-:36])))) | (pt[500-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[274-:36]) == (pt[602-:36] | pt[274-:36])))) | (pt[495-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[238-:36]) == (pt[566-:36] | pt[238-:36])));
+	assign ifc_region_acc_fault_memory_bf = (~ifc_iccm_access_bf & ~ifc_region_acc_okay) & ifc_fetch_req_bf;
+	assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;
+endmodule
+module eb1_lsu (
+	clk_override,
+	dec_tlu_flush_lower_r,
+	dec_tlu_i0_kill_writeb_r,
+	dec_tlu_force_halt,
+	dec_tlu_external_ldfwd_disable,
+	dec_tlu_wb_coalescing_disable,
+	dec_tlu_sideeffect_posted_disable,
+	dec_tlu_core_ecc_disable,
+	exu_lsu_rs1_d,
+	exu_lsu_rs2_d,
+	dec_lsu_offset_d,
+	lsu_p,
+	dec_lsu_valid_raw_d,
+	dec_tlu_mrac_ff,
+	lsu_result_m,
+	lsu_result_corr_r,
+	lsu_load_stall_any,
+	lsu_store_stall_any,
+	lsu_fastint_stall_any,
+	lsu_idle_any,
+	lsu_active,
+	lsu_fir_addr,
+	lsu_fir_error,
+	lsu_single_ecc_error_incr,
+	lsu_error_pkt_r,
+	lsu_imprecise_error_load_any,
+	lsu_imprecise_error_store_any,
+	lsu_imprecise_error_addr_any,
+	lsu_nonblock_load_valid_m,
+	lsu_nonblock_load_tag_m,
+	lsu_nonblock_load_inv_r,
+	lsu_nonblock_load_inv_tag_r,
+	lsu_nonblock_load_data_valid,
+	lsu_nonblock_load_data_error,
+	lsu_nonblock_load_data_tag,
+	lsu_nonblock_load_data,
+	lsu_pmu_load_external_m,
+	lsu_pmu_store_external_m,
+	lsu_pmu_misaligned_m,
+	lsu_pmu_bus_trxn,
+	lsu_pmu_bus_misaligned,
+	lsu_pmu_bus_error,
+	lsu_pmu_bus_busy,
+	trigger_pkt_any,
+	lsu_trigger_match_m,
+	dccm_wren,
+	dccm_rden,
+	dccm_wr_addr_lo,
+	dccm_wr_addr_hi,
+	dccm_rd_addr_lo,
+	dccm_rd_addr_hi,
+	dccm_wr_data_lo,
+	dccm_wr_data_hi,
+	dccm_rd_data_lo,
+	dccm_rd_data_hi,
+	picm_wren,
+	picm_rden,
+	picm_mken,
+	picm_rdaddr,
+	picm_wraddr,
+	picm_wr_data,
+	picm_rd_data,
+	lsu_axi_awvalid,
+	lsu_axi_awready,
+	lsu_axi_awid,
+	lsu_axi_awaddr,
+	lsu_axi_awregion,
+	lsu_axi_awlen,
+	lsu_axi_awsize,
+	lsu_axi_awburst,
+	lsu_axi_awlock,
+	lsu_axi_awcache,
+	lsu_axi_awprot,
+	lsu_axi_awqos,
+	lsu_axi_wvalid,
+	lsu_axi_wready,
+	lsu_axi_wdata,
+	lsu_axi_wstrb,
+	lsu_axi_wlast,
+	lsu_axi_bvalid,
+	lsu_axi_bready,
+	lsu_axi_bresp,
+	lsu_axi_bid,
+	lsu_axi_arvalid,
+	lsu_axi_arready,
+	lsu_axi_arid,
+	lsu_axi_araddr,
+	lsu_axi_arregion,
+	lsu_axi_arlen,
+	lsu_axi_arsize,
+	lsu_axi_arburst,
+	lsu_axi_arlock,
+	lsu_axi_arcache,
+	lsu_axi_arprot,
+	lsu_axi_arqos,
+	lsu_axi_rvalid,
+	lsu_axi_rready,
+	lsu_axi_rid,
+	lsu_axi_rdata,
+	lsu_axi_rresp,
+	lsu_axi_rlast,
+	lsu_bus_clk_en,
+	dma_dccm_req,
+	dma_mem_tag,
+	dma_mem_addr,
+	dma_mem_sz,
+	dma_mem_write,
+	dma_mem_wdata,
+	dccm_dma_rvalid,
+	dccm_dma_ecc_error,
+	dccm_dma_rtag,
+	dccm_dma_rdata,
+	dccm_ready,
+	scan_mode,
+	clk,
+	active_clk,
+	rst_l
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk_override;
+	input wire dec_tlu_flush_lower_r;
+	input wire dec_tlu_i0_kill_writeb_r;
+	input wire dec_tlu_force_halt;
+	input wire dec_tlu_external_ldfwd_disable;
+	input wire dec_tlu_wb_coalescing_disable;
+	input wire dec_tlu_sideeffect_posted_disable;
+	input wire dec_tlu_core_ecc_disable;
+	input wire [31:0] exu_lsu_rs1_d;
+	input wire [31:0] exu_lsu_rs2_d;
+	input wire [11:0] dec_lsu_offset_d;
+	input wire [13:0] lsu_p;
+	input wire dec_lsu_valid_raw_d;
+	input wire [31:0] dec_tlu_mrac_ff;
+	output wire [31:0] lsu_result_m;
+	output wire [31:0] lsu_result_corr_r;
+	output wire lsu_load_stall_any;
+	output wire lsu_store_stall_any;
+	output wire lsu_fastint_stall_any;
+	output wire lsu_idle_any;
+	output wire lsu_active;
+	output wire [31:1] lsu_fir_addr;
+	output wire [1:0] lsu_fir_error;
+	output wire lsu_single_ecc_error_incr;
+	output wire [39:0] lsu_error_pkt_r;
+	output wire lsu_imprecise_error_load_any;
+	output wire lsu_imprecise_error_store_any;
+	output wire [31:0] lsu_imprecise_error_addr_any;
+	output wire lsu_nonblock_load_valid_m;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	output wire lsu_nonblock_load_inv_r;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	output wire lsu_nonblock_load_data_valid;
+	output wire lsu_nonblock_load_data_error;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	output wire [31:0] lsu_nonblock_load_data;
+	output wire lsu_pmu_load_external_m;
+	output wire lsu_pmu_store_external_m;
+	output wire lsu_pmu_misaligned_m;
+	output wire lsu_pmu_bus_trxn;
+	output wire lsu_pmu_bus_misaligned;
+	output wire lsu_pmu_bus_error;
+	output wire lsu_pmu_bus_busy;
+	input wire [151:0] trigger_pkt_any;
+	output wire [3:0] lsu_trigger_match_m;
+	output wire dccm_wren;
+	output wire dccm_rden;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	output wire picm_wren;
+	output wire picm_rden;
+	output wire picm_mken;
+	output wire [31:0] picm_rdaddr;
+	output wire [31:0] picm_wraddr;
+	output wire [31:0] picm_wr_data;
+	input wire [31:0] picm_rd_data;
+	output wire lsu_axi_awvalid;
+	input wire lsu_axi_awready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_awid;
+	output wire [31:0] lsu_axi_awaddr;
+	output wire [3:0] lsu_axi_awregion;
+	output wire [7:0] lsu_axi_awlen;
+	output wire [2:0] lsu_axi_awsize;
+	output wire [1:0] lsu_axi_awburst;
+	output wire lsu_axi_awlock;
+	output wire [3:0] lsu_axi_awcache;
+	output wire [2:0] lsu_axi_awprot;
+	output wire [3:0] lsu_axi_awqos;
+	output wire lsu_axi_wvalid;
+	input wire lsu_axi_wready;
+	output wire [63:0] lsu_axi_wdata;
+	output wire [7:0] lsu_axi_wstrb;
+	output wire lsu_axi_wlast;
+	input wire lsu_axi_bvalid;
+	output wire lsu_axi_bready;
+	input wire [1:0] lsu_axi_bresp;
+	input wire [pt[181-:8] - 1:0] lsu_axi_bid;
+	output wire lsu_axi_arvalid;
+	input wire lsu_axi_arready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_arid;
+	output wire [31:0] lsu_axi_araddr;
+	output wire [3:0] lsu_axi_arregion;
+	output wire [7:0] lsu_axi_arlen;
+	output wire [2:0] lsu_axi_arsize;
+	output wire [1:0] lsu_axi_arburst;
+	output wire lsu_axi_arlock;
+	output wire [3:0] lsu_axi_arcache;
+	output wire [2:0] lsu_axi_arprot;
+	output wire [3:0] lsu_axi_arqos;
+	input wire lsu_axi_rvalid;
+	output wire lsu_axi_rready;
+	input wire [pt[181-:8] - 1:0] lsu_axi_rid;
+	input wire [63:0] lsu_axi_rdata;
+	input wire [1:0] lsu_axi_rresp;
+	input wire lsu_axi_rlast;
+	input wire lsu_bus_clk_en;
+	input wire dma_dccm_req;
+	input wire [2:0] dma_mem_tag;
+	input wire [31:0] dma_mem_addr;
+	input wire [2:0] dma_mem_sz;
+	input wire dma_mem_write;
+	input wire [63:0] dma_mem_wdata;
+	output wire dccm_dma_rvalid;
+	output wire dccm_dma_ecc_error;
+	output wire [2:0] dccm_dma_rtag;
+	output wire [63:0] dccm_dma_rdata;
+	output wire dccm_ready;
+	input wire scan_mode;
+	input wire clk;
+	input wire active_clk;
+	input wire rst_l;
+	wire lsu_dccm_rden_m;
+	wire lsu_dccm_rden_r;
+	wire [31:0] store_data_m;
+	wire [31:0] store_data_r;
+	wire [31:0] store_data_hi_r;
+	wire [31:0] store_data_lo_r;
+	wire [31:0] store_datafn_hi_r;
+	wire [31:0] store_datafn_lo_r;
+	wire [31:0] sec_data_lo_m;
+	wire [31:0] sec_data_hi_m;
+	wire [31:0] sec_data_lo_r;
+	wire [31:0] sec_data_hi_r;
+	wire [31:0] lsu_ld_data_m;
+	wire [31:0] dccm_rdata_hi_m;
+	wire [31:0] dccm_rdata_lo_m;
+	wire [6:0] dccm_data_ecc_hi_m;
+	wire [6:0] dccm_data_ecc_lo_m;
+	wire lsu_single_ecc_error_m;
+	wire lsu_double_ecc_error_m;
+	wire [31:0] lsu_ld_data_r;
+	wire [31:0] lsu_ld_data_corr_r;
+	wire [31:0] dccm_rdata_hi_r;
+	wire [31:0] dccm_rdata_lo_r;
+	wire [6:0] dccm_data_ecc_hi_r;
+	wire [6:0] dccm_data_ecc_lo_r;
+	wire single_ecc_error_hi_r;
+	wire single_ecc_error_lo_r;
+	wire lsu_single_ecc_error_r;
+	wire lsu_double_ecc_error_r;
+	wire ld_single_ecc_error_r;
+	wire ld_single_ecc_error_r_ff;
+	wire [31:0] picm_mask_data_m;
+	wire [31:0] lsu_addr_d;
+	wire [31:0] lsu_addr_m;
+	wire [31:0] lsu_addr_r;
+	wire [31:0] end_addr_d;
+	wire [31:0] end_addr_m;
+	wire [31:0] end_addr_r;
+	wire [13:0] lsu_pkt_d;
+	wire [13:0] lsu_pkt_m;
+	wire [13:0] lsu_pkt_r;
+	wire lsu_i0_valid_d;
+	wire lsu_i0_valid_m;
+	wire lsu_i0_valid_r;
+	wire store_stbuf_reqvld_r;
+	wire ldst_stbuf_reqvld_r;
+	wire lsu_commit_r;
+	wire lsu_exc_m;
+	wire addr_in_dccm_d;
+	wire addr_in_dccm_m;
+	wire addr_in_dccm_r;
+	wire addr_in_pic_d;
+	wire addr_in_pic_m;
+	wire addr_in_pic_r;
+	wire ldst_dual_d;
+	wire ldst_dual_m;
+	wire ldst_dual_r;
+	wire addr_external_m;
+	wire stbuf_reqvld_any;
+	wire stbuf_reqvld_flushed_any;
+	wire [pt[157-:9] - 1:0] stbuf_addr_any;
+	wire [pt[1382-:10] - 1:0] stbuf_data_any;
+	wire [pt[1372-:7] - 1:0] stbuf_ecc_any;
+	wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff;
+	wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff;
+	wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff;
+	wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff;
+	wire lsu_cmpen_m;
+	wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m;
+	wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m;
+	wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m;
+	wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m;
+	wire lsu_stbuf_commit_any;
+	wire lsu_stbuf_empty_any;
+	wire lsu_stbuf_full_any;
+	wire lsu_busreq_r;
+	wire lsu_bus_buffer_pend_any;
+	wire lsu_bus_buffer_empty_any;
+	wire lsu_bus_buffer_full_any;
+	wire lsu_busreq_m;
+	wire [31:0] bus_read_data_m;
+	wire flush_m_up;
+	wire flush_r;
+	wire is_sideeffects_m;
+	wire [2:0] dma_mem_tag_d;
+	wire [2:0] dma_mem_tag_m;
+	wire ldst_nodma_mtor;
+	wire dma_dccm_wen;
+	wire dma_pic_wen;
+	wire [31:0] dma_dccm_wdata_lo;
+	wire [31:0] dma_dccm_wdata_hi;
+	wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo;
+	wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi;
+	wire lsu_busm_clken;
+	wire lsu_bus_obuf_c1_clken;
+	wire lsu_c1_m_clk;
+	wire lsu_c1_r_clk;
+	wire lsu_c2_m_clk;
+	wire lsu_c2_r_clk;
+	wire lsu_store_c1_m_clk;
+	wire lsu_store_c1_r_clk;
+	wire lsu_stbuf_c1_clk;
+	wire lsu_bus_ibuf_c1_clk;
+	wire lsu_bus_obuf_c1_clk;
+	wire lsu_bus_buf_c1_clk;
+	wire lsu_busm_clk;
+	wire lsu_free_c2_clk;
+	wire lsu_raw_fwd_lo_m;
+	wire lsu_raw_fwd_hi_m;
+	wire lsu_raw_fwd_lo_r;
+	wire lsu_raw_fwd_hi_r;
+	assign lsu_raw_fwd_lo_m = |stbuf_fwdbyteen_lo_m[pt[1389-:7] - 1:0];
+	assign lsu_raw_fwd_hi_m = |stbuf_fwdbyteen_hi_m[pt[1389-:7] - 1:0];
+	eb1_lsu_lsc_ctl #(.pt(pt)) lsu_lsc_ctl(
+		.rst_l(rst_l),
+		.clk_override(clk_override),
+		.clk(clk),
+		.lsu_c1_m_clk(lsu_c1_m_clk),
+		.lsu_c1_r_clk(lsu_c1_r_clk),
+		.lsu_c2_m_clk(lsu_c2_m_clk),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.lsu_store_c1_m_clk(lsu_store_c1_m_clk),
+		.lsu_ld_data_r(lsu_ld_data_r),
+		.lsu_ld_data_corr_r(lsu_ld_data_corr_r),
+		.lsu_single_ecc_error_r(lsu_single_ecc_error_r),
+		.lsu_double_ecc_error_r(lsu_double_ecc_error_r),
+		.lsu_ld_data_m(lsu_ld_data_m),
+		.lsu_single_ecc_error_m(lsu_single_ecc_error_m),
+		.lsu_double_ecc_error_m(lsu_double_ecc_error_m),
+		.flush_m_up(flush_m_up),
+		.flush_r(flush_r),
+		.ldst_dual_d(ldst_dual_d),
+		.ldst_dual_m(ldst_dual_m),
+		.ldst_dual_r(ldst_dual_r),
+		.exu_lsu_rs1_d(exu_lsu_rs1_d),
+		.exu_lsu_rs2_d(exu_lsu_rs2_d),
+		.lsu_p(lsu_p),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.dec_lsu_offset_d(dec_lsu_offset_d),
+		.picm_mask_data_m(picm_mask_data_m),
+		.bus_read_data_m(bus_read_data_m),
+		.lsu_result_m(lsu_result_m),
+		.lsu_result_corr_r(lsu_result_corr_r),
+		.lsu_addr_d(lsu_addr_d),
+		.lsu_addr_m(lsu_addr_m),
+		.lsu_addr_r(lsu_addr_r),
+		.end_addr_d(end_addr_d),
+		.end_addr_m(end_addr_m),
+		.end_addr_r(end_addr_r),
+		.store_data_m(store_data_m),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.lsu_exc_m(lsu_exc_m),
+		.is_sideeffects_m(is_sideeffects_m),
+		.lsu_commit_r(lsu_commit_r),
+		.lsu_single_ecc_error_incr(lsu_single_ecc_error_incr),
+		.lsu_error_pkt_r(lsu_error_pkt_r),
+		.lsu_fir_addr(lsu_fir_addr),
+		.lsu_fir_error(lsu_fir_error),
+		.addr_in_dccm_d(addr_in_dccm_d),
+		.addr_in_dccm_m(addr_in_dccm_m),
+		.addr_in_dccm_r(addr_in_dccm_r),
+		.addr_in_pic_d(addr_in_pic_d),
+		.addr_in_pic_m(addr_in_pic_m),
+		.addr_in_pic_r(addr_in_pic_r),
+		.addr_external_m(addr_external_m),
+		.dma_dccm_req(dma_dccm_req),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_sz(dma_mem_sz),
+		.dma_mem_write(dma_mem_write),
+		.dma_mem_wdata(dma_mem_wdata),
+		.lsu_pkt_d(lsu_pkt_d),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.scan_mode(scan_mode)
+	);
+	assign lsu_store_stall_any = (lsu_stbuf_full_any | lsu_bus_buffer_full_any) | ld_single_ecc_error_r_ff;
+	assign lsu_load_stall_any = lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff;
+	assign lsu_fastint_stall_any = ld_single_ecc_error_r;
+	assign dma_mem_tag_d[2:0] = dma_mem_tag[2:0];
+	assign ldst_nodma_mtor = ((lsu_pkt_m[0] & ~lsu_pkt_m[4]) & (addr_in_dccm_m | addr_in_pic_m)) & lsu_pkt_m[6];
+	assign dccm_ready = ~((dec_lsu_valid_raw_d | ldst_nodma_mtor) | ld_single_ecc_error_r_ff);
+	assign dma_dccm_wen = ((dma_dccm_req & dma_mem_write) & addr_in_dccm_d) & dma_mem_sz[1];
+	assign dma_pic_wen = (dma_dccm_req & dma_mem_write) & addr_in_pic_d;
+	assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000};
+	assign flush_m_up = dec_tlu_flush_lower_r;
+	assign flush_r = dec_tlu_i0_kill_writeb_r;
+	assign lsu_idle_any = ~((lsu_pkt_m[0] & ~lsu_pkt_m[4]) | (lsu_pkt_r[0] & ~lsu_pkt_r[4])) & lsu_bus_buffer_empty_any;
+	assign lsu_active = ((lsu_pkt_m[0] | lsu_pkt_r[0]) | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any;
+	assign store_stbuf_reqvld_r = (((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_dccm_r) & ~flush_r) & (~lsu_pkt_r[4] | ((lsu_pkt_r[11] | lsu_pkt_r[10]) & ~lsu_double_ecc_error_r));
+	assign lsu_cmpen_m = (lsu_pkt_m[0] & (lsu_pkt_m[7] | lsu_pkt_m[6])) & (addr_in_dccm_m | addr_in_pic_m);
+	assign lsu_busreq_m = (((lsu_pkt_m[0] & ((lsu_pkt_m[7] | lsu_pkt_m[6]) & addr_external_m)) & ~flush_m_up) & ~lsu_exc_m) & ~lsu_pkt_m[13];
+	assign ldst_dual_d = lsu_addr_d[2] != end_addr_d[2];
+	assign ldst_dual_m = lsu_addr_m[2] != end_addr_m[2];
+	assign ldst_dual_r = lsu_addr_r[2] != end_addr_r[2];
+	assign lsu_pmu_misaligned_m = lsu_pkt_m[0] & ((lsu_pkt_m[10] & lsu_addr_m[0]) | (lsu_pkt_m[9] & |lsu_addr_m[1:0]));
+	assign lsu_pmu_load_external_m = (lsu_pkt_m[0] & lsu_pkt_m[7]) & addr_external_m;
+	assign lsu_pmu_store_external_m = (lsu_pkt_m[0] & lsu_pkt_m[6]) & addr_external_m;
+	eb1_lsu_dccm_ctl #(.pt(pt)) dccm_ctl(
+		.lsu_addr_d(lsu_addr_d[31:0]),
+		.end_addr_d(end_addr_d[pt[1398-:9] - 1:0]),
+		.lsu_addr_m(lsu_addr_m[pt[1398-:9] - 1:0]),
+		.lsu_addr_r(lsu_addr_r[31:0]),
+		.end_addr_m(end_addr_m[pt[1398-:9] - 1:0]),
+		.end_addr_r(end_addr_r[pt[1398-:9] - 1:0]),
+		.lsu_c2_m_clk(lsu_c2_m_clk),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.lsu_c1_r_clk(lsu_c1_r_clk),
+		.lsu_store_c1_r_clk(lsu_store_c1_r_clk),
+		.lsu_free_c2_clk(lsu_free_c2_clk),
+		.clk_override(clk_override),
+		.clk(clk),
+		.rst_l(rst_l),
+		.lsu_pkt_r(lsu_pkt_r),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_d(lsu_pkt_d),
+		.addr_in_dccm_d(addr_in_dccm_d),
+		.addr_in_pic_d(addr_in_pic_d),
+		.addr_in_pic_m(addr_in_pic_m),
+		.addr_in_dccm_m(addr_in_dccm_m),
+		.addr_in_dccm_r(addr_in_dccm_r),
+		.addr_in_pic_r(addr_in_pic_r),
+		.lsu_raw_fwd_lo_r(lsu_raw_fwd_lo_r),
+		.lsu_raw_fwd_hi_r(lsu_raw_fwd_hi_r),
+		.lsu_commit_r(lsu_commit_r),
+		.ldst_dual_m(ldst_dual_m),
+		.ldst_dual_r(ldst_dual_r),
+		.stbuf_reqvld_any(stbuf_reqvld_any),
+		.stbuf_addr_any(stbuf_addr_any),
+		.stbuf_data_any(stbuf_data_any),
+		.stbuf_ecc_any(stbuf_ecc_any),
+		.stbuf_fwddata_hi_m(stbuf_fwddata_hi_m),
+		.stbuf_fwddata_lo_m(stbuf_fwddata_lo_m),
+		.stbuf_fwdbyteen_hi_m(stbuf_fwdbyteen_hi_m),
+		.stbuf_fwdbyteen_lo_m(stbuf_fwdbyteen_lo_m),
+		.dccm_rdata_hi_r(dccm_rdata_hi_r),
+		.dccm_rdata_lo_r(dccm_rdata_lo_r),
+		.dccm_data_ecc_hi_r(dccm_data_ecc_hi_r),
+		.dccm_data_ecc_lo_r(dccm_data_ecc_lo_r),
+		.lsu_ld_data_r(lsu_ld_data_r),
+		.lsu_ld_data_corr_r(lsu_ld_data_corr_r),
+		.lsu_double_ecc_error_r(lsu_double_ecc_error_r),
+		.single_ecc_error_hi_r(single_ecc_error_hi_r),
+		.single_ecc_error_lo_r(single_ecc_error_lo_r),
+		.sec_data_hi_r(sec_data_hi_r),
+		.sec_data_lo_r(sec_data_lo_r),
+		.sec_data_hi_r_ff(sec_data_hi_r_ff),
+		.sec_data_lo_r_ff(sec_data_lo_r_ff),
+		.sec_data_ecc_hi_r_ff(sec_data_ecc_hi_r_ff),
+		.sec_data_ecc_lo_r_ff(sec_data_ecc_lo_r_ff),
+		.dccm_rdata_hi_m(dccm_rdata_hi_m),
+		.dccm_rdata_lo_m(dccm_rdata_lo_m),
+		.dccm_data_ecc_hi_m(dccm_data_ecc_hi_m),
+		.dccm_data_ecc_lo_m(dccm_data_ecc_lo_m),
+		.lsu_ld_data_m(lsu_ld_data_m),
+		.lsu_double_ecc_error_m(lsu_double_ecc_error_m),
+		.sec_data_hi_m(sec_data_hi_m),
+		.sec_data_lo_m(sec_data_lo_m),
+		.store_data_m(store_data_m),
+		.dma_dccm_wen(dma_dccm_wen),
+		.dma_pic_wen(dma_pic_wen),
+		.dma_mem_tag_m(dma_mem_tag_m),
+		.dma_mem_addr(dma_mem_addr),
+		.dma_mem_wdata(dma_mem_wdata),
+		.dma_dccm_wdata_lo(dma_dccm_wdata_lo),
+		.dma_dccm_wdata_hi(dma_dccm_wdata_hi),
+		.dma_dccm_wdata_ecc_hi(dma_dccm_wdata_ecc_hi),
+		.dma_dccm_wdata_ecc_lo(dma_dccm_wdata_ecc_lo),
+		.store_data_hi_r(store_data_hi_r),
+		.store_data_lo_r(store_data_lo_r),
+		.store_datafn_hi_r(store_datafn_hi_r),
+		.store_datafn_lo_r(store_datafn_lo_r),
+		.store_data_r(store_data_r),
+		.ld_single_ecc_error_r(ld_single_ecc_error_r),
+		.ld_single_ecc_error_r_ff(ld_single_ecc_error_r_ff),
+		.picm_mask_data_m(picm_mask_data_m),
+		.lsu_stbuf_commit_any(lsu_stbuf_commit_any),
+		.lsu_dccm_rden_m(lsu_dccm_rden_m),
+		.lsu_dccm_rden_r(lsu_dccm_rden_r),
+		.dccm_dma_rvalid(dccm_dma_rvalid),
+		.dccm_dma_ecc_error(dccm_dma_ecc_error),
+		.dccm_dma_rtag(dccm_dma_rtag),
+		.dccm_dma_rdata(dccm_dma_rdata),
+		.dccm_wren(dccm_wren),
+		.dccm_rden(dccm_rden),
+		.dccm_wr_addr_lo(dccm_wr_addr_lo),
+		.dccm_wr_addr_hi(dccm_wr_addr_hi),
+		.dccm_rd_addr_lo(dccm_rd_addr_lo),
+		.dccm_rd_addr_hi(dccm_rd_addr_hi),
+		.dccm_wr_data_lo(dccm_wr_data_lo),
+		.dccm_wr_data_hi(dccm_wr_data_hi),
+		.dccm_rd_data_lo(dccm_rd_data_lo),
+		.dccm_rd_data_hi(dccm_rd_data_hi),
+		.picm_wren(picm_wren),
+		.picm_rden(picm_rden),
+		.picm_mken(picm_mken),
+		.picm_rdaddr(picm_rdaddr),
+		.picm_wraddr(picm_wraddr),
+		.picm_wr_data(picm_wr_data),
+		.picm_rd_data(picm_rd_data),
+		.scan_mode(scan_mode)
+	);
+	eb1_lsu_stbuf #(.pt(pt)) stbuf(
+		.lsu_addr_d(lsu_addr_d[pt[157-:9] - 1:0]),
+		.end_addr_d(end_addr_d[pt[157-:9] - 1:0]),
+		.clk(clk),
+		.rst_l(rst_l),
+		.lsu_stbuf_c1_clk(lsu_stbuf_c1_clk),
+		.lsu_free_c2_clk(lsu_free_c2_clk),
+		.store_stbuf_reqvld_r(store_stbuf_reqvld_r),
+		.lsu_commit_r(lsu_commit_r),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.store_data_hi_r(store_data_hi_r),
+		.store_data_lo_r(store_data_lo_r),
+		.store_datafn_hi_r(store_datafn_hi_r),
+		.store_datafn_lo_r(store_datafn_lo_r),
+		.stbuf_reqvld_any(stbuf_reqvld_any),
+		.stbuf_reqvld_flushed_any(stbuf_reqvld_flushed_any),
+		.stbuf_addr_any(stbuf_addr_any),
+		.stbuf_data_any(stbuf_data_any),
+		.lsu_stbuf_commit_any(lsu_stbuf_commit_any),
+		.lsu_stbuf_full_any(lsu_stbuf_full_any),
+		.lsu_stbuf_empty_any(lsu_stbuf_empty_any),
+		.ldst_stbuf_reqvld_r(ldst_stbuf_reqvld_r),
+		.lsu_addr_m(lsu_addr_m),
+		.lsu_addr_r(lsu_addr_r),
+		.end_addr_m(end_addr_m),
+		.end_addr_r(end_addr_r),
+		.ldst_dual_d(ldst_dual_d),
+		.ldst_dual_m(ldst_dual_m),
+		.ldst_dual_r(ldst_dual_r),
+		.addr_in_dccm_m(addr_in_dccm_m),
+		.addr_in_dccm_r(addr_in_dccm_r),
+		.lsu_cmpen_m(lsu_cmpen_m),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.stbuf_fwddata_hi_m(stbuf_fwddata_hi_m),
+		.stbuf_fwddata_lo_m(stbuf_fwddata_lo_m),
+		.stbuf_fwdbyteen_hi_m(stbuf_fwdbyteen_hi_m),
+		.stbuf_fwdbyteen_lo_m(stbuf_fwdbyteen_lo_m),
+		.scan_mode(scan_mode)
+	);
+	eb1_lsu_ecc #(.pt(pt)) ecc(
+		.lsu_addr_r(lsu_addr_r[pt[1398-:9] - 1:0]),
+		.end_addr_r(end_addr_r[pt[1398-:9] - 1:0]),
+		.lsu_addr_m(lsu_addr_m[pt[1398-:9] - 1:0]),
+		.end_addr_m(end_addr_m[pt[1398-:9] - 1:0]),
+		.clk(clk),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.clk_override(clk_override),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.stbuf_data_any(stbuf_data_any),
+		.dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable),
+		.lsu_dccm_rden_r(lsu_dccm_rden_r),
+		.addr_in_dccm_r(addr_in_dccm_r),
+		.dccm_rdata_hi_r(dccm_rdata_hi_r),
+		.dccm_rdata_lo_r(dccm_rdata_lo_r),
+		.dccm_data_ecc_hi_r(dccm_data_ecc_hi_r),
+		.dccm_data_ecc_lo_r(dccm_data_ecc_lo_r),
+		.sec_data_hi_r(sec_data_hi_r),
+		.sec_data_lo_r(sec_data_lo_r),
+		.sec_data_hi_r_ff(sec_data_hi_r_ff),
+		.sec_data_lo_r_ff(sec_data_lo_r_ff),
+		.ld_single_ecc_error_r(ld_single_ecc_error_r),
+		.ld_single_ecc_error_r_ff(ld_single_ecc_error_r_ff),
+		.lsu_dccm_rden_m(lsu_dccm_rden_m),
+		.addr_in_dccm_m(addr_in_dccm_m),
+		.dccm_rdata_hi_m(dccm_rdata_hi_m),
+		.dccm_rdata_lo_m(dccm_rdata_lo_m),
+		.dccm_data_ecc_hi_m(dccm_data_ecc_hi_m),
+		.dccm_data_ecc_lo_m(dccm_data_ecc_lo_m),
+		.sec_data_hi_m(sec_data_hi_m),
+		.sec_data_lo_m(sec_data_lo_m),
+		.dma_dccm_wen(dma_dccm_wen),
+		.dma_dccm_wdata_lo(dma_dccm_wdata_lo),
+		.dma_dccm_wdata_hi(dma_dccm_wdata_hi),
+		.dma_dccm_wdata_ecc_hi(dma_dccm_wdata_ecc_hi),
+		.dma_dccm_wdata_ecc_lo(dma_dccm_wdata_ecc_lo),
+		.stbuf_ecc_any(stbuf_ecc_any),
+		.sec_data_ecc_hi_r_ff(sec_data_ecc_hi_r_ff),
+		.sec_data_ecc_lo_r_ff(sec_data_ecc_lo_r_ff),
+		.single_ecc_error_hi_r(single_ecc_error_hi_r),
+		.single_ecc_error_lo_r(single_ecc_error_lo_r),
+		.lsu_single_ecc_error_r(lsu_single_ecc_error_r),
+		.lsu_double_ecc_error_r(lsu_double_ecc_error_r),
+		.lsu_single_ecc_error_m(lsu_single_ecc_error_m),
+		.lsu_double_ecc_error_m(lsu_double_ecc_error_m)
+	);
+	eb1_lsu_trigger #(.pt(pt)) trigger(
+		.store_data_m(store_data_m[31:0]),
+		.trigger_pkt_any(trigger_pkt_any),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_addr_m(lsu_addr_m),
+		.lsu_trigger_match_m(lsu_trigger_match_m)
+	);
+	eb1_lsu_clkdomain #(.pt(pt)) clkdomain(
+		.clk(clk),
+		.active_clk(active_clk),
+		.rst_l(rst_l),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.clk_override(clk_override),
+		.dma_dccm_req(dma_dccm_req),
+		.ldst_stbuf_reqvld_r(ldst_stbuf_reqvld_r),
+		.stbuf_reqvld_any(stbuf_reqvld_any),
+		.stbuf_reqvld_flushed_any(stbuf_reqvld_flushed_any),
+		.lsu_busreq_r(lsu_busreq_r),
+		.lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any),
+		.lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any),
+		.lsu_stbuf_empty_any(lsu_stbuf_empty_any),
+		.lsu_bus_clk_en(lsu_bus_clk_en),
+		.lsu_p(lsu_p),
+		.lsu_pkt_d(lsu_pkt_d),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken),
+		.lsu_busm_clken(lsu_busm_clken),
+		.lsu_c1_m_clk(lsu_c1_m_clk),
+		.lsu_c1_r_clk(lsu_c1_r_clk),
+		.lsu_c2_m_clk(lsu_c2_m_clk),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.lsu_store_c1_m_clk(lsu_store_c1_m_clk),
+		.lsu_store_c1_r_clk(lsu_store_c1_r_clk),
+		.lsu_stbuf_c1_clk(lsu_stbuf_c1_clk),
+		.lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk),
+		.lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk),
+		.lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk),
+		.lsu_busm_clk(lsu_busm_clk),
+		.lsu_free_c2_clk(lsu_free_c2_clk),
+		.scan_mode(scan_mode)
+	);
+	eb1_lsu_bus_intf #(.pt(pt)) bus_intf(
+		.lsu_addr_m(lsu_addr_m[31:0] & {32 {addr_external_m & lsu_pkt_m[0]}}),
+		.lsu_addr_r(lsu_addr_r[31:0] & {32 {lsu_busreq_r}}),
+		.end_addr_m(end_addr_m[31:0] & {32 {addr_external_m & lsu_pkt_m[0]}}),
+		.end_addr_r(end_addr_r[31:0] & {32 {lsu_busreq_r}}),
+		.store_data_r(store_data_r[31:0] & {32 {lsu_busreq_r}}),
+		.clk(clk),
+		.clk_override(clk_override),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable),
+		.dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable),
+		.dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable),
+		.lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken),
+		.lsu_busm_clken(lsu_busm_clken),
+		.lsu_c1_r_clk(lsu_c1_r_clk),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk),
+		.lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk),
+		.lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk),
+		.lsu_free_c2_clk(lsu_free_c2_clk),
+		.active_clk(active_clk),
+		.lsu_busm_clk(lsu_busm_clk),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.lsu_busreq_m(lsu_busreq_m),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.lsu_commit_r(lsu_commit_r),
+		.is_sideeffects_m(is_sideeffects_m),
+		.flush_m_up(flush_m_up),
+		.flush_r(flush_r),
+		.ldst_dual_d(ldst_dual_d),
+		.ldst_dual_m(ldst_dual_m),
+		.ldst_dual_r(ldst_dual_r),
+		.lsu_busreq_r(lsu_busreq_r),
+		.lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any),
+		.lsu_bus_buffer_full_any(lsu_bus_buffer_full_any),
+		.lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any),
+		.bus_read_data_m(bus_read_data_m),
+		.lsu_imprecise_error_load_any(lsu_imprecise_error_load_any),
+		.lsu_imprecise_error_store_any(lsu_imprecise_error_store_any),
+		.lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any),
+		.lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m),
+		.lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m),
+		.lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r),
+		.lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r),
+		.lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid),
+		.lsu_nonblock_load_data_error(lsu_nonblock_load_data_error),
+		.lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag),
+		.lsu_nonblock_load_data(lsu_nonblock_load_data),
+		.lsu_pmu_bus_trxn(lsu_pmu_bus_trxn),
+		.lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned),
+		.lsu_pmu_bus_error(lsu_pmu_bus_error),
+		.lsu_pmu_bus_busy(lsu_pmu_bus_busy),
+		.lsu_axi_awvalid(lsu_axi_awvalid),
+		.lsu_axi_awready(lsu_axi_awready),
+		.lsu_axi_awid(lsu_axi_awid),
+		.lsu_axi_awaddr(lsu_axi_awaddr),
+		.lsu_axi_awregion(lsu_axi_awregion),
+		.lsu_axi_awlen(lsu_axi_awlen),
+		.lsu_axi_awsize(lsu_axi_awsize),
+		.lsu_axi_awburst(lsu_axi_awburst),
+		.lsu_axi_awlock(lsu_axi_awlock),
+		.lsu_axi_awcache(lsu_axi_awcache),
+		.lsu_axi_awprot(lsu_axi_awprot),
+		.lsu_axi_awqos(lsu_axi_awqos),
+		.lsu_axi_wvalid(lsu_axi_wvalid),
+		.lsu_axi_wready(lsu_axi_wready),
+		.lsu_axi_wdata(lsu_axi_wdata),
+		.lsu_axi_wstrb(lsu_axi_wstrb),
+		.lsu_axi_wlast(lsu_axi_wlast),
+		.lsu_axi_bvalid(lsu_axi_bvalid),
+		.lsu_axi_bready(lsu_axi_bready),
+		.lsu_axi_bresp(lsu_axi_bresp),
+		.lsu_axi_bid(lsu_axi_bid),
+		.lsu_axi_arvalid(lsu_axi_arvalid),
+		.lsu_axi_arready(lsu_axi_arready),
+		.lsu_axi_arid(lsu_axi_arid),
+		.lsu_axi_araddr(lsu_axi_araddr),
+		.lsu_axi_arregion(lsu_axi_arregion),
+		.lsu_axi_arlen(lsu_axi_arlen),
+		.lsu_axi_arsize(lsu_axi_arsize),
+		.lsu_axi_arburst(lsu_axi_arburst),
+		.lsu_axi_arlock(lsu_axi_arlock),
+		.lsu_axi_arcache(lsu_axi_arcache),
+		.lsu_axi_arprot(lsu_axi_arprot),
+		.lsu_axi_arqos(lsu_axi_arqos),
+		.lsu_axi_rvalid(lsu_axi_rvalid),
+		.lsu_axi_rready(lsu_axi_rready),
+		.lsu_axi_rid(lsu_axi_rid),
+		.lsu_axi_rdata(lsu_axi_rdata),
+		.lsu_axi_rresp(lsu_axi_rresp),
+		.lsu_bus_clk_en(lsu_bus_clk_en)
+	);
+	rvdff #(.WIDTH(3)) dma_mem_tag_mff(
+		.rst_l(rst_l),
+		.din(dma_mem_tag_d[2:0]),
+		.dout(dma_mem_tag_m[2:0]),
+		.clk(lsu_c1_m_clk)
+	);
+	rvdff #(.WIDTH(2)) lsu_raw_fwd_r_ff(
+		.rst_l(rst_l),
+		.din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}),
+		.dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}),
+		.clk(lsu_c2_r_clk)
+	);
+endmodule
+module eb1_lsu_addrcheck (
+	lsu_c2_m_clk,
+	rst_l,
+	start_addr_d,
+	end_addr_d,
+	lsu_pkt_d,
+	dec_tlu_mrac_ff,
+	rs1_region_d,
+	rs1_d,
+	is_sideeffects_m,
+	addr_in_dccm_d,
+	addr_in_pic_d,
+	addr_external_d,
+	access_fault_d,
+	misaligned_fault_d,
+	exc_mscause_d,
+	fir_dccm_access_error_d,
+	fir_nondccm_access_error_d,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire lsu_c2_m_clk;
+	input wire rst_l;
+	input wire [31:0] start_addr_d;
+	input wire [31:0] end_addr_d;
+	input wire [13:0] lsu_pkt_d;
+	input wire [31:0] dec_tlu_mrac_ff;
+	input wire [3:0] rs1_region_d;
+	input wire [31:0] rs1_d;
+	output wire is_sideeffects_m;
+	output wire addr_in_dccm_d;
+	output wire addr_in_pic_d;
+	output wire addr_external_d;
+	output wire access_fault_d;
+	output wire misaligned_fault_d;
+	output wire [3:0] exc_mscause_d;
+	output wire fir_dccm_access_error_d;
+	output wire fir_nondccm_access_error_d;
+	input wire scan_mode;
+	wire non_dccm_access_ok;
+	wire is_sideeffects_d;
+	wire is_aligned_d;
+	wire start_addr_in_dccm_d;
+	wire end_addr_in_dccm_d;
+	wire start_addr_in_dccm_region_d;
+	wire end_addr_in_dccm_region_d;
+	wire start_addr_in_pic_d;
+	wire end_addr_in_pic_d;
+	wire start_addr_in_pic_region_d;
+	wire end_addr_in_pic_region_d;
+	wire [4:0] csr_idx;
+	wire addr_in_iccm;
+	wire start_addr_dccm_or_pic;
+	wire base_reg_dccm_or_pic;
+	wire unmapped_access_fault_d;
+	wire mpu_access_fault_d;
+	wire picm_access_fault_d;
+	wire regpred_access_fault_d;
+	wire regcross_misaligned_fault_d;
+	wire sideeffect_misaligned_fault_d;
+	wire [3:0] access_fault_mscause_d;
+	wire [3:0] misaligned_fault_mscause_d;
+	generate
+		if (pt[1365-:5] == 1) begin : Gen_dccm_enable
+			rvrangecheck #(
+				.CCM_SADR(pt[1325-:36]),
+				.CCM_SIZE(pt[1289-:14])
+			) start_addr_dccm_rangecheck(
+				.addr(start_addr_d[31:0]),
+				.in_range(start_addr_in_dccm_d),
+				.in_region(start_addr_in_dccm_region_d)
+			);
+			rvrangecheck #(
+				.CCM_SADR(pt[1325-:36]),
+				.CCM_SIZE(pt[1289-:14])
+			) end_addr_dccm_rangecheck(
+				.addr(end_addr_d[31:0]),
+				.in_range(end_addr_in_dccm_d),
+				.in_region(end_addr_in_dccm_region_d)
+			);
+		end
+		else begin : Gen_dccm_disable
+			assign start_addr_in_dccm_d = 1'b0;
+			assign start_addr_in_dccm_region_d = 1'b0;
+			assign end_addr_in_dccm_d = 1'b0;
+			assign end_addr_in_dccm_region_d = 1'b0;
+		end
+	endgenerate
+	generate
+		if (pt[927-:5] == 1) begin : check_iccm
+			assign addr_in_iccm = start_addr_d[31:28] == pt[895-:8];
+		end
+		else assign addr_in_iccm = 1'b0;
+	endgenerate
+	rvrangecheck #(
+		.CCM_SADR(pt[130-:36]),
+		.CCM_SIZE(pt[69-:13])
+	) start_addr_pic_rangecheck(
+		.addr(start_addr_d[31:0]),
+		.in_range(start_addr_in_pic_d),
+		.in_region(start_addr_in_pic_region_d)
+	);
+	rvrangecheck #(
+		.CCM_SADR(pt[130-:36]),
+		.CCM_SIZE(pt[69-:13])
+	) end_addr_pic_rangecheck(
+		.addr(end_addr_d[31:0]),
+		.in_range(end_addr_in_pic_d),
+		.in_region(end_addr_in_pic_region_d)
+	);
+	assign start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d;
+	assign base_reg_dccm_or_pic = ((rs1_region_d[3:0] == pt[1333-:8]) & pt[1365-:5]) | (rs1_region_d[3:0] == pt[77-:8]);
+	assign addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d;
+	assign addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d;
+	assign addr_external_d = ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d);
+	assign csr_idx[4:0] = {start_addr_d[31:28], 1'b1};
+	assign is_sideeffects_d = ((dec_tlu_mrac_ff[csr_idx] & ~((start_addr_in_dccm_region_d | start_addr_in_pic_region_d) | addr_in_iccm)) & lsu_pkt_d[0]) & (lsu_pkt_d[6] | lsu_pkt_d[7]);
+	assign is_aligned_d = ((lsu_pkt_d[9] & (start_addr_d[1:0] == 2'b00)) | (lsu_pkt_d[10] & (start_addr_d[0] == 1'b0))) | lsu_pkt_d[11];
+	assign non_dccm_access_ok = ~(|{pt[1733-:5], pt[1728-:5], pt[1723-:5], pt[1718-:5], pt[1713-:5], pt[1708-:5], pt[1703-:5], pt[1698-:5]}) | (((((((((pt[1733-:5] & ((start_addr_d[31:0] | pt[1693-:36]) == (pt[2021-:36] | pt[1693-:36]))) | (pt[1728-:5] & ((start_addr_d[31:0] | pt[1657-:36]) == (pt[1985-:36] | pt[1657-:36])))) | (pt[1723-:5] & ((start_addr_d[31:0] | pt[1621-:36]) == (pt[1949-:36] | pt[1621-:36])))) | (pt[1718-:5] & ((start_addr_d[31:0] | pt[1585-:36]) == (pt[1913-:36] | pt[1585-:36])))) | (pt[1713-:5] & ((start_addr_d[31:0] | pt[1549-:36]) == (pt[1877-:36] | pt[1549-:36])))) | (pt[1708-:5] & ((start_addr_d[31:0] | pt[1513-:36]) == (pt[1841-:36] | pt[1513-:36])))) | (pt[1703-:5] & ((start_addr_d[31:0] | pt[1477-:36]) == (pt[1805-:36] | pt[1477-:36])))) | (pt[1698-:5] & ((start_addr_d[31:0] | pt[1441-:36]) == (pt[1769-:36] | pt[1441-:36])))) & ((((((((pt[1733-:5] & ((end_addr_d[31:0] | pt[1693-:36]) == (pt[2021-:36] | pt[1693-:36]))) | (pt[1728-:5] & ((end_addr_d[31:0] | pt[1657-:36]) == (pt[1985-:36] | pt[1657-:36])))) | (pt[1723-:5] & ((end_addr_d[31:0] | pt[1621-:36]) == (pt[1949-:36] | pt[1621-:36])))) | (pt[1718-:5] & ((end_addr_d[31:0] | pt[1585-:36]) == (pt[1913-:36] | pt[1585-:36])))) | (pt[1713-:5] & ((end_addr_d[31:0] | pt[1549-:36]) == (pt[1877-:36] | pt[1549-:36])))) | (pt[1708-:5] & ((end_addr_d[31:0] | pt[1513-:36]) == (pt[1841-:36] | pt[1513-:36])))) | (pt[1703-:5] & ((end_addr_d[31:0] | pt[1477-:36]) == (pt[1805-:36] | pt[1477-:36])))) | (pt[1698-:5] & ((end_addr_d[31:0] | pt[1441-:36]) == (pt[1769-:36] | pt[1441-:36])))));
+	assign regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic;
+	assign picm_access_fault_d = addr_in_pic_d & ((start_addr_d[1:0] != 2'b00) | ~lsu_pkt_d[9]);
+	generate
+		if (pt[1365-:5] & (pt[1333-:8] == pt[77-:8])) begin
+			assign unmapped_access_fault_d = (((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) | (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))) | (start_addr_in_dccm_d & end_addr_in_pic_d)) | (start_addr_in_pic_d & end_addr_in_dccm_d);
+			assign mpu_access_fault_d = ~start_addr_in_dccm_region_d & ~non_dccm_access_ok;
+		end
+		else begin
+			assign unmapped_access_fault_d = (((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) | (start_addr_in_pic_region_d & ~start_addr_in_pic_d)) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d);
+			assign mpu_access_fault_d = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d) & ~non_dccm_access_ok;
+		end
+	endgenerate
+	assign access_fault_d = ((((unmapped_access_fault_d | mpu_access_fault_d) | picm_access_fault_d) | regpred_access_fault_d) & lsu_pkt_d[0]) & ~lsu_pkt_d[4];
+	assign access_fault_mscause_d[3:0] = (unmapped_access_fault_d ? 4'h2 : (mpu_access_fault_d ? 4'h3 : (regpred_access_fault_d ? 4'h5 : (picm_access_fault_d ? 4'h6 : 4'h0))));
+	assign regcross_misaligned_fault_d = start_addr_d[31:28] != end_addr_d[31:28];
+	assign sideeffect_misaligned_fault_d = is_sideeffects_d & ~is_aligned_d;
+	assign misaligned_fault_d = ((regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & addr_external_d)) & lsu_pkt_d[0]) & ~lsu_pkt_d[4];
+	assign misaligned_fault_mscause_d[3:0] = (regcross_misaligned_fault_d ? 4'h2 : (sideeffect_misaligned_fault_d ? 4'h1 : 4'h0));
+	assign exc_mscause_d[3:0] = (misaligned_fault_d ? misaligned_fault_mscause_d[3:0] : access_fault_mscause_d[3:0]);
+	assign fir_dccm_access_error_d = (((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d[0]) & lsu_pkt_d[13];
+	assign fir_nondccm_access_error_d = (~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d[0]) & lsu_pkt_d[13];
+	rvdff #(.WIDTH(1)) is_sideeffects_mff(
+		.din(is_sideeffects_d),
+		.dout(is_sideeffects_m),
+		.clk(lsu_c2_m_clk),
+		.rst_l(rst_l)
+	);
+endmodule
+module eb1_lsu_bus_buffer (
+	clk,
+	clk_override,
+	rst_l,
+	scan_mode,
+	dec_tlu_external_ldfwd_disable,
+	dec_tlu_wb_coalescing_disable,
+	dec_tlu_sideeffect_posted_disable,
+	dec_tlu_force_halt,
+	lsu_bus_obuf_c1_clken,
+	lsu_busm_clken,
+	lsu_c2_r_clk,
+	lsu_bus_ibuf_c1_clk,
+	lsu_bus_obuf_c1_clk,
+	lsu_bus_buf_c1_clk,
+	lsu_free_c2_clk,
+	lsu_busm_clk,
+	dec_lsu_valid_raw_d,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	lsu_addr_m,
+	end_addr_m,
+	lsu_addr_r,
+	end_addr_r,
+	store_data_r,
+	no_word_merge_r,
+	no_dword_merge_r,
+	lsu_busreq_m,
+	lsu_busreq_r,
+	ld_full_hit_m,
+	flush_m_up,
+	flush_r,
+	lsu_commit_r,
+	is_sideeffects_r,
+	ldst_dual_d,
+	ldst_dual_m,
+	ldst_dual_r,
+	ldst_byteen_ext_m,
+	lsu_bus_buffer_pend_any,
+	lsu_bus_buffer_full_any,
+	lsu_bus_buffer_empty_any,
+	ld_byte_hit_buf_lo,
+	ld_byte_hit_buf_hi,
+	ld_fwddata_buf_lo,
+	ld_fwddata_buf_hi,
+	lsu_imprecise_error_load_any,
+	lsu_imprecise_error_store_any,
+	lsu_imprecise_error_addr_any,
+	lsu_nonblock_load_valid_m,
+	lsu_nonblock_load_tag_m,
+	lsu_nonblock_load_inv_r,
+	lsu_nonblock_load_inv_tag_r,
+	lsu_nonblock_load_data_valid,
+	lsu_nonblock_load_data_error,
+	lsu_nonblock_load_data_tag,
+	lsu_nonblock_load_data,
+	lsu_pmu_bus_trxn,
+	lsu_pmu_bus_misaligned,
+	lsu_pmu_bus_error,
+	lsu_pmu_bus_busy,
+	lsu_axi_awvalid,
+	lsu_axi_awready,
+	lsu_axi_awid,
+	lsu_axi_awaddr,
+	lsu_axi_awregion,
+	lsu_axi_awlen,
+	lsu_axi_awsize,
+	lsu_axi_awburst,
+	lsu_axi_awlock,
+	lsu_axi_awcache,
+	lsu_axi_awprot,
+	lsu_axi_awqos,
+	lsu_axi_wvalid,
+	lsu_axi_wready,
+	lsu_axi_wdata,
+	lsu_axi_wstrb,
+	lsu_axi_wlast,
+	lsu_axi_bvalid,
+	lsu_axi_bready,
+	lsu_axi_bresp,
+	lsu_axi_bid,
+	lsu_axi_arvalid,
+	lsu_axi_arready,
+	lsu_axi_arid,
+	lsu_axi_araddr,
+	lsu_axi_arregion,
+	lsu_axi_arlen,
+	lsu_axi_arsize,
+	lsu_axi_arburst,
+	lsu_axi_arlock,
+	lsu_axi_arcache,
+	lsu_axi_arprot,
+	lsu_axi_arqos,
+	lsu_axi_rvalid,
+	lsu_axi_rready,
+	lsu_axi_rid,
+	lsu_axi_rdata,
+	lsu_axi_rresp,
+	lsu_bus_clk_en,
+	lsu_bus_clk_en_q
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire clk_override;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire dec_tlu_external_ldfwd_disable;
+	input wire dec_tlu_wb_coalescing_disable;
+	input wire dec_tlu_sideeffect_posted_disable;
+	input wire dec_tlu_force_halt;
+	input wire lsu_bus_obuf_c1_clken;
+	input wire lsu_busm_clken;
+	input wire lsu_c2_r_clk;
+	input wire lsu_bus_ibuf_c1_clk;
+	input wire lsu_bus_obuf_c1_clk;
+	input wire lsu_bus_buf_c1_clk;
+	input wire lsu_free_c2_clk;
+	input wire lsu_busm_clk;
+	input wire dec_lsu_valid_raw_d;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_r;
+	input wire [31:0] lsu_addr_m;
+	input wire [31:0] end_addr_m;
+	input wire [31:0] lsu_addr_r;
+	input wire [31:0] end_addr_r;
+	input wire [31:0] store_data_r;
+	input wire no_word_merge_r;
+	input wire no_dword_merge_r;
+	input wire lsu_busreq_m;
+	output wire lsu_busreq_r;
+	input wire ld_full_hit_m;
+	input wire flush_m_up;
+	input wire flush_r;
+	input wire lsu_commit_r;
+	input wire is_sideeffects_r;
+	input wire ldst_dual_d;
+	input wire ldst_dual_m;
+	input wire ldst_dual_r;
+	input wire [7:0] ldst_byteen_ext_m;
+	output wire lsu_bus_buffer_pend_any;
+	output wire lsu_bus_buffer_full_any;
+	output wire lsu_bus_buffer_empty_any;
+	output wire [3:0] ld_byte_hit_buf_lo;
+	output wire [3:0] ld_byte_hit_buf_hi;
+	output reg [31:0] ld_fwddata_buf_lo;
+	output reg [31:0] ld_fwddata_buf_hi;
+	output wire lsu_imprecise_error_load_any;
+	output reg lsu_imprecise_error_store_any;
+	output wire [31:0] lsu_imprecise_error_addr_any;
+	output wire lsu_nonblock_load_valid_m;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	output wire lsu_nonblock_load_inv_r;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	output wire lsu_nonblock_load_data_valid;
+	output reg lsu_nonblock_load_data_error;
+	output reg [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	output wire [31:0] lsu_nonblock_load_data;
+	output wire lsu_pmu_bus_trxn;
+	output wire lsu_pmu_bus_misaligned;
+	output wire lsu_pmu_bus_error;
+	output wire lsu_pmu_bus_busy;
+	output wire lsu_axi_awvalid;
+	input wire lsu_axi_awready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_awid;
+	output wire [31:0] lsu_axi_awaddr;
+	output wire [3:0] lsu_axi_awregion;
+	output wire [7:0] lsu_axi_awlen;
+	output wire [2:0] lsu_axi_awsize;
+	output wire [1:0] lsu_axi_awburst;
+	output wire lsu_axi_awlock;
+	output wire [3:0] lsu_axi_awcache;
+	output wire [2:0] lsu_axi_awprot;
+	output wire [3:0] lsu_axi_awqos;
+	output wire lsu_axi_wvalid;
+	input wire lsu_axi_wready;
+	output wire [63:0] lsu_axi_wdata;
+	output wire [7:0] lsu_axi_wstrb;
+	output wire lsu_axi_wlast;
+	input wire lsu_axi_bvalid;
+	output wire lsu_axi_bready;
+	input wire [1:0] lsu_axi_bresp;
+	input wire [pt[181-:8] - 1:0] lsu_axi_bid;
+	output wire lsu_axi_arvalid;
+	input wire lsu_axi_arready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_arid;
+	output wire [31:0] lsu_axi_araddr;
+	output wire [3:0] lsu_axi_arregion;
+	output wire [7:0] lsu_axi_arlen;
+	output wire [2:0] lsu_axi_arsize;
+	output wire [1:0] lsu_axi_arburst;
+	output wire lsu_axi_arlock;
+	output wire [3:0] lsu_axi_arcache;
+	output wire [2:0] lsu_axi_arprot;
+	output wire [3:0] lsu_axi_arqos;
+	input wire lsu_axi_rvalid;
+	output wire lsu_axi_rready;
+	input wire [pt[181-:8] - 1:0] lsu_axi_rid;
+	input wire [63:0] lsu_axi_rdata;
+	input wire [1:0] lsu_axi_rresp;
+	input wire lsu_bus_clk_en;
+	input wire lsu_bus_clk_en_q;
+	localparam DEPTH = pt[173-:9];
+	localparam DEPTH_LOG2 = pt[164-:7];
+	localparam TIMER = 8;
+	localparam TIMER_MAX = 7;
+	localparam TIMER_LOG2 = 3;
+	wire [3:0] ldst_byteen_hi_m;
+	wire [3:0] ldst_byteen_lo_m;
+	wire [DEPTH - 1:0] ld_addr_hitvec_lo;
+	wire [DEPTH - 1:0] ld_addr_hitvec_hi;
+	wire [(4 * DEPTH) - 1:0] ld_byte_hitvec_lo;
+	wire [(4 * DEPTH) - 1:0] ld_byte_hitvec_hi;
+	wire [(4 * DEPTH) - 1:0] ld_byte_hitvecfn_lo;
+	wire [(4 * DEPTH) - 1:0] ld_byte_hitvecfn_hi;
+	wire ld_addr_ibuf_hit_lo;
+	wire ld_addr_ibuf_hit_hi;
+	wire [3:0] ld_byte_ibuf_hit_lo;
+	wire [3:0] ld_byte_ibuf_hit_hi;
+	wire [3:0] ldst_byteen_r;
+	wire [3:0] ldst_byteen_hi_r;
+	wire [3:0] ldst_byteen_lo_r;
+	wire [31:0] store_data_hi_r;
+	wire [31:0] store_data_lo_r;
+	wire is_aligned_r;
+	wire ldst_samedw_r;
+	wire lsu_nonblock_load_valid_r;
+	reg [31:0] lsu_nonblock_load_data_hi;
+	reg [31:0] lsu_nonblock_load_data_lo;
+	wire [31:0] lsu_nonblock_data_unalgn;
+	wire [1:0] lsu_nonblock_addr_offset;
+	wire [1:0] lsu_nonblock_sz;
+	wire lsu_nonblock_unsign;
+	reg lsu_nonblock_load_data_ready;
+	wire [DEPTH - 1:0] CmdPtr0Dec;
+	wire [DEPTH - 1:0] CmdPtr1Dec;
+	wire [DEPTH - 1:0] RspPtrDec;
+	wire [DEPTH_LOG2 - 1:0] CmdPtr0;
+	wire [DEPTH_LOG2 - 1:0] CmdPtr1;
+	wire [DEPTH_LOG2 - 1:0] RspPtr;
+	reg [DEPTH_LOG2 - 1:0] WrPtr0_m;
+	wire [DEPTH_LOG2 - 1:0] WrPtr0_r;
+	reg [DEPTH_LOG2 - 1:0] WrPtr1_m;
+	wire [DEPTH_LOG2 - 1:0] WrPtr1_r;
+	reg found_wrptr0;
+	reg found_wrptr1;
+	wire found_cmdptr0;
+	wire found_cmdptr1;
+	reg [3:0] buf_numvld_any;
+	reg [3:0] buf_numvld_wrcmd_any;
+	reg [3:0] buf_numvld_cmd_any;
+	reg [3:0] buf_numvld_pend_any;
+	reg any_done_wait_state;
+	reg bus_sideeffect_pend;
+	wire bus_coalescing_disable;
+	reg bus_addr_match_pending;
+	wire bus_cmd_sent;
+	wire bus_cmd_ready;
+	wire bus_wcmd_sent;
+	wire bus_wdata_sent;
+	wire bus_rsp_read;
+	wire bus_rsp_write;
+	wire [pt[181-:8] - 1:0] bus_rsp_read_tag;
+	wire [pt[181-:8] - 1:0] bus_rsp_write_tag;
+	wire bus_rsp_read_error;
+	wire bus_rsp_write_error;
+	wire [63:0] bus_rsp_rdata;
+	wire [(DEPTH * 3) - 1:0] buf_state;
+	wire [(DEPTH * 2) - 1:0] buf_sz;
+	wire [(DEPTH * 32) - 1:0] buf_addr;
+	wire [(DEPTH * 4) - 1:0] buf_byteen;
+	wire [DEPTH - 1:0] buf_sideeffect;
+	wire [DEPTH - 1:0] buf_write;
+	wire [DEPTH - 1:0] buf_unsign;
+	wire [DEPTH - 1:0] buf_dual;
+	wire [DEPTH - 1:0] buf_samedw;
+	wire [DEPTH - 1:0] buf_nomerge;
+	wire [DEPTH - 1:0] buf_dualhi;
+	wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_dualtag;
+	wire [DEPTH - 1:0] buf_ldfwd;
+	wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_ldfwdtag;
+	wire [DEPTH - 1:0] buf_error;
+	wire [(DEPTH * 32) - 1:0] buf_data;
+	wire [(DEPTH * DEPTH) - 1:0] buf_age;
+	wire [(DEPTH * DEPTH) - 1:0] buf_age_younger;
+	wire [(DEPTH * DEPTH) - 1:0] buf_rspage;
+	wire [(DEPTH * DEPTH) - 1:0] buf_rsp_pickage;
+	reg [(DEPTH * 3) - 1:0] buf_nxtstate;
+	reg [DEPTH - 1:0] buf_rst;
+	reg [DEPTH - 1:0] buf_state_en;
+	reg [DEPTH - 1:0] buf_cmd_state_bus_en;
+	reg [DEPTH - 1:0] buf_resp_state_bus_en;
+	reg [DEPTH - 1:0] buf_state_bus_en;
+	wire [DEPTH - 1:0] buf_dual_in;
+	wire [DEPTH - 1:0] buf_samedw_in;
+	wire [DEPTH - 1:0] buf_nomerge_in;
+	wire [DEPTH - 1:0] buf_sideeffect_in;
+	wire [DEPTH - 1:0] buf_unsign_in;
+	wire [(DEPTH * 2) - 1:0] buf_sz_in;
+	wire [DEPTH - 1:0] buf_write_in;
+	reg [DEPTH - 1:0] buf_wr_en;
+	wire [DEPTH - 1:0] buf_dualhi_in;
+	wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_dualtag_in;
+	reg [DEPTH - 1:0] buf_ldfwd_en;
+	reg [DEPTH - 1:0] buf_ldfwd_in;
+	reg [(DEPTH * DEPTH_LOG2) - 1:0] buf_ldfwdtag_in;
+	wire [(DEPTH * 4) - 1:0] buf_byteen_in;
+	wire [(DEPTH * 32) - 1:0] buf_addr_in;
+	reg [(DEPTH * 32) - 1:0] buf_data_in;
+	reg [DEPTH - 1:0] buf_error_en;
+	reg [DEPTH - 1:0] buf_data_en;
+	wire [(DEPTH * DEPTH) - 1:0] buf_age_in;
+	wire [(DEPTH * DEPTH) - 1:0] buf_ageQ;
+	wire [(DEPTH * DEPTH) - 1:0] buf_rspage_set;
+	wire [(DEPTH * DEPTH) - 1:0] buf_rspage_in;
+	wire [(DEPTH * DEPTH) - 1:0] buf_rspageQ;
+	wire ibuf_valid;
+	wire ibuf_dual;
+	wire ibuf_samedw;
+	wire ibuf_nomerge;
+	wire [DEPTH_LOG2 - 1:0] ibuf_tag;
+	wire [DEPTH_LOG2 - 1:0] ibuf_dualtag;
+	wire ibuf_sideeffect;
+	wire ibuf_unsign;
+	wire ibuf_write;
+	wire [1:0] ibuf_sz;
+	wire [3:0] ibuf_byteen;
+	wire [31:0] ibuf_addr;
+	wire [31:0] ibuf_data;
+	wire [2:0] ibuf_timer;
+	wire ibuf_byp;
+	wire ibuf_wr_en;
+	wire ibuf_rst;
+	wire ibuf_force_drain;
+	wire ibuf_drain_vld;
+	wire [DEPTH - 1:0] ibuf_drainvec_vld;
+	wire [DEPTH_LOG2 - 1:0] ibuf_tag_in;
+	wire [DEPTH_LOG2 - 1:0] ibuf_dualtag_in;
+	wire [1:0] ibuf_sz_in;
+	wire [31:0] ibuf_addr_in;
+	wire [3:0] ibuf_byteen_in;
+	wire [31:0] ibuf_data_in;
+	wire [2:0] ibuf_timer_in;
+	wire [3:0] ibuf_byteen_out;
+	wire [31:0] ibuf_data_out;
+	wire ibuf_merge_en;
+	wire ibuf_merge_in;
+	wire obuf_valid;
+	wire obuf_write;
+	wire obuf_nosend;
+	wire obuf_rdrsp_pend;
+	wire obuf_sideeffect;
+	wire [31:0] obuf_addr;
+	wire [63:0] obuf_data;
+	wire [1:0] obuf_sz;
+	wire [7:0] obuf_byteen;
+	wire obuf_merge;
+	wire obuf_cmd_done;
+	wire obuf_data_done;
+	wire [pt[181-:8] - 1:0] obuf_tag0;
+	wire [pt[181-:8] - 1:0] obuf_tag1;
+	wire [pt[181-:8] - 1:0] obuf_rdrsp_tag;
+	wire ibuf_buf_byp;
+	wire obuf_force_wr_en;
+	wire obuf_wr_wait;
+	wire obuf_wr_en;
+	wire obuf_wr_enQ;
+	wire obuf_rst;
+	wire obuf_write_in;
+	wire obuf_nosend_in;
+	wire obuf_rdrsp_pend_en;
+	wire obuf_rdrsp_pend_in;
+	wire obuf_sideeffect_in;
+	wire obuf_aligned_in;
+	wire [31:0] obuf_addr_in;
+	wire [63:0] obuf_data_in;
+	wire [1:0] obuf_sz_in;
+	wire [7:0] obuf_byteen_in;
+	wire obuf_merge_in;
+	wire obuf_cmd_done_in;
+	wire obuf_data_done_in;
+	wire [pt[181-:8] - 1:0] obuf_tag0_in;
+	wire [pt[181-:8] - 1:0] obuf_tag1_in;
+	wire [pt[181-:8] - 1:0] obuf_rdrsp_tag_in;
+	wire obuf_merge_en;
+	wire [2:0] obuf_wr_timer;
+	wire [2:0] obuf_wr_timer_in;
+	wire [7:0] obuf_byteen0_in;
+	wire [7:0] obuf_byteen1_in;
+	wire [63:0] obuf_data0_in;
+	wire [63:0] obuf_data1_in;
+	wire lsu_axi_awvalid_q;
+	wire lsu_axi_awready_q;
+	wire lsu_axi_wvalid_q;
+	wire lsu_axi_wready_q;
+	wire lsu_axi_arvalid_q;
+	wire lsu_axi_arready_q;
+	wire lsu_axi_bvalid_q;
+	wire lsu_axi_bready_q;
+	wire lsu_axi_rvalid_q;
+	wire lsu_axi_rready_q;
+	wire [pt[181-:8] - 1:0] lsu_axi_bid_q;
+	wire [pt[181-:8] - 1:0] lsu_axi_rid_q;
+	wire [1:0] lsu_axi_bresp_q;
+	wire [1:0] lsu_axi_rresp_q;
+	reg [pt[181-:8] - 1:0] lsu_imprecise_error_store_tag;
+	wire [63:0] lsu_axi_rdata_q;
+	function automatic [2:0] f_Enc8to3;
+		input reg [7:0] Dec_value;
+		reg [2:0] Enc_value;
+		begin
+			Enc_value[0] = ((Dec_value[1] | Dec_value[3]) | Dec_value[5]) | Dec_value[7];
+			Enc_value[1] = ((Dec_value[2] | Dec_value[3]) | Dec_value[6]) | Dec_value[7];
+			Enc_value[2] = ((Dec_value[4] | Dec_value[5]) | Dec_value[6]) | Dec_value[7];
+			f_Enc8to3 = Enc_value[2:0];
+		end
+	endfunction
+	assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
+	assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
+	localparam [2:0] IDLE = 3'b000;
+	generate
+		genvar i;
+		for (i = 0; i < DEPTH; i = i + 1) begin
+			assign ld_addr_hitvec_lo[i] = (((lsu_addr_m[31:2] == buf_addr[(i * 32) + 31-:30]) & buf_write[i]) & (buf_state[i * 3+:3] != IDLE)) & lsu_busreq_m;
+			assign ld_addr_hitvec_hi[i] = (((end_addr_m[31:2] == buf_addr[(i * 32) + 31-:30]) & buf_write[i]) & (buf_state[i * 3+:3] != IDLE)) & lsu_busreq_m;
+		end
+	endgenerate
+	generate
+		genvar j;
+		for (j = 0; j < 4; j = j + 1) begin
+			assign ld_byte_hit_buf_lo[j] = |ld_byte_hitvecfn_lo[j * DEPTH+:DEPTH] | ld_byte_ibuf_hit_lo[j];
+			assign ld_byte_hit_buf_hi[j] = |ld_byte_hitvecfn_hi[j * DEPTH+:DEPTH] | ld_byte_ibuf_hit_hi[j];
+			for (i = 0; i < DEPTH; i = i + 1) begin
+				assign ld_byte_hitvec_lo[(j * DEPTH) + i] = (ld_addr_hitvec_lo[i] & buf_byteen[(i * 4) + j]) & ldst_byteen_lo_m[j];
+				assign ld_byte_hitvec_hi[(j * DEPTH) + i] = (ld_addr_hitvec_hi[i] & buf_byteen[(i * 4) + j]) & ldst_byteen_hi_m[j];
+				assign ld_byte_hitvecfn_lo[(j * DEPTH) + i] = (ld_byte_hitvec_lo[(j * DEPTH) + i] & ~(|(ld_byte_hitvec_lo[j * DEPTH+:DEPTH] & buf_age_younger[i * DEPTH+:DEPTH]))) & ~ld_byte_ibuf_hit_lo[j];
+				assign ld_byte_hitvecfn_hi[(j * DEPTH) + i] = (ld_byte_hitvec_hi[(j * DEPTH) + i] & ~(|(ld_byte_hitvec_hi[j * DEPTH+:DEPTH] & buf_age_younger[i * DEPTH+:DEPTH]))) & ~ld_byte_ibuf_hit_hi[j];
+			end
+		end
+	endgenerate
+	assign ld_addr_ibuf_hit_lo = (((lsu_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write) & ibuf_valid) & lsu_busreq_m;
+	assign ld_addr_ibuf_hit_hi = (((end_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write) & ibuf_valid) & lsu_busreq_m;
+	generate
+		for (i = 0; i < 4; i = i + 1) begin
+			assign ld_byte_ibuf_hit_lo[i] = (ld_addr_ibuf_hit_lo & ibuf_byteen[i]) & ldst_byteen_lo_m[i];
+			assign ld_byte_ibuf_hit_hi[i] = (ld_addr_ibuf_hit_hi & ibuf_byteen[i]) & ldst_byteen_hi_m[i];
+		end
+	endgenerate
+	always @(*) begin
+		ld_fwddata_buf_lo[31:0] = {{8 {ld_byte_ibuf_hit_lo[3]}}, {8 {ld_byte_ibuf_hit_lo[2]}}, {8 {ld_byte_ibuf_hit_lo[1]}}, {8 {ld_byte_ibuf_hit_lo[0]}}} & ibuf_data[31:0];
+		ld_fwddata_buf_hi[31:0] = {{8 {ld_byte_ibuf_hit_hi[3]}}, {8 {ld_byte_ibuf_hit_hi[2]}}, {8 {ld_byte_ibuf_hit_hi[1]}}, {8 {ld_byte_ibuf_hit_hi[0]}}} & ibuf_data[31:0];
+		begin : sv2v_autoblock_50
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					ld_fwddata_buf_lo[7:0] = ld_fwddata_buf_lo[7:0] | ({8 {ld_byte_hitvecfn_lo[i]}} & buf_data[(i * 32) + 7-:8]);
+					ld_fwddata_buf_lo[15:8] = ld_fwddata_buf_lo[15:8] | ({8 {ld_byte_hitvecfn_lo[DEPTH + i]}} & buf_data[(i * 32) + 15-:8]);
+					ld_fwddata_buf_lo[23:16] = ld_fwddata_buf_lo[23:16] | ({8 {ld_byte_hitvecfn_lo[(2 * DEPTH) + i]}} & buf_data[(i * 32) + 23-:8]);
+					ld_fwddata_buf_lo[31:24] = ld_fwddata_buf_lo[31:24] | ({8 {ld_byte_hitvecfn_lo[(3 * DEPTH) + i]}} & buf_data[(i * 32) + 31-:8]);
+					ld_fwddata_buf_hi[7:0] = ld_fwddata_buf_hi[7:0] | ({8 {ld_byte_hitvecfn_hi[i]}} & buf_data[(i * 32) + 7-:8]);
+					ld_fwddata_buf_hi[15:8] = ld_fwddata_buf_hi[15:8] | ({8 {ld_byte_hitvecfn_hi[DEPTH + i]}} & buf_data[(i * 32) + 15-:8]);
+					ld_fwddata_buf_hi[23:16] = ld_fwddata_buf_hi[23:16] | ({8 {ld_byte_hitvecfn_hi[(2 * DEPTH) + i]}} & buf_data[(i * 32) + 23-:8]);
+					ld_fwddata_buf_hi[31:24] = ld_fwddata_buf_hi[31:24] | ({8 {ld_byte_hitvecfn_hi[(3 * DEPTH) + i]}} & buf_data[(i * 32) + 31-:8]);
+				end
+		end
+	end
+	assign bus_coalescing_disable = dec_tlu_wb_coalescing_disable | pt[2038];
+	assign ldst_byteen_r[3:0] = (({4 {lsu_pkt_r[11]}} & 4'b0001) | ({4 {lsu_pkt_r[10]}} & 4'b0011)) | ({4 {lsu_pkt_r[9]}} & 4'b1111);
+	assign {ldst_byteen_hi_r[3:0], ldst_byteen_lo_r[3:0]} = {4'b0000, ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
+	assign {store_data_hi_r[31:0], store_data_lo_r[31:0]} = {32'b00000000000000000000000000000000, store_data_r[31:0]} << (8 * lsu_addr_r[1:0]);
+	assign ldst_samedw_r = lsu_addr_r[3] == end_addr_r[3];
+	assign is_aligned_r = ((lsu_pkt_r[9] & (lsu_addr_r[1:0] == 2'b00)) | (lsu_pkt_r[10] & (lsu_addr_r[0] == 1'b0))) | lsu_pkt_r[11];
+	assign ibuf_byp = (lsu_busreq_r & (lsu_pkt_r[7] | no_word_merge_r)) & ~ibuf_valid;
+	assign ibuf_wr_en = (lsu_busreq_r & lsu_commit_r) & ~ibuf_byp;
+	assign ibuf_rst = (ibuf_drain_vld & ~ibuf_wr_en) | dec_tlu_force_halt;
+	assign ibuf_force_drain = ((lsu_busreq_m & ~lsu_busreq_r) & ibuf_valid) & (lsu_pkt_m[7] | (ibuf_addr[31:2] != lsu_addr_m[31:2]));
+	assign ibuf_drain_vld = ibuf_valid & (((((((ibuf_wr_en | (ibuf_timer == TIMER_MAX)) & ~(ibuf_merge_en & ibuf_merge_in)) | ibuf_byp) | ibuf_force_drain) | ibuf_sideeffect) | ~ibuf_write) | bus_coalescing_disable);
+	assign ibuf_tag_in[DEPTH_LOG2 - 1:0] = (ibuf_merge_en & ibuf_merge_in ? ibuf_tag[DEPTH_LOG2 - 1:0] : (ldst_dual_r ? WrPtr1_r : WrPtr0_r));
+	assign ibuf_dualtag_in[DEPTH_LOG2 - 1:0] = WrPtr0_r;
+	assign ibuf_sz_in[1:0] = {lsu_pkt_r[9], lsu_pkt_r[10]};
+	assign ibuf_addr_in[31:0] = (ldst_dual_r ? end_addr_r[31:0] : lsu_addr_r[31:0]);
+	assign ibuf_byteen_in[3:0] = (ibuf_merge_en & ibuf_merge_in ? ibuf_byteen[3:0] | ldst_byteen_lo_r[3:0] : (ldst_dual_r ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0]));
+	generate
+		for (i = 0; i < 4; i = i + 1) assign ibuf_data_in[(8 * i) + 7:8 * i] = (ibuf_merge_en & ibuf_merge_in ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8 * i) + 7:8 * i] : ibuf_data[(8 * i) + 7:8 * i]) : (ldst_dual_r ? store_data_hi_r[(8 * i) + 7:8 * i] : store_data_lo_r[(8 * i) + 7:8 * i]));
+	endgenerate
+	assign ibuf_timer_in = (ibuf_wr_en ? {3 {1'sb0}} : (ibuf_timer < TIMER_MAX ? ibuf_timer + 1'b1 : ibuf_timer));
+	assign ibuf_merge_en = ((((((lsu_busreq_r & lsu_commit_r) & lsu_pkt_r[6]) & ibuf_valid) & ibuf_write) & (lsu_addr_r[31:2] == ibuf_addr[31:2])) & ~is_sideeffects_r) & ~bus_coalescing_disable;
+	assign ibuf_merge_in = ~ldst_dual_r;
+	generate
+		for (i = 0; i < 4; i = i + 1) begin
+			assign ibuf_byteen_out[i] = (ibuf_merge_en & ~ibuf_merge_in ? ibuf_byteen[i] | ldst_byteen_lo_r[i] : ibuf_byteen[i]);
+			assign ibuf_data_out[(8 * i) + 7:8 * i] = (ibuf_merge_en & ~ibuf_merge_in ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8 * i) + 7:8 * i] : ibuf_data[(8 * i) + 7:8 * i]) : ibuf_data[(8 * i) + 7:8 * i]);
+		end
+	endgenerate
+	rvdffsc #(.WIDTH(1)) ibuf_valid_ff(
+		.din(1'b1),
+		.dout(ibuf_valid),
+		.en(ibuf_wr_en),
+		.clear(ibuf_rst),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_tagff(
+		.din(ibuf_tag_in),
+		.dout(ibuf_tag),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_dualtagff(
+		.din(ibuf_dualtag_in),
+		.dout(ibuf_dualtag),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_dualff(
+		.din(ldst_dual_r),
+		.dout(ibuf_dual),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_samedwff(
+		.din(ldst_samedw_r),
+		.dout(ibuf_samedw),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_nomergeff(
+		.din(no_dword_merge_r),
+		.dout(ibuf_nomerge),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_sideeffectff(
+		.din(is_sideeffects_r),
+		.dout(ibuf_sideeffect),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_unsignff(
+		.din(lsu_pkt_r[5]),
+		.dout(ibuf_unsign),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) ibuf_writeff(
+		.din(lsu_pkt_r[6]),
+		.dout(ibuf_write),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(2)) ibuf_szff(
+		.din(ibuf_sz_in[1:0]),
+		.dout(ibuf_sz),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) ibuf_addrff(
+		.din(ibuf_addr_in[31:0]),
+		.dout(ibuf_addr),
+		.en(ibuf_wr_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffs #(.WIDTH(4)) ibuf_byteenff(
+		.din(ibuf_byteen_in[3:0]),
+		.dout(ibuf_byteen),
+		.en(ibuf_wr_en),
+		.clk(lsu_bus_ibuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) ibuf_dataff(
+		.din(ibuf_data_in[31:0]),
+		.dout(ibuf_data),
+		.en(ibuf_wr_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdff #(.WIDTH(TIMER_LOG2)) ibuf_timerff(
+		.din(ibuf_timer_in),
+		.dout(ibuf_timer),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	assign obuf_wr_wait = ((((((buf_numvld_wrcmd_any[3:0] == 4'b0001) & (buf_numvld_cmd_any[3:0] == 4'b0001)) & (obuf_wr_timer != TIMER_MAX)) & ~bus_coalescing_disable) & ~buf_nomerge[CmdPtr0]) & ~buf_sideeffect[CmdPtr0]) & ~obuf_force_wr_en;
+	assign obuf_wr_timer_in = (obuf_wr_en ? 3'b000 : ((buf_numvld_cmd_any > 4'b0000) & (obuf_wr_timer < TIMER_MAX) ? obuf_wr_timer + 1'b1 : obuf_wr_timer));
+	assign obuf_force_wr_en = (((lsu_busreq_m & ~lsu_busreq_r) & ~ibuf_valid) & (buf_numvld_cmd_any[3:0] == 4'b0001)) & (lsu_addr_m[31:2] != buf_addr[(CmdPtr0 * 32) + 31-:30]);
+	assign ibuf_buf_byp = (ibuf_byp & (buf_numvld_pend_any[3:0] == 4'b0000)) & (~lsu_pkt_r[6] | no_dword_merge_r);
+	localparam [2:0] CMD = 3'b010;
+	assign obuf_wr_en = ((((((ibuf_buf_byp & lsu_commit_r) & ~(is_sideeffects_r & bus_sideeffect_pend)) | (((((buf_state[CmdPtr0 * 3+:3] == CMD) & found_cmdptr0) & ~buf_cmd_state_bus_en[CmdPtr0]) & ~(buf_sideeffect[CmdPtr0] & bus_sideeffect_pend)) & (((~((buf_dual[CmdPtr0] & buf_samedw[CmdPtr0]) & ~buf_write[CmdPtr0]) | found_cmdptr1) | buf_nomerge[CmdPtr0]) | obuf_force_wr_en))) & ((bus_cmd_ready | ~obuf_valid) | obuf_nosend)) & ~obuf_wr_wait) & ~bus_addr_match_pending) & lsu_bus_clk_en;
+	assign obuf_rst = (((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en) & lsu_bus_clk_en) | dec_tlu_force_halt;
+	assign obuf_write_in = (ibuf_buf_byp ? lsu_pkt_r[6] : buf_write[CmdPtr0]);
+	assign obuf_sideeffect_in = (ibuf_buf_byp ? is_sideeffects_r : buf_sideeffect[CmdPtr0]);
+	assign obuf_addr_in[31:0] = (ibuf_buf_byp ? lsu_addr_r[31:0] : buf_addr[CmdPtr0 * 32+:32]);
+	assign obuf_sz_in[1:0] = (ibuf_buf_byp ? {lsu_pkt_r[9], lsu_pkt_r[10]} : buf_sz[CmdPtr0 * 2+:2]);
+	assign obuf_merge_in = obuf_merge_en;
+	function automatic [pt[181-:8] - 1:0] sv2v_cast_72B45;
+		input reg [pt[181-:8] - 1:0] inp;
+		sv2v_cast_72B45 = inp;
+	endfunction
+	assign obuf_tag0_in[pt[181-:8] - 1:0] = (ibuf_buf_byp ? sv2v_cast_72B45(WrPtr0_r) : sv2v_cast_72B45(CmdPtr0));
+	assign obuf_tag1_in[pt[181-:8] - 1:0] = (ibuf_buf_byp ? sv2v_cast_72B45(WrPtr1_r) : sv2v_cast_72B45(CmdPtr1));
+	assign obuf_cmd_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent);
+	assign obuf_data_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent);
+	assign obuf_aligned_in = (ibuf_buf_byp ? is_aligned_r : ((obuf_sz_in[1:0] == 2'b00) | (obuf_sz_in[0] & ~obuf_addr_in[0])) | (obuf_sz_in[1] & ~(|obuf_addr_in[1:0])));
+	assign obuf_rdrsp_pend_in = (((~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend) & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))) | (bus_cmd_sent & ~obuf_write)) & ~dec_tlu_force_halt;
+	assign obuf_rdrsp_pend_en = lsu_bus_clk_en | dec_tlu_force_halt;
+	assign obuf_rdrsp_tag_in[pt[181-:8] - 1:0] = (bus_cmd_sent & ~obuf_write ? obuf_tag0[pt[181-:8] - 1:0] : obuf_rdrsp_tag[pt[181-:8] - 1:0]);
+	assign obuf_nosend_in = ((((((obuf_addr_in[31:3] == obuf_addr[31:3]) & obuf_aligned_in) & ~obuf_sideeffect) & ~obuf_write) & ~obuf_write_in) & ~dec_tlu_external_ldfwd_disable) & ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))));
+	assign obuf_byteen0_in[7:0] = (ibuf_buf_byp ? (lsu_addr_r[2] ? {ldst_byteen_lo_r[3:0], 4'b0000} : {4'b0000, ldst_byteen_lo_r[3:0]}) : (buf_addr[(CmdPtr0 * 32) + 2] ? {buf_byteen[CmdPtr0 * 4+:4], 4'b0000} : {4'b0000, buf_byteen[CmdPtr0 * 4+:4]}));
+	assign obuf_byteen1_in[7:0] = (ibuf_buf_byp ? (end_addr_r[2] ? {ldst_byteen_hi_r[3:0], 4'b0000} : {4'b0000, ldst_byteen_hi_r[3:0]}) : (buf_addr[(CmdPtr1 * 32) + 2] ? {buf_byteen[CmdPtr1 * 4+:4], 4'b0000} : {4'b0000, buf_byteen[CmdPtr1 * 4+:4]}));
+	assign obuf_data0_in[63:0] = (ibuf_buf_byp ? (lsu_addr_r[2] ? {store_data_lo_r[31:0], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, store_data_lo_r[31:0]}) : (buf_addr[(CmdPtr0 * 32) + 2] ? {buf_data[CmdPtr0 * 32+:32], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, buf_data[CmdPtr0 * 32+:32]}));
+	assign obuf_data1_in[63:0] = (ibuf_buf_byp ? (end_addr_r[2] ? {store_data_hi_r[31:0], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, store_data_hi_r[31:0]}) : (buf_addr[(CmdPtr1 * 32) + 2] ? {buf_data[CmdPtr1 * 32+:32], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, buf_data[CmdPtr1 * 32+:32]}));
+	generate
+		for (i = 0; i < 8; i = i + 1) begin
+			assign obuf_byteen_in[i] = obuf_byteen0_in[i] | (obuf_merge_en & obuf_byteen1_in[i]);
+			assign obuf_data_in[(8 * i) + 7:8 * i] = (obuf_merge_en & obuf_byteen1_in[i] ? obuf_data1_in[(8 * i) + 7:8 * i] : obuf_data0_in[(8 * i) + 7:8 * i]);
+		end
+	endgenerate
+	assign obuf_merge_en = ((((((((CmdPtr0 != CmdPtr1) & found_cmdptr0) & found_cmdptr1) & (buf_state[CmdPtr0 * 3+:3] == CMD)) & (buf_state[CmdPtr1 * 3+:3] == CMD)) & ~buf_cmd_state_bus_en[CmdPtr0]) & ~buf_sideeffect[CmdPtr0]) & (((~buf_write[CmdPtr0] & buf_dual[CmdPtr0]) & ~buf_dualhi[CmdPtr0]) & buf_samedw[CmdPtr0])) | ((ibuf_buf_byp & ldst_samedw_r) & ldst_dual_r);
+	rvdff_fpga #(.WIDTH(1)) obuf_wren_ff(
+		.din(obuf_wr_en),
+		.dout(obuf_wr_enQ),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffsc #(.WIDTH(1)) obuf_valid_ff(
+		.din(1'b1),
+		.dout(obuf_valid),
+		.en(obuf_wr_en),
+		.clear(obuf_rst),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) obuf_nosend_ff(
+		.din(obuf_nosend_in),
+		.dout(obuf_nosend),
+		.en(obuf_wr_en),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(1)) obuf_rdrsp_pend_ff(
+		.din(obuf_rdrsp_pend_in),
+		.dout(obuf_rdrsp_pend),
+		.en(obuf_rdrsp_pend_en),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) obuf_cmd_done_ff(
+		.din(obuf_cmd_done_in),
+		.dout(obuf_cmd_done),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) obuf_data_done_ff(
+		.din(obuf_data_done_in),
+		.dout(obuf_data_done),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(pt[181-:8])) obuf_rdrsp_tagff(
+		.din(obuf_rdrsp_tag_in),
+		.dout(obuf_rdrsp_tag),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(pt[181-:8])) obuf_tag0ff(
+		.din(obuf_tag0_in),
+		.dout(obuf_tag0),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(pt[181-:8])) obuf_tag1ff(
+		.din(obuf_tag1_in),
+		.dout(obuf_tag1),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) obuf_mergeff(
+		.din(obuf_merge_in),
+		.dout(obuf_merge),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) obuf_writeff(
+		.din(obuf_write_in),
+		.dout(obuf_write),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(1)) obuf_sideeffectff(
+		.din(obuf_sideeffect_in),
+		.dout(obuf_sideeffect),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(2)) obuf_szff(
+		.din(obuf_sz_in[1:0]),
+		.dout(obuf_sz),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffs_fpga #(.WIDTH(8)) obuf_byteenff(
+		.din(obuf_byteen_in[7:0]),
+		.dout(obuf_byteen),
+		.en(obuf_wr_en),
+		.clk(lsu_bus_obuf_c1_clk),
+		.clken(lsu_bus_obuf_c1_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) obuf_addrff(
+		.din(obuf_addr_in[31:0]),
+		.dout(obuf_addr),
+		.en(obuf_wr_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffe #(.WIDTH(64)) obuf_dataff(
+		.din(obuf_data_in[63:0]),
+		.dout(obuf_data),
+		.en(obuf_wr_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdff_fpga #(.WIDTH(TIMER_LOG2)) obuf_timerff(
+		.din(obuf_wr_timer_in),
+		.dout(obuf_wr_timer),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	function automatic signed [DEPTH_LOG2 - 1:0] sv2v_cast_63A9F_signed;
+		input reg signed [DEPTH_LOG2 - 1:0] inp;
+		sv2v_cast_63A9F_signed = inp;
+	endfunction
+	always @(*) begin
+		WrPtr0_m[DEPTH_LOG2 - 1:0] = {DEPTH_LOG2 {1'sb0}};
+		WrPtr1_m[DEPTH_LOG2 - 1:0] = {DEPTH_LOG2 {1'sb0}};
+		found_wrptr0 = 1'b0;
+		found_wrptr1 = 1'b0;
+		begin : sv2v_autoblock_51
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				if (~found_wrptr0) begin
+					WrPtr0_m[DEPTH_LOG2 - 1:0] = sv2v_cast_63A9F_signed(i);
+					found_wrptr0 = (buf_state[i * 3+:3] == IDLE) & ~((ibuf_valid & (ibuf_tag == i)) | (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+				end
+		end
+		begin : sv2v_autoblock_52
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				if (~found_wrptr1) begin
+					WrPtr1_m[DEPTH_LOG2 - 1:0] = sv2v_cast_63A9F_signed(i);
+					found_wrptr1 = (buf_state[i * 3+:3] == IDLE) & ~(((ibuf_valid & (ibuf_tag == i)) | (lsu_busreq_m & (WrPtr0_m == i))) | (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
+				end
+		end
+	end
+	localparam [2:0] DONE_WAIT = 3'b101;
+	generate
+		for (i = 0; i < DEPTH; i = i + 1) begin
+			assign CmdPtr0Dec[i] = (~(|buf_age[i * DEPTH+:DEPTH]) & (buf_state[i * 3+:3] == CMD)) & ~buf_cmd_state_bus_en[i];
+			assign CmdPtr1Dec[i] = ((~(|(buf_age[i * DEPTH+:DEPTH] & ~CmdPtr0Dec)) & ~CmdPtr0Dec[i]) & (buf_state[i * 3+:3] == CMD)) & ~buf_cmd_state_bus_en[i];
+			assign RspPtrDec[i] = ~(|buf_rsp_pickage[i * DEPTH+:DEPTH]) & (buf_state[i * 3+:3] == DONE_WAIT);
+		end
+	endgenerate
+	assign found_cmdptr0 = |CmdPtr0Dec;
+	assign found_cmdptr1 = |CmdPtr1Dec;
+	function automatic [7:0] sv2v_cast_8;
+		input reg [7:0] inp;
+		sv2v_cast_8 = inp;
+	endfunction
+	assign CmdPtr0 = f_Enc8to3(sv2v_cast_8(CmdPtr0Dec[DEPTH - 1:0]));
+	assign CmdPtr1 = f_Enc8to3(sv2v_cast_8(CmdPtr1Dec[DEPTH - 1:0]));
+	assign RspPtr = f_Enc8to3(sv2v_cast_8(RspPtrDec[DEPTH - 1:0]));
+	localparam [2:0] WAIT = 3'b001;
+	generate
+		for (i = 0; i < DEPTH; i = i + 1) begin : GenAgeVec
+			for (j = 0; j < DEPTH; j = j + 1) begin
+				assign buf_age_in[(i * DEPTH) + j] = (((buf_state[i * 3+:3] == IDLE) & buf_state_en[i]) & ((((buf_state[j * 3+:3] == WAIT) | ((buf_state[j * 3+:3] == CMD) & ~buf_cmd_state_bus_en[j])) | ((((ibuf_drain_vld & lsu_busreq_r) & (ibuf_byp | ldst_dual_r)) & (i == WrPtr0_r)) & (j == ibuf_tag))) | ((((ibuf_byp & lsu_busreq_r) & ldst_dual_r) & (i == WrPtr1_r)) & (j == WrPtr0_r)))) | buf_age[(i * DEPTH) + j];
+				assign buf_age[(i * DEPTH) + j] = (buf_ageQ[(i * DEPTH) + j] & ~((buf_state[j * 3+:3] == CMD) & buf_cmd_state_bus_en[j])) & ~dec_tlu_force_halt;
+				assign buf_age_younger[(i * DEPTH) + j] = (i == j ? 1'b0 : ~buf_age[(i * DEPTH) + j] & (buf_state[j * 3+:3] != IDLE));
+			end
+		end
+	endgenerate
+	localparam [2:0] DONE = 3'b110;
+	generate
+		for (i = 0; i < DEPTH; i = i + 1) begin : GenRspAgeVec
+			for (j = 0; j < DEPTH; j = j + 1) begin
+				function automatic signed [DEPTH_LOG2 - 1:0] sv2v_cast_63A9F_signed;
+					input reg signed [DEPTH_LOG2 - 1:0] inp;
+					sv2v_cast_63A9F_signed = inp;
+				endfunction
+				assign buf_rspage_set[(i * DEPTH) + j] = ((buf_state[i * 3+:3] == IDLE) & buf_state_en[i]) & ((~((buf_state[j * 3+:3] == IDLE) | (buf_state[j * 3+:3] == DONE)) | ((((ibuf_drain_vld & lsu_busreq_r) & (ibuf_byp | ldst_dual_r)) & (sv2v_cast_63A9F_signed(i) == WrPtr0_r)) & (sv2v_cast_63A9F_signed(j) == ibuf_tag))) | ((((ibuf_byp & lsu_busreq_r) & ldst_dual_r) & (sv2v_cast_63A9F_signed(i) == WrPtr1_r)) & (sv2v_cast_63A9F_signed(j) == WrPtr0_r)));
+				assign buf_rspage_in[(i * DEPTH) + j] = buf_rspage_set[(i * DEPTH) + j] | buf_rspage[(i * DEPTH) + j];
+				assign buf_rspage[(i * DEPTH) + j] = (buf_rspageQ[(i * DEPTH) + j] & ~((buf_state[j * 3+:3] == DONE) | (buf_state[j * 3+:3] == IDLE))) & ~dec_tlu_force_halt;
+				assign buf_rsp_pickage[(i * DEPTH) + j] = buf_rspageQ[(i * DEPTH) + j] & (buf_state[j * 3+:3] == DONE_WAIT);
+			end
+		end
+	endgenerate
+	localparam [2:0] DONE_PARTIAL = 3'b100;
+	localparam [2:0] RESP = 3'b011;
+	generate
+		for (i = 0; i < DEPTH; i = i + 1) begin
+			assign ibuf_drainvec_vld[i] = ibuf_drain_vld & (i == ibuf_tag);
+			assign buf_byteen_in[i * 4+:4] = (ibuf_drainvec_vld[i] ? ibuf_byteen_out[3:0] : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0]));
+			assign buf_addr_in[i * 32+:32] = (ibuf_drainvec_vld[i] ? ibuf_addr[31:0] : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? end_addr_r[31:0] : lsu_addr_r[31:0]));
+			assign buf_dual_in[i] = (ibuf_drainvec_vld[i] ? ibuf_dual : ldst_dual_r);
+			assign buf_samedw_in[i] = (ibuf_drainvec_vld[i] ? ibuf_samedw : ldst_samedw_r);
+			assign buf_nomerge_in[i] = (ibuf_drainvec_vld[i] ? ibuf_nomerge | ibuf_force_drain : no_dword_merge_r);
+			assign buf_dualhi_in[i] = (ibuf_drainvec_vld[i] ? ibuf_dual : (ibuf_byp & ldst_dual_r) & (i == WrPtr1_r));
+			assign buf_dualtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = (ibuf_drainvec_vld[i] ? ibuf_dualtag : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? WrPtr0_r : WrPtr1_r));
+			assign buf_sideeffect_in[i] = (ibuf_drainvec_vld[i] ? ibuf_sideeffect : is_sideeffects_r);
+			assign buf_unsign_in[i] = (ibuf_drainvec_vld[i] ? ibuf_unsign : lsu_pkt_r[5]);
+			assign buf_sz_in[i * 2+:2] = (ibuf_drainvec_vld[i] ? ibuf_sz : {lsu_pkt_r[9], lsu_pkt_r[10]});
+			assign buf_write_in[i] = (ibuf_drainvec_vld[i] ? ibuf_write : lsu_pkt_r[6]);
+			function automatic [DEPTH_LOG2 - 1:0] sv2v_cast_63A9F;
+				input reg [DEPTH_LOG2 - 1:0] inp;
+				sv2v_cast_63A9F = inp;
+			endfunction
+			function automatic signed [pt[181-:8] - 1:0] sv2v_cast_72B45_signed;
+				input reg signed [pt[181-:8] - 1:0] inp;
+				sv2v_cast_72B45_signed = inp;
+			endfunction
+			function automatic [pt[181-:8] - 1:0] sv2v_cast_72B45;
+				input reg [pt[181-:8] - 1:0] inp;
+				sv2v_cast_72B45 = inp;
+			endfunction
+			function automatic signed [DEPTH_LOG2 - 1:0] sv2v_cast_63A9F_signed;
+				input reg signed [DEPTH_LOG2 - 1:0] inp;
+				sv2v_cast_63A9F_signed = inp;
+			endfunction
+			always @(*) begin
+				buf_nxtstate[i * 3+:3] = IDLE;
+				buf_state_en[i] = 1'b0;
+				buf_resp_state_bus_en[i] = 1'b0;
+				buf_state_bus_en[i] = 1'b0;
+				buf_wr_en[i] = 1'b0;
+				buf_data_in[i * 32+:32] = {32 {1'sb0}};
+				buf_data_en[i] = 1'b0;
+				buf_error_en[i] = 1'b0;
+				buf_rst[i] = dec_tlu_force_halt;
+				buf_ldfwd_en[i] = dec_tlu_force_halt;
+				buf_ldfwd_in[i] = 1'b0;
+				buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = {DEPTH_LOG2 {1'sb0}};
+				case (buf_state[i * 3+:3])
+					IDLE: begin
+						buf_nxtstate[i * 3+:3] = (lsu_bus_clk_en ? CMD : WAIT);
+						buf_state_en[i] = ((lsu_busreq_r & lsu_commit_r) & ((((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en) & (i == WrPtr0_r)) | ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r)))) | (ibuf_drain_vld & (i == ibuf_tag));
+						buf_wr_en[i] = buf_state_en[i];
+						buf_data_en[i] = buf_state_en[i];
+						buf_data_in[i * 32+:32] = (ibuf_drain_vld & (i == ibuf_tag) ? ibuf_data_out[31:0] : store_data_lo_r[31:0]);
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					WAIT: begin
+						buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? IDLE : CMD);
+						buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					CMD: begin
+						buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? IDLE : ((obuf_nosend & bus_rsp_read) & (bus_rsp_read_tag == obuf_rdrsp_tag) ? DONE_WAIT : RESP));
+						buf_cmd_state_bus_en[i] = (((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid) & obuf_wr_enQ;
+						buf_state_bus_en[i] = buf_cmd_state_bus_en[i];
+						buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+						buf_ldfwd_in[i] = 1'b1;
+						buf_ldfwd_en[i] = ((buf_state_en[i] & ~buf_write[i]) & obuf_nosend) & ~dec_tlu_force_halt;
+						buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = sv2v_cast_63A9F(obuf_rdrsp_tag[pt[181-:8] - 2:0]);
+						buf_data_en[i] = ((buf_state_bus_en[i] & lsu_bus_clk_en) & obuf_nosend) & bus_rsp_read;
+						buf_error_en[i] = ((buf_state_bus_en[i] & lsu_bus_clk_en) & obuf_nosend) & bus_rsp_read_error;
+						buf_data_in[i * 32+:32] = (buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[(i * 32) + 2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]));
+					end
+					RESP: begin
+						buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error) ? IDLE : (((buf_dual[i] & ~buf_samedw[i]) & ~buf_write[i]) & (buf_state[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * 3+:3] != DONE_PARTIAL) ? DONE_PARTIAL : ((buf_ldfwd[i] | any_done_wait_state) | (((((buf_dual[i] & ~buf_samedw[i]) & ~buf_write[i]) & buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]]) & (buf_state[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * 3+:3] == DONE_PARTIAL)) & any_done_wait_state) ? DONE_WAIT : DONE)));
+						buf_resp_state_bus_en[i] = (bus_rsp_write & (bus_rsp_write_tag == sv2v_cast_72B45_signed(i))) | (bus_rsp_read & (((bus_rsp_read_tag == sv2v_cast_72B45_signed(i)) | (buf_ldfwd[i] & (bus_rsp_read_tag == sv2v_cast_72B45(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2])))) | ((((buf_dual[i] & buf_dualhi[i]) & ~buf_write[i]) & buf_samedw[i]) & (bus_rsp_read_tag == sv2v_cast_72B45(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2])))));
+						buf_state_bus_en[i] = buf_resp_state_bus_en[i];
+						buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+						buf_data_en[i] = (buf_state_bus_en[i] & bus_rsp_read) & lsu_bus_clk_en;
+						buf_error_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) & (((bus_rsp_read_error & (bus_rsp_read_tag == sv2v_cast_72B45_signed(i))) | ((bus_rsp_read_error & buf_ldfwd[i]) & (bus_rsp_read_tag == sv2v_cast_72B45(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2])))) | (bus_rsp_write_error & (bus_rsp_write_tag == sv2v_cast_72B45_signed(i))));
+						buf_data_in[(i * 32) + 31-:32] = (buf_state_en[i] & ~buf_error_en[i] ? (buf_addr[(i * 32) + 2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0]);
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					DONE_PARTIAL: begin
+						buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? IDLE : ((buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]]) | any_done_wait_state ? DONE_WAIT : DONE));
+						buf_state_bus_en[i] = bus_rsp_read & ((bus_rsp_read_tag == sv2v_cast_72B45(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2])) | (buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]] & (bus_rsp_read_tag == sv2v_cast_72B45(buf_ldfwdtag[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * DEPTH_LOG2+:DEPTH_LOG2]))));
+						buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					DONE_WAIT: begin
+						buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? IDLE : DONE);
+						buf_state_en[i] = ((RspPtr == sv2v_cast_63A9F_signed(i)) | (buf_dual[i] & (buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] == RspPtr))) | dec_tlu_force_halt;
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					DONE: begin
+						buf_nxtstate[i * 3+:3] = IDLE;
+						buf_rst[i] = 1'b1;
+						buf_state_en[i] = 1'b1;
+						buf_ldfwd_in[i] = 1'b0;
+						buf_ldfwd_en[i] = buf_state_en[i];
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+					default: begin
+						buf_nxtstate[i * 3+:3] = IDLE;
+						buf_state_en[i] = 1'b0;
+						buf_resp_state_bus_en[i] = 1'b0;
+						buf_state_bus_en[i] = 1'b0;
+						buf_wr_en[i] = 1'b0;
+						buf_data_in[i * 32+:32] = {32 {1'sb0}};
+						buf_data_en[i] = 1'b0;
+						buf_error_en[i] = 1'b0;
+						buf_rst[i] = 1'b0;
+						buf_cmd_state_bus_en[i] = 1'b0;
+					end
+				endcase
+			end
+			rvdffs #(.WIDTH(3)) buf_state_ff(
+				.din(buf_nxtstate[i * 3+:3]),
+				.dout({buf_state[i * 3+:3]}),
+				.en(buf_state_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(DEPTH)) buf_ageff(
+				.din(buf_age_in[i * DEPTH+:DEPTH]),
+				.dout(buf_ageQ[i * DEPTH+:DEPTH]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(DEPTH)) buf_rspageff(
+				.din(buf_rspage_in[i * DEPTH+:DEPTH]),
+				.dout(buf_rspageQ[i * DEPTH+:DEPTH]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(DEPTH_LOG2)) buf_dualtagff(
+				.din(buf_dualtag_in[i * DEPTH_LOG2+:DEPTH_LOG2]),
+				.dout(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_dualff(
+				.din(buf_dual_in[i]),
+				.dout(buf_dual[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_samedwff(
+				.din(buf_samedw_in[i]),
+				.dout(buf_samedw[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_nomergeff(
+				.din(buf_nomerge_in[i]),
+				.dout(buf_nomerge[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_dualhiff(
+				.din(buf_dualhi_in[i]),
+				.dout(buf_dualhi[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_ldfwdff(
+				.din(buf_ldfwd_in[i]),
+				.dout(buf_ldfwd[i]),
+				.en(buf_ldfwd_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(DEPTH_LOG2)) buf_ldfwdtagff(
+				.din(buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2]),
+				.dout(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2]),
+				.en(buf_ldfwd_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_sideeffectff(
+				.din(buf_sideeffect_in[i]),
+				.dout(buf_sideeffect[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_unsignff(
+				.din(buf_unsign_in[i]),
+				.dout(buf_unsign[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(1)) buf_writeff(
+				.din(buf_write_in[i]),
+				.dout(buf_write[i]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffs #(.WIDTH(2)) buf_szff(
+				.din(buf_sz_in[i * 2+:2]),
+				.dout(buf_sz[i * 2+:2]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffe #(.WIDTH(32)) buf_addrff(
+				.din(buf_addr_in[(i * 32) + 31-:32]),
+				.dout(buf_addr[i * 32+:32]),
+				.en(buf_wr_en[i]),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+			rvdffs #(.WIDTH(4)) buf_byteenff(
+				.din(buf_byteen_in[(i * 4) + 3-:4]),
+				.dout(buf_byteen[i * 4+:4]),
+				.en(buf_wr_en[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+			rvdffe #(.WIDTH(32)) buf_dataff(
+				.din(buf_data_in[(i * 32) + 31-:32]),
+				.dout(buf_data[i * 32+:32]),
+				.en(buf_data_en[i]),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+			rvdffsc #(.WIDTH(1)) buf_errorff(
+				.din(1'b1),
+				.dout(buf_error[i]),
+				.en(buf_error_en[i]),
+				.clear(buf_rst[i]),
+				.clk(lsu_bus_buf_c1_clk),
+				.rst_l(rst_l)
+			);
+		end
+	endgenerate
+	always @(*) begin
+		buf_numvld_any[3:0] = (({1'b0, lsu_busreq_m} << ldst_dual_m) + ({1'b0, lsu_busreq_r} << ldst_dual_r)) + ibuf_valid;
+		buf_numvld_wrcmd_any[3:0] = 4'b0000;
+		buf_numvld_cmd_any[3:0] = 4'b0000;
+		buf_numvld_pend_any[3:0] = 4'b0000;
+		any_done_wait_state = 1'b0;
+		begin : sv2v_autoblock_53
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					buf_numvld_any[3:0] = buf_numvld_any[3:0] + {3'b000, buf_state[i * 3+:3] != IDLE};
+					buf_numvld_wrcmd_any[3:0] = buf_numvld_wrcmd_any[3:0] + {3'b000, (buf_write[i] & (buf_state[i * 3+:3] == CMD)) & ~buf_cmd_state_bus_en[i]};
+					buf_numvld_cmd_any[3:0] = buf_numvld_cmd_any[3:0] + {3'b000, (buf_state[i * 3+:3] == CMD) & ~buf_cmd_state_bus_en[i]};
+					buf_numvld_pend_any[3:0] = buf_numvld_pend_any[3:0] + {3'b000, (buf_state[i * 3+:3] == WAIT) | ((buf_state[i * 3+:3] == CMD) & ~buf_cmd_state_bus_en[i])};
+					any_done_wait_state = any_done_wait_state | (buf_state[i * 3+:3] == DONE_WAIT);
+				end
+		end
+	end
+	assign lsu_bus_buffer_pend_any = buf_numvld_pend_any != 0;
+	assign lsu_bus_buffer_full_any = (ldst_dual_d & dec_lsu_valid_raw_d ? buf_numvld_any[3:0] >= (DEPTH - 1) : buf_numvld_any[3:0] == DEPTH);
+	assign lsu_bus_buffer_empty_any = (~(|buf_state[3 * ((DEPTH - 1) - (DEPTH - 1))+:3 * DEPTH]) & ~ibuf_valid) & ~obuf_valid;
+	assign lsu_nonblock_load_valid_m = (((lsu_busreq_m & lsu_pkt_m[0]) & lsu_pkt_m[7]) & ~flush_m_up) & ~ld_full_hit_m;
+	assign lsu_nonblock_load_tag_m[DEPTH_LOG2 - 1:0] = WrPtr0_m[DEPTH_LOG2 - 1:0];
+	assign lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & ~lsu_commit_r;
+	assign lsu_nonblock_load_inv_tag_r[DEPTH_LOG2 - 1:0] = WrPtr0_r[DEPTH_LOG2 - 1:0];
+	always @(*) begin
+		lsu_nonblock_load_data_ready = 1'b0;
+		lsu_nonblock_load_data_error = 1'b0;
+		lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] = {DEPTH_LOG2 {1'sb0}};
+		lsu_nonblock_load_data_lo[31:0] = {32 {1'sb0}};
+		lsu_nonblock_load_data_hi[31:0] = {32 {1'sb0}};
+		begin : sv2v_autoblock_54
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					lsu_nonblock_load_data_ready = lsu_nonblock_load_data_ready | ((buf_state[i * 3+:3] == DONE) & ~buf_write[i]);
+					lsu_nonblock_load_data_error = lsu_nonblock_load_data_error | (((buf_state[i * 3+:3] == DONE) & buf_error[i]) & ~buf_write[i]);
+					lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] = lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] | (sv2v_cast_63A9F_signed(i) & {DEPTH_LOG2 {((buf_state[i * 3+:3] == DONE) & ~buf_write[i]) & (~buf_dual[i] | ~buf_dualhi[i])}});
+					lsu_nonblock_load_data_lo[31:0] = lsu_nonblock_load_data_lo[31:0] | (buf_data[(i * 32) + 31-:32] & {32 {((buf_state[i * 3+:3] == DONE) & ~buf_write[i]) & (~buf_dual[i] | ~buf_dualhi[i])}});
+					lsu_nonblock_load_data_hi[31:0] = lsu_nonblock_load_data_hi[31:0] | (buf_data[(i * 32) + 31-:32] & {32 {((buf_state[i * 3+:3] == DONE) & ~buf_write[i]) & (buf_dual[i] & buf_dualhi[i])}});
+				end
+		end
+	end
+	assign lsu_nonblock_addr_offset[1:0] = buf_addr[(lsu_nonblock_load_data_tag * 32) + 1-:2];
+	assign lsu_nonblock_sz[1:0] = buf_sz[(lsu_nonblock_load_data_tag * 2) + 1-:2];
+	assign lsu_nonblock_unsign = buf_unsign[lsu_nonblock_load_data_tag];
+	function automatic [31:0] sv2v_cast_32;
+		input reg [31:0] inp;
+		sv2v_cast_32 = inp;
+	endfunction
+	assign lsu_nonblock_data_unalgn[31:0] = sv2v_cast_32({lsu_nonblock_load_data_hi[31:0], lsu_nonblock_load_data_lo[31:0]} >> (8 * lsu_nonblock_addr_offset[1:0]));
+	assign lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & ~lsu_nonblock_load_data_error;
+	assign lsu_nonblock_load_data[31:0] = (((({32 {lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {24'b000000000000000000000000, lsu_nonblock_data_unalgn[7:0]}) | ({32 {lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {16'b0000000000000000, lsu_nonblock_data_unalgn[15:0]})) | ({32 {~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {{24 {lsu_nonblock_data_unalgn[7]}}, lsu_nonblock_data_unalgn[7:0]})) | ({32 {~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {{16 {lsu_nonblock_data_unalgn[15]}}, lsu_nonblock_data_unalgn[15:0]})) | ({32 {lsu_nonblock_sz[1:0] == 2'b10}} & lsu_nonblock_data_unalgn[31:0]);
+	always @(*) begin
+		bus_sideeffect_pend = (obuf_valid & obuf_sideeffect) & dec_tlu_sideeffect_posted_disable;
+		begin : sv2v_autoblock_55
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				bus_sideeffect_pend = bus_sideeffect_pend | (((buf_state[i * 3+:3] == RESP) & buf_sideeffect[i]) & dec_tlu_sideeffect_posted_disable);
+		end
+	end
+	function automatic signed [pt[181-:8] - 1:0] sv2v_cast_72B45_signed;
+		input reg signed [pt[181-:8] - 1:0] inp;
+		sv2v_cast_72B45_signed = inp;
+	endfunction
+	always @(*) begin
+		bus_addr_match_pending = 1'b0;
+		begin : sv2v_autoblock_56
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				bus_addr_match_pending = bus_addr_match_pending | (((obuf_valid & (obuf_addr[31:3] == buf_addr[(i * 32) + 31-:29])) & (buf_state[i * 3+:3] == RESP)) & ~((obuf_tag0 == sv2v_cast_72B45_signed(i)) | (obuf_merge & (obuf_tag1 == sv2v_cast_72B45_signed(i)))));
+		end
+	end
+	assign bus_cmd_ready = (obuf_write ? (obuf_cmd_done | obuf_data_done ? (obuf_cmd_done ? lsu_axi_wready : lsu_axi_awready) : lsu_axi_awready & lsu_axi_wready) : lsu_axi_arready);
+	assign bus_wcmd_sent = lsu_axi_awvalid & lsu_axi_awready;
+	assign bus_wdata_sent = lsu_axi_wvalid & lsu_axi_wready;
+	assign bus_cmd_sent = ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (lsu_axi_arvalid & lsu_axi_arready);
+	assign bus_rsp_read = lsu_axi_rvalid & lsu_axi_rready;
+	assign bus_rsp_write = lsu_axi_bvalid & lsu_axi_bready;
+	assign bus_rsp_read_tag[pt[181-:8] - 1:0] = lsu_axi_rid[pt[181-:8] - 1:0];
+	assign bus_rsp_write_tag[pt[181-:8] - 1:0] = lsu_axi_bid[pt[181-:8] - 1:0];
+	assign bus_rsp_write_error = bus_rsp_write & (lsu_axi_bresp[1:0] != 2'b00);
+	assign bus_rsp_read_error = bus_rsp_read & (lsu_axi_rresp[1:0] != 2'b00);
+	assign bus_rsp_rdata[63:0] = lsu_axi_rdata[63:0];
+	assign lsu_axi_awvalid = ((obuf_valid & obuf_write) & ~obuf_cmd_done) & ~bus_addr_match_pending;
+	assign lsu_axi_awid[pt[181-:8] - 1:0] = sv2v_cast_72B45(obuf_tag0);
+	assign lsu_axi_awaddr[31:0] = (obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3], 3'b000});
+	assign lsu_axi_awsize[2:0] = (obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011);
+	assign lsu_axi_awprot[2:0] = 3'b001;
+	assign lsu_axi_awcache[3:0] = (obuf_sideeffect ? 4'b0000 : 4'b1111);
+	assign lsu_axi_awregion[3:0] = obuf_addr[31:28];
+	assign lsu_axi_awlen[7:0] = {8 {1'sb0}};
+	assign lsu_axi_awburst[1:0] = 2'b01;
+	assign lsu_axi_awqos[3:0] = {4 {1'sb0}};
+	assign lsu_axi_awlock = 1'b0;
+	assign lsu_axi_wvalid = ((obuf_valid & obuf_write) & ~obuf_data_done) & ~bus_addr_match_pending;
+	assign lsu_axi_wstrb[7:0] = obuf_byteen[7:0] & {8 {obuf_write}};
+	assign lsu_axi_wdata[63:0] = obuf_data[63:0];
+	assign lsu_axi_wlast = 1'b1;
+	assign lsu_axi_arvalid = ((obuf_valid & ~obuf_write) & ~obuf_nosend) & ~bus_addr_match_pending;
+	assign lsu_axi_arid[pt[181-:8] - 1:0] = sv2v_cast_72B45(obuf_tag0);
+	assign lsu_axi_araddr[31:0] = (obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3], 3'b000});
+	assign lsu_axi_arsize[2:0] = (obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011);
+	assign lsu_axi_arprot[2:0] = 3'b001;
+	assign lsu_axi_arcache[3:0] = (obuf_sideeffect ? 4'b0000 : 4'b1111);
+	assign lsu_axi_arregion[3:0] = obuf_addr[31:28];
+	assign lsu_axi_arlen[7:0] = {8 {1'sb0}};
+	assign lsu_axi_arburst[1:0] = 2'b01;
+	assign lsu_axi_arqos[3:0] = {4 {1'sb0}};
+	assign lsu_axi_arlock = 1'b0;
+	assign lsu_axi_bready = 1;
+	assign lsu_axi_rready = 1;
+	always @(*) begin
+		lsu_imprecise_error_store_any = 1'b0;
+		lsu_imprecise_error_store_tag = {pt[181-:8] {1'sb0}};
+		begin : sv2v_autoblock_57
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					lsu_imprecise_error_store_any = lsu_imprecise_error_store_any | (((lsu_bus_clk_en_q & (buf_state[i * 3+:3] == DONE)) & buf_error[i]) & buf_write[i]);
+					lsu_imprecise_error_store_tag = lsu_imprecise_error_store_tag | (sv2v_cast_63A9F_signed(i) & {DEPTH_LOG2 {((buf_state[i * 3+:3] == DONE) & buf_error[i]) & buf_write[i]}});
+				end
+		end
+	end
+	assign lsu_imprecise_error_load_any = lsu_nonblock_load_data_error & ~lsu_imprecise_error_store_any;
+	assign lsu_imprecise_error_addr_any[31:0] = (lsu_imprecise_error_store_any ? buf_addr[lsu_imprecise_error_store_tag * 32+:32] : buf_addr[lsu_nonblock_load_data_tag * 32+:32]);
+	assign lsu_pmu_bus_trxn = ((lsu_axi_awvalid & lsu_axi_awready) | (lsu_axi_wvalid & lsu_axi_wready)) | (lsu_axi_arvalid & lsu_axi_arready);
+	assign lsu_pmu_bus_misaligned = (lsu_busreq_r & ldst_dual_r) & lsu_commit_r;
+	assign lsu_pmu_bus_error = lsu_imprecise_error_load_any | lsu_imprecise_error_store_any;
+	assign lsu_pmu_bus_busy = ((lsu_axi_awvalid & ~lsu_axi_awready) | (lsu_axi_wvalid & ~lsu_axi_wready)) | (lsu_axi_arvalid & ~lsu_axi_arready);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_awvalid_ff(
+		.din(lsu_axi_awvalid),
+		.dout(lsu_axi_awvalid_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_awready_ff(
+		.din(lsu_axi_awready),
+		.dout(lsu_axi_awready_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_wvalid_ff(
+		.din(lsu_axi_wvalid),
+		.dout(lsu_axi_wvalid_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_wready_ff(
+		.din(lsu_axi_wready),
+		.dout(lsu_axi_wready_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_arvalid_ff(
+		.din(lsu_axi_arvalid),
+		.dout(lsu_axi_arvalid_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_arready_ff(
+		.din(lsu_axi_arready),
+		.dout(lsu_axi_arready_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_bvalid_ff(
+		.din(lsu_axi_bvalid),
+		.dout(lsu_axi_bvalid_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_bready_ff(
+		.din(lsu_axi_bready),
+		.dout(lsu_axi_bready_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(2)) lsu_axi_bresp_ff(
+		.din(lsu_axi_bresp[1:0]),
+		.dout(lsu_axi_bresp_q[1:0]),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(pt[181-:8])) lsu_axi_bid_ff(
+		.din(lsu_axi_bid[pt[181-:8] - 1:0]),
+		.dout(lsu_axi_bid_q[pt[181-:8] - 1:0]),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(64)) lsu_axi_rdata_ff(
+		.din(lsu_axi_rdata[63:0]),
+		.dout(lsu_axi_rdata_q[63:0]),
+		.en((lsu_axi_rvalid | clk_override) & lsu_bus_clk_en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_rvalid_ff(
+		.din(lsu_axi_rvalid),
+		.dout(lsu_axi_rvalid_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(1)) lsu_axi_rready_ff(
+		.din(lsu_axi_rready),
+		.dout(lsu_axi_rready_q),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(2)) lsu_axi_rresp_ff(
+		.din(lsu_axi_rresp[1:0]),
+		.dout(lsu_axi_rresp_q[1:0]),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff_fpga #(.WIDTH(pt[181-:8])) lsu_axi_rid_ff(
+		.din(lsu_axi_rid[pt[181-:8] - 1:0]),
+		.dout(lsu_axi_rid_q[pt[181-:8] - 1:0]),
+		.clk(lsu_busm_clk),
+		.clken(lsu_busm_clken),
+		.rawclk(clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr0_rff(
+		.din(WrPtr0_m),
+		.dout(WrPtr0_r),
+		.clk(lsu_c2_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr1_rff(
+		.din(WrPtr1_m),
+		.dout(WrPtr1_r),
+		.clk(lsu_c2_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) lsu_busreq_rff(
+		.din((lsu_busreq_m & ~flush_r) & ~ld_full_hit_m),
+		.dout(lsu_busreq_r),
+		.clk(lsu_c2_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_rff(
+		.din(lsu_nonblock_load_valid_m),
+		.dout(lsu_nonblock_load_valid_r),
+		.clk(lsu_c2_r_clk),
+		.rst_l(rst_l)
+	);
+endmodule
+module eb1_lsu_bus_intf (
+	clk,
+	clk_override,
+	rst_l,
+	scan_mode,
+	dec_tlu_external_ldfwd_disable,
+	dec_tlu_wb_coalescing_disable,
+	dec_tlu_sideeffect_posted_disable,
+	lsu_bus_obuf_c1_clken,
+	lsu_busm_clken,
+	lsu_c1_r_clk,
+	lsu_c2_r_clk,
+	lsu_bus_ibuf_c1_clk,
+	lsu_bus_obuf_c1_clk,
+	lsu_bus_buf_c1_clk,
+	lsu_free_c2_clk,
+	active_clk,
+	lsu_busm_clk,
+	dec_lsu_valid_raw_d,
+	lsu_busreq_m,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	lsu_addr_m,
+	lsu_addr_r,
+	end_addr_m,
+	end_addr_r,
+	store_data_r,
+	dec_tlu_force_halt,
+	lsu_commit_r,
+	is_sideeffects_m,
+	flush_m_up,
+	flush_r,
+	ldst_dual_d,
+	ldst_dual_m,
+	ldst_dual_r,
+	lsu_busreq_r,
+	lsu_bus_buffer_pend_any,
+	lsu_bus_buffer_full_any,
+	lsu_bus_buffer_empty_any,
+	bus_read_data_m,
+	lsu_imprecise_error_load_any,
+	lsu_imprecise_error_store_any,
+	lsu_imprecise_error_addr_any,
+	lsu_nonblock_load_valid_m,
+	lsu_nonblock_load_tag_m,
+	lsu_nonblock_load_inv_r,
+	lsu_nonblock_load_inv_tag_r,
+	lsu_nonblock_load_data_valid,
+	lsu_nonblock_load_data_error,
+	lsu_nonblock_load_data_tag,
+	lsu_nonblock_load_data,
+	lsu_pmu_bus_trxn,
+	lsu_pmu_bus_misaligned,
+	lsu_pmu_bus_error,
+	lsu_pmu_bus_busy,
+	lsu_axi_awvalid,
+	lsu_axi_awready,
+	lsu_axi_awid,
+	lsu_axi_awaddr,
+	lsu_axi_awregion,
+	lsu_axi_awlen,
+	lsu_axi_awsize,
+	lsu_axi_awburst,
+	lsu_axi_awlock,
+	lsu_axi_awcache,
+	lsu_axi_awprot,
+	lsu_axi_awqos,
+	lsu_axi_wvalid,
+	lsu_axi_wready,
+	lsu_axi_wdata,
+	lsu_axi_wstrb,
+	lsu_axi_wlast,
+	lsu_axi_bvalid,
+	lsu_axi_bready,
+	lsu_axi_bresp,
+	lsu_axi_bid,
+	lsu_axi_arvalid,
+	lsu_axi_arready,
+	lsu_axi_arid,
+	lsu_axi_araddr,
+	lsu_axi_arregion,
+	lsu_axi_arlen,
+	lsu_axi_arsize,
+	lsu_axi_arburst,
+	lsu_axi_arlock,
+	lsu_axi_arcache,
+	lsu_axi_arprot,
+	lsu_axi_arqos,
+	lsu_axi_rvalid,
+	lsu_axi_rready,
+	lsu_axi_rid,
+	lsu_axi_rdata,
+	lsu_axi_rresp,
+	lsu_bus_clk_en
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire clk_override;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire dec_tlu_external_ldfwd_disable;
+	input wire dec_tlu_wb_coalescing_disable;
+	input wire dec_tlu_sideeffect_posted_disable;
+	input wire lsu_bus_obuf_c1_clken;
+	input wire lsu_busm_clken;
+	input wire lsu_c1_r_clk;
+	input wire lsu_c2_r_clk;
+	input wire lsu_bus_ibuf_c1_clk;
+	input wire lsu_bus_obuf_c1_clk;
+	input wire lsu_bus_buf_c1_clk;
+	input wire lsu_free_c2_clk;
+	input wire active_clk;
+	input wire lsu_busm_clk;
+	input wire dec_lsu_valid_raw_d;
+	input wire lsu_busreq_m;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_r;
+	input wire [31:0] lsu_addr_m;
+	input wire [31:0] lsu_addr_r;
+	input wire [31:0] end_addr_m;
+	input wire [31:0] end_addr_r;
+	input wire [31:0] store_data_r;
+	input wire dec_tlu_force_halt;
+	input wire lsu_commit_r;
+	input wire is_sideeffects_m;
+	input wire flush_m_up;
+	input wire flush_r;
+	input wire ldst_dual_d;
+	input wire ldst_dual_m;
+	input wire ldst_dual_r;
+	output wire lsu_busreq_r;
+	output wire lsu_bus_buffer_pend_any;
+	output wire lsu_bus_buffer_full_any;
+	output wire lsu_bus_buffer_empty_any;
+	output wire [31:0] bus_read_data_m;
+	output wire lsu_imprecise_error_load_any;
+	output wire lsu_imprecise_error_store_any;
+	output wire [31:0] lsu_imprecise_error_addr_any;
+	output wire lsu_nonblock_load_valid_m;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m;
+	output wire lsu_nonblock_load_inv_r;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r;
+	output wire lsu_nonblock_load_data_valid;
+	output wire lsu_nonblock_load_data_error;
+	output wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag;
+	output wire [31:0] lsu_nonblock_load_data;
+	output wire lsu_pmu_bus_trxn;
+	output wire lsu_pmu_bus_misaligned;
+	output wire lsu_pmu_bus_error;
+	output wire lsu_pmu_bus_busy;
+	output wire lsu_axi_awvalid;
+	input wire lsu_axi_awready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_awid;
+	output wire [31:0] lsu_axi_awaddr;
+	output wire [3:0] lsu_axi_awregion;
+	output wire [7:0] lsu_axi_awlen;
+	output wire [2:0] lsu_axi_awsize;
+	output wire [1:0] lsu_axi_awburst;
+	output wire lsu_axi_awlock;
+	output wire [3:0] lsu_axi_awcache;
+	output wire [2:0] lsu_axi_awprot;
+	output wire [3:0] lsu_axi_awqos;
+	output wire lsu_axi_wvalid;
+	input wire lsu_axi_wready;
+	output wire [63:0] lsu_axi_wdata;
+	output wire [7:0] lsu_axi_wstrb;
+	output wire lsu_axi_wlast;
+	input wire lsu_axi_bvalid;
+	output wire lsu_axi_bready;
+	input wire [1:0] lsu_axi_bresp;
+	input wire [pt[181-:8] - 1:0] lsu_axi_bid;
+	output wire lsu_axi_arvalid;
+	input wire lsu_axi_arready;
+	output wire [pt[181-:8] - 1:0] lsu_axi_arid;
+	output wire [31:0] lsu_axi_araddr;
+	output wire [3:0] lsu_axi_arregion;
+	output wire [7:0] lsu_axi_arlen;
+	output wire [2:0] lsu_axi_arsize;
+	output wire [1:0] lsu_axi_arburst;
+	output wire lsu_axi_arlock;
+	output wire [3:0] lsu_axi_arcache;
+	output wire [2:0] lsu_axi_arprot;
+	output wire [3:0] lsu_axi_arqos;
+	input wire lsu_axi_rvalid;
+	output wire lsu_axi_rready;
+	input wire [pt[181-:8] - 1:0] lsu_axi_rid;
+	input wire [63:0] lsu_axi_rdata;
+	input wire [1:0] lsu_axi_rresp;
+	input wire lsu_bus_clk_en;
+	wire lsu_bus_clk_en_q;
+	wire [3:0] ldst_byteen_m;
+	wire [3:0] ldst_byteen_r;
+	wire [7:0] ldst_byteen_ext_m;
+	wire [7:0] ldst_byteen_ext_r;
+	wire [3:0] ldst_byteen_hi_m;
+	wire [3:0] ldst_byteen_hi_r;
+	wire [3:0] ldst_byteen_lo_m;
+	wire [3:0] ldst_byteen_lo_r;
+	wire is_sideeffects_r;
+	wire [63:0] store_data_ext_r;
+	wire [31:0] store_data_hi_r;
+	wire [31:0] store_data_lo_r;
+	wire addr_match_dw_lo_r_m;
+	wire addr_match_word_lo_r_m;
+	wire no_word_merge_r;
+	wire no_dword_merge_r;
+	wire ld_addr_rhit_lo_lo;
+	wire ld_addr_rhit_hi_lo;
+	wire ld_addr_rhit_lo_hi;
+	wire ld_addr_rhit_hi_hi;
+	wire [3:0] ld_byte_rhit_lo_lo;
+	wire [3:0] ld_byte_rhit_hi_lo;
+	wire [3:0] ld_byte_rhit_lo_hi;
+	wire [3:0] ld_byte_rhit_hi_hi;
+	wire [3:0] ld_byte_hit_lo;
+	wire [3:0] ld_byte_rhit_lo;
+	wire [3:0] ld_byte_hit_hi;
+	wire [3:0] ld_byte_rhit_hi;
+	wire [31:0] ld_fwddata_rpipe_lo;
+	wire [31:0] ld_fwddata_rpipe_hi;
+	wire [3:0] ld_byte_hit_buf_lo;
+	wire [3:0] ld_byte_hit_buf_hi;
+	wire [31:0] ld_fwddata_buf_lo;
+	wire [31:0] ld_fwddata_buf_hi;
+	wire [63:0] ld_fwddata_lo;
+	wire [63:0] ld_fwddata_hi;
+	wire [63:0] ld_fwddata_m;
+	reg ld_full_hit_hi_m;
+	reg ld_full_hit_lo_m;
+	wire ld_full_hit_m;
+	assign ldst_byteen_m[3:0] = (({4 {lsu_pkt_m[11]}} & 4'b0001) | ({4 {lsu_pkt_m[10]}} & 4'b0011)) | ({4 {lsu_pkt_m[9]}} & 4'b1111);
+	eb1_lsu_bus_buffer #(.pt(pt)) bus_buffer(
+		.clk(clk),
+		.clk_override(clk_override),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable),
+		.dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable),
+		.dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable),
+		.dec_tlu_force_halt(dec_tlu_force_halt),
+		.lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken),
+		.lsu_busm_clken(lsu_busm_clken),
+		.lsu_c2_r_clk(lsu_c2_r_clk),
+		.lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk),
+		.lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk),
+		.lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk),
+		.lsu_free_c2_clk(lsu_free_c2_clk),
+		.lsu_busm_clk(lsu_busm_clk),
+		.dec_lsu_valid_raw_d(dec_lsu_valid_raw_d),
+		.lsu_pkt_m(lsu_pkt_m),
+		.lsu_pkt_r(lsu_pkt_r),
+		.lsu_addr_m(lsu_addr_m),
+		.end_addr_m(end_addr_m),
+		.lsu_addr_r(lsu_addr_r),
+		.end_addr_r(end_addr_r),
+		.store_data_r(store_data_r),
+		.no_word_merge_r(no_word_merge_r),
+		.no_dword_merge_r(no_dword_merge_r),
+		.lsu_busreq_m(lsu_busreq_m),
+		.lsu_busreq_r(lsu_busreq_r),
+		.ld_full_hit_m(ld_full_hit_m),
+		.flush_m_up(flush_m_up),
+		.flush_r(flush_r),
+		.lsu_commit_r(lsu_commit_r),
+		.is_sideeffects_r(is_sideeffects_r),
+		.ldst_dual_d(ldst_dual_d),
+		.ldst_dual_m(ldst_dual_m),
+		.ldst_dual_r(ldst_dual_r),
+		.ldst_byteen_ext_m(ldst_byteen_ext_m),
+		.lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any),
+		.lsu_bus_buffer_full_any(lsu_bus_buffer_full_any),
+		.lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any),
+		.ld_byte_hit_buf_lo(ld_byte_hit_buf_lo),
+		.ld_byte_hit_buf_hi(ld_byte_hit_buf_hi),
+		.ld_fwddata_buf_lo(ld_fwddata_buf_lo),
+		.ld_fwddata_buf_hi(ld_fwddata_buf_hi),
+		.lsu_imprecise_error_load_any(lsu_imprecise_error_load_any),
+		.lsu_imprecise_error_store_any(lsu_imprecise_error_store_any),
+		.lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any),
+		.lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m),
+		.lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m),
+		.lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r),
+		.lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r),
+		.lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid),
+		.lsu_nonblock_load_data_error(lsu_nonblock_load_data_error),
+		.lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag),
+		.lsu_nonblock_load_data(lsu_nonblock_load_data),
+		.lsu_pmu_bus_trxn(lsu_pmu_bus_trxn),
+		.lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned),
+		.lsu_pmu_bus_error(lsu_pmu_bus_error),
+		.lsu_pmu_bus_busy(lsu_pmu_bus_busy),
+		.lsu_axi_awvalid(lsu_axi_awvalid),
+		.lsu_axi_awready(lsu_axi_awready),
+		.lsu_axi_awid(lsu_axi_awid),
+		.lsu_axi_awaddr(lsu_axi_awaddr),
+		.lsu_axi_awregion(lsu_axi_awregion),
+		.lsu_axi_awlen(lsu_axi_awlen),
+		.lsu_axi_awsize(lsu_axi_awsize),
+		.lsu_axi_awburst(lsu_axi_awburst),
+		.lsu_axi_awlock(lsu_axi_awlock),
+		.lsu_axi_awcache(lsu_axi_awcache),
+		.lsu_axi_awprot(lsu_axi_awprot),
+		.lsu_axi_awqos(lsu_axi_awqos),
+		.lsu_axi_wvalid(lsu_axi_wvalid),
+		.lsu_axi_wready(lsu_axi_wready),
+		.lsu_axi_wdata(lsu_axi_wdata),
+		.lsu_axi_wstrb(lsu_axi_wstrb),
+		.lsu_axi_wlast(lsu_axi_wlast),
+		.lsu_axi_bvalid(lsu_axi_bvalid),
+		.lsu_axi_bready(lsu_axi_bready),
+		.lsu_axi_bresp(lsu_axi_bresp),
+		.lsu_axi_bid(lsu_axi_bid),
+		.lsu_axi_arvalid(lsu_axi_arvalid),
+		.lsu_axi_arready(lsu_axi_arready),
+		.lsu_axi_arid(lsu_axi_arid),
+		.lsu_axi_araddr(lsu_axi_araddr),
+		.lsu_axi_arregion(lsu_axi_arregion),
+		.lsu_axi_arlen(lsu_axi_arlen),
+		.lsu_axi_arsize(lsu_axi_arsize),
+		.lsu_axi_arburst(lsu_axi_arburst),
+		.lsu_axi_arlock(lsu_axi_arlock),
+		.lsu_axi_arcache(lsu_axi_arcache),
+		.lsu_axi_arprot(lsu_axi_arprot),
+		.lsu_axi_arqos(lsu_axi_arqos),
+		.lsu_axi_rvalid(lsu_axi_rvalid),
+		.lsu_axi_rready(lsu_axi_rready),
+		.lsu_axi_rid(lsu_axi_rid),
+		.lsu_axi_rdata(lsu_axi_rdata),
+		.lsu_axi_rresp(lsu_axi_rresp),
+		.lsu_bus_clk_en(lsu_bus_clk_en),
+		.lsu_bus_clk_en_q(lsu_bus_clk_en_q)
+	);
+	assign addr_match_dw_lo_r_m = lsu_addr_r[31:3] == lsu_addr_m[31:3];
+	assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2] ^ lsu_addr_m[2]);
+	assign no_word_merge_r = ((lsu_busreq_r & ~ldst_dual_r) & lsu_busreq_m) & (lsu_pkt_m[7] | ~addr_match_word_lo_r_m);
+	assign no_dword_merge_r = ((lsu_busreq_r & ~ldst_dual_r) & lsu_busreq_m) & (lsu_pkt_m[7] | ~addr_match_dw_lo_r_m);
+	assign ldst_byteen_ext_m[7:0] = {4'b0000, ldst_byteen_m[3:0]} << lsu_addr_m[1:0];
+	assign ldst_byteen_ext_r[7:0] = {4'b0000, ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
+	assign store_data_ext_r[63:0] = {32'b00000000000000000000000000000000, store_data_r[31:0]} << {lsu_addr_r[1:0], 3'b000};
+	assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
+	assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
+	assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];
+	assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];
+	assign store_data_hi_r[31:0] = store_data_ext_r[63:32];
+	assign store_data_lo_r[31:0] = store_data_ext_r[31:0];
+	assign ld_addr_rhit_lo_lo = (((lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m;
+	assign ld_addr_rhit_lo_hi = (((end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m;
+	assign ld_addr_rhit_hi_lo = (((lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m;
+	assign ld_addr_rhit_hi_hi = (((end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m;
+	generate
+		genvar i;
+		for (i = 0; i < 4; i = i + 1) begin : GenBusBufFwd
+			assign ld_byte_rhit_lo_lo[i] = (ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i]) & ldst_byteen_lo_m[i];
+			assign ld_byte_rhit_lo_hi[i] = (ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i]) & ldst_byteen_hi_m[i];
+			assign ld_byte_rhit_hi_lo[i] = (ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i]) & ldst_byteen_lo_m[i];
+			assign ld_byte_rhit_hi_hi[i] = (ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i]) & ldst_byteen_hi_m[i];
+			assign ld_byte_hit_lo[i] = (ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i]) | ld_byte_hit_buf_lo[i];
+			assign ld_byte_hit_hi[i] = (ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i]) | ld_byte_hit_buf_hi[i];
+			assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
+			assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
+			assign ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]);
+			assign ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]);
+			assign ld_fwddata_lo[(8 * i) + 7:8 * i] = (ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] : ld_fwddata_buf_lo[(8 * i) + 7:8 * i]);
+			assign ld_fwddata_hi[(8 * i) + 7:8 * i] = (ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] : ld_fwddata_buf_hi[(8 * i) + 7:8 * i]);
+		end
+	endgenerate
+	always @(*) begin
+		ld_full_hit_lo_m = 1'b1;
+		ld_full_hit_hi_m = 1'b1;
+		begin : sv2v_autoblock_58
+			reg signed [31:0] i;
+			for (i = 0; i < 4; i = i + 1)
+				begin
+					ld_full_hit_lo_m = ld_full_hit_lo_m & (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]);
+					ld_full_hit_hi_m = ld_full_hit_hi_m & (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]);
+				end
+		end
+	end
+	assign ld_full_hit_m = (((ld_full_hit_lo_m & ld_full_hit_hi_m) & lsu_busreq_m) & lsu_pkt_m[7]) & ~is_sideeffects_m;
+	assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8 * lsu_addr_m[1:0]);
+	assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];
+	rvdff #(.WIDTH(1)) clken_ff(
+		.din(lsu_bus_clk_en),
+		.dout(lsu_bus_clk_en_q),
+		.clk(active_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) is_sideeffects_rff(
+		.din(is_sideeffects_m),
+		.dout(is_sideeffects_r),
+		.clk(lsu_c1_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(4)) lsu_byten_rff(
+		.rst_l(rst_l),
+		.din(ldst_byteen_m[3:0]),
+		.dout(ldst_byteen_r[3:0]),
+		.clk(lsu_c1_r_clk)
+	);
+endmodule
+module eb1_lsu_clkdomain (
+	clk,
+	active_clk,
+	rst_l,
+	dec_tlu_force_halt,
+	clk_override,
+	dma_dccm_req,
+	ldst_stbuf_reqvld_r,
+	stbuf_reqvld_any,
+	stbuf_reqvld_flushed_any,
+	lsu_busreq_r,
+	lsu_bus_buffer_pend_any,
+	lsu_bus_buffer_empty_any,
+	lsu_stbuf_empty_any,
+	lsu_bus_clk_en,
+	lsu_p,
+	lsu_pkt_d,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	lsu_bus_obuf_c1_clken,
+	lsu_busm_clken,
+	lsu_c1_m_clk,
+	lsu_c1_r_clk,
+	lsu_c2_m_clk,
+	lsu_c2_r_clk,
+	lsu_store_c1_m_clk,
+	lsu_store_c1_r_clk,
+	lsu_stbuf_c1_clk,
+	lsu_bus_obuf_c1_clk,
+	lsu_bus_ibuf_c1_clk,
+	lsu_bus_buf_c1_clk,
+	lsu_busm_clk,
+	lsu_free_c2_clk,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire active_clk;
+	input wire rst_l;
+	input wire dec_tlu_force_halt;
+	input wire clk_override;
+	input wire dma_dccm_req;
+	input wire ldst_stbuf_reqvld_r;
+	input wire stbuf_reqvld_any;
+	input wire stbuf_reqvld_flushed_any;
+	input wire lsu_busreq_r;
+	input wire lsu_bus_buffer_pend_any;
+	input wire lsu_bus_buffer_empty_any;
+	input wire lsu_stbuf_empty_any;
+	input wire lsu_bus_clk_en;
+	input wire [13:0] lsu_p;
+	input wire [13:0] lsu_pkt_d;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_r;
+	output wire lsu_bus_obuf_c1_clken;
+	output wire lsu_busm_clken;
+	output wire lsu_c1_m_clk;
+	output wire lsu_c1_r_clk;
+	output wire lsu_c2_m_clk;
+	output wire lsu_c2_r_clk;
+	output wire lsu_store_c1_m_clk;
+	output wire lsu_store_c1_r_clk;
+	output wire lsu_stbuf_c1_clk;
+	output wire lsu_bus_obuf_c1_clk;
+	output wire lsu_bus_ibuf_c1_clk;
+	output wire lsu_bus_buf_c1_clk;
+	output wire lsu_busm_clk;
+	output wire lsu_free_c2_clk;
+	input wire scan_mode;
+	wire lsu_c1_m_clken;
+	wire lsu_c1_r_clken;
+	wire lsu_c2_m_clken;
+	wire lsu_c2_r_clken;
+	wire lsu_c1_m_clken_q;
+	wire lsu_c1_r_clken_q;
+	wire lsu_store_c1_m_clken;
+	wire lsu_store_c1_r_clken;
+	wire lsu_stbuf_c1_clken;
+	wire lsu_bus_ibuf_c1_clken;
+	wire lsu_bus_buf_c1_clken;
+	wire lsu_free_c1_clken;
+	wire lsu_free_c1_clken_q;
+	wire lsu_free_c2_clken;
+	assign lsu_c1_m_clken = (lsu_p[0] | dma_dccm_req) | clk_override;
+	assign lsu_c1_r_clken = (lsu_pkt_m[0] | lsu_c1_m_clken_q) | clk_override;
+	assign lsu_c2_m_clken = (lsu_c1_m_clken | lsu_c1_m_clken_q) | clk_override;
+	assign lsu_c2_r_clken = (lsu_c1_r_clken | lsu_c1_r_clken_q) | clk_override;
+	assign lsu_store_c1_m_clken = (lsu_c1_m_clken & lsu_pkt_d[6]) | clk_override;
+	assign lsu_store_c1_r_clken = (lsu_c1_r_clken & lsu_pkt_m[6]) | clk_override;
+	assign lsu_stbuf_c1_clken = ((ldst_stbuf_reqvld_r | stbuf_reqvld_any) | stbuf_reqvld_flushed_any) | clk_override;
+	assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override;
+	assign lsu_bus_obuf_c1_clken = ((lsu_bus_buffer_pend_any | lsu_busreq_r) | clk_override) & lsu_bus_clk_en;
+	assign lsu_bus_buf_c1_clken = ((~lsu_bus_buffer_empty_any | lsu_busreq_r) | dec_tlu_force_halt) | clk_override;
+	assign lsu_free_c1_clken = (((((lsu_p[0] | lsu_pkt_d[0]) | lsu_pkt_m[0]) | lsu_pkt_r[0]) | ~lsu_bus_buffer_empty_any) | ~lsu_stbuf_empty_any) | clk_override;
+	assign lsu_free_c2_clken = (lsu_free_c1_clken | lsu_free_c1_clken_q) | clk_override;
+	rvdff #(.WIDTH(1)) lsu_free_c1_clkenff(
+		.din(lsu_free_c1_clken),
+		.dout(lsu_free_c1_clken_q),
+		.clk(active_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) lsu_c1_m_clkenff(
+		.din(lsu_c1_m_clken),
+		.dout(lsu_c1_m_clken_q),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) lsu_c1_r_clkenff(
+		.din(lsu_c1_r_clken),
+		.dout(lsu_c1_r_clken_q),
+		.clk(lsu_free_c2_clk),
+		.rst_l(rst_l)
+	);
+	rvoclkhdr lsu_c1m_cgc(
+		.en(lsu_c1_m_clken),
+		.l1clk(lsu_c1_m_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_c1r_cgc(
+		.en(lsu_c1_r_clken),
+		.l1clk(lsu_c1_r_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_c2m_cgc(
+		.en(lsu_c2_m_clken),
+		.l1clk(lsu_c2_m_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_c2r_cgc(
+		.en(lsu_c2_r_clken),
+		.l1clk(lsu_c2_r_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_store_c1m_cgc(
+		.en(lsu_store_c1_m_clken),
+		.l1clk(lsu_store_c1_m_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_store_c1r_cgc(
+		.en(lsu_store_c1_r_clken),
+		.l1clk(lsu_store_c1_r_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_stbuf_c1_cgc(
+		.en(lsu_stbuf_c1_clken),
+		.l1clk(lsu_stbuf_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_bus_ibuf_c1_cgc(
+		.en(lsu_bus_ibuf_c1_clken),
+		.l1clk(lsu_bus_ibuf_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_bus_buf_c1_cgc(
+		.en(lsu_bus_buf_c1_clken),
+		.l1clk(lsu_bus_buf_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	assign lsu_busm_clken = ((~lsu_bus_buffer_empty_any | lsu_busreq_r) | clk_override) & lsu_bus_clk_en;
+	rvclkhdr lsu_bus_obuf_c1_cgc(
+		.en(lsu_bus_obuf_c1_clken),
+		.l1clk(lsu_bus_obuf_c1_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvclkhdr lsu_busm_cgc(
+		.en(lsu_busm_clken),
+		.l1clk(lsu_busm_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+	rvoclkhdr lsu_free_cgc(
+		.en(lsu_free_c2_clken),
+		.l1clk(lsu_free_c2_clk),
+		.clk(clk),
+		.scan_mode(scan_mode)
+	);
+endmodule
+module eb1_lsu_dccm_ctl (
+	lsu_c2_m_clk,
+	lsu_c2_r_clk,
+	lsu_c1_r_clk,
+	lsu_store_c1_r_clk,
+	lsu_free_c2_clk,
+	clk_override,
+	clk,
+	rst_l,
+	lsu_pkt_r,
+	lsu_pkt_m,
+	lsu_pkt_d,
+	addr_in_dccm_d,
+	addr_in_pic_d,
+	addr_in_pic_m,
+	addr_in_dccm_m,
+	addr_in_dccm_r,
+	addr_in_pic_r,
+	lsu_raw_fwd_lo_r,
+	lsu_raw_fwd_hi_r,
+	lsu_commit_r,
+	ldst_dual_m,
+	ldst_dual_r,
+	lsu_addr_d,
+	lsu_addr_m,
+	lsu_addr_r,
+	end_addr_d,
+	end_addr_m,
+	end_addr_r,
+	stbuf_reqvld_any,
+	stbuf_addr_any,
+	stbuf_data_any,
+	stbuf_ecc_any,
+	stbuf_fwddata_hi_m,
+	stbuf_fwddata_lo_m,
+	stbuf_fwdbyteen_hi_m,
+	stbuf_fwdbyteen_lo_m,
+	dccm_rdata_hi_r,
+	dccm_rdata_lo_r,
+	dccm_data_ecc_hi_r,
+	dccm_data_ecc_lo_r,
+	lsu_ld_data_r,
+	lsu_ld_data_corr_r,
+	lsu_double_ecc_error_r,
+	single_ecc_error_hi_r,
+	single_ecc_error_lo_r,
+	sec_data_hi_r,
+	sec_data_lo_r,
+	sec_data_hi_r_ff,
+	sec_data_lo_r_ff,
+	sec_data_ecc_hi_r_ff,
+	sec_data_ecc_lo_r_ff,
+	dccm_rdata_hi_m,
+	dccm_rdata_lo_m,
+	dccm_data_ecc_hi_m,
+	dccm_data_ecc_lo_m,
+	lsu_ld_data_m,
+	lsu_double_ecc_error_m,
+	sec_data_hi_m,
+	sec_data_lo_m,
+	store_data_m,
+	dma_dccm_wen,
+	dma_pic_wen,
+	dma_mem_tag_m,
+	dma_mem_addr,
+	dma_mem_wdata,
+	dma_dccm_wdata_lo,
+	dma_dccm_wdata_hi,
+	dma_dccm_wdata_ecc_hi,
+	dma_dccm_wdata_ecc_lo,
+	store_data_hi_r,
+	store_data_lo_r,
+	store_datafn_hi_r,
+	store_datafn_lo_r,
+	store_data_r,
+	ld_single_ecc_error_r,
+	ld_single_ecc_error_r_ff,
+	picm_mask_data_m,
+	lsu_stbuf_commit_any,
+	lsu_dccm_rden_m,
+	lsu_dccm_rden_r,
+	dccm_dma_rvalid,
+	dccm_dma_ecc_error,
+	dccm_dma_rtag,
+	dccm_dma_rdata,
+	dccm_wren,
+	dccm_rden,
+	dccm_wr_addr_lo,
+	dccm_wr_addr_hi,
+	dccm_rd_addr_lo,
+	dccm_rd_addr_hi,
+	dccm_wr_data_lo,
+	dccm_wr_data_hi,
+	dccm_rd_data_lo,
+	dccm_rd_data_hi,
+	picm_wren,
+	picm_rden,
+	picm_mken,
+	picm_rdaddr,
+	picm_wraddr,
+	picm_wr_data,
+	picm_rd_data,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire lsu_c2_m_clk;
+	input wire lsu_c2_r_clk;
+	input wire lsu_c1_r_clk;
+	input wire lsu_store_c1_r_clk;
+	input wire lsu_free_c2_clk;
+	input wire clk_override;
+	input wire clk;
+	input wire rst_l;
+	input wire [13:0] lsu_pkt_r;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_d;
+	input wire addr_in_dccm_d;
+	input wire addr_in_pic_d;
+	input wire addr_in_pic_m;
+	input wire addr_in_dccm_m;
+	input wire addr_in_dccm_r;
+	input wire addr_in_pic_r;
+	input wire lsu_raw_fwd_lo_r;
+	input wire lsu_raw_fwd_hi_r;
+	input wire lsu_commit_r;
+	input wire ldst_dual_m;
+	input wire ldst_dual_r;
+	input wire [31:0] lsu_addr_d;
+	input wire [pt[1398-:9] - 1:0] lsu_addr_m;
+	input wire [31:0] lsu_addr_r;
+	input wire [pt[1398-:9] - 1:0] end_addr_d;
+	input wire [pt[1398-:9] - 1:0] end_addr_m;
+	input wire [pt[1398-:9] - 1:0] end_addr_r;
+	input wire stbuf_reqvld_any;
+	input wire [pt[157-:9] - 1:0] stbuf_addr_any;
+	input wire [pt[1382-:10] - 1:0] stbuf_data_any;
+	input wire [pt[1372-:7] - 1:0] stbuf_ecc_any;
+	input wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m;
+	input wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m;
+	input wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m;
+	input wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m;
+	output wire [pt[1382-:10] - 1:0] dccm_rdata_hi_r;
+	output wire [pt[1382-:10] - 1:0] dccm_rdata_lo_r;
+	output wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_r;
+	output wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_r;
+	output wire [pt[1382-:10] - 1:0] lsu_ld_data_r;
+	output wire [pt[1382-:10] - 1:0] lsu_ld_data_corr_r;
+	input wire lsu_double_ecc_error_r;
+	input wire single_ecc_error_hi_r;
+	input wire single_ecc_error_lo_r;
+	input wire [pt[1382-:10] - 1:0] sec_data_hi_r;
+	input wire [pt[1382-:10] - 1:0] sec_data_lo_r;
+	input wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff;
+	input wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff;
+	input wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff;
+	input wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff;
+	output wire [pt[1382-:10] - 1:0] dccm_rdata_hi_m;
+	output wire [pt[1382-:10] - 1:0] dccm_rdata_lo_m;
+	output wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_m;
+	output wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_m;
+	output wire [pt[1382-:10] - 1:0] lsu_ld_data_m;
+	input wire lsu_double_ecc_error_m;
+	input wire [pt[1382-:10] - 1:0] sec_data_hi_m;
+	input wire [pt[1382-:10] - 1:0] sec_data_lo_m;
+	input wire [31:0] store_data_m;
+	input wire dma_dccm_wen;
+	input wire dma_pic_wen;
+	input wire [2:0] dma_mem_tag_m;
+	input wire [31:0] dma_mem_addr;
+	input wire [63:0] dma_mem_wdata;
+	input wire [31:0] dma_dccm_wdata_lo;
+	input wire [31:0] dma_dccm_wdata_hi;
+	input wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi;
+	input wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo;
+	output wire [pt[1382-:10] - 1:0] store_data_hi_r;
+	output wire [pt[1382-:10] - 1:0] store_data_lo_r;
+	output wire [pt[1382-:10] - 1:0] store_datafn_hi_r;
+	output wire [pt[1382-:10] - 1:0] store_datafn_lo_r;
+	output wire [31:0] store_data_r;
+	output wire ld_single_ecc_error_r;
+	output wire ld_single_ecc_error_r_ff;
+	output wire [31:0] picm_mask_data_m;
+	output wire lsu_stbuf_commit_any;
+	output wire lsu_dccm_rden_m;
+	output wire lsu_dccm_rden_r;
+	output wire dccm_dma_rvalid;
+	output wire dccm_dma_ecc_error;
+	output wire [2:0] dccm_dma_rtag;
+	output wire [63:0] dccm_dma_rdata;
+	output wire dccm_wren;
+	output wire dccm_rden;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	output wire picm_wren;
+	output wire picm_rden;
+	output wire picm_mken;
+	output wire [31:0] picm_rdaddr;
+	output wire [31:0] picm_wraddr;
+	output wire [31:0] picm_wr_data;
+	input wire [31:0] picm_rd_data;
+	input wire scan_mode;
+	localparam DCCM_WIDTH_BITS = $clog2(pt[1389-:7]);
+	wire lsu_dccm_rden_d;
+	wire lsu_dccm_wren_d;
+	wire ld_single_ecc_error_lo_r;
+	wire ld_single_ecc_error_hi_r;
+	wire ld_single_ecc_error_lo_r_ns;
+	wire ld_single_ecc_error_hi_r_ns;
+	wire ld_single_ecc_error_lo_r_ff;
+	wire ld_single_ecc_error_hi_r_ff;
+	wire lsu_double_ecc_error_r_ff;
+	wire [pt[1398-:9] - 1:0] ld_sec_addr_lo_r_ff;
+	wire [pt[1398-:9] - 1:0] ld_sec_addr_hi_r_ff;
+	wire [pt[1382-:10] - 1:0] store_data_lo_r_in;
+	wire [pt[1382-:10] - 1:0] store_data_hi_r_in;
+	wire [63:0] picm_rd_data_m;
+	wire dccm_wr_bypass_d_m_hi;
+	wire dccm_wr_bypass_d_r_hi;
+	wire dccm_wr_bypass_d_m_lo;
+	wire dccm_wr_bypass_d_r_lo;
+	wire kill_ecc_corr_lo_r;
+	wire kill_ecc_corr_hi_r;
+	wire [3:0] store_byteen_m;
+	wire [3:0] store_byteen_r;
+	wire [7:0] store_byteen_ext_m;
+	wire [7:0] store_byteen_ext_r;
+	generate
+		if (pt[202-:5] == 1) begin : L2U_Plus1_1
+			wire [63:0] lsu_rdata_r;
+			wire [63:0] lsu_rdata_corr_r;
+			wire [63:0] dccm_rdata_r;
+			wire [63:0] dccm_rdata_corr_r;
+			wire [63:0] stbuf_fwddata_r;
+			wire [7:0] stbuf_fwdbyteen_r;
+			wire [31:0] stbuf_fwddata_lo_r;
+			wire [31:0] stbuf_fwddata_hi_r;
+			wire [3:0] stbuf_fwdbyteen_lo_r;
+			wire [3:0] stbuf_fwdbyteen_hi_r;
+			wire [31:0] lsu_rdata_lo_r;
+			wire [31:0] lsu_rdata_hi_r;
+			wire [63:0] picm_rd_data_r;
+			wire [63:32] lsu_ld_data_r_nc;
+			wire [63:32] lsu_ld_data_corr_r_nc;
+			wire [2:0] dma_mem_tag_r;
+			wire stbuf_fwddata_en;
+			assign dccm_dma_rvalid = (lsu_pkt_r[0] & lsu_pkt_r[7]) & lsu_pkt_r[4];
+			assign dccm_dma_ecc_error = lsu_double_ecc_error_r;
+			assign dccm_dma_rtag[2:0] = dma_mem_tag_r[2:0];
+			assign dccm_dma_rdata[63:0] = (ldst_dual_r ? lsu_rdata_corr_r[63:0] : {2 {lsu_rdata_corr_r[31:0]}});
+			assign {lsu_ld_data_r_nc[63:32], lsu_ld_data_r[31:0]} = lsu_rdata_r[63:0] >> (8 * lsu_addr_r[1:0]);
+			assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> (8 * lsu_addr_r[1:0]);
+			assign picm_rd_data_r[63:32] = picm_rd_data_r[31:0];
+			assign dccm_rdata_r[63:0] = {dccm_rdata_hi_r[31:0], dccm_rdata_lo_r[31:0]};
+			assign dccm_rdata_corr_r[63:0] = {sec_data_hi_r[31:0], sec_data_lo_r[31:0]};
+			assign stbuf_fwddata_r[63:0] = {stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]};
+			assign stbuf_fwdbyteen_r[7:0] = {stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]};
+			assign stbuf_fwddata_en = (|stbuf_fwdbyteen_hi_m[3:0] | |stbuf_fwdbyteen_lo_m[3:0]) | clk_override;
+			genvar i;
+			for (i = 0; i < 8; i = i + 1) begin : GenDMAData
+				assign lsu_rdata_corr_r[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8 * i) + 7:8 * i] : (addr_in_pic_r ? picm_rd_data_r[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_r}} & dccm_rdata_corr_r[(8 * i) + 7:8 * i]));
+				assign lsu_rdata_r[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8 * i) + 7:8 * i] : (addr_in_pic_r ? picm_rd_data_r[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_r}} & dccm_rdata_r[(8 * i) + 7:8 * i]));
+			end
+			rvdffe #(.WIDTH(pt[1382-:10])) dccm_rdata_hi_r_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(dccm_rdata_hi_m[pt[1382-:10] - 1:0]),
+				.dout(dccm_rdata_hi_r[pt[1382-:10] - 1:0]),
+				.en((lsu_dccm_rden_m & ldst_dual_m) | clk_override)
+			);
+			rvdffe #(.WIDTH(pt[1382-:10])) dccm_rdata_lo_r_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(dccm_rdata_lo_m[pt[1382-:10] - 1:0]),
+				.dout(dccm_rdata_lo_r[pt[1382-:10] - 1:0]),
+				.en(lsu_dccm_rden_m | clk_override)
+			);
+			rvdffe #(.WIDTH(2 * pt[1372-:7])) dccm_data_ecc_r_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din({dccm_data_ecc_hi_m[pt[1372-:7] - 1:0], dccm_data_ecc_lo_m[pt[1372-:7] - 1:0]}),
+				.dout({dccm_data_ecc_hi_r[pt[1372-:7] - 1:0], dccm_data_ecc_lo_r[pt[1372-:7] - 1:0]}),
+				.en(lsu_dccm_rden_m | clk_override)
+			);
+			rvdff #(.WIDTH(8)) stbuf_fwdbyteen_ff(
+				.rst_l(rst_l),
+				.din({stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}),
+				.dout({stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}),
+				.clk(lsu_c2_r_clk)
+			);
+			rvdffe #(.WIDTH(64)) stbuf_fwddata_ff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din({stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}),
+				.dout({stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}),
+				.en(stbuf_fwddata_en)
+			);
+			rvdffe #(.WIDTH(32)) picm_rddata_rff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(picm_rd_data_m[31:0]),
+				.dout(picm_rd_data_r[31:0]),
+				.en(addr_in_pic_m | clk_override)
+			);
+			rvdff #(.WIDTH(3)) dma_mem_tag_rff(
+				.rst_l(rst_l),
+				.din(dma_mem_tag_m[2:0]),
+				.dout(dma_mem_tag_r[2:0]),
+				.clk(lsu_c1_r_clk)
+			);
+		end
+		else begin : L2U_Plus1_0
+			wire [63:0] lsu_rdata_m;
+			wire [63:0] lsu_rdata_corr_m;
+			wire [63:0] dccm_rdata_m;
+			wire [63:0] dccm_rdata_corr_m;
+			wire [63:0] stbuf_fwddata_m;
+			wire [7:0] stbuf_fwdbyteen_m;
+			wire [63:32] lsu_ld_data_m_nc;
+			wire [63:32] lsu_ld_data_corr_m_nc;
+			wire [31:0] lsu_ld_data_corr_m;
+			assign dccm_dma_rvalid = (lsu_pkt_m[0] & lsu_pkt_m[7]) & lsu_pkt_m[4];
+			assign dccm_dma_ecc_error = lsu_double_ecc_error_m;
+			assign dccm_dma_rtag[2:0] = dma_mem_tag_m[2:0];
+			assign dccm_dma_rdata[63:0] = (ldst_dual_m ? lsu_rdata_corr_m[63:0] : {2 {lsu_rdata_corr_m[31:0]}});
+			assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = lsu_rdata_m[63:0] >> (8 * lsu_addr_m[1:0]);
+			assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = lsu_rdata_corr_m[63:0] >> (8 * lsu_addr_m[1:0]);
+			assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0], dccm_rdata_lo_m[31:0]};
+			assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0], sec_data_lo_m[31:0]};
+			assign stbuf_fwddata_m[63:0] = {stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]};
+			assign stbuf_fwdbyteen_m[7:0] = {stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]};
+			genvar i;
+			for (i = 0; i < 8; i = i + 1) begin : GenLoop
+				assign lsu_rdata_corr_m[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8 * i) + 7:8 * i] : (addr_in_pic_m ? picm_rd_data_m[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_m}} & dccm_rdata_corr_m[(8 * i) + 7:8 * i]));
+				assign lsu_rdata_m[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8 * i) + 7:8 * i] : (addr_in_pic_m ? picm_rd_data_m[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_m}} & dccm_rdata_m[(8 * i) + 7:8 * i]));
+			end
+			rvdffe #(.WIDTH(32)) lsu_ld_data_corr_rff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(lsu_ld_data_corr_m[31:0]),
+				.dout(lsu_ld_data_corr_r[31:0]),
+				.en(((lsu_pkt_m[0] & lsu_pkt_m[7]) & (addr_in_pic_m | addr_in_dccm_m)) | clk_override)
+			);
+		end
+	endgenerate
+	assign kill_ecc_corr_lo_r = ((((((lsu_addr_d[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) | (end_addr_d[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_d[0]) & lsu_pkt_d[6]) & lsu_pkt_d[4]) & addr_in_dccm_d) | ((((((lsu_addr_m[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) | (end_addr_m[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_m[0]) & lsu_pkt_m[6]) & lsu_pkt_m[4]) & addr_in_dccm_m);
+	assign kill_ecc_corr_hi_r = ((((((lsu_addr_d[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) | (end_addr_d[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_d[0]) & lsu_pkt_d[6]) & lsu_pkt_d[4]) & addr_in_dccm_d) | ((((((lsu_addr_m[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) | (end_addr_m[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_m[0]) & lsu_pkt_m[6]) & lsu_pkt_m[4]) & addr_in_dccm_m);
+	assign ld_single_ecc_error_lo_r = (lsu_pkt_r[7] & single_ecc_error_lo_r) & ~lsu_raw_fwd_lo_r;
+	assign ld_single_ecc_error_hi_r = (lsu_pkt_r[7] & single_ecc_error_hi_r) & ~lsu_raw_fwd_hi_r;
+	assign ld_single_ecc_error_r = (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & ~lsu_double_ecc_error_r;
+	assign ld_single_ecc_error_lo_r_ns = (ld_single_ecc_error_lo_r & (lsu_commit_r | lsu_pkt_r[4])) & ~kill_ecc_corr_lo_r;
+	assign ld_single_ecc_error_hi_r_ns = (ld_single_ecc_error_hi_r & (lsu_commit_r | lsu_pkt_r[4])) & ~kill_ecc_corr_hi_r;
+	assign ld_single_ecc_error_r_ff = (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & ~lsu_double_ecc_error_r_ff;
+	assign lsu_stbuf_commit_any = stbuf_reqvld_any & (~((lsu_dccm_rden_d | lsu_dccm_wren_d) | ld_single_ecc_error_r_ff) | (lsu_dccm_rden_d & ~((stbuf_addr_any[pt[1275-:6]+:pt[1405-:7]] == lsu_addr_d[pt[1275-:6]+:pt[1405-:7]]) | (stbuf_addr_any[pt[1275-:6]+:pt[1405-:7]] == end_addr_d[pt[1275-:6]+:pt[1405-:7]]))));
+	assign lsu_dccm_rden_d = (lsu_pkt_d[0] & (lsu_pkt_d[7] | (lsu_pkt_d[6] & (~(lsu_pkt_d[9] | lsu_pkt_d[8]) | (lsu_addr_d[1:0] != 2'b00))))) & addr_in_dccm_d;
+	assign lsu_dccm_wren_d = dma_dccm_wen;
+	assign dccm_wren = (lsu_dccm_wren_d | lsu_stbuf_commit_any) | ld_single_ecc_error_r_ff;
+	assign dccm_rden = lsu_dccm_rden_d & addr_in_dccm_d;
+	assign dccm_wr_addr_lo[pt[1398-:9] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0] : ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0]) : (lsu_dccm_wren_d ? lsu_addr_d[pt[1398-:9] - 1:0] : stbuf_addr_any[pt[1398-:9] - 1:0]));
+	assign dccm_wr_addr_hi[pt[1398-:9] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0] : ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0]) : (lsu_dccm_wren_d ? end_addr_d[pt[1398-:9] - 1:0] : stbuf_addr_any[pt[1398-:9] - 1:0]));
+	assign dccm_rd_addr_lo[pt[1398-:9] - 1:0] = lsu_addr_d[pt[1398-:9] - 1:0];
+	assign dccm_rd_addr_hi[pt[1398-:9] - 1:0] = end_addr_d[pt[1398-:9] - 1:0];
+	assign dccm_wr_data_lo[pt[1360-:10] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? {sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0], sec_data_lo_r_ff[pt[1382-:10] - 1:0]} : {sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0], sec_data_hi_r_ff[pt[1382-:10] - 1:0]}) : (dma_dccm_wen ? {dma_dccm_wdata_ecc_lo[pt[1372-:7] - 1:0], dma_dccm_wdata_lo[pt[1382-:10] - 1:0]} : {stbuf_ecc_any[pt[1372-:7] - 1:0], stbuf_data_any[pt[1382-:10] - 1:0]}));
+	assign dccm_wr_data_hi[pt[1360-:10] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? {sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0], sec_data_hi_r_ff[pt[1382-:10] - 1:0]} : {sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0], sec_data_lo_r_ff[pt[1382-:10] - 1:0]}) : (dma_dccm_wen ? {dma_dccm_wdata_ecc_hi[pt[1372-:7] - 1:0], dma_dccm_wdata_hi[pt[1382-:10] - 1:0]} : {stbuf_ecc_any[pt[1372-:7] - 1:0], stbuf_data_any[pt[1382-:10] - 1:0]}));
+	assign store_byteen_m[3:0] = {4 {lsu_pkt_m[6]}} & ((({4 {lsu_pkt_m[11]}} & 4'b0001) | ({4 {lsu_pkt_m[10]}} & 4'b0011)) | ({4 {lsu_pkt_m[9]}} & 4'b1111));
+	assign store_byteen_r[3:0] = {4 {lsu_pkt_r[6]}} & ((({4 {lsu_pkt_r[11]}} & 4'b0001) | ({4 {lsu_pkt_r[10]}} & 4'b0011)) | ({4 {lsu_pkt_r[9]}} & 4'b1111));
+	assign store_byteen_ext_m[7:0] = {4'b0000, store_byteen_m[3:0]} << lsu_addr_m[1:0];
+	assign store_byteen_ext_r[7:0] = {4'b0000, store_byteen_r[3:0]} << lsu_addr_r[1:0];
+	assign dccm_wr_bypass_d_m_lo = (stbuf_addr_any[pt[1398-:9] - 1:2] == lsu_addr_m[pt[1398-:9] - 1:2]) & addr_in_dccm_m;
+	assign dccm_wr_bypass_d_m_hi = (stbuf_addr_any[pt[1398-:9] - 1:2] == end_addr_m[pt[1398-:9] - 1:2]) & addr_in_dccm_m;
+	assign dccm_wr_bypass_d_r_lo = (stbuf_addr_any[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) & addr_in_dccm_r;
+	assign dccm_wr_bypass_d_r_hi = (stbuf_addr_any[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) & addr_in_dccm_r;
+	generate
+		if (pt[202-:5] == 1) begin : L2U1_Plus1_1
+			wire dccm_wren_Q;
+			wire [31:0] dccm_wr_data_Q;
+			wire dccm_wr_bypass_d_m_lo_Q;
+			wire dccm_wr_bypass_d_m_hi_Q;
+			wire [31:0] store_data_pre_hi_r;
+			wire [31:0] store_data_pre_lo_r;
+			assign {store_data_pre_hi_r[31:0], store_data_pre_lo_r[31:0]} = {32'b00000000000000000000000000000000, store_data_r[31:0]} << (8 * lsu_addr_r[1:0]);
+			genvar i;
+			for (i = 0; i < 4; i = i + 1) begin
+				assign store_data_lo_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i] ? store_data_pre_lo_r[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_lo_r[(8 * i) + 7:8 * i]));
+				assign store_data_hi_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i + 4] ? store_data_pre_hi_r[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_hi_r[(8 * i) + 7:8 * i]));
+				assign store_datafn_lo_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i] ? store_data_pre_lo_r[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo ? stbuf_data_any[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_lo_r[(8 * i) + 7:8 * i])));
+				assign store_datafn_hi_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i + 4] ? store_data_pre_hi_r[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi ? stbuf_data_any[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_hi_r[(8 * i) + 7:8 * i])));
+			end
+			rvdff #(.WIDTH(1)) dccm_wren_ff(
+				.rst_l(rst_l),
+				.din(lsu_stbuf_commit_any),
+				.dout(dccm_wren_Q),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdffe #(.WIDTH(32)) dccm_wrdata_ff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(stbuf_data_any[31:0]),
+				.dout(dccm_wr_data_Q[31:0]),
+				.en(lsu_stbuf_commit_any | clk_override),
+				.clk(clk)
+			);
+			rvdff #(.WIDTH(1)) dccm_wrbyp_dm_loff(
+				.rst_l(rst_l),
+				.din(dccm_wr_bypass_d_m_lo),
+				.dout(dccm_wr_bypass_d_m_lo_Q),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdff #(.WIDTH(1)) dccm_wrbyp_dm_hiff(
+				.rst_l(rst_l),
+				.din(dccm_wr_bypass_d_m_hi),
+				.dout(dccm_wr_bypass_d_m_hi_Q),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdff #(.WIDTH(32)) store_data_rff(
+				.rst_l(rst_l),
+				.din(store_data_m[31:0]),
+				.dout(store_data_r[31:0]),
+				.clk(lsu_store_c1_r_clk)
+			);
+		end
+		else begin : L2U1_Plus1_0
+			wire [31:0] store_data_hi_m;
+			wire [31:0] store_data_lo_m;
+			wire [63:0] store_data_mask;
+			assign {store_data_hi_m[31:0], store_data_lo_m[31:0]} = {32'b00000000000000000000000000000000, store_data_m[31:0]} << (8 * lsu_addr_m[1:0]);
+			genvar i;
+			for (i = 0; i < 4; i = i + 1) begin
+				assign store_data_hi_r_in[(8 * i) + 7:8 * i] = (store_byteen_ext_m[i + 4] ? store_data_hi_m[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi ? stbuf_data_any[(8 * i) + 7:8 * i] : sec_data_hi_m[(8 * i) + 7:8 * i]));
+				assign store_data_lo_r_in[(8 * i) + 7:8 * i] = (store_byteen_ext_m[i] ? store_data_lo_m[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo ? stbuf_data_any[(8 * i) + 7:8 * i] : sec_data_lo_m[(8 * i) + 7:8 * i]));
+				assign store_datafn_lo_r[(8 * i) + 7:8 * i] = ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo) & ~store_byteen_ext_r[i] ? stbuf_data_any[(8 * i) + 7:8 * i] : store_data_lo_r[(8 * i) + 7:8 * i]);
+				assign store_datafn_hi_r[(8 * i) + 7:8 * i] = ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi) & ~store_byteen_ext_r[i + 4] ? stbuf_data_any[(8 * i) + 7:8 * i] : store_data_hi_r[(8 * i) + 7:8 * i]);
+			end
+			for (i = 0; i < 4; i = i + 1) assign store_data_mask[(8 * i) + 7:8 * i] = {8 {store_byteen_r[i]}};
+			function automatic [31:0] sv2v_cast_32;
+				input reg [31:0] inp;
+				sv2v_cast_32 = inp;
+			endfunction
+			assign store_data_r[31:0] = sv2v_cast_32({store_data_hi_r[31:0], store_data_lo_r[31:0]} >> (8 * lsu_addr_r[1:0])) & store_data_mask[31:0];
+			rvdffe #(.WIDTH(pt[1382-:10])) store_data_hi_rff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(store_data_hi_r_in[pt[1382-:10] - 1:0]),
+				.dout(store_data_hi_r[pt[1382-:10] - 1:0]),
+				.en(((ldst_dual_m & lsu_pkt_m[0]) & lsu_pkt_m[6]) | clk_override),
+				.clk(clk)
+			);
+			rvdff #(.WIDTH(pt[1382-:10])) store_data_lo_rff(
+				.rst_l(rst_l),
+				.din(store_data_lo_r_in[pt[1382-:10] - 1:0]),
+				.dout(store_data_lo_r[pt[1382-:10] - 1:0]),
+				.clk(lsu_store_c1_r_clk)
+			);
+		end
+	endgenerate
+	assign dccm_rdata_lo_m[pt[1382-:10] - 1:0] = dccm_rd_data_lo[pt[1382-:10] - 1:0];
+	assign dccm_rdata_hi_m[pt[1382-:10] - 1:0] = dccm_rd_data_hi[pt[1382-:10] - 1:0];
+	assign dccm_data_ecc_lo_m[pt[1372-:7] - 1:0] = dccm_rd_data_lo[pt[1360-:10] - 1:pt[1382-:10]];
+	assign dccm_data_ecc_hi_m[pt[1372-:7] - 1:0] = dccm_rd_data_hi[pt[1360-:10] - 1:pt[1382-:10]];
+	assign picm_wren = (((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_pic_r) & lsu_commit_r) | dma_pic_wen;
+	assign picm_rden = (lsu_pkt_d[0] & lsu_pkt_d[7]) & addr_in_pic_d;
+	assign picm_mken = (lsu_pkt_d[0] & lsu_pkt_d[6]) & addr_in_pic_d;
+	assign picm_rdaddr[31:0] = pt[130-:36] | {{32 - pt[94-:9] {1'b0}}, lsu_addr_d[pt[94-:9] - 1:0]};
+	assign picm_wraddr[31:0] = pt[130-:36] | {{32 - pt[94-:9] {1'b0}}, (dma_pic_wen ? dma_mem_addr[pt[94-:9] - 1:0] : lsu_addr_r[pt[94-:9] - 1:0])};
+	assign picm_wr_data[31:0] = (dma_pic_wen ? dma_mem_wdata[31:0] : store_datafn_lo_r[31:0]);
+	assign picm_mask_data_m[31:0] = picm_rd_data_m[31:0];
+	assign picm_rd_data_m[63:0] = {picm_rd_data[31:0], picm_rd_data[31:0]};
+	generate
+		if (pt[1365-:5] == 1) begin : Gen_dccm_enable
+			rvdff #(.WIDTH(1)) dccm_rden_mff(
+				.rst_l(rst_l),
+				.din(lsu_dccm_rden_d),
+				.dout(lsu_dccm_rden_m),
+				.clk(lsu_c2_m_clk)
+			);
+			rvdff #(.WIDTH(1)) dccm_rden_rff(
+				.rst_l(rst_l),
+				.din(lsu_dccm_rden_m),
+				.dout(lsu_dccm_rden_r),
+				.clk(lsu_c2_r_clk)
+			);
+			rvdff #(.WIDTH(1)) ld_double_ecc_error_rff(
+				.rst_l(rst_l),
+				.din(lsu_double_ecc_error_r),
+				.dout(lsu_double_ecc_error_r_ff),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdff #(.WIDTH(1)) ld_single_ecc_error_hi_rff(
+				.rst_l(rst_l),
+				.din(ld_single_ecc_error_hi_r_ns),
+				.dout(ld_single_ecc_error_hi_r_ff),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdff #(.WIDTH(1)) ld_single_ecc_error_lo_rff(
+				.rst_l(rst_l),
+				.din(ld_single_ecc_error_lo_r_ns),
+				.dout(ld_single_ecc_error_lo_r_ff),
+				.clk(lsu_free_c2_clk)
+			);
+			rvdffe #(.WIDTH(pt[1398-:9])) ld_sec_addr_hi_rff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(end_addr_r[pt[1398-:9] - 1:0]),
+				.dout(ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0]),
+				.en(ld_single_ecc_error_r | clk_override),
+				.clk(clk)
+			);
+			rvdffe #(.WIDTH(pt[1398-:9])) ld_sec_addr_lo_rff(
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(lsu_addr_r[pt[1398-:9] - 1:0]),
+				.dout(ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0]),
+				.en(ld_single_ecc_error_r | clk_override),
+				.clk(clk)
+			);
+		end
+		else begin : Gen_dccm_disable
+			assign lsu_dccm_rden_m = 1'b0;
+			assign lsu_dccm_rden_r = 1'b0;
+			assign lsu_double_ecc_error_r_ff = 1'b0;
+			assign ld_single_ecc_error_hi_r_ff = 1'b0;
+			assign ld_single_ecc_error_lo_r_ff = 1'b0;
+			assign ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0] = {pt[1398-:9] {1'sb0}};
+			assign ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0] = {pt[1398-:9] {1'sb0}};
+		end
+	endgenerate
+endmodule
+module eb1_lsu_dccm_mem (
+`ifdef USE_POWER_PINS	
+	vccd1,
+	vssd1,
+`endif
+	clk,
+	active_clk,
+	rst_l,
+	clk_override,
+	dccm_wren,
+	dccm_rden,
+	dccm_wr_addr_lo,
+	dccm_wr_addr_hi,
+	dccm_rd_addr_lo,
+	dccm_rd_addr_hi,
+	dccm_wr_data_lo,
+	dccm_wr_data_hi,
+	dccm_ext_in_pkt,
+	dccm_rd_data_lo,
+	dccm_rd_data_hi,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+`ifdef USE_POWER_PINS
+	inout wire vccd1;
+	inout wire vssd1;
+`endif
+	input wire clk;
+	input wire active_clk;
+	input wire rst_l;
+	input wire clk_override;
+	input wire dccm_wren;
+	input wire dccm_rden;
+	input wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo;
+	input wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi;
+	input wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo;
+	input wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi;
+	input wire [pt[1360-:10] - 1:0] dccm_wr_data_lo;
+	input wire [pt[1360-:10] - 1:0] dccm_wr_data_hi;
+	input wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt;
+	output wire [pt[1360-:10] - 1:0] dccm_rd_data_lo;
+	output wire [pt[1360-:10] - 1:0] dccm_rd_data_hi;
+	input wire scan_mode;
+	localparam DCCM_WIDTH_BITS = $clog2(pt[1389-:7]);
+	localparam DCCM_INDEX_BITS = (pt[1398-:9] - pt[1405-:7]) - pt[1275-:6];
+	localparam DCCM_INDEX_DEPTH = (pt[1289-:14] * 1024) / (pt[1389-:7] * pt[1342-:9]);
+	wire [pt[1342-:9] - 1:0] wren_bank;
+	wire [pt[1342-:9] - 1:0] rden_bank;
+	wire [((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? (pt[1342-:9] * (((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1)) + (pt[1405-:7] + 1) : (pt[1342-:9] * (((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + (pt[1398-:9] - 2)):((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1)] addr_bank;
+	wire [pt[1398-:9] - 1:pt[1405-:7] + DCCM_WIDTH_BITS] rd_addr_even;
+	wire [pt[1398-:9] - 1:pt[1405-:7] + DCCM_WIDTH_BITS] rd_addr_odd;
+	wire rd_unaligned;
+	wire wr_unaligned;
+	wire [(pt[1342-:9] * pt[1360-:10]) - 1:0] dccm_bank_dout;
+	wire [pt[1360-:10] - 1:0] wrdata;
+	wire [(pt[1342-:9] * pt[1360-:10]) - 1:0] wr_data_bank;
+	wire [(DCCM_WIDTH_BITS + pt[1405-:7]) - 1:DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
+	wire [(DCCM_WIDTH_BITS + pt[1405-:7]) - 1:DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
+	wire [pt[1342-:9] - 1:0] dccm_clken;
+	assign rd_unaligned = dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]];
+	assign wr_unaligned = dccm_wr_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]];
+	assign dccm_rd_data_lo[pt[1360-:10] - 1:0] = dccm_bank_dout[(dccm_rd_addr_lo_q[pt[1275-:6]+:pt[1405-:7]] * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]];
+	assign dccm_rd_data_hi[pt[1360-:10] - 1:0] = dccm_bank_dout[(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt[1405-:7]] * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]];
+	generate
+		genvar i;
+		for (i = 0; i < pt[1342-:9]; i = i + 1) begin : mem_bank
+			assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) | (dccm_wr_addr_lo[2+:pt[1405-:7]] == i));
+			assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:pt[1405-:7]] == i) | (dccm_rd_addr_lo[2+:pt[1405-:7]] == i));
+			assign addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + DCCM_WIDTH_BITS : (pt[1405-:7] + 2) - ((pt[1405-:7] + DCCM_WIDTH_BITS) - (pt[1398-:9] - 1))) : (((i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + DCCM_WIDTH_BITS : (pt[1405-:7] + 2) - ((pt[1405-:7] + DCCM_WIDTH_BITS) - (pt[1398-:9] - 1)))) - DCCM_INDEX_BITS) + 1)+:DCCM_INDEX_BITS] = (wren_bank[i] ? ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) & wr_unaligned ? dccm_wr_addr_hi[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS] : dccm_wr_addr_lo[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS]) : ((dccm_rd_addr_hi[2+:pt[1405-:7]] == i) & rd_unaligned ? dccm_rd_addr_hi[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS] : dccm_rd_addr_lo[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS]));
+			assign wr_data_bank[i * pt[1360-:10]+:pt[1360-:10]] = ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) & wr_unaligned ? dccm_wr_data_hi[pt[1360-:10] - 1:0] : dccm_wr_data_lo[pt[1360-:10] - 1:0]);
+			assign dccm_clken[i] = (wren_bank[i] | rden_bank[i]) | clk_override;
+			if (DCCM_INDEX_DEPTH == 32768) begin : dccm
+				ram_32768x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
+				ram_16384x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
+				ram_8192x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
+				ram_4096x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
+				ram_3072x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
+				ram_2048x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
+				sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+					`ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(~dccm_clken[i]),
+					.web0(~wren_bank[i]),
+					.wmask0(4'hf),
+					.addr0(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.din0(wr_data_bank[i * pt[1360-:10]+:pt[1360-:10]]),
+					.dout0(dccm_bank_dout[i * pt[1360-:10]+:pt[1360-:10]]),
+					.clk1(clk),
+					.csb1(1'b1),
+					.addr1(8'h00),
+					.dout1()
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 512) begin : dccm
+				ram_512x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+			else if (DCCM_INDEX_DEPTH == 256) begin : dccm
+				/*sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+					`ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(~dccm_clken[i]),
+					.web0(~wren_bank[i]),
+					.wmask0(4'hf),
+					.addr0(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.din0(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
+					.dout0(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
+					.clk1(clk),
+					.csb1(1'b1),
+					.addr1(8'h00),
+					.dout1()
+				);*/
+				/*SRAM64x32 dccm(
+						`ifdef USE_POWER_PINS
+    						.VPWR(vccd1),
+    						.VGND(vssd1),
+						`endif
+    						.CLK(clk),
+    						.WE({4{wren_bank[i]}}),
+    						.EN(dccm_clken[i]),
+    						.Di(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
+    						.Do(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
+    						.A(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)])
+);*/
+					
+				DFFRAM dccm
+					(
+					`ifdef USE_POWER_PINS
+    					 .VPWR(vccd1),
+    					 .VGND(vssd1),
+					 `endif
+    					 .CLK(clk),
+    					 .WE({4{wren_bank[i]}}),
+    					 .EN(dccm_clken[i]),
+    					 .Di(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
+    					 .Do(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
+    					 .A(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)])
+					);
+			end
+			else if (DCCM_INDEX_DEPTH == 128) begin : dccm
+				ram_128x39 dccm_bank(
+					.ME(dccm_clken[i]),
+					.CLK(clk),
+					.WE(wren_bank[i]),
+					.ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]),
+					.D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]),
+					.ROP(),
+					.TEST1(dccm_ext_in_pkt[(i * 12) + 11]),
+					.RME(dccm_ext_in_pkt[(i * 12) + 10]),
+					.RM(dccm_ext_in_pkt[(i * 12) + 9-:4]),
+					.LS(dccm_ext_in_pkt[(i * 12) + 5]),
+					.DS(dccm_ext_in_pkt[(i * 12) + 4]),
+					.SD(dccm_ext_in_pkt[(i * 12) + 3]),
+					.TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]),
+					.BC1(dccm_ext_in_pkt[(i * 12) + 1]),
+					.BC2(dccm_ext_in_pkt[i * 12]),
+					.*
+				);
+			end
+		end
+	endgenerate
+	rvdff #(.WIDTH(pt[1405-:7])) rd_addr_lo_ff(
+		.rst_l(rst_l),
+		.din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]]),
+		.dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:pt[1405-:7]]),
+		.clk(active_clk)
+	);
+	rvdff #(.WIDTH(pt[1405-:7])) rd_addr_hi_ff(
+		.rst_l(rst_l),
+		.din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]]),
+		.dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt[1405-:7]]),
+		.clk(active_clk)
+	);
+endmodule
+module eb1_lsu_ecc (
+	clk,
+	lsu_c2_r_clk,
+	clk_override,
+	rst_l,
+	scan_mode,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	stbuf_data_any,
+	dec_tlu_core_ecc_disable,
+	lsu_dccm_rden_r,
+	addr_in_dccm_r,
+	lsu_addr_r,
+	end_addr_r,
+	dccm_rdata_hi_r,
+	dccm_rdata_lo_r,
+	dccm_data_ecc_hi_r,
+	dccm_data_ecc_lo_r,
+	sec_data_hi_r,
+	sec_data_lo_r,
+	sec_data_hi_r_ff,
+	sec_data_lo_r_ff,
+	ld_single_ecc_error_r,
+	ld_single_ecc_error_r_ff,
+	lsu_dccm_rden_m,
+	addr_in_dccm_m,
+	lsu_addr_m,
+	end_addr_m,
+	dccm_rdata_hi_m,
+	dccm_rdata_lo_m,
+	dccm_data_ecc_hi_m,
+	dccm_data_ecc_lo_m,
+	sec_data_hi_m,
+	sec_data_lo_m,
+	dma_dccm_wen,
+	dma_dccm_wdata_lo,
+	dma_dccm_wdata_hi,
+	dma_dccm_wdata_ecc_hi,
+	dma_dccm_wdata_ecc_lo,
+	stbuf_ecc_any,
+	sec_data_ecc_hi_r_ff,
+	sec_data_ecc_lo_r_ff,
+	single_ecc_error_hi_r,
+	single_ecc_error_lo_r,
+	lsu_single_ecc_error_r,
+	lsu_double_ecc_error_r,
+	lsu_single_ecc_error_m,
+	lsu_double_ecc_error_m
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire lsu_c2_r_clk;
+	input wire clk_override;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_r;
+	input wire [pt[1382-:10] - 1:0] stbuf_data_any;
+	input wire dec_tlu_core_ecc_disable;
+	input wire lsu_dccm_rden_r;
+	input wire addr_in_dccm_r;
+	input wire [pt[1398-:9] - 1:0] lsu_addr_r;
+	input wire [pt[1398-:9] - 1:0] end_addr_r;
+	input wire [pt[1382-:10] - 1:0] dccm_rdata_hi_r;
+	input wire [pt[1382-:10] - 1:0] dccm_rdata_lo_r;
+	input wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_r;
+	input wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_r;
+	output wire [pt[1382-:10] - 1:0] sec_data_hi_r;
+	output wire [pt[1382-:10] - 1:0] sec_data_lo_r;
+	output wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff;
+	output wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff;
+	input wire ld_single_ecc_error_r;
+	input wire ld_single_ecc_error_r_ff;
+	input wire lsu_dccm_rden_m;
+	input wire addr_in_dccm_m;
+	input wire [pt[1398-:9] - 1:0] lsu_addr_m;
+	input wire [pt[1398-:9] - 1:0] end_addr_m;
+	input wire [pt[1382-:10] - 1:0] dccm_rdata_hi_m;
+	input wire [pt[1382-:10] - 1:0] dccm_rdata_lo_m;
+	input wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_m;
+	input wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_m;
+	output wire [pt[1382-:10] - 1:0] sec_data_hi_m;
+	output wire [pt[1382-:10] - 1:0] sec_data_lo_m;
+	input wire dma_dccm_wen;
+	input wire [31:0] dma_dccm_wdata_lo;
+	input wire [31:0] dma_dccm_wdata_hi;
+	output wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi;
+	output wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo;
+	output wire [pt[1372-:7] - 1:0] stbuf_ecc_any;
+	output wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff;
+	output wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff;
+	output wire single_ecc_error_hi_r;
+	output wire single_ecc_error_lo_r;
+	output wire lsu_single_ecc_error_r;
+	output wire lsu_double_ecc_error_r;
+	output wire lsu_single_ecc_error_m;
+	output wire lsu_double_ecc_error_m;
+	wire is_ldst_r;
+	wire is_ldst_hi_any;
+	wire is_ldst_lo_any;
+	wire [pt[1382-:10] - 1:0] dccm_wdata_hi_any;
+	wire [pt[1382-:10] - 1:0] dccm_wdata_lo_any;
+	wire [pt[1372-:7] - 1:0] dccm_wdata_ecc_hi_any;
+	wire [pt[1372-:7] - 1:0] dccm_wdata_ecc_lo_any;
+	wire [pt[1382-:10] - 1:0] dccm_rdata_hi_any;
+	wire [pt[1382-:10] - 1:0] dccm_rdata_lo_any;
+	wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_any;
+	wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_any;
+	wire [pt[1382-:10] - 1:0] sec_data_hi_any;
+	wire [pt[1382-:10] - 1:0] sec_data_lo_any;
+	wire single_ecc_error_hi_any;
+	wire single_ecc_error_lo_any;
+	wire double_ecc_error_hi_any;
+	wire double_ecc_error_lo_any;
+	wire double_ecc_error_hi_m;
+	wire double_ecc_error_lo_m;
+	wire double_ecc_error_hi_r;
+	wire double_ecc_error_lo_r;
+	wire [6:0] ecc_out_hi_nc;
+	wire [6:0] ecc_out_lo_nc;
+	generate
+		if (pt[202-:5] == 1) begin : L2U_Plus1_1
+			wire ldst_dual_m;
+			wire ldst_dual_r;
+			wire is_ldst_m;
+			wire is_ldst_hi_r;
+			wire is_ldst_lo_r;
+			assign ldst_dual_r = lsu_addr_r[2] != end_addr_r[2];
+			assign is_ldst_r = ((lsu_pkt_r[0] & (lsu_pkt_r[7] | lsu_pkt_r[6])) & addr_in_dccm_r) & lsu_dccm_rden_r;
+			assign is_ldst_lo_r = is_ldst_r & ~dec_tlu_core_ecc_disable;
+			assign is_ldst_hi_r = (is_ldst_r & ldst_dual_r) & ~dec_tlu_core_ecc_disable;
+			assign is_ldst_hi_any = is_ldst_hi_r;
+			assign dccm_rdata_hi_any[pt[1382-:10] - 1:0] = dccm_rdata_hi_r[pt[1382-:10] - 1:0];
+			assign dccm_data_ecc_hi_any[pt[1372-:7] - 1:0] = dccm_data_ecc_hi_r[pt[1372-:7] - 1:0];
+			assign is_ldst_lo_any = is_ldst_lo_r;
+			assign dccm_rdata_lo_any[pt[1382-:10] - 1:0] = dccm_rdata_lo_r[pt[1382-:10] - 1:0];
+			assign dccm_data_ecc_lo_any[pt[1372-:7] - 1:0] = dccm_data_ecc_lo_r[pt[1372-:7] - 1:0];
+			assign sec_data_hi_r[pt[1382-:10] - 1:0] = sec_data_hi_any[pt[1382-:10] - 1:0];
+			assign single_ecc_error_hi_r = single_ecc_error_hi_any;
+			assign double_ecc_error_hi_r = double_ecc_error_hi_any;
+			assign sec_data_lo_r[pt[1382-:10] - 1:0] = sec_data_lo_any[pt[1382-:10] - 1:0];
+			assign single_ecc_error_lo_r = single_ecc_error_lo_any;
+			assign double_ecc_error_lo_r = double_ecc_error_lo_any;
+			assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r;
+			assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r;
+		end
+		else begin : L2U_Plus1_0
+			wire ldst_dual_m;
+			wire is_ldst_m;
+			wire is_ldst_hi_m;
+			wire is_ldst_lo_m;
+			assign ldst_dual_m = lsu_addr_m[2] != end_addr_m[2];
+			assign is_ldst_m = ((lsu_pkt_m[0] & (lsu_pkt_m[7] | lsu_pkt_m[6])) & addr_in_dccm_m) & lsu_dccm_rden_m;
+			assign is_ldst_lo_m = is_ldst_m & ~dec_tlu_core_ecc_disable;
+			assign is_ldst_hi_m = (is_ldst_m & (ldst_dual_m | lsu_pkt_m[4])) & ~dec_tlu_core_ecc_disable;
+			assign is_ldst_hi_any = is_ldst_hi_m;
+			assign dccm_rdata_hi_any[pt[1382-:10] - 1:0] = dccm_rdata_hi_m[pt[1382-:10] - 1:0];
+			assign dccm_data_ecc_hi_any[pt[1372-:7] - 1:0] = dccm_data_ecc_hi_m[pt[1372-:7] - 1:0];
+			assign is_ldst_lo_any = is_ldst_lo_m;
+			assign dccm_rdata_lo_any[pt[1382-:10] - 1:0] = dccm_rdata_lo_m[pt[1382-:10] - 1:0];
+			assign dccm_data_ecc_lo_any[pt[1372-:7] - 1:0] = dccm_data_ecc_lo_m[pt[1372-:7] - 1:0];
+			assign sec_data_hi_m[pt[1382-:10] - 1:0] = sec_data_hi_any[pt[1382-:10] - 1:0];
+			assign double_ecc_error_hi_m = double_ecc_error_hi_any;
+			assign sec_data_lo_m[pt[1382-:10] - 1:0] = sec_data_lo_any[pt[1382-:10] - 1:0];
+			assign double_ecc_error_lo_m = double_ecc_error_lo_any;
+			assign lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any;
+			assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m;
+			rvdff #(.WIDTH(1)) lsu_single_ecc_err_r(
+				.din(lsu_single_ecc_error_m),
+				.dout(lsu_single_ecc_error_r),
+				.clk(lsu_c2_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) lsu_double_ecc_err_r(
+				.din(lsu_double_ecc_error_m),
+				.dout(lsu_double_ecc_error_r),
+				.clk(lsu_c2_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) ldst_sec_lo_rff(
+				.din(single_ecc_error_lo_any),
+				.dout(single_ecc_error_lo_r),
+				.clk(lsu_c2_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) ldst_sec_hi_rff(
+				.din(single_ecc_error_hi_any),
+				.dout(single_ecc_error_hi_r),
+				.clk(lsu_c2_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdffe #(.WIDTH(pt[1382-:10])) sec_data_hi_rff(
+				.din(sec_data_hi_m[pt[1382-:10] - 1:0]),
+				.dout(sec_data_hi_r[pt[1382-:10] - 1:0]),
+				.en(lsu_single_ecc_error_m | clk_override),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+			rvdffe #(.WIDTH(pt[1382-:10])) sec_data_lo_rff(
+				.din(sec_data_lo_m[pt[1382-:10] - 1:0]),
+				.dout(sec_data_lo_r[pt[1382-:10] - 1:0]),
+				.en(lsu_single_ecc_error_m | clk_override),
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode)
+			);
+		end
+	endgenerate
+	assign dccm_wdata_lo_any[pt[1382-:10] - 1:0] = (ld_single_ecc_error_r_ff ? sec_data_lo_r_ff[pt[1382-:10] - 1:0] : (dma_dccm_wen ? dma_dccm_wdata_lo[pt[1382-:10] - 1:0] : stbuf_data_any[pt[1382-:10] - 1:0]));
+	assign dccm_wdata_hi_any[pt[1382-:10] - 1:0] = (ld_single_ecc_error_r_ff ? sec_data_hi_r_ff[pt[1382-:10] - 1:0] : (dma_dccm_wen ? dma_dccm_wdata_hi[pt[1382-:10] - 1:0] : 32'h00000000));
+	assign sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0] = dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0];
+	assign sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0];
+	assign stbuf_ecc_any[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0];
+	assign dma_dccm_wdata_ecc_hi[pt[1372-:7] - 1:0] = dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0];
+	assign dma_dccm_wdata_ecc_lo[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0];
+	generate
+		if (pt[1365-:5] == 1) begin : Gen_dccm_enable
+			rvecc_decode lsu_ecc_decode_hi(
+				.en(is_ldst_hi_any),
+				.sed_ded(1'b0),
+				.din(dccm_rdata_hi_any[pt[1382-:10] - 1:0]),
+				.ecc_in(dccm_data_ecc_hi_any[pt[1372-:7] - 1:0]),
+				.dout(sec_data_hi_any[pt[1382-:10] - 1:0]),
+				.ecc_out(ecc_out_hi_nc[6:0]),
+				.single_ecc_error(single_ecc_error_hi_any),
+				.double_ecc_error(double_ecc_error_hi_any)
+			);
+			rvecc_decode lsu_ecc_decode_lo(
+				.en(is_ldst_lo_any),
+				.sed_ded(1'b0),
+				.din(dccm_rdata_lo_any[pt[1382-:10] - 1:0]),
+				.ecc_in(dccm_data_ecc_lo_any[pt[1372-:7] - 1:0]),
+				.dout(sec_data_lo_any[pt[1382-:10] - 1:0]),
+				.ecc_out(ecc_out_lo_nc[6:0]),
+				.single_ecc_error(single_ecc_error_lo_any),
+				.double_ecc_error(double_ecc_error_lo_any)
+			);
+			rvecc_encode lsu_ecc_encode_hi(
+				.din(dccm_wdata_hi_any[pt[1382-:10] - 1:0]),
+				.ecc_out(dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0])
+			);
+			rvecc_encode lsu_ecc_encode_lo(
+				.din(dccm_wdata_lo_any[pt[1382-:10] - 1:0]),
+				.ecc_out(dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0])
+			);
+		end
+		else begin : Gen_dccm_disable
+			assign sec_data_hi_any[pt[1382-:10] - 1:0] = {pt[1382-:10] {1'sb0}};
+			assign sec_data_lo_any[pt[1382-:10] - 1:0] = {pt[1382-:10] {1'sb0}};
+			assign single_ecc_error_hi_any = 1'b0;
+			assign double_ecc_error_hi_any = 1'b0;
+			assign single_ecc_error_lo_any = 1'b0;
+			assign double_ecc_error_lo_any = 1'b0;
+		end
+	endgenerate
+	rvdffe #(.WIDTH(pt[1382-:10])) sec_data_hi_rplus1ff(
+		.din(sec_data_hi_r[pt[1382-:10] - 1:0]),
+		.dout(sec_data_hi_r_ff[pt[1382-:10] - 1:0]),
+		.en(ld_single_ecc_error_r | clk_override),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+	rvdffe #(.WIDTH(pt[1382-:10])) sec_data_lo_rplus1ff(
+		.din(sec_data_lo_r[pt[1382-:10] - 1:0]),
+		.dout(sec_data_lo_r_ff[pt[1382-:10] - 1:0]),
+		.en(ld_single_ecc_error_r | clk_override),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode)
+	);
+endmodule
+module eb1_lsu_lsc_ctl (
+	rst_l,
+	clk_override,
+	clk,
+	lsu_c1_m_clk,
+	lsu_c1_r_clk,
+	lsu_c2_m_clk,
+	lsu_c2_r_clk,
+	lsu_store_c1_m_clk,
+	lsu_ld_data_r,
+	lsu_ld_data_corr_r,
+	lsu_single_ecc_error_r,
+	lsu_double_ecc_error_r,
+	lsu_ld_data_m,
+	lsu_single_ecc_error_m,
+	lsu_double_ecc_error_m,
+	flush_m_up,
+	flush_r,
+	ldst_dual_d,
+	ldst_dual_m,
+	ldst_dual_r,
+	exu_lsu_rs1_d,
+	exu_lsu_rs2_d,
+	lsu_p,
+	dec_lsu_valid_raw_d,
+	dec_lsu_offset_d,
+	picm_mask_data_m,
+	bus_read_data_m,
+	lsu_result_m,
+	lsu_result_corr_r,
+	lsu_addr_d,
+	lsu_addr_m,
+	lsu_addr_r,
+	end_addr_d,
+	end_addr_m,
+	end_addr_r,
+	store_data_m,
+	dec_tlu_mrac_ff,
+	lsu_exc_m,
+	is_sideeffects_m,
+	lsu_commit_r,
+	lsu_single_ecc_error_incr,
+	lsu_error_pkt_r,
+	lsu_fir_addr,
+	lsu_fir_error,
+	addr_in_dccm_d,
+	addr_in_dccm_m,
+	addr_in_dccm_r,
+	addr_in_pic_d,
+	addr_in_pic_m,
+	addr_in_pic_r,
+	addr_external_m,
+	dma_dccm_req,
+	dma_mem_addr,
+	dma_mem_sz,
+	dma_mem_write,
+	dma_mem_wdata,
+	lsu_pkt_d,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire rst_l;
+	input wire clk_override;
+	input wire clk;
+	input wire lsu_c1_m_clk;
+	input wire lsu_c1_r_clk;
+	input wire lsu_c2_m_clk;
+	input wire lsu_c2_r_clk;
+	input wire lsu_store_c1_m_clk;
+	input wire [31:0] lsu_ld_data_r;
+	input wire [31:0] lsu_ld_data_corr_r;
+	input wire lsu_single_ecc_error_r;
+	input wire lsu_double_ecc_error_r;
+	input wire [31:0] lsu_ld_data_m;
+	input wire lsu_single_ecc_error_m;
+	input wire lsu_double_ecc_error_m;
+	input wire flush_m_up;
+	input wire flush_r;
+	input wire ldst_dual_d;
+	input wire ldst_dual_m;
+	input wire ldst_dual_r;
+	input wire [31:0] exu_lsu_rs1_d;
+	input wire [31:0] exu_lsu_rs2_d;
+	input wire [13:0] lsu_p;
+	input wire dec_lsu_valid_raw_d;
+	input wire [11:0] dec_lsu_offset_d;
+	input wire [31:0] picm_mask_data_m;
+	input wire [31:0] bus_read_data_m;
+	output wire [31:0] lsu_result_m;
+	output wire [31:0] lsu_result_corr_r;
+	output wire [31:0] lsu_addr_d;
+	output wire [31:0] lsu_addr_m;
+	output wire [31:0] lsu_addr_r;
+	output wire [31:0] end_addr_d;
+	output wire [31:0] end_addr_m;
+	output wire [31:0] end_addr_r;
+	output wire [31:0] store_data_m;
+	input wire [31:0] dec_tlu_mrac_ff;
+	output wire lsu_exc_m;
+	output wire is_sideeffects_m;
+	output wire lsu_commit_r;
+	output wire lsu_single_ecc_error_incr;
+	output wire [39:0] lsu_error_pkt_r;
+	output wire [31:1] lsu_fir_addr;
+	output wire [1:0] lsu_fir_error;
+	output wire addr_in_dccm_d;
+	output wire addr_in_dccm_m;
+	output wire addr_in_dccm_r;
+	output wire addr_in_pic_d;
+	output wire addr_in_pic_m;
+	output wire addr_in_pic_r;
+	output wire addr_external_m;
+	input wire dma_dccm_req;
+	input wire [31:0] dma_mem_addr;
+	input wire [2:0] dma_mem_sz;
+	input wire dma_mem_write;
+	input wire [63:0] dma_mem_wdata;
+	output reg [13:0] lsu_pkt_d;
+	output wire [13:0] lsu_pkt_m;
+	output wire [13:0] lsu_pkt_r;
+	input wire scan_mode;
+	wire [31:3] end_addr_pre_m;
+	wire [31:3] end_addr_pre_r;
+	wire [31:0] full_addr_d;
+	wire [31:0] full_end_addr_d;
+	wire [31:0] lsu_rs1_d;
+	wire [11:0] lsu_offset_d;
+	wire [31:0] rs1_d;
+	wire [11:0] offset_d;
+	wire [12:0] end_addr_offset_d;
+	wire [2:0] addr_offset_d;
+	wire [63:0] dma_mem_wdata_shifted;
+	wire addr_external_d;
+	wire addr_external_r;
+	wire access_fault_d;
+	wire misaligned_fault_d;
+	wire access_fault_m;
+	wire misaligned_fault_m;
+	wire fir_dccm_access_error_d;
+	wire fir_nondccm_access_error_d;
+	wire fir_dccm_access_error_m;
+	wire fir_nondccm_access_error_m;
+	wire [3:0] exc_mscause_d;
+	wire [3:0] exc_mscause_m;
+	wire [31:0] rs1_d_raw;
+	wire [31:0] store_data_d;
+	wire [31:0] store_data_pre_m;
+	wire [31:0] store_data_m_in;
+	wire [31:0] bus_read_data_r;
+	reg [13:0] dma_pkt_d;
+	reg [13:0] lsu_pkt_m_in;
+	reg [13:0] lsu_pkt_r_in;
+	wire [39:0] lsu_error_pkt_m;
+	assign lsu_rs1_d[31:0] = (dec_lsu_valid_raw_d ? exu_lsu_rs1_d[31:0] : dma_mem_addr[31:0]);
+	assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & {12 {dec_lsu_valid_raw_d}};
+	assign rs1_d_raw[31:0] = lsu_rs1_d[31:0];
+	assign offset_d[11:0] = lsu_offset_d[11:0];
+	assign rs1_d[31:0] = (lsu_pkt_d[2] ? lsu_result_m[31:0] : rs1_d_raw[31:0]);
+	rvlsadder lsadder(
+		.rs1(rs1_d[31:0]),
+		.offset(offset_d[11:0]),
+		.dout(full_addr_d[31:0])
+	);
+	eb1_lsu_addrcheck #(.pt(pt)) addrcheck(
+		.start_addr_d(full_addr_d[31:0]),
+		.end_addr_d(full_end_addr_d[31:0]),
+		.rs1_region_d(rs1_d[31:28]),
+		.lsu_c2_m_clk(lsu_c2_m_clk),
+		.rst_l(rst_l),
+		.lsu_pkt_d(lsu_pkt_d),
+		.dec_tlu_mrac_ff(dec_tlu_mrac_ff),
+		.rs1_d(rs1_d),
+		.is_sideeffects_m(is_sideeffects_m),
+		.addr_in_dccm_d(addr_in_dccm_d),
+		.addr_in_pic_d(addr_in_pic_d),
+		.addr_external_d(addr_external_d),
+		.access_fault_d(access_fault_d),
+		.misaligned_fault_d(misaligned_fault_d),
+		.exc_mscause_d(exc_mscause_d),
+		.fir_dccm_access_error_d(fir_dccm_access_error_d),
+		.fir_nondccm_access_error_d(fir_nondccm_access_error_d),
+		.scan_mode(scan_mode)
+	);
+	assign addr_offset_d[2:0] = (({3 {lsu_pkt_d[10]}} & 3'b001) | ({3 {lsu_pkt_d[9]}} & 3'b011)) | ({3 {lsu_pkt_d[8]}} & 3'b111);
+	assign end_addr_offset_d[12:0] = {offset_d[11], offset_d[11:0]} + {9'b000000000, addr_offset_d[2:0]};
+	assign full_end_addr_d[31:0] = rs1_d[31:0] + {{19 {end_addr_offset_d[12]}}, end_addr_offset_d[12:0]};
+	assign end_addr_d[31:0] = full_end_addr_d[31:0];
+	assign lsu_exc_m = access_fault_m | misaligned_fault_m;
+	assign lsu_single_ecc_error_incr = ((lsu_single_ecc_error_r & ~lsu_double_ecc_error_r) & (lsu_commit_r | lsu_pkt_r[4])) & lsu_pkt_r[0];
+	generate
+		if (pt[202-:5] == 1) begin : L2U_Plus1_1
+			wire access_fault_r;
+			wire misaligned_fault_r;
+			wire [3:0] exc_mscause_r;
+			wire fir_dccm_access_error_r;
+			wire fir_nondccm_access_error_r;
+			assign lsu_error_pkt_r[0] = ((((access_fault_r | misaligned_fault_r) | lsu_double_ecc_error_r) & lsu_pkt_r[0]) & ~lsu_pkt_r[4]) & ~lsu_pkt_r[13];
+			assign lsu_error_pkt_r[1] = (lsu_single_ecc_error_r & ~lsu_error_pkt_r[0]) & ~lsu_pkt_r[4];
+			assign lsu_error_pkt_r[39] = lsu_pkt_r[6];
+			assign lsu_error_pkt_r[38] = ~misaligned_fault_r;
+			assign lsu_error_pkt_r[37:34] = ((lsu_double_ecc_error_r & ~misaligned_fault_r) & ~access_fault_r ? 4'h1 : exc_mscause_r[3:0]);
+			assign lsu_error_pkt_r[33:2] = lsu_addr_r[31:0];
+			assign lsu_fir_error[1:0] = (fir_nondccm_access_error_r ? 2'b11 : (fir_dccm_access_error_r ? 2'b10 : (lsu_pkt_r[13] & lsu_double_ecc_error_r ? 2'b01 : 2'b00)));
+			rvdff #(.WIDTH(1)) access_fault_rff(
+				.din(access_fault_m),
+				.dout(access_fault_r),
+				.clk(lsu_c1_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) misaligned_fault_rff(
+				.din(misaligned_fault_m),
+				.dout(misaligned_fault_r),
+				.clk(lsu_c1_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(4)) exc_mscause_rff(
+				.din(exc_mscause_m[3:0]),
+				.dout(exc_mscause_r[3:0]),
+				.clk(lsu_c1_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) fir_dccm_access_error_mff(
+				.din(fir_dccm_access_error_m),
+				.dout(fir_dccm_access_error_r),
+				.clk(lsu_c1_r_clk),
+				.rst_l(rst_l)
+			);
+			rvdff #(.WIDTH(1)) fir_nondccm_access_error_mff(
+				.din(fir_nondccm_access_error_m),
+				.dout(fir_nondccm_access_error_r),
+				.clk(lsu_c1_r_clk),
+				.rst_l(rst_l)
+			);
+		end
+		else begin : L2U_Plus1_0
+			wire [1:0] lsu_fir_error_m;
+			assign lsu_error_pkt_m[0] = (((((access_fault_m | misaligned_fault_m) | lsu_double_ecc_error_m) & lsu_pkt_m[0]) & ~lsu_pkt_m[4]) & ~lsu_pkt_m[13]) & ~flush_m_up;
+			assign lsu_error_pkt_m[1] = (lsu_single_ecc_error_m & ~lsu_error_pkt_m[0]) & ~lsu_pkt_m[4];
+			assign lsu_error_pkt_m[39] = lsu_pkt_m[6];
+			assign lsu_error_pkt_m[38] = ~misaligned_fault_m;
+			assign lsu_error_pkt_m[37:34] = ((lsu_double_ecc_error_m & ~misaligned_fault_m) & ~access_fault_m ? 4'h1 : exc_mscause_m[3:0]);
+			assign lsu_error_pkt_m[33:2] = lsu_addr_m[31:0];
+			assign lsu_fir_error_m[1:0] = (fir_nondccm_access_error_m ? 2'b11 : (fir_dccm_access_error_m ? 2'b10 : (lsu_pkt_m[13] & lsu_double_ecc_error_m ? 2'b01 : 2'b00)));
+			rvdff #(.WIDTH(1)) lsu_exc_valid_rff(
+				.rst_l(rst_l),
+				.din(lsu_error_pkt_m[0]),
+				.dout(lsu_error_pkt_r[0]),
+				.clk(lsu_c2_r_clk)
+			);
+			rvdff #(.WIDTH(1)) lsu_single_ecc_error_rff(
+				.rst_l(rst_l),
+				.din(lsu_error_pkt_m[1]),
+				.dout(lsu_error_pkt_r[1]),
+				.clk(lsu_c2_r_clk)
+			);
+			rvdffe #(.WIDTH(38)) lsu_error_pkt_rff(
+				.clk(clk),
+				.rst_l(rst_l),
+				.scan_mode(scan_mode),
+				.din(lsu_error_pkt_m[39:2]),
+				.dout(lsu_error_pkt_r[39:2]),
+				.en((lsu_error_pkt_m[0] | lsu_error_pkt_m[1]) | clk_override)
+			);
+			rvdff #(.WIDTH(2)) lsu_fir_error_rff(
+				.rst_l(rst_l),
+				.din(lsu_fir_error_m[1:0]),
+				.dout(lsu_fir_error[1:0]),
+				.clk(lsu_c2_r_clk)
+			);
+		end
+	endgenerate
+	always @(*) begin
+		dma_pkt_d = {14 {1'sb0}};
+		dma_pkt_d[0] = dma_dccm_req;
+		dma_pkt_d[4] = 1'b1;
+		dma_pkt_d[6] = dma_mem_write;
+		dma_pkt_d[7] = ~dma_mem_write;
+		dma_pkt_d[11] = dma_mem_sz[2:0] == 3'b000;
+		dma_pkt_d[10] = dma_mem_sz[2:0] == 3'b001;
+		dma_pkt_d[9] = dma_mem_sz[2:0] == 3'b010;
+		dma_pkt_d[8] = dma_mem_sz[2:0] == 3'b011;
+	end
+	always @(*) begin
+		lsu_pkt_d = (dec_lsu_valid_raw_d ? lsu_p : dma_pkt_d);
+		lsu_pkt_m_in = lsu_pkt_d;
+		lsu_pkt_r_in = lsu_pkt_m;
+		lsu_pkt_d[0] = (lsu_p[0] & ~(flush_m_up & ~lsu_p[13])) | dma_dccm_req;
+		lsu_pkt_m_in[0] = lsu_pkt_d[0] & ~(flush_m_up & ~lsu_pkt_d[4]);
+		lsu_pkt_r_in[0] = lsu_pkt_m[0] & ~(flush_m_up & ~lsu_pkt_m[4]);
+	end
+	rvdff #(.WIDTH(1)) lsu_pkt_vldmff(
+		.rst_l(rst_l),
+		.din(lsu_pkt_m_in[0]),
+		.dout(lsu_pkt_m[0]),
+		.clk(lsu_c2_m_clk)
+	);
+	rvdff #(.WIDTH(1)) lsu_pkt_vldrff(
+		.rst_l(rst_l),
+		.din(lsu_pkt_r_in[0]),
+		.dout(lsu_pkt_r[0]),
+		.clk(lsu_c2_r_clk)
+	);
+	rvdff #(.WIDTH(13)) lsu_pkt_mff(
+		.rst_l(rst_l),
+		.din(lsu_pkt_m_in[13:1]),
+		.dout(lsu_pkt_m[13:1]),
+		.clk(lsu_c1_m_clk)
+	);
+	rvdff #(.WIDTH(13)) lsu_pkt_rff(
+		.rst_l(rst_l),
+		.din(lsu_pkt_r_in[13:1]),
+		.dout(lsu_pkt_r[13:1]),
+		.clk(lsu_c1_r_clk)
+	);
+	generate
+		if (pt[202-:5] == 1) begin : L2U1_Plus1_1
+			wire [31:0] lsu_ld_datafn_r;
+			wire [31:0] lsu_ld_datafn_corr_r;
+			assign lsu_ld_datafn_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_r[31:0]);
+			assign lsu_ld_datafn_corr_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0]);
+			assign lsu_result_m[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_r[15]}}, lsu_ld_datafn_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_r[31:0]);
+			assign lsu_result_corr_r[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_corr_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_corr_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_corr_r[15]}}, lsu_ld_datafn_corr_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_corr_r[31:0]);
+		end
+		else begin : L2U1_Plus1_0
+			wire [31:0] lsu_ld_datafn_m;
+			wire [31:0] lsu_ld_datafn_corr_r;
+			assign lsu_ld_datafn_m[31:0] = (addr_external_m ? bus_read_data_m[31:0] : lsu_ld_data_m[31:0]);
+			assign lsu_ld_datafn_corr_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0]);
+			assign lsu_result_m[31:0] = (((({32 {lsu_pkt_m[5] & lsu_pkt_m[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_m[7:0]}) | ({32 {lsu_pkt_m[5] & lsu_pkt_m[10]}} & {16'b0000000000000000, lsu_ld_datafn_m[15:0]})) | ({32 {~lsu_pkt_m[5] & lsu_pkt_m[11]}} & {{24 {lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]})) | ({32 {~lsu_pkt_m[5] & lsu_pkt_m[10]}} & {{16 {lsu_ld_datafn_m[15]}}, lsu_ld_datafn_m[15:0]})) | ({32 {lsu_pkt_m[9]}} & lsu_ld_datafn_m[31:0]);
+			assign lsu_result_corr_r[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_corr_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_corr_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_corr_r[15]}}, lsu_ld_datafn_corr_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_corr_r[31:0]);
+		end
+	endgenerate
+	assign lsu_fir_addr[31:1] = lsu_ld_data_corr_r[31:1];
+	assign lsu_addr_d[31:0] = full_addr_d[31:0];
+	assign lsu_commit_r = ((lsu_pkt_r[0] & (lsu_pkt_r[6] | lsu_pkt_r[7])) & ~flush_r) & ~lsu_pkt_r[4];
+	assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000};
+	assign store_data_d[31:0] = (dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]);
+	assign store_data_m_in[31:0] = (lsu_pkt_d[3] ? lsu_result_m[31:0] : store_data_d[31:0]);
+	assign store_data_m[31:0] = (picm_mask_data_m[31:0] | {32 {~addr_in_pic_m}}) & (lsu_pkt_m[1] ? lsu_result_m[31:0] : store_data_pre_m[31:0]);
+	rvdff #(.WIDTH(32)) sdmff(
+		.rst_l(rst_l),
+		.din(store_data_m_in[31:0]),
+		.dout(store_data_pre_m[31:0]),
+		.clk(lsu_store_c1_m_clk)
+	);
+	rvdff #(.WIDTH(32)) samff(
+		.rst_l(rst_l),
+		.din(lsu_addr_d[31:0]),
+		.dout(lsu_addr_m[31:0]),
+		.clk(lsu_c1_m_clk)
+	);
+	rvdff #(.WIDTH(32)) sarff(
+		.rst_l(rst_l),
+		.din(lsu_addr_m[31:0]),
+		.dout(lsu_addr_r[31:0]),
+		.clk(lsu_c1_r_clk)
+	);
+	assign end_addr_m[31:3] = (ldst_dual_m ? end_addr_pre_m[31:3] : lsu_addr_m[31:3]);
+	assign end_addr_r[31:3] = (ldst_dual_r ? end_addr_pre_r[31:3] : lsu_addr_r[31:3]);
+	rvdffe #(.WIDTH(29)) end_addr_hi_mff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(end_addr_d[31:3]),
+		.dout(end_addr_pre_m[31:3]),
+		.en((lsu_pkt_d[0] & ldst_dual_d) | clk_override)
+	);
+	rvdffe #(.WIDTH(29)) end_addr_hi_rff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(end_addr_m[31:3]),
+		.dout(end_addr_pre_r[31:3]),
+		.en((lsu_pkt_m[0] & ldst_dual_m) | clk_override)
+	);
+	rvdff #(.WIDTH(3)) end_addr_lo_mff(
+		.rst_l(rst_l),
+		.din(end_addr_d[2:0]),
+		.dout(end_addr_m[2:0]),
+		.clk(lsu_c1_m_clk)
+	);
+	rvdff #(.WIDTH(3)) end_addr_lo_rff(
+		.rst_l(rst_l),
+		.din(end_addr_m[2:0]),
+		.dout(end_addr_r[2:0]),
+		.clk(lsu_c1_r_clk)
+	);
+	rvdff #(.WIDTH(1)) addr_in_dccm_mff(
+		.din(addr_in_dccm_d),
+		.dout(addr_in_dccm_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) addr_in_dccm_rff(
+		.din(addr_in_dccm_m),
+		.dout(addr_in_dccm_r),
+		.clk(lsu_c1_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) addr_in_pic_mff(
+		.din(addr_in_pic_d),
+		.dout(addr_in_pic_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) addr_in_pic_rff(
+		.din(addr_in_pic_m),
+		.dout(addr_in_pic_r),
+		.clk(lsu_c1_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) addr_external_mff(
+		.din(addr_external_d),
+		.dout(addr_external_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) addr_external_rff(
+		.din(addr_external_m),
+		.dout(addr_external_r),
+		.clk(lsu_c1_r_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) access_fault_mff(
+		.din(access_fault_d),
+		.dout(access_fault_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) misaligned_fault_mff(
+		.din(misaligned_fault_d),
+		.dout(misaligned_fault_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(4)) exc_mscause_mff(
+		.din(exc_mscause_d[3:0]),
+		.dout(exc_mscause_m[3:0]),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) fir_dccm_access_error_mff(
+		.din(fir_dccm_access_error_d),
+		.dout(fir_dccm_access_error_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdff #(.WIDTH(1)) fir_nondccm_access_error_mff(
+		.din(fir_nondccm_access_error_d),
+		.dout(fir_nondccm_access_error_m),
+		.clk(lsu_c1_m_clk),
+		.rst_l(rst_l)
+	);
+	rvdffe #(.WIDTH(32)) bus_read_data_r_ff(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(bus_read_data_m[31:0]),
+		.dout(bus_read_data_r[31:0]),
+		.en(addr_external_m | clk_override)
+	);
+endmodule
+module eb1_lsu_stbuf (
+	clk,
+	rst_l,
+	lsu_stbuf_c1_clk,
+	lsu_free_c2_clk,
+	store_stbuf_reqvld_r,
+	lsu_commit_r,
+	dec_lsu_valid_raw_d,
+	store_data_hi_r,
+	store_data_lo_r,
+	store_datafn_hi_r,
+	store_datafn_lo_r,
+	stbuf_reqvld_any,
+	stbuf_reqvld_flushed_any,
+	stbuf_addr_any,
+	stbuf_data_any,
+	lsu_stbuf_commit_any,
+	lsu_stbuf_full_any,
+	lsu_stbuf_empty_any,
+	ldst_stbuf_reqvld_r,
+	lsu_addr_d,
+	lsu_addr_m,
+	lsu_addr_r,
+	end_addr_d,
+	end_addr_m,
+	end_addr_r,
+	ldst_dual_d,
+	ldst_dual_m,
+	ldst_dual_r,
+	addr_in_dccm_m,
+	addr_in_dccm_r,
+	lsu_cmpen_m,
+	lsu_pkt_m,
+	lsu_pkt_r,
+	stbuf_fwddata_hi_m,
+	stbuf_fwddata_lo_m,
+	stbuf_fwdbyteen_hi_m,
+	stbuf_fwdbyteen_lo_m,
+	scan_mode
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire clk;
+	input wire rst_l;
+	input wire lsu_stbuf_c1_clk;
+	input wire lsu_free_c2_clk;
+	input wire store_stbuf_reqvld_r;
+	input wire lsu_commit_r;
+	input wire dec_lsu_valid_raw_d;
+	input wire [pt[1382-:10] - 1:0] store_data_hi_r;
+	input wire [pt[1382-:10] - 1:0] store_data_lo_r;
+	input wire [pt[1382-:10] - 1:0] store_datafn_hi_r;
+	input wire [pt[1382-:10] - 1:0] store_datafn_lo_r;
+	output wire stbuf_reqvld_any;
+	output wire stbuf_reqvld_flushed_any;
+	output wire [pt[157-:9] - 1:0] stbuf_addr_any;
+	output wire [pt[1382-:10] - 1:0] stbuf_data_any;
+	input wire lsu_stbuf_commit_any;
+	output wire lsu_stbuf_full_any;
+	output wire lsu_stbuf_empty_any;
+	output wire ldst_stbuf_reqvld_r;
+	input wire [pt[157-:9] - 1:0] lsu_addr_d;
+	input wire [31:0] lsu_addr_m;
+	input wire [31:0] lsu_addr_r;
+	input wire [pt[157-:9] - 1:0] end_addr_d;
+	input wire [31:0] end_addr_m;
+	input wire [31:0] end_addr_r;
+	input wire ldst_dual_d;
+	input wire ldst_dual_m;
+	input wire ldst_dual_r;
+	input wire addr_in_dccm_m;
+	input wire addr_in_dccm_r;
+	input wire lsu_cmpen_m;
+	input wire [13:0] lsu_pkt_m;
+	input wire [13:0] lsu_pkt_r;
+	output wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m;
+	output wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m;
+	output wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m;
+	output wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m;
+	input wire scan_mode;
+	localparam DEPTH = pt[148-:8];
+	localparam DATA_WIDTH = pt[1382-:10];
+	localparam BYTE_WIDTH = pt[1389-:7];
+	localparam DEPTH_LOG2 = $clog2(DEPTH);
+	wire [DEPTH - 1:0] stbuf_vld;
+	wire [DEPTH - 1:0] stbuf_dma_kill;
+	wire [(DEPTH * pt[157-:9]) - 1:0] stbuf_addr;
+	wire [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_byteen;
+	wire [(DEPTH * DATA_WIDTH) - 1:0] stbuf_data;
+	wire [DEPTH - 1:0] sel_lo;
+	wire [DEPTH - 1:0] stbuf_wr_en;
+	reg [DEPTH - 1:0] stbuf_dma_kill_en;
+	wire [DEPTH - 1:0] stbuf_reset;
+	wire [(DEPTH * pt[157-:9]) - 1:0] stbuf_addrin;
+	wire [(DEPTH * DATA_WIDTH) - 1:0] stbuf_datain;
+	wire [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_byteenin;
+	wire [7:0] store_byteen_ext_r;
+	wire [BYTE_WIDTH - 1:0] store_byteen_hi_r;
+	wire [BYTE_WIDTH - 1:0] store_byteen_lo_r;
+	wire WrPtrEn;
+	wire RdPtrEn;
+	wire [DEPTH_LOG2 - 1:0] WrPtr;
+	wire [DEPTH_LOG2 - 1:0] RdPtr;
+	wire [DEPTH_LOG2 - 1:0] NxtWrPtr;
+	wire [DEPTH_LOG2 - 1:0] NxtRdPtr;
+	wire [DEPTH_LOG2 - 1:0] WrPtrPlus1;
+	wire [DEPTH_LOG2 - 1:0] WrPtrPlus2;
+	wire [DEPTH_LOG2 - 1:0] RdPtrPlus1;
+	wire dual_stbuf_write_r;
+	wire isdccmst_m;
+	wire isdccmst_r;
+	reg [3:0] stbuf_numvld_any;
+	wire [3:0] stbuf_specvld_any;
+	wire [1:0] stbuf_specvld_m;
+	wire [1:0] stbuf_specvld_r;
+	wire [pt[157-:9] - 1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m;
+	wire [pt[157-:9] - 1:$clog2(BYTE_WIDTH)] cmpaddr_lo_m;
+	reg [DEPTH - 1:0] stbuf_match_hi;
+	reg [DEPTH - 1:0] stbuf_match_lo;
+	reg [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_fwdbyteenvec_hi;
+	reg [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_fwdbyteenvec_lo;
+	reg [DATA_WIDTH - 1:0] stbuf_fwddata_hi_pre_m;
+	reg [DATA_WIDTH - 1:0] stbuf_fwddata_lo_pre_m;
+	reg [BYTE_WIDTH - 1:0] stbuf_fwdbyteen_hi_pre_m;
+	reg [BYTE_WIDTH - 1:0] stbuf_fwdbyteen_lo_pre_m;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo_lo;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi_lo;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo_hi;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi_hi;
+	wire ld_addr_rhit_lo_lo;
+	wire ld_addr_rhit_hi_lo;
+	wire ld_addr_rhit_lo_hi;
+	wire ld_addr_rhit_hi_hi;
+	wire [BYTE_WIDTH - 1:0] ld_byte_hit_lo;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo;
+	wire [BYTE_WIDTH - 1:0] ld_byte_hit_hi;
+	wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi;
+	wire [BYTE_WIDTH - 1:0] ldst_byteen_hi_r;
+	wire [BYTE_WIDTH - 1:0] ldst_byteen_lo_r;
+	wire [7:0] ldst_byteen_r;
+	wire [7:0] ldst_byteen_ext_r;
+	wire [31:0] ld_fwddata_rpipe_lo;
+	wire [31:0] ld_fwddata_rpipe_hi;
+	wire [DEPTH - 1:0] store_matchvec_lo_r;
+	wire [DEPTH - 1:0] store_matchvec_hi_r;
+	wire store_coalesce_lo_r;
+	wire store_coalesce_hi_r;
+	assign store_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];
+	assign store_byteen_hi_r[BYTE_WIDTH - 1:0] = store_byteen_ext_r[7:4] & {4 {lsu_pkt_r[6]}};
+	assign store_byteen_lo_r[BYTE_WIDTH - 1:0] = store_byteen_ext_r[3:0] & {4 {lsu_pkt_r[6]}};
+	assign RdPtrPlus1[DEPTH_LOG2 - 1:0] = RdPtr[DEPTH_LOG2 - 1:0] + 1'b1;
+	assign WrPtrPlus1[DEPTH_LOG2 - 1:0] = WrPtr[DEPTH_LOG2 - 1:0] + 1'b1;
+	assign WrPtrPlus2[DEPTH_LOG2 - 1:0] = WrPtr[DEPTH_LOG2 - 1:0] + 2'b10;
+	assign dual_stbuf_write_r = ldst_dual_r & store_stbuf_reqvld_r;
+	assign ldst_stbuf_reqvld_r = (lsu_commit_r | lsu_pkt_r[4]) & store_stbuf_reqvld_r;
+	generate
+		genvar i;
+		for (i = 0; i < DEPTH; i = i + 1) begin : FindMatchEntry
+			assign store_matchvec_lo_r[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == lsu_addr_r[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & ~stbuf_reset[i];
+			assign store_matchvec_hi_r[i] = ((((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == end_addr_r[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & dual_stbuf_write_r) & ~stbuf_reset[i];
+		end
+	endgenerate
+	assign store_coalesce_lo_r = |store_matchvec_lo_r[DEPTH - 1:0];
+	assign store_coalesce_hi_r = |store_matchvec_hi_r[DEPTH - 1:0];
+	generate
+		if (pt[1365-:5] == 1) begin : Gen_dccm_enable
+			for (i = 0; i < DEPTH; i = i + 1) begin : GenStBuf
+				assign stbuf_wr_en[i] = ldst_stbuf_reqvld_r & ((((((i == WrPtr[DEPTH_LOG2 - 1:0]) & ~store_coalesce_lo_r) | (((i == WrPtr[DEPTH_LOG2 - 1:0]) & dual_stbuf_write_r) & ~store_coalesce_hi_r)) | (((i == WrPtrPlus1[DEPTH_LOG2 - 1:0]) & dual_stbuf_write_r) & ~(store_coalesce_lo_r | store_coalesce_hi_r))) | store_matchvec_lo_r[i]) | store_matchvec_hi_r[i]);
+				assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2 - 1:0]);
+				assign sel_lo[i] = (((~ldst_dual_r | store_stbuf_reqvld_r) & (i == WrPtr[DEPTH_LOG2 - 1:0])) & ~store_coalesce_lo_r) | store_matchvec_lo_r[i];
+				assign stbuf_addrin[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]] = (sel_lo[i] ? lsu_addr_r[pt[157-:9] - 1:0] : end_addr_r[pt[157-:9] - 1:0]);
+				assign stbuf_byteenin[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] = (sel_lo[i] ? stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] | store_byteen_lo_r[BYTE_WIDTH - 1:0] : stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] | store_byteen_hi_r[BYTE_WIDTH - 1:0]);
+				assign stbuf_datain[(i * DATA_WIDTH) + 7-:8] = (sel_lo[i] ? (~stbuf_byteen[i * BYTE_WIDTH] | store_byteen_lo_r[0] ? store_datafn_lo_r[7:0] : stbuf_data[(i * DATA_WIDTH) + 7-:8]) : (~stbuf_byteen[i * BYTE_WIDTH] | store_byteen_hi_r[0] ? store_datafn_hi_r[7:0] : stbuf_data[(i * DATA_WIDTH) + 7-:8]));
+				assign stbuf_datain[(i * DATA_WIDTH) + 15-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 1] | store_byteen_lo_r[1] ? store_datafn_lo_r[15:8] : stbuf_data[(i * DATA_WIDTH) + 15-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 1] | store_byteen_hi_r[1] ? store_datafn_hi_r[15:8] : stbuf_data[(i * DATA_WIDTH) + 15-:8]));
+				assign stbuf_datain[(i * DATA_WIDTH) + 23-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 2] | store_byteen_lo_r[2] ? store_datafn_lo_r[23:16] : stbuf_data[(i * DATA_WIDTH) + 23-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 2] | store_byteen_hi_r[2] ? store_datafn_hi_r[23:16] : stbuf_data[(i * DATA_WIDTH) + 23-:8]));
+				assign stbuf_datain[(i * DATA_WIDTH) + 31-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 3] | store_byteen_lo_r[3] ? store_datafn_lo_r[31:24] : stbuf_data[(i * DATA_WIDTH) + 31-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 3] | store_byteen_hi_r[3] ? store_datafn_hi_r[31:24] : stbuf_data[(i * DATA_WIDTH) + 31-:8]));
+				rvdffsc #(.WIDTH(1)) stbuf_vldff(
+					.din(1'b1),
+					.dout(stbuf_vld[i]),
+					.en(stbuf_wr_en[i]),
+					.clear(stbuf_reset[i]),
+					.clk(lsu_free_c2_clk),
+					.rst_l(rst_l)
+				);
+				rvdffsc #(.WIDTH(1)) stbuf_killff(
+					.din(1'b1),
+					.dout(stbuf_dma_kill[i]),
+					.en(stbuf_dma_kill_en[i]),
+					.clear(stbuf_reset[i]),
+					.clk(lsu_free_c2_clk),
+					.rst_l(rst_l)
+				);
+				rvdffe #(.WIDTH(pt[157-:9])) stbuf_addrff(
+					.din(stbuf_addrin[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]]),
+					.dout(stbuf_addr[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]]),
+					.en(stbuf_wr_en[i]),
+					.clk(clk),
+					.rst_l(rst_l),
+					.scan_mode(scan_mode)
+				);
+				rvdffsc #(.WIDTH(BYTE_WIDTH)) stbuf_byteenff(
+					.din(stbuf_byteenin[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH]),
+					.dout(stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH]),
+					.en(stbuf_wr_en[i]),
+					.clear(stbuf_reset[i]),
+					.clk(lsu_stbuf_c1_clk),
+					.rst_l(rst_l)
+				);
+				rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_dataff(
+					.din(stbuf_datain[(i * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH]),
+					.dout(stbuf_data[(i * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH]),
+					.en(stbuf_wr_en[i]),
+					.clk(clk),
+					.rst_l(rst_l),
+					.scan_mode(scan_mode)
+				);
+			end
+		end
+		else begin : Gen_dccm_disable
+			assign stbuf_wr_en[DEPTH - 1:0] = {DEPTH {1'sb0}};
+			assign stbuf_reset[DEPTH - 1:0] = {DEPTH {1'sb0}};
+			assign stbuf_vld[DEPTH - 1:0] = {DEPTH {1'sb0}};
+			assign stbuf_dma_kill[DEPTH - 1:0] = {DEPTH {1'sb0}};
+			assign stbuf_addr[pt[157-:9] * ((DEPTH - 1) - (DEPTH - 1))+:pt[157-:9] * DEPTH] = {pt[157-:9] * DEPTH {1'sb0}};
+			assign stbuf_byteen[BYTE_WIDTH * ((DEPTH - 1) - (DEPTH - 1))+:BYTE_WIDTH * DEPTH] = {BYTE_WIDTH * DEPTH {1'sb0}};
+			assign stbuf_data[DATA_WIDTH * ((DEPTH - 1) - (DEPTH - 1))+:DATA_WIDTH * DEPTH] = {DATA_WIDTH * DEPTH {1'sb0}};
+		end
+	endgenerate
+	assign stbuf_reqvld_flushed_any = stbuf_vld[RdPtr] & stbuf_dma_kill[RdPtr];
+	assign stbuf_reqvld_any = (stbuf_vld[RdPtr] & ~stbuf_dma_kill[RdPtr]) & ~(|stbuf_dma_kill_en[DEPTH - 1:0]);
+	assign stbuf_addr_any[pt[157-:9] - 1:0] = stbuf_addr[(RdPtr * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]];
+	assign stbuf_data_any[DATA_WIDTH - 1:0] = stbuf_data[(RdPtr * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH];
+	assign WrPtrEn = ((ldst_stbuf_reqvld_r & ~dual_stbuf_write_r) & ~(store_coalesce_hi_r | store_coalesce_lo_r)) | ((ldst_stbuf_reqvld_r & dual_stbuf_write_r) & ~(store_coalesce_hi_r & store_coalesce_lo_r));
+	assign NxtWrPtr[DEPTH_LOG2 - 1:0] = ((ldst_stbuf_reqvld_r & dual_stbuf_write_r) & ~(store_coalesce_hi_r | store_coalesce_lo_r) ? WrPtrPlus2[DEPTH_LOG2 - 1:0] : WrPtrPlus1[DEPTH_LOG2 - 1:0]);
+	assign RdPtrEn = lsu_stbuf_commit_any | stbuf_reqvld_flushed_any;
+	assign NxtRdPtr[DEPTH_LOG2 - 1:0] = RdPtrPlus1[DEPTH_LOG2 - 1:0];
+	always @(*) begin
+		stbuf_numvld_any[3:0] = {4 {1'sb0}};
+		begin : sv2v_autoblock_59
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				stbuf_numvld_any[3:0] = stbuf_numvld_any[3:0] + {3'b000, stbuf_vld[i]};
+		end
+	end
+	assign isdccmst_m = ((lsu_pkt_m[0] & lsu_pkt_m[6]) & addr_in_dccm_m) & ~lsu_pkt_m[4];
+	assign isdccmst_r = ((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_dccm_r) & ~lsu_pkt_r[4];
+	assign stbuf_specvld_m[1:0] = {1'b0, isdccmst_m} << (isdccmst_m & ldst_dual_m);
+	assign stbuf_specvld_r[1:0] = {1'b0, isdccmst_r} << (isdccmst_r & ldst_dual_r);
+	assign stbuf_specvld_any[3:0] = (stbuf_numvld_any[3:0] + {2'b00, stbuf_specvld_m[1:0]}) + {2'b00, stbuf_specvld_r[1:0]};
+	assign lsu_stbuf_full_any = (~ldst_dual_d & dec_lsu_valid_raw_d ? stbuf_specvld_any[3:0] >= DEPTH : stbuf_specvld_any[3:0] >= (DEPTH - 1));
+	assign lsu_stbuf_empty_any = stbuf_numvld_any[3:0] == 4'b0000;
+	assign cmpaddr_hi_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)] = end_addr_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)];
+	assign cmpaddr_lo_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)] = lsu_addr_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)];
+	always @(*) begin : GenLdFwd
+		stbuf_fwdbyteen_hi_pre_m[BYTE_WIDTH - 1:0] = {BYTE_WIDTH {1'sb0}};
+		stbuf_fwdbyteen_lo_pre_m[BYTE_WIDTH - 1:0] = {BYTE_WIDTH {1'sb0}};
+		begin : sv2v_autoblock_60
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					stbuf_match_hi[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == cmpaddr_hi_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & addr_in_dccm_m;
+					stbuf_match_lo[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == cmpaddr_lo_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & addr_in_dccm_m;
+					stbuf_dma_kill_en[i] = (((stbuf_match_hi[i] | stbuf_match_lo[i]) & lsu_pkt_m[0]) & lsu_pkt_m[4]) & lsu_pkt_m[6];
+					begin : sv2v_autoblock_61
+						reg signed [31:0] j;
+						for (j = 0; j < BYTE_WIDTH; j = j + 1)
+							begin
+								stbuf_fwdbyteenvec_hi[(i * BYTE_WIDTH) + j] = (stbuf_match_hi[i] & stbuf_byteen[(i * BYTE_WIDTH) + j]) & stbuf_vld[i];
+								stbuf_fwdbyteen_hi_pre_m[j] = stbuf_fwdbyteen_hi_pre_m[j] | stbuf_fwdbyteenvec_hi[(i * BYTE_WIDTH) + j];
+								stbuf_fwdbyteenvec_lo[(i * BYTE_WIDTH) + j] = (stbuf_match_lo[i] & stbuf_byteen[(i * BYTE_WIDTH) + j]) & stbuf_vld[i];
+								stbuf_fwdbyteen_lo_pre_m[j] = stbuf_fwdbyteen_lo_pre_m[j] | stbuf_fwdbyteenvec_lo[(i * BYTE_WIDTH) + j];
+							end
+					end
+				end
+		end
+	end
+	always @(*) begin : GenLdData
+		stbuf_fwddata_hi_pre_m[31:0] = {32 {1'sb0}};
+		stbuf_fwddata_lo_pre_m[31:0] = {32 {1'sb0}};
+		begin : sv2v_autoblock_62
+			reg signed [31:0] i;
+			for (i = 0; i < DEPTH; i = i + 1)
+				begin
+					stbuf_fwddata_hi_pre_m[31:0] = stbuf_fwddata_hi_pre_m[31:0] | ({32 {stbuf_match_hi[i]}} & stbuf_data[(i * DATA_WIDTH) + 31-:32]);
+					stbuf_fwddata_lo_pre_m[31:0] = stbuf_fwddata_lo_pre_m[31:0] | ({32 {stbuf_match_lo[i]}} & stbuf_data[(i * DATA_WIDTH) + 31-:32]);
+				end
+		end
+	end
+	assign ldst_byteen_r[7:0] = ((({8 {lsu_pkt_r[11]}} & 8'b00000001) | ({8 {lsu_pkt_r[10]}} & 8'b00000011)) | ({8 {lsu_pkt_r[9]}} & 8'b00001111)) | ({8 {lsu_pkt_r[8]}} & 8'b11111111);
+	assign ldst_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];
+	assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];
+	assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];
+	assign ld_addr_rhit_lo_lo = (((lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4];
+	assign ld_addr_rhit_lo_hi = (((end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4];
+	assign ld_addr_rhit_hi_lo = ((((lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]) & dual_stbuf_write_r;
+	assign ld_addr_rhit_hi_hi = ((((end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]) & dual_stbuf_write_r;
+	generate
+		for (i = 0; i < BYTE_WIDTH; i = i + 1) begin
+			assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i];
+			assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i];
+			assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i];
+			assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i];
+			assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
+			assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
+			assign ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]);
+			assign ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]);
+			assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
+			assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
+			assign stbuf_fwdbyteen_hi_m[i] = ld_byte_hit_hi[i] | stbuf_fwdbyteen_hi_pre_m[i];
+			assign stbuf_fwdbyteen_lo_m[i] = ld_byte_hit_lo[i] | stbuf_fwdbyteen_lo_pre_m[i];
+			assign stbuf_fwddata_lo_m[(8 * i) + 7:8 * i] = (ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] : stbuf_fwddata_lo_pre_m[(8 * i) + 7:8 * i]);
+			assign stbuf_fwddata_hi_m[(8 * i) + 7:8 * i] = (ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] : stbuf_fwddata_hi_pre_m[(8 * i) + 7:8 * i]);
+		end
+	endgenerate
+	rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff(
+		.din(NxtWrPtr[DEPTH_LOG2 - 1:0]),
+		.dout(WrPtr[DEPTH_LOG2 - 1:0]),
+		.en(WrPtrEn),
+		.clk(lsu_stbuf_c1_clk),
+		.rst_l(rst_l)
+	);
+	rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff(
+		.din(NxtRdPtr[DEPTH_LOG2 - 1:0]),
+		.dout(RdPtr[DEPTH_LOG2 - 1:0]),
+		.en(RdPtrEn),
+		.clk(lsu_stbuf_c1_clk),
+		.rst_l(rst_l)
+	);
+endmodule
+module eb1_lsu_trigger (
+	trigger_pkt_any,
+	lsu_pkt_m,
+	lsu_addr_m,
+	store_data_m,
+	lsu_trigger_match_m
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [151:0] trigger_pkt_any;
+	input wire [13:0] lsu_pkt_m;
+	input wire [31:0] lsu_addr_m;
+	input wire [31:0] store_data_m;
+	output wire [3:0] lsu_trigger_match_m;
+	reg trigger_enable;
+	wire [127:0] lsu_match_data;
+	wire [3:0] lsu_trigger_data_match;
+	wire [31:0] store_data_trigger_m;
+	wire [31:0] ldst_addr_trigger_m;
+	always @(*) begin
+		trigger_enable = 1'b0;
+		begin : sv2v_autoblock_63
+			reg signed [31:0] i;
+			for (i = 0; i < 4; i = i + 1)
+				trigger_enable = trigger_enable | trigger_pkt_any[(i * 38) + 32];
+		end
+	end
+	assign store_data_trigger_m[31:0] = {{16 {lsu_pkt_m[9]}} & store_data_m[31:16], {8 {lsu_pkt_m[10] | lsu_pkt_m[9]}} & store_data_m[15:8], store_data_m[7:0]} & {32 {trigger_enable}};
+	assign ldst_addr_trigger_m[31:0] = lsu_addr_m[31:0] & {32 {trigger_enable}};
+	generate
+		genvar i;
+		for (i = 0; i < 4; i = i + 1) begin
+			assign lsu_match_data[(i * 32) + 31-:32] = ({32 {~trigger_pkt_any[(i * 38) + 37]}} & ldst_addr_trigger_m[31:0]) | ({32 {trigger_pkt_any[(i * 38) + 37] & trigger_pkt_any[(i * 38) + 35]}} & store_data_trigger_m[31:0]);
+			rvmaskandmatch trigger_match(
+				.mask(trigger_pkt_any[(i * 38) + 31-:32]),
+				.data(lsu_match_data[(i * 32) + 31-:32]),
+				.masken(trigger_pkt_any[(i * 38) + 36]),
+				.match(lsu_trigger_data_match[i])
+			);
+			assign lsu_trigger_match_m[i] = (((lsu_pkt_m[0] & ~lsu_pkt_m[4]) & trigger_enable) & ((trigger_pkt_any[(i * 38) + 35] & lsu_pkt_m[6]) | ((trigger_pkt_any[(i * 38) + 34] & lsu_pkt_m[7]) & ~trigger_pkt_any[(i * 38) + 37]))) & lsu_trigger_data_match[i];
+		end
+	endgenerate
+endmodule
+module rvjtag_tap (
+	trst,
+	tck,
+	tms,
+	tdi,
+	tdo,
+	tdoEnable,
+	wr_data,
+	wr_addr,
+	wr_en,
+	rd_en,
+	rd_data,
+	rd_status,
+	dmi_reset,
+	dmi_hard_reset,
+	idle,
+	dmi_stat,
+	jtag_id,
+	version
+);
+	parameter AWIDTH = 7;
+	input trst;
+	input tck;
+	input tms;
+	input tdi;
+	output reg tdo;
+	output tdoEnable;
+	output [31:0] wr_data;
+	output [AWIDTH - 1:0] wr_addr;
+	output wr_en;
+	output rd_en;
+	input [31:0] rd_data;
+	input [1:0] rd_status;
+	output reg dmi_reset;
+	output reg dmi_hard_reset;
+	input [2:0] idle;
+	input [1:0] dmi_stat;
+	input [31:1] jtag_id;
+	input [3:0] version;
+	localparam USER_DR_LENGTH = AWIDTH + 34;
+	reg [USER_DR_LENGTH - 1:0] sr;
+	reg [USER_DR_LENGTH - 1:0] nsr;
+	reg [USER_DR_LENGTH - 1:0] dr;
+	reg [3:0] state;
+	reg [3:0] nstate;
+	reg [4:0] ir;
+	wire jtag_reset;
+	wire shift_dr;
+	wire pause_dr;
+	wire update_dr;
+	wire capture_dr;
+	wire shift_ir;
+	wire pause_ir;
+	wire update_ir;
+	wire capture_ir;
+	wire [1:0] dr_en;
+	wire devid_sel;
+	wire [5:0] abits;
+	assign abits = AWIDTH[5:0];
+	localparam TEST_LOGIC_RESET_STATE = 0;
+	localparam RUN_TEST_IDLE_STATE = 1;
+	localparam SELECT_DR_SCAN_STATE = 2;
+	localparam CAPTURE_DR_STATE = 3;
+	localparam SHIFT_DR_STATE = 4;
+	localparam EXIT1_DR_STATE = 5;
+	localparam PAUSE_DR_STATE = 6;
+	localparam EXIT2_DR_STATE = 7;
+	localparam UPDATE_DR_STATE = 8;
+	localparam SELECT_IR_SCAN_STATE = 9;
+	localparam CAPTURE_IR_STATE = 10;
+	localparam SHIFT_IR_STATE = 11;
+	localparam EXIT1_IR_STATE = 12;
+	localparam PAUSE_IR_STATE = 13;
+	localparam EXIT2_IR_STATE = 14;
+	localparam UPDATE_IR_STATE = 15;
+	always @(*) begin
+		nstate = state;
+		case (state)
+			TEST_LOGIC_RESET_STATE: nstate = (tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE);
+			RUN_TEST_IDLE_STATE: nstate = (tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE);
+			SELECT_DR_SCAN_STATE: nstate = (tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE);
+			CAPTURE_DR_STATE: nstate = (tms ? EXIT1_DR_STATE : SHIFT_DR_STATE);
+			SHIFT_DR_STATE: nstate = (tms ? EXIT1_DR_STATE : SHIFT_DR_STATE);
+			EXIT1_DR_STATE: nstate = (tms ? UPDATE_DR_STATE : PAUSE_DR_STATE);
+			PAUSE_DR_STATE: nstate = (tms ? EXIT2_DR_STATE : PAUSE_DR_STATE);
+			EXIT2_DR_STATE: nstate = (tms ? UPDATE_DR_STATE : SHIFT_DR_STATE);
+			UPDATE_DR_STATE: nstate = (tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE);
+			SELECT_IR_SCAN_STATE: nstate = (tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE);
+			CAPTURE_IR_STATE: nstate = (tms ? EXIT1_IR_STATE : SHIFT_IR_STATE);
+			SHIFT_IR_STATE: nstate = (tms ? EXIT1_IR_STATE : SHIFT_IR_STATE);
+			EXIT1_IR_STATE: nstate = (tms ? UPDATE_IR_STATE : PAUSE_IR_STATE);
+			PAUSE_IR_STATE: nstate = (tms ? EXIT2_IR_STATE : PAUSE_IR_STATE);
+			EXIT2_IR_STATE: nstate = (tms ? UPDATE_IR_STATE : SHIFT_IR_STATE);
+			UPDATE_IR_STATE: nstate = (tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE);
+			default: nstate = TEST_LOGIC_RESET_STATE;
+		endcase
+	end
+	always @(posedge tck or negedge trst)
+		if (!trst)
+			state <= TEST_LOGIC_RESET_STATE;
+		else
+			state <= nstate;
+	assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
+	assign shift_dr = state == SHIFT_DR_STATE;
+	assign pause_dr = state == PAUSE_DR_STATE;
+	assign update_dr = state == UPDATE_DR_STATE;
+	assign capture_dr = state == CAPTURE_DR_STATE;
+	assign shift_ir = state == SHIFT_IR_STATE;
+	assign pause_ir = state == PAUSE_IR_STATE;
+	assign update_ir = state == UPDATE_IR_STATE;
+	assign capture_ir = state == CAPTURE_IR_STATE;
+	assign tdoEnable = shift_dr | shift_ir;
+	always @(negedge tck or negedge trst)
+		if (!trst)
+			ir <= 5'b00001;
+		else if (jtag_reset)
+			ir <= 5'b00001;
+		else if (update_ir)
+			ir <= (sr[4:0] == {5 {1'sb0}} ? 5'h1f : sr[4:0]);
+	assign devid_sel = ir == 5'b00001;
+	assign dr_en[0] = ir == 5'b10000;
+	assign dr_en[1] = ir == 5'b10001;
+	always @(posedge tck or negedge trst)
+		if (!trst)
+			sr <= {USER_DR_LENGTH {1'sb0}};
+		else
+			sr <= nsr;
+	always @(*) begin
+		nsr = sr;
+		case (1)
+			shift_dr:
+				case (1)
+					dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH - 1:1]};
+					dr_en[0], devid_sel: nsr = {{USER_DR_LENGTH - 32 {1'b0}}, tdi, sr[31:1]};
+					default: nsr = {{USER_DR_LENGTH - 1 {1'b0}}, tdi};
+				endcase
+			capture_dr: begin
+				nsr[0] = 1'b0;
+				case (1)
+					dr_en[0]: nsr = {{USER_DR_LENGTH - 15 {1'b0}}, idle, dmi_stat, abits, version};
+					dr_en[1]: nsr = {{AWIDTH {1'b0}}, rd_data, rd_status};
+					devid_sel: nsr = {{USER_DR_LENGTH - 32 {1'b0}}, jtag_id, 1'b1};
+				endcase
+			end
+			shift_ir: nsr = {{USER_DR_LENGTH - 5 {1'b0}}, tdi, sr[4:1]};
+			capture_ir: nsr = {{USER_DR_LENGTH - 1 {1'b0}}, 1'b1};
+		endcase
+	end
+	always @(negedge tck) tdo <= sr[0];
+	always @(posedge tck or negedge trst)
+		if (!trst) begin
+			dmi_hard_reset <= 1'b0;
+			dmi_reset <= 1'b0;
+		end
+		else if (update_dr & dr_en[0]) begin
+			dmi_hard_reset <= sr[17];
+			dmi_reset <= sr[16];
+		end
+		else begin
+			dmi_hard_reset <= 1'b0;
+			dmi_reset <= 1'b0;
+		end
+	always @(posedge tck or negedge trst)
+		if (!trst)
+			dr <= {USER_DR_LENGTH {1'sb0}};
+		else if (update_dr & dr_en[1])
+			dr <= sr;
+		else
+			dr <= {dr[USER_DR_LENGTH - 1:2], 2'b00};
+	assign {wr_addr, wr_data, wr_en, rd_en} = dr;
+endmodule
+module eb1_btb_tag_hash (
+	pc,
+	hash
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1] pc;
+	output wire [pt[2139-:9] - 1:0] hash;
+	assign hash = {(pc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + 1] ^ pc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:(pt[2172-:9] + pt[2139-:9]) + 1]) ^ pc[pt[2172-:9] + pt[2139-:9]:pt[2172-:9] + 1]};
+endmodule
+module eb1_btb_tag_hash_fold (
+	pc,
+	hash
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1] pc;
+	output wire [pt[2139-:9] - 1:0] hash;
+	assign hash = {pc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:(pt[2172-:9] + pt[2139-:9]) + 1] ^ pc[pt[2172-:9] + pt[2139-:9]:pt[2172-:9] + 1]};
+endmodule
+module eb1_btb_addr_hash (
+	pc,
+	hash
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [pt[2079-:9]:pt[2106-:9]] pc;
+	output wire [pt[2172-:9]:pt[2163-:6]] hash;
+	generate
+		if (pt[2125-:5]) begin : fold2
+			assign hash[pt[2172-:9]:pt[2163-:6]] = pc[pt[2115-:9]:pt[2106-:9]] ^ pc[pt[2079-:9]:pt[2070-:9]];
+		end
+		else assign hash[pt[2172-:9]:pt[2163-:6]] = (pc[pt[2115-:9]:pt[2106-:9]] ^ pc[pt[2097-:9]:pt[2088-:9]]) ^ pc[pt[2079-:9]:pt[2070-:9]];
+	endgenerate
+endmodule
+module eb1_btb_ghr_hash (
+	hashin,
+	ghr,
+	hash
+);
+	function automatic [0:0] sv2v_cast_1;
+		input reg [0:0] inp;
+		sv2v_cast_1 = inp;
+	endfunction
+	parameter [2270:0] pt = {232'h0808040001c0400000000000010102000060800080103c12160802000c, sv2v_cast_1(4'h0), 5'h01, 5'h01, 6'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 7'h02, 9'h00c, 7'h04, 10'h020, 7'h07, 5'h01, 10'h027, 8'h08, 9'h004, 8'h0f, 36'h0f0040000, 14'h0004, 6'h02, 7'h03, 5'h01, 7'h05, 9'h001, 6'h02, 8'h01, 5'h01, 5'h01, 7'h01, 7'h03, 6'h03, 8'h08, 7'h02, 8'h05, 8'h03, 5'h01, 18'h00200, 7'h04, 11'h040, 5'h01, 5'h00, 11'h047, 9'h00c, 11'h040, 8'h08, 8'h02, 8'h02, 7'h02, 5'h00, 8'h06, 13'h0010, 7'h01, 5'h01, 17'h00080, 7'h06, 9'h00d, 8'h02, 8'h02, 5'h01, 7'h02, 9'h003, 9'h004, 9'h00c, 5'h01, 5'h00, 8'h08, 9'h004, 5'h01, 8'h0a, 36'h0affff000, 14'h0004, 5'h01, 6'h02, 8'h03, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 36'h000000000, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 5'h00, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 36'h0ffffffff, 5'h00, 5'h00, 5'h01, 6'h02, 8'h03, 9'h004, 7'h02, 9'h00c, 8'h04, 5'h00, 5'h00, 36'h0f00c0000, 9'h00f, 8'h01, 8'h0f, 13'h0020, 12'h01f, 13'h0020, 8'h08, 5'h01, 6'h02, 8'h01, 5'h01};
+	input wire [pt[2172-:9]:pt[2163-:6]] hashin;
+	input wire [pt[2236-:8] - 1:0] ghr;
+	output wire [pt[2270-:8]:pt[2262-:6]] hash;
+	generate
+		if (pt[2241-:5]) begin : ghrhash_cfg1
+			assign hash[pt[2270-:8]:pt[2262-:6]] = {ghr[pt[2236-:8] - 1:pt[2115-:9] - 1], hashin[pt[2115-:9]:2] ^ ghr[pt[2115-:9] - 2:0]};
+		end
+		else begin : ghrhash_cfg2
+			assign hash[pt[2270-:8]:pt[2262-:6]] = {hashin[pt[2236-:8] + 1:2] ^ ghr[pt[2236-:8] - 1:0]};
+		end
+	endgenerate
+endmodule
+module rvdff (
+	din,
+	clk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	output reg [WIDTH - 1:0] dout;
+	generate
+		if (SHORT == 1) begin
+			wire [WIDTH:1] sv2v_tmp_70387;
+			assign sv2v_tmp_70387 = din;
+			always @(*) dout = sv2v_tmp_70387;
+		end
+	endgenerate
+	always @(posedge clk or negedge rst_l)
+		if (rst_l == 0)
+			dout[WIDTH - 1:0] <= 0;
+		else
+			dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
+endmodule
+module rvdffs (
+	din,
+	en,
+	clk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire en;
+	input wire clk;
+	input wire rst_l;
+	output wire [WIDTH - 1:0] dout;
+	generate
+		if (SHORT == 1) begin : genblock
+			assign dout = din;
+		end
+		else begin : genblock
+			rvdff #(.WIDTH(WIDTH)) dffs(
+				.din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])),
+				.clk(clk),
+				.rst_l(rst_l),
+				.dout(dout)
+			);
+		end
+	endgenerate
+endmodule
+module rvdffsc (
+	din,
+	en,
+	clear,
+	clk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire en;
+	input wire clear;
+	input wire clk;
+	input wire rst_l;
+	output wire [WIDTH - 1:0] dout;
+	wire [WIDTH - 1:0] din_new;
+	generate
+		if (SHORT == 1) begin
+			assign dout = din;
+		end
+		else begin
+			assign din_new = {WIDTH {~clear}} & (en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0]);
+			rvdff #(.WIDTH(WIDTH)) dffsc(
+				.din(din_new[WIDTH - 1:0]),
+				.clk(clk),
+				.rst_l(rst_l),
+				.dout(dout)
+			);
+		end
+	endgenerate
+endmodule
+module rvdff_fpga (
+	din,
+	clk,
+	clken,
+	rawclk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire clken;
+	input wire rawclk;
+	input wire rst_l;
+	output wire [WIDTH - 1:0] dout;
+	generate
+		if (SHORT == 1) begin
+			assign dout = din;
+		end
+		else rvdff #(.WIDTH(WIDTH)) dff(
+			.din(din),
+			.clk(clk),
+			.rst_l(rst_l),
+			.dout(dout)
+		);
+	endgenerate
+endmodule
+module rvdffs_fpga (
+	din,
+	en,
+	clk,
+	clken,
+	rawclk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire en;
+	input wire clk;
+	input wire clken;
+	input wire rawclk;
+	input wire rst_l;
+	output wire [WIDTH - 1:0] dout;
+	generate
+		if (SHORT == 1) begin : genblock
+			assign dout = din;
+		end
+		else begin : genblock
+			rvdffs #(.WIDTH(WIDTH)) dffs(
+				.din(din),
+				.en(en),
+				.clk(clk),
+				.rst_l(rst_l),
+				.dout(dout)
+			);
+		end
+	endgenerate
+endmodule
+module rvdffsc_fpga (
+	din,
+	en,
+	clear,
+	clk,
+	clken,
+	rawclk,
+	rst_l,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire en;
+	input wire clear;
+	input wire clk;
+	input wire clken;
+	input wire rawclk;
+	input wire rst_l;
+	output wire [WIDTH - 1:0] dout;
+	wire [WIDTH - 1:0] din_new;
+	generate
+		if (SHORT == 1) begin
+			assign dout = din;
+		end
+		else rvdffsc #(.WIDTH(WIDTH)) dffsc(
+			.din(din),
+			.en(en),
+			.clear(clear),
+			.clk(clk),
+			.rst_l(rst_l),
+			.dout(dout)
+		);
+	endgenerate
+endmodule
+module rvdffe (
+	din,
+	en,
+	clk,
+	rst_l,
+	scan_mode,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter SHORT = 0;
+	parameter OVERRIDE = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire en;
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	output wire [WIDTH - 1:0] dout;
+	wire l1clk;
+	generate
+		if (SHORT == 1) begin : genblock
+			begin : genblock
+				assign dout = din;
+			end
+		end
+		else begin : genblock
+			rvclkhdr clkhdr(
+				.en(en),
+				.clk(clk),
+				.scan_mode(scan_mode),
+				.l1clk(l1clk)
+			);
+			rvdff #(.WIDTH(WIDTH)) dff(
+				.din(din),
+				.rst_l(rst_l),
+				.dout(dout),
+				.clk(l1clk)
+			);
+		end
+	endgenerate
+endmodule
+module rvdffpcie (
+	din,
+	clk,
+	rst_l,
+	en,
+	scan_mode,
+	dout
+);
+	parameter WIDTH = 31;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	input wire en;
+	input wire scan_mode;
+	output wire [WIDTH - 1:0] dout;
+	rvdfflie #(
+		.WIDTH(WIDTH),
+		.LEFT(19)
+	) dff(
+		.din(din),
+		.clk(clk),
+		.rst_l(rst_l),
+		.en(en),
+		.scan_mode(scan_mode),
+		.dout(dout)
+	);
+endmodule
+module rvdfflie (
+	din,
+	clk,
+	rst_l,
+	en,
+	scan_mode,
+	dout
+);
+	parameter WIDTH = 16;
+	parameter LEFT = 8;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	input wire en;
+	input wire scan_mode;
+	output wire [WIDTH - 1:0] dout;
+	localparam EXTRA = WIDTH - LEFT;
+	localparam LMSB = WIDTH - 1;
+	localparam LLSB = (LMSB - LEFT) + 1;
+	localparam XMSB = LLSB - 1;
+	localparam XLSB = LLSB - EXTRA;
+	rvdffiee #(.WIDTH(LEFT)) dff_left(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.en(en),
+		.din(din[LMSB:LLSB]),
+		.dout(dout[LMSB:LLSB])
+	);
+	rvdffe #(.WIDTH(EXTRA)) dff_extra(
+		.en(en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(din[XMSB:XLSB]),
+		.dout(dout[XMSB:XLSB])
+	);
+endmodule
+module rvdffppe (
+	din,
+	clk,
+	rst_l,
+	en,
+	scan_mode,
+	dout
+);
+	parameter WIDTH = 32;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	input wire en;
+	input wire scan_mode;
+	output wire [WIDTH - 1:0] dout;
+	localparam RIGHT = 31;
+	localparam LEFT = WIDTH - RIGHT;
+	localparam LMSB = WIDTH - 1;
+	localparam LLSB = (LMSB - LEFT) + 1;
+	localparam RMSB = LLSB - 1;
+	localparam RLSB = LLSB - RIGHT;
+	rvdffe #(.WIDTH(LEFT)) dff_left(
+		.en(en),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(din[LMSB:LLSB]),
+		.dout(dout[LMSB:LLSB])
+	);
+	rvdffe #(.WIDTH(RIGHT)) dff_right(
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.din(din[RMSB:RLSB]),
+		.dout(dout[RMSB:RLSB]),
+		.en(en & din[LLSB])
+	);
+endmodule
+module rvdffie (
+	din,
+	clk,
+	rst_l,
+	scan_mode,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter OVERRIDE = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	output wire [WIDTH - 1:0] dout;
+	wire l1clk;
+	wire en;
+	assign en = |(din ^ dout);
+	rvclkhdr clkhdr(
+		.en(en),
+		.clk(clk),
+		.scan_mode(scan_mode),
+		.l1clk(l1clk)
+	);
+	rvdff #(.WIDTH(WIDTH)) dff(
+		.din(din),
+		.rst_l(rst_l),
+		.dout(dout),
+		.clk(l1clk)
+	);
+endmodule
+module rvdffiee (
+	din,
+	clk,
+	rst_l,
+	scan_mode,
+	en,
+	dout
+);
+	parameter WIDTH = 1;
+	parameter OVERRIDE = 0;
+	input wire [WIDTH - 1:0] din;
+	input wire clk;
+	input wire rst_l;
+	input wire scan_mode;
+	input wire en;
+	output wire [WIDTH - 1:0] dout;
+	wire l1clk;
+	wire final_en;
+	assign final_en = |(din ^ dout) & en;
+	rvdffe #(.WIDTH(WIDTH)) dff(
+		.din(din),
+		.clk(clk),
+		.rst_l(rst_l),
+		.scan_mode(scan_mode),
+		.dout(dout),
+		.en(final_en)
+	);
+endmodule
+module rvsyncss (
+	clk,
+	rst_l,
+	din,
+	dout
+);
+	parameter WIDTH = 251;
+	input wire clk;
+	input wire rst_l;
+	input wire [WIDTH - 1:0] din;
+	output wire [WIDTH - 1:0] dout;
+	wire [WIDTH - 1:0] din_ff1;
+	rvdff #(.WIDTH(WIDTH)) sync_ff1(
+		.clk(clk),
+		.rst_l(rst_l),
+		.din(din[WIDTH - 1:0]),
+		.dout(din_ff1[WIDTH - 1:0])
+	);
+	rvdff #(.WIDTH(WIDTH)) sync_ff2(
+		.clk(clk),
+		.rst_l(rst_l),
+		.din(din_ff1[WIDTH - 1:0]),
+		.dout(dout[WIDTH - 1:0])
+	);
+endmodule
+module rvsyncss_fpga (
+	gw_clk,
+	rawclk,
+	clken,
+	rst_l,
+	din,
+	dout
+);
+	parameter WIDTH = 251;
+	input wire gw_clk;
+	input wire rawclk;
+	input wire clken;
+	input wire rst_l;
+	input wire [WIDTH - 1:0] din;
+	output wire [WIDTH - 1:0] dout;
+	wire [WIDTH - 1:0] din_ff1;
+	rvdff_fpga #(.WIDTH(WIDTH)) sync_ff1(
+		.rst_l(rst_l),
+		.clk(gw_clk),
+		.rawclk(rawclk),
+		.clken(clken),
+		.din(din[WIDTH - 1:0]),
+		.dout(din_ff1[WIDTH - 1:0])
+	);
+	rvdff_fpga #(.WIDTH(WIDTH)) sync_ff2(
+		.rst_l(rst_l),
+		.clk(gw_clk),
+		.rawclk(rawclk),
+		.clken(clken),
+		.din(din_ff1[WIDTH - 1:0]),
+		.dout(dout[WIDTH - 1:0])
+	);
+endmodule
+module rvlsadder (
+	rs1,
+	offset,
+	dout
+);
+	input wire [31:0] rs1;
+	input wire [11:0] offset;
+	output wire [31:0] dout;
+	wire cout;
+	wire sign;
+	wire [31:12] rs1_inc;
+	wire [31:12] rs1_dec;
+	assign {cout, dout[11:0]} = {1'b0, rs1[11:0]} + {1'b0, offset[11:0]};
+	assign rs1_inc[31:12] = rs1[31:12] + 1;
+	assign rs1_dec[31:12] = rs1[31:12] - 1;
+	assign sign = offset[11];
+	assign dout[31:12] = (({20 {sign ~^ cout}} & rs1[31:12]) | ({20 {~sign & cout}} & rs1_inc[31:12])) | ({20 {sign & ~cout}} & rs1_dec[31:12]);
+endmodule
+module rvbradder (
+	pc,
+	offset,
+	dout
+);
+	input [31:1] pc;
+	input [12:1] offset;
+	output [31:1] dout;
+	wire cout;
+	wire sign;
+	wire [31:13] pc_inc;
+	wire [31:13] pc_dec;
+	assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]};
+	assign pc_inc[31:13] = pc[31:13] + 1;
+	assign pc_dec[31:13] = pc[31:13] - 1;
+	assign sign = offset[12];
+	assign dout[31:13] = (({19 {sign ~^ cout}} & pc[31:13]) | ({19 {~sign & cout}} & pc_inc[31:13])) | ({19 {sign & ~cout}} & pc_dec[31:13]);
+endmodule
+module rvtwoscomp (
+	din,
+	dout
+);
+	parameter WIDTH = 32;
+	input wire [WIDTH - 1:0] din;
+	output wire [WIDTH - 1:0] dout;
+	wire [WIDTH - 1:1] dout_temp;
+	genvar i;
+	generate
+		for (i = 1; i < WIDTH; i = i + 1) begin : flip_after_first_one
+			assign dout_temp[i] = (|din[i - 1:0] ? ~din[i] : din[i]);
+		end
+	endgenerate
+	assign dout[WIDTH - 1:0] = {dout_temp[WIDTH - 1:1], din[0]};
+endmodule
+module rvfindfirst1 (
+	din,
+	dout
+);
+	parameter WIDTH = 32;
+	parameter SHIFT = $clog2(WIDTH);
+	input wire [WIDTH - 1:0] din;
+	output reg [SHIFT - 1:0] dout;
+	reg done;
+	always @(*) begin
+		dout[SHIFT - 1:0] = {SHIFT {1'b0}};
+		done = 1'b0;
+		begin : sv2v_autoblock_64
+			reg signed [31:0] i;
+			for (i = WIDTH - 1; i > 0; i = i - 1)
+				begin : find_first_one
+					done = done | din[i];
+					dout[SHIFT - 1:0] = dout[SHIFT - 1:0] + (done ? 1'b0 : 1'b1);
+				end
+		end
+	end
+endmodule
+module rvfindfirst1hot (
+	din,
+	dout
+);
+	parameter WIDTH = 32;
+	input wire [WIDTH - 1:0] din;
+	output reg [WIDTH - 1:0] dout;
+	reg done;
+	always @(*) begin
+		dout[WIDTH - 1:0] = {WIDTH {1'b0}};
+		done = 1'b0;
+		begin : sv2v_autoblock_65
+			reg signed [31:0] i;
+			for (i = 0; i < WIDTH; i = i + 1)
+				begin : find_first_one
+					dout[i] = ~done & din[i];
+					done = done | din[i];
+				end
+		end
+	end
+endmodule
+module rvmaskandmatch (
+	mask,
+	data,
+	masken,
+	match
+);
+	parameter WIDTH = 32;
+	input wire [WIDTH - 1:0] mask;
+	input wire [WIDTH - 1:0] data;
+	input wire masken;
+	output wire match;
+	wire [WIDTH - 1:0] matchvec;
+	wire masken_or_fullmask;
+	assign masken_or_fullmask = masken & ~(&mask[WIDTH - 1:0]);
+	assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
+	genvar i;
+	generate
+		for (i = 1; i < WIDTH; i = i + 1) begin : match_after_first_zero
+			assign matchvec[i] = (&mask[i - 1:0] & masken_or_fullmask ? 1'b1 : mask[i] == data[i]);
+		end
+	endgenerate
+	assign match = &matchvec[WIDTH - 1:0];
+endmodule
+module rvrangecheck (
+	addr,
+	in_range,
+	in_region
+);
+	parameter CCM_SADR = 32'h00000000;
+	parameter CCM_SIZE = 128;
+	input wire [31:0] addr;
+	output wire in_range;
+	output wire in_region;
+	localparam REGION_BITS = 4;
+	localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
+	wire [31:0] start_addr;
+	wire [3:0] region;
+	assign start_addr[31:0] = CCM_SADR;
+	assign region[3:0] = start_addr[31:28];
+	assign in_region = addr[31:28] == region[3:0];
+	generate
+		if (CCM_SIZE == 48) begin
+			assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS - 1:MASK_BITS - 2]);
+		end
+		else assign in_range = addr[31:MASK_BITS] == start_addr[31:MASK_BITS];
+	endgenerate
+endmodule
+module rveven_paritygen (
+	data_in,
+	parity_out
+);
+	parameter WIDTH = 16;
+	input wire [WIDTH - 1:0] data_in;
+	output wire parity_out;
+	assign parity_out = ^data_in[WIDTH - 1:0];
+endmodule
+module rveven_paritycheck (
+	data_in,
+	parity_in,
+	parity_err
+);
+	parameter WIDTH = 16;
+	input wire [WIDTH - 1:0] data_in;
+	input wire parity_in;
+	output wire parity_err;
+	assign parity_err = ^data_in[WIDTH - 1:0] ^ parity_in;
+endmodule
+module rvecc_encode (
+	din,
+	ecc_out
+);
+	input [31:0] din;
+	output [6:0] ecc_out;
+	wire [5:0] ecc_out_temp;
+	assign ecc_out_temp[0] = ((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
+	assign ecc_out_temp[1] = ((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
+	assign ecc_out_temp[2] = ((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
+	assign ecc_out_temp[3] = (((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+	assign ecc_out_temp[4] = (((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+	assign ecc_out_temp[5] = ((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
+	assign ecc_out[6:0] = {^din[31:0] ^ ^ecc_out_temp[5:0], ecc_out_temp[5:0]};
+endmodule
+module rvecc_decode (
+	en,
+	din,
+	ecc_in,
+	sed_ded,
+	dout,
+	ecc_out,
+	single_ecc_error,
+	double_ecc_error
+);
+	input en;
+	input [31:0] din;
+	input [6:0] ecc_in;
+	input sed_ded;
+	output [31:0] dout;
+	output [6:0] ecc_out;
+	output single_ecc_error;
+	output double_ecc_error;
+	wire [6:0] ecc_check;
+	wire [38:0] error_mask;
+	wire [38:0] din_plus_parity;
+	wire [38:0] dout_plus_parity;
+	assign ecc_check[0] = (((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
+	assign ecc_check[1] = (((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
+	assign ecc_check[2] = (((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
+	assign ecc_check[3] = ((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+	assign ecc_check[4] = ((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+	assign ecc_check[5] = (((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
+	assign ecc_check[6] = (^din[31:0] ^ ^ecc_in[6:0]) & ~sed_ded;
+	assign single_ecc_error = (en & (ecc_check[6:0] != 0)) & ecc_check[6];
+	assign double_ecc_error = (en & (ecc_check[6:0] != 0)) & ~ecc_check[6];
+	generate
+		genvar i;
+		for (i = 1; i < 40; i = i + 1) assign error_mask[i - 1] = ecc_check[5:0] == i;
+	endgenerate
+	assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
+	assign dout_plus_parity[38:0] = (single_ecc_error ? error_mask[38:0] ^ din_plus_parity[38:0] : din_plus_parity[38:0]);
+	assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
+	assign ecc_out[6:0] = {dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
+endmodule
+module rvecc_encode_64 (
+	din,
+	ecc_out
+);
+	input [63:0] din;
+	output [6:0] ecc_out;
+	assign ecc_out[0] = (((((((((((((((((((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63];
+	assign ecc_out[1] = (((((((((((((((((((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63];
+	assign ecc_out[2] = (((((((((((((((((((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+	assign ecc_out[3] = (((((((((((((((((((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_out[4] = (((((((((((((((((((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_out[5] = (((((((((((((((((((((((((((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_out[6] = (((((din[57] ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+endmodule
+module rvecc_decode_64 (
+	en,
+	din,
+	ecc_in,
+	ecc_error
+);
+	input en;
+	input [63:0] din;
+	input [6:0] ecc_in;
+	output ecc_error;
+	wire [6:0] ecc_check;
+	assign ecc_check[0] = ((((((((((((((((((((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63];
+	assign ecc_check[1] = ((((((((((((((((((((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63];
+	assign ecc_check[2] = ((((((((((((((((((((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+	assign ecc_check[3] = ((((((((((((((((((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_check[4] = ((((((((((((((((((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_check[5] = ((((((((((((((((((((((((((((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+	assign ecc_check[6] = ((((((ecc_in[6] ^ din[57]) ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+	assign ecc_error = en & (ecc_check[6:0] != 0);
+endmodule
+module rvclkhdr (
+
+	en,
+	clk,
+	scan_mode,
+	l1clk
+);
+
+	input wire en;
+	input wire clk;
+	input wire scan_mode;
+	output wire l1clk;
+	wire SE;
+	assign SE = 0;
+	sky130_fd_sc_hd__dlclkp_1 clkhdr(
+		`ifdef USE_POWER_PINS
+		.VPWR(1'b1),
+		.VGND(1'b0),
+		`endif
+		.CLK(clk),
+		.GCLK(l1clk),
+		.GATE(en)
+	);
+endmodule
+module rvoclkhdr (
+	en,
+	clk,
+	scan_mode,
+	l1clk
+);
+
+	input wire en;
+	input wire clk;
+	input wire scan_mode;
+	output wire l1clk;
+	wire SE;
+	assign SE = 0;
+	sky130_fd_sc_hd__dlclkp_1 clkhdr(
+		`ifdef USE_POWER_PINS
+		.VPWR(1'b1),
+		.VGND(1'b0),
+		`endif
+		.CLK(clk),
+		.GCLK(l1clk),
+		.GATE(en)
+	);
+endmodule

verilog/rtl/BrqRV_EB1/DFFRAM.v

diff --git a/verilog/rtl/BrqRV_EB1/DFFRAM.v b/verilog/rtl/BrqRV_EB1/DFFRAM.v
new file mode 100644
index 0000000..b80677f
--- /dev/null
+++ b/verilog/rtl/BrqRV_EB1/DFFRAM.v
@@ -0,0 +1,176 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`ifndef USE_CUSTOM_DFFRAM
+
+module DFFRAM(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input CLK,
+    input [3:0] WE,
+    input EN,
+    input [31:0] Di,
+    output reg [31:0] Do,
+    input [7:0] A
+);
+  
+
+reg [31:0] mem [0:`MEM_WORDS-1];
+
+always @(posedge CLK) begin
+    if (EN == 1'b1) begin
+        Do <= mem[A];
+        if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0];
+        if (WE[1]) mem[A][15: 8] <= Di[15: 8];
+        if (WE[2]) mem[A][23:16] <= Di[23:16];
+        if (WE[3]) mem[A][31:24] <= Di[31:24];
+    end
+end
+endmodule
+
+`else
+
+module DFFRAM #( parameter COLS=1)
+(
+`ifdef USE_POWER_PINS
+    VPWR,
+    VGND,
+`endif
+    CLK,
+    WE,
+    EN,
+    Di,
+    Do,
+    A
+);
+
+    input           CLK;
+    input   [3:0]   WE;
+    input           EN;
+    input   [31:0]  Di;
+    output  [31:0]  Do;
+    input   [7+$clog2(COLS):0]   A;
+
+`ifdef USE_POWER_PINS
+    input VPWR;
+    input VGND;
+`endif
+
+    wire [31:0]     DOUT [COLS-1:0];
+    wire [31:0]     Do_pre;
+    wire [COLS-1:0] EN_lines;
+
+    generate
+        genvar i;
+        for (i=0; i<COLS; i=i+1) begin : COLUMN
+            DFFRAM_COL4 RAMCOLS (
+                                `ifdef USE_POWER_PINS
+                                    .VPWR(VPWR),
+                                    .VGND(VGND),
+                                `endif
+                                    .CLK(CLK), 
+                                    .WE(WE), 
+                                    .EN(EN_lines[i]), 
+                                    .Di(Di), 
+                                    .Do(DOUT[i]), 
+                                    .A(A[7:0]) 
+                                );    
+        end
+        if(COLS==4) begin
+            MUX4x1_32 MUX ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif
+                .A0(DOUT[0]),
+                .A1(DOUT[1]),
+                .A2(DOUT[2]),
+                .A3(DOUT[3]),
+                .S(A[9:8]),
+                .X(Do_pre)
+            );
+            DEC2x4 DEC (
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif 
+                .EN(EN),
+                .A(A[9:8]),
+                .SEL(EN_lines)
+            );
+        end
+        else if(COLS==2) begin
+            MUX2x1_32 MUX ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif 
+                .A0(DOUT[0]),
+                .A1(DOUT[1]),
+                .S(A[8]),
+                .X(Do_pre)
+            );
+            //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
+            //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
+            DEC1x2 DEC ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif 
+                .EN(EN),
+                .A(A[8]),
+                .SEL(EN_lines[1:0]) 
+            );
+            
+        end
+        else begin
+            PASS MUX ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif 
+                .A(DOUT[0]),
+                .X(Do_pre)
+            );
+            sky130_fd_sc_hd__clkbuf_4 ENBUF (
+           `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+                .VPB(VPWR),
+                .VNB(VGND),
+            `endif 
+                .X(EN_lines[0]),
+                .A(EN)
+            );
+        end
+    endgenerate
+    
+    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif 
+        .X(Do),
+        .A(Do_pre)
+    );
+
+endmodule
+
+`endif
\ No newline at end of file

verilog/rtl/BrqRV_EB1/DFFRAMBB.v

diff --git a/verilog/rtl/BrqRV_EB1/DFFRAMBB.v b/verilog/rtl/BrqRV_EB1/DFFRAMBB.v
new file mode 100644
index 0000000..22ab55e
--- /dev/null
+++ b/verilog/rtl/BrqRV_EB1/DFFRAMBB.v
@@ -0,0 +1,784 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+    Building blocks for DFF based RAM compiler for SKY130A 
+    BYTE        :   8 memory cells used as a building block for WORD module
+    WORD        :   32-bit memory word with select and byte-level WE
+    DEC6x64     :   2x4 Binary Decoder
+    DEC6x64     :   6x64 Binary decoder
+    MUX4x1_32   :   32-bit 4x1 MUX
+    MUX2x1_32   :   32-bit 2x1 MUX
+    SRAM64x32   :   Tri-state buffers based 64x32 DFF RAM 
+    DFFRAM_COL4 :   A single column of 4 SRAM64x32 blocks using 4x1 multiplexors
+*/
+/*
+    Author: Mohamed Shalan (mshalan@aucegypt.edu)
+*/
+
+module BYTE (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input CLK,
+    input WE,
+    input SEL,
+    input [7:0] Di,
+    output [7:0] Do
+);
+
+    wire [7:0]  q_wire;
+    wire        we_wire;
+    wire        SEL_B;
+    wire        GCLK;
+
+    sky130_fd_sc_hd__inv_1 INV(
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .Y(SEL_B),
+        .A(SEL)
+    );
+
+    sky130_fd_sc_hd__and2_1 CGAND( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A(SEL),
+        .B(WE),
+        .X(we_wire)
+    );
+
+    sky130_fd_sc_hd__dlclkp_1 CG( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .CLK(CLK),
+        .GCLK(GCLK),
+        .GATE(we_wire) 
+    );
+
+    generate 
+        genvar i;
+        for(i=0; i<8; i=i+1) begin : BIT
+            sky130_fd_sc_hd__dfxtp_1 FF (
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+                .VPB(VPWR),
+                .VNB(VGND),
+            `endif 
+                .D(Di[i]),
+                .Q(q_wire[i]),
+                .CLK(GCLK)
+            );
+
+            sky130_fd_sc_hd__ebufn_2 OBUF ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+                .VPB(VPWR),
+                .VNB(VGND),
+            `endif
+                .A(q_wire[i]),
+                .Z(Do[i]),
+                .TE_B(SEL_B)
+            );
+
+        end
+    endgenerate 
+
+endmodule
+
+
+module WORD32 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input CLK,
+    input [3:0] WE,
+    input SEL,
+    input [31:0] Di,
+    output [31:0] Do
+);
+
+    BYTE B0 (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif 
+        .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
+    
+    BYTE B1 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR), 
+        .VGND(VGND),
+    `endif
+        .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
+    
+    BYTE B2 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
+    
+    BYTE B3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
+    
+endmodule 
+
+module DEC1x2 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input           EN,
+    input   [0:0]   A,
+    output  [1:0]   SEL
+);
+    sky130_fd_sc_hd__and2b_2    AND1 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[0]),
+        .A_N(A),
+        .B(EN)
+    );
+
+    sky130_fd_sc_hd__and2_2     AND3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[1]),
+        .A(A),
+        .B(A[0])
+    );
+    
+endmodule
+
+module DEC2x4 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input           EN,
+    input   [1:0]   A,
+    output  [3:0]   SEL
+);
+    sky130_fd_sc_hd__nor3b_4    AND0 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .Y(SEL[0]),
+        .A(A[0]),
+        .B(A[1]),
+        .C_N(EN)
+    );
+
+    sky130_fd_sc_hd__and3b_4    AND1 (
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif 
+        .X(SEL[1]),
+        .A_N(A[1]),
+        .B(A[0]),
+        .C(EN) 
+    );
+
+    sky130_fd_sc_hd__and3b_4    AND2 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[2]),
+        .A_N(A[0]),
+        .B(A[1]),
+        .C(EN)
+    );
+   
+    sky130_fd_sc_hd__and3_4     AND3 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[3]),
+        .A(A[1]),
+        .B(A[0]),
+        .C(EN) 
+    );
+    
+endmodule
+
+module DEC3x8 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input           EN,
+    input [2:0]     A,
+    output [7:0]    SEL
+);
+    sky130_fd_sc_hd__nor4b_2   AND0 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .Y(SEL[0]),
+        .A(A[0]),
+        .B(A[1]),
+        .C(A[2]),
+        .D_N(EN)
+    ); // 000
+
+    sky130_fd_sc_hd__and4bb_2   AND1 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[1]),
+        .A_N(A[2]),
+        .B_N(A[1]),
+        .C(A[0]),
+        .D(EN)
+    ); // 001
+
+    sky130_fd_sc_hd__and4bb_2   AND2 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[2]),
+        .A_N(A[2]),
+        .B_N(A[0]),
+        .C(A[1]),
+        .D(EN) 
+    ); // 010
+
+    sky130_fd_sc_hd__and4b_2    AND3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[3]),
+        .A_N(A[2]),
+        .B(A[1]),
+        .C(A[0]),
+        .D(EN) 
+    );   // 011
+
+    sky130_fd_sc_hd__and4bb_2   AND4 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[4]),
+        .A_N(A[0]),
+        .B_N(A[1]),
+        .C(A[2]),
+        .D(EN) 
+    ); // 100
+
+    sky130_fd_sc_hd__and4b_2    AND5 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[5]),
+        .A_N(A[1]),
+        .B(A[0]),
+        .C(A[2]),
+        .D(EN)
+    );   // 101
+
+    sky130_fd_sc_hd__and4b_2    AND6 ( 
+     `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[6]),
+        .A_N(A[0]),
+        .B(A[1]), 
+        .C(A[2]),
+        .D(EN) 
+    );   // 110
+
+    sky130_fd_sc_hd__and4_2     AND7 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[7]),
+        .A(A[0]),
+        .B(A[1]),
+        .C(A[2]), 
+        .D(EN)
+    ); // 111
+endmodule
+
+
+module DEC6x64 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input           EN,
+    input   [5:0]   A,
+    output  [63:0] SEL
+);
+    wire [7:0] SEL0_w ;
+    wire [2:0] A_buf;
+    
+    DEC3x8 DEC_L0 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .EN(EN),
+        .A(A[5:3]),
+        .SEL(SEL0_w)
+    );
+
+    sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(A_buf),
+        .A(A[2:0])
+    );
+
+    generate
+        genvar i;
+        for(i=0; i<8; i=i+1) begin : DEC_L1
+            DEC3x8 U ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif
+                .EN(SEL0_w[i]),
+                .A(A_buf),
+                .SEL(SEL[7+8*i: 8*i])
+            );
+        end
+    endgenerate
+endmodule
+
+module MUX2x1_32(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input   [31:0]      A0, A1,
+    input   [0:0]       S,
+    output  [31:0]      X
+);
+    sky130_fd_sc_hd__mux2_1 MUX[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A0(A0),
+        .A1(A1),
+        .S(S[0]),
+        .X(X)
+    );
+
+endmodule
+
+module MUX4x1_32(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input   [31:0]      A0, A1, A2, A3,
+    input   [1:0]       S,
+    output  [31:0]      X
+);
+    sky130_fd_sc_hd__mux4_1 MUX[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A0(A0), 
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S[0]),
+        .S1(S[1]),
+        .X(X)
+    );
+endmodule
+
+module PASS (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input [31:0] A,
+    output [31:0] X
+);
+    assign X = A;
+endmodule
+
+module SRAM64x32(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
+    input CLK,
+    input [3:0] WE,
+    input EN,
+    input [31:0] Di,
+    output [31:0] Do,
+    input [5:0] A
+);
+
+    wire [63:0]     SEL;
+    wire [31:0]     Do_pre;
+    wire [31:0]     Di_buf;
+    wire            CLK_buf;
+    wire [3:0]      WE_buf;
+
+    sky130_fd_sc_hd__clkbuf_16 CLKBUF (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(CLK_buf),
+        .A(CLK)
+    );
+    
+    sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(WE_buf),
+        .A(WE)
+    );
+
+    sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(Di_buf),
+        .A(Di)
+    );
+
+    DEC6x64 DEC  ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .EN(EN),
+        .A(A),
+        .SEL(SEL)
+    );
+
+    generate
+        genvar i;
+        for (i=0; i< 64; i=i+1) begin : WORD
+            WORD32 W ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+            `endif
+                .CLK(CLK_buf),
+                .WE(WE_buf),
+                .SEL(SEL[i]),
+                .Di(Di_buf),
+                .Do(Do_pre)
+            );
+        end
+    endgenerate
+
+    // Ensure that the Do_pre lines are not floating when EN = 0
+    wire lo;
+    wire float_buf_en;
+    sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(float_buf_en),
+        .A(EN)
+    );
+
+    sky130_fd_sc_hd__conb_1 TIE (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .LO(lo),
+        .HI()
+    );
+
+    sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A( lo ),
+        .Z(Do_pre),
+        .TE_B(float_buf_en)
+    );
+
+    generate 
+        //genvar i;
+        for(i=0; i<32; i=i+1) begin : OUT
+            sky130_fd_sc_hd__dfxtp_1 FF ( 
+            `ifdef USE_POWER_PINS
+                .VPWR(VPWR),
+                .VGND(VGND),
+                .VPB(VPWR),
+                .VNB(VGND),
+            `endif
+                .D(Do_pre[i]),
+                .Q(Do[i]),
+                .CLK(CLK)
+            );
+        end
+    endgenerate 
+
+endmodule
+
+module DFFRAM_COL4 
+(
+`ifdef USE_POWER_PINS
+    VPWR,
+    VGND,
+`endif
+    CLK,
+    WE,
+    EN,
+    Di,
+    Do,
+    A
+);
+
+    input           CLK;
+    input   [3:0]   WE;
+    input           EN;
+    input   [31:0]  Di;
+    output  [31:0]  Do;
+    input   [7:0]   A;
+
+`ifdef USE_POWER_PINS
+    input VPWR;
+    input VGND;
+`endif
+
+    wire [31:0]     Di_buf;
+    wire [31:0]     Do_pre;
+    wire            CLK_buf;
+    wire [3:0]      WE_buf;
+    wire [5:3]      A_buf;
+
+    wire [31:0]     Do_B_0_0;
+    wire [31:0]     Do_B_0_1;
+    wire [31:0]     Do_B_0_2;
+    wire [31:0]     Do_B_0_3;
+
+    wire [3:0]      row_sel;
+
+    sky130_fd_sc_hd__clkbuf_8 CLKBUF (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(CLK_buf),
+        .A(CLK)
+    );
+
+    sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(WE_buf),
+        .A(WE)
+    );
+
+    sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(Di_buf), 
+        .A(Di)
+    );
+
+    sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(A_buf),
+        .A(A[5:3])
+    );
+    
+    DEC2x4 DEC ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR), 
+        .VGND(VGND),
+    `endif
+        .EN(EN),
+        .A(A[7:6]),
+        .SEL(row_sel)
+    );
+
+    SRAM64x32 B_0_0 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .CLK(CLK_buf),
+        .WE(WE_buf),
+        .EN(row_sel[0]),
+        .Di(Di_buf),
+        .Do(Do_B_0_0),
+        .A({A_buf,A[2:0]})
+    );
+
+    SRAM64x32 B_0_1 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR), 
+        .VGND(VGND),
+    `endif
+        .CLK(CLK_buf),
+        .WE(WE_buf),
+        .EN(row_sel[1]),
+        .Di(Di_buf),
+        .Do(Do_B_0_1),
+        .A({A_buf,A[2:0]})
+    );
+
+    SRAM64x32 B_0_2 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .CLK(CLK_buf),
+        .WE(WE_buf),
+        .EN(row_sel[2]),
+        .Di(Di_buf),
+        .Do(Do_B_0_2), 
+        .A({A_buf,A[2:0]}) 
+    );
+
+    SRAM64x32 B_0_3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .CLK(CLK_buf),
+        .WE(WE_buf),
+        .EN(row_sel[3]),
+        .Di(Di_buf),
+        .Do(Do_B_0_3),
+        .A({A_buf,A[2:0]})
+    );
+
+    MUX4x1_32 MUX ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .A0(Do_B_0_0),
+        .A1(Do_B_0_1),
+        .A2(Do_B_0_2),
+        .A3(Do_B_0_3),
+        .S(A[7:6]),
+        .X(Do)
+    );
+
+endmodule
+

verilog/rtl/rams/ram_256x32_2r1w/Makefile

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/Makefile b/verilog/rtl/rams/ram_256x32_2r1w/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean

verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v
new file mode 100644
index 0000000..90b67bb
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v
@@ -0,0 +1,184 @@
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+                   
+//`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 256,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 8,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @(Addr_sel or addr or web or csb) begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @(Addr_sel_1 or addr1 or csb1) begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+

verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v
new file mode 100644
index 0000000..d7b2f26
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v
@@ -0,0 +1,81 @@
+
+//`include "utils.vh"
+module ram_generic_nr1w
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 256,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 2 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 8,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  vccd1,
+  vssd1,
+`endif
+  addr, clk, csb, web, wmask, din, dout, addr1, csb1, clk1, dout1);
+  `ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+  `endif
+  input  clk; // clock
+  input  csb; // active low chip select
+  input  web; // active low write control
+  input [NUM_WMASKS-1:0]  wmask; // write mask
+  input [ADDR_WIDTH * nRPORTS-1:0] addr;
+  input [DATA_WIDTH-1:0]  din;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout;
+  input clk1;
+  input csb1;
+  input [ADDR_WIDTH * nRPORTS-1:0] addr1;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout1;
+    // unpacked read addresses/data
+  reg  [ADDR_WIDTH-1:0] RAddr_upk [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk [nRPORTS-1:0]; // read data      - unpacked 2D array 
+  reg  [ADDR_WIDTH-1:0] RAddr_upk_1 [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk_1 [nRPORTS-1:0]; // read data      - unpacked 2D array 
+
+  // unpack read addresses; pack read data
+  `ARRINIT;
+  always @* begin
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr,RAddr_upk);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk,dout);
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr1,RAddr_upk_1);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk_1,dout1);
+  end
+genvar rpi;
+  generate
+    for (rpi=0 ; rpi<nRPORTS; rpi=rpi+1) begin
+    ram_generic_1rw #( .NUM_WMASKS (NUM_WMASKS),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATA_WIDTH), // data width
+                    .nRPORTS(1), // number of reading ports
+      		    .nWPORTS(1), // number of write ports
+     		    .IZERO  (IZERO), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (IFILE),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDR_WIDTH),
+     		    .DELAY (DELAY),
+     		    .BYPASS(BYPASS))
+    ram_1rw      ( `ifdef USE_POWER_PINS
+    		    .vccd1(vccd1),
+    		    .vssd1(vssd1),
+    		    `endif
+    		    .clk(clk), // clock
+  		    .csb(csb), // active low chip select
+  		    .web(web), // active low write control
+  		    .wmask(wmask), // write mask
+  		    .addr(RAddr_upk[rpi]/*(web == 0) ? RAddr_upk[0] : RAddr_upk[rpi]*/),
+  		    .din(din),
+   		    .dout(RData_upk[rpi]),
+                    .clk1(clk1),
+                    .csb1(csb1), 
+                    .addr1(RAddr_upk_1[rpi]),
+                    .dout1(RData_upk_1[rpi]));
+    end
+  endgenerate
+endmodule
+

verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v
new file mode 100644
index 0000000..3cc323c
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/ram_generated_256x32_2r1w_tb.v
@@ -0,0 +1,289 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   256
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 2
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 8
+`endif
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+module ram_generic_nr1w_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+  reg                      clk = 1'b0                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+   
+  initial begin
+  	$dumpfile("srimulation.vcd");
+  	$dumpvars(0,ram_generic_nr1w_tb);
+  end
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"===============================Simulation Results======================================\n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fwrite(rep_fd,"Golden   Golden     Golden          Actual       Actual     Actual          Result   \n");
+      $fwrite(rep_fd,"Read     Model      Model           Read         Model      Model                    \n");
+      $fwrite(rep_fd,"Port     RAddr      RData           Port         RAddr      RData                    \n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fclose(rep_fd);
+    end
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n",ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end
+
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        );
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR2D1D(nRPORTS,DATAW,RData_upk_golden ,RData_pck_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+    // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+integer p;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        
+        //if (cycc==CYCC) begin
+        for(p=0; p<nRPORTS; p=p+1) begin
+            pass = (RData_upk_golden[p]===RData_upk_sram[p]);
+    	    rep_fd = $fopen("sim.txt","a+");
+            $fwrite(rep_fd,"%-10d %-10d %-15h %-10d %-10d %-15h %-10s \n",p,RAddr_upk[p],RData_upk_golden[p],p,RAddr_upk[p],RData_upk_sram[p],pass?"pass":"fail");
+            $fclose(rep_fd);
+        end
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r,s;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+//      $readmemh("init_ram.hex", mem);
+        for(r=0; r<MEMD; r=r+1) mem[r] = {DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(s=0; s<`WMASK; s=s+1) begin
+    		if(wmask_pck[s])
+        		mem[WAddr_pck][8*s +: 8] = WData_pck[8*s +: 8];
+    	end
+    end
+   else begin
+      for(q=0; q<nRPORTS; q=q+1) begin
+        RData_upk_golden[q] <= #(10) mem[RAddr_upk[q]];
+      end
+   end
+  end
+
+
+ram_generic_nr1w #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDRW),
+     		    .DELAY (3))
+ram_nr1w          ( `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)? {nRPORTS{WAddr_pck}}:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW*nRPORTS{1'b0}}),
+                    .dout1());
+endmodule
+

verilog/rtl/rams/ram_256x32_2r1w/sim.txt

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/sim.txt b/verilog/rtl/rams/ram_256x32_2r1w/sim.txt
new file mode 100644
index 0000000..eb7b9fa
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/sim.txt
@@ -0,0 +1,2006 @@
+===============================Simulation Results======================================
+=======================================================================================
+Golden   Golden     Golden          Actual       Actual     Actual          Result   
+Read     Model      Model           Read         Model      Model                    
+Port     RAddr      RData           Port         RAddr      RData                    
+=======================================================================================
+0          100        00000000        0          100        00000000        pass       
+1          135        00000000        1          135        00000000        pass       
+0          172        00000000        0          172        00000000        pass       
+1          217        00000000        1          217        00000000        pass       
+0          1          00000000        0          1          00000000        pass       
+1          2          00000000        1          2          00000000        pass       
+0          70         00000000        0          70         00000000        pass       
+1          116        00000000        1          116        00000000        pass       
+0          160        00000000        0          160        00000000        pass       
+1          134        00000000        1          134        00000000        pass       
+0          152        00000000        0          152        00000000        pass       
+1          40         00000000        1          40         00000000        pass       
+0          174        00000000        0          174        00000000        pass       
+1          181        00000000        1          181        00000000        pass       
+0          35         00000000        0          35         00000000        pass       
+1          201        00000000        1          201        00000000        pass       
+0          172        00000000        0          172        00000000        pass       
+1          180        00000000        1          180        00000000        pass       
+0          92         00000000        0          92         00000000        pass       
+1          104        00000000        1          104        00000000        pass       
+0          69         00000000        0          69         00000000        pass       
+1          110        00000000        1          110        00000000        pass       
+0          249        00000000        0          249        00000000        pass       
+1          98         00000000        1          98         00000000        pass       
+0          226        00000000        0          226        00000000        pass       
+1          13         00000000        1          13         00000000        pass       
+0          97         00000000        0          97         00000000        pass       
+1          124        00000000        1          124        00000000        pass       
+0          214        00000000        0          214        00000000        pass       
+1          146        00000000        1          146        00000000        pass       
+0          46         00000000        0          46         00000000        pass       
+1          130        00000000        1          130        00000000        pass       
+0          242        00000000        0          242        00000000        pass       
+1          213        00000000        1          213        00000000        pass       
+0          125        00000000        0          125        00000000        pass       
+1          238        00000000        1          238        00000000        pass       
+0          196        00000000        0          196        00000000        pass       
+1          223        00000000        1          223        00000000        pass       
+0          13         00000000        0          13         00000000        pass       
+1          235        00000000        1          235        00000000        pass       
+0          14         00008dab        0          14         00008dab        pass       
+1          246        00000000        1          246        00000000        pass       
+0          255        006a00d8        0          255        006a00d8        pass       
+1          159        00000000        1          159        00000000        pass       
+0          9          00000000        0          9          00000000        pass       
+1          226        03004500        1          226        03004500        pass       
+0          181        00000000        0          181        00000000        pass       
+1          135        00000000        1          135        00000000        pass       
+0          229        00000000        0          229        00000000        pass       
+1          2          00000000        1          2          00000000        pass       
+0          220        00000000        0          220        00000000        pass       
+1          176        00000000        1          176        00000000        pass       
+0          57         00000000        0          57         00000000        pass       
+1          110        00000000        1          110        00000000        pass       
+0          124        00000000        0          124        00000000        pass       
+1          41         00000000        1          41         00000000        pass       
+0          22         00000000        0          22         00000000        pass       
+1          181        00000000        1          181        00000000        pass       
+0          10         00000000        0          10         00000000        pass       
+1          74         00000000        1          74         00000000        pass       
+0          246        00000000        0          246        00000000        pass       
+1          188        00000000        1          188        00000000        pass       
+0          28         00000000        0          28         00000000        pass       
+1          100        00000000        1          100        00000000        pass       
+0          146        00000000        0          146        00000000        pass       
+1          132        00000000        1          132        00000000        pass       
+0          193        00000000        0          193        00000000        pass       
+1          168        00000000        1          168        00000000        pass       
+0          3          00000000        0          3          00000000        pass       
+1          173        00000000        1          173        00000000        pass       
+0          218        00000000        0          218        00000000        pass       
+1          65         00000000        1          65         00000000        pass       
+0          39         00000000        0          39         00000000        pass       
+1          140        00000000        1          140        00000000        pass       
+0          42         00000000        0          42         00000000        pass       
+1          133        00000000        1          133        00000000        pass       
+0          44         00000000        0          44         00000000        pass       
+1          97         00000000        1          97         00000000        pass       
+0          135        00000000        0          135        00000000        pass       
+1          80         00000000        1          80         00000000        pass       
+0          34         00000000        0          34         00000000        pass       
+1          252        00000000        1          252        00000000        pass       
+0          206        00000000        0          206        00000000        pass       
+1          215        00000000        1          215        00000000        pass       
+0          194        00000000        0          194        00000000        pass       
+1          20         00000000        1          20         00000000        pass       
+0          253        00000000        0          253        00000000        pass       
+1          97         00000000        1          97         00000000        pass       
+0          189        00000000        0          189        00000000        pass       
+1          200        00000000        1          200        00000000        pass       
+0          168        00000000        0          168        00000000        pass       
+1          115        00000000        1          115        00000000        pass       
+0          74         00000000        0          74         00000000        pass       
+1          248        00000000        1          248        00000000        pass       
+0          126        00000000        0          126        00000000        pass       
+1          226        00000000        1          226        00000000        pass       
+0          208        00000000        0          208        00000000        pass       
+1          58         00000000        1          58         00000000        pass       
+0          204        00000000        0          204        00000000        pass       
+1          8          00000000        1          8          00000000        pass       
+0          170        00000000        0          170        00000000        pass       
+1          137        00000000        1          137        00000000        pass       
+0          23         00000000        0          23         00000000        pass       
+1          170        00000000        1          170        00000000        pass       
+0          242        00000000        0          242        00000000        pass       
+1          180        00000000        1          180        00000000        pass       
+0          244        00000000        0          244        00000000        pass       
+1          137        00000000        1          137        00000000        pass       
+0          237        00000000        0          237        00000000        pass       
+1          118        00000000        1          118        00000000        pass       
+0          245        00000000        0          245        00000000        pass       
+1          183        00000000        1          183        00000000        pass       
+0          9          00000000        0          9          00000000        pass       
+1          193        00000000        1          193        00000000        pass       
+0          102        00000000        0          102        00000000        pass       
+1          250        00000000        1          250        00000000        pass       
+0          121        00000000        0          121        00000000        pass       
+1          46         00000000        1          46         00000000        pass       
+0          60         00000000        0          60         00000000        pass       
+1          19         00000000        1          19         00000000        pass       
+0          243        0671000c        0          243        0671000c        pass       
+1          53         00000000        1          53         00000000        pass       
+0          23         00000000        0          23         00000000        pass       
+1          51         00000000        1          51         00000000        pass       
+0          61         00000000        0          61         00000000        pass       
+1          183        00000000        1          183        00000000        pass       
+0          214        0000002d        0          214        0000002d        pass       
+1          6          00000000        1          6          00000000        pass       
+0          192        0000002d        0          192        0000002d        pass       
+1          3          00000000        1          3          00000000        pass       
+0          216        00000000        0          216        00000000        pass       
+1          8          00000000        1          8          00000000        pass       
+0          48         00000000        0          48         00000000        pass       
+1          72         00000000        1          72         00000000        pass       
+0          91         2ca90059        0          91         2ca90059        pass       
+1          46         00000000        1          46         00000000        pass       
+0          177        2ca90059        0          177        2ca90059        pass       
+1          23         00000000        1          23         00000000        pass       
+0          27         2ca90059        0          27         2ca90059        pass       
+1          244        00000000        1          244        00000000        pass       
+0          62         00000000        0          62         00000000        pass       
+1          207        00000000        1          207        00000000        pass       
+0          235        00000000        0          235        00000000        pass       
+1          38         00000000        1          38         00000000        pass       
+0          240        00000000        0          240        00000000        pass       
+1          64         00000000        1          64         00000000        pass       
+0          135        00000000        0          135        00000000        pass       
+1          52         00000000        1          52         00000000        pass       
+0          105        00000000        0          105        00000000        pass       
+1          108        00000000        1          108        00000000        pass       
+0          171        00000000        0          171        00000000        pass       
+1          233        00000000        1          233        00000000        pass       
+0          182        00000000        0          182        00000000        pass       
+1          14         00000000        1          14         00000000        pass       
+0          96         00000000        0          96         00000000        pass       
+1          232        00000000        1          232        00000000        pass       
+0          191        00000000        0          191        00000000        pass       
+1          126        00000000        1          126        00000000        pass       
+0          65         00000000        0          65         00000000        pass       
+1          0          00000000        1          0          00000000        pass       
+0          79         00000000        0          79         00000000        pass       
+1          36         00000000        1          36         00000000        pass       
+0          146        00000000        0          146        00000000        pass       
+1          172        00000000        1          172        00000000        pass       
+0          106        00000000        0          106        00000000        pass       
+1          201        00000000        1          201        00000000        pass       
+0          123        00000000        0          123        00000000        pass       
+1          57         00000000        1          57         00000000        pass       
+0          52         00000000        0          52         00000000        pass       
+1          101        00000000        1          101        00000000        pass       
+0          218        00000000        0          218        00000000        pass       
+1          193        00000000        1          193        00000000        pass       
+0          2          57001d00        0          2          57001d00        pass       
+1          220        00000000        1          220        00000000        pass       
+0          248        57001d00        0          248        57001d00        pass       
+1          114        00000000        1          114        00000000        pass       
+0          47         00000000        0          47         00000000        pass       
+1          7          00000000        1          7          00000000        pass       
+0          77         00000000        0          77         00000000        pass       
+1          181        00000000        1          181        00000000        pass       
+0          225        00000000        0          225        00000000        pass       
+1          175        00000000        1          175        00000000        pass       
+0          132        00000000        0          132        00000000        pass       
+1          181        00000000        1          181        00000000        pass       
+0          59         3a980075        0          59         3a980075        pass       
+1          90         00000000        1          90         00000000        pass       
+0          79         00000000        0          79         00000000        pass       
+1          42         e9b40000        1          42         e9b40000        pass       
+0          22         00000000        0          22         00000000        pass       
+1          53         e9b40000        1          53         e9b40000        pass       
+0          132        00000000        0          132        00000000        pass       
+1          170        00000000        1          170        00000000        pass       
+0          146        00000000        0          146        00000000        pass       
+1          231        00000000        1          231        00000000        pass       
+0          173        00000000        0          173        00000000        pass       
+1          18         00000000        1          18         00000000        pass       
+0          84         00000000        0          84         00000000        pass       
+1          66         00000000        1          66         00000000        pass       
+0          154        00000000        0          154        00000000        pass       
+1          40         00000000        1          40         00000000        pass       
+0          39         000000f2        0          39         000000f2        pass       
+1          44         00000000        1          44         00000000        pass       
+0          113        000000f2        0          113        000000f2        pass       
+1          165        00000000        1          165        00000000        pass       
+0          217        00000000        0          217        00000000        pass       
+1          20         00000000        1          20         00000000        pass       
+0          93         00000000        0          93         00000000        pass       
+1          101        00000000        1          101        00000000        pass       
+0          109        00000000        0          109        00000000        pass       
+1          16         00000000        1          16         00000000        pass       
+0          162        00000000        0          162        00000000        pass       
+1          207        00000000        1          207        00000000        pass       
+0          64         00000000        0          64         00000000        pass       
+1          89         00000000        1          89         00000000        pass       
+0          215        00000000        0          215        00000000        pass       
+1          7          00000000        1          7          00000000        pass       
+0          58         00000000        0          58         00000000        pass       
+1          223        00000000        1          223        00000000        pass       
+0          253        00000000        0          253        00000000        pass       
+1          211        00000000        1          211        00000000        pass       
+0          178        00000000        0          178        00000000        pass       
+1          123        00000000        1          123        00000000        pass       
+0          31         00000000        0          31         00000000        pass       
+1          35         00000000        1          35         00000000        pass       
+0          25         dc2200b8        0          25         dc2200b8        pass       
+1          110        00000000        1          110        00000000        pass       
+0          107        00000000        0          107        00000000        pass       
+1          131        00000000        1          131        00000000        pass       
+0          230        00000000        0          230        00000000        pass       
+1          148        00000000        1          148        00000000        pass       
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verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..428a5a7
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,122 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 0 ;
+  parameter VERBOSE = 0 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 0 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+   // $display("hey");
+    //#(T_HOLD) dout0 = 32'bx;
+    //if ( !csb0_reg && web0_reg && VERBOSE ) 
+    //  $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    //if ( !csb0_reg && !web0_reg && VERBOSE )
+    //  $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    //if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+    //    $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    //if ( !csb1_reg && VERBOSE ) 
+    // $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+//integer i;
+//initial
+    //if (IZERO)
+  //    for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule

verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd b/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd
new file mode 100644
index 0000000..55bd769
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/srimulation.vcd
@@ -0,0 +1,53164 @@
+$date
+	Wed Nov 24 03:18:12 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_nr1w_tb $end
+$var wire 64 ! RData_pck_sram [63:0] $end
+$var reg 16 " RAddr_pck [15:0] $end
+$var reg 64 # RData_pck_golden [63:0] $end
+$var reg 8 $ WAddr_pck [7:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 p [31:0] $end
+$var integer 32 3 pass [31:0] $end
+$var integer 32 4 q [31:0] $end
+$var integer 32 5 r [31:0] $end
+$var integer 32 6 rep_fd [31:0] $end
+$var integer 32 7 s [31:0] $end
+$scope module ram_nr1w $end
+$var wire 16 8 addr [15:0] $end
+$var wire 16 9 addr1 [15:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 < din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 > wmask [3:0] $end
+$var reg 64 ? dout [63:0] $end
+$var reg 64 @ dout1 [63:0] $end
+$var integer 32 A _i_ [31:0] $end
+$scope begin genblk1[0] $end
+$scope module ram_1rw $end
+$var wire 8 B addr [7:0] $end
+$var wire 8 C addr1 [7:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 D din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 E wmask [3:0] $end
+$var wire 1 F Addr_sel_1 $end
+$var wire 1 G Addr_sel $end
+$var reg 32 H RData_out [31:0] $end
+$var reg 32 I RData_out_1 [31:0] $end
+$var reg 1 J Raddr_sel $end
+$var reg 1 K Raddr_sel_1 $end
+$var reg 32 L dout [31:0] $end
+$var reg 32 M dout1 [31:0] $end
+$var reg 1 N web_reg $end
+$var integer 32 O i [31:0] $end
+$var integer 32 P j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Q addr0 [7:0] $end
+$var wire 8 R addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 S csb0 $end
+$var wire 1 T csb1 $end
+$var wire 32 U din0 [31:0] $end
+$var wire 1 V web0 $end
+$var wire 4 W wmask0 [3:0] $end
+$var reg 8 X addr0_reg [7:0] $end
+$var reg 8 Y addr1_reg [7:0] $end
+$var reg 1 Z csb0_reg $end
+$var reg 1 [ csb1_reg $end
+$var reg 32 \ din0_reg [31:0] $end
+$var reg 32 ] dout0 [31:0] $end
+$var reg 32 ^ dout1 [31:0] $end
+$var reg 1 _ web0_reg $end
+$var reg 4 ` wmask0_reg [3:0] $end
+$var integer 32 a i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope module ram_1rw $end
+$var wire 8 b addr [7:0] $end
+$var wire 8 c addr1 [7:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 d din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 e wmask [3:0] $end
+$var wire 1 f Addr_sel_1 $end
+$var wire 1 g Addr_sel $end
+$var reg 32 h RData_out [31:0] $end
+$var reg 32 i RData_out_1 [31:0] $end
+$var reg 1 j Raddr_sel $end
+$var reg 1 k Raddr_sel_1 $end
+$var reg 32 l dout [31:0] $end
+$var reg 32 m dout1 [31:0] $end
+$var reg 1 n web_reg $end
+$var integer 32 o i [31:0] $end
+$var integer 32 p j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 q addr0 [7:0] $end
+$var wire 8 r addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 s csb0 $end
+$var wire 1 t csb1 $end
+$var wire 32 u din0 [31:0] $end
+$var wire 1 v web0 $end
+$var wire 4 w wmask0 [3:0] $end
+$var reg 8 x addr0_reg [7:0] $end
+$var reg 8 y addr1_reg [7:0] $end
+$var reg 1 z csb0_reg $end
+$var reg 1 { csb1_reg $end
+$var reg 32 | din0_reg [31:0] $end
+$var reg 32 } dout0 [31:0] $end
+$var reg 32 ~ dout1 [31:0] $end
+$var reg 1 !" web0_reg $end
+$var reg 4 "" wmask0_reg [3:0] $end
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+$var reg 1 '" RAND $end
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+$var integer 32 *" addr [31:0] $end
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verilog/rtl/rams/ram_256x32_2r1w/utils.vh

diff --git a/verilog/rtl/rams/ram_256x32_2r1w/utils.vh b/verilog/rtl/rams/ram_256x32_2r1w/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_256x32_2r1w/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__

verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean

verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v
new file mode 100644
index 0000000..35c2bd5
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw.v
@@ -0,0 +1,159 @@
+`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+

verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v
new file mode 100644
index 0000000..8009039
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/ram_generated_512x32_1rw_tb.v
@@ -0,0 +1,287 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   512
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 1
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 9
+`endif
+
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+
+
+module ram_generic_1rw_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+
+  reg                      clk = 1'b1                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+  
+  initial begin
+  $dumpfile("simulation.vcd");
+  $dumpvars(0,ram_generic_1rw_tb);
+  end
+
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"=======================Simulation Results======================\n");
+      $fwrite(rep_fd,"===============================================================\n");
+      $fwrite(rep_fd,"Golden   Golden           Actual      Actual          Result   \n");
+      $fwrite(rep_fd,"Model    Model            Model       Model                    \n");
+      $fwrite(rep_fd,"RAddr    RData            RAddr       RData                    \n");
+      $fwrite(rep_fd,"===============================================================\n");
+      $fclose(rep_fd);
+    end
+   // rep_fd = $fopen("sim.txt","a+");
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n"  ,ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    //$fclose(rep_fd);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end   
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        ); 
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_golden ,RData_upk_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+   // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+    
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        pass = (RData_pck_golden===RData_pck_sram);
+        //if (cycc==CYCC) begin
+    	rep_fd = $fopen("sim.txt","a+");
+        $fwrite(rep_fd,"%-10d %-15h %-10d %-15h %-10s \n",RAddr_pck,RData_pck_golden,RAddr_pck,RData_pck_sram,pass?"pass":"fail");
+        $fclose(rep_fd);
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+      //$readmemh("init_ram.hex", mem);
+      for(q=0; q<MEMD; q=q+1) mem[q] ={DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(r=0; r<`WMASK; r=r+1) begin
+    		if(wmask_pck[r])
+        		mem[WAddr_pck][8*r +: 8] = WData_pck[8*r +: 8];
+    	end
+    end
+   else
+        RData_pck_golden <= #(10) mem[RAddr_pck];
+  end
+
+// Actual Model
+ram_generic_1rw #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE(""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(`log2(MEMD)),
+     		    .DELAY (3))
+ram_1rw          (  `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)?WAddr_pck:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW{1'b0}}),
+                    .dout1());
+endmodule
+

verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt
new file mode 100644
index 0000000..e55150a
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sim.txt
@@ -0,0 +1,1006 @@
+=======================Simulation Results======================
+===============================================================
+Golden   Golden           Actual      Actual          Result   
+Model    Model            Model       Model                    
+RAddr    RData            RAddr       RData                    
+===============================================================
+185        00000000        185        00000000        pass       
+143        00000000        143        00000000        pass       
+105        00000000        105        00000000        pass       
+211        00000000        211        00000000        pass       
+293        00000000        293        00000000        pass       
+26         00000000        26         00000000        pass       
+416        00000000        416        00000000        pass       
+216        00000000        216        00000000        pass       
+337        00000000        337        00000000        pass       
+252        00000000        252        00000000        pass       
+131        00000000        131        00000000        pass       
+241        00000000        241        00000000        pass       
+266        00000000        266        00000000        pass       
+364        00000000        364        00000000        pass       
+39         00000000        39         00000000        pass       
+70         00000000        70         00000000        pass       
+114        00000000        114        00000000        pass       
+104        00000000        104        00000000        pass       
+94         00000000        94         00000000        pass       
+319        00000000        319        00000000        pass       
+94         00000000        94         00000000        pass       
+201        00000000        201        00000000        pass       
+35         00000000        35         00000000        pass       
+14         00000000        14         00000000        pass       
+155        00000000        155        00000000        pass       
+189        00000000        189        00000000        pass       
+285        00000000        285        00000000        pass       
+364        00000000        364        00000000        pass       
+343        00000000        343        00000000        pass       
+135        00000000        135        00000000        pass       
+84         00000000        84         00000000        pass       
+45         00000000        45         00000000        pass       
+160        00000000        160        00000000        pass       
+286        00000000        286        00000000        pass       
+425        00000000        425        00000000        pass       
+501        00000000        501        00000000        pass       
+68         00000000        68         00000000        pass       
+133        00000000        133        00000000        pass       
+308        00000000        308        00000000        pass       
+189        00000000        189        00000000        pass       
+492        00000000        492        00000000        pass       
+356        00000000        356        00000000        pass       
+275        00000000        275        00000000        pass       
+93         00000000        93         00000000        pass       
+202        00000000        202        00000000        pass       
+219        00000000        219        00000000        pass       
+461        00000000        461        00000000        pass       
+221        00000000        221        00000000        pass       
+434        00000000        434        00000000        pass       
+252        00000000        252        00000000        pass       
+217        00000000        217        00000000        pass       
+447        00000000        447        00000000        pass       
+507        00000000        507        00000000        pass       
+493        00000000        493        00000000        pass       
+104        00000000        104        00000000        pass       
+503        00000000        503        00000000        pass       
+244        00000000        244        00000000        pass       
+297        00000000        297        00000000        pass       
+262        00000000        262        00000000        pass       
+461        00000000        461        00000000        pass       
+341        00000000        341        00000000        pass       
+467        000086cd        467        000086cd        pass       
+293        00000000        293        00000000        pass       
+359        00000000        359        00000000        pass       
+370        00000000        370        00000000        pass       
+158        00000000        158        00000000        pass       
+56         00000000        56         00000000        pass       
+33         00000000        33         00000000        pass       
+156        00000000        156        00000000        pass       
+301        00000000        301        00000000        pass       
+104        00000000        104        00000000        pass       
+131        00000000        131        00000000        pass       
+370        00000000        370        00000000        pass       
+130        00000000        130        00000000        pass       
+385        00000000        385        00000000        pass       
+501        00000000        501        00000000        pass       
+147        00000000        147        00000000        pass       
+337        00000000        337        00000000        pass       
+305        00000000        305        00000000        pass       
+256        00000000        256        00000000        pass       
+109        00000000        109        00000000        pass       
+206        00000000        206        00000000        pass       
+44         00000000        44         00000000        pass       
+61         00000000        61         00000000        pass       
+154        00000000        154        00000000        pass       
+473        00000000        473        00000000        pass       
+335        00000000        335        00000000        pass       
+445        00000000        445        00000000        pass       
+150        00000000        150        00000000        pass       
+10         00000000        10         00000000        pass       
+349        00000000        349        00000000        pass       
+26         00000000        26         00000000        pass       
+294        00000000        294        00000000        pass       
+402        00000000        402        00000000        pass       
+365        00000000        365        00000000        pass       
+486        00000000        486        00000000        pass       
+332        00000000        332        00000000        pass       
+108        00000000        108        00000000        pass       
+407        00000000        407        00000000        pass       
+436        00000000        436        00000000        pass       
+287        00000000        287        00000000        pass       
+206        00000000        206        00000000        pass       
+269        00000000        269        00000000        pass       
+122        00000000        122        00000000        pass       
+94         00000000        94         00000000        pass       
+91         00000000        91         00000000        pass       
+29         00000000        29         00000000        pass       
+367        00000000        367        00000000        pass       
+24         00000000        24         00000000        pass       
+269        00000000        269        00000000        pass       
+84         00000000        84         00000000        pass       
+55         00000000        55         00000000        pass       
+59         00000000        59         00000000        pass       
+72         00000000        72         00000000        pass       
+55         00000000        55         00000000        pass       
+387        00000000        387        00000000        pass       
+364        00000000        364        00000000        pass       
+18         00000000        18         00000000        pass       
+452        00000000        452        00000000        pass       
+479        00000000        479        00000000        pass       
+249        00000000        249        00000000        pass       
+497        00000000        497        00000000        pass       
+80         00000000        80         00000000        pass       
+499        00000000        499        00000000        pass       
+57         00000000        57         00000000        pass       
+80         00000000        80         00000000        pass       
+456        00000000        456        00000000        pass       
+220        00000000        220        00000000        pass       
+67         00000000        67         00000000        pass       
+257        00000000        257        00000000        pass       
+258        00000000        258        00000000        pass       
+228        00000000        228        00000000        pass       
+58         00000000        58         00000000        pass       
+183        00000000        183        00000000        pass       
+44         00000000        44         00000000        pass       
+75         00000000        75         00000000        pass       
+35         00000000        35         00000000        pass       
+266        00000000        266        00000000        pass       
+497        f8d30000        497        f8d30000        pass       
+340        f8d30000        340        f8d30000        pass       
+387        f8d30000        387        f8d30000        pass       
+486        f8d30000        486        f8d30000        pass       
+365        f8d30000        365        f8d30000        pass       
+96         f8d30000        96         f8d30000        pass       
+174        f8d30000        174        f8d30000        pass       
+235        f8d30000        235        f8d30000        pass       
+143        f8d30000        143        f8d30000        pass       
+49         00000000        49         00000000        pass       
+282        00000000        282        00000000        pass       
+183        00000000        183        00000000        pass       
+494        00000000        494        00000000        pass       
+48         00000000        48         00000000        pass       
+139        00000000        139        00000000        pass       
+390        00000000        390        00000000        pass       
+196        00000000        196        00000000        pass       
+463        00000000        463        00000000        pass       
+116        00000000        116        00000000        pass       
+48         00c5f25f        48         00c5f25f        pass       
+267        00000000        267        00000000        pass       
+469        00000000        469        00000000        pass       
+100        00000000        100        00000000        pass       
+489        00000000        489        00000000        pass       
+364        00000000        364        00000000        pass       
+448        00000000        448        00000000        pass       
+466        00000000        466        00000000        pass       
+211        00000000        211        00000000        pass       
+8          00000000        8          00000000        pass       
+247        00000000        247        00000000        pass       
+300        00000000        300        00000000        pass       
+198        00000000        198        00000000        pass       
+187        00000000        187        00000000        pass       
+267        2e00b75d        267        2e00b75d        pass       
+374        2e00b75d        374        2e00b75d        pass       
+331        2e00b75d        331        2e00b75d        pass       
+236        2e00b75d        236        2e00b75d        pass       
+434        2e00b75d        434        2e00b75d        pass       
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verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd
new file mode 100644
index 0000000..5018e38
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/simulation.vcd
@@ -0,0 +1,40667 @@
+$date
+	Wed Nov 24 03:19:06 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_1rw_tb $end
+$var wire 32 ! RData_pck_sram [31:0] $end
+$var reg 9 " RAddr_pck [8:0] $end
+$var reg 32 # RData_pck_golden [31:0] $end
+$var reg 9 $ WAddr_pck [8:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 pass [31:0] $end
+$var integer 32 3 q [31:0] $end
+$var integer 32 4 r [31:0] $end
+$var integer 32 5 rep_fd [31:0] $end
+$scope module ram_1rw $end
+$var wire 9 6 addr [8:0] $end
+$var wire 9 7 addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 8 csb $end
+$var wire 1 9 csb1 $end
+$var wire 32 : din [31:0] $end
+$var wire 1 ; web $end
+$var wire 4 < wmask [3:0] $end
+$var wire 2 = Addr_sel_1 [1:0] $end
+$var wire 2 > Addr_sel [1:0] $end
+$var reg 32 ? RData_out [31:0] $end
+$var reg 32 @ RData_out_1 [31:0] $end
+$var reg 2 A Raddr_sel [1:0] $end
+$var reg 2 B Raddr_sel_1 [1:0] $end
+$var reg 32 C dout [31:0] $end
+$var reg 32 D dout1 [31:0] $end
+$var reg 1 E web_reg $end
+$var integer 32 F i [31:0] $end
+$var integer 32 G j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 H addr0 [7:0] $end
+$var wire 8 I addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 J csb0 $end
+$var wire 1 K csb1 $end
+$var wire 32 L din0 [31:0] $end
+$var wire 1 M web0 $end
+$var wire 4 N wmask0 [3:0] $end
+$var reg 8 O addr0_reg [7:0] $end
+$var reg 8 P addr1_reg [7:0] $end
+$var reg 1 Q csb0_reg $end
+$var reg 1 R csb1_reg $end
+$var reg 32 S din0_reg [31:0] $end
+$var reg 32 T dout0 [31:0] $end
+$var reg 32 U dout1 [31:0] $end
+$var reg 1 V web0_reg $end
+$var reg 4 W wmask0_reg [3:0] $end
+$var integer 32 X i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Y addr0 [7:0] $end
+$var wire 8 Z addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 [ csb0 $end
+$var wire 1 \ csb1 $end
+$var wire 32 ] din0 [31:0] $end
+$var wire 1 ^ web0 $end
+$var wire 4 _ wmask0 [3:0] $end
+$var reg 8 ` addr0_reg [7:0] $end
+$var reg 8 a addr1_reg [7:0] $end
+$var reg 1 b csb0_reg $end
+$var reg 1 c csb1_reg $end
+$var reg 32 d din0_reg [31:0] $end
+$var reg 32 e dout0 [31:0] $end
+$var reg 32 f dout1 [31:0] $end
+$var reg 1 g web0_reg $end
+$var reg 4 h wmask0_reg [3:0] $end
+$var integer 32 i i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope task genInitFiles $end
+$var reg 32 j DEPTH [31:0] $end
+$var reg 160 k FILEN [1:160] $end
+$var reg 256 l INITVAL [255:0] $end
+$var reg 1 m RAND $end
+$var reg 32 n WIDTH [31:0] $end
+$var reg 256 o ramdata [255:0] $end
+$var integer 32 p addr [31:0] $end
+$var integer 32 q hex_fd [31:0] $end
+$var integer 32 r mif_fd [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000000000000000000000100 r
+b10000000000000000000000000000011 q
+b1000000000 p
+b10100010001010101100011001000100 o
+b100000 n
+1m
+b0 l
+b110100101101110011010010111010001011111011100100110000101101101 k
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+xb
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+bx `
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+x^
+bx ]
+1\
+x[
+b0 Z
+bx Y
+b100000000 X
+bx W
+xV
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+bx T
+bx S
+1R
+xQ
+b0 P
+bx O
+bx N
+xM
+bx L
+1K
+xJ
+b0 I
+bx H
+b10 G
+b10 F
+xE
+bx D
+bx C
+b0 B
+bx A
+bx @
+bx ?
+bx >
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+bx <
+x;
+bx :
+19
+08
+b0 7
+bx 6
+b10000000000000000000000000000011 5
+bx 4
+b1000000000 3
+bx 2
+bx 1
+bx 0
+b1 /
+bx .
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+x,
+x+
+1*
+x)
+x(
+1'
+x&
+bx %
+bx $
+bx #
+bx "
+bx !
+$end
+#5
+1[
+0J
+b0 >
+1^
+b0 Y
+1M
+b101110 H
+b10 F
+b101110 6
+1;
+b101100010 $
+b111 -
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+b111 _
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+b10 .
+0&
+b11000110100100000001001010001101 %
+b11000110100100000001001010001101 :
+b11000110100100000001001010001101 L
+b11000110100100000001001010001101 ]
+0(
+0)
+b0 1
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+0,
+b1 0
+0'
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+b0 A
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+b11000110100100000001001010001101 d
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+b11000110100100000001001010001101 S
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+b1101 -
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+b11111000011000000010111011110000 %
+b11111000011000000010111011110000 :
+b11111000011000000010111011110000 L
+b11111000011000000010111011110000 ]
+0(
+0)
+0+
+0,
+b1 0
+0'
+#18
+b0 T
+#20
+b0 #
+b10 .
+b0 !
+b0 C
+b11111000011000000010111011110000 S
+b110111 O
+b1101 W
+b11111000011000000010111011110000 d
+b1101 h
+b0 ?
+b10 G
+1'
+#25
+b10111011 H
+b10 F
+b10111011 6
+b111001101 $
+b110 -
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+b110 _
+b10111011 "
+b10 .
+b11101111111101101001001011011111 %
+b11101111111101101001001011011111 :
+b11101111111101101001001011011111 L
+b11101111111101101001001011011111 ]
+0(
+0)
+0+
+0,
+b1 0
+0'
+#30
+b10 G
+b11101111111101101001001011011111 d
+b110 h
+b11101111111101101001001011011111 S
+b10111011 O
+b110 W
+1'
+#35
+b10010111 H
+b10 F
+b10010111 6
+b1011000 $
+b1100 -
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+b1100 N
+b1100 _
+b10010111 "
+b10 .
+0&
+b10000011010111011010001000000110 %
+b10000011010111011010001000000110 :
+b10000011010111011010001000000110 L
+b10000011010111011010001000000110 ]
+0(
+0)
+0+
+0,
+b1 0
+0'
+#40
+b10000011010111011010001000000110 S
+b10010111 O
+b1100 W
+b10000011010111011010001000000110 d
+b1100 h
+b10 G
+1'
+#45
+0[
+b1011101 Y
+1J
+b0 H
+b10 F
+b1 >
+b101011101 6
+b11000100 $
+b1110 -
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verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..1a195b3
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,121 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+        $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+     $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+integer i;
+initial
+    //if (IZERO)
+      for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule

verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh

diff --git a/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_1rw_2021-11-24_03-18-56/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile
new file mode 100644
index 0000000..dd9bae8
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/Makefile
@@ -0,0 +1,18 @@
+XRUN = xrun
+VCS  = vcs
+IV   = iverilog
+
+all: clean iverilog
+
+iverilog:
+	iverilog -o test sky130_sram_1kbyte_1rw1r_32x256_8.v ram* utils.vh
+	vvp test
+	rm -f *.mif *.hex *.vvp test
+	
+xrun:
+	xrun -gui -xprop F utils.vh sky130_sram_1kbyte_1rw1r_32x256_8.v ram* -access +rwc
+	
+clean:
+	rm -f *.mif *.hex *.vvp *.vcd *.txt test
+
+.PHONY: clean

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v
new file mode 100644
index 0000000..35c2bd5
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_1rw.v
@@ -0,0 +1,159 @@
+`include "utils.vh"
+module ram_generic_1rw
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 1 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter BASIC_DATA_WIDTH = 32,
+     parameter fixed_width = 0,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  inout vccd1,
+  inout vssd1,
+`endif
+  input  clk, // clock
+  input  csb, // active low chip select
+  input  web, // active low write control
+  input [NUM_WMASKS-1:0]  wmask, // write mask
+  input [ADDR_WIDTH-1:0]  addr,
+  input [DATA_WIDTH-1:0]  din,
+  output reg[DATA_WIDTH-1:0]  dout,
+  input clk1,
+  input csb1,
+  input [ADDR_WIDTH-1:0] addr1,
+  output reg [DATA_WIDTH-1:0] dout1);
+
+localparam ADDRW = ADDR_WIDTH; // address width
+localparam NUM_OF_BANKS = MEMD / BASIC_MODEL;
+localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width
+localparam horizontal_banks = DATA_WIDTH / BASIC_DATA_WIDTH;
+
+reg [DATA_WIDTH-1:0] RData_out;
+wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel; 
+reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0];
+reg wen [NUM_OF_BANKS-1:0];
+reg csb_i [NUM_OF_BANKS-1:0];
+reg web_reg;
+
+// port  2
+reg [DATA_WIDTH-1:0] RData_out_1;
+wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0];
+wire [$clog2(NUM_OF_BANKS):0] Addr_sel_1;
+reg  [$clog2(NUM_OF_BANKS):0] Raddr_sel_1;
+reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0];
+reg csb_i_1 [NUM_OF_BANKS-1:0];
+
+
+assign Addr_sel = addr / BASIC_MODEL;//addr % NUM_OF_BANKS;
+assign Addr_sel_1 = addr1 / BASIC_MODEL; 
+
+always @(posedge clk) begin
+Raddr_sel <= addr / BASIC_MODEL; // addr % NUM_OF_BANKS;
+Raddr_sel_1 <= addr1 / BASIC_MODEL;
+web_reg <= web;
+end
+
+integer i;
+integer j;
+
+ always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+	Addr[i] = (Addr_sel == i) ? addr : 0;
+        wen[i] = (Addr_sel == i) ? web : 1;
+	csb_i[i] = (Addr_sel == i) ? csb : 1;
+	end
+end
+
+always @* begin
+	for(i=0; i<NUM_OF_BANKS; i=i+1) begin
+        Addr_1[i] = (Addr_sel_1 == i) ? addr1 : 0;
+        csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1;
+	end
+end
+
+genvar p,h;
+generate
+	for(p=0; p<NUM_OF_BANKS; p=p+1) begin
+		if(fixed_width == 32'h00000001) begin
+			for(h=0; h<horizontal_banks; h=h+1) begin
+			
+			sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask[4*h +: 4]),
+					.addr0(Addr[p]),
+					.din0(din[BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+					.dout0(Rdata[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p][BASIC_DATA_WIDTH*h +: BASIC_DATA_WIDTH]));
+             		end
+             	end
+             	else begin
+             		sky130_sram_1kbyte_1rw1r_32x256_8 
+				ram_i ( `ifdef USE_POWER_PINS
+					.vccd1(vccd1),
+					.vssd1(vssd1),
+					`endif
+					.clk0(clk),
+					.csb0(csb_i[p]),
+					.web0(wen[p]),
+					.wmask0(wmask),
+					.addr0(Addr[p]),
+					.din0(din),
+					.dout0(Rdata[p]),
+               		        .clk1(clk1),
+               		        .csb1(csb_i_1[p]),
+               		        .addr1(Addr_1[p]),
+               		        .dout1(Rdata_1[p]));
+               end
+               	        
+	end
+endgenerate
+
+always @(posedge clk) begin
+        if(web_reg==1) begin
+	for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+	 RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out;
+	end
+        end
+        else
+         RData_out = RData_out;
+        // Port 2
+end
+always @(posedge clk) begin 
+        for(j=0; j<NUM_OF_BANKS; j=j+1) begin
+        //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1;
+	if(Raddr_sel_1 == j) 
+        RData_out_1 = Rdata_1[j];
+        else
+        RData_out_1 = RData_out_1;	
+	end
+end
+
+always @* begin
+dout = RData_out;
+end
+
+
+always @* begin 
+dout1 = RData_out_1;
+end
+
+endmodule
+
+

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v
new file mode 100644
index 0000000..95edafa
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w.v
@@ -0,0 +1,80 @@
+`include "utils.vh"
+module ram_generic_nr1w
+ #(  parameter NUM_WMASKS    = 4,
+     parameter MEMD = 512,
+     parameter DATA_WIDTH    = 32, // data width
+     parameter nRPORTS = 2 , // number of reading ports
+     parameter nWPORTS = 1, // number of write ports
+     parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
+     parameter IFILE   = "",  // initialization mif file (don't pass extension), optional
+     parameter BASIC_MODEL = 256,
+     parameter ADDR_WIDTH = 9,
+     parameter DELAY = 3,
+     parameter BYPASS = 1
+  )( `ifdef USE_POWER_PINS
+  vccd1,
+  vssd1,
+`endif
+  addr, clk, csb, web, wmask, din, dout, addr1, csb1, clk1, dout1);
+  `ifdef USE_POWER_PINS
+  inout vccd1;
+  inout vssd1;
+  `endif
+  input  clk; // clock
+  input  csb; // active low chip select
+  input  web; // active low write control
+  input [NUM_WMASKS-1:0]  wmask; // write mask
+  input [ADDR_WIDTH * nRPORTS-1:0] addr;
+  input [DATA_WIDTH-1:0]  din;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout;
+  input clk1;
+  input csb1;
+  input [ADDR_WIDTH * nRPORTS-1:0] addr1;
+  output reg [DATA_WIDTH*nRPORTS-1:0]  dout1;
+    // unpacked read addresses/data
+  reg  [ADDR_WIDTH-1:0] RAddr_upk [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk [nRPORTS-1:0]; // read data      - unpacked 2D array 
+  reg  [ADDR_WIDTH-1:0] RAddr_upk_1 [nRPORTS-1:0]; // read addresses - unpacked 2D array 
+  wire [DATA_WIDTH-1:0] RData_upk_1 [nRPORTS-1:0]; // read data      - unpacked 2D array 
+
+  // unpack read addresses; pack read data
+  `ARRINIT;
+  always @* begin
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr,RAddr_upk);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk,dout);
+    `ARR1D2D(nRPORTS,ADDR_WIDTH,addr1,RAddr_upk_1);
+    `ARR2D1D(nRPORTS,DATA_WIDTH,RData_upk_1,dout1);
+  end
+genvar rpi;
+  generate
+    for (rpi=0 ; rpi<nRPORTS; rpi=rpi+1) begin
+    ram_generic_1rw #( .NUM_WMASKS (NUM_WMASKS),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATA_WIDTH), // data width
+                    .nRPORTS(1), // number of reading ports
+      		    .nWPORTS(1), // number of write ports
+     		    .IZERO  (IZERO), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (IFILE),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDR_WIDTH),
+     		    .DELAY (DELAY),
+     		    .BYPASS(BYPASS))
+    ram_1rw      ( `ifdef USE_POWER_PINS
+    		    .vccd1(vccd1),
+    		    .vssd1(vssd1),
+    		    `endif
+    		    .clk(clk), // clock
+  		    .csb(csb), // active low chip select
+  		    .web(web), // active low write control
+  		    .wmask(wmask), // write mask
+  		    .addr(RAddr_upk[rpi]/*(web == 0) ? RAddr_upk[0] : RAddr_upk[rpi]*/),
+  		    .din(din),
+   		    .dout(RData_upk[rpi]),
+                    .clk1(clk1),
+                    .csb1(csb1), 
+                    .addr1(RAddr_upk_1[rpi]),
+                    .dout1(RData_upk_1[rpi]));
+    end
+  endgenerate
+endmodule
+

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v
new file mode 100644
index 0000000..49cb7a9
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/ram_generated_512x32_2r1w_tb.v
@@ -0,0 +1,289 @@
+`include "utils.vh"
+
+// set default value for the following parameters, if not defined from command-line
+// memory depth
+`ifndef WMASK
+`define WMASK   4
+`endif
+
+`ifndef MEMD
+`define MEMD   512
+`endif
+// data width
+`ifndef DATAW
+`define DATAW   32
+`endif
+// number of reading ports
+`ifndef nWPORTS
+`define nWPORTS 1
+`endif
+// number of writing ports
+`ifndef nRPORTS
+`define nRPORTS 2
+`endif
+// Simulation cycles count
+`ifndef CYCC
+`define CYCC 1000
+`endif
+
+`ifndef Basic_Model
+`define Basic_Model 256
+`endif
+
+`ifndef ADDRW 
+`define ADDRW 9
+`endif
+
+// WDW (Write-During-Write) protection
+`ifndef WDW
+`define WDW 0
+`endif
+
+// WAW (Write-After-Write) protection
+`ifndef WAW
+`define WAW 1
+`endif
+
+// RDW (Read-During-Write) protection
+`ifndef RDW
+`define RDW 1
+`endif
+
+// RAW (Read-After-Write) protection
+`ifndef RAW
+`define RAW 1
+`endif
+
+module ram_generic_nr1w_tb;
+
+  localparam MEMD    = `MEMD         ; // memory depth
+  localparam DATAW   = `DATAW        ; // data width
+  localparam nRPORTS = `nRPORTS      ; // number of reading ports
+  localparam nWPORTS = `nWPORTS      ; // number of writing ports
+  localparam CYCC    = `CYCC         ; // simulation cycles count
+  
+  localparam ADDRW  = `ADDRW; // address size
+  localparam VERBOSE = 0             ; // verbose logging (1:yes; 0:no)
+  localparam CYCT    = 10            ; // cycle      time
+  localparam RSTT    = 5.2*CYCT      ; // reset      time
+  localparam TERFAIL = 0             ; // terminate if fail?
+  localparam TIMEOUT = 2*CYCT*CYCC   ; // simulation time
+  localparam BASIC_MODEL = `Basic_Model;
+  reg                      clk = 1'b0                    ; // global clock
+  reg                      rst = 1'b1                    ; // global reset
+  reg  [nWPORTS-1:0      ] WEnb                          ; // write enable for each writing port
+  reg  [ADDRW*nWPORTS-1:0] WAddr_pck                     ; // write addresses - packed from nWPORTS write ports
+  reg  [ADDRW-1:0        ] WAddr_upk        [nWPORTS-1:0]; // write addresses - unpacked 2D array 
+  reg  [ADDRW*nRPORTS-1:0] RAddr_pck                     ; // read  addresses - packed from nRPORTS  read  ports
+  reg  [ADDRW-1:0        ] RAddr_upk        [nRPORTS-1:0]; // read  addresses - unpacked 2D array 
+  reg  [DATAW*nWPORTS-1:0] WData_pck                     ; // write data - packed from nWPORTS read ports
+  reg  [DATAW-1:0        ] WData_upk        [nWPORTS-1:0]; // write data - unpacked 2D array 
+  wire [DATAW*nRPORTS-1:0] RData_pck_sram             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_sram [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg [DATAW*nRPORTS-1:0] RData_pck_golden             ; // read  data - packed from nRPORTS read ports
+  reg  [DATAW-1:0        ] RData_upk_golden [nRPORTS-1:0]; // read  data - unpacked 2D array 
+  reg  [`WMASK*nWPORTS-1:0] wmask_pck	    		  ; // wmask packed
+  reg  [`WMASK-1:0        ] wmask_upk	     [nWPORTS-1:0]; // wmask unpacked
+  integer i,j; // general indeces
+
+ // generates random ram hex/mif initializing files
+  task genInitFiles;
+    input [31  :0] DEPTH  ; // memory depth
+    input [31  :0] WIDTH  ; // memoty width
+    input [255 :0] INITVAL; // initial vlaue (if not random)
+    input          RAND   ; // random value?
+    input [1:8*20] FILEN  ; // memory initializing file name
+    reg   [255 :0] ramdata;
+    integer addr,hex_fd,mif_fd;
+    begin
+      // open hex/mif file descriptors
+      hex_fd = $fopen({FILEN,".hex"},"w");
+      mif_fd = $fopen({FILEN,".mif"},"w");
+      // write mif header
+      $fwrite(mif_fd,"WIDTH         = %0d;\n",WIDTH);
+      $fwrite(mif_fd,"DEPTH         = %0d;\n",DEPTH);
+      $fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n"     );
+      $fwrite(mif_fd,"DATA_RADIX    = HEX;\n\n"   );
+      $fwrite(mif_fd,"CONTENT BEGIN\n"            );
+      // write random memory lines
+      for(addr=0;addr<DEPTH;addr=addr+1) begin
+        if (RAND) begin
+          `GETRAND(ramdata,WIDTH); 
+        end else ramdata = INITVAL;
+        $fwrite(hex_fd,"%0h\n",ramdata);
+        $fwrite(mif_fd,"  %0h :  %0h;\n",addr,ramdata);
+      end
+      // write mif tail
+      $fwrite(mif_fd,"END;\n");
+      // close hex/mif file descriptors
+      $fclose(hex_fd);
+      $fclose(mif_fd);
+    end
+  endtask
+  
+   
+  initial begin
+  	$dumpfile("srimulation.vcd");
+  	$dumpvars(0,ram_generic_nr1w_tb);
+  end
+
+  integer rep_fd, ferr;
+  initial begin
+    // write header
+    //rep_fd = $fopen("sim.txt","r"); // try to open report file for read
+    //$ferror(rep_fd,ferr);       // detect error
+    //$fclose(rep_fd);
+    rep_fd = $fopen("sim.txt","w"); // open report file for append
+    if (1) begin     // if file is new (can't open for read); write header
+      $fwrite(rep_fd,"===============================Simulation Results======================================\n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fwrite(rep_fd,"Golden   Golden     Golden          Actual       Actual     Actual          Result   \n");
+      $fwrite(rep_fd,"Read     Model      Model           Read         Model      Model                    \n");
+      $fwrite(rep_fd,"Port     RAddr      RData           Port         RAddr      RData                    \n");
+      $fwrite(rep_fd,"=======================================================================================\n");
+      $fclose(rep_fd);
+    end
+    $write("Simulating  RAM:\n");
+    $write("Write ports  : %0d\n"  ,nWPORTS  );
+    $write("Read ports   : %0d\n"  ,nRPORTS  );
+    $write("Data width   : %0d\n"  ,DATAW    );
+    $write("RAM depth    : %0d\n"  ,MEMD     );
+    $write("Address width: %0d\n",ADDRW    );
+    $write("Memory Size : %0d KB \n\n", (MEMD*DATAW)/8000);
+    // generate random ram hex/mif initializing file
+    genInitFiles(MEMD,DATAW   ,0,1,"init_ram");
+    // finish simulation
+    #(TIMEOUT) begin 
+      $write("*** Simulation terminated due to timeout\n");
+      $finish;
+    end
+  end
+
+// generate clock and reset
+  always  #(CYCT/2) clk = ~clk; // toggle clock
+  initial #(RSTT  ) rst = 1'b0; // lower reset
+
+  // pack/unpack data and addresses
+  `ARRINIT;
+  always @* begin
+    `ARR2D1D(nRPORTS,ADDRW,RAddr_upk        ,RAddr_pck        );
+    `ARR2D1D(nWPORTS,`WMASK,wmask_upk        ,wmask_pck        );
+    `ARR2D1D(nWPORTS,ADDRW,WAddr_upk        ,WAddr_pck        );
+    `ARR1D2D(nWPORTS,DATAW,WData_pck        ,WData_upk        );
+    `ARR1D2D(nRPORTS,DATAW,RData_pck_sram   ,RData_upk_sram   );
+    `ARR2D1D(nRPORTS,DATAW,RData_upk_golden ,RData_pck_golden );
+end
+
+  // register write addresses
+  reg  [ADDRW-1:0        ] WAddr_r_upk   [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array 
+  always @(negedge clk)
+    //WAddr_r_pck <= WAddr_pck;
+    for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
+
+  // generate random write data and random write/read addresses; on falling edge
+  reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
+  reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
+  reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
+  reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
+
+always @(negedge clk) begin
+    // generate random write addresses; different that current and previous write addresses
+     for (i=0;i<nWPORTS;i=i+1) begin
+      wdw_addr = 1; waw_addr = 1;
+      while (wdw_addr || waw_addr) begin
+        `GETRAND(WAddr_upk[i],ADDRW);
+        wdw_addr = 0; waw_addr = 0;
+        if (!`WDW) for (j=0;j<i      ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j]  );
+        if (!`WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+
+ // generate random read addresses; different that current and previous write addresses
+    for (i=0;i<nRPORTS;i=i+1) begin
+      rdw_addr = 1; raw_addr = 1;
+      while (rdw_addr || raw_addr) begin
+        `GETRAND(RAddr_upk[i],ADDRW);
+        `GETRAND(wmask_upk[i],      `WMASK); 
+        rdw_addr = 0; raw_addr = 0;
+        if (!`RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j]  );
+        if (!`RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
+      end
+    end
+  // generate random write data and write enables
+    `GETRAND(WData_pck,DATAW*nWPORTS);
+    `GETRAND(WEnb     ,      nWPORTS); 
+	if (rst) WEnb=1'b0; //else WEnb={nWPORTS{1'b1}};
+  end
+
+integer cycc=1; // cycles count
+integer pass;
+integer p;
+always @(negedge clk) begin
+    if (!rst) begin
+        #(CYCT/10) // a little after falling edge
+        #(CYCT/2) // a little after rising edge
+        
+        //if (cycc==CYCC) begin
+        for(p=0; p<nRPORTS; p=p+1) begin
+            pass = (RData_upk_golden[p]===RData_upk_sram[p]);
+    	    rep_fd = $fopen("sim.txt","a+");
+            $fwrite(rep_fd,"%-10d %-10d %-15h %-10d %-10d %-15h %-10s \n",p,RAddr_upk[p],RData_upk_golden[p],p,RAddr_upk[p],RData_upk_sram[p],pass?"pass":"fail");
+            $fclose(rep_fd);
+        end
+        if (cycc==CYCC) begin
+	$finish;
+	end
+        cycc=cycc+1;
+    end
+end
+
+// Golden model of SRAM
+integer q,r,s;
+reg [DATAW-1:0] mem [0:MEMD-1];
+initial begin
+//      $readmemh("init_ram.hex", mem);
+        for(r=0; r<MEMD; r=r+1) mem[r] = {DATAW{1'b0}};
+end
+always @(posedge clk)
+  begin
+    if(WEnb) begin
+    	for(s=0; s<`WMASK; s=s+1) begin
+    		if(wmask_pck[s])
+        		mem[WAddr_pck][8*s +: 8] = WData_pck[8*s +: 8];
+    	end
+    end
+   else begin
+      for(q=0; q<nRPORTS; q=q+1) begin
+        RData_upk_golden[q] <= #(10) mem[RAddr_upk[q]];
+      end
+   end
+  end
+
+
+ram_generic_nr1w #( .NUM_WMASKS (`WMASK),
+     		    .MEMD(MEMD),
+     		    .DATA_WIDTH(DATAW), // data width
+                    .nRPORTS(nRPORTS), // number of reading ports
+     		    .nWPORTS(nWPORTS), // number of write ports
+     		    .IZERO  (1), // binary / Initial RAM with zeros (has priority over IFILE)
+    		    .IFILE   (""),  // initialization mif file (don't pass extension), optional
+     		    .BASIC_MODEL (BASIC_MODEL),
+         	    .ADDR_WIDTH(ADDRW),
+     		    .DELAY (3))
+ram_nr1w          ( `ifdef USE_POWER_PINS
+		    .vccd1(vccd1),
+		    .vssd1(vssd1),
+		    `endif
+		    .clk(clk), // clock
+  		    .csb(1'b0), // active low chip select
+  		    .web(~WEnb), // active low write control
+  		    .wmask(wmask_pck), // write mask
+		    .addr((WEnb==1'b1)? {nRPORTS{WAddr_pck}}:RAddr_pck),
+  		    .din(WData_pck),
+   		    .dout(RData_pck_sram),
+                    .clk1(clk),
+                    .csb1(1'b1),
+                    .addr1({ADDRW*nRPORTS{1'b0}}),
+                    .dout1());
+endmodule
+

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt
new file mode 100644
index 0000000..405adfa
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sim.txt
@@ -0,0 +1,2006 @@
+===============================Simulation Results======================================
+=======================================================================================
+Golden   Golden     Golden          Actual       Actual     Actual          Result   
+Read     Model      Model           Read         Model      Model                    
+Port     RAddr      RData           Port         RAddr      RData                    
+=======================================================================================
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verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100755
index 0000000..1a195b3
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,121 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+        $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+     $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+integer i;
+initial
+    //if (IZERO)
+      for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    //else
+      //if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
+      
+      
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule

verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd
new file mode 100644
index 0000000..a0d44da
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/srimulation.vcd
@@ -0,0 +1,69464 @@
+$date
+	Wed Nov 24 03:18:48 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ram_generic_nr1w_tb $end
+$var wire 64 ! RData_pck_sram [63:0] $end
+$var reg 18 " RAddr_pck [17:0] $end
+$var reg 64 # RData_pck_golden [63:0] $end
+$var reg 9 $ WAddr_pck [8:0] $end
+$var reg 32 % WData_pck [31:0] $end
+$var reg 1 & WEnb $end
+$var reg 1 ' clk $end
+$var reg 1 ( raw_addr $end
+$var reg 1 ) rdw_addr $end
+$var reg 1 * rst $end
+$var reg 1 + waw_addr $end
+$var reg 1 , wdw_addr $end
+$var reg 4 - wmask_pck [3:0] $end
+$var integer 32 . _i_ [31:0] $end
+$var integer 32 / cycc [31:0] $end
+$var integer 32 0 i [31:0] $end
+$var integer 32 1 j [31:0] $end
+$var integer 32 2 p [31:0] $end
+$var integer 32 3 pass [31:0] $end
+$var integer 32 4 q [31:0] $end
+$var integer 32 5 r [31:0] $end
+$var integer 32 6 rep_fd [31:0] $end
+$var integer 32 7 s [31:0] $end
+$scope module ram_nr1w $end
+$var wire 18 8 addr [17:0] $end
+$var wire 18 9 addr1 [17:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 < din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 > wmask [3:0] $end
+$var reg 64 ? dout [63:0] $end
+$var reg 64 @ dout1 [63:0] $end
+$var integer 32 A _i_ [31:0] $end
+$scope begin genblk1[0] $end
+$scope module ram_1rw $end
+$var wire 9 B addr [8:0] $end
+$var wire 9 C addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 D din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 E wmask [3:0] $end
+$var wire 2 F Addr_sel_1 [1:0] $end
+$var wire 2 G Addr_sel [1:0] $end
+$var reg 32 H RData_out [31:0] $end
+$var reg 32 I RData_out_1 [31:0] $end
+$var reg 2 J Raddr_sel [1:0] $end
+$var reg 2 K Raddr_sel_1 [1:0] $end
+$var reg 32 L dout [31:0] $end
+$var reg 32 M dout1 [31:0] $end
+$var reg 1 N web_reg $end
+$var integer 32 O i [31:0] $end
+$var integer 32 P j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 Q addr0 [7:0] $end
+$var wire 8 R addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 S csb0 $end
+$var wire 1 T csb1 $end
+$var wire 32 U din0 [31:0] $end
+$var wire 1 V web0 $end
+$var wire 4 W wmask0 [3:0] $end
+$var reg 8 X addr0_reg [7:0] $end
+$var reg 8 Y addr1_reg [7:0] $end
+$var reg 1 Z csb0_reg $end
+$var reg 1 [ csb1_reg $end
+$var reg 32 \ din0_reg [31:0] $end
+$var reg 32 ] dout0 [31:0] $end
+$var reg 32 ^ dout1 [31:0] $end
+$var reg 1 _ web0_reg $end
+$var reg 4 ` wmask0_reg [3:0] $end
+$var integer 32 a i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 b addr0 [7:0] $end
+$var wire 8 c addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 d csb0 $end
+$var wire 1 e csb1 $end
+$var wire 32 f din0 [31:0] $end
+$var wire 1 g web0 $end
+$var wire 4 h wmask0 [3:0] $end
+$var reg 8 i addr0_reg [7:0] $end
+$var reg 8 j addr1_reg [7:0] $end
+$var reg 1 k csb0_reg $end
+$var reg 1 l csb1_reg $end
+$var reg 32 m din0_reg [31:0] $end
+$var reg 32 n dout0 [31:0] $end
+$var reg 32 o dout1 [31:0] $end
+$var reg 1 p web0_reg $end
+$var reg 4 q wmask0_reg [3:0] $end
+$var integer 32 r i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope module ram_1rw $end
+$var wire 9 s addr [8:0] $end
+$var wire 9 t addr1 [8:0] $end
+$var wire 1 ' clk $end
+$var wire 1 ' clk1 $end
+$var wire 1 : csb $end
+$var wire 1 ; csb1 $end
+$var wire 32 u din [31:0] $end
+$var wire 1 = web $end
+$var wire 4 v wmask [3:0] $end
+$var wire 2 w Addr_sel_1 [1:0] $end
+$var wire 2 x Addr_sel [1:0] $end
+$var reg 32 y RData_out [31:0] $end
+$var reg 32 z RData_out_1 [31:0] $end
+$var reg 2 { Raddr_sel [1:0] $end
+$var reg 2 | Raddr_sel_1 [1:0] $end
+$var reg 32 } dout [31:0] $end
+$var reg 32 ~ dout1 [31:0] $end
+$var reg 1 !" web_reg $end
+$var integer 32 "" i [31:0] $end
+$var integer 32 #" j [31:0] $end
+$scope begin genblk1[0] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 $" addr0 [7:0] $end
+$var wire 8 %" addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 &" csb0 $end
+$var wire 1 '" csb1 $end
+$var wire 32 (" din0 [31:0] $end
+$var wire 1 )" web0 $end
+$var wire 4 *" wmask0 [3:0] $end
+$var reg 8 +" addr0_reg [7:0] $end
+$var reg 8 ," addr1_reg [7:0] $end
+$var reg 1 -" csb0_reg $end
+$var reg 1 ." csb1_reg $end
+$var reg 32 /" din0_reg [31:0] $end
+$var reg 32 0" dout0 [31:0] $end
+$var reg 32 1" dout1 [31:0] $end
+$var reg 1 2" web0_reg $end
+$var reg 4 3" wmask0_reg [3:0] $end
+$var integer 32 4" i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk1[1] $end
+$scope begin genblk4 $end
+$scope module ram_i $end
+$var wire 8 5" addr0 [7:0] $end
+$var wire 8 6" addr1 [7:0] $end
+$var wire 1 ' clk0 $end
+$var wire 1 ' clk1 $end
+$var wire 1 7" csb0 $end
+$var wire 1 8" csb1 $end
+$var wire 32 9" din0 [31:0] $end
+$var wire 1 :" web0 $end
+$var wire 4 ;" wmask0 [3:0] $end
+$var reg 8 <" addr0_reg [7:0] $end
+$var reg 8 =" addr1_reg [7:0] $end
+$var reg 1 >" csb0_reg $end
+$var reg 1 ?" csb1_reg $end
+$var reg 32 @" din0_reg [31:0] $end
+$var reg 32 A" dout0 [31:0] $end
+$var reg 32 B" dout1 [31:0] $end
+$var reg 1 C" web0_reg $end
+$var reg 4 D" wmask0_reg [3:0] $end
+$var integer 32 E" i [31:0] $end
+$scope begin MEM_READ0 $end
+$upscope $end
+$scope begin MEM_READ1 $end
+$upscope $end
+$scope begin MEM_WRITE0 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope task genInitFiles $end
+$var reg 32 F" DEPTH [31:0] $end
+$var reg 160 G" FILEN [1:160] $end
+$var reg 256 H" INITVAL [255:0] $end
+$var reg 1 I" RAND $end
+$var reg 32 J" WIDTH [31:0] $end
+$var reg 256 K" ramdata [255:0] $end
+$var integer 32 L" addr [31:0] $end
+$var integer 32 M" hex_fd [31:0] $end
+$var integer 32 N" mif_fd [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10000000000000000000000000000100 N"
+b10000000000000000000000000000011 M"
+b1000000000 L"
+b10100010001010101100011001000100 K"
+b100000 J"
+1I"
+b0 H"
+b110100101101110011010010111010001011111011100100110000101101101 G"
+b1000000000 F"
+b100000000 E"
+bx D"
+xC"
+bx B"
+bx A"
+bx @"
+x?"
+x>"
+bx ="
+bx <"
+bx ;"
+x:"
+bx 9"
+18"
+x7"
+b0 6"
+bx 5"
+b100000000 4"
+bx 3"
+x2"
+bx 1"
+bx 0"
+bx /"
+x."
+x-"
+bx ,"
+bx +"
+bx *"
+x)"
+bx ("
+1'"
+x&"
+b0 %"
+bx $"
+bx #"
+b10 ""
+x!"
+bx ~
+bx }
+bx |
+bx {
+bx z
+bx y
+bx x
+b0 w
+bx v
+bx u
+b0 t
+bx s
+b100000000 r
+bx q
+xp
+bx o
+bx n
+bx m
+xl
+xk
+bx j
+bx i
+bx h
+xg
+bx f
+1e
+xd
+b0 c
+bx b
+b100000000 a
+bx `
+x_
+bx ^
+bx ]
+bx \
+x[
+xZ
+bx Y
+bx X
+bx W
+xV
+bx U
+1T
+xS
+b0 R
+bx Q
+bx P
+b10 O
+xN
+bx M
+bx L
+bx K
+bx J
+bx I
+bx H
+bx G
+b0 F
+bx E
+bx D
+b0 C
+bx B
+b11 A
+bx @
+bx ?
+bx >
+x=
+bx <
+1;
+0:
+b0 9
+bx 8
+bx 7
+b10000000000000000000000000000011 6
+b1000000000 5
+bx 4
+bx 3
+bx 2
+bx 1
+bx 0
+b1 /
+bx .
+bx -
+x,
+x+
+1*
+x)
+x(
+0'
+x&
+bx %
+bx $
+bx #
+bx "
+bx !
+$end
+#5
+b0 K
+b0 |
+b0 Y
+1[
+b0 j
+1l
+b10 P
+b0 ,"
+1."
+b0 ="
+1?"
+b10 #"
+b10 4
+1'
+#10
+07"
+b10001101 5"
+1&"
+b0 $"
+b1 x
+1d
+b0 b
+0S
+b11101001 Q
+b0 G
+b110001101 s
+b11101001 B
+b11 A
+1g
+1V
+b10 O
+1:"
+1)"
+b10 ""
+b110001101011101001 8
+1=
+b101100010 $
+b1 -
+b1 >
+b1 E
+b1 W
+b1 h
+b1 v
+b1 *"
+b1 ;"
+b110001101011101001 "
+b11 .
+0&
+b11010101000111001011010010101010 %
+b11010101000111001011010010101010 <
+b11010101000111001011010010101010 D
+b11010101000111001011010010101010 U
+b11010101000111001011010010101010 f
+b11010101000111001011010010101010 u
+b11010101000111001011010010101010 ("
+b11010101000111001011010010101010 9"
+0(
+0)
+b0 1
+0+
+0,
+b1 0
+0'
+#15
+1!"
+b1 {
+1N
+b0 J
+b10 4
+b10 #"
+b11010101000111001011010010101010 @"
+b10001101 <"
+b1 D"
+1C"
+0>"
+b11010101000111001011010010101010 /"
+b0 +"
+b1 3"
+12"
+1-"
+b10 P
+b11010101000111001011010010101010 m
+b0 i
+b1 q
+1p
+1k
+b11010101000111001011010010101010 \
+b11101001 X
+b1 `
+1_
+0Z
+1'
+#20
+b11001101 5"
+b10 ""
+0d
+b11110000 b
+1S
+b0 Q
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+b1 G
+b111001101 s
+b111110000 B
+b11 A
+b111001101111110000 8
+b110111 $
+b1111 -
+b1111 >
+b1111 E
+b1111 W
+b1111 h
+b1111 v
+b1111 *"
+b1111 ;"
+b111001101111110000 "
+b11 .
+0&
+b1011101100000110110001110111011 %
+b1011101100000110110001110111011 <
+b1011101100000110110001110111011 D
+b1011101100000110110001110111011 U
+b1011101100000110110001110111011 f
+b1011101100000110110001110111011 u
+b1011101100000110110001110111011 ("
+b1011101100000110110001110111011 9"
+0(
+0)
+0+
+0,
+b10 0
+0'
+#23
+b0 A"
+b0 ]
+#25
+b0 #
+b1 J
+b11 .
+b0 !
+b0 ?
+b11 A
+b0 L
+b0 }
+b1011101100000110110001110111011 \
+b0 X
+b1111 `
+1Z
+b1011101100000110110001110111011 m
+b11110000 i
+b1111 q
+0k
+b0 H
+b10 P
+b1011101100000110110001110111011 /"
+b1111 3"
+b1011101100000110110001110111011 @"
+b11001101 <"
+b1111 D"
+b0 y
+b10 #"
+b10 4
+1'
+#30
+17"
+b0 5"
+0&"
+b10010111 $"
+b10 ""
+b0 x
+1d
+b0 b
+0S
+b1011000 Q
+b10 O
+b0 G
+b10010111 s
+b1011000 B
+b11 A
+b10010111001011000 8
+b1111101 $
+b1100 -
+b1100 >
+b1100 E
+b1100 W
+b1100 h
+b1100 v
+b1100 *"
+b1100 ;"
+b10010111001011000 "
+b11 .
+b10010100101000010010111000101001 %
+b10010100101000010010111000101001 <
+b10010100101000010010111000101001 D
+b10010100101000010010111000101001 U
+b10010100101000010010111000101001 f
+b10010100101000010010111000101001 u
+b10010100101000010010111000101001 ("
+b10010100101000010010111000101001 9"
+0(
+0)
+0+
+0,
+b1 0
+0'
+#33
+b0 n
+#35
+b0 {
+b0 J
+b10 4
+b10 #"
+b10010100101000010010111000101001 @"
+b0 <"
+b1100 D"
+1>"
+b10010100101000010010111000101001 /"
+b10010111 +"
+b1100 3"
+0-"
+b10 P
+b10010100101000010010111000101001 m
+b0 i
+b1100 q
+1k
+b10010100101000010010111000101001 \
+b1011000 X
+b1100 `
+0Z
+1'
+#40
+b1110011 $"
+b10 ""
+0d
+b1011101 b
+1S
+b0 Q
+b10 O
+b1 G
+b1110011 s
+b101011101 B
+b11 A
+b1110011101011101 8
+b111010111 $
+b10 -
+b10 >
+b10 E
+b10 W
+b10 h
+b10 v
+b10 *"
+b10 ;"
+b1110011101011101 "
+b11 .
+b10100111000000110111010001001110 %
+b10100111000000110111010001001110 <
+b10100111000000110111010001001110 D
+b10100111000000110111010001001110 U
+b10100111000000110111010001001110 f
+b10100111000000110111010001001110 u
+b10100111000000110111010001001110 ("
+b10100111000000110111010001001110 9"
+0(
+0)
+0+
+0,
+b10 0
+0'
+#43
+b0 0"
+#45
+b1 J
+b10100111000000110111010001001110 \
+b0 X
+b10 `
+1Z
+b10100111000000110111010001001110 m
+b1011101 i
+b10 q
+0k
+b10 P
+b10100111000000110111010001001110 /"
+b1110011 +"
+b10 3"
+b10100111000000110111010001001110 @"
+b10 D"
+b10 #"
+b10 4
+1'
+#50
+b110001 $"
+b10 ""
+b111001 b
+b10 O
+b110001 s
+b100111001 B
+b11 A
+b110001100111001 8
+b111100000 $
+b100 -
+b100 >
+b100 E
+b100 W
+b100 h
+b100 v
+b100 *"
+b100 ;"
+b110001100111001 "
+b11 .
+0&
+b1111111010100110111110111111110 %
+b1111111010100110111110111111110 <
+b1111111010100110111110111111110 D
+b1111111010100110111110111111110 U
+b1111111010100110111110111111110 f
+b1111111010100110111110111111110 u
+b1111111010100110111110111111110 ("
+b1111111010100110111110111111110 9"
+0(
+0)
+0+
+0,
+b1 0
+0'
+#52
+0*
+#55
+b10 4
+b10 #"
+b1111111010100110111110111111110 @"
+b100 D"
+b1111111010100110111110111111110 /"
+b110001 +"
+b100 3"
+b10 P
+b1111111010100110111110111111110 m
+b111001 i
+b100 q
+b1111111010100110111110111111110 \
+b100 `
+1'
+#60
+b1010110 $"
+b10 ""
+1d
+b0 b
+0S
+b110011 Q
+b10 O
+b0 G
+b1010110 s
+b110011 B
+b11 A
+b1010110000110011 8
+b100001111 $
+b11 -
+b11 >
+b11 E
+b11 W
+b11 h
+b11 v
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verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh

diff --git a/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh
new file mode 100644
index 0000000..6a8c518
--- /dev/null
+++ b/verilog/rtl/rams/ram_512x32_2r1w_2021-11-24_03-18-38/utils.vh
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
+//                                                                                //
+// Redistribution  and  use  in  source   and  binary  forms,   with  or  without //
+// modification,  are permitted  provided that  the following conditions are met: //
+//   * Redistributions   of  source   code  must  retain   the   above  copyright //
+//     notice,  this   list   of   conditions   and   the  following  disclaimer. //
+//   * Redistributions  in  binary  form  must  reproduce  the  above   copyright //
+//     notice, this  list  of  conditions  and the  following  disclaimer in  the //
+//     documentation and/or  other  materials  provided  with  the  distribution. //
+//   * Neither the name of the University of British Columbia (UBC) nor the names //
+//     of   its   contributors  may  be  used  to  endorse  or   promote products //
+//     derived from  this  software without  specific  prior  written permission. //
+//                                                                                //
+// THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
+// AND  ANY EXPRESS  OR IMPLIED WARRANTIES,  INCLUDING,  BUT NOT LIMITED TO,  THE //
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
+// DISCLAIMED.  IN NO  EVENT SHALL University of British Columbia (UBC) BE LIABLE //
+// FOR ANY DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL //
+// DAMAGES  (INCLUDING,  BUT NOT LIMITED TO,  PROCUREMENT OF  SUBSTITUTE GOODS OR //
+// SERVICES;  LOSS OF USE,  DATA,  OR PROFITS;  OR BUSINESS INTERRUPTION) HOWEVER //
+// CAUSED AND ON ANY THEORY OF LIABILITY,  WHETHER IN CONTRACT, STRICT LIABILITY, //
+// OR TORT  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
+// OF  THIS SOFTWARE,  EVEN  IF  ADVISED  OF  THE  POSSIBILITY  OF  SUCH  DAMAGE. //
+////////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////////
+//                    utils.vh: Design utilities (pre-compile)                    //
+//                                                                                //
+//    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    //
+// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
+////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef __UTILS_VH__
+`define __UTILS_VH__
+
+`define DEBUG_MODE // debug mode, comment this line for other modes
+`define VERBOSE    // verbose debug, comment this line for other modes
+
+// Initiate Array structure - use once before calling packing/unpacking modules
+`define ARRINIT integer _i_,_j_
+// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial
+`define ARR2D1D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1]
+`define ARR1D2D(D1W,D2W,    SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1)                                 DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W]
+`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W]
+`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1]
+
+// print a 2-D array in a comma-delimited list
+`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",")
+// Initialize a vector with a specific width random number; extra bits are zero padded
+`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32))
+
+// factorial (n!)
+`define fact(n)  ( ( ((n) >= 2      ) ? 2  : 1) * \
+                   ( ((n) >= 3      ) ? 3  : 1) * \
+                   ( ((n) >= 4      ) ? 4  : 1) * \
+                   ( ((n) >= 5      ) ? 5  : 1) * \
+                   ( ((n) >= 6      ) ? 6  : 1) * \
+                   ( ((n) >= 7      ) ? 7  : 1) * \
+                   ( ((n) >= 8      ) ? 8  : 1) * \
+                   ( ((n) >= 9      ) ? 9  : 1) * \
+                   ( ((n) >= 10     ) ? 10 : 1)   )
+
+// ceiling of log2
+`define log2(x)  ( ( ((x) >  1      ) ? 1  : 0) + \
+                   ( ((x) >  2      ) ? 1  : 0) + \
+                   ( ((x) >  4      ) ? 1  : 0) + \
+                   ( ((x) >  8      ) ? 1  : 0) + \
+                   ( ((x) >  16     ) ? 1  : 0) + \
+                   ( ((x) >  32     ) ? 1  : 0) + \
+                   ( ((x) >  64     ) ? 1  : 0) + \
+                   ( ((x) >  128    ) ? 1  : 0) + \
+                   ( ((x) >  256    ) ? 1  : 0) + \
+                   ( ((x) >  512    ) ? 1  : 0) + \
+                   ( ((x) >  1024   ) ? 1  : 0) + \
+                   ( ((x) >  2048   ) ? 1  : 0) + \
+                   ( ((x) >  4096   ) ? 1  : 0) + \
+                   ( ((x) >  8192   ) ? 1  : 0) + \
+                   ( ((x) >  16384  ) ? 1  : 0) + \
+                   ( ((x) >  32768  ) ? 1  : 0) + \
+                   ( ((x) >  65536  ) ? 1  : 0) + \
+                   ( ((x) >  131072 ) ? 1  : 0) + \
+                   ( ((x) >  262144 ) ? 1  : 0) + \
+                   ( ((x) >  524288 ) ? 1  : 0) + \
+                   ( ((x) >  1048576) ? 1  : 0) + \
+                   ( ((x) >  2097152) ? 1  : 0) + \
+                   ( ((x) >  4194304) ? 1  : 0)   )
+
+// floor of log2
+`define log2f(x) ( ( ((x) >= 2      ) ? 1  : 0) + \
+                   ( ((x) >= 4      ) ? 1  : 0) + \
+                   ( ((x) >= 8      ) ? 1  : 0) + \
+                   ( ((x) >= 16     ) ? 1  : 0) + \
+                   ( ((x) >= 32     ) ? 1  : 0) + \
+                   ( ((x) >= 64     ) ? 1  : 0) + \
+                   ( ((x) >= 128    ) ? 1  : 0) + \
+                   ( ((x) >= 256    ) ? 1  : 0) + \
+                   ( ((x) >= 512    ) ? 1  : 0) + \
+                   ( ((x) >= 1024   ) ? 1  : 0) + \
+                   ( ((x) >= 2048   ) ? 1  : 0) + \
+                   ( ((x) >= 4096   ) ? 1  : 0) + \
+                   ( ((x) >= 8192   ) ? 1  : 0) + \
+                   ( ((x) >= 16384  ) ? 1  : 0) + \
+                   ( ((x) >= 32768  ) ? 1  : 0) + \
+                   ( ((x) >= 65536  ) ? 1  : 0) + \
+                   ( ((x) >= 131072 ) ? 1  : 0) + \
+                   ( ((x) >= 262144 ) ? 1  : 0) + \
+                   ( ((x) >= 524288 ) ? 1  : 0) + \
+                   ( ((x) >= 1048576) ? 1  : 0) + \
+                   ( ((x) >= 2097152) ? 1  : 0) + \
+                   ( ((x) >= 4194304) ? 1  : 0)   )
+
+`endif //__UTILS_VH__

verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v

diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
new file mode 100644
index 0000000..4048ea8
--- /dev/null
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+    vccd1,
+    vssd1,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 4 ;
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vccd1;
+    inout vssd1;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //#(T_HOLD) dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+         $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    //#(T_HOLD) dout1 = 32'bx;
+    if ( !csb1_reg && VERBOSE ) 
+      $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..969d635 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -15,6 +15,7 @@
 
 // Include caravel global defines for the number of the user project IO pads 
 `include "defines.v"
+
 `define USE_POWER_PINS
 
 `ifdef GL
@@ -23,6 +24,18 @@
     `include "gl/user_project_wrapper.v"
     `include "gl/user_proj_example.v"
 `else
+    
+   // for netlist verification
+   // `include "../gl/user_project_wrapper.v"
+   // `include "../gl/user_proj_example.v"
+   
+  // for rtl verification
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
-`endif
\ No newline at end of file
+    `include "rams/ram_256x32_2r1w/utils.vh"
+    `include "rams/ram_256x32_2r1w/ram_generated_256x32_2r1w.v"
+    `include "rams/ram_256x32_2r1w/ram_generated_256x32_1rw.v"
+    `include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+    
+    
+`endif

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..6101828 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -64,102 +64,132 @@
     input  [`MPRJ_IO_PADS-1:0] io_in,
     output [`MPRJ_IO_PADS-1:0] io_out,
     output [`MPRJ_IO_PADS-1:0] io_oeb,
-
+ 
+    
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+    
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+    
     // IRQ
-    output [2:0] irq
+    output [2:0] user_irq
 );
     wire clk;
     wire rst;
+    reg csb0;
+    reg csb1;
+    reg web; 
+    wire [15:0] addr;
+    wire [31:0] din;
+    wire [63:0] dout0;
+    wire [31:0] dout1;
 
-    wire [`MPRJ_IO_PADS-1:0] io_in;
-    wire [`MPRJ_IO_PADS-1:0] io_out;
-    wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
-    wire [31:0] rdata; 
-    wire [31:0] wdata;
-    wire [BITS-1:0] count;
-
-    wire valid;
-    wire [3:0] wstrb;
-    wire [31:0] la_write;
 
     // WB MI A
-    assign valid = wbs_cyc_i && wbs_stb_i; 
-    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    assign wbs_dat_o = rdata;
-    assign wdata = wbs_dat_i;
+    assign wbs_ack_o = 1'b0; // Unused
+    assign wbs_dat_o = 32'h00000000;  // Unused
+
 
     // IO
-    assign io_out = count;
-    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
+    //assign io_out[35:8] = (| lsu_axi_wstrb[3:0]) ? lsu_axi_wdata[27:0] : (| lsu_axi_wstrb[7:4]) ? lsu_axi_wdata[59:32] : {28{1'b0}};
+    
+    // io_oeb 0 for output 1 for input
+    
+    assign io_oeb[3:0]  = 4'hf;
+    assign io_oeb[4]    = 1'b0;
+    assign io_oeb[6:5]  = 2'b01;
+    assign io_oeb[7]    = 1'b0;
+    assign io_oeb[8]    = 1'b1; // csb0 for M0
+    assign io_oeb[9]    = 1'b1; // csb1 for M1
+    assign io_oeb[10]    = 1'b1; // web
+    assign io_oeb[26:11]    = 16'hFFFF; // addr
+    assign io_oeb[34:27]    = 8'h00; // data out
+    assign io_oeb[35]    = 1'b1; // output selector // if 0 so output will map on la_data if 1 so will map on io ports
     // IRQ
-    assign irq = 3'b000;	// Unused
+    assign user_irq = 3'b000;	// Unused
 
-    // LA
-    assign la_data_out = {{(127-BITS){1'b0}}, count};
-    // Assuming LA probes [63:32] are for controlling the count register  
-    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
-    // Assuming LA probes [65:64] are for controlling the count clk & reset  
-    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
-    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
 
-    counter #(
-        .BITS(BITS)
-    ) counter(
-        .clk(clk),
-        .reset(rst),
-        .ready(wbs_ack_o),
-        .valid(valid),
-        .rdata(rdata),
-        .wdata(wbs_dat_i),
-        .wstrb(wstrb),
-        .la_write(la_write),
-        .la_input(la_data_in[63:32]),
-        .count(count)
+    // Assuming LA probes [65:64] are for controlling the clk & reset  
+    assign clk = (~la_oenb[65]) ? la_data_in[65] :  wb_clk_i;
+    assign rst = (~la_oenb[64]) ? la_data_in[64] :  wb_rst_i;
+    always @(negedge clk) begin
+    	csb0 <= (~la_oenb[0]) ? la_data_in[0] : io_in[8];
+    	csb1 <= (~la_oenb[1]) ? la_data_in[1] : io_in[9];
+    	web <= (~la_oenb[2]) ? la_data_in[2] : io_in[10];
+    end
+    assign addr = (~la_oenb[18:3]) ? la_data_in[18:3] : io_in[26:11];
+    assign din = la_data_in[50:19];    
+    assign la_data_out[97:66] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[31:0] : (csb1 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout1 : 32'h00000000;
+    assign la_data_out[61:52] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[41:32] : 10'h000;
+    assign la_data_out[119:98] = (csb0 == 1'b0 & web == 1'b1 & ~io_in[35]) ? dout0[63:42] : 22'h000000;
+    assign io_out[34:27] = (csb0 == 1'b0 & web == 1'b1 & io_in[35]) ? {dout0[35:32],dout0[3:0]} : (csb1 == 1'b0 & web == 1'b1 & io_in[35]) ? dout1[7:0] : 8'h00;
+    
+
+    
+    /*always @posedge(clk) begin
+    if(rst) begin
+    state <= 2'b00; // IDLE
+    end
+    else begin
+    state <= next_state;
+    end
+    */
+    /*// IDLE = 3'b000, READ_M1 = 3'b001, WRITE_M1 = 3'b010, READ_M2 = 3'b011, WRITE_M2 = 3'b100, COMPLETE = 3'b101 
+    case(state) begin
+    3'b000 : begin
+            next_state = (csb0==1'b0 & web == 1'b1) ? 3'b001 : (csb0==1'b0 & web == 1'b0) ? 3'b010 : (csb1==1'b0 & web == 1'b1) ? 3'b011 : (csb1==1'b0 & web == 1'b0) ? 3'b100 : 3'b00;
+     	     wmask <= 4'h0;
+     	     din <= 32'h00000000;
+     	     count <= 3'h0;      
+            end
+            
+     3'b001 : begin
+     	     next_state = (count <= 3'h7) : 3'b101 :  
+      */ 
+              
+   //=========================================================================-
+   // RTL instance
+   //=========================================================================-
+
+ram_generic_nr1w 
+ram_2r1w_256x32 ( `ifdef USE_POWER_PINS
+    .vccd1		     ( vccd1	      ),
+    .vssd1                   ( vssd1         ),
+  `endif
+    .clk(clk),
+    .csb(csb0),
+    .web(web),
+    .wmask(4'hF),
+    .din(din),
+    .addr(addr),
+    .dout(dout0),
+    .addr1(addr), 
+    .csb1(1'b1),
+    .clk1(clk), 
+    .dout1()
     );
 
+sky130_sram_1kbyte_1rw1r_32x256_8 sram (`ifdef USE_POWER_PINS
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+`endif
+					 .clk0(clk),
+					 .csb0(csb1),
+					 .web0(web),
+					 .wmask0(4'hf),
+					 .addr0(addr[7:0]),
+					 .din0(din),
+					 .dout0(dout1),
+    					 .clk1(clk),
+    					 .csb1(1'b1),
+    					 .addr1(addr[7:0]),
+    					 .dout1() 
+    					 );				 
 endmodule
 
-module counter #(
-    parameter BITS = 32
-)(
-    input clk,
-    input reset,
-    input valid,
-    input [3:0] wstrb,
-    input [BITS-1:0] wdata,
-    input [BITS-1:0] la_write,
-    input [BITS-1:0] la_input,
-    output ready,
-    output [BITS-1:0] rdata,
-    output [BITS-1:0] count
-);
-    reg ready;
-    reg [BITS-1:0] count;
-    reg [BITS-1:0] rdata;
 
-    always @(posedge clk) begin
-        if (reset) begin
-            count <= 0;
-            ready <= 0;
-        end else begin
-            ready <= 1'b0;
-            if (~|la_write) begin
-                count <= count + 1;
-            end
-            if (valid && !ready) begin
-                ready <= 1'b1;
-                rdata <= count;
-                if (wstrb[0]) count[7:0]   <= wdata[7:0];
-                if (wstrb[1]) count[15:8]  <= wdata[15:8];
-                if (wstrb[2]) count[23:16] <= wdata[23:16];
-                if (wstrb[3]) count[31:24] <= wdata[31:24];
-            end else if (|la_write) begin
-                count <= la_write & la_input;
-            end
-        end
-    end
-
-endmodule
 `default_nettype wire

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..71cf59f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -113,9 +113,15 @@
     .io_in (io_in),
     .io_out(io_out),
     .io_oeb(io_oeb),
+    
+    // analog
+    .analog_io(analog_io),
+    
+    // Independent clock
+    .user_clock2(user_clock2),
 
     // IRQ
-    .irq(user_irq)
+    .user_irq(user_irq)
 );
 
 endmodule	// user_project_wrapper