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foss-eda-tools / third_party / shuttle / sky130 / mpw-004 / slot-005 / 435570185d44367fcce5f01f4f53939fa5c85826
commit435570185d44367fcce5f01f4f53939fa5c85826[log] [tgz]
authorHamzaShabbir517 <53592110+HamzaShabbir517@users.noreply.github.com>Sun Jun 13 08:39:10 2021 +0500
committerGitHub <noreply@github.com>Sun Jun 13 08:39:10 2021 +0500
treeadff7415e200787380f6c7e38a393a0b9187342a
parenteee2e552bde2e29930b9c4472713412f36f9234b [diff]
Update README.md
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tree: adff7415e200787380f6c7e38a393a0b9187342a
  1. .github/
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  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
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  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

BrqRV EB1 RISC-V Core 1.0 from MERL

This repository contains the brqrv eb1 Core design RTL. Brqrv Eb1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline

Block Diagram

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The BrqRV_EB1 Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
|           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
|           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex file folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── BrqRV_EB1                    #   User Design Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── BrqRV_EB1                       #    User Design def

├── lef                                 #    lef Directory
│   ├── BrqRV_EB1                       #    User Design lef

├── gds                                 #    gds Directory
│   ├── BrqRV_EB1                       #    User Design gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

  1. Set the GCC_PATH environment variable.
  2. Set the PDK_PATH environment variable.
  3. Copy the given program hex file into uart.hex.
  4. run the make commad for RTL simulation
  5. run the SIM=GL make command for netlist simulation