commit 2bc66bc70a18806e9bb1b440a295c92d69d5b40e
author hamzashabbir517 <shabbirhamza517@gmail.com> Thu Jun 10 05:37:43 2021 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Thu Jun 10 05:37:43 2021 +0500
tree 6a7583e3be6cef61ac6c69e0f7baed9a7060adc4
parent 641bdf632dfcceb153aecbc60ccdf790287704ec

Added Project Files

verilog/rtl/BrqRV_EB1/design/iccm_controller.v

diff --git a/verilog/rtl/BrqRV_EB1/design/iccm_controller.v b/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
index 611396f..c28bc9d 100644
--- a/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
+++ b/verilog/rtl/BrqRV_EB1/design/iccm_controller.v
@@ -82,7 +82,7 @@
 	always @(posedge clk_i or negedge rst_ni)
 		if (!rst_ni) begin
 			we_q <= 1'b0;
-			addr_q <= 13'b0000000000000;
+			addr_q <= 14'b00000000000000;
 			rx_byte_q0 <= 8'b00000000;
 			rx_byte_q1 <= 8'b00000000;
 			rx_byte_q2 <= 8'b00000000;

verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v

diff --git a/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v b/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
index 611396f..c28bc9d 100644
--- a/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
+++ b/verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v
@@ -82,7 +82,7 @@
 	always @(posedge clk_i or negedge rst_ni)
 		if (!rst_ni) begin
 			we_q <= 1'b0;
-			addr_q <= 13'b0000000000000;
+			addr_q <= 14'b00000000000000;
 			rx_byte_q0 <= 8'b00000000;
 			rx_byte_q1 <= 8'b00000000;
 			rx_byte_q2 <= 8'b00000000;