Update
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 99185a5..331c80b 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -91,9 +91,18 @@
wait(mprj_io_0 == 28'd30);
*/
// Observe Output pins [35:8] for mean & Determinant
- wait(mprj_io_0 == 28'd5);
- //wait(mprj_io_0 == 28'd7);
+ //wait(mprj_io_0 == 28'd5);
+ // Observe Output pins [35:8] for power
+ //wait(mprj_io_0 == 28'd64);
+
+ // Observe Output pins [35:8] for flip number
+ //wait(mprj_io_0 == 28'd4889874);
+
+ // Observe Output pins [35:8] for Queue
+ wait(mprj_io_0 == 28'd5);
+ wait(mprj_io_0 == 28'd6);
+ wait(mprj_io_0 == 28'd7);
$display("MPRJ-IO state = %d ", mprj_io[35:8]);
`ifdef GL
diff --git a/verilog/dv/asm/Determinent.s b/verilog/dv/asm/Determinent.s
index a879ee5..0ac250a 100644
--- a/verilog/dv/asm/Determinent.s
+++ b/verilog/dv/asm/Determinent.s
@@ -14,7 +14,7 @@
csrw 0x7c0, x1
li x1, 4
csrw 0x7f9, x1
-
+nop
li x8,0xf0040000 //For Load
li x19,STDOUT //B.addr
diff --git a/verilog/dv/asm/Power.s b/verilog/dv/asm/Power.s
index 7ef91bb..a1ea198 100644
--- a/verilog/dv/asm/Power.s
+++ b/verilog/dv/asm/Power.s
@@ -14,19 +14,20 @@
csrw 0x7c0, x1
li x1, 4
csrw 0x7f9, x1
+nop
li x8,0xf0040000 //For Load
li x19,STDOUT //B.addr
li x5,4 // Base number
sb x5,0(x8)
-li x5,4 // Base number
-sb x5,1(x8)
+//li x5,4 // Base number
+//sb x5,4(x8)
li x5,3 // power number
-sb x5,2(x8)
+sb x5,4(x8)
lb x5,0(x8)
-lb x6,1(x8)
-lb x7,2(x8)
+lb x6,0(x8)
+lb x7,4(x8)
addi x7,x7,-1
loop:
mul x6,x6,x5
diff --git a/verilog/dv/asm/Queue_push.s b/verilog/dv/asm/Queue_push.s
index 27ef87f..1139e93 100644
--- a/verilog/dv/asm/Queue_push.s
+++ b/verilog/dv/asm/Queue_push.s
@@ -38,9 +38,11 @@
li x4, 4 // Neccessary for terminating code
csrw 0x7f9 ,x4 // Neccessary for terminating code
-
+
+
+
li s0, 0xf0040000 //dccm base address
- li s5,0xf0040100 //Queue Adress
+ //li s5,0xf0040100 //Queue Adress
addi s1,x0,5 //element 1 to push INPUT expected output should be 5 6 7
addi s2,x0,6 //element 2 to push INPUT
@@ -65,28 +67,41 @@
ret
PUSH1:
- sb s1,0(s5) // save element 1 on first location of queue
+ sw s1,0(s0) // save element 1 on first location of queue
j PUSH // jump to push function
PUSH2:
- sb s2,4(s5) // save element 2 on second location of queue
+ sw s2,4(s0) // save element 2 on second location of queue
j PUSH
PUSH3:
- sb s3,8(s5) // save element 3 on third location of queue
+ sw s3,8(s0) // save element 3 on third location of queue
j PUSH
LOAD_QUEUE:
- lb x5,0(s5)
- lb x6,4(s5)
- lb x7,8(s5)
+ lw x5,0(s0)
+ lw x6,4(s0)
+ lw x7,8(s0)
li s6,STDOUT
- sb x5,0(s6) //Sending element 1 to tb
- sb x6,4(s6) //Sending element 2 to tb
- sb x7,8(s6) //Sending element 3 to tb
+ sw x5,0(s6) //Sending element 1 to tb
+ addi s6, s6, 4
+ nop
+ nop
+ nop
+ nop
+ sw x6,0(s6) //Sending element 2 to tb
+ addi s6, s6, 4
+ nop
+ nop
+ nop
+ sw x7,0(s6) //Sending element 3 to tb
+ nop
+ nop
+ nop
+
diff --git a/verilog/dv/asm/flip_num.s b/verilog/dv/asm/flip_num.s
index d119d65..dcc51e6 100644
--- a/verilog/dv/asm/flip_num.s
+++ b/verilog/dv/asm/flip_num.s
@@ -9,14 +9,14 @@
//Prime numbers in a given range
-// li x1, 0x5f555555
-// csrw 0x7c0, x1
+
csrw minstret, zero
csrw minstreth, zero
-
-//li x4, 4 // Neccessary for terminating code
-//csrw 0x7f9 ,x4 // Neccessary for terminating code
+li x1, 0x5f555555
+csrw 0x7c0, x1
+li x4, 4 // Neccessary for terminating code
+csrw 0x7f9 ,x4 // Neccessary for terminating code
diff --git a/verilog/dv/asm/mean.s b/verilog/dv/asm/mean.s
index 2bc53a4..c5587b4 100644
--- a/verilog/dv/asm/mean.s
+++ b/verilog/dv/asm/mean.s
@@ -14,7 +14,7 @@
csrw 0x7c0, x1
li x1, 4
csrw 0x7f9, x1
-
+nop
li x8,0xf0040000 //For Load
li x19,STDOUT //B.addr
diff --git a/verilog/dv/hex/flip_num.hex b/verilog/dv/hex/flip_num.hex
new file mode 100755
index 0000000..d19dd5d
--- /dev/null
+++ b/verilog/dv/hex/flip_num.hex
@@ -0,0 +1,10 @@
+@00000000
+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
+7C 00 90 73 10 73 42 11 14 37 7F 92 04 13 00 49
+44 9D 67 C4 4E 91 42 A9 F0 04 09 37 03 D4 8E 33
+0E 33 9E 4A 09 33 41 DE 0A 13 41 D9 43 09 00 0E
+00 03 0D 63 02 54 43 33 02 54 63 B3 00 03 04 13
+00 7E 00 23 41 DE 0E 33 8F B3 B7 E5 0F 03 02 5F
+0A 33 00 0A 9F FA 41 DA FF 49 19 E3 D0 58 02 B7
+01 F2 A0 23 D0 58 01 B7 0F F0 02 93 00 51 80 23
+FE 00 0A E3 00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/power.hex b/verilog/dv/hex/power.hex
new file mode 100755
index 0000000..e8e3012
--- /dev/null
+++ b/verilog/dv/hex/power.hex
@@ -0,0 +1,8 @@
+@00000000
+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
+7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37
+D0 58 09 B7 00 23 42 91 42 8D 00 54 00 54 02 23
+00 04 02 83 00 04 03 03 00 44 03 83 03 33 13 FD
+13 FD 02 53 00 03 84 63 FE 03 9B E3 00 69 80 23
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/queue.hex b/verilog/dv/hex/queue.hex
new file mode 100755
index 0000000..5a3b56e
--- /dev/null
+++ b/verilog/dv/hex/queue.hex
@@ -0,0 +1,12 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92
+04 93 F0 04 09 13 00 50 09 93 00 60 0A 13 00 70
+02 93 00 30 03 13 00 00 03 93 00 10 0E 13 00 20
+00 EF 00 30 A0 0D 00 60 87 63 02 85 87 63 00 62
+88 63 00 72 80 82 01 C2 B7 FD C0 04 01 24 22 23
+24 23 B7 E5 B7 CD 01 34 00 04 22 83 00 44 23 03
+00 84 23 83 D0 58 0B 37 00 5B 20 23 00 01 0B 11
+00 01 00 01 20 23 00 01 0B 11 00 6B 00 01 00 01
+20 23 00 01 00 01 00 7B 00 01 00 01 D0 58 01 B7
+0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01
+00 00 0F FF
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 87076f3..5a3b56e 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,9 +1,12 @@
@00000000
-B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
-7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37
-D0 58 09 B7 00 23 42 91 42 8D 00 54 00 54 00 A3
-01 23 42 85 42 89 00 54 00 54 01 A3 00 04 02 83
-00 34 03 03 02 62 83 B3 00 14 02 83 00 24 03 03
-02 62 84 33 40 83 82 B3 00 54 02 A3 00 59 80 23
-D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
-00 01 00 01 00 00 0F FF
+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92
+04 93 F0 04 09 13 00 50 09 93 00 60 0A 13 00 70
+02 93 00 30 03 13 00 00 03 93 00 10 0E 13 00 20
+00 EF 00 30 A0 0D 00 60 87 63 02 85 87 63 00 62
+88 63 00 72 80 82 01 C2 B7 FD C0 04 01 24 22 23
+24 23 B7 E5 B7 CD 01 34 00 04 22 83 00 44 23 03
+00 84 23 83 D0 58 0B 37 00 5B 20 23 00 01 0B 11
+00 01 00 01 20 23 00 01 0B 11 00 6B 00 01 00 01
+20 23 00 01 00 01 00 7B 00 01 00 01 D0 58 01 B7
+0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01
+00 00 0F FF
