| commit | 173727d62f7f7f9e5bad4a6a44e28a81a592912c | [log] [tgz] |
|---|---|---|
| author | hamzashabbir517 <shabbirhamza517@gmail.com> | Wed Dec 08 20:29:48 2021 +0200 |
| committer | hamzashabbir517 <shabbirhamza517@gmail.com> | Wed Dec 08 20:29:48 2021 +0200 |
| tree | 28151276a87b58d436499d71f5c6454c8caa0fdd | |
| parent | 12f71fdfd194cdc2ee2b5dab11da8add60d07813 [diff] | |
| parent | c5da9e9885e361d05dee2aa6303a69fc26423c8e [diff] |
Merge branch 'main' of git://github.com/efabless/caravel_user_project into efabless-main modified: .github/scripts/dv/run-dv-wrapper.sh modified: .github/scripts/dv/run-dv.sh modified: .github/scripts/precheck/precheckBuild.sh modified: .github/scripts/precheck/run-precheck-drc.sh modified: .github/scripts/precheck/run-precheck.sh modified: .github/workflows/caravel_build.yml modified: .github/workflows/user_project_ci.yml modified: .gitignore modified: Makefile modified: caravel new file: def/user_proj_example.def modified: def/user_project_wrapper.def new file: docs/source/_static/empty.png new file: docs/source/_static/layout.png new file: docs/source/_static/option1.png new file: docs/source/_static/option2.png new file: docs/source/_static/option3.png new file: docs/source/_static/pitch.png modified: docs/source/index.rst new file: gds/user_proj_example.gds new file: gds/user_project_wrapper.gds modified: lef/user_proj_example.lef modified: lef/user_project_wrapper.lef new file: mag/user_proj_example.mag modified: mag/user_project_wrapper.mag new file: maglef/user_proj_example.mag modified: maglef/user_project_wrapper.lef.mag new file: openlane/user_proj_example/config.json modified: openlane/user_proj_example/config.tcl modified: openlane/user_proj_example/pin_order.cfg new file: openlane/user_project_wrapper/config.json modified: openlane/user_project_wrapper/config.tcl modified: openlane/user_project_wrapper/pin_order.cfg new file: signoff/user_proj_example/OPENLANE_VERSION new file: signoff/user_proj_example/PDK_SOURCES new file: signoff/user_proj_example/final_summary_report.csv modified: signoff/user_project_wrapper/OPENLANE_VERSION modified: signoff/user_project_wrapper/PDK_SOURCES modified: signoff/user_project_wrapper/final_summary_report.csv deleted: signoff/user_project_wrapper_xor/total.txt deleted: signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds deleted: signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds.png deleted: signoff/user_project_wrapper_xor/user_project_wrapper.xor.xml deleted: signoff/user_project_wrapper_xor/xor.log modified: spi/lvs/user_proj_example.spice modified: spi/lvs/user_project_wrapper.spice modified: verilog/dv/io_ports/Makefile modified: verilog/dv/la_test1/Makefile modified: verilog/dv/la_test2/Makefile modified: verilog/dv/la_test2/la_test2.c modified: verilog/dv/mprj_stimulus/Makefile modified: verilog/dv/wb_port/Makefile modified: verilog/rtl/user_proj_example.v modified: verilog/rtl/user_project_wrapper.v
SPDX-FileCopyrightText: 2020 Efabless Corporation Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. SPDX-License-Identifier: Apache-2.0
This repository contains the BrqRV EB1 Core design RTL. BrqRV EB1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline
├── verlog # User verilog Directory │ ├── rtl # RTL │ ├── dv # Design Verification │ ├── gl # Gate Level Netlis
├── verlog # User verilog Directory │ ├── rtl # RTL | ├── user_project_wrapper.v # User Project Wrapper source file | ├── user_proj_example.v # User Project Example source file | ├── Brqrv_EB1 # BrqRV_EB1 folder | ├── Brqrv_EB1.v # BrqRV_EB1 source file | ├── sky130_sram_1kbyte_1rw1r_32x256_8.v # 1KB sram
├── verlog # User verilog Directory │ ├── dv # Design Verification │ ├── BrqRV_EB1 # Design Test Directory │ ├── hex # Hex files folder │ ├── asm # Assmebly files folder
├── verlog # User verilog Directory │ ├── gl # Gate Level Netlis │ ├── user_project_wrapper.v # User Project Wrapper Netlist │ ├── user_proj_example.v # User Project Example Netlist
├── def # def Directory │ ├── user_project_wrapper.def # User Project Wrapper def file ├── lef # lef Directory │ ├── user_project_wrapper.lef # User Project Wrapper lef file │ ├── user_proj_example.lef # User Project Example lef file ├── gds # gds Directory │ ├── user_project_wrapper.gdz.gz # User Project Wrapper gds │ ├── user_proj_example.gdz.gz # User Project Example gds
Go to verilog/dv/BrqRV_EB1/ directory
Note: Dont forget to add 00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.