commit	8e8933d5f525fdb43fc744f2b78cbbda3192a07d	[log] [tgz]
author	Anish <anish@anishsinghani.com>	Tue Dec 28 20:36:00 2021 -0800
committer	Anish <anish@anishsinghani.com>	Tue Dec 28 20:36:00 2021 -0800
tree	fbd1760ad33fb14edf900075932145a25a887faf
parent	f7c7a712b21631456ee81f9146d5a2545c9080c2 [diff]

Integrate and build

Makefile[diff]
README.md[Added - diff]
caravel[diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
docs/Makefile[Deleted - diff]
docs/environment.yml[Deleted - diff]
docs/requirements.txt[Deleted - diff]
docs/source/_static/counter_32.png[Deleted - diff]
docs/source/_static/wrapper.png[Deleted - diff]
docs/source/conf.py[Deleted - diff]
docs/source/index.rst[Deleted - diff]
gds/tmp/user_proj_example.drc[Added - diff]
gds/tmp/user_proj_example.drc.drc.mag[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[diff]
verilog/dv/io_ports/io_ports.vcd.gz[Added - diff]
verilog/dv/verify.log[Added - diff]
verilog/gl/user_proj_example.v[diff]
verilog/rtl/soc.v[Added - diff]
verilog/rtl/user_proj_example.v[diff]

39 files changed

tree: fbd1760ad33fb14edf900075932145a25a887faf

README.md

PiFive Chip

RISC-V SoC in sky130