two slew violations remaining in the core
diff --git a/openlane/core/config.tcl b/openlane/core/config.tcl
index b33ea10..9f3ab42 100755
--- a/openlane/core/config.tcl
+++ b/openlane/core/config.tcl
@@ -51,7 +51,7 @@
set ::env(PL_TARGET_DENSITY) 0.24
set ::env(FP_CORE_UTIL) "50"
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
+#set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
@@ -67,13 +67,15 @@
# If you're going to use multiple power domains, then disable cvc run.
set ::env(RUN_CVC) 1
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.5"
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) "0.5"
+set ::env(SYNTH_MAX_TRAN) "3.1"
+
set ::env(SYNTH_STRATEGY) "DELAY 2"
# set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
# set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(ROUTING_CORES) 6
-set ::env(DECAP_PERCENT) 75
\ No newline at end of file
