better naming for read test
diff --git a/verilog/dv/testIn/Makefile b/verilog/dv/testRead/Makefile
similarity index 99%
rename from verilog/dv/testIn/Makefile
rename to verilog/dv/testRead/Makefile
index 1947777..91a8a72 100644
--- a/verilog/dv/testIn/Makefile
+++ b/verilog/dv/testRead/Makefile
@@ -40,7 +40,7 @@
.SUFFIXES:
-PATTERN = testIn
+PATTERN = testRead
all: ${PATTERN:=.vcd}
diff --git a/verilog/dv/testIn/preview.gtkw b/verilog/dv/testRead/preview.gtkw
similarity index 100%
rename from verilog/dv/testIn/preview.gtkw
rename to verilog/dv/testRead/preview.gtkw
diff --git a/verilog/dv/testIn/testIn.c b/verilog/dv/testRead/testRead.c
similarity index 98%
rename from verilog/dv/testIn/testIn.c
rename to verilog/dv/testRead/testRead.c
index cf1a9f9..10fe03c 100644
--- a/verilog/dv/testIn/testIn.c
+++ b/verilog/dv/testRead/testRead.c
@@ -231,6 +231,6 @@
reg_mprj_datal = 0xAB410000;
print("\n");
- print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
+ print("Monitor: Test Read Passed\n\n"); // Makes simulation very long!
reg_mprj_datal = 0xAB510000;
}
\ No newline at end of file
diff --git a/verilog/dv/testIn/testIn.hex b/verilog/dv/testRead/testRead.hex
similarity index 98%
rename from verilog/dv/testIn/testIn.hex
rename to verilog/dv/testRead/testRead.hex
index 64de4d8..0eaab11 100755
--- a/verilog/dv/testIn/testIn.hex
+++ b/verilog/dv/testRead/testRead.hex
@@ -130,5 +130,5 @@
B5 3A B7 17 00 10 13 85 C7 82 8D 3A B7 07 00 26
B1 07 37 07 51 AB 98 C3 01 00 83 20 C1 12 03 24
81 12 55 61 82 80 00 00 0A 00 00 00 4D 6F 6E 69
-74 6F 72 3A 20 54 65 73 74 20 31 20 50 61 73 73
-65 64 0A 0A 00 00 00 00
+74 6F 72 3A 20 54 65 73 74 20 52 65 61 64 20 50
+61 73 73 65 64 0A 0A 00
diff --git a/verilog/dv/testIn/testIn_tb.v b/verilog/dv/testRead/testRead_tb.v
similarity index 82%
rename from verilog/dv/testIn/testIn_tb.v
rename to verilog/dv/testRead/testRead_tb.v
index 3845e60..e3c1a65 100644
--- a/verilog/dv/testIn/testIn_tb.v
+++ b/verilog/dv/testRead/testRead_tb.v
@@ -23,7 +23,7 @@
`include "spiflash.v"
`include "tbuart.v"
-module testIn_tb;
+module testRead_tb;
reg clock;
reg RSTB;
reg CSB;
@@ -47,8 +47,8 @@
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
initial begin
- $dumpfile("testIn.vcd");
- $dumpvars(0, testIn_tb);
+ $dumpfile("testRead.vcd");
+ $dumpvars(0, testRead_tb);
// TIP. Increase the first repeat number until it is needed
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (100) begin
@@ -57,19 +57,19 @@
end
$display("%c[1;31m",27);
`ifdef GL
- $display ("Monitor: Timeout, Test Input to Elpis (GL) Failed");
+ $display ("Monitor: Timeout, Test Input (read) to Elpis (GL) Failed");
`else
- $display ("Monitor: Timeout, Test Input to Elpis (RTL) Failed");
+ $display ("Monitor: Timeout, Test Input (read) to Elpis (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
- $display("Test 1 (Input to Elpis) started");
- wait(testIn_tb.uut.mprj.core0.datapath.regfile.registers[15] == 2);
+ $display("Test 1 (Input (read) to Elpis) started");
+ wait(testRead_tb.uut.mprj.core0.datapath.regfile.registers[15] == 2);
$display("%c[1;32m",27);
- $display("Test 2 (Input to Elpis) Finished correctly");
+ $display("Test 2 (Input (read) to Elpis) Finished correctly");
$display("%c[0m",27);
#1;
$finish;
@@ -79,21 +79,21 @@
integer i_mem;
initial begin
for (i_mem = 0; i_mem < 512; i_mem = i_mem + 1) begin
- $dumpvars(0, testIn_tb.uut.mprj.custom_sram.mem[i_mem]);
+ $dumpvars(0, testRead_tb.uut.mprj.custom_sram.mem[i_mem]);
end
end
integer i_reg;
initial begin
for (i_reg = 0; i_reg < 32; i_reg = i_reg + 1) begin
- $dumpvars(0, testIn_tb.uut.mprj.core0.datapath.regfile.registers[i_reg]);
+ $dumpvars(0, testRead_tb.uut.mprj.core0.datapath.regfile.registers[i_reg]);
end
end
integer i_sreg;
initial begin
for (i_sreg = 0; i_sreg < 5; i_sreg = i_sreg + 1) begin
- $dumpvars(0, testIn_tb.uut.mprj.core0.datapath.specialreg.rm[i_sreg]);
+ $dumpvars(0, testRead_tb.uut.mprj.core0.datapath.specialreg.rm[i_sreg]);
end
end
@@ -154,7 +154,7 @@
);
spiflash #(
- .FILENAME("testIn.hex")
+ .FILENAME("testRead.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
diff --git a/verilog/rtl/elpis/definitions.v b/verilog/rtl/elpis/definitions.v
index 4803a28..32b39c6 100644
--- a/verilog/rtl/elpis/definitions.v
+++ b/verilog/rtl/elpis/definitions.v
@@ -90,7 +90,7 @@
// Constants for memory
`define MEMORY_DELAY_CYCLES 5
-`define MEMORY_SIZE 512 // 2^20 - 2^5 = 2^15.
+`define MEMORY_SIZE 512 // 2^20 - 2^5 = 2^15.
// Constants for cache
`define CACHE_LINE_SIZE 128
@@ -141,8 +141,8 @@
`define HF_NUM_ENTRIES 5'd16
// Constants for FIFO coherence response states
-`define FIFO_COH_NOT_SENT 2'b00
-`define FIFO_COH_FIRST_SENT 2'b01
+`define FIFO_COH_NOT_SENT 2'b00
+`define FIFO_COH_FIRST_SENT 2'b01
`define FIFO_COH_COMPLETE_SENT 2'b10
// Implementation of ceiling log2
diff --git a/workflow.sh b/workflow.sh
index 88d8f01..5993530 100755
--- a/workflow.sh
+++ b/workflow.sh
@@ -6,4 +6,4 @@
make sram_wrapper
make chip_controller
make core
-
+#make user_project_wrapper
\ No newline at end of file
