added testBytes
diff --git a/verilog/dv/testBytes/Makefile b/verilog/dv/testBytes/Makefile
new file mode 100644
index 0000000..c87b107
--- /dev/null
+++ b/verilog/dv/testBytes/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM -DTESTS
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = testBytes
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/testBytes/preview.gtkw b/verilog/dv/testBytes/preview.gtkw
new file mode 100644
index 0000000..4b34ffd
--- /dev/null
+++ b/verilog/dv/testBytes/preview.gtkw
@@ -0,0 +1,159 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Sat Nov 6 19:55:55 2021
+[*]
+[dumpfile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testBytes/testBytes.vcd"
+[dumpfile_mtime] "Sat Nov 6 19:41:03 2021"
+[dumpfile_size] 2119544755
+[savefile] "/home/aurora/Elpis-Light-MPW3/verilog/dv/testBytes/preview.gtkw"
+[timestart] 2273389800
+[size] 2560 1466
+[pos] -51 -51
+*-15.000000 2273609300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testBytes_tb.
+[treeopen] testBytes_tb.uut.
+[treeopen] testBytes_tb.uut.mprj.
+[treeopen] testBytes_tb.uut.mprj.core0.
+[sst_width] 388
+[signals_width] 350
+[sst_expanded] 1
+[sst_vpaned_height] 420
+@c00023
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+@28
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+@1401201
+-group_end
+@22
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+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/verilog/dv/testBytes/testBytes.c b/verilog/dv/testBytes/testBytes.c
new file mode 100644
index 0000000..90305c2
--- /dev/null
+++ b/verilog/dv/testBytes/testBytes.c
@@ -0,0 +1,227 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+
+void elpis_load_memory(uint32_t* program_data, uint32_t* program_addr)
+{
+ int i, continue_reading;
+ continue_reading = 1;
+ i = 0;
+ reg_la3_data = 0x00000004;
+ reg_la3_data = 0x00000005;
+ reg_la3_data = 0x00000004;
+ while (continue_reading)
+ {
+ if (program_data[i] == ((uint32_t) 0xFFFFFFFF))
+ {
+ continue_reading = 0;
+ }else {
+ reg_la0_data = program_addr[i];
+ reg_la1_data = program_data[i];
+ }
+ reg_la3_data = 0x00000005;
+ reg_la3_data = 0x00000004;
+ i++;
+ }
+ reg_la3_data = 0x00000001;
+ reg_la3_data = 0x00000000;
+}
+
+// --------------------------------------------------------
+
+/*
+ MPRJ Logic Analyzer Test:
+ - Observes counter value through LA probes [31:0]
+ - Sets counter initial value through LA probes [63:32]
+ - Flags when counter value exceeds 500 through the management SoC gpio
+ - Outputs message to the UART when the test concludes successfuly
+*/
+void main()
+{
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // The upper GPIO pins are configured to be output
+ // and accessble to the management SoC.
+ // Used to flad the start/end of a test
+ // The lower GPIO pins are configured to be output
+ // and accessible to the user project. They show
+ // the project count value, although this test is
+ // designed to read the project count through the
+ // logic analyzer probes.
+ // I/O 6 is configured for the UART Tx line
+
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set UART clock to 64 kbaud (enable before I/O configuration)
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configuring LA probes
+ // outputs from the cpu are inputs for my project denoted for been 0
+ // inputs to the cpu are outpus for my project denoted for been 1
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB400000;
+
+ // Elpis OS information
+ uint32_t OS_DATA[30];
+ OS_DATA[0] = 0x00502023;
+ OS_DATA[1] = 0x00602223;
+ OS_DATA[2] = 0x00702423;
+ OS_DATA[3] = 0x00802623;
+ OS_DATA[4] = 0x00902823;
+ OS_DATA[5] = 0x00400413;
+ OS_DATA[6] = 0x00500493;
+ OS_DATA[7] = 0x00600293;
+ OS_DATA[8] = 0x00700313;
+ OS_DATA[9] = 0x002003af;
+ OS_DATA[10] = 0x00838c63;
+ OS_DATA[11] = 0x00938a63;
+ OS_DATA[12] = 0x00538c63;
+ OS_DATA[13] = 0x00638e63;
+ OS_DATA[14] = 0x00038e63;
+ OS_DATA[15] = 0x02000863;
+ OS_DATA[16] = 0x0000002e;
+ OS_DATA[17] = 0x00000863;
+ OS_DATA[18] = 0x0200007D;
+ OS_DATA[19] = 0x00000463;
+ OS_DATA[20] = 0x0400007D;
+ OS_DATA[21] = 0x00002283;
+ OS_DATA[22] = 0x00402303;
+ OS_DATA[23] = 0x00802383;
+ OS_DATA[24] = 0x00c02403;
+ OS_DATA[25] = 0x01002483;
+ OS_DATA[26] = 0x0000007F;
+ OS_DATA[27] = 0x00000033;
+ OS_DATA[28] = 0x00002050;
+ OS_DATA[29] = 0xFFFFFFFF;
+
+ uint32_t OS_ADDR[30];
+ OS_ADDR[0] = 0x00000010;
+ OS_ADDR[1] = 0x00000011;
+ OS_ADDR[2] = 0x00000012;
+ OS_ADDR[3] = 0x00000013;
+ OS_ADDR[4] = 0x00000014;
+ OS_ADDR[5] = 0x00000015;
+ OS_ADDR[6] = 0x00000016;
+ OS_ADDR[7] = 0x00000017;
+ OS_ADDR[8] = 0x00000018;
+ OS_ADDR[9] = 0x00000019;
+ OS_ADDR[10] = 0x0000001a;
+ OS_ADDR[11] = 0x0000001b;
+ OS_ADDR[12] = 0x0000001c;
+ OS_ADDR[13] = 0x0000001d;
+ OS_ADDR[14] = 0x0000001e;
+ OS_ADDR[15] = 0x0000001f;
+ OS_ADDR[16] = 0x00000020;
+ OS_ADDR[17] = 0x00000021;
+ OS_ADDR[18] = 0x00000022;
+ OS_ADDR[19] = 0x00000023;
+ OS_ADDR[20] = 0x00000024;
+ OS_ADDR[21] = 0x00000025;
+ OS_ADDR[22] = 0x00000026;
+ OS_ADDR[23] = 0x00000027;
+ OS_ADDR[24] = 0x00000028;
+ OS_ADDR[25] = 0x00000029;
+ OS_ADDR[26] = 0x0000002a;
+ OS_ADDR[27] = 0x0000002b;
+ OS_ADDR[28] = 0x00000005;
+ OS_ADDR[29] = 0xFFFFFFFF;
+
+ // Elpis user program
+ uint32_t USER_DATA[4];
+ USER_DATA[0] = 0x00000083;
+ USER_DATA[1] = 0x00100223;
+ USER_DATA[2] = 0xFF00FF33;
+ USER_DATA[3] = 0xFFFFFFFF;
+
+ uint32_t USER_ADDR[4];
+ USER_ADDR[0] = 0x00000040;
+ USER_ADDR[1] = 0x00000041;
+ USER_ADDR[2] = 0x00000100;
+ USER_ADDR[3] = 0xFFFFFFFF;
+
+
+ // Loading elpis memory
+ elpis_load_memory(OS_DATA, OS_ADDR);
+ elpis_load_memory(USER_DATA, USER_ADDR);
+
+ reg_la3_oenb = reg_la3_iena = 0x00000001; // Recovering fast clock not controlled by the user
+
+ // Reset of Elpis and start of computation at Elpis
+ reg_la3_data = 0x00000002;
+ reg_la3_data = 0x00000000;
+
+ reg_mprj_datal = 0xAB410000;
+ print("\n");
+ print("Monitor: Test Bytes Passed\n\n"); // Makes simulation very long!
+ reg_mprj_datal = 0xAB510000;
+}
\ No newline at end of file
diff --git a/verilog/dv/testBytes/testBytes.elf b/verilog/dv/testBytes/testBytes.elf
new file mode 100755
index 0000000..21f3a4c
--- /dev/null
+++ b/verilog/dv/testBytes/testBytes.elf
Binary files differ
diff --git a/verilog/dv/testBytes/testBytes.hex b/verilog/dv/testBytes/testBytes.hex
new file mode 100755
index 0000000..dcd1f2b
--- /dev/null
+++ b/verilog/dv/testBytes/testBytes.hex
@@ -0,0 +1,130 @@
+@00000000
+93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
+13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
+13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
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+13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
+13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
+13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
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+11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
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+01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
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+F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
+00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
+93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
+93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
+23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
+FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
+A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC
+00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14
+F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE
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+01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07
+00 25 13 87 07 02 81 47 1C C3 37 07 00 25 41 07
+1C C3 B7 07 00 25 13 87 47 02 81 47 1C C3 37 07
+00 25 51 07 1C C3 B7 07 00 25 13 87 87 02 81 47
+1C C3 37 07 00 25 61 07 1C C3 B7 07 00 25 13 87
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+37 31 23 2C F4 F8 B7 07 20 00 93 87 F7 3A 23 2E
+F4 F8 B7 97 83 00 93 87 37 C6 23 20 F4 FA B7 97
+93 00 93 87 37 A6 23 22 F4 FA B7 97 53 00 93 87
+37 C6 23 24 F4 FA B7 97 63 00 93 87 37 E6 23 26
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+00 02 93 87 37 86 23 2A F4 FA 93 07 E0 02 23 2C
+F4 FA 85 67 93 87 37 86 23 2E F4 FA B7 07 00 02
+93 87 D7 07 23 20 F4 FC 93 07 30 46 23 22 F4 FC
+B7 07 00 04 93 87 D7 07 23 24 F4 FC 89 67 93 87
+37 28 23 26 F4 FC B7 27 40 00 93 87 37 30 23 28
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+C0 00 93 87 37 40 23 2C F4 FC B7 27 00 01 93 87
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+30 03 23 22 F4 FE 89 67 93 87 07 05 23 24 F4 FE
+FD 57 23 26 F4 FE C1 47 23 20 F4 F0 C5 47 23 22
+F4 F0 C9 47 23 24 F4 F0 CD 47 23 26 F4 F0 D1 47
+23 28 F4 F0 D5 47 23 2A F4 F0 D9 47 23 2C F4 F0
+DD 47 23 2E F4 F0 E1 47 23 20 F4 F2 E5 47 23 22
+F4 F2 E9 47 23 24 F4 F2 ED 47 23 26 F4 F2 F1 47
+23 28 F4 F2 F5 47 23 2A F4 F2 F9 47 23 2C F4 F2
+FD 47 23 2E F4 F2 93 07 00 02 23 20 F4 F4 93 07
+10 02 23 22 F4 F4 93 07 20 02 23 24 F4 F4 93 07
+30 02 23 26 F4 F4 93 07 40 02 23 28 F4 F4 93 07
+50 02 23 2A F4 F4 93 07 60 02 23 2C F4 F4 93 07
+70 02 23 2E F4 F4 93 07 80 02 23 20 F4 F6 93 07
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+B0 02 23 26 F4 F6 95 47 23 28 F4 F6 FD 57 23 2A
+F4 F6 93 07 30 08 23 28 F4 EE B7 07 10 00 93 87
+37 22 23 2A F4 EE B7 07 01 FF 93 87 37 F3 23 2C
+F4 EE FD 57 23 2E F4 EE 93 07 00 04 23 20 F4 EE
+93 07 10 04 23 22 F4 EE 93 07 00 10 23 24 F4 EE
+FD 57 23 26 F4 EE 13 07 04 F0 93 07 84 F7 BA 85
+3E 85 81 34 13 07 04 EE 93 07 04 EF BA 85 3E 85
+0D 3C B7 07 00 25 13 87 C7 02 85 47 1C C3 37 07
+00 25 71 07 1C C3 B7 07 00 25 B1 07 09 47 98 C3
+B7 07 00 25 B1 07 23 A0 07 00 B7 07 00 26 B1 07
+37 07 41 AB 98 C3 B7 07 00 10 13 85 47 7E 7D 3A
+B7 07 00 10 13 85 87 7E 55 3A B7 07 00 26 B1 07
+37 07 51 AB 98 C3 01 00 83 20 C1 11 03 24 81 11
+15 61 82 80 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A
+20 54 65 73 74 20 42 79 74 65 73 20 50 61 73 73
+65 64 0A 0A 00 00 00 00
diff --git a/verilog/dv/testBytes/testBytes_tb.v b/verilog/dv/testBytes/testBytes_tb.v
new file mode 100644
index 0000000..99f936c
--- /dev/null
+++ b/verilog/dv/testBytes/testBytes_tb.v
@@ -0,0 +1,177 @@
+
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module testBytes_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ initial begin
+ $dumpfile("testBytes.vcd");
+ $dumpvars(0, testBytes_tb);
+ // TIP. Increase the first repeat number until it is needed
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (200) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Bytes (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Bytes (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire[127:0] cache_line0;
+ assign cache_line0 = testBytes_tb.uut.mprj.core0.datapath.dcache.cacheData[0];
+
+ initial begin
+ $display("Test Bytes started");
+ wait(cache_line0[39:0] == 'h33FF00FF33);
+ $display("%c[1;32m",27);
+ $display("Test Bytes Finished correctly");
+ $display("%c[0m",27);
+ #1;
+ $finish;
+ end
+
+ // TIP. Dumping of memory addresses. Do something similar with registers
+ integer i_mem;
+ initial begin
+ for (i_mem = 0; i_mem < 512; i_mem = i_mem + 1) begin
+ $dumpvars(0, testBytes_tb.uut.mprj.custom_sram.mem[i_mem]);
+ end
+ end
+
+ integer i_reg;
+ initial begin
+ for (i_reg = 0; i_reg < 32; i_reg = i_reg + 1) begin
+ $dumpvars(0, testBytes_tb.uut.mprj.core0.datapath.regfile.registers[i_reg]);
+ end
+ end
+
+ // Printing first cache positions ...
+ integer i_dcache;
+ initial begin
+ for (i_dcache = 0; i_dcache < 4; i_dcache = i_dcache + 1) begin
+ $dumpvars(0, testBytes_tb.uut.mprj.core0.datapath.dcache.cacheData[i_dcache]);
+ end
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("testBytes.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
