Added multiplication instruction, fixed sram_wrapper, added chip_controller logic, first steps to do dv tests
diff --git a/verilog/rtl/elpis/storebuffer.v b/verilog/rtl/elpis/storebuffer.v
index bc173fc..66fee0e 100644
--- a/verilog/rtl/elpis/storebuffer.v
+++ b/verilog/rtl/elpis/storebuffer.v
@@ -61,15 +61,13 @@
integer i;
always@(*) begin
sb_hit = 1'b0;
+ hit_pos = 2'b0;
for (i = 0; (i < `SB_NUM_ENTRIES); i=i+1) begin
if (sb_valid[i] && (sb_addr[i] <= ld_first_byte) && ( (sb_addr[i] + (sb_size[i] ? 0 : 3'b11) ) >= ld_last_byte) ) begin
sb_hit = 1'b1;
hit_pos = i[1:0];
end
end
- if (!sb_hit) begin
- hit_pos = 2'b0;
- end
end
always@(posedge clk) begin
