Added chip controller openlane workflow, core still has problems with timing
18 files changed
tree: b767170178dc604f151bc59da0153d5e450d7a88
  1. .github/
  2. def/
  3. docs/
  4. lef/
  5. openlane/
  6. signoff/
  7. spi/
  8. verilog/
  9. .gitignore
  10. .gitmodules
  11. info.yaml
  12. Makefile
  13. README.md
README.md

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