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- Rodrigo Huerta ([@rodhuega]( https://github.com/rodhuega )) (UPC¹)
- Aurora Tomás ([@theatomb]( https://github.com/theatomb )) (UPC¹)
<br/>
-¹ Universitat Politècnica de Catalunya (UPC) <br/><br/><img src="readme_data/logo-upc.png" width="450"> <br/><br/>
+¹ Universitat Politècnica de Catalunya (UPC) <br/><br/><img src="readme_data/logo-upc.png" width="525"> <br/><br/>
## **Project description**
-This chip is a reduced version of the one developed by the authors in the following subjects of the MIRI-HPC master of the UPC:
+This chip is a reduced version of the one developed by the authors during the following courses of the MIRI-HPC master taught in the UPC:
- Processor Architecture
- Multiprocessors Architecture
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### **GL**
The tests that we are providing in GL are the following:
-- [testPrint](https://github.com/theatomb/Elpis-Light-MPW3/tree/main/verilog/dv/testPrint): This test checks that Elpis is able to send data to PicoRV.
\ No newline at end of file
+- [testPrint](https://github.com/theatomb/Elpis-Light-MPW3/tree/main/verilog/dv/testPrint): This test checks that Elpis is able to send data to PicoRV.
