Update to coincide with the most recent commit to the caravel
project.  Added C code to control the input enable lines for
inputs coming from the user project.  Since the example code assumes
one-way traffic, the output enable is just the inverse of the input
enable.

verilog/dv/la_test1/la_test1.c

diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index b77c8d5..220bdfe 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c
@@ -97,10 +97,10 @@
 
 	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
 	// Configure LA probes [63:32] as outputs from the cpu
-	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_ena = 0x00000000;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	// Flag start of the test 
 	reg_mprj_datal = 0xAB400000;
@@ -109,7 +109,7 @@
 	reg_la1_data = 0x00000000;
 
 	// Configure LA probes from [63:32] as inputs to disable counter write
-	reg_la1_ena  = 0xFFFFFFFF;    
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    
 
 	while (1) {
 		if (reg_la0_data > 0x1F4) {

verilog/dv/la_test2/la_test2.c

diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
index 1b8a383..f9a293c 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/verilog/dv/la_test2/la_test2.c
@@ -83,16 +83,16 @@
         while (reg_mprj_xfer == 1);
 
 	// Configure All LA probes as inputs to the cpu 
-	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
 	// Flag start of the test
 	reg_mprj_datal = 0xAB600000;
 
 	// Configure LA[64] LA[65] as outputs from the cpu
-	reg_la2_ena  = 0xFFFFFFFC; 
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; 
 
 	// Set clk & reset to one
 	reg_la2_data = 0x00000003;

verilog/dv/mprj_stimulus/mprj_stimulus.c

diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 2fae0f1..e4d0a2d 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -97,10 +97,10 @@
 
     // Configure LA probes [31:0], [127:64] as inputs to the cpu
     // Configure LA probes [63:32] as outputs from the cpu
-    reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-    reg_la1_ena = 0x00000000;    // [63:32]
-    reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-    reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+    reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+    reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
 
     // Flag start of the test
     reg_mprj_datal = 0xAB400000;
@@ -109,7 +109,7 @@
     reg_la1_data = 0x00000000;
 
     // Configure LA probes from [63:32] as inputs to disable counter write
-    reg_la1_ena  = 0xFFFFFFFF;
+    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
 
     reg_mprj_datal = 0xAB410000;
     reg_mprj_datah = 0x00000000;

verilog/dv/wb_port/wb_port.c

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 46d7783..6c8129d 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -75,7 +75,7 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
 
     // Flag start of the test
 	reg_mprj_datal = 0xAB600000;
@@ -86,4 +86,4 @@
     } else {
         reg_mprj_datal = 0xAB600000;
     }
-}
\ No newline at end of file
+}

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b949583..b33e032 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -64,7 +64,7 @@
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
     output [127:0] la_data_out,
-    input  [127:0] la_oen,
+    input  [127:0] la_oenb,
 
     // IOs
     input  [`MPRJ_IO_PADS-1:0] io_in,
@@ -105,10 +105,10 @@
     // LA
     assign la_data_out = {{(127-BITS){1'b0}}, count};
     // Assuming LA probes [63:32] are for controlling the count register  
-    assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
+    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
-    assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
-    assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
 
     counter #(
         .BITS(BITS)

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 17c2511..2a3462b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -58,7 +58,7 @@
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
     output [127:0] la_data_out,
-    input  [127:0] la_oen,
+    input  [127:0] la_oenb,
 
     // IOs
     input  [`MPRJ_IO_PADS-1:0] io_in,
@@ -112,7 +112,7 @@
 
     .la_data_in(la_data_in),
     .la_data_out(la_data_out),
-    .la_oen (la_oen),
+    .la_oenb (la_oenb),
 
     // IO Pads