Add files via upload
diff --git a/Simulations/post_synthesis/a.out b/Simulations/post_synthesis/a.out
new file mode 100644
index 0000000..562b1d6
--- /dev/null
+++ b/Simulations/post_synthesis/a.out
@@ -0,0 +1,28686 @@
+#! c:/iverilog-x64/bin/vvp
+:ivl_version "10.1 (stable)" "(v10_1_1)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_000000000269ec20 .scope module, "gls" "gls" 2 1;
+ .timescale 0 0;
+P_00000000033ab8d0 .param/l "exp" 0 2 4, +C4<00000000000000000000000000001000>;
+P_00000000033ab908 .param/l "in" 0 2 2, +C4<00000000000000000000000000010011>;
+P_00000000033ab940 .param/l "man" 0 2 3, +C4<00000000000000000000000000010111>;
+v00000000035308f0_0 .var "a", 18 0;
+v000000000352f630_0 .net "b", 31 0, L_000000000380d0a0; 1 drivers
+v0000000003531890_0 .net "zro", 0 0, L_000000000391e640; 1 drivers
+S_00000000026c0180 .scope module, "u1" "fxd2flot" 2 10, 3 3 0, S_000000000269ec20;
+ .timescale 0 0;
+ .port_info 0 /INPUT 19 "a"
+ .port_info 1 /OUTPUT 32 "b"
+ .port_info 2 /OUTPUT 1 "zro"
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+v0000000003529d70_0 .net "_001_", 0 0, L_000000000391fa60; 1 drivers
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+L_0000000003922930 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v00000000035290f0_0 .net8 "_003_", 0 0, L_0000000003922930; 1 drivers, strength-aware
+v0000000003528f10_0 .net "_004_", 0 0, L_0000000003920780; 1 drivers
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+v000000000352fd10_0 .net "b", 31 0, L_000000000380d0a0; alias, 1 drivers
+v0000000003531070_0 .net "zro", 0 0, L_000000000391e640; alias, 1 drivers
+L_000000000380d000 .part v00000000035308f0_0, 10, 1;
+L_000000000380aa80 .part v00000000035308f0_0, 11, 1;
+L_000000000380ae40 .part v00000000035308f0_0, 12, 1;
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+L_000000000380c100 .part v00000000035308f0_0, 9, 1;
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+L_000000000380c600 .part v00000000035308f0_0, 10, 1;
+L_000000000380b8e0 .part v00000000035308f0_0, 14, 1;
+L_000000000380ad00 .part v00000000035308f0_0, 16, 1;
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+L_000000000380cf60 .part v00000000035308f0_0, 1, 1;
+L_000000000380c740 .part v00000000035308f0_0, 0, 1;
+L_000000000380c880 .part v00000000035308f0_0, 1, 1;
+L_000000000380ce20 .part v00000000035308f0_0, 3, 1;
+L_000000000380cb00 .part v00000000035308f0_0, 7, 1;
+L_000000000380b340 .part v00000000035308f0_0, 9, 1;
+L_000000000380bfc0 .part v00000000035308f0_0, 11, 1;
+L_000000000380be80 .part v00000000035308f0_0, 15, 1;
+L_000000000380b3e0 .part v00000000035308f0_0, 8, 1;
+L_000000000380cba0 .part L_000000000380d0a0, 23, 1;
+L_000000000380cc40 .part L_000000000380d0a0, 23, 1;
+L_000000000380ab20 .part L_000000000380d0a0, 23, 1;
+L_000000000380cd80 .part v00000000035308f0_0, 0, 1;
+L_000000000380cec0 .part v00000000035308f0_0, 2, 1;
+L_000000000380c060 .part v00000000035308f0_0, 6, 1;
+L_000000000380c1a0 .part v00000000035308f0_0, 18, 1;
+L_0000000003923ab0 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+L_0000000003923f10 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+L_00000000039238f0 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+L_0000000003924140 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+LS_000000000380d0a0_0_0 .concat8 [ 1 1 1 1], L_0000000003923ab0, L_0000000003923f10, L_00000000039238f0, L_0000000003924140;
+LS_000000000380d0a0_0_4 .concat8 [ 1 1 1 1], L_0000000003921f20, L_0000000003922000, L_00000000039223f0, L_00000000039228c0;
+LS_000000000380d0a0_0_8 .concat8 [ 1 1 1 1], L_000000000391d5a0, L_000000000391d6f0, L_000000000391cce0, L_000000000391c810;
+LS_000000000380d0a0_0_12 .concat8 [ 1 1 1 1], L_000000000391cab0, L_000000000391ddf0, L_000000000391d0d0, L_000000000391d140;
+LS_000000000380d0a0_0_16 .concat8 [ 1 1 1 1], L_0000000003924290, L_0000000003924680, L_0000000003924300, L_0000000003924f40;
+LS_000000000380d0a0_0_20 .concat8 [ 1 1 1 1], L_0000000003923650, L_0000000003924450, L_0000000003924370, L_0000000003920fd0;
+LS_000000000380d0a0_0_24 .concat8 [ 1 1 1 1], L_0000000003923730, L_0000000003924b50, L_00000000039236c0, L_0000000003924610;
+LS_000000000380d0a0_0_28 .concat8 [ 1 1 1 1], L_0000000003924ae0, L_0000000003924bc0, L_0000000003923960, L_0000000003923b20;
+LS_000000000380d0a0_1_0 .concat8 [ 4 4 4 4], LS_000000000380d0a0_0_0, LS_000000000380d0a0_0_4, LS_000000000380d0a0_0_8, LS_000000000380d0a0_0_12;
+LS_000000000380d0a0_1_4 .concat8 [ 4 4 4 4], LS_000000000380d0a0_0_16, LS_000000000380d0a0_0_20, LS_000000000380d0a0_0_24, LS_000000000380d0a0_0_28;
+L_000000000380d0a0 .concat8 [ 16 16 0 0], LS_000000000380d0a0_1_0, LS_000000000380d0a0_1_4;
+L_000000000380c2e0 .part L_000000000380d0a0, 23, 1;
+S_00000000026c1e00 .scope module, "_188_" "sky130_fd_sc_hd__or2_2" 3 195, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000033a3fc0_0 .net "A", 0 0, L_000000000380d000; 1 drivers
+v00000000033a3f20_0 .net "B", 0 0, L_000000000380aa80; 1 drivers
+L_0000000002971e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a37a0_0 .net8 "VGND", 0 0, L_0000000002971e20; 1 drivers, strength-aware
+L_0000000002971b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a3840_0 .net8 "VNB", 0 0, L_0000000002971b10; 1 drivers, strength-aware
+L_00000000029726e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a4060_0 .net8 "VPB", 0 0, L_00000000029726e0; 1 drivers, strength-aware
+L_0000000002972520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3340_0 .net8 "VPWR", 0 0, L_0000000002972520; 1 drivers, strength-aware
+v00000000033a4600_0 .net "X", 0 0, L_000000000391c340; alias, 1 drivers
+S_00000000026c0300 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000026c1e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391bf50 .functor OR 1, L_000000000380aa80, L_000000000380d000, C4<0>, C4<0>;
+L_000000000391c340 .functor BUF 1, L_000000000391bf50, C4<0>, C4<0>, C4<0>;
+v00000000033a4d80_0 .net "A", 0 0, L_000000000380d000; alias, 1 drivers
+v00000000033a42e0_0 .net "B", 0 0, L_000000000380aa80; alias, 1 drivers
+L_0000000002971b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a35c0_0 .net8 "VGND", 0 0, L_0000000002971b80; 1 drivers, strength-aware
+L_0000000002971720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a3660_0 .net8 "VNB", 0 0, L_0000000002971720; 1 drivers, strength-aware
+L_0000000002972600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3c00_0 .net8 "VPB", 0 0, L_0000000002972600; 1 drivers, strength-aware
+L_0000000002971410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3200_0 .net8 "VPWR", 0 0, L_0000000002971410; 1 drivers, strength-aware
+v00000000033a32a0_0 .net "X", 0 0, L_000000000391c340; alias, 1 drivers
+v00000000033a4e20_0 .net "or0_out_X", 0 0, L_000000000391bf50; 1 drivers
+S_00000000026c1980 .scope module, "_189_" "sky130_fd_sc_hd__inv_2" 3 200, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v00000000033a3b60_0 .net "A", 0 0, L_000000000380ae40; 1 drivers
+L_0000000002972130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a3700_0 .net8 "VGND", 0 0, L_0000000002972130; 1 drivers, strength-aware
+L_00000000029721a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a4880_0 .net8 "VNB", 0 0, L_00000000029721a0; 1 drivers, strength-aware
+L_0000000002971330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3980_0 .net8 "VPB", 0 0, L_0000000002971330; 1 drivers, strength-aware
+L_0000000002971790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3a20_0 .net8 "VPWR", 0 0, L_0000000002971790; 1 drivers, strength-aware
+v00000000033a46a0_0 .net "Y", 0 0, L_000000000391bfc0; alias, 1 drivers
+S_00000000026c2580 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026c1980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391bd20 .functor NOT 1, L_000000000380ae40, C4<0>, C4<0>, C4<0>;
+L_000000000391bfc0 .functor BUF 1, L_000000000391bd20, C4<0>, C4<0>, C4<0>;
+v00000000033a4100_0 .net "A", 0 0, L_000000000380ae40; alias, 1 drivers
+L_0000000002971090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a4240_0 .net8 "VGND", 0 0, L_0000000002971090; 1 drivers, strength-aware
+L_0000000002971480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a38e0_0 .net8 "VNB", 0 0, L_0000000002971480; 1 drivers, strength-aware
+L_0000000002972360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a33e0_0 .net8 "VPB", 0 0, L_0000000002972360; 1 drivers, strength-aware
+L_00000000029714f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a3480_0 .net8 "VPWR", 0 0, L_00000000029714f0; 1 drivers, strength-aware
+v00000000033a41a0_0 .net "Y", 0 0, L_000000000391bfc0; alias, 1 drivers
+v00000000033a4ec0_0 .net "not0_out_Y", 0 0, L_000000000391bd20; 1 drivers
+S_00000000026c1680 .scope module, "_190_" "sky130_fd_sc_hd__inv_2" 3 204, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a743e0_0 .net "A", 0 0, L_000000000380b700; 1 drivers
+L_0000000002972210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a74480_0 .net8 "VGND", 0 0, L_0000000002972210; 1 drivers, strength-aware
+L_0000000002972440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75880_0 .net8 "VNB", 0 0, L_0000000002972440; 1 drivers, strength-aware
+L_00000000029715d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a75ce0_0 .net8 "VPB", 0 0, L_00000000029715d0; 1 drivers, strength-aware
+L_0000000002971640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a75ec0_0 .net8 "VPWR", 0 0, L_0000000002971640; 1 drivers, strength-aware
+v0000000002a763c0_0 .net "Y", 0 0, L_000000000391aac0; alias, 1 drivers
+S_00000000026c0c00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026c1680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391b3f0 .functor NOT 1, L_000000000380b700, C4<0>, C4<0>, C4<0>;
+L_000000000391aac0 .functor BUF 1, L_000000000391b3f0, C4<0>, C4<0>, C4<0>;
+v00000000033a3ca0_0 .net "A", 0 0, L_000000000380b700; alias, 1 drivers
+L_00000000029716b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a3d40_0 .net8 "VGND", 0 0, L_00000000029716b0; 1 drivers, strength-aware
+L_0000000002972980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000033a3de0_0 .net8 "VNB", 0 0, L_0000000002972980; 1 drivers, strength-aware
+L_0000000002971e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a4380_0 .net8 "VPB", 0 0, L_0000000002971e90; 1 drivers, strength-aware
+L_0000000002972050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000033a4420_0 .net8 "VPWR", 0 0, L_0000000002972050; 1 drivers, strength-aware
+v00000000033a4740_0 .net "Y", 0 0, L_000000000391aac0; alias, 1 drivers
+v00000000033a44c0_0 .net "not0_out_Y", 0 0, L_000000000391b3f0; 1 drivers
+S_00000000026be980 .scope module, "_191_" "sky130_fd_sc_hd__nor2_2" 3 208, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a751a0_0 .net "A", 0 0, L_000000000380c9c0; 1 drivers
+v0000000002a76280_0 .net "B", 0 0, L_000000000380b660; 1 drivers
+L_0000000002972910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a745c0_0 .net8 "VGND", 0 0, L_0000000002972910; 1 drivers, strength-aware
+L_0000000002972280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a74840_0 .net8 "VNB", 0 0, L_0000000002972280; 1 drivers, strength-aware
+L_0000000002972ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74b60_0 .net8 "VPB", 0 0, L_0000000002972ad0; 1 drivers, strength-aware
+L_0000000002971f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a75380_0 .net8 "VPWR", 0 0, L_0000000002971f70; 1 drivers, strength-aware
+v0000000002a74660_0 .net "Y", 0 0, L_000000000391c110; alias, 1 drivers
+S_00000000026c2e80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026be980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391c0a0 .functor NOR 1, L_000000000380c9c0, L_000000000380b660, C4<0>, C4<0>;
+L_000000000391c110 .functor BUF 1, L_000000000391c0a0, C4<0>, C4<0>, C4<0>;
+v0000000002a75560_0 .net "A", 0 0, L_000000000380c9c0; alias, 1 drivers
+v0000000002a76640_0 .net "B", 0 0, L_000000000380b660; alias, 1 drivers
+L_00000000029723d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75920_0 .net8 "VGND", 0 0, L_00000000029723d0; 1 drivers, strength-aware
+L_0000000002971800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75d80_0 .net8 "VNB", 0 0, L_0000000002971800; 1 drivers, strength-aware
+L_0000000002971870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74fc0_0 .net8 "VPB", 0 0, L_0000000002971870; 1 drivers, strength-aware
+L_00000000029718e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74520_0 .net8 "VPWR", 0 0, L_00000000029718e0; 1 drivers, strength-aware
+v0000000002a76000_0 .net "Y", 0 0, L_000000000391c110; alias, 1 drivers
+v0000000002a74a20_0 .net "nor0_out_Y", 0 0, L_000000000391c0a0; 1 drivers
+S_00000000026beb00 .scope module, "_192_" "sky130_fd_sc_hd__and3_2" 3 213, 4 10013 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+v0000000002a75a60_0 .net "A", 0 0, L_000000000391bfc0; alias, 1 drivers
+v0000000002a754c0_0 .net "B", 0 0, L_000000000391aac0; alias, 1 drivers
+v0000000002a75ba0_0 .net "C", 0 0, L_000000000391c110; alias, 1 drivers
+L_0000000002971950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75740_0 .net8 "VGND", 0 0, L_0000000002971950; 1 drivers, strength-aware
+L_0000000002972590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75e20_0 .net8 "VNB", 0 0, L_0000000002972590; 1 drivers, strength-aware
+L_0000000002972670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a752e0_0 .net8 "VPB", 0 0, L_0000000002972670; 1 drivers, strength-aware
+L_0000000002972750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74ac0_0 .net8 "VPWR", 0 0, L_0000000002972750; 1 drivers, strength-aware
+v0000000002a742a0_0 .net "X", 0 0, L_000000000391aa50; alias, 1 drivers
+S_00000000026c3480 .scope module, "base" "sky130_fd_sc_hd__and3" 4 10031, 4 10319 1, S_00000000026beb00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000391a900 .functor AND 1, L_000000000391c110, L_000000000391bfc0, L_000000000391aac0, C4<1>;
+L_000000000391aa50 .functor BUF 1, L_000000000391a900, C4<0>, C4<0>, C4<0>;
+v0000000002a74700_0 .net "A", 0 0, L_000000000391bfc0; alias, 1 drivers
+v0000000002a747a0_0 .net "B", 0 0, L_000000000391aac0; alias, 1 drivers
+v0000000002a75b00_0 .net "C", 0 0, L_000000000391c110; alias, 1 drivers
+L_0000000002971fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75240_0 .net8 "VGND", 0 0, L_0000000002971fe0; 1 drivers, strength-aware
+L_00000000029719c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a748e0_0 .net8 "VNB", 0 0, L_00000000029719c0; 1 drivers, strength-aware
+L_0000000002971bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76500_0 .net8 "VPB", 0 0, L_0000000002971bf0; 1 drivers, strength-aware
+L_0000000002971c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74980_0 .net8 "VPWR", 0 0, L_0000000002971c60; 1 drivers, strength-aware
+v0000000002a759c0_0 .net "X", 0 0, L_000000000391aa50; alias, 1 drivers
+v0000000002a75420_0 .net "and0_out_X", 0 0, L_000000000391a900; 1 drivers
+S_00000000026c0f00 .scope module, "_193_" "sky130_fd_sc_hd__or4b_2" 3 219, 4 18015 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+v0000000002a75060_0 .net "A", 0 0, L_000000000380c100; 1 drivers
+v0000000002a760a0_0 .net "B", 0 0, L_000000000380b020; 1 drivers
+v0000000002a76460_0 .net "C", 0 0, L_000000000391c340; alias, 1 drivers
+v0000000002a740c0_0 .net "D_N", 0 0, L_000000000391aa50; alias, 1 drivers
+L_0000000002971cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a761e0_0 .net8 "VGND", 0 0, L_0000000002971cd0; 1 drivers, strength-aware
+L_0000000002971d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a75100_0 .net8 "VNB", 0 0, L_0000000002971d40; 1 drivers, strength-aware
+L_00000000029720c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76320_0 .net8 "VPB", 0 0, L_00000000029720c0; 1 drivers, strength-aware
+L_00000000029727c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a765a0_0 .net8 "VPWR", 0 0, L_00000000029727c0; 1 drivers, strength-aware
+v0000000002a766e0_0 .net "X", 0 0, L_000000000391c570; alias, 1 drivers
+S_00000000026c1f80 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 18035, 4 17892 1, S_00000000026c0f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000391ad60 .functor NOT 1, L_000000000391aa50, C4<0>, C4<0>, C4<0>;
+L_000000000391da70 .functor OR 1, L_000000000391ad60, L_000000000391c340, L_000000000380b020, L_000000000380c100;
+L_000000000391c570 .functor BUF 1, L_000000000391da70, C4<0>, C4<0>, C4<0>;
+v0000000002a75c40_0 .net "A", 0 0, L_000000000380c100; alias, 1 drivers
+v0000000002a74c00_0 .net "B", 0 0, L_000000000380b020; alias, 1 drivers
+v0000000002a74ca0_0 .net "C", 0 0, L_000000000391c340; alias, 1 drivers
+v0000000002a75600_0 .net "D_N", 0 0, L_000000000391aa50; alias, 1 drivers
+L_0000000002972830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a74d40_0 .net8 "VGND", 0 0, L_0000000002972830; 1 drivers, strength-aware
+L_00000000029728a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a756a0_0 .net8 "VNB", 0 0, L_00000000029728a0; 1 drivers, strength-aware
+L_00000000029729f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a757e0_0 .net8 "VPB", 0 0, L_00000000029729f0; 1 drivers, strength-aware
+L_0000000002972bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76140_0 .net8 "VPWR", 0 0, L_0000000002972bb0; 1 drivers, strength-aware
+v0000000002a75f60_0 .net "X", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000002a74de0_0 .net "not0_out", 0 0, L_000000000391ad60; 1 drivers
+v0000000002a74e80_0 .net "or0_out_X", 0 0, L_000000000391da70; 1 drivers
+S_00000000026bf580 .scope module, "_194_" "sky130_fd_sc_hd__or2_2" 3 226, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a76d20_0 .net "A", 0 0, L_000000000380bd40; 1 drivers
+v0000000002a76fa0_0 .net "B", 0 0, L_000000000380bb60; 1 drivers
+L_0000000002972c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a76e60_0 .net8 "VGND", 0 0, L_0000000002972c20; 1 drivers, strength-aware
+L_0000000002973860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78760_0 .net8 "VNB", 0 0, L_0000000002973860; 1 drivers, strength-aware
+L_0000000002973e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78c60_0 .net8 "VPB", 0 0, L_0000000002973e10; 1 drivers, strength-aware
+L_00000000029734e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76c80_0 .net8 "VPWR", 0 0, L_00000000029734e0; 1 drivers, strength-aware
+v0000000002a76f00_0 .net "X", 0 0, L_000000000391dd10; alias, 1 drivers
+S_00000000026c0000 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000026bf580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391cea0 .functor OR 1, L_000000000380bb60, L_000000000380bd40, C4<0>, C4<0>;
+L_000000000391dd10 .functor BUF 1, L_000000000391cea0, C4<0>, C4<0>, C4<0>;
+v0000000002a76780_0 .net "A", 0 0, L_000000000380bd40; alias, 1 drivers
+v0000000002a74f20_0 .net "B", 0 0, L_000000000380bb60; alias, 1 drivers
+L_0000000002973780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a76820_0 .net8 "VGND", 0 0, L_0000000002973780; 1 drivers, strength-aware
+L_00000000029740b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a74160_0 .net8 "VNB", 0 0, L_00000000029740b0; 1 drivers, strength-aware
+L_0000000002972e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74200_0 .net8 "VPB", 0 0, L_0000000002972e50; 1 drivers, strength-aware
+L_0000000002974740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a74340_0 .net8 "VPWR", 0 0, L_0000000002974740; 1 drivers, strength-aware
+v0000000002a783a0_0 .net "X", 0 0, L_000000000391dd10; alias, 1 drivers
+v0000000002a77ea0_0 .net "or0_out_X", 0 0, L_000000000391cea0; 1 drivers
+S_00000000026c2100 .scope module, "_195_" "sky130_fd_sc_hd__or2_2" 3 231, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a779a0_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000002a77220_0 .net "B", 0 0, L_000000000391dd10; alias, 1 drivers
+L_0000000002972c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a76aa0_0 .net8 "VGND", 0 0, L_0000000002972c90; 1 drivers, strength-aware
+L_0000000002972d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78440_0 .net8 "VNB", 0 0, L_0000000002972d00; 1 drivers, strength-aware
+L_0000000002973b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78da0_0 .net8 "VPB", 0 0, L_0000000002973b00; 1 drivers, strength-aware
+L_00000000029739b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76960_0 .net8 "VPWR", 0 0, L_00000000029739b0; 1 drivers, strength-aware
+v0000000002a78a80_0 .net "X", 0 0, L_000000000391d4c0; alias, 1 drivers
+S_00000000026c0480 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000026c2100;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391c880 .functor OR 1, L_000000000391dd10, L_000000000391c570, C4<0>, C4<0>;
+L_000000000391d4c0 .functor BUF 1, L_000000000391c880, C4<0>, C4<0>, C4<0>;
+v0000000002a77040_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000002a781c0_0 .net "B", 0 0, L_000000000391dd10; alias, 1 drivers
+L_0000000002973e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a77540_0 .net8 "VGND", 0 0, L_0000000002973e80; 1 drivers, strength-aware
+L_0000000002973ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a768c0_0 .net8 "VNB", 0 0, L_0000000002973ef0; 1 drivers, strength-aware
+L_0000000002973400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78d00_0 .net8 "VPB", 0 0, L_0000000002973400; 1 drivers, strength-aware
+L_0000000002973160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a788a0_0 .net8 "VPWR", 0 0, L_0000000002973160; 1 drivers, strength-aware
+v0000000002a78bc0_0 .net "X", 0 0, L_000000000391d4c0; alias, 1 drivers
+v0000000002a78080_0 .net "or0_out_X", 0 0, L_000000000391c880; 1 drivers
+S_00000000026c1800 .scope module, "_196_" "sky130_fd_sc_hd__buf_1" 3 236, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a78260_0 .net "A", 0 0, L_000000000391d4c0; alias, 1 drivers
+L_0000000002973da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78300_0 .net8 "VGND", 0 0, L_0000000002973da0; 1 drivers, strength-aware
+L_0000000002973f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78800_0 .net8 "VNB", 0 0, L_0000000002973f60; 1 drivers, strength-aware
+L_0000000002974120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a77e00_0 .net8 "VPB", 0 0, L_0000000002974120; 1 drivers, strength-aware
+L_00000000029745f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a77900_0 .net8 "VPWR", 0 0, L_00000000029745f0; 1 drivers, strength-aware
+v0000000002a77c20_0 .net "X", 0 0, L_000000000391c730; alias, 1 drivers
+S_00000000026c3780 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000026c1800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391d220 .functor BUF 1, L_000000000391d4c0, C4<0>, C4<0>, C4<0>;
+L_000000000391c730 .functor BUF 1, L_000000000391d220, C4<0>, C4<0>, C4<0>;
+v0000000002a77d60_0 .net "A", 0 0, L_000000000391d4c0; alias, 1 drivers
+L_0000000002972ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a76be0_0 .net8 "VGND", 0 0, L_0000000002972ec0; 1 drivers, strength-aware
+L_0000000002972fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a77b80_0 .net8 "VNB", 0 0, L_0000000002972fa0; 1 drivers, strength-aware
+L_0000000002972f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78e40_0 .net8 "VPB", 0 0, L_0000000002972f30; 1 drivers, strength-aware
+L_0000000002974350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78940_0 .net8 "VPWR", 0 0, L_0000000002974350; 1 drivers, strength-aware
+v0000000002a786c0_0 .net "X", 0 0, L_000000000391c730; alias, 1 drivers
+v0000000002a770e0_0 .net "buf0_out_X", 0 0, L_000000000391d220; 1 drivers
+S_00000000026c2280 .scope module, "_197_" "sky130_fd_sc_hd__inv_2" 3 240, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a77fe0_0 .net "A", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000002973d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78120_0 .net8 "VGND", 0 0, L_0000000002973d30; 1 drivers, strength-aware
+L_00000000029747b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79020_0 .net8 "VNB", 0 0, L_00000000029747b0; 1 drivers, strength-aware
+L_0000000002973b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a77f40_0 .net8 "VPB", 0 0, L_0000000002973b70; 1 drivers, strength-aware
+L_0000000002973010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76dc0_0 .net8 "VPWR", 0 0, L_0000000002973010; 1 drivers, strength-aware
+v0000000002a784e0_0 .net "Y", 0 0, L_000000000391e090; alias, 1 drivers
+S_00000000026bfb80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026c2280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391c960 .functor NOT 1, L_000000000391c730, C4<0>, C4<0>, C4<0>;
+L_000000000391e090 .functor BUF 1, L_000000000391c960, C4<0>, C4<0>, C4<0>;
+v0000000002a77720_0 .net "A", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000002973c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a789e0_0 .net8 "VGND", 0 0, L_0000000002973c50; 1 drivers, strength-aware
+L_0000000002973be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a77a40_0 .net8 "VNB", 0 0, L_0000000002973be0; 1 drivers, strength-aware
+L_0000000002974580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a774a0_0 .net8 "VPB", 0 0, L_0000000002974580; 1 drivers, strength-aware
+L_0000000002973a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a77180_0 .net8 "VPWR", 0 0, L_0000000002973a90; 1 drivers, strength-aware
+v0000000002a777c0_0 .net "Y", 0 0, L_000000000391e090; alias, 1 drivers
+v0000000002a77ae0_0 .net "not0_out_Y", 0 0, L_000000000391c960; 1 drivers
+S_00000000026c2400 .scope module, "_198_" "sky130_fd_sc_hd__buf_1" 3 244, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a77680_0 .net "A", 0 0, L_000000000391e090; alias, 1 drivers
+L_00000000029731d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78f80_0 .net8 "VGND", 0 0, L_00000000029731d0; 1 drivers, strength-aware
+L_0000000002973470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a77860_0 .net8 "VNB", 0 0, L_0000000002973470; 1 drivers, strength-aware
+L_0000000002972d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a76b40_0 .net8 "VPB", 0 0, L_0000000002972d70; 1 drivers, strength-aware
+L_00000000029737f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a772c0_0 .net8 "VPWR", 0 0, L_00000000029737f0; 1 drivers, strength-aware
+v0000000002a77360_0 .net "X", 0 0, L_000000000391ce30; alias, 1 drivers
+S_00000000026c2700 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000026c2400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391c500 .functor BUF 1, L_000000000391e090, C4<0>, C4<0>, C4<0>;
+L_000000000391ce30 .functor BUF 1, L_000000000391c500, C4<0>, C4<0>, C4<0>;
+v0000000002a76a00_0 .net "A", 0 0, L_000000000391e090; alias, 1 drivers
+L_0000000002974190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a78580_0 .net8 "VGND", 0 0, L_0000000002974190; 1 drivers, strength-aware
+L_00000000029736a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a77cc0_0 .net8 "VNB", 0 0, L_00000000029736a0; 1 drivers, strength-aware
+L_0000000002973fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78620_0 .net8 "VPB", 0 0, L_0000000002973fd0; 1 drivers, strength-aware
+L_0000000002973cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a78b20_0 .net8 "VPWR", 0 0, L_0000000002973cc0; 1 drivers, strength-aware
+v0000000002a775e0_0 .net "X", 0 0, L_000000000391ce30; alias, 1 drivers
+v0000000002a78ee0_0 .net "buf0_out_X", 0 0, L_000000000391c500; 1 drivers
+S_00000000026c2880 .scope module, "_199_" "sky130_fd_sc_hd__nor2_2" 3 248, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7a1a0_0 .net "A", 0 0, L_0000000003925100; alias, 1 drivers
+v0000000002a7aba0_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b500_0 .net8 "VGND", 0 0, L_0000000002974040; 1 drivers, strength-aware
+L_0000000002973080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79340_0 .net8 "VNB", 0 0, L_0000000002973080; 1 drivers, strength-aware
+L_0000000002974200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b640_0 .net8 "VPB", 0 0, L_0000000002974200; 1 drivers, strength-aware
+L_0000000002974270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a920_0 .net8 "VPWR", 0 0, L_0000000002974270; 1 drivers, strength-aware
+v0000000002a7a4c0_0 .net "Y", 0 0, L_000000000391d5a0; 1 drivers
+S_00000000026bdf00 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026c2880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d920 .functor NOR 1, L_0000000003925100, L_000000000391ce30, C4<0>, C4<0>;
+L_000000000391d5a0 .functor BUF 1, L_000000000391d920, C4<0>, C4<0>, C4<0>;
+v0000000002a77400_0 .net "A", 0 0, L_0000000003925100; alias, 1 drivers
+v0000000002a793e0_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_00000000029730f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79480_0 .net8 "VGND", 0 0, L_00000000029730f0; 1 drivers, strength-aware
+L_0000000002974430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a880_0 .net8 "VNB", 0 0, L_0000000002974430; 1 drivers, strength-aware
+L_00000000029742e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a79fc0_0 .net8 "VPB", 0 0, L_00000000029742e0; 1 drivers, strength-aware
+L_0000000002973240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7aec0_0 .net8 "VPWR", 0 0, L_0000000002973240; 1 drivers, strength-aware
+v0000000002a7b1e0_0 .net "Y", 0 0, L_000000000391d5a0; alias, 1 drivers
+v0000000002a79700_0 .net "nor0_out_Y", 0 0, L_000000000391d920; 1 drivers
+S_00000000026be500 .scope module, "_200_" "sky130_fd_sc_hd__nor2_2" 3 253, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7b780_0 .net "A", 0 0, L_0000000003926ad0; alias, 1 drivers
+v0000000002a79a20_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_00000000029746d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ace0_0 .net8 "VGND", 0 0, L_00000000029746d0; 1 drivers, strength-aware
+L_00000000029732b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a100_0 .net8 "VNB", 0 0, L_00000000029732b0; 1 drivers, strength-aware
+L_00000000029744a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a240_0 .net8 "VPB", 0 0, L_00000000029744a0; 1 drivers, strength-aware
+L_00000000029743c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a79660_0 .net8 "VPWR", 0 0, L_00000000029743c0; 1 drivers, strength-aware
+v0000000002a7ad80_0 .net "Y", 0 0, L_000000000391d6f0; 1 drivers
+S_00000000026bf280 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026be500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391dd80 .functor NOR 1, L_0000000003926ad0, L_000000000391ce30, C4<0>, C4<0>;
+L_000000000391d6f0 .functor BUF 1, L_000000000391dd80, C4<0>, C4<0>, C4<0>;
+v0000000002a79c00_0 .net "A", 0 0, L_0000000003926ad0; alias, 1 drivers
+v0000000002a7ab00_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b820_0 .net8 "VGND", 0 0, L_0000000002974510; 1 drivers, strength-aware
+L_0000000002973320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ac40_0 .net8 "VNB", 0 0, L_0000000002973320; 1 drivers, strength-aware
+L_0000000002973550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a6a0_0 .net8 "VPB", 0 0, L_0000000002973550; 1 drivers, strength-aware
+L_0000000002973710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a795c0_0 .net8 "VPWR", 0 0, L_0000000002973710; 1 drivers, strength-aware
+v0000000002a79520_0 .net "Y", 0 0, L_000000000391d6f0; alias, 1 drivers
+v0000000002a79200_0 .net "nor0_out_Y", 0 0, L_000000000391dd80; 1 drivers
+S_00000000026be200 .scope module, "_201_" "sky130_fd_sc_hd__inv_2" 3 258, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a7af60_0 .net "A", 0 0, L_000000000380c600; 1 drivers
+L_00000000029735c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b280_0 .net8 "VGND", 0 0, L_00000000029735c0; 1 drivers, strength-aware
+L_0000000002974660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b460_0 .net8 "VNB", 0 0, L_0000000002974660; 1 drivers, strength-aware
+L_0000000002972de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a792a0_0 .net8 "VPB", 0 0, L_0000000002972de0; 1 drivers, strength-aware
+L_0000000002973390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b320_0 .net8 "VPWR", 0 0, L_0000000002973390; 1 drivers, strength-aware
+v0000000002a7b140_0 .net "Y", 0 0, L_000000000391c7a0; alias, 1 drivers
+S_00000000026bee00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026be200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cb90 .functor NOT 1, L_000000000380c600, C4<0>, C4<0>, C4<0>;
+L_000000000391c7a0 .functor BUF 1, L_000000000391cb90, C4<0>, C4<0>, C4<0>;
+v0000000002a79d40_0 .net "A", 0 0, L_000000000380c600; alias, 1 drivers
+L_0000000002973630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a790c0_0 .net8 "VGND", 0 0, L_0000000002973630; 1 drivers, strength-aware
+L_0000000002974820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79f20_0 .net8 "VNB", 0 0, L_0000000002974820; 1 drivers, strength-aware
+L_00000000029738d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a380_0 .net8 "VPB", 0 0, L_00000000029738d0; 1 drivers, strength-aware
+L_0000000002973940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ae20_0 .net8 "VPWR", 0 0, L_0000000002973940; 1 drivers, strength-aware
+v0000000002a797a0_0 .net "Y", 0 0, L_000000000391c7a0; alias, 1 drivers
+v0000000002a79160_0 .net "not0_out_Y", 0 0, L_000000000391cb90; 1 drivers
+S_00000000026c3900 .scope module, "_202_" "sky130_fd_sc_hd__nor2_2" 3 262, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a798e0_0 .net "A", 0 0, L_0000000003926750; alias, 1 drivers
+v0000000002a7b0a0_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002973a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a560_0 .net8 "VGND", 0 0, L_0000000002973a20; 1 drivers, strength-aware
+L_0000000002974c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79e80_0 .net8 "VNB", 0 0, L_0000000002974c80; 1 drivers, strength-aware
+L_0000000002974f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a600_0 .net8 "VPB", 0 0, L_0000000002974f90; 1 drivers, strength-aware
+L_0000000002974cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a79980_0 .net8 "VPWR", 0 0, L_0000000002974cf0; 1 drivers, strength-aware
+v0000000002a7b6e0_0 .net "Y", 0 0, L_000000000391cce0; 1 drivers
+S_00000000026bef80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026c3900;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d990 .functor NOR 1, L_0000000003926750, L_000000000391ce30, C4<0>, C4<0>;
+L_000000000391cce0 .functor BUF 1, L_000000000391d990, C4<0>, C4<0>, C4<0>;
+v0000000002a79ac0_0 .net "A", 0 0, L_0000000003926750; alias, 1 drivers
+v0000000002a7a2e0_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a420_0 .net8 "VGND", 0 0, L_0000000002974d60; 1 drivers, strength-aware
+L_0000000002974dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b5a0_0 .net8 "VNB", 0 0, L_0000000002974dd0; 1 drivers, strength-aware
+L_0000000002974a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b3c0_0 .net8 "VPB", 0 0, L_0000000002974a50; 1 drivers, strength-aware
+L_0000000002974e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b000_0 .net8 "VPWR", 0 0, L_0000000002974e40; 1 drivers, strength-aware
+v0000000002a79840_0 .net "Y", 0 0, L_000000000391cce0; alias, 1 drivers
+v0000000002a7a060_0 .net "nor0_out_Y", 0 0, L_000000000391d990; 1 drivers
+S_00000000026c0600 .scope module, "_203_" "sky130_fd_sc_hd__nor2_2" 3 267, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7dda0_0 .net "A", 0 0, L_0000000003925f70; alias, 1 drivers
+v0000000002a7d080_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c4a0_0 .net8 "VGND", 0 0, L_0000000002974eb0; 1 drivers, strength-aware
+L_0000000002974890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ccc0_0 .net8 "VNB", 0 0, L_0000000002974890; 1 drivers, strength-aware
+L_0000000002974970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c5e0_0 .net8 "VPB", 0 0, L_0000000002974970; 1 drivers, strength-aware
+L_0000000002974900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d580_0 .net8 "VPWR", 0 0, L_0000000002974900; 1 drivers, strength-aware
+v0000000002a7ba00_0 .net "Y", 0 0, L_000000000391c810; 1 drivers
+S_00000000026c1080 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026c0600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d370 .functor NOR 1, L_0000000003925f70, L_000000000391ce30, C4<0>, C4<0>;
+L_000000000391c810 .functor BUF 1, L_000000000391d370, C4<0>, C4<0>, C4<0>;
+v0000000002a7a740_0 .net "A", 0 0, L_0000000003925f70; alias, 1 drivers
+v0000000002a7a7e0_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a79b60_0 .net8 "VGND", 0 0, L_0000000002974f20; 1 drivers, strength-aware
+L_00000000029749e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7a9c0_0 .net8 "VNB", 0 0, L_00000000029749e0; 1 drivers, strength-aware
+L_0000000002974ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7aa60_0 .net8 "VPB", 0 0, L_0000000002974ba0; 1 drivers, strength-aware
+L_0000000002974ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a79ca0_0 .net8 "VPWR", 0 0, L_0000000002974ac0; 1 drivers, strength-aware
+v0000000002a79de0_0 .net "Y", 0 0, L_000000000391c810; alias, 1 drivers
+v0000000002a7c7c0_0 .net "nor0_out_Y", 0 0, L_000000000391d370; 1 drivers
+S_00000000026c2d00 .scope module, "_204_" "sky130_fd_sc_hd__nor2_2" 3 272, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7bb40_0 .net "A", 0 0, L_0000000003928350; alias, 1 drivers
+v0000000002a7ca40_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_0000000002974b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7db20_0 .net8 "VGND", 0 0, L_0000000002974b30; 1 drivers, strength-aware
+L_0000000002974c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7dd00_0 .net8 "VNB", 0 0, L_0000000002974c10; 1 drivers, strength-aware
+L_0000000003836d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7cd60_0 .net8 "VPB", 0 0, L_0000000003836d90; 1 drivers, strength-aware
+L_0000000003836620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7de40_0 .net8 "VPWR", 0 0, L_0000000003836620; 1 drivers, strength-aware
+v0000000002a7c540_0 .net "Y", 0 0, L_000000000391cab0; 1 drivers
+S_00000000026c3000 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026c2d00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391c5e0 .functor NOR 1, L_0000000003928350, L_000000000391ce30, C4<0>, C4<0>;
+L_000000000391cab0 .functor BUF 1, L_000000000391c5e0, C4<0>, C4<0>, C4<0>;
+v0000000002a7bc80_0 .net "A", 0 0, L_0000000003928350; alias, 1 drivers
+v0000000002a7c400_0 .net "B", 0 0, L_000000000391ce30; alias, 1 drivers
+L_00000000038372d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7bbe0_0 .net8 "VGND", 0 0, L_00000000038372d0; 1 drivers, strength-aware
+L_00000000038370a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7bd20_0 .net8 "VNB", 0 0, L_00000000038370a0; 1 drivers, strength-aware
+L_0000000003836700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7dc60_0 .net8 "VPB", 0 0, L_0000000003836700; 1 drivers, strength-aware
+L_0000000003836310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c860_0 .net8 "VPWR", 0 0, L_0000000003836310; 1 drivers, strength-aware
+v0000000002a7baa0_0 .net "Y", 0 0, L_000000000391cab0; alias, 1 drivers
+v0000000002a7c9a0_0 .net "nor0_out_Y", 0 0, L_000000000391c5e0; 1 drivers
+S_00000000026c2a00 .scope module, "_205_" "sky130_fd_sc_hd__nor2_2" 3 277, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7d940_0 .net "A", 0 0, L_00000000039285f0; alias, 1 drivers
+v0000000002a7df80_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_00000000038371f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d760_0 .net8 "VGND", 0 0, L_00000000038371f0; 1 drivers, strength-aware
+L_0000000003836000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d3a0_0 .net8 "VNB", 0 0, L_0000000003836000; 1 drivers, strength-aware
+L_0000000003836d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7bdc0_0 .net8 "VPB", 0 0, L_0000000003836d20; 1 drivers, strength-aware
+L_0000000003836e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7cae0_0 .net8 "VPWR", 0 0, L_0000000003836e00; 1 drivers, strength-aware
+v0000000002a7bfa0_0 .net "Y", 0 0, L_000000000391ddf0; 1 drivers
+S_00000000026bf100 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026c2a00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d300 .functor NOR 1, L_00000000039285f0, L_000000000391e090, C4<0>, C4<0>;
+L_000000000391ddf0 .functor BUF 1, L_000000000391d300, C4<0>, C4<0>, C4<0>;
+v0000000002a7d1c0_0 .net "A", 0 0, L_00000000039285f0; alias, 1 drivers
+v0000000002a7c680_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_0000000003835e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d300_0 .net8 "VGND", 0 0, L_0000000003835e40; 1 drivers, strength-aware
+L_0000000003836380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e020_0 .net8 "VNB", 0 0, L_0000000003836380; 1 drivers, strength-aware
+L_0000000003835c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c720_0 .net8 "VPB", 0 0, L_0000000003835c80; 1 drivers, strength-aware
+L_0000000003835cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7cea0_0 .net8 "VPWR", 0 0, L_0000000003835cf0; 1 drivers, strength-aware
+v0000000002a7c360_0 .net "Y", 0 0, L_000000000391ddf0; alias, 1 drivers
+v0000000002a7cb80_0 .net "nor0_out_Y", 0 0, L_000000000391d300; 1 drivers
+S_00000000026c2b80 .scope module, "_206_" "sky130_fd_sc_hd__inv_2" 3 282, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a7ce00_0 .net "A", 0 0, L_000000000380b8e0; 1 drivers
+L_0000000003836ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d4e0_0 .net8 "VGND", 0 0, L_0000000003836ee0; 1 drivers, strength-aware
+L_0000000003835eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d9e0_0 .net8 "VNB", 0 0, L_0000000003835eb0; 1 drivers, strength-aware
+L_0000000003836e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7dee0_0 .net8 "VPB", 0 0, L_0000000003836e70; 1 drivers, strength-aware
+L_0000000003837030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7cfe0_0 .net8 "VPWR", 0 0, L_0000000003837030; 1 drivers, strength-aware
+v0000000002a7da80_0 .net "Y", 0 0, L_000000000391ca40; alias, 1 drivers
+S_00000000026c3a80 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026c2b80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391da00 .functor NOT 1, L_000000000380b8e0, C4<0>, C4<0>, C4<0>;
+L_000000000391ca40 .functor BUF 1, L_000000000391da00, C4<0>, C4<0>, C4<0>;
+v0000000002a7d260_0 .net "A", 0 0, L_000000000380b8e0; alias, 1 drivers
+L_00000000038361c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c900_0 .net8 "VGND", 0 0, L_00000000038361c0; 1 drivers, strength-aware
+L_0000000003836150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b8c0_0 .net8 "VNB", 0 0, L_0000000003836150; 1 drivers, strength-aware
+L_0000000003836070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7cc20_0 .net8 "VPB", 0 0, L_0000000003836070; 1 drivers, strength-aware
+L_0000000003837570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d8a0_0 .net8 "VPWR", 0 0, L_0000000003837570; 1 drivers, strength-aware
+v0000000002a7d440_0 .net "Y", 0 0, L_000000000391ca40; alias, 1 drivers
+v0000000002a7cf40_0 .net "not0_out_Y", 0 0, L_000000000391da00; 1 drivers
+S_00000000026be680 .scope module, "_207_" "sky130_fd_sc_hd__nor2_2" 3 286, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7d800_0 .net "A", 0 0, L_0000000003928190; alias, 1 drivers
+v0000000002a7c0e0_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_00000000038369a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c040_0 .net8 "VGND", 0 0, L_00000000038369a0; 1 drivers, strength-aware
+L_0000000003836c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c180_0 .net8 "VNB", 0 0, L_0000000003836c40; 1 drivers, strength-aware
+L_0000000003837500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7c2c0_0 .net8 "VPB", 0 0, L_0000000003837500; 1 drivers, strength-aware
+L_0000000003836f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f380_0 .net8 "VPWR", 0 0, L_0000000003836f50; 1 drivers, strength-aware
+v0000000002a7e700_0 .net "Y", 0 0, L_000000000391d0d0; 1 drivers
+S_00000000026be800 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026be680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d060 .functor NOR 1, L_0000000003928190, L_000000000391e090, C4<0>, C4<0>;
+L_000000000391d0d0 .functor BUF 1, L_000000000391d060, C4<0>, C4<0>, C4<0>;
+v0000000002a7d120_0 .net "A", 0 0, L_0000000003928190; alias, 1 drivers
+v0000000002a7c220_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_0000000003837650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7be60_0 .net8 "VGND", 0 0, L_0000000003837650; 1 drivers, strength-aware
+L_0000000003836a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7d620_0 .net8 "VNB", 0 0, L_0000000003836a10; 1 drivers, strength-aware
+L_0000000003836fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7dbc0_0 .net8 "VPB", 0 0, L_0000000003836fc0; 1 drivers, strength-aware
+L_0000000003835d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7b960_0 .net8 "VPWR", 0 0, L_0000000003835d60; 1 drivers, strength-aware
+v0000000002a7bf00_0 .net "Y", 0 0, L_000000000391d0d0; alias, 1 drivers
+v0000000002a7d6c0_0 .net "nor0_out_Y", 0 0, L_000000000391d060; 1 drivers
+S_00000000026bdc00 .scope module, "_208_" "sky130_fd_sc_hd__nor2_2" 3 291, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a7ff60_0 .net "A", 0 0, L_0000000003926e50; alias, 1 drivers
+v0000000002a7f560_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_0000000003835f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f100_0 .net8 "VGND", 0 0, L_0000000003835f20; 1 drivers, strength-aware
+L_00000000038363f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f4c0_0 .net8 "VNB", 0 0, L_00000000038363f0; 1 drivers, strength-aware
+L_0000000003836460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e840_0 .net8 "VPB", 0 0, L_0000000003836460; 1 drivers, strength-aware
+L_0000000003837110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7fd80_0 .net8 "VPWR", 0 0, L_0000000003837110; 1 drivers, strength-aware
+v0000000002a7fba0_0 .net "Y", 0 0, L_000000000391d140; 1 drivers
+S_00000000026c3600 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000026bdc00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391c8f0 .functor NOR 1, L_0000000003926e50, L_000000000391e090, C4<0>, C4<0>;
+L_000000000391d140 .functor BUF 1, L_000000000391c8f0, C4<0>, C4<0>, C4<0>;
+v0000000002a7e3e0_0 .net "A", 0 0, L_0000000003926e50; alias, 1 drivers
+v0000000002a7f420_0 .net "B", 0 0, L_000000000391e090; alias, 1 drivers
+L_0000000003837180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a80140_0 .net8 "VGND", 0 0, L_0000000003837180; 1 drivers, strength-aware
+L_0000000003837260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a801e0_0 .net8 "VNB", 0 0, L_0000000003837260; 1 drivers, strength-aware
+L_0000000003836a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e0c0_0 .net8 "VPB", 0 0, L_0000000003836a80; 1 drivers, strength-aware
+L_00000000038364d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e7a0_0 .net8 "VPWR", 0 0, L_00000000038364d0; 1 drivers, strength-aware
+v0000000002a7f060_0 .net "Y", 0 0, L_000000000391d140; alias, 1 drivers
+v0000000002a80460_0 .net "nor0_out_Y", 0 0, L_000000000391c8f0; 1 drivers
+S_00000000026bec80 .scope module, "_209_" "sky130_fd_sc_hd__inv_2" 3 296, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a7f740_0 .net "A", 0 0, L_0000000003926360; alias, 1 drivers
+L_00000000038360e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e480_0 .net8 "VGND", 0 0, L_00000000038360e0; 1 drivers, strength-aware
+L_0000000003836230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e200_0 .net8 "VNB", 0 0, L_0000000003836230; 1 drivers, strength-aware
+L_0000000003835dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7fec0_0 .net8 "VPB", 0 0, L_0000000003835dd0; 1 drivers, strength-aware
+L_00000000038367e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e160_0 .net8 "VPWR", 0 0, L_00000000038367e0; 1 drivers, strength-aware
+v0000000002a7f920_0 .net "Y", 0 0, L_000000000391df40; alias, 1 drivers
+S_00000000026bf700 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026bec80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391c650 .functor NOT 1, L_0000000003926360, C4<0>, C4<0>, C4<0>;
+L_000000000391df40 .functor BUF 1, L_000000000391c650, C4<0>, C4<0>, C4<0>;
+v0000000002a806e0_0 .net "A", 0 0, L_0000000003926360; alias, 1 drivers
+L_0000000003836850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e660_0 .net8 "VGND", 0 0, L_0000000003836850; 1 drivers, strength-aware
+L_0000000003836770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7efc0_0 .net8 "VNB", 0 0, L_0000000003836770; 1 drivers, strength-aware
+L_00000000038368c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f1a0_0 .net8 "VPB", 0 0, L_00000000038368c0; 1 drivers, strength-aware
+L_00000000038362a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7eca0_0 .net8 "VPWR", 0 0, L_00000000038362a0; 1 drivers, strength-aware
+v0000000002a7fe20_0 .net "Y", 0 0, L_000000000391df40; alias, 1 drivers
+v0000000002a7f240_0 .net "not0_out_Y", 0 0, L_000000000391c650; 1 drivers
+S_00000000026bf880 .scope module, "_210_" "sky130_fd_sc_hd__inv_2" 3 300, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a7fc40_0 .net "A", 0 0, L_0000000003926830; alias, 1 drivers
+L_0000000003836540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ea20_0 .net8 "VGND", 0 0, L_0000000003836540; 1 drivers, strength-aware
+L_0000000003836cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a80500_0 .net8 "VNB", 0 0, L_0000000003836cb0; 1 drivers, strength-aware
+L_0000000003837340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ed40_0 .net8 "VPB", 0 0, L_0000000003837340; 1 drivers, strength-aware
+L_00000000038365b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7eb60_0 .net8 "VPWR", 0 0, L_00000000038365b0; 1 drivers, strength-aware
+v0000000002a7e980_0 .net "Y", 0 0, L_000000000391d760; alias, 1 drivers
+S_00000000029c55d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000026bf880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391c9d0 .functor NOT 1, L_0000000003926830, C4<0>, C4<0>, C4<0>;
+L_000000000391d760 .functor BUF 1, L_000000000391c9d0, C4<0>, C4<0>, C4<0>;
+v0000000002a7e340_0 .net "A", 0 0, L_0000000003926830; alias, 1 drivers
+L_0000000003837810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f880_0 .net8 "VGND", 0 0, L_0000000003837810; 1 drivers, strength-aware
+L_0000000003836690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7fce0_0 .net8 "VNB", 0 0, L_0000000003836690; 1 drivers, strength-aware
+L_0000000003836930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f2e0_0 .net8 "VPB", 0 0, L_0000000003836930; 1 drivers, strength-aware
+L_00000000038375e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a803c0_0 .net8 "VPWR", 0 0, L_00000000038375e0; 1 drivers, strength-aware
+v0000000002a7fa60_0 .net "Y", 0 0, L_000000000391d760; alias, 1 drivers
+v0000000002a7e8e0_0 .net "not0_out_Y", 0 0, L_000000000391c9d0; 1 drivers
+S_00000000029c52d0 .scope module, "_211_" "sky130_fd_sc_hd__inv_2" 3 304, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a80640_0 .net "A", 0 0, L_0000000003927160; alias, 1 drivers
+L_00000000038376c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f7e0_0 .net8 "VGND", 0 0, L_00000000038376c0; 1 drivers, strength-aware
+L_0000000003836af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a805a0_0 .net8 "VNB", 0 0, L_0000000003836af0; 1 drivers, strength-aware
+L_0000000003836b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ede0_0 .net8 "VPB", 0 0, L_0000000003836b60; 1 drivers, strength-aware
+L_00000000038377a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ee80_0 .net8 "VPWR", 0 0, L_00000000038377a0; 1 drivers, strength-aware
+v0000000002a7ef20_0 .net "Y", 0 0, L_000000000391cb20; alias, 1 drivers
+S_00000000029c6350 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c52d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cf80 .functor NOT 1, L_0000000003927160, C4<0>, C4<0>, C4<0>;
+L_000000000391cb20 .functor BUF 1, L_000000000391cf80, C4<0>, C4<0>, C4<0>;
+v0000000002a7f600_0 .net "A", 0 0, L_0000000003927160; alias, 1 drivers
+L_0000000003836bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a80280_0 .net8 "VGND", 0 0, L_0000000003836bd0; 1 drivers, strength-aware
+L_00000000038373b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7e520_0 .net8 "VNB", 0 0, L_00000000038373b0; 1 drivers, strength-aware
+L_0000000003835f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7eac0_0 .net8 "VPB", 0 0, L_0000000003835f90; 1 drivers, strength-aware
+L_0000000003837420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a7ec00_0 .net8 "VPWR", 0 0, L_0000000003837420; 1 drivers, strength-aware
+v0000000002a7f6a0_0 .net "Y", 0 0, L_000000000391cb20; alias, 1 drivers
+v0000000002a7e5c0_0 .net "not0_out_Y", 0 0, L_000000000391cf80; 1 drivers
+S_00000000029c5150 .scope module, "_212_" "sky130_fd_sc_hd__inv_2" 3 308, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a80320_0 .net "A", 0 0, L_000000000380ad00; 1 drivers
+L_0000000003837490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81220_0 .net8 "VGND", 0 0, L_0000000003837490; 1 drivers, strength-aware
+L_0000000003837730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81860_0 .net8 "VNB", 0 0, L_0000000003837730; 1 drivers, strength-aware
+L_00000000038380d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a81540_0 .net8 "VPB", 0 0, L_00000000038380d0; 1 drivers, strength-aware
+L_0000000003838060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a81ae0_0 .net8 "VPWR", 0 0, L_0000000003838060; 1 drivers, strength-aware
+v0000000002a80be0_0 .net "Y", 0 0, L_000000000391d7d0; alias, 1 drivers
+S_00000000029c4550 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c5150;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cd50 .functor NOT 1, L_000000000380ad00, C4<0>, C4<0>, C4<0>;
+L_000000000391d7d0 .functor BUF 1, L_000000000391cd50, C4<0>, C4<0>, C4<0>;
+v0000000002a80780_0 .net "A", 0 0, L_000000000380ad00; alias, 1 drivers
+L_0000000003838b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7f9c0_0 .net8 "VGND", 0 0, L_0000000003838b50; 1 drivers, strength-aware
+L_00000000038391e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a7fb00_0 .net8 "VNB", 0 0, L_00000000038391e0; 1 drivers, strength-aware
+L_0000000003839170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80820_0 .net8 "VPB", 0 0, L_0000000003839170; 1 drivers, strength-aware
+L_00000000038393a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80000_0 .net8 "VPWR", 0 0, L_00000000038393a0; 1 drivers, strength-aware
+v0000000002a7e2a0_0 .net "Y", 0 0, L_000000000391d7d0; alias, 1 drivers
+v0000000002a800a0_0 .net "not0_out_Y", 0 0, L_000000000391cd50; 1 drivers
+S_00000000029c76d0 .scope module, "_213_" "sky130_fd_sc_hd__inv_2" 3 312, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a823a0_0 .net "A", 0 0, L_0000000003928430; alias, 1 drivers
+L_00000000038387d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81360_0 .net8 "VGND", 0 0, L_00000000038387d0; 1 drivers, strength-aware
+L_0000000003838140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81b80_0 .net8 "VNB", 0 0, L_0000000003838140; 1 drivers, strength-aware
+L_0000000003838df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80a00_0 .net8 "VPB", 0 0, L_0000000003838df0; 1 drivers, strength-aware
+L_0000000003837d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80fa0_0 .net8 "VPWR", 0 0, L_0000000003837d50; 1 drivers, strength-aware
+v0000000002a80e60_0 .net "Y", 0 0, L_000000000391dca0; alias, 1 drivers
+S_00000000029c9dd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c76d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cc00 .functor NOT 1, L_0000000003928430, C4<0>, C4<0>, C4<0>;
+L_000000000391dca0 .functor BUF 1, L_000000000391cc00, C4<0>, C4<0>, C4<0>;
+v0000000002a812c0_0 .net "A", 0 0, L_0000000003928430; alias, 1 drivers
+L_0000000003838450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a80c80_0 .net8 "VGND", 0 0, L_0000000003838450; 1 drivers, strength-aware
+L_0000000003838a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a817c0_0 .net8 "VNB", 0 0, L_0000000003838a00; 1 drivers, strength-aware
+L_00000000038384c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a821c0_0 .net8 "VPB", 0 0, L_00000000038384c0; 1 drivers, strength-aware
+L_0000000003837e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82760_0 .net8 "VPWR", 0 0, L_0000000003837e30; 1 drivers, strength-aware
+v0000000002a80dc0_0 .net "Y", 0 0, L_000000000391dca0; alias, 1 drivers
+v0000000002a82a80_0 .net "not0_out_Y", 0 0, L_000000000391cc00; 1 drivers
+S_00000000029c9650 .scope module, "_214_" "sky130_fd_sc_hd__inv_2" 3 316, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a814a0_0 .net "A", 0 0, L_0000000003928270; alias, 1 drivers
+L_00000000038378f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82120_0 .net8 "VGND", 0 0, L_00000000038378f0; 1 drivers, strength-aware
+L_00000000038381b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82bc0_0 .net8 "VNB", 0 0, L_00000000038381b0; 1 drivers, strength-aware
+L_0000000003837ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a81f40_0 .net8 "VPB", 0 0, L_0000000003837ea0; 1 drivers, strength-aware
+L_0000000003839330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82580_0 .net8 "VPWR", 0 0, L_0000000003839330; 1 drivers, strength-aware
+v0000000002a819a0_0 .net "Y", 0 0, L_000000000391cc70; alias, 1 drivers
+S_00000000029c67d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c9650;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391dae0 .functor NOT 1, L_0000000003928270, C4<0>, C4<0>, C4<0>;
+L_000000000391cc70 .functor BUF 1, L_000000000391dae0, C4<0>, C4<0>, C4<0>;
+v0000000002a80f00_0 .net "A", 0 0, L_0000000003928270; alias, 1 drivers
+L_0000000003838290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83020_0 .net8 "VGND", 0 0, L_0000000003838290; 1 drivers, strength-aware
+L_0000000003838220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81900_0 .net8 "VNB", 0 0, L_0000000003838220; 1 drivers, strength-aware
+L_0000000003837ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82f80_0 .net8 "VPB", 0 0, L_0000000003837ff0; 1 drivers, strength-aware
+L_0000000003838ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a81040_0 .net8 "VPWR", 0 0, L_0000000003838ed0; 1 drivers, strength-aware
+v0000000002a82260_0 .net "Y", 0 0, L_000000000391cc70; alias, 1 drivers
+v0000000002a81c20_0 .net "not0_out_Y", 0 0, L_000000000391dae0; 1 drivers
+S_00000000029c6650 .scope module, "_215_" "sky130_fd_sc_hd__inv_2" 3 320, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a81cc0_0 .net "A", 0 0, L_0000000003927550; alias, 1 drivers
+L_0000000003837f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a829e0_0 .net8 "VGND", 0 0, L_0000000003837f10; 1 drivers, strength-aware
+L_0000000003838300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82c60_0 .net8 "VNB", 0 0, L_0000000003838300; 1 drivers, strength-aware
+L_0000000003838530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a826c0_0 .net8 "VPB", 0 0, L_0000000003838530; 1 drivers, strength-aware
+L_00000000038385a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a810e0_0 .net8 "VPWR", 0 0, L_00000000038385a0; 1 drivers, strength-aware
+v0000000002a82440_0 .net "Y", 0 0, L_000000000391c6c0; alias, 1 drivers
+S_00000000029c97d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c6650;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391dfb0 .functor NOT 1, L_0000000003927550, C4<0>, C4<0>, C4<0>;
+L_000000000391c6c0 .functor BUF 1, L_000000000391dfb0, C4<0>, C4<0>, C4<0>;
+v0000000002a82b20_0 .net "A", 0 0, L_0000000003927550; alias, 1 drivers
+L_0000000003838920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82940_0 .net8 "VGND", 0 0, L_0000000003838920; 1 drivers, strength-aware
+L_00000000038383e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82300_0 .net8 "VNB", 0 0, L_00000000038383e0; 1 drivers, strength-aware
+L_0000000003837b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80d20_0 .net8 "VPB", 0 0, L_0000000003837b90; 1 drivers, strength-aware
+L_0000000003839410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82ee0_0 .net8 "VPWR", 0 0, L_0000000003839410; 1 drivers, strength-aware
+v0000000002a81a40_0 .net "Y", 0 0, L_000000000391c6c0; alias, 1 drivers
+v0000000002a81d60_0 .net "not0_out_Y", 0 0, L_000000000391dfb0; 1 drivers
+S_00000000029c5450 .scope module, "_216_" "sky130_fd_sc_hd__buf_1" 3 324, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a81ea0_0 .net "A", 0 0, L_000000000391dd10; alias, 1 drivers
+L_0000000003838370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a80960_0 .net8 "VGND", 0 0, L_0000000003838370; 1 drivers, strength-aware
+L_0000000003838d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81400_0 .net8 "VNB", 0 0, L_0000000003838d10; 1 drivers, strength-aware
+L_0000000003837880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a81fe0_0 .net8 "VPB", 0 0, L_0000000003837880; 1 drivers, strength-aware
+L_0000000003838d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82080_0 .net8 "VPWR", 0 0, L_0000000003838d80; 1 drivers, strength-aware
+v0000000002a81680_0 .net "X", 0 0, L_000000000391d3e0; alias, 1 drivers
+S_00000000029c6950 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000029c5450;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391de60 .functor BUF 1, L_000000000391dd10, C4<0>, C4<0>, C4<0>;
+L_000000000391d3e0 .functor BUF 1, L_000000000391de60, C4<0>, C4<0>, C4<0>;
+v0000000002a82d00_0 .net "A", 0 0, L_000000000391dd10; alias, 1 drivers
+L_0000000003838610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a81180_0 .net8 "VGND", 0 0, L_0000000003838610; 1 drivers, strength-aware
+L_0000000003839100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82620_0 .net8 "VNB", 0 0, L_0000000003839100; 1 drivers, strength-aware
+L_0000000003837ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a808c0_0 .net8 "VPB", 0 0, L_0000000003837ab0; 1 drivers, strength-aware
+L_0000000003838680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a815e0_0 .net8 "VPWR", 0 0, L_0000000003838680; 1 drivers, strength-aware
+v0000000002a824e0_0 .net "X", 0 0, L_000000000391d3e0; alias, 1 drivers
+v0000000002a81e00_0 .net "buf0_out_X", 0 0, L_000000000391de60; 1 drivers
+S_00000000029c6ad0 .scope module, "_217_" "sky130_fd_sc_hd__inv_2" 3 328, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a83660_0 .net "A", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_0000000003837960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83d40_0 .net8 "VGND", 0 0, L_0000000003837960; 1 drivers, strength-aware
+L_0000000003837f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83700_0 .net8 "VNB", 0 0, L_0000000003837f80; 1 drivers, strength-aware
+L_00000000038379d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a853c0_0 .net8 "VPB", 0 0, L_00000000038379d0; 1 drivers, strength-aware
+L_0000000003838c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84ce0_0 .net8 "VPWR", 0 0, L_0000000003838c30; 1 drivers, strength-aware
+v0000000002a841a0_0 .net "Y", 0 0, L_000000000391db50; alias, 1 drivers
+S_00000000029c70d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c6ad0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391d680 .functor NOT 1, L_000000000391d3e0, C4<0>, C4<0>, C4<0>;
+L_000000000391db50 .functor BUF 1, L_000000000391d680, C4<0>, C4<0>, C4<0>;
+v0000000002a82800_0 .net "A", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_0000000003838990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a828a0_0 .net8 "VGND", 0 0, L_0000000003838990; 1 drivers, strength-aware
+L_00000000038386f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a82da0_0 .net8 "VNB", 0 0, L_00000000038386f0; 1 drivers, strength-aware
+L_0000000003838760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a82e40_0 .net8 "VPB", 0 0, L_0000000003838760; 1 drivers, strength-aware
+L_0000000003838e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a80aa0_0 .net8 "VPWR", 0 0, L_0000000003838e60; 1 drivers, strength-aware
+v0000000002a80b40_0 .net "Y", 0 0, L_000000000391db50; alias, 1 drivers
+v0000000002a81720_0 .net "not0_out_Y", 0 0, L_000000000391d680; 1 drivers
+S_00000000029c7e50 .scope module, "_218_" "sky130_fd_sc_hd__buf_1" 3 332, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a84ec0_0 .net "A", 0 0, L_000000000391db50; alias, 1 drivers
+L_0000000003837a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84740_0 .net8 "VGND", 0 0, L_0000000003837a40; 1 drivers, strength-aware
+L_0000000003837b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83480_0 .net8 "VNB", 0 0, L_0000000003837b20; 1 drivers, strength-aware
+L_0000000003837c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a83200_0 .net8 "VPB", 0 0, L_0000000003837c00; 1 drivers, strength-aware
+L_0000000003838bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84f60_0 .net8 "VPWR", 0 0, L_0000000003838bc0; 1 drivers, strength-aware
+v0000000002a830c0_0 .net "X", 0 0, L_000000000391d840; alias, 1 drivers
+S_00000000029c6c50 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000029c7e50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cdc0 .functor BUF 1, L_000000000391db50, C4<0>, C4<0>, C4<0>;
+L_000000000391d840 .functor BUF 1, L_000000000391cdc0, C4<0>, C4<0>, C4<0>;
+v0000000002a85500_0 .net "A", 0 0, L_000000000391db50; alias, 1 drivers
+L_0000000003838f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83340_0 .net8 "VGND", 0 0, L_0000000003838f40; 1 drivers, strength-aware
+L_0000000003837c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83c00_0 .net8 "VNB", 0 0, L_0000000003837c70; 1 drivers, strength-aware
+L_0000000003838840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a83b60_0 .net8 "VPB", 0 0, L_0000000003838840; 1 drivers, strength-aware
+L_00000000038388b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84d80_0 .net8 "VPWR", 0 0, L_00000000038388b0; 1 drivers, strength-aware
+v0000000002a855a0_0 .net "X", 0 0, L_000000000391d840; alias, 1 drivers
+v0000000002a84e20_0 .net "buf0_out_X", 0 0, L_000000000391cdc0; 1 drivers
+S_00000000029c91d0 .scope module, "_219_" "sky130_fd_sc_hd__inv_2" 3 336, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a84060_0 .net "A", 0 0, L_0000000003927940; alias, 1 drivers
+L_0000000003838a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85320_0 .net8 "VGND", 0 0, L_0000000003838a70; 1 drivers, strength-aware
+L_0000000003837ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85640_0 .net8 "VNB", 0 0, L_0000000003837ce0; 1 drivers, strength-aware
+L_0000000003838ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a833e0_0 .net8 "VPB", 0 0, L_0000000003838ae0; 1 drivers, strength-aware
+L_0000000003838fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a856e0_0 .net8 "VPWR", 0 0, L_0000000003838fb0; 1 drivers, strength-aware
+v0000000002a84920_0 .net "Y", 0 0, L_000000000391dbc0; alias, 1 drivers
+S_00000000029c9050 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c91d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391d8b0 .functor NOT 1, L_0000000003927940, C4<0>, C4<0>, C4<0>;
+L_000000000391dbc0 .functor BUF 1, L_000000000391d8b0, C4<0>, C4<0>, C4<0>;
+v0000000002a837a0_0 .net "A", 0 0, L_0000000003927940; alias, 1 drivers
+L_0000000003837dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84420_0 .net8 "VGND", 0 0, L_0000000003837dc0; 1 drivers, strength-aware
+L_0000000003838ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85460_0 .net8 "VNB", 0 0, L_0000000003838ca0; 1 drivers, strength-aware
+L_0000000003839020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a83fc0_0 .net8 "VPB", 0 0, L_0000000003839020; 1 drivers, strength-aware
+L_0000000003839090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a832a0_0 .net8 "VPWR", 0 0, L_0000000003839090; 1 drivers, strength-aware
+v0000000002a851e0_0 .net "Y", 0 0, L_000000000391dbc0; alias, 1 drivers
+v0000000002a83840_0 .net "not0_out_Y", 0 0, L_000000000391d8b0; 1 drivers
+S_00000000029c64d0 .scope module, "_220_" "sky130_fd_sc_hd__inv_2" 3 340, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a83de0_0 .net "A", 0 0, L_0000000003926910; alias, 1 drivers
+L_0000000003839250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85780_0 .net8 "VGND", 0 0, L_0000000003839250; 1 drivers, strength-aware
+L_00000000038392c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84600_0 .net8 "VNB", 0 0, L_00000000038392c0; 1 drivers, strength-aware
+L_0000000003839b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a85820_0 .net8 "VPB", 0 0, L_0000000003839b10; 1 drivers, strength-aware
+L_0000000003839950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a844c0_0 .net8 "VPWR", 0 0, L_0000000003839950; 1 drivers, strength-aware
+v0000000002a838e0_0 .net "Y", 0 0, L_000000000391cf10; alias, 1 drivers
+S_00000000029c8bd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c64d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391d610 .functor NOT 1, L_0000000003926910, C4<0>, C4<0>, C4<0>;
+L_000000000391cf10 .functor BUF 1, L_000000000391d610, C4<0>, C4<0>, C4<0>;
+v0000000002a84880_0 .net "A", 0 0, L_0000000003926910; alias, 1 drivers
+L_000000000383a7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84240_0 .net8 "VGND", 0 0, L_000000000383a7c0; 1 drivers, strength-aware
+L_000000000383ac90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85280_0 .net8 "VNB", 0 0, L_000000000383ac90; 1 drivers, strength-aware
+L_000000000383a910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a83520_0 .net8 "VPB", 0 0, L_000000000383a910; 1 drivers, strength-aware
+L_0000000003839f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84ba0_0 .net8 "VPWR", 0 0, L_0000000003839f00; 1 drivers, strength-aware
+v0000000002a83ca0_0 .net "Y", 0 0, L_000000000391cf10; alias, 1 drivers
+v0000000002a835c0_0 .net "not0_out_Y", 0 0, L_000000000391d610; 1 drivers
+S_00000000029c4e50 .scope module, "_221_" "sky130_fd_sc_hd__inv_2" 3 344, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a83a20_0 .net "A", 0 0, L_00000000039284a0; alias, 1 drivers
+L_000000000383a440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83ac0_0 .net8 "VGND", 0 0, L_000000000383a440; 1 drivers, strength-aware
+L_000000000383a1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83f20_0 .net8 "VNB", 0 0, L_000000000383a1a0; 1 drivers, strength-aware
+L_00000000038396b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84100_0 .net8 "VPB", 0 0, L_00000000038396b0; 1 drivers, strength-aware
+L_00000000038398e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84c40_0 .net8 "VPWR", 0 0, L_00000000038398e0; 1 drivers, strength-aware
+v0000000002a842e0_0 .net "Y", 0 0, L_000000000391ded0; alias, 1 drivers
+S_00000000029c6dd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c4e50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391dc30 .functor NOT 1, L_00000000039284a0, C4<0>, C4<0>, C4<0>;
+L_000000000391ded0 .functor BUF 1, L_000000000391dc30, C4<0>, C4<0>, C4<0>;
+v0000000002a83160_0 .net "A", 0 0, L_00000000039284a0; alias, 1 drivers
+L_000000000383a9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a83980_0 .net8 "VGND", 0 0, L_000000000383a9f0; 1 drivers, strength-aware
+L_0000000003839cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84380_0 .net8 "VNB", 0 0, L_0000000003839cd0; 1 drivers, strength-aware
+L_0000000003839d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a84560_0 .net8 "VPB", 0 0, L_0000000003839d40; 1 drivers, strength-aware
+L_000000000383aad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a83e80_0 .net8 "VPWR", 0 0, L_000000000383aad0; 1 drivers, strength-aware
+v0000000002a849c0_0 .net "Y", 0 0, L_000000000391ded0; alias, 1 drivers
+v0000000002a846a0_0 .net "not0_out_Y", 0 0, L_000000000391dc30; 1 drivers
+S_00000000029c7fd0 .scope module, "_222_" "sky130_fd_sc_hd__inv_2" 3 348, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a86fe0_0 .net "A", 0 0, L_000000000380b480; 1 drivers
+L_000000000383a520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a86860_0 .net8 "VGND", 0 0, L_000000000383a520; 1 drivers, strength-aware
+L_0000000003839480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87260_0 .net8 "VNB", 0 0, L_0000000003839480; 1 drivers, strength-aware
+L_0000000003839db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a860e0_0 .net8 "VPB", 0 0, L_0000000003839db0; 1 drivers, strength-aware
+L_000000000383a590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87760_0 .net8 "VPWR", 0 0, L_000000000383a590; 1 drivers, strength-aware
+v0000000002a86d60_0 .net "Y", 0 0, L_000000000391d1b0; alias, 1 drivers
+S_00000000029c43d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c7fd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391cff0 .functor NOT 1, L_000000000380b480, C4<0>, C4<0>, C4<0>;
+L_000000000391d1b0 .functor BUF 1, L_000000000391cff0, C4<0>, C4<0>, C4<0>;
+v0000000002a847e0_0 .net "A", 0 0, L_000000000380b480; alias, 1 drivers
+L_000000000383a130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84a60_0 .net8 "VGND", 0 0, L_000000000383a130; 1 drivers, strength-aware
+L_000000000383ac20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a84b00_0 .net8 "VNB", 0 0, L_000000000383ac20; 1 drivers, strength-aware
+L_000000000383a4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a85000_0 .net8 "VPB", 0 0, L_000000000383a4b0; 1 drivers, strength-aware
+L_000000000383afa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a850a0_0 .net8 "VPWR", 0 0, L_000000000383afa0; 1 drivers, strength-aware
+v0000000002a85140_0 .net "Y", 0 0, L_000000000391d1b0; alias, 1 drivers
+v0000000002a87080_0 .net "not0_out_Y", 0 0, L_000000000391cff0; 1 drivers
+S_00000000029c6f50 .scope module, "_223_" "sky130_fd_sc_hd__inv_2" 3 352, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a869a0_0 .net "A", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003839a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a86540_0 .net8 "VGND", 0 0, L_0000000003839a30; 1 drivers, strength-aware
+L_000000000383a2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a86220_0 .net8 "VNB", 0 0, L_000000000383a2f0; 1 drivers, strength-aware
+L_0000000003839e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87120_0 .net8 "VPB", 0 0, L_0000000003839e20; 1 drivers, strength-aware
+L_000000000383b010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86400_0 .net8 "VPWR", 0 0, L_000000000383b010; 1 drivers, strength-aware
+v0000000002a87300_0 .net "Y", 0 0, L_000000000391d290; alias, 1 drivers
+S_00000000029c5750 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c6f50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e020 .functor NOT 1, L_00000000039263d0, C4<0>, C4<0>, C4<0>;
+L_000000000391d290 .functor BUF 1, L_000000000391e020, C4<0>, C4<0>, C4<0>;
+v0000000002a865e0_0 .net "A", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000383a360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a873a0_0 .net8 "VGND", 0 0, L_000000000383a360; 1 drivers, strength-aware
+L_000000000383ab40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a86900_0 .net8 "VNB", 0 0, L_000000000383ab40; 1 drivers, strength-aware
+L_0000000003839e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a85dc0_0 .net8 "VPB", 0 0, L_0000000003839e90; 1 drivers, strength-aware
+L_000000000383aa60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86a40_0 .net8 "VPWR", 0 0, L_000000000383aa60; 1 drivers, strength-aware
+v0000000002a864a0_0 .net "Y", 0 0, L_000000000391d290; alias, 1 drivers
+v0000000002a85e60_0 .net "not0_out_Y", 0 0, L_000000000391e020; 1 drivers
+S_00000000029c61d0 .scope module, "_224_" "sky130_fd_sc_hd__or2_2" 3 356, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a86180_0 .net "A", 0 0, L_000000000391d1b0; alias, 1 drivers
+v0000000002a86ae0_0 .net "B", 0 0, L_000000000391d290; alias, 1 drivers
+L_0000000003839640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85aa0_0 .net8 "VGND", 0 0, L_0000000003839640; 1 drivers, strength-aware
+L_0000000003839720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a862c0_0 .net8 "VNB", 0 0, L_0000000003839720; 1 drivers, strength-aware
+L_0000000003839f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87bc0_0 .net8 "VPB", 0 0, L_0000000003839f70; 1 drivers, strength-aware
+L_000000000383ae50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86b80_0 .net8 "VPWR", 0 0, L_000000000383ae50; 1 drivers, strength-aware
+v0000000002a86360_0 .net "X", 0 0, L_000000000391d530; alias, 1 drivers
+S_00000000029c5a50 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000029c61d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391d450 .functor OR 1, L_000000000391d290, L_000000000391d1b0, C4<0>, C4<0>;
+L_000000000391d530 .functor BUF 1, L_000000000391d450, C4<0>, C4<0>, C4<0>;
+v0000000002a85d20_0 .net "A", 0 0, L_000000000391d1b0; alias, 1 drivers
+v0000000002a85fa0_0 .net "B", 0 0, L_000000000391d290; alias, 1 drivers
+L_000000000383a050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85f00_0 .net8 "VGND", 0 0, L_000000000383a050; 1 drivers, strength-aware
+L_0000000003839b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87800_0 .net8 "VNB", 0 0, L_0000000003839b80; 1 drivers, strength-aware
+L_0000000003839800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87c60_0 .net8 "VPB", 0 0, L_0000000003839800; 1 drivers, strength-aware
+L_000000000383af30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a85c80_0 .net8 "VPWR", 0 0, L_000000000383af30; 1 drivers, strength-aware
+v0000000002a86040_0 .net "X", 0 0, L_000000000391d530; alias, 1 drivers
+v0000000002a867c0_0 .net "or0_out_X", 0 0, L_000000000391d450; 1 drivers
+S_00000000029c7b50 .scope module, "_225_" "sky130_fd_sc_hd__inv_2" 3 361, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a85a00_0 .net "A", 0 0, L_00000000039286d0; alias, 1 drivers
+L_000000000383a600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87f80_0 .net8 "VGND", 0 0, L_000000000383a600; 1 drivers, strength-aware
+L_00000000038394f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87ee0_0 .net8 "VNB", 0 0, L_00000000038394f0; 1 drivers, strength-aware
+L_000000000383a3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86c20_0 .net8 "VPB", 0 0, L_000000000383a3d0; 1 drivers, strength-aware
+L_000000000383a6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86e00_0 .net8 "VPWR", 0 0, L_000000000383a6e0; 1 drivers, strength-aware
+v0000000002a85be0_0 .net "Y", 0 0, L_000000000391fbb0; alias, 1 drivers
+S_00000000029c8150 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c7b50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e2c0 .functor NOT 1, L_00000000039286d0, C4<0>, C4<0>, C4<0>;
+L_000000000391fbb0 .functor BUF 1, L_000000000391e2c0, C4<0>, C4<0>, C4<0>;
+v0000000002a858c0_0 .net "A", 0 0, L_00000000039286d0; alias, 1 drivers
+L_000000000383a670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87d00_0 .net8 "VGND", 0 0, L_000000000383a670; 1 drivers, strength-aware
+L_0000000003839bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a85b40_0 .net8 "VNB", 0 0, L_0000000003839bf0; 1 drivers, strength-aware
+L_000000000383a750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87440_0 .net8 "VPB", 0 0, L_000000000383a750; 1 drivers, strength-aware
+L_000000000383ad00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87da0_0 .net8 "VPWR", 0 0, L_000000000383ad00; 1 drivers, strength-aware
+v0000000002a85960_0 .net "Y", 0 0, L_000000000391fbb0; alias, 1 drivers
+v0000000002a87a80_0 .net "not0_out_Y", 0 0, L_000000000391e2c0; 1 drivers
+S_00000000029c8ed0 .scope module, "_226_" "sky130_fd_sc_hd__inv_2" 3 365, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a86720_0 .net "A", 0 0, L_0000000003925db0; alias, 1 drivers
+L_000000000383a830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87580_0 .net8 "VGND", 0 0, L_000000000383a830; 1 drivers, strength-aware
+L_000000000383aec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a86f40_0 .net8 "VNB", 0 0, L_000000000383aec0; 1 drivers, strength-aware
+L_000000000383a210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a871c0_0 .net8 "VPB", 0 0, L_000000000383a210; 1 drivers, strength-aware
+L_000000000383a8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a87620_0 .net8 "VPWR", 0 0, L_000000000383a8a0; 1 drivers, strength-aware
+v0000000002a876c0_0 .net "Y", 0 0, L_000000000391f670; alias, 1 drivers
+S_00000000029c7250 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c8ed0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f980 .functor NOT 1, L_0000000003925db0, C4<0>, C4<0>, C4<0>;
+L_000000000391f670 .functor BUF 1, L_000000000391f980, C4<0>, C4<0>, C4<0>;
+v0000000002a86680_0 .net "A", 0 0, L_0000000003925db0; alias, 1 drivers
+L_0000000003839560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a87e40_0 .net8 "VGND", 0 0, L_0000000003839560; 1 drivers, strength-aware
+L_0000000003839790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a874e0_0 .net8 "VNB", 0 0, L_0000000003839790; 1 drivers, strength-aware
+L_0000000003839c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a878a0_0 .net8 "VPB", 0 0, L_0000000003839c60; 1 drivers, strength-aware
+L_0000000003839fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a86cc0_0 .net8 "VPWR", 0 0, L_0000000003839fe0; 1 drivers, strength-aware
+v0000000002a86ea0_0 .net "Y", 0 0, L_000000000391f670; alias, 1 drivers
+v0000000002a87b20_0 .net "not0_out_Y", 0 0, L_000000000391f980; 1 drivers
+S_00000000029c5d50 .scope module, "_227_" "sky130_fd_sc_hd__inv_2" 3 369, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a89ba0_0 .net "A", 0 0, L_0000000003926d70; alias, 1 drivers
+L_000000000383a980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a1e0_0 .net8 "VGND", 0 0, L_000000000383a980; 1 drivers, strength-aware
+L_000000000383abb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a280_0 .net8 "VNB", 0 0, L_000000000383abb0; 1 drivers, strength-aware
+L_000000000383ad70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a880c0_0 .net8 "VPB", 0 0, L_000000000383ad70; 1 drivers, strength-aware
+L_000000000383a280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a88520_0 .net8 "VPWR", 0 0, L_000000000383a280; 1 drivers, strength-aware
+v0000000002a88980_0 .net "Y", 0 0, L_000000000391ee20; alias, 1 drivers
+S_00000000029c73d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c5d50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391ef70 .functor NOT 1, L_0000000003926d70, C4<0>, C4<0>, C4<0>;
+L_000000000391ee20 .functor BUF 1, L_000000000391ef70, C4<0>, C4<0>, C4<0>;
+v0000000002a87940_0 .net "A", 0 0, L_0000000003926d70; alias, 1 drivers
+L_000000000383a0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a879e0_0 .net8 "VGND", 0 0, L_000000000383a0c0; 1 drivers, strength-aware
+L_0000000003839870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88020_0 .net8 "VNB", 0 0, L_0000000003839870; 1 drivers, strength-aware
+L_00000000038399c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89d80_0 .net8 "VPB", 0 0, L_00000000038399c0; 1 drivers, strength-aware
+L_00000000038395d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89740_0 .net8 "VPWR", 0 0, L_00000000038395d0; 1 drivers, strength-aware
+v0000000002a88480_0 .net "Y", 0 0, L_000000000391ee20; alias, 1 drivers
+v0000000002a89600_0 .net "not0_out_Y", 0 0, L_000000000391ef70; 1 drivers
+S_00000000029c46d0 .scope module, "_228_" "sky130_fd_sc_hd__inv_2" 3 373, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a88ca0_0 .net "A", 0 0, L_0000000003927780; alias, 1 drivers
+L_000000000383ade0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a894c0_0 .net8 "VGND", 0 0, L_000000000383ade0; 1 drivers, strength-aware
+L_0000000003839aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88fc0_0 .net8 "VNB", 0 0, L_0000000003839aa0; 1 drivers, strength-aware
+L_000000000383b630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a885c0_0 .net8 "VPB", 0 0, L_000000000383b630; 1 drivers, strength-aware
+L_000000000383b6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a3c0_0 .net8 "VPWR", 0 0, L_000000000383b6a0; 1 drivers, strength-aware
+v0000000002a88200_0 .net "Y", 0 0, L_000000000391f360; alias, 1 drivers
+S_00000000029c94d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c46d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f2f0 .functor NOT 1, L_0000000003927780, C4<0>, C4<0>, C4<0>;
+L_000000000391f360 .functor BUF 1, L_000000000391f2f0, C4<0>, C4<0>, C4<0>;
+v0000000002a891a0_0 .net "A", 0 0, L_0000000003927780; alias, 1 drivers
+L_000000000383b8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88700_0 .net8 "VGND", 0 0, L_000000000383b8d0; 1 drivers, strength-aware
+L_000000000383b4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88340_0 .net8 "VNB", 0 0, L_000000000383b4e0; 1 drivers, strength-aware
+L_000000000383b0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89240_0 .net8 "VPB", 0 0, L_000000000383b0f0; 1 drivers, strength-aware
+L_000000000383b5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a320_0 .net8 "VPWR", 0 0, L_000000000383b5c0; 1 drivers, strength-aware
+v0000000002a8a500_0 .net "Y", 0 0, L_000000000391f360; alias, 1 drivers
+v0000000002a89560_0 .net "not0_out_Y", 0 0, L_000000000391f2f0; 1 drivers
+S_00000000029c4fd0 .scope module, "_229_" "sky130_fd_sc_hd__or2_2" 3 377, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a899c0_0 .net "A", 0 0, L_0000000003927630; alias, 1 drivers
+v0000000002a88c00_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_000000000383b1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88840_0 .net8 "VGND", 0 0, L_000000000383b1d0; 1 drivers, strength-aware
+L_000000000383b080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a883e0_0 .net8 "VNB", 0 0, L_000000000383b080; 1 drivers, strength-aware
+L_000000000383b550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a888e0_0 .net8 "VPB", 0 0, L_000000000383b550; 1 drivers, strength-aware
+L_000000000383b710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a88ac0_0 .net8 "VPWR", 0 0, L_000000000383b710; 1 drivers, strength-aware
+v0000000002a88de0_0 .net "X", 0 0, L_000000000391e9c0; alias, 1 drivers
+S_00000000029c58d0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000029c4fd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391f9f0 .functor OR 1, L_000000000391d3e0, L_0000000003927630, C4<0>, C4<0>;
+L_000000000391e9c0 .functor BUF 1, L_000000000391f9f0, C4<0>, C4<0>, C4<0>;
+v0000000002a89c40_0 .net "A", 0 0, L_0000000003927630; alias, 1 drivers
+v0000000002a88a20_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_000000000383b240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a460_0 .net8 "VGND", 0 0, L_000000000383b240; 1 drivers, strength-aware
+L_000000000383b400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88d40_0 .net8 "VNB", 0 0, L_000000000383b400; 1 drivers, strength-aware
+L_000000000383bd30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a88b60_0 .net8 "VPB", 0 0, L_000000000383bd30; 1 drivers, strength-aware
+L_000000000383b470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a88660_0 .net8 "VPWR", 0 0, L_000000000383b470; 1 drivers, strength-aware
+v0000000002a896a0_0 .net "X", 0 0, L_000000000391e9c0; alias, 1 drivers
+v0000000002a887a0_0 .net "or0_out_X", 0 0, L_000000000391f9f0; 1 drivers
+S_00000000029c4850 .scope module, "_230_" "sky130_fd_sc_hd__buf_1" 3 382, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a89420_0 .net "A", 0 0, L_000000000391e9c0; alias, 1 drivers
+L_000000000383b2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a5a0_0 .net8 "VGND", 0 0, L_000000000383b2b0; 1 drivers, strength-aware
+L_000000000383b940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a89880_0 .net8 "VNB", 0 0, L_000000000383b940; 1 drivers, strength-aware
+L_000000000383b320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89920_0 .net8 "VPB", 0 0, L_000000000383b320; 1 drivers, strength-aware
+L_000000000383bda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89a60_0 .net8 "VPWR", 0 0, L_000000000383bda0; 1 drivers, strength-aware
+v0000000002a89b00_0 .net "X", 0 0, L_000000000391fc90; alias, 1 drivers
+S_00000000029c9ad0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000029c4850;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f050 .functor BUF 1, L_000000000391e9c0, C4<0>, C4<0>, C4<0>;
+L_000000000391fc90 .functor BUF 1, L_000000000391f050, C4<0>, C4<0>, C4<0>;
+v0000000002a88e80_0 .net "A", 0 0, L_000000000391e9c0; alias, 1 drivers
+L_000000000383b780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a897e0_0 .net8 "VGND", 0 0, L_000000000383b780; 1 drivers, strength-aware
+L_000000000383bbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a88f20_0 .net8 "VNB", 0 0, L_000000000383bbe0; 1 drivers, strength-aware
+L_000000000383bc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89060_0 .net8 "VPB", 0 0, L_000000000383bc50; 1 drivers, strength-aware
+L_000000000383ba90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a89100_0 .net8 "VPWR", 0 0, L_000000000383ba90; 1 drivers, strength-aware
+v0000000002a892e0_0 .net "X", 0 0, L_000000000391fc90; alias, 1 drivers
+v0000000002a89380_0 .net "buf0_out_X", 0 0, L_000000000391f050; 1 drivers
+S_00000000029c79d0 .scope module, "_231_" "sky130_fd_sc_hd__inv_2" 3 386, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a89e20_0 .net "A", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000383b7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a89ec0_0 .net8 "VGND", 0 0, L_000000000383b7f0; 1 drivers, strength-aware
+L_000000000383be10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a89f60_0 .net8 "VNB", 0 0, L_000000000383be10; 1 drivers, strength-aware
+L_000000000383bcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a000_0 .net8 "VPB", 0 0, L_000000000383bcc0; 1 drivers, strength-aware
+L_000000000383b860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a0a0_0 .net8 "VPWR", 0 0, L_000000000383b860; 1 drivers, strength-aware
+v0000000002a8a820_0 .net "Y", 0 0, L_000000000391fa60; alias, 1 drivers
+S_00000000029c40d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c79d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f520 .functor NOT 1, L_000000000391fc90, C4<0>, C4<0>, C4<0>;
+L_000000000391fa60 .functor BUF 1, L_000000000391f520, C4<0>, C4<0>, C4<0>;
+v0000000002a89ce0_0 .net "A", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000383b9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a640_0 .net8 "VGND", 0 0, L_000000000383b9b0; 1 drivers, strength-aware
+L_000000000383be80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a6e0_0 .net8 "VNB", 0 0, L_000000000383be80; 1 drivers, strength-aware
+L_000000000383b390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a88160_0 .net8 "VPB", 0 0, L_000000000383b390; 1 drivers, strength-aware
+L_000000000383bb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a780_0 .net8 "VPWR", 0 0, L_000000000383bb00; 1 drivers, strength-aware
+v0000000002a8a140_0 .net "Y", 0 0, L_000000000391fa60; alias, 1 drivers
+v0000000002a882a0_0 .net "not0_out_Y", 0 0, L_000000000391f520; 1 drivers
+S_00000000029c7550 .scope module, "_232_" "sky130_fd_sc_hd__inv_2" 3 390, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a8d020_0 .net "A", 0 0, L_000000000391d530; alias, 1 drivers
+L_000000000383bb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b4a0_0 .net8 "VGND", 0 0, L_000000000383bb70; 1 drivers, strength-aware
+L_000000000383ba20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c1c0_0 .net8 "VNB", 0 0, L_000000000383ba20; 1 drivers, strength-aware
+L_000000000383bef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b040_0 .net8 "VPB", 0 0, L_000000000383bef0; 1 drivers, strength-aware
+L_000000000383b160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8adc0_0 .net8 "VPWR", 0 0, L_000000000383b160; 1 drivers, strength-aware
+v0000000002a8c120_0 .net "Y", 0 0, L_000000000391e3a0; alias, 1 drivers
+S_00000000029c5bd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c7550;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e330 .functor NOT 1, L_000000000391d530, C4<0>, C4<0>, C4<0>;
+L_000000000391e3a0 .functor BUF 1, L_000000000391e330, C4<0>, C4<0>, C4<0>;
+v0000000002a8c260_0 .net "A", 0 0, L_000000000391d530; alias, 1 drivers
+L_000000000383bf60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b0e0_0 .net8 "VGND", 0 0, L_000000000383bf60; 1 drivers, strength-aware
+L_00000000038352e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c580_0 .net8 "VNB", 0 0, L_00000000038352e0; 1 drivers, strength-aware
+L_00000000038342b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c4e0_0 .net8 "VPB", 0 0, L_00000000038342b0; 1 drivers, strength-aware
+L_0000000003835200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b680_0 .net8 "VPWR", 0 0, L_0000000003835200; 1 drivers, strength-aware
+v0000000002a8abe0_0 .net "Y", 0 0, L_000000000391e3a0; alias, 1 drivers
+v0000000002a8afa0_0 .net "not0_out_Y", 0 0, L_000000000391e330; 1 drivers
+S_00000000029c49d0 .scope module, "_233_" "sky130_fd_sc_hd__inv_2" 3 394, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a8c9e0_0 .net "A", 0 0, L_00000000039276a0; alias, 1 drivers
+L_0000000003835430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ca80_0 .net8 "VGND", 0 0, L_0000000003835430; 1 drivers, strength-aware
+L_00000000038345c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8a8c0_0 .net8 "VNB", 0 0, L_00000000038345c0; 1 drivers, strength-aware
+L_0000000003834550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8cb20_0 .net8 "VPB", 0 0, L_0000000003834550; 1 drivers, strength-aware
+L_0000000003834470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b180_0 .net8 "VPWR", 0 0, L_0000000003834470; 1 drivers, strength-aware
+v0000000002a8b540_0 .net "Y", 0 0, L_000000000391e790; alias, 1 drivers
+S_00000000029c7850 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c49d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391ee90 .functor NOT 1, L_00000000039276a0, C4<0>, C4<0>, C4<0>;
+L_000000000391e790 .functor BUF 1, L_000000000391ee90, C4<0>, C4<0>, C4<0>;
+v0000000002a8bfe0_0 .net "A", 0 0, L_00000000039276a0; alias, 1 drivers
+L_0000000003835970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b900_0 .net8 "VGND", 0 0, L_0000000003835970; 1 drivers, strength-aware
+L_0000000003834da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c620_0 .net8 "VNB", 0 0, L_0000000003834da0; 1 drivers, strength-aware
+L_0000000003835040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b5e0_0 .net8 "VPB", 0 0, L_0000000003835040; 1 drivers, strength-aware
+L_0000000003835270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ac80_0 .net8 "VPWR", 0 0, L_0000000003835270; 1 drivers, strength-aware
+v0000000002a8aa00_0 .net "Y", 0 0, L_000000000391e790; alias, 1 drivers
+v0000000002a8c6c0_0 .net "not0_out_Y", 0 0, L_000000000391ee90; 1 drivers
+S_00000000029c7cd0 .scope module, "_234_" "sky130_fd_sc_hd__or2_2" 3 398, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a8cda0_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000002a8aaa0_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_00000000038348d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ae60_0 .net8 "VGND", 0 0, L_00000000038348d0; 1 drivers, strength-aware
+L_0000000003834b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b9a0_0 .net8 "VNB", 0 0, L_0000000003834b70; 1 drivers, strength-aware
+L_00000000038354a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ce40_0 .net8 "VPB", 0 0, L_00000000038354a0; 1 drivers, strength-aware
+L_0000000003834240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8cee0_0 .net8 "VPWR", 0 0, L_0000000003834240; 1 drivers, strength-aware
+v0000000002a8bd60_0 .net "X", 0 0, L_000000000391e6b0; alias, 1 drivers
+S_00000000029c4250 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000029c7cd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391f7c0 .functor OR 1, L_000000000391d3e0, L_0000000003926980, C4<0>, C4<0>;
+L_000000000391e6b0 .functor BUF 1, L_000000000391f7c0, C4<0>, C4<0>, C4<0>;
+v0000000002a8cbc0_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000002a8a960_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_0000000003835b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ad20_0 .net8 "VGND", 0 0, L_0000000003835b30; 1 drivers, strength-aware
+L_0000000003834080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b220_0 .net8 "VNB", 0 0, L_0000000003834080; 1 drivers, strength-aware
+L_00000000038340f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8be00_0 .net8 "VPB", 0 0, L_00000000038340f0; 1 drivers, strength-aware
+L_0000000003834ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ab40_0 .net8 "VPWR", 0 0, L_0000000003834ef0; 1 drivers, strength-aware
+v0000000002a8cc60_0 .net "X", 0 0, L_000000000391e6b0; alias, 1 drivers
+v0000000002a8cd00_0 .net "or0_out_X", 0 0, L_000000000391f7c0; 1 drivers
+S_00000000029c82d0 .scope module, "_235_" "sky130_fd_sc_hd__inv_2" 3 403, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a8b400_0 .net "A", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_0000000003834e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8bb80_0 .net8 "VGND", 0 0, L_0000000003834e10; 1 drivers, strength-aware
+L_0000000003835350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b7c0_0 .net8 "VNB", 0 0, L_0000000003835350; 1 drivers, strength-aware
+L_00000000038353c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c940_0 .net8 "VPB", 0 0, L_00000000038353c0; 1 drivers, strength-aware
+L_00000000038347f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b860_0 .net8 "VPWR", 0 0, L_00000000038347f0; 1 drivers, strength-aware
+v0000000002a8c760_0 .net "Y", 0 0, L_000000000391eaa0; alias, 1 drivers
+S_00000000029c5ed0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c82d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391efe0 .functor NOT 1, L_000000000391e6b0, C4<0>, C4<0>, C4<0>;
+L_000000000391eaa0 .functor BUF 1, L_000000000391efe0, C4<0>, C4<0>, C4<0>;
+v0000000002a8b2c0_0 .net "A", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_0000000003834630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8b360_0 .net8 "VGND", 0 0, L_0000000003834630; 1 drivers, strength-aware
+L_0000000003835190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c080_0 .net8 "VNB", 0 0, L_0000000003835190; 1 drivers, strength-aware
+L_0000000003835510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ba40_0 .net8 "VPB", 0 0, L_0000000003835510; 1 drivers, strength-aware
+L_0000000003835580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c300_0 .net8 "VPWR", 0 0, L_0000000003835580; 1 drivers, strength-aware
+v0000000002a8af00_0 .net "Y", 0 0, L_000000000391eaa0; alias, 1 drivers
+v0000000002a8b720_0 .net "not0_out_Y", 0 0, L_000000000391efe0; 1 drivers
+S_00000000029c4b50 .scope module, "_236_" "sky130_fd_sc_hd__nor2_2" 3 407, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a8c800_0 .net "A", 0 0, L_0000000003927940; alias, 1 drivers
+v0000000002a8c8a0_0 .net "B", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038359e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ed80_0 .net8 "VGND", 0 0, L_00000000038359e0; 1 drivers, strength-aware
+L_0000000003834320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e1a0_0 .net8 "VNB", 0 0, L_0000000003834320; 1 drivers, strength-aware
+L_0000000003834390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8da20_0 .net8 "VPB", 0 0, L_0000000003834390; 1 drivers, strength-aware
+L_0000000003834400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e060_0 .net8 "VPWR", 0 0, L_0000000003834400; 1 drivers, strength-aware
+v0000000002a8eba0_0 .net "Y", 0 0, L_000000000391fad0; alias, 1 drivers
+S_00000000029c8450 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000029c4b50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391e100 .functor NOR 1, L_0000000003927940, L_000000000391eaa0, C4<0>, C4<0>;
+L_000000000391fad0 .functor BUF 1, L_000000000391e100, C4<0>, C4<0>, C4<0>;
+v0000000002a8bae0_0 .net "A", 0 0, L_0000000003927940; alias, 1 drivers
+v0000000002a8bc20_0 .net "B", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003835740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8cf80_0 .net8 "VGND", 0 0, L_0000000003835740; 1 drivers, strength-aware
+L_0000000003835120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8bcc0_0 .net8 "VNB", 0 0, L_0000000003835120; 1 drivers, strength-aware
+L_0000000003835ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8c3a0_0 .net8 "VPB", 0 0, L_0000000003835ba0; 1 drivers, strength-aware
+L_0000000003834f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8bea0_0 .net8 "VPWR", 0 0, L_0000000003834f60; 1 drivers, strength-aware
+v0000000002a8c440_0 .net "Y", 0 0, L_000000000391fad0; alias, 1 drivers
+v0000000002a8bf40_0 .net "nor0_out_Y", 0 0, L_000000000391e100; 1 drivers
+S_00000000029c4cd0 .scope module, "_237_" "sky130_fd_sc_hd__inv_2" 3 412, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a8d0c0_0 .net "A", 0 0, L_0000000003927be0; alias, 1 drivers
+L_00000000038344e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d7a0_0 .net8 "VGND", 0 0, L_00000000038344e0; 1 drivers, strength-aware
+L_00000000038350b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ea60_0 .net8 "VNB", 0 0, L_00000000038350b0; 1 drivers, strength-aware
+L_0000000003834fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d480_0 .net8 "VPB", 0 0, L_0000000003834fd0; 1 drivers, strength-aware
+L_0000000003835a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d8e0_0 .net8 "VPWR", 0 0, L_0000000003835a50; 1 drivers, strength-aware
+v0000000002a8ee20_0 .net "Y", 0 0, L_000000000391fb40; alias, 1 drivers
+S_00000000029c9350 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c4cd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391ef00 .functor NOT 1, L_0000000003927be0, C4<0>, C4<0>, C4<0>;
+L_000000000391fb40 .functor BUF 1, L_000000000391ef00, C4<0>, C4<0>, C4<0>;
+v0000000002a8f780_0 .net "A", 0 0, L_0000000003927be0; alias, 1 drivers
+L_0000000003834e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f6e0_0 .net8 "VGND", 0 0, L_0000000003834e80; 1 drivers, strength-aware
+L_00000000038346a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e240_0 .net8 "VNB", 0 0, L_00000000038346a0; 1 drivers, strength-aware
+L_0000000003834860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8dac0_0 .net8 "VPB", 0 0, L_0000000003834860; 1 drivers, strength-aware
+L_0000000003834160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d3e0_0 .net8 "VPWR", 0 0, L_0000000003834160; 1 drivers, strength-aware
+v0000000002a8e380_0 .net "Y", 0 0, L_000000000391fb40; alias, 1 drivers
+v0000000002a8f140_0 .net "not0_out_Y", 0 0, L_000000000391ef00; 1 drivers
+S_00000000029c85d0 .scope module, "_238_" "sky130_fd_sc_hd__nor2_2" 3 416, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a8e100_0 .net "A", 0 0, L_00000000039286d0; alias, 1 drivers
+v0000000002a8dde0_0 .net "B", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003834be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e7e0_0 .net8 "VGND", 0 0, L_0000000003834be0; 1 drivers, strength-aware
+L_00000000038355f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e2e0_0 .net8 "VNB", 0 0, L_00000000038355f0; 1 drivers, strength-aware
+L_0000000003834a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f820_0 .net8 "VPB", 0 0, L_0000000003834a90; 1 drivers, strength-aware
+L_0000000003835660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e740_0 .net8 "VPWR", 0 0, L_0000000003835660; 1 drivers, strength-aware
+v0000000002a8d520_0 .net "Y", 0 0, L_000000000391ec60; alias, 1 drivers
+S_00000000029c6050 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000029c85d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391e170 .functor NOR 1, L_00000000039286d0, L_000000000391eaa0, C4<0>, C4<0>;
+L_000000000391ec60 .functor BUF 1, L_000000000391e170, C4<0>, C4<0>, C4<0>;
+v0000000002a8ec40_0 .net "A", 0 0, L_00000000039286d0; alias, 1 drivers
+v0000000002a8dca0_0 .net "B", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038356d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e9c0_0 .net8 "VGND", 0 0, L_00000000038356d0; 1 drivers, strength-aware
+L_00000000038357b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d840_0 .net8 "VNB", 0 0, L_00000000038357b0; 1 drivers, strength-aware
+L_0000000003834710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d5c0_0 .net8 "VPB", 0 0, L_0000000003834710; 1 drivers, strength-aware
+L_0000000003835820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e920_0 .net8 "VPWR", 0 0, L_0000000003835820; 1 drivers, strength-aware
+v0000000002a8dd40_0 .net "Y", 0 0, L_000000000391ec60; alias, 1 drivers
+v0000000002a8d660_0 .net "nor0_out_Y", 0 0, L_000000000391e170; 1 drivers
+S_00000000029c8750 .scope module, "_239_" "sky130_fd_sc_hd__or2_2" 3 421, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a8e560_0 .net "A", 0 0, L_000000000380ca60; 1 drivers
+v0000000002a8d700_0 .net "B", 0 0, L_000000000380c380; 1 drivers
+L_0000000003835890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e420_0 .net8 "VGND", 0 0, L_0000000003835890; 1 drivers, strength-aware
+L_0000000003834780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f500_0 .net8 "VNB", 0 0, L_0000000003834780; 1 drivers, strength-aware
+L_0000000003835900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f320_0 .net8 "VPB", 0 0, L_0000000003835900; 1 drivers, strength-aware
+L_0000000003835ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8eec0_0 .net8 "VPWR", 0 0, L_0000000003835ac0; 1 drivers, strength-aware
+v0000000002a8d980_0 .net "X", 0 0, L_000000000391fc20; alias, 1 drivers
+S_00000000029c9950 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000029c8750;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391f0c0 .functor OR 1, L_000000000380c380, L_000000000380ca60, C4<0>, C4<0>;
+L_000000000391fc20 .functor BUF 1, L_000000000391f0c0, C4<0>, C4<0>, C4<0>;
+v0000000002a8f1e0_0 .net "A", 0 0, L_000000000380ca60; alias, 1 drivers
+v0000000002a8f460_0 .net "B", 0 0, L_000000000380c380; alias, 1 drivers
+L_0000000003834940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d160_0 .net8 "VGND", 0 0, L_0000000003834940; 1 drivers, strength-aware
+L_0000000003835c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8eb00_0 .net8 "VNB", 0 0, L_0000000003835c10; 1 drivers, strength-aware
+L_00000000038349b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f280_0 .net8 "VPB", 0 0, L_00000000038349b0; 1 drivers, strength-aware
+L_00000000038341d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ece0_0 .net8 "VPWR", 0 0, L_00000000038341d0; 1 drivers, strength-aware
+v0000000002a8d200_0 .net "X", 0 0, L_000000000391fc20; alias, 1 drivers
+v0000000002a8df20_0 .net "or0_out_X", 0 0, L_000000000391f0c0; 1 drivers
+S_00000000029c88d0 .scope module, "_240_" "sky130_fd_sc_hd__inv_2" 3 426, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a8dc00_0 .net "A", 0 0, L_000000000391fc20; alias, 1 drivers
+L_0000000003834a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e6a0_0 .net8 "VGND", 0 0, L_0000000003834a20; 1 drivers, strength-aware
+L_0000000003834b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8dfc0_0 .net8 "VNB", 0 0, L_0000000003834b00; 1 drivers, strength-aware
+L_0000000003834c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e880_0 .net8 "VPB", 0 0, L_0000000003834c50; 1 drivers, strength-aware
+L_0000000003834cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f000_0 .net8 "VPWR", 0 0, L_0000000003834cc0; 1 drivers, strength-aware
+v0000000002a8f0a0_0 .net "Y", 0 0, L_000000000391f130; alias, 1 drivers
+S_00000000029c8a50 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c88d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f280 .functor NOT 1, L_000000000391fc20, C4<0>, C4<0>, C4<0>;
+L_000000000391f130 .functor BUF 1, L_000000000391f280, C4<0>, C4<0>, C4<0>;
+v0000000002a8e4c0_0 .net "A", 0 0, L_000000000391fc20; alias, 1 drivers
+L_0000000003834d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8e600_0 .net8 "VGND", 0 0, L_0000000003834d30; 1 drivers, strength-aware
+L_000000000383c870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8db60_0 .net8 "VNB", 0 0, L_000000000383c870; 1 drivers, strength-aware
+L_000000000383ca30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f5a0_0 .net8 "VPB", 0 0, L_000000000383ca30; 1 drivers, strength-aware
+L_000000000383c2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d2a0_0 .net8 "VPWR", 0 0, L_000000000383c2c0; 1 drivers, strength-aware
+v0000000002a8de80_0 .net "Y", 0 0, L_000000000391f130; alias, 1 drivers
+v0000000002a8ef60_0 .net "not0_out_Y", 0 0, L_000000000391f280; 1 drivers
+S_00000000029c8d50 .scope module, "_241_" "sky130_fd_sc_hd__nor2_2" 3 430, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000002a90e00_0 .net "A", 0 0, L_000000000380bde0; 1 drivers
+v0000000002a8fb40_0 .net "B", 0 0, L_000000000380c560; 1 drivers
+L_000000000383d2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a91080_0 .net8 "VGND", 0 0, L_000000000383d2f0; 1 drivers, strength-aware
+L_000000000383d6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a914e0_0 .net8 "VNB", 0 0, L_000000000383d6e0; 1 drivers, strength-aware
+L_000000000383db40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a916c0_0 .net8 "VPB", 0 0, L_000000000383db40; 1 drivers, strength-aware
+L_000000000383d280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91bc0_0 .net8 "VPWR", 0 0, L_000000000383d280; 1 drivers, strength-aware
+v0000000002a8f960_0 .net "Y", 0 0, L_000000000391eb80; alias, 1 drivers
+S_00000000029c9f50 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000029c8d50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000391e410 .functor NOR 1, L_000000000380bde0, L_000000000380c560, C4<0>, C4<0>;
+L_000000000391eb80 .functor BUF 1, L_000000000391e410, C4<0>, C4<0>, C4<0>;
+v0000000002a8f3c0_0 .net "A", 0 0, L_000000000380bde0; alias, 1 drivers
+v0000000002a8f640_0 .net "B", 0 0, L_000000000380c560; alias, 1 drivers
+L_000000000383cb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8d340_0 .net8 "VGND", 0 0, L_000000000383cb10; 1 drivers, strength-aware
+L_000000000383d130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8f8c0_0 .net8 "VNB", 0 0, L_000000000383d130; 1 drivers, strength-aware
+L_000000000383d360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a919e0_0 .net8 "VPB", 0 0, L_000000000383d360; 1 drivers, strength-aware
+L_000000000383cfe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91a80_0 .net8 "VPWR", 0 0, L_000000000383cfe0; 1 drivers, strength-aware
+v0000000002a8fa00_0 .net "Y", 0 0, L_000000000391eb80; alias, 1 drivers
+v0000000002a91b20_0 .net "nor0_out_Y", 0 0, L_000000000391e410; 1 drivers
+S_00000000029c9c50 .scope module, "_242_" "sky130_fd_sc_hd__inv_2" 3 435, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a909a0_0 .net "A", 0 0, L_000000000380c4c0; 1 drivers
+L_000000000383c790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a91c60_0 .net8 "VGND", 0 0, L_000000000383c790; 1 drivers, strength-aware
+L_000000000383d1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8fbe0_0 .net8 "VNB", 0 0, L_000000000383d1a0; 1 drivers, strength-aware
+L_000000000383d590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a90040_0 .net8 "VPB", 0 0, L_000000000383d590; 1 drivers, strength-aware
+L_000000000383c100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a90360_0 .net8 "VPWR", 0 0, L_000000000383c100; 1 drivers, strength-aware
+v0000000002a90b80_0 .net "Y", 0 0, L_000000000391e4f0; alias, 1 drivers
+S_00000000029cbd50 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029c9c50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e480 .functor NOT 1, L_000000000380c4c0, C4<0>, C4<0>, C4<0>;
+L_000000000391e4f0 .functor BUF 1, L_000000000391e480, C4<0>, C4<0>, C4<0>;
+v0000000002a91e40_0 .net "A", 0 0, L_000000000380c4c0; alias, 1 drivers
+L_000000000383c250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a91120_0 .net8 "VGND", 0 0, L_000000000383c250; 1 drivers, strength-aware
+L_000000000383dbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a91580_0 .net8 "VNB", 0 0, L_000000000383dbb0; 1 drivers, strength-aware
+L_000000000383d3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a90ea0_0 .net8 "VPB", 0 0, L_000000000383d3d0; 1 drivers, strength-aware
+L_000000000383d600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8fc80_0 .net8 "VPWR", 0 0, L_000000000383d600; 1 drivers, strength-aware
+v0000000002a907c0_0 .net "Y", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000002a90720_0 .net "not0_out_Y", 0 0, L_000000000391e480; 1 drivers
+S_00000000029ca550 .scope module, "_243_" "sky130_fd_sc_hd__inv_2" 3 439, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a900e0_0 .net "A", 0 0, L_000000000380c6a0; 1 drivers
+L_000000000383c410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90180_0 .net8 "VGND", 0 0, L_000000000383c410; 1 drivers, strength-aware
+L_000000000383d050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90ae0_0 .net8 "VNB", 0 0, L_000000000383d050; 1 drivers, strength-aware
+L_000000000383c8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91d00_0 .net8 "VPB", 0 0, L_000000000383c8e0; 1 drivers, strength-aware
+L_000000000383caa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a911c0_0 .net8 "VPWR", 0 0, L_000000000383caa0; 1 drivers, strength-aware
+v0000000002a91da0_0 .net "Y", 0 0, L_000000000391f3d0; alias, 1 drivers
+S_00000000029cbed0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029ca550;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e1e0 .functor NOT 1, L_000000000380c6a0, C4<0>, C4<0>, C4<0>;
+L_000000000391f3d0 .functor BUF 1, L_000000000391e1e0, C4<0>, C4<0>, C4<0>;
+v0000000002a91300_0 .net "A", 0 0, L_000000000380c6a0; alias, 1 drivers
+L_000000000383c330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90900_0 .net8 "VGND", 0 0, L_000000000383c330; 1 drivers, strength-aware
+L_000000000383d440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90860_0 .net8 "VNB", 0 0, L_000000000383d440; 1 drivers, strength-aware
+L_000000000383d750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8fe60_0 .net8 "VPB", 0 0, L_000000000383d750; 1 drivers, strength-aware
+L_000000000383dc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a92020_0 .net8 "VPWR", 0 0, L_000000000383dc20; 1 drivers, strength-aware
+v0000000002a90a40_0 .net "Y", 0 0, L_000000000391f3d0; alias, 1 drivers
+v0000000002a8faa0_0 .net "not0_out_Y", 0 0, L_000000000391e1e0; 1 drivers
+S_00000000029cb5d0 .scope module, "_244_" "sky130_fd_sc_hd__and3_2" 3 443, 4 10013 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+v0000000002a913a0_0 .net "A", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000002a902c0_0 .net "B", 0 0, L_000000000391f3d0; alias, 1 drivers
+v0000000002a91620_0 .net "C", 0 0, L_000000000391eb80; alias, 1 drivers
+L_000000000383d4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90f40_0 .net8 "VGND", 0 0, L_000000000383d4b0; 1 drivers, strength-aware
+L_000000000383cb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a91260_0 .net8 "VNB", 0 0, L_000000000383cb80; 1 drivers, strength-aware
+L_000000000383d210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91440_0 .net8 "VPB", 0 0, L_000000000383d210; 1 drivers, strength-aware
+L_000000000383c3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a8ff00_0 .net8 "VPWR", 0 0, L_000000000383c3a0; 1 drivers, strength-aware
+v0000000002a90400_0 .net "X", 0 0, L_000000000391e800; alias, 1 drivers
+S_00000000029cb2d0 .scope module, "base" "sky130_fd_sc_hd__and3" 4 10031, 4 10319 1, S_00000000029cb5d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000391ebf0 .functor AND 1, L_000000000391eb80, L_000000000391e4f0, L_000000000391f3d0, C4<1>;
+L_000000000391e800 .functor BUF 1, L_000000000391ebf0, C4<0>, C4<0>, C4<0>;
+v0000000002a91ee0_0 .net "A", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000002a90c20_0 .net "B", 0 0, L_000000000391f3d0; alias, 1 drivers
+v0000000002a90220_0 .net "C", 0 0, L_000000000391eb80; alias, 1 drivers
+L_000000000383d520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90cc0_0 .net8 "VGND", 0 0, L_000000000383d520; 1 drivers, strength-aware
+L_000000000383c720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90d60_0 .net8 "VNB", 0 0, L_000000000383c720; 1 drivers, strength-aware
+L_000000000383c560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91f80_0 .net8 "VPB", 0 0, L_000000000383c560; 1 drivers, strength-aware
+L_000000000383d670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91940_0 .net8 "VPWR", 0 0, L_000000000383d670; 1 drivers, strength-aware
+v0000000002a8fd20_0 .net "X", 0 0, L_000000000391e800; alias, 1 drivers
+v0000000002a90fe0_0 .net "and0_out_X", 0 0, L_000000000391ebf0; 1 drivers
+S_00000000029ca9d0 .scope module, "_245_" "sky130_fd_sc_hd__inv_2" 3 449, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a905e0_0 .net "A", 0 0, L_000000000391c340; alias, 1 drivers
+L_000000000383d8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a90680_0 .net8 "VGND", 0 0, L_000000000383d8a0; 1 drivers, strength-aware
+L_000000000383d7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a92340_0 .net8 "VNB", 0 0, L_000000000383d7c0; 1 drivers, strength-aware
+L_000000000383cbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a92160_0 .net8 "VPB", 0 0, L_000000000383cbf0; 1 drivers, strength-aware
+L_000000000383d0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a936a0_0 .net8 "VPWR", 0 0, L_000000000383d0c0; 1 drivers, strength-aware
+v0000000002a920c0_0 .net "Y", 0 0, L_000000000391e870; alias, 1 drivers
+S_00000000029cacd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029ca9d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f6e0 .functor NOT 1, L_000000000391c340, C4<0>, C4<0>, C4<0>;
+L_000000000391e870 .functor BUF 1, L_000000000391f6e0, C4<0>, C4<0>, C4<0>;
+v0000000002a91760_0 .net "A", 0 0, L_000000000391c340; alias, 1 drivers
+L_000000000383cdb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a904a0_0 .net8 "VGND", 0 0, L_000000000383cdb0; 1 drivers, strength-aware
+L_000000000383c480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a8fdc0_0 .net8 "VNB", 0 0, L_000000000383c480; 1 drivers, strength-aware
+L_000000000383c4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a91800_0 .net8 "VPB", 0 0, L_000000000383c4f0; 1 drivers, strength-aware
+L_000000000383d830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a918a0_0 .net8 "VPWR", 0 0, L_000000000383d830; 1 drivers, strength-aware
+v0000000002a8ffa0_0 .net "Y", 0 0, L_000000000391e870; alias, 1 drivers
+v0000000002a90540_0 .net "not0_out_Y", 0 0, L_000000000391f6e0; 1 drivers
+S_00000000029cba50 .scope module, "_246_" "sky130_fd_sc_hd__inv_2" 3 453, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000002a92de0_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+L_000000000383c950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a937e0_0 .net8 "VGND", 0 0, L_000000000383c950; 1 drivers, strength-aware
+L_000000000383c9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a923e0_0 .net8 "VNB", 0 0, L_000000000383c9c0; 1 drivers, strength-aware
+L_000000000383d910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a931a0_0 .net8 "VPB", 0 0, L_000000000383d910; 1 drivers, strength-aware
+L_000000000383d980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a93e20_0 .net8 "VPWR", 0 0, L_000000000383d980; 1 drivers, strength-aware
+v0000000002a92ac0_0 .net "Y", 0 0, L_000000000391eb10; alias, 1 drivers
+S_00000000029cbbd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029cba50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e250 .functor NOT 1, L_000000000391c570, C4<0>, C4<0>, C4<0>;
+L_000000000391eb10 .functor BUF 1, L_000000000391e250, C4<0>, C4<0>, C4<0>;
+v0000000002a92660_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+L_000000000383c090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a93100_0 .net8 "VGND", 0 0, L_000000000383c090; 1 drivers, strength-aware
+L_000000000383cc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a93d80_0 .net8 "VNB", 0 0, L_000000000383cc60; 1 drivers, strength-aware
+L_000000000383d9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a92d40_0 .net8 "VPB", 0 0, L_000000000383d9f0; 1 drivers, strength-aware
+L_000000000383cd40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a922a0_0 .net8 "VPWR", 0 0, L_000000000383cd40; 1 drivers, strength-aware
+v0000000002a93ba0_0 .net "Y", 0 0, L_000000000391eb10; alias, 1 drivers
+v0000000002a92700_0 .net "not0_out_Y", 0 0, L_000000000391e250; 1 drivers
+S_00000000029ca3d0 .scope module, "_247_" "sky130_fd_sc_hd__or4_2" 3 457, 4 87422 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+v0000000002a93ce0_0 .net "A", 0 0, L_000000000380cf60; 1 drivers
+v0000000002a93880_0 .net "B", 0 0, L_000000000380c740; 1 drivers
+v0000000002a93240_0 .net "C", 0 0, L_000000000391dd10; alias, 1 drivers
+v0000000002a93380_0 .net "D", 0 0, L_000000000391fc20; alias, 1 drivers
+L_000000000383da60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a92fc0_0 .net8 "VGND", 0 0, L_000000000383da60; 1 drivers, strength-aware
+L_000000000383dad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a928e0_0 .net8 "VNB", 0 0, L_000000000383dad0; 1 drivers, strength-aware
+L_000000000383c170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a92480_0 .net8 "VPB", 0 0, L_000000000383c170; 1 drivers, strength-aware
+L_000000000383c640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a934c0_0 .net8 "VPWR", 0 0, L_000000000383c640; 1 drivers, strength-aware
+v0000000002a92c00_0 .net "X", 0 0, L_000000000391e5d0; alias, 1 drivers
+S_00000000029ca6d0 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87442, 4 87301 1, S_00000000029ca3d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000391e560 .functor OR 1, L_000000000391fc20, L_000000000391dd10, L_000000000380c740, L_000000000380cf60;
+L_000000000391e5d0 .functor BUF 1, L_000000000391e560, C4<0>, C4<0>, C4<0>;
+v0000000002a92e80_0 .net "A", 0 0, L_000000000380cf60; alias, 1 drivers
+v0000000002a939c0_0 .net "B", 0 0, L_000000000380c740; alias, 1 drivers
+v0000000002a925c0_0 .net "C", 0 0, L_000000000391dd10; alias, 1 drivers
+v0000000002a93c40_0 .net "D", 0 0, L_000000000391fc20; alias, 1 drivers
+L_000000000383cf00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a92200_0 .net8 "VGND", 0 0, L_000000000383cf00; 1 drivers, strength-aware
+L_000000000383ccd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a93920_0 .net8 "VNB", 0 0, L_000000000383ccd0; 1 drivers, strength-aware
+L_000000000383c1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a93560_0 .net8 "VPB", 0 0, L_000000000383c1e0; 1 drivers, strength-aware
+L_000000000383cf70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a92ca0_0 .net8 "VPWR", 0 0, L_000000000383cf70; 1 drivers, strength-aware
+v0000000002a932e0_0 .net "X", 0 0, L_000000000391e5d0; alias, 1 drivers
+v0000000002a92520_0 .net "or0_out_X", 0 0, L_000000000391e560; 1 drivers
+S_00000000029ca850 .scope module, "_248_" "sky130_fd_sc_hd__or3b_2" 3 464, 4 36566 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+v0000000002a92b60_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000002a93060_0 .net "B", 0 0, L_000000000391e5d0; alias, 1 drivers
+v0000000002a93420_0 .net "C_N", 0 0, L_000000000391e800; alias, 1 drivers
+L_000000000383c5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a93a60_0 .net8 "VGND", 0 0, L_000000000383c5d0; 1 drivers, strength-aware
+L_000000000383ce20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b380_0 .net8 "VNB", 0 0, L_000000000383ce20; 1 drivers, strength-aware
+L_000000000383c6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a840_0 .net8 "VPB", 0 0, L_000000000383c6b0; 1 drivers, strength-aware
+L_000000000383c800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003459e40_0 .net8 "VPWR", 0 0, L_000000000383c800; 1 drivers, strength-aware
+v000000000345aac0_0 .net "X", 0 0, L_000000000391f440; alias, 1 drivers
+S_00000000029cb750 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 36584, 4 36878 1, S_00000000029ca850;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_000000000391edb0 .functor NOT 1, L_000000000391e800, C4<0>, C4<0>, C4<0>;
+L_000000000391f750 .functor OR 1, L_000000000391e5d0, L_000000000391c570, L_000000000391edb0, C4<0>;
+L_000000000391f440 .functor BUF 1, L_000000000391f750, C4<0>, C4<0>, C4<0>;
+v0000000002a927a0_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000002a92840_0 .net "B", 0 0, L_000000000391e5d0; alias, 1 drivers
+v0000000002a93b00_0 .net "C_N", 0 0, L_000000000391e800; alias, 1 drivers
+L_000000000383ce90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a92980_0 .net8 "VGND", 0 0, L_000000000383ce90; 1 drivers, strength-aware
+L_000000000383e6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000002a93740_0 .net8 "VNB", 0 0, L_000000000383e6a0; 1 drivers, strength-aware
+L_000000000383f660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a93ec0_0 .net8 "VPB", 0 0, L_000000000383f660; 1 drivers, strength-aware
+L_000000000383e860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000002a93600_0 .net8 "VPWR", 0 0, L_000000000383e860; 1 drivers, strength-aware
+v0000000002a93f60_0 .net "X", 0 0, L_000000000391f440; alias, 1 drivers
+v0000000002a92a20_0 .net "not0_out", 0 0, L_000000000391edb0; 1 drivers
+v0000000002a92f20_0 .net "or0_out_X", 0 0, L_000000000391f750; 1 drivers
+S_00000000029ca0d0 .scope module, "_249_" "sky130_fd_sc_hd__buf_1" 3 470, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v000000000345b240_0 .net "A", 0 0, L_000000000391f440; alias, 1 drivers
+L_000000000383e390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345a480_0 .net8 "VGND", 0 0, L_000000000383e390; 1 drivers, strength-aware
+L_000000000383e010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003459940_0 .net8 "VNB", 0 0, L_000000000383e010; 1 drivers, strength-aware
+L_000000000383f740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a520_0 .net8 "VPB", 0 0, L_000000000383f740; 1 drivers, strength-aware
+L_000000000383ec50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a3e0_0 .net8 "VPWR", 0 0, L_000000000383ec50; 1 drivers, strength-aware
+v000000000345b420_0 .net "X", 0 0, L_000000000391e640; alias, 1 drivers
+S_00000000029cb8d0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000029ca0d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f4b0 .functor BUF 1, L_000000000391f440, C4<0>, C4<0>, C4<0>;
+L_000000000391e640 .functor BUF 1, L_000000000391f4b0, C4<0>, C4<0>, C4<0>;
+v0000000003459580_0 .net "A", 0 0, L_000000000391f440; alias, 1 drivers
+L_000000000383f7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003459b20_0 .net8 "VGND", 0 0, L_000000000383f7b0; 1 drivers, strength-aware
+L_000000000383eb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b1a0_0 .net8 "VNB", 0 0, L_000000000383eb70; 1 drivers, strength-aware
+L_000000000383e8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034598a0_0 .net8 "VPB", 0 0, L_000000000383e8d0; 1 drivers, strength-aware
+L_000000000383ee10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003459ee0_0 .net8 "VPWR", 0 0, L_000000000383ee10; 1 drivers, strength-aware
+v000000000345b920_0 .net "X", 0 0, L_000000000391e640; alias, 1 drivers
+v000000000345a0c0_0 .net "buf0_out_X", 0 0, L_000000000391f4b0; 1 drivers
+S_00000000029ca250 .scope module, "_250_" "sky130_fd_sc_hd__inv_2" 3 474, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345a660_0 .net "A", 0 0, L_000000000391e640; alias, 1 drivers
+L_000000000383e4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003459c60_0 .net8 "VGND", 0 0, L_000000000383e4e0; 1 drivers, strength-aware
+L_000000000383e780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b060_0 .net8 "VNB", 0 0, L_000000000383e780; 1 drivers, strength-aware
+L_000000000383f0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a700_0 .net8 "VPB", 0 0, L_000000000383f0b0; 1 drivers, strength-aware
+L_000000000383de50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003459bc0_0 .net8 "VPWR", 0 0, L_000000000383de50; 1 drivers, strength-aware
+v000000000345b9c0_0 .net "Y", 0 0, L_000000000391e8e0; alias, 1 drivers
+S_00000000029cab50 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029ca250;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e720 .functor NOT 1, L_000000000391e640, C4<0>, C4<0>, C4<0>;
+L_000000000391e8e0 .functor BUF 1, L_000000000391e720, C4<0>, C4<0>, C4<0>;
+v000000000345a020_0 .net "A", 0 0, L_000000000391e640; alias, 1 drivers
+L_000000000383f820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003459800_0 .net8 "VGND", 0 0, L_000000000383f820; 1 drivers, strength-aware
+L_000000000383dc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345a2a0_0 .net8 "VNB", 0 0, L_000000000383dc90; 1 drivers, strength-aware
+L_000000000383dd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345bb00_0 .net8 "VPB", 0 0, L_000000000383dd00; 1 drivers, strength-aware
+L_000000000383eb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345bc40_0 .net8 "VPWR", 0 0, L_000000000383eb00; 1 drivers, strength-aware
+v0000000003459f80_0 .net "Y", 0 0, L_000000000391e8e0; alias, 1 drivers
+v000000000345afc0_0 .net "not0_out_Y", 0 0, L_000000000391e720; 1 drivers
+S_00000000029cae50 .scope module, "_251_" "sky130_fd_sc_hd__inv_2" 3 478, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345a8e0_0 .net "A", 0 0, L_000000000380c880; 1 drivers
+L_000000000383e9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034599e0_0 .net8 "VGND", 0 0, L_000000000383e9b0; 1 drivers, strength-aware
+L_000000000383ee80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b2e0_0 .net8 "VNB", 0 0, L_000000000383ee80; 1 drivers, strength-aware
+L_000000000383eef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034596c0_0 .net8 "VPB", 0 0, L_000000000383eef0; 1 drivers, strength-aware
+L_000000000383e400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345ad40_0 .net8 "VPWR", 0 0, L_000000000383e400; 1 drivers, strength-aware
+v000000000345a980_0 .net "Y", 0 0, L_000000000391ea30; alias, 1 drivers
+S_00000000029cafd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029cae50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391e950 .functor NOT 1, L_000000000380c880, C4<0>, C4<0>, C4<0>;
+L_000000000391ea30 .functor BUF 1, L_000000000391e950, C4<0>, C4<0>, C4<0>;
+v000000000345ade0_0 .net "A", 0 0, L_000000000380c880; alias, 1 drivers
+L_000000000383e160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b880_0 .net8 "VGND", 0 0, L_000000000383e160; 1 drivers, strength-aware
+L_000000000383eda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ac00_0 .net8 "VNB", 0 0, L_000000000383eda0; 1 drivers, strength-aware
+L_000000000383ef60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003459620_0 .net8 "VPB", 0 0, L_000000000383ef60; 1 drivers, strength-aware
+L_000000000383f120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a7a0_0 .net8 "VPWR", 0 0, L_000000000383f120; 1 drivers, strength-aware
+v000000000345b100_0 .net "Y", 0 0, L_000000000391ea30; alias, 1 drivers
+v000000000345a5c0_0 .net "not0_out_Y", 0 0, L_000000000391e950; 1 drivers
+S_00000000029cb150 .scope module, "_252_" "sky130_fd_sc_hd__inv_2" 3 482, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345aa20_0 .net "A", 0 0, L_000000000380ce20; 1 drivers
+L_000000000383f5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345a340_0 .net8 "VGND", 0 0, L_000000000383f5f0; 1 drivers, strength-aware
+L_000000000383dec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345a160_0 .net8 "VNB", 0 0, L_000000000383dec0; 1 drivers, strength-aware
+L_000000000383dfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345a200_0 .net8 "VPB", 0 0, L_000000000383dfa0; 1 drivers, strength-aware
+L_000000000383df30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345ba60_0 .net8 "VPWR", 0 0, L_000000000383df30; 1 drivers, strength-aware
+v000000000345ab60_0 .net "Y", 0 0, L_000000000391f590; alias, 1 drivers
+S_00000000029cb450 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000029cb150;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391ecd0 .functor NOT 1, L_000000000380ce20, C4<0>, C4<0>, C4<0>;
+L_000000000391f590 .functor BUF 1, L_000000000391ecd0, C4<0>, C4<0>, C4<0>;
+v000000000345b600_0 .net "A", 0 0, L_000000000380ce20; alias, 1 drivers
+L_000000000383f350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b6a0_0 .net8 "VGND", 0 0, L_000000000383f350; 1 drivers, strength-aware
+L_000000000383ed30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b4c0_0 .net8 "VNB", 0 0, L_000000000383ed30; 1 drivers, strength-aware
+L_000000000383dd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003459a80_0 .net8 "VPB", 0 0, L_000000000383dd70; 1 drivers, strength-aware
+L_000000000383ebe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345af20_0 .net8 "VPWR", 0 0, L_000000000383ebe0; 1 drivers, strength-aware
+v0000000003459d00_0 .net "Y", 0 0, L_000000000391f590; alias, 1 drivers
+v0000000003459da0_0 .net "not0_out_Y", 0 0, L_000000000391ecd0; 1 drivers
+S_00000000028d1bd0 .scope module, "_253_" "sky130_fd_sc_hd__inv_2" 3 486, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003459760_0 .net "A", 0 0, L_000000000380cb00; 1 drivers
+L_000000000383e080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345d2c0_0 .net8 "VGND", 0 0, L_000000000383e080; 1 drivers, strength-aware
+L_000000000383ecc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345d540_0 .net8 "VNB", 0 0, L_000000000383ecc0; 1 drivers, strength-aware
+L_000000000383efd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345cbe0_0 .net8 "VPB", 0 0, L_000000000383efd0; 1 drivers, strength-aware
+L_000000000383f580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c5a0_0 .net8 "VPWR", 0 0, L_000000000383f580; 1 drivers, strength-aware
+v000000000345d220_0 .net "Y", 0 0, L_000000000391f1a0; alias, 1 drivers
+S_00000000028d2dd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d1bd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391ed40 .functor NOT 1, L_000000000380cb00, C4<0>, C4<0>, C4<0>;
+L_000000000391f1a0 .functor BUF 1, L_000000000391ed40, C4<0>, C4<0>, C4<0>;
+v000000000345aca0_0 .net "A", 0 0, L_000000000380cb00; alias, 1 drivers
+L_000000000383ea90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ae80_0 .net8 "VGND", 0 0, L_000000000383ea90; 1 drivers, strength-aware
+L_000000000383e1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345b560_0 .net8 "VNB", 0 0, L_000000000383e1d0; 1 drivers, strength-aware
+L_000000000383e470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345b740_0 .net8 "VPB", 0 0, L_000000000383e470; 1 drivers, strength-aware
+L_000000000383dde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345b7e0_0 .net8 "VPWR", 0 0, L_000000000383dde0; 1 drivers, strength-aware
+v000000000345bba0_0 .net "Y", 0 0, L_000000000391f1a0; alias, 1 drivers
+v000000000345bce0_0 .net "not0_out_Y", 0 0, L_000000000391ed40; 1 drivers
+S_00000000028d21d0 .scope module, "_254_" "sky130_fd_sc_hd__inv_2" 3 490, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345d040_0 .net "A", 0 0, L_000000000380b340; 1 drivers
+L_000000000383e7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345c500_0 .net8 "VGND", 0 0, L_000000000383e7f0; 1 drivers, strength-aware
+L_000000000383f190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e260_0 .net8 "VNB", 0 0, L_000000000383f190; 1 drivers, strength-aware
+L_000000000383e710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345caa0_0 .net8 "VPB", 0 0, L_000000000383e710; 1 drivers, strength-aware
+L_000000000383f040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345cc80_0 .net8 "VPWR", 0 0, L_000000000383f040; 1 drivers, strength-aware
+v000000000345c780_0 .net "Y", 0 0, L_000000000391f600; alias, 1 drivers
+S_00000000028d45d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d21d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f210 .functor NOT 1, L_000000000380b340, C4<0>, C4<0>, C4<0>;
+L_000000000391f600 .functor BUF 1, L_000000000391f210, C4<0>, C4<0>, C4<0>;
+v000000000345bd80_0 .net "A", 0 0, L_000000000380b340; alias, 1 drivers
+L_000000000383f200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345c460_0 .net8 "VGND", 0 0, L_000000000383f200; 1 drivers, strength-aware
+L_000000000383f270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345d720_0 .net8 "VNB", 0 0, L_000000000383f270; 1 drivers, strength-aware
+L_000000000383e0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c140_0 .net8 "VPB", 0 0, L_000000000383e0f0; 1 drivers, strength-aware
+L_000000000383f2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c640_0 .net8 "VPWR", 0 0, L_000000000383f2e0; 1 drivers, strength-aware
+v000000000345da40_0 .net "Y", 0 0, L_000000000391f600; alias, 1 drivers
+v000000000345d360_0 .net "not0_out_Y", 0 0, L_000000000391f210; 1 drivers
+S_00000000028d2f50 .scope module, "_255_" "sky130_fd_sc_hd__inv_2" 3 494, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345bec0_0 .net "A", 0 0, L_000000000380bfc0; 1 drivers
+L_000000000383f3c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345db80_0 .net8 "VGND", 0 0, L_000000000383f3c0; 1 drivers, strength-aware
+L_000000000383e240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345df40_0 .net8 "VNB", 0 0, L_000000000383e240; 1 drivers, strength-aware
+L_000000000383f430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c820_0 .net8 "VPB", 0 0, L_000000000383f430; 1 drivers, strength-aware
+L_000000000383f4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345d400_0 .net8 "VPWR", 0 0, L_000000000383f4a0; 1 drivers, strength-aware
+v000000000345e440_0 .net "Y", 0 0, L_000000000391f8a0; alias, 1 drivers
+S_00000000028d1450 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d2f50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f830 .functor NOT 1, L_000000000380bfc0, C4<0>, C4<0>, C4<0>;
+L_000000000391f8a0 .functor BUF 1, L_000000000391f830, C4<0>, C4<0>, C4<0>;
+v000000000345cd20_0 .net "A", 0 0, L_000000000380bfc0; alias, 1 drivers
+L_000000000383e2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345cdc0_0 .net8 "VGND", 0 0, L_000000000383e2b0; 1 drivers, strength-aware
+L_000000000383f6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e300_0 .net8 "VNB", 0 0, L_000000000383f6d0; 1 drivers, strength-aware
+L_000000000383e320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345d5e0_0 .net8 "VPB", 0 0, L_000000000383e320; 1 drivers, strength-aware
+L_000000000383f510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c960_0 .net8 "VPWR", 0 0, L_000000000383f510; 1 drivers, strength-aware
+v000000000345d180_0 .net "Y", 0 0, L_000000000391f8a0; alias, 1 drivers
+v000000000345cb40_0 .net "not0_out_Y", 0 0, L_000000000391f830; 1 drivers
+S_00000000028d0550 .scope module, "_256_" "sky130_fd_sc_hd__inv_2" 3 498, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345c000_0 .net "A", 0 0, L_000000000380be80; 1 drivers
+L_000000000383e550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345c8c0_0 .net8 "VGND", 0 0, L_000000000383e550; 1 drivers, strength-aware
+L_000000000383e5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ca00_0 .net8 "VNB", 0 0, L_000000000383e5c0; 1 drivers, strength-aware
+L_000000000383e630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c3c0_0 .net8 "VPB", 0 0, L_000000000383e630; 1 drivers, strength-aware
+L_000000000383e940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345d4a0_0 .net8 "VPWR", 0 0, L_000000000383e940; 1 drivers, strength-aware
+v000000000345c6e0_0 .net "Y", 0 0, L_0000000003921580; alias, 1 drivers
+S_00000000028cfdd0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d0550;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391f910 .functor NOT 1, L_000000000380be80, C4<0>, C4<0>, C4<0>;
+L_0000000003921580 .functor BUF 1, L_000000000391f910, C4<0>, C4<0>, C4<0>;
+v000000000345ce60_0 .net "A", 0 0, L_000000000380be80; alias, 1 drivers
+L_000000000383ea20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345dc20_0 .net8 "VGND", 0 0, L_000000000383ea20; 1 drivers, strength-aware
+L_0000000003840bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e080_0 .net8 "VNB", 0 0, L_0000000003840bd0; 1 drivers, strength-aware
+L_0000000003840a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345d7c0_0 .net8 "VPB", 0 0, L_0000000003840a10; 1 drivers, strength-aware
+L_000000000383fc10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c320_0 .net8 "VPWR", 0 0, L_000000000383fc10; 1 drivers, strength-aware
+v000000000345d9a0_0 .net "Y", 0 0, L_0000000003921580; alias, 1 drivers
+v000000000345d860_0 .net "not0_out_Y", 0 0, L_000000000391f910; 1 drivers
+S_00000000028d33d0 .scope module, "_257_" "sky130_fd_sc_hd__inv_2" 3 502, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345d680_0 .net "A", 0 0, L_000000000380b3e0; 1 drivers
+L_0000000003840e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345dae0_0 .net8 "VGND", 0 0, L_0000000003840e00; 1 drivers, strength-aware
+L_000000000383fc80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345dcc0_0 .net8 "VNB", 0 0, L_000000000383fc80; 1 drivers, strength-aware
+L_0000000003840af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345dd60_0 .net8 "VPB", 0 0, L_0000000003840af0; 1 drivers, strength-aware
+L_0000000003840b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345de00_0 .net8 "VPWR", 0 0, L_0000000003840b60; 1 drivers, strength-aware
+v000000000345dea0_0 .net "Y", 0 0, L_0000000003920cc0; alias, 1 drivers
+S_00000000028d2050 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d33d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921430 .functor NOT 1, L_000000000380b3e0, C4<0>, C4<0>, C4<0>;
+L_0000000003920cc0 .functor BUF 1, L_0000000003921430, C4<0>, C4<0>, C4<0>;
+v000000000345e4e0_0 .net "A", 0 0, L_000000000380b3e0; alias, 1 drivers
+L_0000000003840e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345d900_0 .net8 "VGND", 0 0, L_0000000003840e70; 1 drivers, strength-aware
+L_0000000003840a80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345cf00_0 .net8 "VNB", 0 0, L_0000000003840a80; 1 drivers, strength-aware
+L_0000000003840c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345d0e0_0 .net8 "VPB", 0 0, L_0000000003840c40; 1 drivers, strength-aware
+L_0000000003840cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c1e0_0 .net8 "VPWR", 0 0, L_0000000003840cb0; 1 drivers, strength-aware
+v000000000345cfa0_0 .net "Y", 0 0, L_0000000003920cc0; alias, 1 drivers
+v000000000345e3a0_0 .net "not0_out_Y", 0 0, L_0000000003921430; 1 drivers
+S_00000000028d54d0 .scope module, "_258_" "sky130_fd_sc_hd__or2_2" 3 506, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000034606a0_0 .net "A", 0 0, L_000000000391eb10; alias, 1 drivers
+v000000000345f200_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_0000000003840690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345f7a0_0 .net8 "VGND", 0 0, L_0000000003840690; 1 drivers, strength-aware
+L_000000000383ff20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e8a0_0 .net8 "VNB", 0 0, L_000000000383ff20; 1 drivers, strength-aware
+L_000000000383fcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345ffc0_0 .net8 "VPB", 0 0, L_000000000383fcf0; 1 drivers, strength-aware
+L_000000000383fdd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345fc00_0 .net8 "VPWR", 0 0, L_000000000383fdd0; 1 drivers, strength-aware
+v00000000034607e0_0 .net "X", 0 0, L_00000000039210b0; alias, 1 drivers
+S_00000000028d09d0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d54d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_00000000039214a0 .functor OR 1, L_000000000391d3e0, L_000000000391eb10, C4<0>, C4<0>;
+L_00000000039210b0 .functor BUF 1, L_00000000039214a0, C4<0>, C4<0>, C4<0>;
+v000000000345c280_0 .net "A", 0 0, L_000000000391eb10; alias, 1 drivers
+v000000000345dfe0_0 .net "B", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_000000000383f9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e120_0 .net8 "VGND", 0 0, L_000000000383f9e0; 1 drivers, strength-aware
+L_00000000038403f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e1c0_0 .net8 "VNB", 0 0, L_00000000038403f0; 1 drivers, strength-aware
+L_0000000003840460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345be20_0 .net8 "VPB", 0 0, L_0000000003840460; 1 drivers, strength-aware
+L_0000000003840310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345c0a0_0 .net8 "VPWR", 0 0, L_0000000003840310; 1 drivers, strength-aware
+v000000000345bf60_0 .net "X", 0 0, L_00000000039210b0; alias, 1 drivers
+v000000000345f660_0 .net "or0_out_X", 0 0, L_00000000039214a0; 1 drivers
+S_00000000028d3cd0 .scope module, "_259_" "sky130_fd_sc_hd__inv_2" 3 511, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000345fca0_0 .net "A", 0 0, L_00000000039210b0; alias, 1 drivers
+L_0000000003840380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345fd40_0 .net8 "VGND", 0 0, L_0000000003840380; 1 drivers, strength-aware
+L_0000000003840850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003460ce0_0 .net8 "VNB", 0 0, L_0000000003840850; 1 drivers, strength-aware
+L_00000000038400e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345fde0_0 .net8 "VPB", 0 0, L_00000000038400e0; 1 drivers, strength-aware
+L_000000000383fa50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345e940_0 .net8 "VPWR", 0 0, L_000000000383fa50; 1 drivers, strength-aware
+v000000000345fac0_0 .net "Y", 0 0, L_0000000003920860; alias, 1 drivers
+S_00000000028d1750 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d3cd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003920710 .functor NOT 1, L_00000000039210b0, C4<0>, C4<0>, C4<0>;
+L_0000000003920860 .functor BUF 1, L_0000000003920710, C4<0>, C4<0>, C4<0>;
+v000000000345ef80_0 .net "A", 0 0, L_00000000039210b0; alias, 1 drivers
+L_0000000003840230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345fa20_0 .net8 "VGND", 0 0, L_0000000003840230; 1 drivers, strength-aware
+L_000000000383fb30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345f700_0 .net8 "VNB", 0 0, L_000000000383fb30; 1 drivers, strength-aware
+L_000000000383f900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345f160_0 .net8 "VPB", 0 0, L_000000000383f900; 1 drivers, strength-aware
+L_000000000383ff90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345eb20_0 .net8 "VPWR", 0 0, L_000000000383ff90; 1 drivers, strength-aware
+v000000000345f480_0 .net "Y", 0 0, L_0000000003920860; alias, 1 drivers
+v000000000345f5c0_0 .net "not0_out_Y", 0 0, L_0000000003920710; 1 drivers
+S_00000000028d3850 .scope module, "_260_" "sky130_fd_sc_hd__buf_1" 3 515, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003460920_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+L_0000000003840000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e580_0 .net8 "VGND", 0 0, L_0000000003840000; 1 drivers, strength-aware
+L_000000000383f970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ed00_0 .net8 "VNB", 0 0, L_000000000383f970; 1 drivers, strength-aware
+L_000000000383fe40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460240_0 .net8 "VPB", 0 0, L_000000000383fe40; 1 drivers, strength-aware
+L_0000000003840ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460060_0 .net8 "VPWR", 0 0, L_0000000003840ee0; 1 drivers, strength-aware
+v000000000345eee0_0 .net "X", 0 0, L_0000000003920e80; alias, 1 drivers
+S_00000000028d3250 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d3850;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003920390 .functor BUF 1, L_0000000003920860, C4<0>, C4<0>, C4<0>;
+L_0000000003920e80 .functor BUF 1, L_0000000003920390, C4<0>, C4<0>, C4<0>;
+v0000000003460380_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+L_000000000383feb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345f840_0 .net8 "VGND", 0 0, L_000000000383feb0; 1 drivers, strength-aware
+L_000000000383fac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ebc0_0 .net8 "VNB", 0 0, L_000000000383fac0; 1 drivers, strength-aware
+L_0000000003840700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345f8e0_0 .net8 "VPB", 0 0, L_0000000003840700; 1 drivers, strength-aware
+L_000000000383fba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345ec60_0 .net8 "VPWR", 0 0, L_000000000383fba0; 1 drivers, strength-aware
+v0000000003460880_0 .net "X", 0 0, L_0000000003920e80; alias, 1 drivers
+v00000000034601a0_0 .net "buf0_out_X", 0 0, L_0000000003920390; 1 drivers
+S_00000000028d12d0 .scope module, "_261_" "sky130_fd_sc_hd__or2_2" 3 519, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000345ea80_0 .net "A", 0 0, L_000000000391d290; alias, 1 drivers
+v000000000345e800_0 .net "B", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_0000000003840f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345e6c0_0 .net8 "VGND", 0 0, L_0000000003840f50; 1 drivers, strength-aware
+L_00000000038409a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003460600_0 .net8 "VNB", 0 0, L_00000000038409a0; 1 drivers, strength-aware
+L_00000000038413b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345eda0_0 .net8 "VPB", 0 0, L_00000000038413b0; 1 drivers, strength-aware
+L_0000000003840d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460560_0 .net8 "VPWR", 0 0, L_0000000003840d20; 1 drivers, strength-aware
+v00000000034609c0_0 .net "X", 0 0, L_00000000039200f0; alias, 1 drivers
+S_00000000028d27d0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d12d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003920080 .functor OR 1, L_000000000391e8e0, L_000000000391d290, C4<0>, C4<0>;
+L_00000000039200f0 .functor BUF 1, L_0000000003920080, C4<0>, C4<0>, C4<0>;
+v000000000345f2a0_0 .net "A", 0 0, L_000000000391d290; alias, 1 drivers
+v00000000034604c0_0 .net "B", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_0000000003840d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345f3e0_0 .net8 "VGND", 0 0, L_0000000003840d90; 1 drivers, strength-aware
+L_00000000038402a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003460420_0 .net8 "VNB", 0 0, L_00000000038402a0; 1 drivers, strength-aware
+L_0000000003840fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345f980_0 .net8 "VPB", 0 0, L_0000000003840fc0; 1 drivers, strength-aware
+L_0000000003841030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460740_0 .net8 "VPWR", 0 0, L_0000000003841030; 1 drivers, strength-aware
+v000000000345e620_0 .net "X", 0 0, L_00000000039200f0; alias, 1 drivers
+v000000000345f340_0 .net "or0_out_X", 0 0, L_0000000003920080; 1 drivers
+S_00000000028d2350 .scope module, "_262_" "sky130_fd_sc_hd__inv_2" 3 524, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003460ba0_0 .net "A", 0 0, L_00000000039200f0; alias, 1 drivers
+L_00000000038404d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345fe80_0 .net8 "VGND", 0 0, L_00000000038404d0; 1 drivers, strength-aware
+L_0000000003840070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034602e0_0 .net8 "VNB", 0 0, L_0000000003840070; 1 drivers, strength-aware
+L_00000000038410a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345fb60_0 .net8 "VPB", 0 0, L_00000000038410a0; 1 drivers, strength-aware
+L_000000000383fd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345f0c0_0 .net8 "VPWR", 0 0, L_000000000383fd60; 1 drivers, strength-aware
+v000000000345ff20_0 .net "Y", 0 0, L_0000000003920fd0; 1 drivers
+S_00000000028d06d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d2350;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000391fec0 .functor NOT 1, L_00000000039200f0, C4<0>, C4<0>, C4<0>;
+L_0000000003920fd0 .functor BUF 1, L_000000000391fec0, C4<0>, C4<0>, C4<0>;
+v000000000345f520_0 .net "A", 0 0, L_00000000039200f0; alias, 1 drivers
+L_0000000003840930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003460c40_0 .net8 "VGND", 0 0, L_0000000003840930; 1 drivers, strength-aware
+L_0000000003841110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000345ee40_0 .net8 "VNB", 0 0, L_0000000003841110; 1 drivers, strength-aware
+L_0000000003840150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460a60_0 .net8 "VPB", 0 0, L_0000000003840150; 1 drivers, strength-aware
+L_00000000038401c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000345f020_0 .net8 "VPWR", 0 0, L_00000000038401c0; 1 drivers, strength-aware
+v0000000003460100_0 .net "Y", 0 0, L_0000000003920fd0; alias, 1 drivers
+v0000000003460b00_0 .net "not0_out_Y", 0 0, L_000000000391fec0; 1 drivers
+S_00000000028d24d0 .scope module, "_263_" "sky130_fd_sc_hd__nor2_2" 3 528, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003460d80_0 .net "A", 0 0, L_000000000391fa60; alias, 1 drivers
+v00000000034624a0_0 .net "B", 0 0, L_00000000039200f0; alias, 1 drivers
+L_000000000383f890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034611e0_0 .net8 "VGND", 0 0, L_000000000383f890; 1 drivers, strength-aware
+L_0000000003840540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463120_0 .net8 "VNB", 0 0, L_0000000003840540; 1 drivers, strength-aware
+L_0000000003841180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003461140_0 .net8 "VPB", 0 0, L_0000000003841180; 1 drivers, strength-aware
+L_00000000038405b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034616e0_0 .net8 "VPWR", 0 0, L_00000000038405b0; 1 drivers, strength-aware
+v0000000003462a40_0 .net "Y", 0 0, L_0000000003921510; alias, 1 drivers
+S_00000000028d48d0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000028d24d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003920d30 .functor NOR 1, L_000000000391fa60, L_00000000039200f0, C4<0>, C4<0>;
+L_0000000003921510 .functor BUF 1, L_0000000003920d30, C4<0>, C4<0>, C4<0>;
+v000000000345e760_0 .net "A", 0 0, L_000000000391fa60; alias, 1 drivers
+v000000000345e9e0_0 .net "B", 0 0, L_00000000039200f0; alias, 1 drivers
+L_00000000038411f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034633a0_0 .net8 "VGND", 0 0, L_00000000038411f0; 1 drivers, strength-aware
+L_0000000003841260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003461f00_0 .net8 "VNB", 0 0, L_0000000003841260; 1 drivers, strength-aware
+L_0000000003840620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462220_0 .net8 "VPB", 0 0, L_0000000003840620; 1 drivers, strength-aware
+L_0000000003840770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034610a0_0 .net8 "VPWR", 0 0, L_0000000003840770; 1 drivers, strength-aware
+v0000000003461fa0_0 .net "Y", 0 0, L_0000000003921510; alias, 1 drivers
+v0000000003462f40_0 .net "nor0_out_Y", 0 0, L_0000000003920d30; 1 drivers
+S_00000000028d30d0 .scope module, "_264_" "sky130_fd_sc_hd__buf_1" 3 533, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003461280_0 .net "A", 0 0, L_00000000039253a0; alias, 1 drivers
+L_00000000038407e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034622c0_0 .net8 "VGND", 0 0, L_00000000038407e0; 1 drivers, strength-aware
+L_00000000038412d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463300_0 .net8 "VNB", 0 0, L_00000000038412d0; 1 drivers, strength-aware
+L_00000000038408c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034625e0_0 .net8 "VPB", 0 0, L_00000000038408c0; 1 drivers, strength-aware
+L_0000000003841340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462180_0 .net8 "VPWR", 0 0, L_0000000003841340; 1 drivers, strength-aware
+v0000000003461c80_0 .net "X", 0 0, L_0000000003920160; alias, 1 drivers
+S_00000000028d0850 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d30d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921200 .functor BUF 1, L_00000000039253a0, C4<0>, C4<0>, C4<0>;
+L_0000000003920160 .functor BUF 1, L_0000000003921200, C4<0>, C4<0>, C4<0>;
+v0000000003461320_0 .net "A", 0 0, L_00000000039253a0; alias, 1 drivers
+L_0000000003841420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463080_0 .net8 "VGND", 0 0, L_0000000003841420; 1 drivers, strength-aware
+L_0000000003842680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003460ec0_0 .net8 "VNB", 0 0, L_0000000003842680; 1 drivers, strength-aware
+L_0000000003842e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462ea0_0 .net8 "VPB", 0 0, L_0000000003842e60; 1 drivers, strength-aware
+L_00000000038421b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034613c0_0 .net8 "VPWR", 0 0, L_00000000038421b0; 1 drivers, strength-aware
+v0000000003461000_0 .net "X", 0 0, L_0000000003920160; alias, 1 drivers
+v0000000003461d20_0 .net "buf0_out_X", 0 0, L_0000000003921200; 1 drivers
+S_00000000028d42d0 .scope module, "_265_" "sky130_fd_sc_hd__nor2_2" 3 537, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003462360_0 .net "A", 0 0, L_0000000003920160; alias, 1 drivers
+v00000000034618c0_0 .net "B", 0 0, L_00000000039200f0; alias, 1 drivers
+L_00000000038426f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034627c0_0 .net8 "VGND", 0 0, L_00000000038426f0; 1 drivers, strength-aware
+L_0000000003841570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003461dc0_0 .net8 "VNB", 0 0, L_0000000003841570; 1 drivers, strength-aware
+L_00000000038416c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003461e60_0 .net8 "VPB", 0 0, L_00000000038416c0; 1 drivers, strength-aware
+L_0000000003841b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003461960_0 .net8 "VPWR", 0 0, L_0000000003841b90; 1 drivers, strength-aware
+v0000000003462860_0 .net "Y", 0 0, L_000000000391fd70; alias, 1 drivers
+S_00000000028d3550 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000028d42d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921740 .functor NOR 1, L_0000000003920160, L_00000000039200f0, C4<0>, C4<0>;
+L_000000000391fd70 .functor BUF 1, L_0000000003921740, C4<0>, C4<0>, C4<0>;
+v0000000003461460_0 .net "A", 0 0, L_0000000003920160; alias, 1 drivers
+v0000000003461500_0 .net "B", 0 0, L_00000000039200f0; alias, 1 drivers
+L_0000000003841b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034615a0_0 .net8 "VGND", 0 0, L_0000000003841b20; 1 drivers, strength-aware
+L_0000000003842840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003461640_0 .net8 "VNB", 0 0, L_0000000003842840; 1 drivers, strength-aware
+L_0000000003842ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003461820_0 .net8 "VPB", 0 0, L_0000000003842ae0; 1 drivers, strength-aware
+L_00000000038428b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462040_0 .net8 "VPWR", 0 0, L_00000000038428b0; 1 drivers, strength-aware
+v0000000003461780_0 .net "Y", 0 0, L_000000000391fd70; alias, 1 drivers
+v0000000003461aa0_0 .net "nor0_out_Y", 0 0, L_0000000003921740; 1 drivers
+S_00000000028cfc50 .scope module, "_266_" "sky130_fd_sc_hd__a21o_2" 3 542, 4 46093 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+v00000000034620e0_0 .net "A1", 0 0, L_0000000003920160; alias, 1 drivers
+v0000000003461b40_0 .net "A2", 0 0, L_00000000039200f0; alias, 1 drivers
+v00000000034629a0_0 .net "B1", 0 0, L_000000000391fd70; alias, 1 drivers
+L_0000000003841f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003462e00_0 .net8 "VGND", 0 0, L_0000000003841f10; 1 drivers, strength-aware
+L_0000000003841c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003461be0_0 .net8 "VNB", 0 0, L_0000000003841c00; 1 drivers, strength-aware
+L_0000000003842a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003460e20_0 .net8 "VPB", 0 0, L_0000000003842a00; 1 drivers, strength-aware
+L_0000000003841810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462540_0 .net8 "VPWR", 0 0, L_0000000003841810; 1 drivers, strength-aware
+v0000000003462680_0 .net "X", 0 0, L_0000000003920780; alias, 1 drivers
+S_00000000028d0b50 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46111, 4 46415 1, S_00000000028cfc50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000391ff30 .functor AND 1, L_0000000003920160, L_00000000039200f0, C4<1>, C4<1>;
+L_00000000039217b0 .functor OR 1, L_000000000391ff30, L_000000000391fd70, C4<0>, C4<0>;
+L_0000000003920780 .functor BUF 1, L_00000000039217b0, C4<0>, C4<0>, C4<0>;
+v0000000003461a00_0 .net "A1", 0 0, L_0000000003920160; alias, 1 drivers
+v0000000003462900_0 .net "A2", 0 0, L_00000000039200f0; alias, 1 drivers
+v00000000034631c0_0 .net "B1", 0 0, L_000000000391fd70; alias, 1 drivers
+L_0000000003842530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003462d60_0 .net8 "VGND", 0 0, L_0000000003842530; 1 drivers, strength-aware
+L_00000000038425a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463260_0 .net8 "VNB", 0 0, L_00000000038425a0; 1 drivers, strength-aware
+L_0000000003841650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462400_0 .net8 "VPB", 0 0, L_0000000003841650; 1 drivers, strength-aware
+L_0000000003841c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462ae0_0 .net8 "VPWR", 0 0, L_0000000003841c70; 1 drivers, strength-aware
+v0000000003463440_0 .net "X", 0 0, L_0000000003920780; alias, 1 drivers
+v00000000034634e0_0 .net "and0_out", 0 0, L_000000000391ff30; 1 drivers
+v0000000003460f60_0 .net "or0_out_X", 0 0, L_00000000039217b0; 1 drivers
+S_00000000028cff50 .scope module, "_267_" "sky130_fd_sc_hd__inv_2" 3 548, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v00000000034657e0_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+L_0000000003841490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463bc0_0 .net8 "VGND", 0 0, L_0000000003841490; 1 drivers, strength-aware
+L_0000000003841500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003465240_0 .net8 "VNB", 0 0, L_0000000003841500; 1 drivers, strength-aware
+L_0000000003842760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003465ce0_0 .net8 "VPB", 0 0, L_0000000003842760; 1 drivers, strength-aware
+L_0000000003841730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003464660_0 .net8 "VPWR", 0 0, L_0000000003841730; 1 drivers, strength-aware
+v0000000003464e80_0 .net "Y", 0 0, L_0000000003921270; alias, 1 drivers
+S_00000000028d4a50 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028cff50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003920400 .functor NOT 1, L_00000000039251e0, C4<0>, C4<0>, C4<0>;
+L_0000000003921270 .functor BUF 1, L_0000000003920400, C4<0>, C4<0>, C4<0>;
+v0000000003462720_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+L_0000000003842610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003462b80_0 .net8 "VGND", 0 0, L_0000000003842610; 1 drivers, strength-aware
+L_0000000003842920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003462c20_0 .net8 "VNB", 0 0, L_0000000003842920; 1 drivers, strength-aware
+L_00000000038419d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462cc0_0 .net8 "VPB", 0 0, L_00000000038419d0; 1 drivers, strength-aware
+L_0000000003841960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003462fe0_0 .net8 "VPWR", 0 0, L_0000000003841960; 1 drivers, strength-aware
+v0000000003465420_0 .net "Y", 0 0, L_0000000003921270; alias, 1 drivers
+v0000000003464520_0 .net "not0_out_Y", 0 0, L_0000000003920400; 1 drivers
+S_00000000028d03d0 .scope module, "_268_" "sky130_fd_sc_hd__or3_2" 3 552, 4 49901 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+v0000000003463620_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v00000000034656a0_0 .net "B", 0 0, L_00000000039253a0; alias, 1 drivers
+v0000000003464020_0 .net "C", 0 0, L_00000000039200f0; alias, 1 drivers
+L_0000000003841880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003464ac0_0 .net8 "VGND", 0 0, L_0000000003841880; 1 drivers, strength-aware
+L_0000000003842d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003465380_0 .net8 "VNB", 0 0, L_0000000003842d80; 1 drivers, strength-aware
+L_0000000003842220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003464200_0 .net8 "VPB", 0 0, L_0000000003842220; 1 drivers, strength-aware
+L_0000000003842450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003463b20_0 .net8 "VPWR", 0 0, L_0000000003842450; 1 drivers, strength-aware
+v0000000003464b60_0 .net "X", 0 0, L_000000000391fde0; alias, 1 drivers
+S_00000000028d5350 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_00000000028d03d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_0000000003920470 .functor OR 1, L_00000000039253a0, L_00000000039251e0, L_00000000039200f0, C4<0>;
+L_000000000391fde0 .functor BUF 1, L_0000000003920470, C4<0>, C4<0>, C4<0>;
+v0000000003464980_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v00000000034645c0_0 .net "B", 0 0, L_00000000039253a0; alias, 1 drivers
+v0000000003464160_0 .net "C", 0 0, L_00000000039200f0; alias, 1 drivers
+L_0000000003842d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003464ca0_0 .net8 "VGND", 0 0, L_0000000003842d10; 1 drivers, strength-aware
+L_00000000038427d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003464d40_0 .net8 "VNB", 0 0, L_00000000038427d0; 1 drivers, strength-aware
+L_0000000003842ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003463580_0 .net8 "VPB", 0 0, L_0000000003842ed0; 1 drivers, strength-aware
+L_0000000003842290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003464a20_0 .net8 "VPWR", 0 0, L_0000000003842290; 1 drivers, strength-aware
+v00000000034642a0_0 .net "X", 0 0, L_000000000391fde0; alias, 1 drivers
+v0000000003463940_0 .net "or0_out_X", 0 0, L_0000000003920470; 1 drivers
+S_00000000028d5050 .scope module, "_269_" "sky130_fd_sc_hd__o21ai_2" 3 558, 4 89631 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+v0000000003463c60_0 .net "A1", 0 0, L_0000000003921270; alias, 1 drivers
+v0000000003464fc0_0 .net "A2", 0 0, L_000000000391fd70; alias, 1 drivers
+v0000000003464480_0 .net "B1", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003842990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463800_0 .net8 "VGND", 0 0, L_0000000003842990; 1 drivers, strength-aware
+L_00000000038415e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003464700_0 .net8 "VNB", 0 0, L_00000000038415e0; 1 drivers, strength-aware
+L_00000000038417a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003463d00_0 .net8 "VPB", 0 0, L_00000000038417a0; 1 drivers, strength-aware
+L_0000000003841ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003465100_0 .net8 "VPWR", 0 0, L_0000000003841ce0; 1 drivers, strength-aware
+v0000000003463da0_0 .net "Y", 0 0, L_000000000391ffa0; alias, 1 drivers
+S_00000000028d1ed0 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_00000000028d5050;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_00000000039206a0 .functor OR 1, L_000000000391fd70, L_0000000003921270, C4<0>, C4<0>;
+L_0000000003920010 .functor NAND 1, L_000000000391fde0, L_00000000039206a0, C4<1>, C4<1>;
+L_000000000391ffa0 .functor BUF 1, L_0000000003920010, C4<0>, C4<0>, C4<0>;
+v0000000003464c00_0 .net "A1", 0 0, L_0000000003921270; alias, 1 drivers
+v00000000034639e0_0 .net "A2", 0 0, L_000000000391fd70; alias, 1 drivers
+v00000000034636c0_0 .net "B1", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003841d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034654c0_0 .net8 "VGND", 0 0, L_0000000003841d50; 1 drivers, strength-aware
+L_0000000003842a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003463760_0 .net8 "VNB", 0 0, L_0000000003842a70; 1 drivers, strength-aware
+L_0000000003842b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003464de0_0 .net8 "VPB", 0 0, L_0000000003842b50; 1 drivers, strength-aware
+L_0000000003842bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003464f20_0 .net8 "VPWR", 0 0, L_0000000003842bc0; 1 drivers, strength-aware
+v0000000003465060_0 .net "Y", 0 0, L_000000000391ffa0; alias, 1 drivers
+v0000000003465c40_0 .net "nand0_out_Y", 0 0, L_0000000003920010; 1 drivers
+v0000000003464340_0 .net "or0_out", 0 0, L_00000000039206a0; 1 drivers
+S_00000000028d4ed0 .scope module, "_270_" "sky130_fd_sc_hd__inv_2" 3 564, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003465740_0 .net "A", 0 0, L_0000000003920160; alias, 1 drivers
+L_0000000003842300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034638a0_0 .net8 "VGND", 0 0, L_0000000003842300; 1 drivers, strength-aware
+L_0000000003841dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003465880_0 .net8 "VNB", 0 0, L_0000000003841dc0; 1 drivers, strength-aware
+L_00000000038418f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034643e0_0 .net8 "VPB", 0 0, L_00000000038418f0; 1 drivers, strength-aware
+L_0000000003841a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003463a80_0 .net8 "VPWR", 0 0, L_0000000003841a40; 1 drivers, strength-aware
+v0000000003463ee0_0 .net "Y", 0 0, L_00000000039201d0; alias, 1 drivers
+S_00000000028d4d50 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d4ed0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921820 .functor NOT 1, L_0000000003920160, C4<0>, C4<0>, C4<0>;
+L_00000000039201d0 .functor BUF 1, L_0000000003921820, C4<0>, C4<0>, C4<0>;
+v00000000034640c0_0 .net "A", 0 0, L_0000000003920160; alias, 1 drivers
+L_0000000003841ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034651a0_0 .net8 "VGND", 0 0, L_0000000003841ab0; 1 drivers, strength-aware
+L_0000000003841ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034652e0_0 .net8 "VNB", 0 0, L_0000000003841ff0; 1 drivers, strength-aware
+L_0000000003842060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003463e40_0 .net8 "VPB", 0 0, L_0000000003842060; 1 drivers, strength-aware
+L_0000000003841f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034647a0_0 .net8 "VPWR", 0 0, L_0000000003841f80; 1 drivers, strength-aware
+v0000000003465560_0 .net "Y", 0 0, L_00000000039201d0; alias, 1 drivers
+v0000000003465600_0 .net "not0_out_Y", 0 0, L_0000000003921820; 1 drivers
+S_00000000028d51d0 .scope module, "_271_" "sky130_fd_sc_hd__o22a_2" 3 568, 4 50766 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+v00000000034677c0_0 .net "A1", 0 0, L_00000000039251e0; alias, 1 drivers
+v0000000003467400_0 .net "A2", 0 0, L_0000000003920160; alias, 1 drivers
+v0000000003467a40_0 .net "B1", 0 0, L_0000000003921270; alias, 1 drivers
+v0000000003468080_0 .net "B2", 0 0, L_00000000039201d0; alias, 1 drivers
+L_00000000038420d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003466e60_0 .net8 "VGND", 0 0, L_00000000038420d0; 1 drivers, strength-aware
+L_00000000038424c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467900_0 .net8 "VNB", 0 0, L_00000000038424c0; 1 drivers, strength-aware
+L_0000000003841e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003466d20_0 .net8 "VPB", 0 0, L_0000000003841e30; 1 drivers, strength-aware
+L_0000000003841ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034679a0_0 .net8 "VPWR", 0 0, L_0000000003841ea0; 1 drivers, strength-aware
+v0000000003468120_0 .net "X", 0 0, L_0000000003921190; alias, 1 drivers
+S_00000000028d4150 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_00000000028d51d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003920da0 .functor OR 1, L_0000000003920160, L_00000000039251e0, C4<0>, C4<0>;
+L_0000000003920a20 .functor OR 1, L_00000000039201d0, L_0000000003921270, C4<0>, C4<0>;
+L_0000000003920240 .functor AND 1, L_0000000003920da0, L_0000000003920a20, C4<1>, C4<1>;
+L_0000000003921190 .functor BUF 1, L_0000000003920240, C4<0>, C4<0>, C4<0>;
+v0000000003463f80_0 .net "A1", 0 0, L_00000000039251e0; alias, 1 drivers
+v0000000003464840_0 .net "A2", 0 0, L_0000000003920160; alias, 1 drivers
+v00000000034648e0_0 .net "B1", 0 0, L_0000000003921270; alias, 1 drivers
+v0000000003465920_0 .net "B2", 0 0, L_00000000039201d0; alias, 1 drivers
+L_0000000003842370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034659c0_0 .net8 "VGND", 0 0, L_0000000003842370; 1 drivers, strength-aware
+L_0000000003842c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003465a60_0 .net8 "VNB", 0 0, L_0000000003842c30; 1 drivers, strength-aware
+L_00000000038423e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003465b00_0 .net8 "VPB", 0 0, L_00000000038423e0; 1 drivers, strength-aware
+L_0000000003842140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003465ba0_0 .net8 "VPWR", 0 0, L_0000000003842140; 1 drivers, strength-aware
+v0000000003466500_0 .net "X", 0 0, L_0000000003921190; alias, 1 drivers
+v0000000003466640_0 .net "and0_out_X", 0 0, L_0000000003920240; 1 drivers
+v0000000003466280_0 .net "or0_out", 0 0, L_0000000003920da0; 1 drivers
+v0000000003467860_0 .net "or1_out", 0 0, L_0000000003920a20; 1 drivers
+S_00000000028d36d0 .scope module, "_272_" "sky130_fd_sc_hd__inv_2" 3 575, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003466dc0_0 .net "A", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003842ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034681c0_0 .net8 "VGND", 0 0, L_0000000003842ca0; 1 drivers, strength-aware
+L_0000000003842df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467ae0_0 .net8 "VNB", 0 0, L_0000000003842df0; 1 drivers, strength-aware
+L_0000000003842f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003467c20_0 .net8 "VPB", 0 0, L_0000000003842f40; 1 drivers, strength-aware
+L_0000000003842fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003466f00_0 .net8 "VPWR", 0 0, L_0000000003842fb0; 1 drivers, strength-aware
+v0000000003466fa0_0 .net "Y", 0 0, L_0000000003920320; alias, 1 drivers
+S_00000000028d5650 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d36d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039202b0 .functor NOT 1, L_000000000391fde0, C4<0>, C4<0>, C4<0>;
+L_0000000003920320 .functor BUF 1, L_00000000039202b0, C4<0>, C4<0>, C4<0>;
+v0000000003466780_0 .net "A", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003843020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467220_0 .net8 "VGND", 0 0, L_0000000003843020; 1 drivers, strength-aware
+L_00000000038438e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034660a0_0 .net8 "VNB", 0 0, L_00000000038438e0; 1 drivers, strength-aware
+L_0000000003843480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003467040_0 .net8 "VPB", 0 0, L_0000000003843480; 1 drivers, strength-aware
+L_0000000003843bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003467e00_0 .net8 "VPWR", 0 0, L_0000000003843bf0; 1 drivers, strength-aware
+v0000000003467ea0_0 .net "Y", 0 0, L_0000000003920320; alias, 1 drivers
+v0000000003465d80_0 .net "not0_out_Y", 0 0, L_00000000039202b0; 1 drivers
+S_00000000028d0cd0 .scope module, "_273_" "sky130_fd_sc_hd__a22o_2" 3 579, 4 92017 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+v00000000034663c0_0 .net "A1", 0 0, L_00000000039210b0; alias, 1 drivers
+v0000000003466000_0 .net "A2", 0 0, L_0000000003920320; alias, 1 drivers
+v0000000003465ec0_0 .net "B1", 0 0, L_0000000003920860; alias, 1 drivers
+v0000000003466460_0 .net "B2", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003843330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467fe0_0 .net8 "VGND", 0 0, L_0000000003843330; 1 drivers, strength-aware
+L_0000000003843720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003468440_0 .net8 "VNB", 0 0, L_0000000003843720; 1 drivers, strength-aware
+L_0000000003843f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468260_0 .net8 "VPB", 0 0, L_0000000003843f00; 1 drivers, strength-aware
+L_0000000003843790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468300_0 .net8 "VPWR", 0 0, L_0000000003843790; 1 drivers, strength-aware
+v0000000003467180_0 .net "X", 0 0, L_0000000003920ef0; alias, 1 drivers
+S_00000000028cf7d0 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92037, 4 91890 1, S_00000000028d0cd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_00000000039215f0 .functor AND 1, L_0000000003920860, L_000000000391fde0, C4<1>, C4<1>;
+L_0000000003920a90 .functor AND 1, L_00000000039210b0, L_0000000003920320, C4<1>, C4<1>;
+L_0000000003921120 .functor OR 1, L_0000000003920a90, L_00000000039215f0, C4<0>, C4<0>;
+L_0000000003920ef0 .functor BUF 1, L_0000000003921120, C4<0>, C4<0>, C4<0>;
+v0000000003466c80_0 .net "A1", 0 0, L_00000000039210b0; alias, 1 drivers
+v0000000003466820_0 .net "A2", 0 0, L_0000000003920320; alias, 1 drivers
+v00000000034672c0_0 .net "B1", 0 0, L_0000000003920860; alias, 1 drivers
+v00000000034670e0_0 .net "B2", 0 0, L_000000000391fde0; alias, 1 drivers
+L_00000000038433a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034675e0_0 .net8 "VGND", 0 0, L_00000000038433a0; 1 drivers, strength-aware
+L_0000000003843090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467cc0_0 .net8 "VNB", 0 0, L_0000000003843090; 1 drivers, strength-aware
+L_0000000003843c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034666e0_0 .net8 "VPB", 0 0, L_0000000003843c60; 1 drivers, strength-aware
+L_0000000003843100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003467680_0 .net8 "VPWR", 0 0, L_0000000003843100; 1 drivers, strength-aware
+v0000000003467d60_0 .net "X", 0 0, L_0000000003920ef0; alias, 1 drivers
+v0000000003466320_0 .net "and0_out", 0 0, L_00000000039215f0; 1 drivers
+v0000000003467f40_0 .net "and1_out", 0 0, L_0000000003920a90; 1 drivers
+v00000000034684e0_0 .net "or0_out_X", 0 0, L_0000000003921120; 1 drivers
+S_00000000028d39d0 .scope module, "_274_" "sky130_fd_sc_hd__or3_2" 3 586, 4 49901 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+v0000000003466a00_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v0000000003466140_0 .net "B", 0 0, L_0000000003920160; alias, 1 drivers
+v00000000034661e0_0 .net "C", 0 0, L_000000000380cba0; 1 drivers
+L_0000000003843cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003466aa0_0 .net8 "VGND", 0 0, L_0000000003843cd0; 1 drivers, strength-aware
+L_00000000038436b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467360_0 .net8 "VNB", 0 0, L_00000000038436b0; 1 drivers, strength-aware
+L_0000000003843e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003466b40_0 .net8 "VPB", 0 0, L_0000000003843e90; 1 drivers, strength-aware
+L_00000000038432c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034674a0_0 .net8 "VPWR", 0 0, L_00000000038432c0; 1 drivers, strength-aware
+v0000000003467720_0 .net "X", 0 0, L_00000000039204e0; alias, 1 drivers
+S_00000000028d1d50 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_00000000028d39d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_00000000039216d0 .functor OR 1, L_0000000003920160, L_00000000039251e0, L_000000000380cba0, C4<0>;
+L_00000000039204e0 .functor BUF 1, L_00000000039216d0, C4<0>, C4<0>, C4<0>;
+v00000000034665a0_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v00000000034668c0_0 .net "B", 0 0, L_0000000003920160; alias, 1 drivers
+v00000000034683a0_0 .net "C", 0 0, L_000000000380cba0; alias, 1 drivers
+L_0000000003843800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003466960_0 .net8 "VGND", 0 0, L_0000000003843800; 1 drivers, strength-aware
+L_0000000003843170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003467b80_0 .net8 "VNB", 0 0, L_0000000003843170; 1 drivers, strength-aware
+L_0000000003843560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003466be0_0 .net8 "VPB", 0 0, L_0000000003843560; 1 drivers, strength-aware
+L_00000000038431e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003465e20_0 .net8 "VPWR", 0 0, L_00000000038431e0; 1 drivers, strength-aware
+v0000000003465f60_0 .net "X", 0 0, L_00000000039204e0; alias, 1 drivers
+v0000000003467540_0 .net "or0_out_X", 0 0, L_00000000039216d0; 1 drivers
+S_00000000028cf950 .scope module, "_275_" "sky130_fd_sc_hd__nor2_2" 3 592, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000346a240_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+v0000000003469a20_0 .net "B", 0 0, L_00000000039204e0; alias, 1 drivers
+L_0000000003843d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034695c0_0 .net8 "VGND", 0 0, L_0000000003843d40; 1 drivers, strength-aware
+L_0000000003843b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034698e0_0 .net8 "VNB", 0 0, L_0000000003843b80; 1 drivers, strength-aware
+L_0000000003843870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468bc0_0 .net8 "VPB", 0 0, L_0000000003843870; 1 drivers, strength-aware
+L_0000000003843950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346a2e0_0 .net8 "VPWR", 0 0, L_0000000003843950; 1 drivers, strength-aware
+v000000000346a060_0 .net "Y", 0 0, L_0000000003920550; alias, 1 drivers
+S_00000000028d2950 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000028cf950;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_00000000039212e0 .functor NOR 1, L_0000000003920860, L_00000000039204e0, C4<0>, C4<0>;
+L_0000000003920550 .functor BUF 1, L_00000000039212e0, C4<0>, C4<0>, C4<0>;
+v0000000003469700_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+v0000000003469840_0 .net "B", 0 0, L_00000000039204e0; alias, 1 drivers
+L_00000000038434f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346a9c0_0 .net8 "VGND", 0 0, L_00000000038434f0; 1 drivers, strength-aware
+L_00000000038435d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469340_0 .net8 "VNB", 0 0, L_00000000038435d0; 1 drivers, strength-aware
+L_0000000003843aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346a380_0 .net8 "VPB", 0 0, L_0000000003843aa0; 1 drivers, strength-aware
+L_0000000003843db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034689e0_0 .net8 "VPWR", 0 0, L_0000000003843db0; 1 drivers, strength-aware
+v0000000003469f20_0 .net "Y", 0 0, L_0000000003920550; alias, 1 drivers
+v0000000003469fc0_0 .net "nor0_out_Y", 0 0, L_00000000039212e0; 1 drivers
+S_00000000028d3b50 .scope module, "_276_" "sky130_fd_sc_hd__a21oi_2" 3 597, 4 51903 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+v000000000346a4c0_0 .net "A1", 0 0, L_0000000003920ef0; alias, 1 drivers
+v0000000003468580_0 .net "A2", 0 0, L_00000000039204e0; alias, 1 drivers
+v000000000346a6a0_0 .net "B1", 0 0, L_0000000003920550; alias, 1 drivers
+L_0000000003843640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469020_0 .net8 "VGND", 0 0, L_0000000003843640; 1 drivers, strength-aware
+L_0000000003843250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469ac0_0 .net8 "VNB", 0 0, L_0000000003843250; 1 drivers, strength-aware
+L_00000000038439c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ac40_0 .net8 "VPB", 0 0, L_00000000038439c0; 1 drivers, strength-aware
+L_0000000003843a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003469b60_0 .net8 "VPWR", 0 0, L_0000000003843a30; 1 drivers, strength-aware
+v0000000003468e40_0 .net "Y", 0 0, L_0000000003920f60; alias, 1 drivers
+S_00000000028d2ad0 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51921, 4 51555 1, S_00000000028d3b50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_0000000003920940 .functor AND 1, L_0000000003920ef0, L_00000000039204e0, C4<1>, C4<1>;
+L_00000000039205c0 .functor NOR 1, L_0000000003920550, L_0000000003920940, C4<0>, C4<0>;
+L_0000000003920f60 .functor BUF 1, L_00000000039205c0, C4<0>, C4<0>, C4<0>;
+v000000000346aba0_0 .net "A1", 0 0, L_0000000003920ef0; alias, 1 drivers
+v0000000003468b20_0 .net "A2", 0 0, L_00000000039204e0; alias, 1 drivers
+v0000000003469480_0 .net "B1", 0 0, L_0000000003920550; alias, 1 drivers
+L_0000000003843410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469660_0 .net8 "VGND", 0 0, L_0000000003843410; 1 drivers, strength-aware
+L_0000000003843b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469160_0 .net8 "VNB", 0 0, L_0000000003843b10; 1 drivers, strength-aware
+L_0000000003843e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346a420_0 .net8 "VPB", 0 0, L_0000000003843e20; 1 drivers, strength-aware
+L_0000000003843f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034697a0_0 .net8 "VPWR", 0 0, L_0000000003843f70; 1 drivers, strength-aware
+v000000000346ace0_0 .net "Y", 0 0, L_0000000003920f60; alias, 1 drivers
+v0000000003469980_0 .net "and0_out", 0 0, L_0000000003920940; 1 drivers
+v00000000034688a0_0 .net "nor0_out_Y", 0 0, L_00000000039205c0; 1 drivers
+S_00000000028cfad0 .scope module, "_277_" "sky130_fd_sc_hd__or2_2" 3 603, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003469520_0 .net "A", 0 0, L_000000000391c730; alias, 1 drivers
+v00000000034692a0_0 .net "B", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003859730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034693e0_0 .net8 "VGND", 0 0, L_0000000003859730; 1 drivers, strength-aware
+L_0000000003858d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034690c0_0 .net8 "VNB", 0 0, L_0000000003858d90; 1 drivers, strength-aware
+L_0000000003858070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468f80_0 .net8 "VPB", 0 0, L_0000000003858070; 1 drivers, strength-aware
+L_0000000003857f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003469ca0_0 .net8 "VPWR", 0 0, L_0000000003857f20; 1 drivers, strength-aware
+v0000000003469d40_0 .net "X", 0 0, L_0000000003920b00; alias, 1 drivers
+S_00000000028d3e50 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028cfad0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921660 .functor OR 1, L_000000000391fde0, L_000000000391c730, C4<0>, C4<0>;
+L_0000000003920b00 .functor BUF 1, L_0000000003921660, C4<0>, C4<0>, C4<0>;
+v000000000346a880_0 .net "A", 0 0, L_000000000391c730; alias, 1 drivers
+v000000000346a100_0 .net "B", 0 0, L_000000000391fde0; alias, 1 drivers
+L_0000000003858ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469c00_0 .net8 "VGND", 0 0, L_0000000003858ee0; 1 drivers, strength-aware
+L_0000000003857f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346a1a0_0 .net8 "VNB", 0 0, L_0000000003857f90; 1 drivers, strength-aware
+L_0000000003859420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346aa60_0 .net8 "VPB", 0 0, L_0000000003859420; 1 drivers, strength-aware
+L_0000000003859180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468800_0 .net8 "VPWR", 0 0, L_0000000003859180; 1 drivers, strength-aware
+v000000000346ab00_0 .net "X", 0 0, L_0000000003920b00; alias, 1 drivers
+v0000000003469200_0 .net "or0_out_X", 0 0, L_0000000003921660; 1 drivers
+S_00000000028d0e50 .scope module, "_278_" "sky130_fd_sc_hd__o21ai_2" 3 608, 4 89631 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+v000000000346a920_0 .net "A1", 0 0, L_000000000391db50; alias, 1 drivers
+v0000000003468a80_0 .net "A2", 0 0, L_0000000003920320; alias, 1 drivers
+v0000000003468c60_0 .net "B1", 0 0, L_0000000003920b00; alias, 1 drivers
+L_00000000038580e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003468d00_0 .net8 "VGND", 0 0, L_00000000038580e0; 1 drivers, strength-aware
+L_00000000038596c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003468da0_0 .net8 "VNB", 0 0, L_00000000038596c0; 1 drivers, strength-aware
+L_0000000003857e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003468ee0_0 .net8 "VPB", 0 0, L_0000000003857e40; 1 drivers, strength-aware
+L_0000000003859490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346bc80_0 .net8 "VPWR", 0 0, L_0000000003859490; 1 drivers, strength-aware
+v000000000346aec0_0 .net "Y", 0 0, L_0000000003920630; alias, 1 drivers
+S_00000000028d4450 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89649, 4 89511 1, S_00000000028d0e50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_0000000003921890 .functor OR 1, L_0000000003920320, L_000000000391db50, C4<0>, C4<0>;
+L_000000000391fe50 .functor NAND 1, L_0000000003920b00, L_0000000003921890, C4<1>, C4<1>;
+L_0000000003920630 .functor BUF 1, L_000000000391fe50, C4<0>, C4<0>, C4<0>;
+v0000000003468620_0 .net "A1", 0 0, L_000000000391db50; alias, 1 drivers
+v0000000003469de0_0 .net "A2", 0 0, L_0000000003920320; alias, 1 drivers
+v00000000034686c0_0 .net "B1", 0 0, L_0000000003920b00; alias, 1 drivers
+L_0000000003858af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003469e80_0 .net8 "VGND", 0 0, L_0000000003858af0; 1 drivers, strength-aware
+L_0000000003858e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003468940_0 .net8 "VNB", 0 0, L_0000000003858e00; 1 drivers, strength-aware
+L_00000000038582a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346a560_0 .net8 "VPB", 0 0, L_00000000038582a0; 1 drivers, strength-aware
+L_00000000038584d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346a600_0 .net8 "VPWR", 0 0, L_00000000038584d0; 1 drivers, strength-aware
+v000000000346a740_0 .net "Y", 0 0, L_0000000003920630; alias, 1 drivers
+v0000000003468760_0 .net "nand0_out_Y", 0 0, L_000000000391fe50; 1 drivers
+v000000000346a7e0_0 .net "or0_out", 0 0, L_0000000003921890; 1 drivers
+S_00000000028d2c50 .scope module, "_279_" "sky130_fd_sc_hd__inv_2" 3 614, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000346bbe0_0 .net "A", 0 0, L_0000000003920630; alias, 1 drivers
+L_0000000003858700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346c540_0 .net8 "VGND", 0 0, L_0000000003858700; 1 drivers, strength-aware
+L_0000000003858fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346be60_0 .net8 "VNB", 0 0, L_0000000003858fc0; 1 drivers, strength-aware
+L_0000000003858e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346cf40_0 .net8 "VPB", 0 0, L_0000000003858e70; 1 drivers, strength-aware
+L_0000000003858000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346d4e0_0 .net8 "VPWR", 0 0, L_0000000003858000; 1 drivers, strength-aware
+v000000000346c860_0 .net "Y", 0 0, L_000000000391fd00; alias, 1 drivers
+S_00000000028d2650 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d2c50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039207f0 .functor NOT 1, L_0000000003920630, C4<0>, C4<0>, C4<0>;
+L_000000000391fd00 .functor BUF 1, L_00000000039207f0, C4<0>, C4<0>, C4<0>;
+v000000000346d1c0_0 .net "A", 0 0, L_0000000003920630; alias, 1 drivers
+L_00000000038591f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b000_0 .net8 "VGND", 0 0, L_00000000038591f0; 1 drivers, strength-aware
+L_0000000003858150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b8c0_0 .net8 "VNB", 0 0, L_0000000003858150; 1 drivers, strength-aware
+L_0000000003858f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346b820_0 .net8 "VPB", 0 0, L_0000000003858f50; 1 drivers, strength-aware
+L_0000000003859030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c9a0_0 .net8 "VPWR", 0 0, L_0000000003859030; 1 drivers, strength-aware
+v000000000346c360_0 .net "Y", 0 0, L_000000000391fd00; alias, 1 drivers
+v000000000346b140_0 .net "not0_out_Y", 0 0, L_00000000039207f0; 1 drivers
+S_00000000028d0fd0 .scope module, "_280_" "sky130_fd_sc_hd__or3_2" 3 618, 4 49901 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+v000000000346b5a0_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v000000000346ccc0_0 .net "B", 0 0, L_00000000039253a0; alias, 1 drivers
+v000000000346b6e0_0 .net "C", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003859260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346bfa0_0 .net8 "VGND", 0 0, L_0000000003859260; 1 drivers, strength-aware
+L_00000000038590a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b960_0 .net8 "VNB", 0 0, L_00000000038590a0; 1 drivers, strength-aware
+L_0000000003858850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c5e0_0 .net8 "VPB", 0 0, L_0000000003858850; 1 drivers, strength-aware
+L_0000000003859110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c040_0 .net8 "VPWR", 0 0, L_0000000003859110; 1 drivers, strength-aware
+v000000000346c900_0 .net "X", 0 0, L_00000000039209b0; alias, 1 drivers
+S_00000000028d00d0 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49919, 4 49673 1, S_00000000028d0fd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_00000000039213c0 .functor OR 1, L_00000000039253a0, L_00000000039251e0, L_000000000391c730, C4<0>;
+L_00000000039209b0 .functor BUF 1, L_00000000039213c0, C4<0>, C4<0>, C4<0>;
+v000000000346b320_0 .net "A", 0 0, L_00000000039251e0; alias, 1 drivers
+v000000000346cc20_0 .net "B", 0 0, L_00000000039253a0; alias, 1 drivers
+v000000000346c7c0_0 .net "C", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003858540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b1e0_0 .net8 "VGND", 0 0, L_0000000003858540; 1 drivers, strength-aware
+L_0000000003858770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b3c0_0 .net8 "VNB", 0 0, L_0000000003858770; 1 drivers, strength-aware
+L_00000000038592d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346b460_0 .net8 "VPB", 0 0, L_00000000038592d0; 1 drivers, strength-aware
+L_0000000003857eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346b500_0 .net8 "VPWR", 0 0, L_0000000003857eb0; 1 drivers, strength-aware
+v000000000346ad80_0 .net "X", 0 0, L_00000000039209b0; alias, 1 drivers
+v000000000346bf00_0 .net "or0_out_X", 0 0, L_00000000039213c0; 1 drivers
+S_00000000028d3fd0 .scope module, "_281_" "sky130_fd_sc_hd__buf_1" 3 624, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v000000000346c220_0 .net "A", 0 0, L_00000000039209b0; alias, 1 drivers
+L_00000000038597a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346b640_0 .net8 "VGND", 0 0, L_00000000038597a0; 1 drivers, strength-aware
+L_0000000003857c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346c0e0_0 .net8 "VNB", 0 0, L_0000000003857c80; 1 drivers, strength-aware
+L_0000000003857cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ce00_0 .net8 "VPB", 0 0, L_0000000003857cf0; 1 drivers, strength-aware
+L_0000000003858b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c720_0 .net8 "VPWR", 0 0, L_0000000003858b60; 1 drivers, strength-aware
+v000000000346af60_0 .net "X", 0 0, L_0000000003920b70; alias, 1 drivers
+S_00000000028d0250 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d3fd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039208d0 .functor BUF 1, L_00000000039209b0, C4<0>, C4<0>, C4<0>;
+L_0000000003920b70 .functor BUF 1, L_00000000039208d0, C4<0>, C4<0>, C4<0>;
+v000000000346d120_0 .net "A", 0 0, L_00000000039209b0; alias, 1 drivers
+L_00000000038589a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346ae20_0 .net8 "VGND", 0 0, L_00000000038589a0; 1 drivers, strength-aware
+L_0000000003859340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346ca40_0 .net8 "VNB", 0 0, L_0000000003859340; 1 drivers, strength-aware
+L_0000000003859650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c400_0 .net8 "VPB", 0 0, L_0000000003859650; 1 drivers, strength-aware
+L_00000000038593b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c680_0 .net8 "VPWR", 0 0, L_00000000038593b0; 1 drivers, strength-aware
+v000000000346b0a0_0 .net "X", 0 0, L_0000000003920b70; alias, 1 drivers
+v000000000346d3a0_0 .net "buf0_out_X", 0 0, L_00000000039208d0; 1 drivers
+S_00000000028d4750 .scope module, "_282_" "sky130_fd_sc_hd__o22a_2" 3 628, 4 50766 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+v000000000346d080_0 .net "A1", 0 0, L_0000000003920550; alias, 1 drivers
+v000000000346d260_0 .net "A2", 0 0, L_000000000391fd00; alias, 1 drivers
+v000000000346d300_0 .net "B1", 0 0, L_000000000380cc40; 1 drivers
+v000000000346bb40_0 .net "B2", 0 0, L_0000000003920b70; alias, 1 drivers
+L_00000000038588c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346bd20_0 .net8 "VGND", 0 0, L_00000000038588c0; 1 drivers, strength-aware
+L_00000000038581c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346bdc0_0 .net8 "VNB", 0 0, L_00000000038581c0; 1 drivers, strength-aware
+L_0000000003859810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c180_0 .net8 "VPB", 0 0, L_0000000003859810; 1 drivers, strength-aware
+L_0000000003858460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346d940_0 .net8 "VPWR", 0 0, L_0000000003858460; 1 drivers, strength-aware
+v000000000346dda0_0 .net "X", 0 0, L_0000000003921040; alias, 1 drivers
+S_00000000028d1150 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50786, 4 51223 1, S_00000000028d4750;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003920be0 .functor OR 1, L_000000000391fd00, L_0000000003920550, C4<0>, C4<0>;
+L_0000000003920c50 .functor OR 1, L_0000000003920b70, L_000000000380cc40, C4<0>, C4<0>;
+L_0000000003920e10 .functor AND 1, L_0000000003920be0, L_0000000003920c50, C4<1>, C4<1>;
+L_0000000003921040 .functor BUF 1, L_0000000003920e10, C4<0>, C4<0>, C4<0>;
+v000000000346cae0_0 .net "A1", 0 0, L_0000000003920550; alias, 1 drivers
+v000000000346cb80_0 .net "A2", 0 0, L_000000000391fd00; alias, 1 drivers
+v000000000346cfe0_0 .net "B1", 0 0, L_000000000380cc40; alias, 1 drivers
+v000000000346b780_0 .net "B2", 0 0, L_0000000003920b70; alias, 1 drivers
+L_0000000003859500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346ba00_0 .net8 "VGND", 0 0, L_0000000003859500; 1 drivers, strength-aware
+L_0000000003858bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346cd60_0 .net8 "VNB", 0 0, L_0000000003858bd0; 1 drivers, strength-aware
+L_0000000003859570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346c4a0_0 .net8 "VPB", 0 0, L_0000000003859570; 1 drivers, strength-aware
+L_0000000003858c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346cea0_0 .net8 "VPWR", 0 0, L_0000000003858c40; 1 drivers, strength-aware
+v000000000346d440_0 .net "X", 0 0, L_0000000003921040; alias, 1 drivers
+v000000000346b280_0 .net "and0_out_X", 0 0, L_0000000003920e10; 1 drivers
+v000000000346baa0_0 .net "or0_out", 0 0, L_0000000003920be0; 1 drivers
+v000000000346c2c0_0 .net "or1_out", 0 0, L_0000000003920c50; 1 drivers
+S_00000000028d4bd0 .scope module, "_283_" "sky130_fd_sc_hd__inv_2" 3 635, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000346f420_0 .net "A", 0 0, L_0000000003920b00; alias, 1 drivers
+L_0000000003858380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346e5c0_0 .net8 "VGND", 0 0, L_0000000003858380; 1 drivers, strength-aware
+L_0000000003858d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346fa60_0 .net8 "VNB", 0 0, L_0000000003858d20; 1 drivers, strength-aware
+L_00000000038595e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ed40_0 .net8 "VPB", 0 0, L_00000000038595e0; 1 drivers, strength-aware
+L_0000000003857d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346e160_0 .net8 "VPWR", 0 0, L_0000000003857d60; 1 drivers, strength-aware
+v000000000346e980_0 .net "Y", 0 0, L_00000000039229a0; alias, 1 drivers
+S_00000000028d15d0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d4bd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921350 .functor NOT 1, L_0000000003920b00, C4<0>, C4<0>, C4<0>;
+L_00000000039229a0 .functor BUF 1, L_0000000003921350, C4<0>, C4<0>, C4<0>;
+v000000000346fce0_0 .net "A", 0 0, L_0000000003920b00; alias, 1 drivers
+L_0000000003858230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346e480_0 .net8 "VGND", 0 0, L_0000000003858230; 1 drivers, strength-aware
+L_0000000003857dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346df80_0 .net8 "VNB", 0 0, L_0000000003857dd0; 1 drivers, strength-aware
+L_0000000003858310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ea20_0 .net8 "VPB", 0 0, L_0000000003858310; 1 drivers, strength-aware
+L_00000000038583f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ec00_0 .net8 "VPWR", 0 0, L_00000000038583f0; 1 drivers, strength-aware
+v000000000346fba0_0 .net "Y", 0 0, L_00000000039229a0; alias, 1 drivers
+v000000000346e8e0_0 .net "not0_out_Y", 0 0, L_0000000003921350; 1 drivers
+S_00000000028d18d0 .scope module, "_284_" "sky130_fd_sc_hd__buf_1" 3 639, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v000000000346e520_0 .net "A", 0 0, L_00000000039229a0; alias, 1 drivers
+L_00000000038585b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346d6c0_0 .net8 "VGND", 0 0, L_00000000038585b0; 1 drivers, strength-aware
+L_0000000003858cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346e660_0 .net8 "VNB", 0 0, L_0000000003858cb0; 1 drivers, strength-aware
+L_0000000003858620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346e0c0_0 .net8 "VPB", 0 0, L_0000000003858620; 1 drivers, strength-aware
+L_0000000003858690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346f100_0 .net8 "VPWR", 0 0, L_0000000003858690; 1 drivers, strength-aware
+v000000000346e700_0 .net "X", 0 0, L_0000000003921970; alias, 1 drivers
+S_00000000028d1a50 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d18d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003922e00 .functor BUF 1, L_00000000039229a0, C4<0>, C4<0>, C4<0>;
+L_0000000003921970 .functor BUF 1, L_0000000003922e00, C4<0>, C4<0>, C4<0>;
+v000000000346f6a0_0 .net "A", 0 0, L_00000000039229a0; alias, 1 drivers
+L_00000000038587e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346eac0_0 .net8 "VGND", 0 0, L_00000000038587e0; 1 drivers, strength-aware
+L_0000000003858930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346f380_0 .net8 "VNB", 0 0, L_0000000003858930; 1 drivers, strength-aware
+L_0000000003858a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346e840_0 .net8 "VPB", 0 0, L_0000000003858a10; 1 drivers, strength-aware
+L_0000000003858a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346de40_0 .net8 "VPWR", 0 0, L_0000000003858a80; 1 drivers, strength-aware
+v000000000346e200_0 .net "X", 0 0, L_0000000003921970; alias, 1 drivers
+v000000000346d800_0 .net "buf0_out_X", 0 0, L_0000000003922e00; 1 drivers
+S_00000000028d7450 .scope module, "_285_" "sky130_fd_sc_hd__buf_1" 3 643, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v000000000346d8a0_0 .net "A", 0 0, L_0000000003920b70; alias, 1 drivers
+L_000000000385aa70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346d9e0_0 .net8 "VGND", 0 0, L_000000000385aa70; 1 drivers, strength-aware
+L_000000000385a300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346dd00_0 .net8 "VNB", 0 0, L_000000000385a300; 1 drivers, strength-aware
+L_000000000385a920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346e3e0_0 .net8 "VPB", 0 0, L_000000000385a920; 1 drivers, strength-aware
+L_0000000003859b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346eb60_0 .net8 "VPWR", 0 0, L_0000000003859b90; 1 drivers, strength-aware
+v000000000346d760_0 .net "X", 0 0, L_00000000039233b0; alias, 1 drivers
+S_00000000028d72d0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d7450;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921ac0 .functor BUF 1, L_0000000003920b70, C4<0>, C4<0>, C4<0>;
+L_00000000039233b0 .functor BUF 1, L_0000000003921ac0, C4<0>, C4<0>, C4<0>;
+v000000000346e020_0 .net "A", 0 0, L_0000000003920b70; alias, 1 drivers
+L_000000000385ac30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346db20_0 .net8 "VGND", 0 0, L_000000000385ac30; 1 drivers, strength-aware
+L_0000000003859f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346e2a0_0 .net8 "VNB", 0 0, L_0000000003859f10; 1 drivers, strength-aware
+L_0000000003859d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346f4c0_0 .net8 "VPB", 0 0, L_0000000003859d50; 1 drivers, strength-aware
+L_000000000385abc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346dee0_0 .net8 "VPWR", 0 0, L_000000000385abc0; 1 drivers, strength-aware
+v000000000346ede0_0 .net "X", 0 0, L_00000000039233b0; alias, 1 drivers
+v000000000346e340_0 .net "buf0_out_X", 0 0, L_0000000003921ac0; 1 drivers
+S_00000000028d5ad0 .scope module, "_286_" "sky130_fd_sc_hd__nor2_2" 3 647, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000346f060_0 .net "A", 0 0, L_000000000391e8e0; alias, 1 drivers
+v000000000346f1a0_0 .net "B", 0 0, L_00000000039229a0; alias, 1 drivers
+L_000000000385b090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346f240_0 .net8 "VGND", 0 0, L_000000000385b090; 1 drivers, strength-aware
+L_000000000385ad10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346f2e0_0 .net8 "VNB", 0 0, L_000000000385ad10; 1 drivers, strength-aware
+L_000000000385a370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346f560_0 .net8 "VPB", 0 0, L_000000000385a370; 1 drivers, strength-aware
+L_000000000385a840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346da80_0 .net8 "VPWR", 0 0, L_000000000385a840; 1 drivers, strength-aware
+v000000000346d580_0 .net "Y", 0 0, L_0000000003922e70; alias, 1 drivers
+S_00000000028d5dd0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000028d5ad0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922bd0 .functor NOR 1, L_000000000391e8e0, L_00000000039229a0, C4<0>, C4<0>;
+L_0000000003922e70 .functor BUF 1, L_0000000003922bd0, C4<0>, C4<0>, C4<0>;
+v000000000346e7a0_0 .net "A", 0 0, L_000000000391e8e0; alias, 1 drivers
+v000000000346eca0_0 .net "B", 0 0, L_00000000039229a0; alias, 1 drivers
+L_000000000385a5a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346dbc0_0 .net8 "VGND", 0 0, L_000000000385a5a0; 1 drivers, strength-aware
+L_0000000003859ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346dc60_0 .net8 "VNB", 0 0, L_0000000003859ab0; 1 drivers, strength-aware
+L_0000000003859ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346ee80_0 .net8 "VPB", 0 0, L_0000000003859ce0; 1 drivers, strength-aware
+L_000000000385adf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346fc40_0 .net8 "VPWR", 0 0, L_000000000385adf0; 1 drivers, strength-aware
+v000000000346ef20_0 .net "Y", 0 0, L_0000000003922e70; alias, 1 drivers
+v000000000346efc0_0 .net "nor0_out_Y", 0 0, L_0000000003922bd0; 1 drivers
+S_00000000028d57d0 .scope module, "_287_" "sky130_fd_sc_hd__inv_2" 3 652, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000346d620_0 .net "A", 0 0, L_0000000003920b70; alias, 1 drivers
+L_000000000385a0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472440_0 .net8 "VGND", 0 0, L_000000000385a0d0; 1 drivers, strength-aware
+L_000000000385a140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003471400_0 .net8 "VNB", 0 0, L_000000000385a140; 1 drivers, strength-aware
+L_000000000385aed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034723a0_0 .net8 "VPB", 0 0, L_000000000385aed0; 1 drivers, strength-aware
+L_000000000385a990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034710e0_0 .net8 "VPWR", 0 0, L_000000000385a990; 1 drivers, strength-aware
+v0000000003471180_0 .net "Y", 0 0, L_0000000003922c40; alias, 1 drivers
+S_00000000028d6250 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d57d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921c80 .functor NOT 1, L_0000000003920b70, C4<0>, C4<0>, C4<0>;
+L_0000000003922c40 .functor BUF 1, L_0000000003921c80, C4<0>, C4<0>, C4<0>;
+v000000000346f600_0 .net "A", 0 0, L_0000000003920b70; alias, 1 drivers
+L_0000000003859880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346f740_0 .net8 "VGND", 0 0, L_0000000003859880; 1 drivers, strength-aware
+L_000000000385a1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346f7e0_0 .net8 "VNB", 0 0, L_000000000385a1b0; 1 drivers, strength-aware
+L_000000000385aa00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346f880_0 .net8 "VPB", 0 0, L_000000000385aa00; 1 drivers, strength-aware
+L_000000000385a530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346f920_0 .net8 "VPWR", 0 0, L_000000000385a530; 1 drivers, strength-aware
+v000000000346f9c0_0 .net "Y", 0 0, L_0000000003922c40; alias, 1 drivers
+v000000000346fb00_0 .net "not0_out_Y", 0 0, L_0000000003921c80; 1 drivers
+S_00000000028d63d0 .scope module, "_288_" "sky130_fd_sc_hd__o32a_2" 3 656, 4 45973 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+v0000000003471b80_0 .net "A1", 0 0, L_000000000380ab20; 1 drivers
+v0000000003470e60_0 .net "A2", 0 0, L_0000000003920b70; alias, 1 drivers
+v0000000003470a00_0 .net "A3", 0 0, L_000000000391e640; alias, 1 drivers
+v00000000034708c0_0 .net "B1", 0 0, L_000000000391e8e0; alias, 1 drivers
+v00000000034714a0_0 .net "B2", 0 0, L_0000000003922c40; alias, 1 drivers
+L_000000000385b020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003471680_0 .net8 "VGND", 0 0, L_000000000385b020; 1 drivers, strength-aware
+L_000000000385a8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003470f00_0 .net8 "VNB", 0 0, L_000000000385a8b0; 1 drivers, strength-aware
+L_000000000385b3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003471fe0_0 .net8 "VPB", 0 0, L_000000000385b3a0; 1 drivers, strength-aware
+L_0000000003859e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034700a0_0 .net8 "VPWR", 0 0, L_0000000003859e30; 1 drivers, strength-aware
+v0000000003471540_0 .net "X", 0 0, L_0000000003922f50; alias, 1 drivers
+S_00000000028d6fd0 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45995, 4 45841 1, S_00000000028d63d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_0000000003922cb0 .functor OR 1, L_0000000003920b70, L_000000000380ab20, L_000000000391e640, C4<0>;
+L_00000000039224d0 .functor OR 1, L_0000000003922c40, L_000000000391e8e0, C4<0>, C4<0>;
+L_0000000003922ee0 .functor AND 1, L_0000000003922cb0, L_00000000039224d0, C4<1>, C4<1>;
+L_0000000003922f50 .functor BUF 1, L_0000000003922ee0, C4<0>, C4<0>, C4<0>;
+v0000000003471a40_0 .net "A1", 0 0, L_000000000380ab20; alias, 1 drivers
+v0000000003470aa0_0 .net "A2", 0 0, L_0000000003920b70; alias, 1 drivers
+v0000000003471ae0_0 .net "A3", 0 0, L_000000000391e640; alias, 1 drivers
+v0000000003471220_0 .net "B1", 0 0, L_000000000391e8e0; alias, 1 drivers
+v00000000034719a0_0 .net "B2", 0 0, L_0000000003922c40; alias, 1 drivers
+L_000000000385a6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000346fd80_0 .net8 "VGND", 0 0, L_000000000385a6f0; 1 drivers, strength-aware
+L_000000000385a220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003471ea0_0 .net8 "VNB", 0 0, L_000000000385a220; 1 drivers, strength-aware
+L_000000000385b410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470820_0 .net8 "VPB", 0 0, L_000000000385b410; 1 drivers, strength-aware
+L_000000000385a760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034712c0_0 .net8 "VPWR", 0 0, L_000000000385a760; 1 drivers, strength-aware
+v00000000034724e0_0 .net "X", 0 0, L_0000000003922f50; alias, 1 drivers
+v0000000003471040_0 .net "and0_out_X", 0 0, L_0000000003922ee0; 1 drivers
+v0000000003470640_0 .net "or0_out", 0 0, L_0000000003922cb0; 1 drivers
+v0000000003471360_0 .net "or1_out", 0 0, L_00000000039224d0; 1 drivers
+S_00000000028d6e50 .scope module, "_289_" "sky130_fd_sc_hd__inv_2" 3 664, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003470000_0 .net "A", 0 0, L_000000000380cd80; 1 drivers
+L_000000000385af40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003470b40_0 .net8 "VGND", 0 0, L_000000000385af40; 1 drivers, strength-aware
+L_000000000385a290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472300_0 .net8 "VNB", 0 0, L_000000000385a290; 1 drivers, strength-aware
+L_000000000385ae60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034717c0_0 .net8 "VPB", 0 0, L_000000000385ae60; 1 drivers, strength-aware
+L_0000000003859a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470780_0 .net8 "VPWR", 0 0, L_0000000003859a40; 1 drivers, strength-aware
+v0000000003471900_0 .net "Y", 0 0, L_00000000039222a0; alias, 1 drivers
+S_00000000028d6550 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000028d6e50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039231f0 .functor NOT 1, L_000000000380cd80, C4<0>, C4<0>, C4<0>;
+L_00000000039222a0 .functor BUF 1, L_00000000039231f0, C4<0>, C4<0>, C4<0>;
+v00000000034706e0_0 .net "A", 0 0, L_000000000380cd80; alias, 1 drivers
+L_0000000003859b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034715e0_0 .net8 "VGND", 0 0, L_0000000003859b20; 1 drivers, strength-aware
+L_000000000385a3e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003470fa0_0 .net8 "VNB", 0 0, L_000000000385a3e0; 1 drivers, strength-aware
+L_0000000003859c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003471f40_0 .net8 "VPB", 0 0, L_0000000003859c00; 1 drivers, strength-aware
+L_000000000385b330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000346fe20_0 .net8 "VPWR", 0 0, L_000000000385b330; 1 drivers, strength-aware
+v0000000003471860_0 .net "Y", 0 0, L_00000000039222a0; alias, 1 drivers
+v0000000003471720_0 .net "not0_out_Y", 0 0, L_00000000039231f0; 1 drivers
+S_00000000028d66d0 .scope module, "_290_" "sky130_fd_sc_hd__or2_2" 3 668, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003470140_0 .net "A", 0 0, L_00000000039263d0; alias, 1 drivers
+v000000000346fec0_0 .net "B", 0 0, L_00000000039222a0; alias, 1 drivers
+L_00000000038598f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003471c20_0 .net8 "VGND", 0 0, L_00000000038598f0; 1 drivers, strength-aware
+L_0000000003859960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003471cc0_0 .net8 "VNB", 0 0, L_0000000003859960; 1 drivers, strength-aware
+L_000000000385a7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470d20_0 .net8 "VPB", 0 0, L_000000000385a7d0; 1 drivers, strength-aware
+L_000000000385a610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470dc0_0 .net8 "VPWR", 0 0, L_000000000385a610; 1 drivers, strength-aware
+v0000000003471e00_0 .net "X", 0 0, L_0000000003922d90; alias, 1 drivers
+S_00000000028d6cd0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d66d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922690 .functor OR 1, L_00000000039222a0, L_00000000039263d0, C4<0>, C4<0>;
+L_0000000003922d90 .functor BUF 1, L_0000000003922690, C4<0>, C4<0>, C4<0>;
+v00000000034703c0_0 .net "A", 0 0, L_00000000039263d0; alias, 1 drivers
+v00000000034721c0_0 .net "B", 0 0, L_00000000039222a0; alias, 1 drivers
+L_000000000385aae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003470500_0 .net8 "VGND", 0 0, L_000000000385aae0; 1 drivers, strength-aware
+L_000000000385ab50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003470960_0 .net8 "VNB", 0 0, L_000000000385ab50; 1 drivers, strength-aware
+L_0000000003859ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470280_0 .net8 "VPB", 0 0, L_0000000003859ff0; 1 drivers, strength-aware
+L_0000000003859dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470be0_0 .net8 "VPWR", 0 0, L_0000000003859dc0; 1 drivers, strength-aware
+v0000000003470c80_0 .net "X", 0 0, L_0000000003922d90; alias, 1 drivers
+v0000000003471d60_0 .net "or0_out_X", 0 0, L_0000000003922690; 1 drivers
+S_00000000028d7150 .scope module, "_291_" "sky130_fd_sc_hd__or2_2" 3 673, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003473f20_0 .net "A", 0 0, L_000000000391fc90; alias, 1 drivers
+v0000000003473fc0_0 .net "B", 0 0, L_0000000003922d90; alias, 1 drivers
+L_000000000385aca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474060_0 .net8 "VGND", 0 0, L_000000000385aca0; 1 drivers, strength-aware
+L_000000000385ad80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474420_0 .net8 "VNB", 0 0, L_000000000385ad80; 1 drivers, strength-aware
+L_000000000385afb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473520_0 .net8 "VPB", 0 0, L_000000000385afb0; 1 drivers, strength-aware
+L_000000000385b1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034735c0_0 .net8 "VPWR", 0 0, L_000000000385b1e0; 1 drivers, strength-aware
+v0000000003473660_0 .net "X", 0 0, L_0000000003922540; alias, 1 drivers
+S_00000000028d6b50 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d7150;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922310 .functor OR 1, L_0000000003922d90, L_000000000391fc90, C4<0>, C4<0>;
+L_0000000003922540 .functor BUF 1, L_0000000003922310, C4<0>, C4<0>, C4<0>;
+v000000000346ff60_0 .net "A", 0 0, L_000000000391fc90; alias, 1 drivers
+v0000000003472080_0 .net "B", 0 0, L_0000000003922d90; alias, 1 drivers
+L_0000000003859c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472120_0 .net8 "VGND", 0 0, L_0000000003859c70; 1 drivers, strength-aware
+L_0000000003859ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472260_0 .net8 "VNB", 0 0, L_0000000003859ea0; 1 drivers, strength-aware
+L_0000000003859f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034701e0_0 .net8 "VPB", 0 0, L_0000000003859f80; 1 drivers, strength-aware
+L_000000000385b100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003470320_0 .net8 "VPWR", 0 0, L_000000000385b100; 1 drivers, strength-aware
+v0000000003470460_0 .net "X", 0 0, L_0000000003922540; alias, 1 drivers
+v00000000034705a0_0 .net "or0_out_X", 0 0, L_0000000003922310; 1 drivers
+S_00000000028d5f50 .scope module, "_292_" "sky130_fd_sc_hd__or2_2" 3 678, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003474880_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003474a60_0 .net "B", 0 0, L_0000000003922540; alias, 1 drivers
+L_000000000385b170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034741a0_0 .net8 "VGND", 0 0, L_000000000385b170; 1 drivers, strength-aware
+L_00000000038599d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034746a0_0 .net8 "VNB", 0 0, L_00000000038599d0; 1 drivers, strength-aware
+L_000000000385b250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473200_0 .net8 "VPB", 0 0, L_000000000385b250; 1 drivers, strength-aware
+L_000000000385a060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034738e0_0 .net8 "VPWR", 0 0, L_000000000385a060; 1 drivers, strength-aware
+v00000000034728a0_0 .net "X", 0 0, L_0000000003921cf0; alias, 1 drivers
+S_00000000028d6850 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d5f50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922380 .functor OR 1, L_0000000003922540, L_0000000003926980, C4<0>, C4<0>;
+L_0000000003921cf0 .functor BUF 1, L_0000000003922380, C4<0>, C4<0>, C4<0>;
+v00000000034749c0_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003472d00_0 .net "B", 0 0, L_0000000003922540; alias, 1 drivers
+L_000000000385b2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472e40_0 .net8 "VGND", 0 0, L_000000000385b2c0; 1 drivers, strength-aware
+L_000000000385a450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003473700_0 .net8 "VNB", 0 0, L_000000000385a450; 1 drivers, strength-aware
+L_000000000385a4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473160_0 .net8 "VPB", 0 0, L_000000000385a4c0; 1 drivers, strength-aware
+L_000000000385a680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473de0_0 .net8 "VPWR", 0 0, L_000000000385a680; 1 drivers, strength-aware
+v0000000003473840_0 .net "X", 0 0, L_0000000003921cf0; alias, 1 drivers
+v0000000003474100_0 .net "or0_out_X", 0 0, L_0000000003922380; 1 drivers
+S_00000000028d5950 .scope module, "_293_" "sky130_fd_sc_hd__buf_1" 3 683, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003474240_0 .net "A", 0 0, L_0000000003921cf0; alias, 1 drivers
+L_000000000385b950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034742e0_0 .net8 "VGND", 0 0, L_000000000385b950; 1 drivers, strength-aware
+L_000000000385bbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472da0_0 .net8 "VNB", 0 0, L_000000000385bbf0; 1 drivers, strength-aware
+L_000000000385b480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034744c0_0 .net8 "VPB", 0 0, L_000000000385b480; 1 drivers, strength-aware
+L_000000000385bf70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473a20_0 .net8 "VPWR", 0 0, L_000000000385bf70; 1 drivers, strength-aware
+v00000000034733e0_0 .net "X", 0 0, L_0000000003922d20; alias, 1 drivers
+S_00000000028d60d0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000028d5950;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921b30 .functor BUF 1, L_0000000003921cf0, C4<0>, C4<0>, C4<0>;
+L_0000000003922d20 .functor BUF 1, L_0000000003921b30, C4<0>, C4<0>, C4<0>;
+v00000000034737a0_0 .net "A", 0 0, L_0000000003921cf0; alias, 1 drivers
+L_000000000385c910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472ee0_0 .net8 "VGND", 0 0, L_000000000385c910; 1 drivers, strength-aware
+L_000000000385be90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003473980_0 .net8 "VNB", 0 0, L_000000000385be90; 1 drivers, strength-aware
+L_000000000385c6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003474740_0 .net8 "VPB", 0 0, L_000000000385c6e0; 1 drivers, strength-aware
+L_000000000385cf30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003474b00_0 .net8 "VPWR", 0 0, L_000000000385cf30; 1 drivers, strength-aware
+v0000000003473340_0 .net "X", 0 0, L_0000000003922d20; alias, 1 drivers
+v0000000003474380_0 .net "buf0_out_X", 0 0, L_0000000003921b30; 1 drivers
+S_00000000028d69d0 .scope module, "_294_" "sky130_fd_sc_hd__nor2_2" 3 687, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003474560_0 .net "A", 0 0, L_0000000003920e80; alias, 1 drivers
+v0000000003473c00_0 .net "B", 0 0, L_0000000003922d20; alias, 1 drivers
+L_000000000385c590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474ce0_0 .net8 "VGND", 0 0, L_000000000385c590; 1 drivers, strength-aware
+L_000000000385b870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003473ca0_0 .net8 "VNB", 0 0, L_000000000385b870; 1 drivers, strength-aware
+L_000000000385b720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034729e0_0 .net8 "VPB", 0 0, L_000000000385b720; 1 drivers, strength-aware
+L_000000000385c750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003473d40_0 .net8 "VPWR", 0 0, L_000000000385c750; 1 drivers, strength-aware
+v0000000003474600_0 .net "Y", 0 0, L_0000000003922700; alias, 1 drivers
+S_00000000028d75d0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000028d69d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921ba0 .functor NOR 1, L_0000000003920e80, L_0000000003922d20, C4<0>, C4<0>;
+L_0000000003922700 .functor BUF 1, L_0000000003921ba0, C4<0>, C4<0>, C4<0>;
+v0000000003473020_0 .net "A", 0 0, L_0000000003920e80; alias, 1 drivers
+v0000000003473480_0 .net "B", 0 0, L_0000000003922d20; alias, 1 drivers
+L_000000000385b790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472a80_0 .net8 "VGND", 0 0, L_000000000385b790; 1 drivers, strength-aware
+L_000000000385cc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003473e80_0 .net8 "VNB", 0 0, L_000000000385cc20; 1 drivers, strength-aware
+L_000000000385c980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034732a0_0 .net8 "VPB", 0 0, L_000000000385c980; 1 drivers, strength-aware
+L_000000000385b8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003472940_0 .net8 "VPWR", 0 0, L_000000000385b8e0; 1 drivers, strength-aware
+v0000000003473ac0_0 .net "Y", 0 0, L_0000000003922700; alias, 1 drivers
+v0000000003473b60_0 .net "nor0_out_Y", 0 0, L_0000000003921ba0; 1 drivers
+S_00000000028d5c50 .scope module, "_295_" "sky130_fd_sc_hd__or2_2" 3 692, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003472800_0 .net "A", 0 0, L_0000000003926c20; alias, 1 drivers
+v0000000003472b20_0 .net "B", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000385cec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472bc0_0 .net8 "VGND", 0 0, L_000000000385cec0; 1 drivers, strength-aware
+L_000000000385b640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003472c60_0 .net8 "VNB", 0 0, L_000000000385b640; 1 drivers, strength-aware
+L_000000000385cc90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003472f80_0 .net8 "VPB", 0 0, L_000000000385cc90; 1 drivers, strength-aware
+L_000000000385c2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034730c0_0 .net8 "VPWR", 0 0, L_000000000385c2f0; 1 drivers, strength-aware
+v0000000003475820_0 .net "X", 0 0, L_00000000039220e0; alias, 1 drivers
+S_00000000034a2b60 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000028d5c50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922150 .functor OR 1, L_000000000391fc90, L_0000000003926c20, C4<0>, C4<0>;
+L_00000000039220e0 .functor BUF 1, L_0000000003922150, C4<0>, C4<0>, C4<0>;
+v00000000034747e0_0 .net "A", 0 0, L_0000000003926c20; alias, 1 drivers
+v0000000003474920_0 .net "B", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000385c600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474ba0_0 .net8 "VGND", 0 0, L_000000000385c600; 1 drivers, strength-aware
+L_000000000385baa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474c40_0 .net8 "VNB", 0 0, L_000000000385baa0; 1 drivers, strength-aware
+L_000000000385bcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003472580_0 .net8 "VPB", 0 0, L_000000000385bcd0; 1 drivers, strength-aware
+L_000000000385bf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034726c0_0 .net8 "VPWR", 0 0, L_000000000385bf00; 1 drivers, strength-aware
+v0000000003472620_0 .net "X", 0 0, L_00000000039220e0; alias, 1 drivers
+v0000000003472760_0 .net "or0_out_X", 0 0, L_0000000003922150; 1 drivers
+S_00000000034a1960 .scope module, "_296_" "sky130_fd_sc_hd__or2_2" 3 697, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003475320_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v00000000034762c0_0 .net "B", 0 0, L_00000000039220e0; alias, 1 drivers
+L_000000000385c7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034756e0_0 .net8 "VGND", 0 0, L_000000000385c7c0; 1 drivers, strength-aware
+L_000000000385c670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476180_0 .net8 "VNB", 0 0, L_000000000385c670; 1 drivers, strength-aware
+L_000000000385b800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034755a0_0 .net8 "VPB", 0 0, L_000000000385b800; 1 drivers, strength-aware
+L_000000000385c9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003475fa0_0 .net8 "VPWR", 0 0, L_000000000385c9f0; 1 drivers, strength-aware
+v0000000003476f40_0 .net "X", 0 0, L_0000000003921c10; alias, 1 drivers
+S_00000000034a1c60 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000034a1960;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922fc0 .functor OR 1, L_00000000039220e0, L_0000000003926980, C4<0>, C4<0>;
+L_0000000003921c10 .functor BUF 1, L_0000000003922fc0, C4<0>, C4<0>, C4<0>;
+v0000000003476c20_0 .net "A", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003475280_0 .net "B", 0 0, L_00000000039220e0; alias, 1 drivers
+L_000000000385b9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034750a0_0 .net8 "VGND", 0 0, L_000000000385b9c0; 1 drivers, strength-aware
+L_000000000385c830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475b40_0 .net8 "VNB", 0 0, L_000000000385c830; 1 drivers, strength-aware
+L_000000000385c8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003475500_0 .net8 "VPB", 0 0, L_000000000385c8a0; 1 drivers, strength-aware
+L_000000000385ca60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034758c0_0 .net8 "VPWR", 0 0, L_000000000385ca60; 1 drivers, strength-aware
+v0000000003476040_0 .net "X", 0 0, L_0000000003921c10; alias, 1 drivers
+v00000000034751e0_0 .net "or0_out_X", 0 0, L_0000000003922fc0; 1 drivers
+S_00000000034a1060 .scope module, "_297_" "sky130_fd_sc_hd__buf_1" 3 702, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003475aa0_0 .net "A", 0 0, L_0000000003921c10; alias, 1 drivers
+L_000000000385cad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475c80_0 .net8 "VGND", 0 0, L_000000000385cad0; 1 drivers, strength-aware
+L_000000000385c050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475960_0 .net8 "VNB", 0 0, L_000000000385c050; 1 drivers, strength-aware
+L_000000000385cb40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003476220_0 .net8 "VPB", 0 0, L_000000000385cb40; 1 drivers, strength-aware
+L_000000000385bd40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003476400_0 .net8 "VPWR", 0 0, L_000000000385bd40; 1 drivers, strength-aware
+v00000000034773a0_0 .net "X", 0 0, L_0000000003922770; alias, 1 drivers
+S_00000000034a14e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000034a1060;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003923110 .functor BUF 1, L_0000000003921c10, C4<0>, C4<0>, C4<0>;
+L_0000000003922770 .functor BUF 1, L_0000000003923110, C4<0>, C4<0>, C4<0>;
+v0000000003475140_0 .net "A", 0 0, L_0000000003921c10; alias, 1 drivers
+L_000000000385bfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475780_0 .net8 "VGND", 0 0, L_000000000385bfe0; 1 drivers, strength-aware
+L_000000000385cbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475d20_0 .net8 "VNB", 0 0, L_000000000385cbb0; 1 drivers, strength-aware
+L_000000000385c0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003475dc0_0 .net8 "VPB", 0 0, L_000000000385c0c0; 1 drivers, strength-aware
+L_000000000385c210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003476fe0_0 .net8 "VPWR", 0 0, L_000000000385c210; 1 drivers, strength-aware
+v00000000034753c0_0 .net "X", 0 0, L_0000000003922770; alias, 1 drivers
+v0000000003475640_0 .net "buf0_out_X", 0 0, L_0000000003923110; 1 drivers
+S_00000000034a20e0 .scope module, "_298_" "sky130_fd_sc_hd__nor2_2" 3 706, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003477080_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+v0000000003475f00_0 .net "B", 0 0, L_0000000003922770; alias, 1 drivers
+L_000000000385bc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476540_0 .net8 "VGND", 0 0, L_000000000385bc60; 1 drivers, strength-aware
+L_000000000385c280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034760e0_0 .net8 "VNB", 0 0, L_000000000385c280; 1 drivers, strength-aware
+L_000000000385c440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034765e0_0 .net8 "VPB", 0 0, L_000000000385c440; 1 drivers, strength-aware
+L_000000000385c360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003476680_0 .net8 "VPWR", 0 0, L_000000000385c360; 1 drivers, strength-aware
+v0000000003476720_0 .net "Y", 0 0, L_0000000003923030; alias, 1 drivers
+S_00000000034a1de0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000034a20e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922a80 .functor NOR 1, L_0000000003920860, L_0000000003922770, C4<0>, C4<0>;
+L_0000000003923030 .functor BUF 1, L_0000000003922a80, C4<0>, C4<0>, C4<0>;
+v0000000003476a40_0 .net "A", 0 0, L_0000000003920860; alias, 1 drivers
+v0000000003475a00_0 .net "B", 0 0, L_0000000003922770; alias, 1 drivers
+L_000000000385bdb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476360_0 .net8 "VGND", 0 0, L_000000000385bdb0; 1 drivers, strength-aware
+L_000000000385be20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003475460_0 .net8 "VNB", 0 0, L_000000000385be20; 1 drivers, strength-aware
+L_000000000385cd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003476ae0_0 .net8 "VPB", 0 0, L_000000000385cd00; 1 drivers, strength-aware
+L_000000000385cde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034764a0_0 .net8 "VPWR", 0 0, L_000000000385cde0; 1 drivers, strength-aware
+v0000000003475be0_0 .net "Y", 0 0, L_0000000003923030; alias, 1 drivers
+v0000000003475e60_0 .net "nor0_out_Y", 0 0, L_0000000003922a80; 1 drivers
+S_00000000034a1f60 .scope module, "_299_" "sky130_fd_sc_hd__inv_2" 3 711, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v0000000003476d60_0 .net "A", 0 0, L_000000000380cec0; 1 drivers
+L_000000000385cd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476e00_0 .net8 "VGND", 0 0, L_000000000385cd70; 1 drivers, strength-aware
+L_000000000385cfa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476ea0_0 .net8 "VNB", 0 0, L_000000000385cfa0; 1 drivers, strength-aware
+L_000000000385c3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034771c0_0 .net8 "VPB", 0 0, L_000000000385c3d0; 1 drivers, strength-aware
+L_000000000385c130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003477260_0 .net8 "VPWR", 0 0, L_000000000385c130; 1 drivers, strength-aware
+v0000000003477300_0 .net "Y", 0 0, L_00000000039230a0; alias, 1 drivers
+S_00000000034a1ae0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000034a1f60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921d60 .functor NOT 1, L_000000000380cec0, C4<0>, C4<0>, C4<0>;
+L_00000000039230a0 .functor BUF 1, L_0000000003921d60, C4<0>, C4<0>, C4<0>;
+v00000000034767c0_0 .net "A", 0 0, L_000000000380cec0; alias, 1 drivers
+L_000000000385ce50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476860_0 .net8 "VGND", 0 0, L_000000000385ce50; 1 drivers, strength-aware
+L_000000000385ba30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003476900_0 .net8 "VNB", 0 0, L_000000000385ba30; 1 drivers, strength-aware
+L_000000000385c1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003477120_0 .net8 "VPB", 0 0, L_000000000385c1a0; 1 drivers, strength-aware
+L_000000000385d010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034769a0_0 .net8 "VPWR", 0 0, L_000000000385d010; 1 drivers, strength-aware
+v0000000003476b80_0 .net "Y", 0 0, L_00000000039230a0; alias, 1 drivers
+v0000000003476cc0_0 .net "not0_out_Y", 0 0, L_0000000003921d60; 1 drivers
+S_00000000034a17e0 .scope module, "_300_" "sky130_fd_sc_hd__or2_2" 3 715, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003478520_0 .net "A", 0 0, L_0000000003926440; alias, 1 drivers
+v0000000003479c40_0 .net "B", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_000000000385c4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477d00_0 .net8 "VGND", 0 0, L_000000000385c4b0; 1 drivers, strength-aware
+L_000000000385bb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003478ac0_0 .net8 "VNB", 0 0, L_000000000385bb10; 1 drivers, strength-aware
+L_000000000385b4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003477e40_0 .net8 "VPB", 0 0, L_000000000385b4f0; 1 drivers, strength-aware
+L_000000000385c520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478660_0 .net8 "VPWR", 0 0, L_000000000385c520; 1 drivers, strength-aware
+v0000000003478160_0 .net "X", 0 0, L_00000000039225b0; alias, 1 drivers
+S_00000000034a1660 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000034a17e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922620 .functor OR 1, L_000000000391e6b0, L_0000000003926440, C4<0>, C4<0>;
+L_00000000039225b0 .functor BUF 1, L_0000000003922620, C4<0>, C4<0>, C4<0>;
+v0000000003477440_0 .net "A", 0 0, L_0000000003926440; alias, 1 drivers
+v00000000034774e0_0 .net "B", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_000000000385bb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474d80_0 .net8 "VGND", 0 0, L_000000000385bb80; 1 drivers, strength-aware
+L_000000000385b560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003474e20_0 .net8 "VNB", 0 0, L_000000000385b560; 1 drivers, strength-aware
+L_000000000385b5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003474ec0_0 .net8 "VPB", 0 0, L_000000000385b5d0; 1 drivers, strength-aware
+L_000000000385b6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003474f60_0 .net8 "VPWR", 0 0, L_000000000385b6b0; 1 drivers, strength-aware
+v0000000003475000_0 .net "X", 0 0, L_00000000039225b0; alias, 1 drivers
+v0000000003477a80_0 .net "or0_out_X", 0 0, L_0000000003922620; 1 drivers
+S_00000000034a2ce0 .scope module, "_301_" "sky130_fd_sc_hd__buf_1" 3 720, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003479ce0_0 .net "A", 0 0, L_00000000039225b0; alias, 1 drivers
+L_000000000385d470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034783e0_0 .net8 "VGND", 0 0, L_000000000385d470; 1 drivers, strength-aware
+L_000000000385dcc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477f80_0 .net8 "VNB", 0 0, L_000000000385dcc0; 1 drivers, strength-aware
+L_000000000385d390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478a20_0 .net8 "VPB", 0 0, L_000000000385d390; 1 drivers, strength-aware
+L_000000000385d5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478e80_0 .net8 "VPWR", 0 0, L_000000000385d5c0; 1 drivers, strength-aware
+v00000000034780c0_0 .net "X", 0 0, L_00000000039219e0; alias, 1 drivers
+S_00000000034a1360 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000034a2ce0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003921eb0 .functor BUF 1, L_00000000039225b0, C4<0>, C4<0>, C4<0>;
+L_00000000039219e0 .functor BUF 1, L_0000000003921eb0, C4<0>, C4<0>, C4<0>;
+v00000000034799c0_0 .net "A", 0 0, L_00000000039225b0; alias, 1 drivers
+L_000000000385d6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477760_0 .net8 "VGND", 0 0, L_000000000385d6a0; 1 drivers, strength-aware
+L_000000000385d710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003479060_0 .net8 "VNB", 0 0, L_000000000385d710; 1 drivers, strength-aware
+L_000000000385d940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034787a0_0 .net8 "VPB", 0 0, L_000000000385d940; 1 drivers, strength-aware
+L_000000000385d780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003477620_0 .net8 "VPWR", 0 0, L_000000000385d780; 1 drivers, strength-aware
+v0000000003478fc0_0 .net "X", 0 0, L_00000000039219e0; alias, 1 drivers
+v0000000003479600_0 .net "buf0_out_X", 0 0, L_0000000003921eb0; 1 drivers
+S_00000000034a2260 .scope module, "_302_" "sky130_fd_sc_hd__nor2_2" 3 724, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003477da0_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v0000000003477580_0 .net "B", 0 0, L_00000000039219e0; alias, 1 drivers
+L_000000000385d240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003478700_0 .net8 "VGND", 0 0, L_000000000385d240; 1 drivers, strength-aware
+L_000000000385def0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477800_0 .net8 "VNB", 0 0, L_000000000385def0; 1 drivers, strength-aware
+L_000000000385d4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479a60_0 .net8 "VPB", 0 0, L_000000000385d4e0; 1 drivers, strength-aware
+L_000000000385db70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003477ee0_0 .net8 "VPWR", 0 0, L_000000000385db70; 1 drivers, strength-aware
+v0000000003479420_0 .net "Y", 0 0, L_0000000003923180; alias, 1 drivers
+S_00000000034a26e0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000034a2260;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922230 .functor NOR 1, L_000000000391c570, L_00000000039219e0, C4<0>, C4<0>;
+L_0000000003923180 .functor BUF 1, L_0000000003922230, C4<0>, C4<0>, C4<0>;
+v0000000003477b20_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v00000000034779e0_0 .net "B", 0 0, L_00000000039219e0; alias, 1 drivers
+L_000000000385d080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477c60_0 .net8 "VGND", 0 0, L_000000000385d080; 1 drivers, strength-aware
+L_000000000385dc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477bc0_0 .net8 "VNB", 0 0, L_000000000385dc50; 1 drivers, strength-aware
+L_000000000385d630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478b60_0 .net8 "VPB", 0 0, L_000000000385d630; 1 drivers, strength-aware
+L_000000000385de10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479920_0 .net8 "VPWR", 0 0, L_000000000385de10; 1 drivers, strength-aware
+v0000000003478980_0 .net "Y", 0 0, L_0000000003923180; alias, 1 drivers
+v00000000034785c0_0 .net "nor0_out_Y", 0 0, L_0000000003922230; 1 drivers
+S_00000000034a23e0 .scope module, "_303_" "sky130_fd_sc_hd__or2_2" 3 729, 4 33031 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v0000000003478d40_0 .net "A", 0 0, L_0000000003926210; alias, 1 drivers
+v0000000003478de0_0 .net "B", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_000000000385d2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003477940_0 .net8 "VGND", 0 0, L_000000000385d2b0; 1 drivers, strength-aware
+L_000000000385d7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003478020_0 .net8 "VNB", 0 0, L_000000000385d7f0; 1 drivers, strength-aware
+L_000000000385d0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478f20_0 .net8 "VPB", 0 0, L_000000000385d0f0; 1 drivers, strength-aware
+L_000000000385d550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034782a0_0 .net8 "VPWR", 0 0, L_000000000385d550; 1 drivers, strength-aware
+v0000000003478340_0 .net "X", 0 0, L_0000000003922af0; alias, 1 drivers
+S_00000000034a29e0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 33047, 4 32814 1, S_00000000034a23e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003923260 .functor OR 1, L_000000000391e6b0, L_0000000003926210, C4<0>, C4<0>;
+L_0000000003922af0 .functor BUF 1, L_0000000003923260, C4<0>, C4<0>, C4<0>;
+v0000000003478c00_0 .net "A", 0 0, L_0000000003926210; alias, 1 drivers
+v00000000034776c0_0 .net "B", 0 0, L_000000000391e6b0; alias, 1 drivers
+L_000000000385d160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003478840_0 .net8 "VGND", 0 0, L_000000000385d160; 1 drivers, strength-aware
+L_000000000385dd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003479100_0 .net8 "VNB", 0 0, L_000000000385dd30; 1 drivers, strength-aware
+L_000000000385db00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034788e0_0 .net8 "VPB", 0 0, L_000000000385db00; 1 drivers, strength-aware
+L_000000000385d860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003478200_0 .net8 "VPWR", 0 0, L_000000000385d860; 1 drivers, strength-aware
+v0000000003478ca0_0 .net "X", 0 0, L_0000000003922af0; alias, 1 drivers
+v00000000034778a0_0 .net "or0_out_X", 0 0, L_0000000003923260; 1 drivers
+S_00000000034a2e60 .scope module, "_304_" "sky130_fd_sc_hd__buf_1" 3 734, 4 81154 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v00000000034796a0_0 .net "A", 0 0, L_0000000003922af0; alias, 1 drivers
+L_000000000385d8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003479740_0 .net8 "VGND", 0 0, L_000000000385d8d0; 1 drivers, strength-aware
+L_000000000385d9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034797e0_0 .net8 "VNB", 0 0, L_000000000385d9b0; 1 drivers, strength-aware
+L_000000000385d400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479880_0 .net8 "VPB", 0 0, L_000000000385d400; 1 drivers, strength-aware
+L_000000000385da20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479b00_0 .net8 "VPWR", 0 0, L_000000000385da20; 1 drivers, strength-aware
+v0000000003479ba0_0 .net "X", 0 0, L_00000000039232d0; alias, 1 drivers
+S_00000000034a11e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81168, 4 80948 1, S_00000000034a2e60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039227e0 .functor BUF 1, L_0000000003922af0, C4<0>, C4<0>, C4<0>;
+L_00000000039232d0 .functor BUF 1, L_00000000039227e0, C4<0>, C4<0>, C4<0>;
+v00000000034791a0_0 .net "A", 0 0, L_0000000003922af0; alias, 1 drivers
+L_000000000385dbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003479240_0 .net8 "VGND", 0 0, L_000000000385dbe0; 1 drivers, strength-aware
+L_000000000385da90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003478480_0 .net8 "VNB", 0 0, L_000000000385da90; 1 drivers, strength-aware
+L_000000000385d1d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034792e0_0 .net8 "VPB", 0 0, L_000000000385d1d0; 1 drivers, strength-aware
+L_000000000385dda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479380_0 .net8 "VPWR", 0 0, L_000000000385dda0; 1 drivers, strength-aware
+v00000000034794c0_0 .net "X", 0 0, L_00000000039232d0; alias, 1 drivers
+v0000000003479560_0 .net "buf0_out_X", 0 0, L_00000000039227e0; 1 drivers
+S_00000000034a2560 .scope module, "_305_" "sky130_fd_sc_hd__nor2_2" 3 738, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347a140_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v000000000347a5a0_0 .net "B", 0 0, L_00000000039232d0; alias, 1 drivers
+L_000000000385de80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347bcc0_0 .net8 "VGND", 0 0, L_000000000385de80; 1 drivers, strength-aware
+L_000000000385d320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347a000_0 .net8 "VNB", 0 0, L_000000000385d320; 1 drivers, strength-aware
+L_000000000385df60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347c440_0 .net8 "VPB", 0 0, L_000000000385df60; 1 drivers, strength-aware
+L_0000000003856550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a640_0 .net8 "VPWR", 0 0, L_0000000003856550; 1 drivers, strength-aware
+v000000000347b2c0_0 .net "Y", 0 0, L_0000000003921e40; alias, 1 drivers
+S_00000000034a2860 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000034a2560;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921dd0 .functor NOR 1, L_000000000391c570, L_00000000039232d0, C4<0>, C4<0>;
+L_0000000003921e40 .functor BUF 1, L_0000000003921dd0, C4<0>, C4<0>, C4<0>;
+v000000000347a960_0 .net "A", 0 0, L_000000000391c570; alias, 1 drivers
+v000000000347c260_0 .net "B", 0 0, L_00000000039232d0; alias, 1 drivers
+L_0000000003856390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347b540_0 .net8 "VGND", 0 0, L_0000000003856390; 1 drivers, strength-aware
+L_0000000003856c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347c4e0_0 .net8 "VNB", 0 0, L_0000000003856c50; 1 drivers, strength-aware
+L_00000000038562b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347b180_0 .net8 "VPB", 0 0, L_00000000038562b0; 1 drivers, strength-aware
+L_0000000003856780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a0a0_0 .net8 "VPWR", 0 0, L_0000000003856780; 1 drivers, strength-aware
+v000000000347ba40_0 .net "Y", 0 0, L_0000000003921e40; alias, 1 drivers
+v0000000003479ec0_0 .net "nor0_out_Y", 0 0, L_0000000003921dd0; 1 drivers
+S_000000000349e960 .scope module, "_306_" "sky130_fd_sc_hd__nor2_2" 3 743, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347ac80_0 .net "A", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000347a280_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003856710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347bd60_0 .net8 "VGND", 0 0, L_0000000003856710; 1 drivers, strength-aware
+L_0000000003857430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347b680_0 .net8 "VNB", 0 0, L_0000000003857430; 1 drivers, strength-aware
+L_0000000003857200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347ad20_0 .net8 "VPB", 0 0, L_0000000003857200; 1 drivers, strength-aware
+L_00000000038574a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a320_0 .net8 "VPWR", 0 0, L_00000000038574a0; 1 drivers, strength-aware
+v000000000347afa0_0 .net "Y", 0 0, L_0000000003923420; alias, 1 drivers
+S_000000000349b360 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349e960;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003923340 .functor NOR 1, L_0000000003925cd0, L_0000000003920e80, C4<0>, C4<0>;
+L_0000000003923420 .functor BUF 1, L_0000000003923340, C4<0>, C4<0>, C4<0>;
+v000000000347ae60_0 .net "A", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000347b900_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003856e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347af00_0 .net8 "VGND", 0 0, L_0000000003856e80; 1 drivers, strength-aware
+L_00000000038567f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347b860_0 .net8 "VNB", 0 0, L_00000000038567f0; 1 drivers, strength-aware
+L_0000000003856470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347c1c0_0 .net8 "VPB", 0 0, L_0000000003856470; 1 drivers, strength-aware
+L_00000000038565c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a1e0_0 .net8 "VPWR", 0 0, L_00000000038565c0; 1 drivers, strength-aware
+v000000000347c300_0 .net "Y", 0 0, L_0000000003923420; alias, 1 drivers
+v000000000347aa00_0 .net "nor0_out_Y", 0 0, L_0000000003923340; 1 drivers
+S_000000000349b960 .scope module, "_307_" "sky130_fd_sc_hd__nor2_2" 3 748, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347be00_0 .net "A", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000347bfe0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_00000000038561d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347a6e0_0 .net8 "VGND", 0 0, L_00000000038561d0; 1 drivers, strength-aware
+L_0000000003856be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347ab40_0 .net8 "VNB", 0 0, L_0000000003856be0; 1 drivers, strength-aware
+L_0000000003856cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a500_0 .net8 "VPB", 0 0, L_0000000003856cc0; 1 drivers, strength-aware
+L_0000000003856860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347b0e0_0 .net8 "VPWR", 0 0, L_0000000003856860; 1 drivers, strength-aware
+v000000000347a780_0 .net "Y", 0 0, L_0000000003921f20; 1 drivers
+S_000000000349d760 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349b960;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922850 .functor NOR 1, L_0000000003925cd0, L_000000000391d840, C4<0>, C4<0>;
+L_0000000003921f20 .functor BUF 1, L_0000000003922850, C4<0>, C4<0>, C4<0>;
+v000000000347b4a0_0 .net "A", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000347adc0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_0000000003857270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347bae0_0 .net8 "VGND", 0 0, L_0000000003857270; 1 drivers, strength-aware
+L_0000000003857040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347aaa0_0 .net8 "VNB", 0 0, L_0000000003857040; 1 drivers, strength-aware
+L_00000000038568d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a3c0_0 .net8 "VPB", 0 0, L_00000000038568d0; 1 drivers, strength-aware
+L_0000000003856240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003479f60_0 .net8 "VPWR", 0 0, L_0000000003856240; 1 drivers, strength-aware
+v000000000347b040_0 .net "Y", 0 0, L_0000000003921f20; alias, 1 drivers
+v000000000347a460_0 .net "nor0_out_Y", 0 0, L_0000000003922850; 1 drivers
+S_000000000349b4e0 .scope module, "_308_" "sky130_fd_sc_hd__nor2_2" 3 753, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347b360_0 .net "A", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000347b400_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003857350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347b7c0_0 .net8 "VGND", 0 0, L_0000000003857350; 1 drivers, strength-aware
+L_0000000003856320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347bc20_0 .net8 "VNB", 0 0, L_0000000003856320; 1 drivers, strength-aware
+L_00000000038560f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347bea0_0 .net8 "VPB", 0 0, L_00000000038560f0; 1 drivers, strength-aware
+L_0000000003856940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347bf40_0 .net8 "VPWR", 0 0, L_0000000003856940; 1 drivers, strength-aware
+v0000000003479d80_0 .net "Y", 0 0, L_0000000003922b60; alias, 1 drivers
+S_000000000349ce60 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349b4e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921f90 .functor NOR 1, L_00000000039283c0, L_0000000003920e80, C4<0>, C4<0>;
+L_0000000003922b60 .functor BUF 1, L_0000000003921f90, C4<0>, C4<0>, C4<0>;
+v000000000347b720_0 .net "A", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000347b9a0_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_00000000038569b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347bb80_0 .net8 "VGND", 0 0, L_00000000038569b0; 1 drivers, strength-aware
+L_0000000003856160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347a820_0 .net8 "VNB", 0 0, L_0000000003856160; 1 drivers, strength-aware
+L_0000000003856630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347a8c0_0 .net8 "VPB", 0 0, L_0000000003856630; 1 drivers, strength-aware
+L_0000000003857660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347abe0_0 .net8 "VPWR", 0 0, L_0000000003857660; 1 drivers, strength-aware
+v000000000347b5e0_0 .net "Y", 0 0, L_0000000003922b60; alias, 1 drivers
+v000000000347b220_0 .net "nor0_out_Y", 0 0, L_0000000003921f90; 1 drivers
+S_000000000349c9e0 .scope module, "_309_" "sky130_fd_sc_hd__nor2_2" 3 758, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347c760_0 .net "A", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000347e9c0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_00000000038566a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347cd00_0 .net8 "VGND", 0 0, L_00000000038566a0; 1 drivers, strength-aware
+L_0000000003856400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347e420_0 .net8 "VNB", 0 0, L_0000000003856400; 1 drivers, strength-aware
+L_0000000003856ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347cee0_0 .net8 "VPB", 0 0, L_0000000003856ef0; 1 drivers, strength-aware
+L_00000000038564e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347e060_0 .net8 "VPWR", 0 0, L_00000000038564e0; 1 drivers, strength-aware
+v000000000347e920_0 .net "Y", 0 0, L_0000000003922000; 1 drivers
+S_000000000349b660 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349c9e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003923490 .functor NOR 1, L_00000000039283c0, L_000000000391d840, C4<0>, C4<0>;
+L_0000000003922000 .functor BUF 1, L_0000000003923490, C4<0>, C4<0>, C4<0>;
+v000000000347c080_0 .net "A", 0 0, L_00000000039283c0; alias, 1 drivers
+v0000000003479e20_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_00000000038576d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347c120_0 .net8 "VGND", 0 0, L_00000000038576d0; 1 drivers, strength-aware
+L_0000000003857190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347c3a0_0 .net8 "VNB", 0 0, L_0000000003857190; 1 drivers, strength-aware
+L_0000000003857ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d5c0_0 .net8 "VPB", 0 0, L_0000000003857ba0; 1 drivers, strength-aware
+L_0000000003857510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d480_0 .net8 "VPWR", 0 0, L_0000000003857510; 1 drivers, strength-aware
+v000000000347ca80_0 .net "Y", 0 0, L_0000000003922000; alias, 1 drivers
+v000000000347dfc0_0 .net "nor0_out_Y", 0 0, L_0000000003923490; 1 drivers
+S_000000000349ef60 .scope module, "_310_" "sky130_fd_sc_hd__inv_2" 3 763, 4 54053 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v000000000347c940_0 .net "A", 0 0, L_000000000380c060; 1 drivers
+L_00000000038572e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347cda0_0 .net8 "VGND", 0 0, L_00000000038572e0; 1 drivers, strength-aware
+L_0000000003856a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347da20_0 .net8 "VNB", 0 0, L_0000000003856a20; 1 drivers, strength-aware
+L_0000000003857740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347ce40_0 .net8 "VPB", 0 0, L_0000000003857740; 1 drivers, strength-aware
+L_0000000003857580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d700_0 .net8 "VPWR", 0 0, L_0000000003857580; 1 drivers, strength-aware
+v000000000347e740_0 .net "Y", 0 0, L_00000000039221c0; alias, 1 drivers
+S_000000000349f560 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_000000000349ef60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003922070 .functor NOT 1, L_000000000380c060, C4<0>, C4<0>, C4<0>;
+L_00000000039221c0 .functor BUF 1, L_0000000003922070, C4<0>, C4<0>, C4<0>;
+v000000000347cf80_0 .net "A", 0 0, L_000000000380c060; alias, 1 drivers
+L_0000000003856b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347d520_0 .net8 "VGND", 0 0, L_0000000003856b00; 1 drivers, strength-aware
+L_0000000003856a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347d200_0 .net8 "VNB", 0 0, L_0000000003856a90; 1 drivers, strength-aware
+L_00000000038575f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d840_0 .net8 "VPB", 0 0, L_00000000038575f0; 1 drivers, strength-aware
+L_0000000003856b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347c8a0_0 .net8 "VPWR", 0 0, L_0000000003856b70; 1 drivers, strength-aware
+v000000000347e1a0_0 .net "Y", 0 0, L_00000000039221c0; alias, 1 drivers
+v000000000347dc00_0 .net "not0_out_Y", 0 0, L_0000000003922070; 1 drivers
+S_000000000349d160 .scope module, "_311_" "sky130_fd_sc_hd__nor2_2" 3 767, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347d660_0 .net "A", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000347cb20_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003857120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347d980_0 .net8 "VGND", 0 0, L_0000000003857120; 1 drivers, strength-aware
+L_00000000038573c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347d7a0_0 .net8 "VNB", 0 0, L_00000000038573c0; 1 drivers, strength-aware
+L_0000000003856d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d160_0 .net8 "VPB", 0 0, L_0000000003856d30; 1 drivers, strength-aware
+L_0000000003856da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347dca0_0 .net8 "VPWR", 0 0, L_0000000003856da0; 1 drivers, strength-aware
+v000000000347dd40_0 .net "Y", 0 0, L_0000000003922a10; alias, 1 drivers
+S_000000000349c0e0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349d160;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921900 .functor NOR 1, L_0000000003927470, L_0000000003920e80, C4<0>, C4<0>;
+L_0000000003922a10 .functor BUF 1, L_0000000003921900, C4<0>, C4<0>, C4<0>;
+v000000000347df20_0 .net "A", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000347d020_0 .net "B", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003856080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347e240_0 .net8 "VGND", 0 0, L_0000000003856080; 1 drivers, strength-aware
+L_0000000003856e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347e2e0_0 .net8 "VNB", 0 0, L_0000000003856e10; 1 drivers, strength-aware
+L_00000000038577b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347d340_0 .net8 "VPB", 0 0, L_00000000038577b0; 1 drivers, strength-aware
+L_0000000003856f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347c9e0_0 .net8 "VPWR", 0 0, L_0000000003856f60; 1 drivers, strength-aware
+v000000000347cc60_0 .net "Y", 0 0, L_0000000003922a10; alias, 1 drivers
+v000000000347e380_0 .net "nor0_out_Y", 0 0, L_0000000003921900; 1 drivers
+S_000000000349e660 .scope module, "_312_" "sky130_fd_sc_hd__nor2_2" 3 772, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347dde0_0 .net "A", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000347d8e0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_0000000003857820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347c6c0_0 .net8 "VGND", 0 0, L_0000000003857820; 1 drivers, strength-aware
+L_0000000003857890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347de80_0 .net8 "VNB", 0 0, L_0000000003857890; 1 drivers, strength-aware
+L_0000000003856fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347e100_0 .net8 "VPB", 0 0, L_0000000003856fd0; 1 drivers, strength-aware
+L_00000000038570b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347e560_0 .net8 "VPWR", 0 0, L_00000000038570b0; 1 drivers, strength-aware
+v000000000347e600_0 .net "Y", 0 0, L_00000000039223f0; 1 drivers
+S_000000000349f6e0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_000000000349e660;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003921a50 .functor NOR 1, L_0000000003927470, L_000000000391d840, C4<0>, C4<0>;
+L_00000000039223f0 .functor BUF 1, L_0000000003921a50, C4<0>, C4<0>, C4<0>;
+v000000000347e4c0_0 .net "A", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000347cbc0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_0000000003857900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347d0c0_0 .net8 "VGND", 0 0, L_0000000003857900; 1 drivers, strength-aware
+L_0000000003857970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347ea60_0 .net8 "VNB", 0 0, L_0000000003857970; 1 drivers, strength-aware
+L_00000000038579e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347c800_0 .net8 "VPB", 0 0, L_00000000038579e0; 1 drivers, strength-aware
+L_0000000003857a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347dac0_0 .net8 "VPWR", 0 0, L_0000000003857a50; 1 drivers, strength-aware
+v000000000347d2a0_0 .net "Y", 0 0, L_00000000039223f0; alias, 1 drivers
+v000000000347db60_0 .net "nor0_out_Y", 0 0, L_0000000003921a50; 1 drivers
+S_00000000034a0760 .scope module, "_313_" "sky130_fd_sc_hd__nor2_2" 3 777, 4 30285 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v000000000347c580_0 .net "A", 0 0, L_0000000003927a90; alias, 1 drivers
+v000000000347c620_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_0000000003857ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347f820_0 .net8 "VGND", 0 0, L_0000000003857ac0; 1 drivers, strength-aware
+L_0000000003857b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347f000_0 .net8 "VNB", 0 0, L_0000000003857b30; 1 drivers, strength-aware
+L_0000000003857c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347eec0_0 .net8 "VPB", 0 0, L_0000000003857c10; 1 drivers, strength-aware
+L_000000000385f600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003480e00_0 .net8 "VPWR", 0 0, L_000000000385f600; 1 drivers, strength-aware
+v000000000347f320_0 .net "Y", 0 0, L_00000000039228c0; 1 drivers
+S_00000000034a05e0 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000034a0760;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003922460 .functor NOR 1, L_0000000003927a90, L_000000000391d840, C4<0>, C4<0>;
+L_00000000039228c0 .functor BUF 1, L_0000000003922460, C4<0>, C4<0>, C4<0>;
+v000000000347d3e0_0 .net "A", 0 0, L_0000000003927a90; alias, 1 drivers
+v000000000347e6a0_0 .net "B", 0 0, L_000000000391d840; alias, 1 drivers
+L_000000000385eb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347e7e0_0 .net8 "VGND", 0 0, L_000000000385eb80; 1 drivers, strength-aware
+L_000000000385f1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347e880_0 .net8 "VNB", 0 0, L_000000000385f1a0; 1 drivers, strength-aware
+L_000000000385e9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347eb00_0 .net8 "VPB", 0 0, L_000000000385e9c0; 1 drivers, strength-aware
+L_000000000385e640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347eba0_0 .net8 "VPWR", 0 0, L_000000000385e640; 1 drivers, strength-aware
+v000000000347ec40_0 .net "Y", 0 0, L_00000000039228c0; alias, 1 drivers
+v000000000347ece0_0 .net "nor0_out_Y", 0 0, L_0000000003922460; 1 drivers
+S_000000000349f0e0 .scope module, "_314_" "sky130_fd_sc_hd__conb_1" 3 782, 4 20862 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v0000000003480860_0 .net8 "HI", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_00000000039247d0 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+v000000000347fbe0_0 .net8 "LO", 0 0, L_00000000039247d0; 1 drivers, strength-aware
+L_000000000385fb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480040_0 .net8 "VGND", 0 0, L_000000000385fb40; 1 drivers, strength-aware
+L_000000000385eaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480540_0 .net8 "VNB", 0 0, L_000000000385eaa0; 1 drivers, strength-aware
+L_000000000385e870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f0a0_0 .net8 "VPB", 0 0, L_000000000385e870; 1 drivers, strength-aware
+L_000000000385e800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481080_0 .net8 "VPWR", 0 0, L_000000000385e800; 1 drivers, strength-aware
+S_000000000349bde0 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_000000000349f0e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v000000000347f3c0_0 .net8 "HI", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+v000000000347f460_0 .net8 "LO", 0 0, L_00000000039247d0; alias, 1 drivers, strength-aware
+L_000000000385f6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347f500_0 .net8 "VGND", 0 0, L_000000000385f6e0; 1 drivers, strength-aware
+L_000000000385e6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034811c0_0 .net8 "VNB", 0 0, L_000000000385e6b0; 1 drivers, strength-aware
+L_000000000385ea30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f5a0_0 .net8 "VPB", 0 0, L_000000000385ea30; 1 drivers, strength-aware
+L_000000000385ec60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003480c20_0 .net8 "VPWR", 0 0, L_000000000385ec60; 1 drivers, strength-aware
+S_000000000349b7e0 .scope module, "_315_" "sky130_fd_sc_hd__conb_1" 3 785, 4 20862 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+L_0000000003923ce0 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v000000000347f640_0 .net8 "HI", 0 0, L_0000000003923ce0; 1 drivers, strength-aware
+v000000000347ffa0_0 .net8 "LO", 0 0, L_0000000003924140; 1 drivers, strength-aware
+L_000000000385ed40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480ea0_0 .net8 "VGND", 0 0, L_000000000385ed40; 1 drivers, strength-aware
+L_000000000385f130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480f40_0 .net8 "VNB", 0 0, L_000000000385f130; 1 drivers, strength-aware
+L_000000000385ebf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347ed80_0 .net8 "VPB", 0 0, L_000000000385ebf0; 1 drivers, strength-aware
+L_000000000385e3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f6e0_0 .net8 "VPWR", 0 0, L_000000000385e3a0; 1 drivers, strength-aware
+S_000000000349cfe0 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_000000000349b7e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v000000000347f140_0 .net8 "HI", 0 0, L_0000000003923ce0; alias, 1 drivers, strength-aware
+v00000000034809a0_0 .net8 "LO", 0 0, L_0000000003924140; alias, 1 drivers, strength-aware
+L_000000000385fbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347ef60_0 .net8 "VGND", 0 0, L_000000000385fbb0; 1 drivers, strength-aware
+L_000000000385e8e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003481440_0 .net8 "VNB", 0 0, L_000000000385e8e0; 1 drivers, strength-aware
+L_000000000385f520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347fc80_0 .net8 "VPB", 0 0, L_000000000385f520; 1 drivers, strength-aware
+L_000000000385e090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f780_0 .net8 "VPWR", 0 0, L_000000000385e090; 1 drivers, strength-aware
+S_000000000349ede0 .scope module, "_316_" "sky130_fd_sc_hd__conb_1" 3 788, 4 20862 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+L_0000000003923a40 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v000000000347fd20_0 .net8 "HI", 0 0, L_0000000003923a40; 1 drivers, strength-aware
+v000000000347f280_0 .net8 "LO", 0 0, L_00000000039238f0; 1 drivers, strength-aware
+L_000000000385f590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034805e0_0 .net8 "VGND", 0 0, L_000000000385f590; 1 drivers, strength-aware
+L_000000000385eb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347faa0_0 .net8 "VNB", 0 0, L_000000000385eb10; 1 drivers, strength-aware
+L_000000000385f910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f1e0_0 .net8 "VPB", 0 0, L_000000000385f910; 1 drivers, strength-aware
+L_000000000385e2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347f960_0 .net8 "VPWR", 0 0, L_000000000385e2c0; 1 drivers, strength-aware
+S_000000000349c6e0 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_000000000349ede0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v0000000003480a40_0 .net8 "HI", 0 0, L_0000000003923a40; alias, 1 drivers, strength-aware
+v0000000003480fe0_0 .net8 "LO", 0 0, L_00000000039238f0; alias, 1 drivers, strength-aware
+L_000000000385ecd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347f8c0_0 .net8 "VGND", 0 0, L_000000000385ecd0; 1 drivers, strength-aware
+L_000000000385e100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480ae0_0 .net8 "VNB", 0 0, L_000000000385e100; 1 drivers, strength-aware
+L_000000000385e720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003480900_0 .net8 "VPB", 0 0, L_000000000385e720; 1 drivers, strength-aware
+L_000000000385f670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347fe60_0 .net8 "VPWR", 0 0, L_000000000385f670; 1 drivers, strength-aware
+S_000000000349cb60 .scope module, "_317_" "sky130_fd_sc_hd__conb_1" 3 791, 4 20862 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+L_00000000039244c0 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v00000000034800e0_0 .net8 "HI", 0 0, L_00000000039244c0; 1 drivers, strength-aware
+v0000000003480180_0 .net8 "LO", 0 0, L_0000000003923f10; 1 drivers, strength-aware
+L_000000000385edb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480680_0 .net8 "VGND", 0 0, L_000000000385edb0; 1 drivers, strength-aware
+L_000000000385f210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480b80_0 .net8 "VNB", 0 0, L_000000000385f210; 1 drivers, strength-aware
+L_000000000385ee20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003480cc0_0 .net8 "VPB", 0 0, L_000000000385ee20; 1 drivers, strength-aware
+L_000000000385ee90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003480220_0 .net8 "VPWR", 0 0, L_000000000385ee90; 1 drivers, strength-aware
+S_000000000349b1e0 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_000000000349cb60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v000000000347fa00_0 .net8 "HI", 0 0, L_00000000039244c0; alias, 1 drivers, strength-aware
+v000000000347fb40_0 .net8 "LO", 0 0, L_0000000003923f10; alias, 1 drivers, strength-aware
+L_000000000385e5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034802c0_0 .net8 "VGND", 0 0, L_000000000385e5d0; 1 drivers, strength-aware
+L_000000000385e480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000347fdc0_0 .net8 "VNB", 0 0, L_000000000385e480; 1 drivers, strength-aware
+L_000000000385f050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481120_0 .net8 "VPB", 0 0, L_000000000385f050; 1 drivers, strength-aware
+L_000000000385f360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347ff00_0 .net8 "VPWR", 0 0, L_000000000385f360; 1 drivers, strength-aware
+S_000000000349cce0 .scope module, "_318_" "sky130_fd_sc_hd__conb_1" 3 794, 4 20862 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+L_0000000003924c30 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v00000000034813a0_0 .net8 "HI", 0 0, L_0000000003924c30; 1 drivers, strength-aware
+v0000000003480720_0 .net8 "LO", 0 0, L_0000000003923ab0; 1 drivers, strength-aware
+L_000000000385e790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034807c0_0 .net8 "VGND", 0 0, L_000000000385e790; 1 drivers, strength-aware
+L_000000000385fc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034814e0_0 .net8 "VNB", 0 0, L_000000000385fc20; 1 drivers, strength-aware
+L_000000000385e950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000347ee20_0 .net8 "VPB", 0 0, L_000000000385e950; 1 drivers, strength-aware
+L_000000000385ef00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481b20_0 .net8 "VPWR", 0 0, L_000000000385ef00; 1 drivers, strength-aware
+S_000000000349e060 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_000000000349cce0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v0000000003480360_0 .net8 "HI", 0 0, L_0000000003924c30; alias, 1 drivers, strength-aware
+v0000000003480d60_0 .net8 "LO", 0 0, L_0000000003923ab0; alias, 1 drivers, strength-aware
+L_000000000385f980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003480400_0 .net8 "VGND", 0 0, L_000000000385f980; 1 drivers, strength-aware
+L_000000000385f9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003481260_0 .net8 "VNB", 0 0, L_000000000385f9f0; 1 drivers, strength-aware
+L_000000000385e560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034804a0_0 .net8 "VPB", 0 0, L_000000000385e560; 1 drivers, strength-aware
+L_000000000385e410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481300_0 .net8 "VPWR", 0 0, L_000000000385e410; 1 drivers, strength-aware
+S_00000000034a08e0 .scope module, "_319_" "sky130_fd_sc_hd__buf_2" 3 797, 4 81354 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+v0000000003482160_0 .net "A", 0 0, L_000000000380c1a0; 1 drivers
+L_000000000385ef70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482de0_0 .net8 "VGND", 0 0, L_000000000385ef70; 1 drivers, strength-aware
+L_000000000385efe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003483880_0 .net8 "VNB", 0 0, L_000000000385efe0; 1 drivers, strength-aware
+L_000000000385f0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003482c00_0 .net8 "VPB", 0 0, L_000000000385f0c0; 1 drivers, strength-aware
+L_000000000385f280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003483240_0 .net8 "VPWR", 0 0, L_000000000385f280; 1 drivers, strength-aware
+v0000000003482660_0 .net "X", 0 0, L_0000000003923b20; 1 drivers
+S_000000000349d8e0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81368, 4 80948 1, S_00000000034a08e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003924ca0 .functor BUF 1, L_000000000380c1a0, C4<0>, C4<0>, C4<0>;
+L_0000000003923b20 .functor BUF 1, L_0000000003924ca0, C4<0>, C4<0>, C4<0>;
+v0000000003481a80_0 .net "A", 0 0, L_000000000380c1a0; alias, 1 drivers
+L_000000000385f2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003483ce0_0 .net8 "VGND", 0 0, L_000000000385f2f0; 1 drivers, strength-aware
+L_000000000385f3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482520_0 .net8 "VNB", 0 0, L_000000000385f3d0; 1 drivers, strength-aware
+L_000000000385f440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003483c40_0 .net8 "VPB", 0 0, L_000000000385f440; 1 drivers, strength-aware
+L_000000000385f4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481d00_0 .net8 "VPWR", 0 0, L_000000000385f4b0; 1 drivers, strength-aware
+v0000000003482ac0_0 .net "X", 0 0, L_0000000003923b20; alias, 1 drivers
+v0000000003481e40_0 .net "buf0_out_X", 0 0, L_0000000003924ca0; 1 drivers
+S_000000000349d5e0 .scope module, "_320_" "sky130_fd_sc_hd__mux2_1" 3 801, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034836a0_0 .net "A0", 0 0, L_000000000391d760; alias, 1 drivers
+v0000000003481620_0 .net "A1", 0 0, L_00000000039280b0; alias, 1 drivers
+v0000000003481c60_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000385f750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034825c0_0 .net8 "VGND", 0 0, L_000000000385f750; 1 drivers, strength-aware
+L_000000000385f7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003483920_0 .net8 "VNB", 0 0, L_000000000385f7c0; 1 drivers, strength-aware
+L_000000000385fa60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003482fc0_0 .net8 "VPB", 0 0, L_000000000385fa60; 1 drivers, strength-aware
+L_000000000385fad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003482020_0 .net8 "VPWR", 0 0, L_000000000385fad0; 1 drivers, strength-aware
+v00000000034832e0_0 .net "X", 0 0, L_0000000003923500; alias, 1 drivers
+S_00000000034a0a60 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349d5e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+UDP_sky130_fd_sc_hd__udp_mux_2to1 .udp/comb "sky130_fd_sc_hd__udp_mux_2to1", 3
+ ,"00?0"
+ ,"11?1"
+ ,"0?00"
+ ,"1?01"
+ ,"?010"
+ ,"?111";
+L_0000000003924920 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391d760, L_00000000039280b0, L_000000000391eaa0;
+L_0000000003923500 .functor BUF 1, L_0000000003924920, C4<0>, C4<0>, C4<0>;
+v0000000003483740_0 .net "A0", 0 0, L_000000000391d760; alias, 1 drivers
+v0000000003483600_0 .net "A1", 0 0, L_00000000039280b0; alias, 1 drivers
+v0000000003482e80_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000385e170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003481580_0 .net8 "VGND", 0 0, L_000000000385e170; 1 drivers, strength-aware
+L_000000000385f830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034823e0_0 .net8 "VNB", 0 0, L_000000000385f830; 1 drivers, strength-aware
+L_000000000385f8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481f80_0 .net8 "VPB", 0 0, L_000000000385f8a0; 1 drivers, strength-aware
+L_000000000385e1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003482a20_0 .net8 "VPWR", 0 0, L_000000000385e1e0; 1 drivers, strength-aware
+v0000000003481ee0_0 .net "X", 0 0, L_0000000003923500; alias, 1 drivers
+v00000000034818a0_0 .net "mux_2to10_out_X", 0 0, L_0000000003924920; 1 drivers
+S_000000000349dd60 .scope module, "_321_" "sky130_fd_sc_hd__mux2_1" 3 807, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003483380_0 .net "A0", 0 0, L_0000000003923500; alias, 1 drivers
+v00000000034827a0_0 .net "A1", 0 0, L_000000000391df40; alias, 1 drivers
+v00000000034816c0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000385e250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482980_0 .net8 "VGND", 0 0, L_000000000385e250; 1 drivers, strength-aware
+L_000000000385e330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482840_0 .net8 "VNB", 0 0, L_000000000385e330; 1 drivers, strength-aware
+L_000000000385e4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003482200_0 .net8 "VPB", 0 0, L_000000000385e4f0; 1 drivers, strength-aware
+L_0000000003860860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034837e0_0 .net8 "VPWR", 0 0, L_0000000003860860; 1 drivers, strength-aware
+v0000000003481760_0 .net "X", 0 0, L_00000000039245a0; alias, 1 drivers
+S_000000000349c3e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349dd60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923e30 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923500, L_000000000391df40, L_0000000003920e80;
+L_00000000039245a0 .functor BUF 1, L_0000000003923e30, C4<0>, C4<0>, C4<0>;
+v00000000034822a0_0 .net "A0", 0 0, L_0000000003923500; alias, 1 drivers
+v00000000034820c0_0 .net "A1", 0 0, L_000000000391df40; alias, 1 drivers
+v0000000003482480_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003860240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482b60_0 .net8 "VGND", 0 0, L_0000000003860240; 1 drivers, strength-aware
+L_000000000385fd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482ca0_0 .net8 "VNB", 0 0, L_000000000385fd00; 1 drivers, strength-aware
+L_00000000038608d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003483ba0_0 .net8 "VPB", 0 0, L_00000000038608d0; 1 drivers, strength-aware
+L_00000000038602b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034828e0_0 .net8 "VPWR", 0 0, L_00000000038602b0; 1 drivers, strength-aware
+v0000000003481940_0 .net "X", 0 0, L_00000000039245a0; alias, 1 drivers
+v0000000003482700_0 .net "mux_2to10_out_X", 0 0, L_0000000003923e30; 1 drivers
+S_000000000349e1e0 .scope module, "_322_" "sky130_fd_sc_hd__mux2_1" 3 813, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034831a0_0 .net "A0", 0 0, L_0000000003922700; alias, 1 drivers
+v00000000034834c0_0 .net "A1", 0 0, L_00000000039245a0; alias, 1 drivers
+v0000000003483560_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_000000000385fd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003483b00_0 .net8 "VGND", 0 0, L_000000000385fd70; 1 drivers, strength-aware
+L_00000000038605c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003481800_0 .net8 "VNB", 0 0, L_00000000038605c0; 1 drivers, strength-aware
+L_0000000003860320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481bc0_0 .net8 "VPB", 0 0, L_0000000003860320; 1 drivers, strength-aware
+L_0000000003861740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003481da0_0 .net8 "VPWR", 0 0, L_0000000003861740; 1 drivers, strength-aware
+v0000000003485680_0 .net "X", 0 0, L_0000000003924290; 1 drivers
+S_000000000349e360 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349e1e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039237a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003922700, L_00000000039245a0, L_000000000391c730;
+L_0000000003924290 .functor BUF 1, L_00000000039237a0, C4<0>, C4<0>, C4<0>;
+v00000000034839c0_0 .net "A0", 0 0, L_0000000003922700; alias, 1 drivers
+v0000000003482d40_0 .net "A1", 0 0, L_00000000039245a0; alias, 1 drivers
+v0000000003483420_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_00000000038606a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482340_0 .net8 "VGND", 0 0, L_00000000038606a0; 1 drivers, strength-aware
+L_0000000003860470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003482f20_0 .net8 "VNB", 0 0, L_0000000003860470; 1 drivers, strength-aware
+L_0000000003860400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003483060_0 .net8 "VPB", 0 0, L_0000000003860400; 1 drivers, strength-aware
+L_00000000038612e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003483100_0 .net8 "VPWR", 0 0, L_00000000038612e0; 1 drivers, strength-aware
+v0000000003483a60_0 .net "X", 0 0, L_0000000003924290; alias, 1 drivers
+v00000000034819e0_0 .net "mux_2to10_out_X", 0 0, L_00000000039237a0; 1 drivers
+S_00000000034a0160 .scope module, "_323_" "sky130_fd_sc_hd__mux2_1" 3 819, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003484460_0 .net "A0", 0 0, L_000000000391c6c0; alias, 1 drivers
+v0000000003484d20_0 .net "A1", 0 0, L_000000000391dbc0; alias, 1 drivers
+v0000000003483f60_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003860390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034861c0_0 .net8 "VGND", 0 0, L_0000000003860390; 1 drivers, strength-aware
+L_0000000003860630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003484500_0 .net8 "VNB", 0 0, L_0000000003860630; 1 drivers, strength-aware
+L_0000000003860940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485c20_0 .net8 "VPB", 0 0, L_0000000003860940; 1 drivers, strength-aware
+L_00000000038609b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003484780_0 .net8 "VPWR", 0 0, L_00000000038609b0; 1 drivers, strength-aware
+v0000000003484e60_0 .net "X", 0 0, L_0000000003923ff0; alias, 1 drivers
+S_000000000349d2e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034a0160;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924990 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391c6c0, L_000000000391dbc0, L_000000000391eaa0;
+L_0000000003923ff0 .functor BUF 1, L_0000000003924990, C4<0>, C4<0>, C4<0>;
+v0000000003484820_0 .net "A0", 0 0, L_000000000391c6c0; alias, 1 drivers
+v0000000003484000_0 .net "A1", 0 0, L_000000000391dbc0; alias, 1 drivers
+v0000000003484aa0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003860d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003486300_0 .net8 "VGND", 0 0, L_0000000003860d30; 1 drivers, strength-aware
+L_00000000038607f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003486440_0 .net8 "VNB", 0 0, L_00000000038607f0; 1 drivers, strength-aware
+L_000000000385ffa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034846e0_0 .net8 "VPB", 0 0, L_000000000385ffa0; 1 drivers, strength-aware
+L_00000000038617b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034857c0_0 .net8 "VPWR", 0 0, L_00000000038617b0; 1 drivers, strength-aware
+v0000000003484140_0 .net "X", 0 0, L_0000000003923ff0; alias, 1 drivers
+v0000000003484320_0 .net "mux_2to10_out_X", 0 0, L_0000000003924990; 1 drivers
+S_000000000349dee0 .scope module, "_324_" "sky130_fd_sc_hd__mux2_1" 3 825, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034848c0_0 .net "A0", 0 0, L_0000000003923ff0; alias, 1 drivers
+v0000000003485220_0 .net "A1", 0 0, L_000000000391cc70; alias, 1 drivers
+v0000000003484960_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_00000000038604e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034841e0_0 .net8 "VGND", 0 0, L_00000000038604e0; 1 drivers, strength-aware
+L_0000000003861120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003485040_0 .net8 "VNB", 0 0, L_0000000003861120; 1 drivers, strength-aware
+L_000000000385fc90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485f40_0 .net8 "VPB", 0 0, L_000000000385fc90; 1 drivers, strength-aware
+L_0000000003861190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485540_0 .net8 "VPWR", 0 0, L_0000000003861190; 1 drivers, strength-aware
+v0000000003484b40_0 .net "X", 0 0, L_0000000003923b90; alias, 1 drivers
+S_000000000349e7e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349dee0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923c00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923ff0, L_000000000391cc70, L_0000000003920e80;
+L_0000000003923b90 .functor BUF 1, L_0000000003923c00, C4<0>, C4<0>, C4<0>;
+v0000000003484f00_0 .net "A0", 0 0, L_0000000003923ff0; alias, 1 drivers
+v0000000003485860_0 .net "A1", 0 0, L_000000000391cc70; alias, 1 drivers
+v0000000003485ea0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003860710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003484a00_0 .net8 "VGND", 0 0, L_0000000003860710; 1 drivers, strength-aware
+L_0000000003861510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003484fa0_0 .net8 "VNB", 0 0, L_0000000003861510; 1 drivers, strength-aware
+L_000000000385fec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034840a0_0 .net8 "VPB", 0 0, L_000000000385fec0; 1 drivers, strength-aware
+L_0000000003860a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485900_0 .net8 "VPWR", 0 0, L_0000000003860a20; 1 drivers, strength-aware
+v0000000003485e00_0 .net "X", 0 0, L_0000000003923b90; alias, 1 drivers
+v0000000003483ec0_0 .net "mux_2to10_out_X", 0 0, L_0000000003923c00; 1 drivers
+S_000000000349f260 .scope module, "_325_" "sky130_fd_sc_hd__mux2_1" 3 831, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034855e0_0 .net "A0", 0 0, L_0000000003923030; alias, 1 drivers
+v00000000034852c0_0 .net "A1", 0 0, L_0000000003923b90; alias, 1 drivers
+v0000000003484640_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_000000000385fde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003485360_0 .net8 "VGND", 0 0, L_000000000385fde0; 1 drivers, strength-aware
+L_0000000003860550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003485cc0_0 .net8 "VNB", 0 0, L_0000000003860550; 1 drivers, strength-aware
+L_0000000003861200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485400_0 .net8 "VPB", 0 0, L_0000000003861200; 1 drivers, strength-aware
+L_0000000003860780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486260_0 .net8 "VPWR", 0 0, L_0000000003860780; 1 drivers, strength-aware
+v0000000003485a40_0 .net "X", 0 0, L_0000000003924680; 1 drivers
+S_000000000349f3e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349f260;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039248b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923030, L_0000000003923b90, L_000000000391c730;
+L_0000000003924680 .functor BUF 1, L_00000000039248b0, C4<0>, C4<0>, C4<0>;
+v0000000003484dc0_0 .net "A0", 0 0, L_0000000003923030; alias, 1 drivers
+v00000000034850e0_0 .net "A1", 0 0, L_0000000003923b90; alias, 1 drivers
+v0000000003485180_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003860da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034843c0_0 .net8 "VGND", 0 0, L_0000000003860da0; 1 drivers, strength-aware
+L_0000000003860a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034845a0_0 .net8 "VNB", 0 0, L_0000000003860a90; 1 drivers, strength-aware
+L_0000000003860b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034859a0_0 .net8 "VPB", 0 0, L_0000000003860b00; 1 drivers, strength-aware
+L_00000000038601d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003484be0_0 .net8 "VPWR", 0 0, L_00000000038601d0; 1 drivers, strength-aware
+v0000000003484c80_0 .net "X", 0 0, L_0000000003924680; alias, 1 drivers
+v0000000003485720_0 .net "mux_2to10_out_X", 0 0, L_00000000039248b0; 1 drivers
+S_000000000349eae0 .scope module, "_326_" "sky130_fd_sc_hd__mux2_1" 3 837, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003486120_0 .net "A0", 0 0, L_000000000391ded0; alias, 1 drivers
+v00000000034864e0_0 .net "A1", 0 0, L_000000000391fbb0; alias, 1 drivers
+v0000000003483e20_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003860080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488c40_0 .net8 "VGND", 0 0, L_0000000003860080; 1 drivers, strength-aware
+L_0000000003860c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034873e0_0 .net8 "VNB", 0 0, L_0000000003860c50; 1 drivers, strength-aware
+L_0000000003860f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486f80_0 .net8 "VPB", 0 0, L_0000000003860f60; 1 drivers, strength-aware
+L_0000000003860b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487a20_0 .net8 "VPWR", 0 0, L_0000000003860b70; 1 drivers, strength-aware
+v0000000003486ee0_0 .net "X", 0 0, L_0000000003924d10; alias, 1 drivers
+S_000000000349f860 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349eae0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923f80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391ded0, L_000000000391fbb0, L_000000000391eaa0;
+L_0000000003924d10 .functor BUF 1, L_0000000003923f80, C4<0>, C4<0>, C4<0>;
+v00000000034854a0_0 .net "A0", 0 0, L_000000000391ded0; alias, 1 drivers
+v0000000003485ae0_0 .net "A1", 0 0, L_000000000391fbb0; alias, 1 drivers
+v0000000003485b80_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003861820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003484280_0 .net8 "VGND", 0 0, L_0000000003861820; 1 drivers, strength-aware
+L_0000000003860be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003483d80_0 .net8 "VNB", 0 0, L_0000000003860be0; 1 drivers, strength-aware
+L_0000000003860cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034863a0_0 .net8 "VPB", 0 0, L_0000000003860cc0; 1 drivers, strength-aware
+L_0000000003861580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003485d60_0 .net8 "VPWR", 0 0, L_0000000003861580; 1 drivers, strength-aware
+v0000000003485fe0_0 .net "X", 0 0, L_0000000003924d10; alias, 1 drivers
+v0000000003486080_0 .net "mux_2to10_out_X", 0 0, L_0000000003923f80; 1 drivers
+S_000000000349fe60 .scope module, "_327_" "sky130_fd_sc_hd__mux2_1" 3 843, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003487660_0 .net "A0", 0 0, L_0000000003924d10; alias, 1 drivers
+v00000000034870c0_0 .net "A1", 0 0, L_000000000391cf10; alias, 1 drivers
+v0000000003487160_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_00000000038615f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488ce0_0 .net8 "VGND", 0 0, L_00000000038615f0; 1 drivers, strength-aware
+L_0000000003860160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003486a80_0 .net8 "VNB", 0 0, L_0000000003860160; 1 drivers, strength-aware
+L_0000000003860010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487de0_0 .net8 "VPB", 0 0, L_0000000003860010; 1 drivers, strength-aware
+L_0000000003860e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487200_0 .net8 "VPWR", 0 0, L_0000000003860e10; 1 drivers, strength-aware
+v0000000003486b20_0 .net "X", 0 0, L_0000000003924a00; alias, 1 drivers
+S_000000000349d460 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349fe60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923570 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003924d10, L_000000000391cf10, L_0000000003920e80;
+L_0000000003924a00 .functor BUF 1, L_0000000003923570, C4<0>, C4<0>, C4<0>;
+v00000000034869e0_0 .net "A0", 0 0, L_0000000003924d10; alias, 1 drivers
+v0000000003488920_0 .net "A1", 0 0, L_000000000391cf10; alias, 1 drivers
+v0000000003487fc0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003860e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003487020_0 .net8 "VGND", 0 0, L_0000000003860e80; 1 drivers, strength-aware
+L_0000000003860ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488240_0 .net8 "VNB", 0 0, L_0000000003860ef0; 1 drivers, strength-aware
+L_0000000003860fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034881a0_0 .net8 "VPB", 0 0, L_0000000003860fd0; 1 drivers, strength-aware
+L_0000000003861040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487340_0 .net8 "VPWR", 0 0, L_0000000003861040; 1 drivers, strength-aware
+v0000000003487840_0 .net "X", 0 0, L_0000000003924a00; alias, 1 drivers
+v0000000003486bc0_0 .net "mux_2to10_out_X", 0 0, L_0000000003923570; 1 drivers
+S_000000000349da60 .scope module, "_328_" "sky130_fd_sc_hd__mux2_1" 3 849, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003486c60_0 .net "A0", 0 0, L_0000000003923180; alias, 1 drivers
+v0000000003487520_0 .net "A1", 0 0, L_0000000003924a00; alias, 1 drivers
+v0000000003486800_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_00000000038610b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488a60_0 .net8 "VGND", 0 0, L_00000000038610b0; 1 drivers, strength-aware
+L_0000000003861270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488880_0 .net8 "VNB", 0 0, L_0000000003861270; 1 drivers, strength-aware
+L_0000000003861350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486760_0 .net8 "VPB", 0 0, L_0000000003861350; 1 drivers, strength-aware
+L_00000000038613c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487700_0 .net8 "VPWR", 0 0, L_00000000038613c0; 1 drivers, strength-aware
+v00000000034877a0_0 .net "X", 0 0, L_0000000003924300; 1 drivers
+S_000000000349f9e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349da60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924060 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923180, L_0000000003924a00, L_000000000391c730;
+L_0000000003924300 .functor BUF 1, L_0000000003924060, C4<0>, C4<0>, C4<0>;
+v00000000034882e0_0 .net "A0", 0 0, L_0000000003923180; alias, 1 drivers
+v00000000034872a0_0 .net "A1", 0 0, L_0000000003924a00; alias, 1 drivers
+v0000000003488380_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003861430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034866c0_0 .net8 "VGND", 0 0, L_0000000003861430; 1 drivers, strength-aware
+L_0000000003861660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034875c0_0 .net8 "VNB", 0 0, L_0000000003861660; 1 drivers, strength-aware
+L_00000000038616d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003487480_0 .net8 "VPB", 0 0, L_00000000038616d0; 1 drivers, strength-aware
+L_000000000385fe50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034886a0_0 .net8 "VPWR", 0 0, L_000000000385fe50; 1 drivers, strength-aware
+v0000000003486620_0 .net "X", 0 0, L_0000000003924300; alias, 1 drivers
+v00000000034889c0_0 .net "mux_2to10_out_X", 0 0, L_0000000003924060; 1 drivers
+S_000000000349dbe0 .scope module, "_329_" "sky130_fd_sc_hd__mux2_1" 3 855, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034868a0_0 .net "A0", 0 0, L_000000000391ee20; alias, 1 drivers
+v0000000003486d00_0 .net "A1", 0 0, L_000000000391d3e0; alias, 1 drivers
+v0000000003488060_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038614a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003487c00_0 .net8 "VGND", 0 0, L_00000000038614a0; 1 drivers, strength-aware
+L_000000000385ff30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003487ca0_0 .net8 "VNB", 0 0, L_000000000385ff30; 1 drivers, strength-aware
+L_00000000038600f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486da0_0 .net8 "VPB", 0 0, L_00000000038600f0; 1 drivers, strength-aware
+L_0000000003861d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486e40_0 .net8 "VPWR", 0 0, L_0000000003861d60; 1 drivers, strength-aware
+v0000000003487d40_0 .net "X", 0 0, L_00000000039240d0; alias, 1 drivers
+S_000000000349bae0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349dbe0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924a70 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391ee20, L_000000000391d3e0, L_000000000391eaa0;
+L_00000000039240d0 .functor BUF 1, L_0000000003924a70, C4<0>, C4<0>, C4<0>;
+v0000000003488b00_0 .net "A0", 0 0, L_000000000391ee20; alias, 1 drivers
+v00000000034878e0_0 .net "A1", 0 0, L_000000000391d3e0; alias, 1 drivers
+v0000000003487980_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038624d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488420_0 .net8 "VGND", 0 0, L_00000000038624d0; 1 drivers, strength-aware
+L_00000000038633b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003487ac0_0 .net8 "VNB", 0 0, L_00000000038633b0; 1 drivers, strength-aware
+L_0000000003862310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003486940_0 .net8 "VPB", 0 0, L_0000000003862310; 1 drivers, strength-aware
+L_0000000003861f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034884c0_0 .net8 "VPWR", 0 0, L_0000000003861f20; 1 drivers, strength-aware
+v0000000003487b60_0 .net "X", 0 0, L_00000000039240d0; alias, 1 drivers
+v0000000003487e80_0 .net "mux_2to10_out_X", 0 0, L_0000000003924a70; 1 drivers
+S_000000000349c860 .scope module, "_330_" "sky130_fd_sc_hd__mux2_1" 3 861, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003489fa0_0 .net "A0", 0 0, L_00000000039240d0; alias, 1 drivers
+v0000000003488e20_0 .net "A1", 0 0, L_000000000391f670; alias, 1 drivers
+v000000000348af40_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003862e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a9a0_0 .net8 "VGND", 0 0, L_0000000003862e00; 1 drivers, strength-aware
+L_0000000003861c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a400_0 .net8 "VNB", 0 0, L_0000000003861c10; 1 drivers, strength-aware
+L_0000000003862930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a540_0 .net8 "VPB", 0 0, L_0000000003862930; 1 drivers, strength-aware
+L_00000000038629a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034890a0_0 .net8 "VPWR", 0 0, L_00000000038629a0; 1 drivers, strength-aware
+v000000000348b3a0_0 .net "X", 0 0, L_0000000003924fb0; alias, 1 drivers
+S_000000000349bc60 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349c860;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924760 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039240d0, L_000000000391f670, L_0000000003920e80;
+L_0000000003924fb0 .functor BUF 1, L_0000000003924760, C4<0>, C4<0>, C4<0>;
+v0000000003487f20_0 .net "A0", 0 0, L_00000000039240d0; alias, 1 drivers
+v0000000003488100_0 .net "A1", 0 0, L_000000000391f670; alias, 1 drivers
+v0000000003488560_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003861a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488ba0_0 .net8 "VGND", 0 0, L_0000000003861a50; 1 drivers, strength-aware
+L_0000000003861f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488600_0 .net8 "VNB", 0 0, L_0000000003861f90; 1 drivers, strength-aware
+L_0000000003861890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003488740_0 .net8 "VPB", 0 0, L_0000000003861890; 1 drivers, strength-aware
+L_0000000003861900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034887e0_0 .net8 "VPWR", 0 0, L_0000000003861900; 1 drivers, strength-aware
+v0000000003486580_0 .net "X", 0 0, L_0000000003924fb0; alias, 1 drivers
+v000000000348a860_0 .net "mux_2to10_out_X", 0 0, L_0000000003924760; 1 drivers
+S_000000000349c260 .scope module, "_331_" "sky130_fd_sc_hd__mux2_1" 3 867, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003489640_0 .net "A0", 0 0, L_0000000003921e40; alias, 1 drivers
+v000000000348b260_0 .net "A1", 0 0, L_0000000003924fb0; alias, 1 drivers
+v000000000348b4e0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003862af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489e60_0 .net8 "VGND", 0 0, L_0000000003862af0; 1 drivers, strength-aware
+L_0000000003861ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489820_0 .net8 "VNB", 0 0, L_0000000003861ac0; 1 drivers, strength-aware
+L_0000000003862a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003489c80_0 .net8 "VPB", 0 0, L_0000000003862a10; 1 drivers, strength-aware
+L_0000000003862c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a220_0 .net8 "VPWR", 0 0, L_0000000003862c40; 1 drivers, strength-aware
+v000000000348a4a0_0 .net "X", 0 0, L_0000000003924f40; 1 drivers
+S_000000000349e4e0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349c260;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925090 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003921e40, L_0000000003924fb0, L_000000000391c730;
+L_0000000003924f40 .functor BUF 1, L_0000000003925090, C4<0>, C4<0>, C4<0>;
+v000000000348ae00_0 .net "A0", 0 0, L_0000000003921e40; alias, 1 drivers
+v000000000348ab80_0 .net "A1", 0 0, L_0000000003924fb0; alias, 1 drivers
+v00000000034891e0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003861dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a720_0 .net8 "VGND", 0 0, L_0000000003861dd0; 1 drivers, strength-aware
+L_0000000003861e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a7c0_0 .net8 "VNB", 0 0, L_0000000003861e40; 1 drivers, strength-aware
+L_0000000003861c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034895a0_0 .net8 "VPB", 0 0, L_0000000003861c80; 1 drivers, strength-aware
+L_0000000003863180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348ac20_0 .net8 "VPWR", 0 0, L_0000000003863180; 1 drivers, strength-aware
+v0000000003489d20_0 .net "X", 0 0, L_0000000003924f40; alias, 1 drivers
+v000000000348aa40_0 .net "mux_2to10_out_X", 0 0, L_0000000003925090; 1 drivers
+S_000000000349bf60 .scope module, "_332_" "sky130_fd_sc_hd__mux2_1" 3 873, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003489000_0 .net "A0", 0 0, L_00000000039280b0; alias, 1 drivers
+v000000000348b440_0 .net "A1", 0 0, L_000000000391e3a0; alias, 1 drivers
+v0000000003489aa0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038625b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489320_0 .net8 "VGND", 0 0, L_00000000038625b0; 1 drivers, strength-aware
+L_0000000003862850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489b40_0 .net8 "VNB", 0 0, L_0000000003862850; 1 drivers, strength-aware
+L_0000000003863110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034893c0_0 .net8 "VPB", 0 0, L_0000000003863110; 1 drivers, strength-aware
+L_0000000003862a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a900_0 .net8 "VPWR", 0 0, L_0000000003862a80; 1 drivers, strength-aware
+v0000000003489f00_0 .net "X", 0 0, L_0000000003923810; alias, 1 drivers
+S_000000000349ec60 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349bf60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924d80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039280b0, L_000000000391e3a0, L_000000000391eaa0;
+L_0000000003923810 .functor BUF 1, L_0000000003924d80, C4<0>, C4<0>, C4<0>;
+v000000000348a5e0_0 .net "A0", 0 0, L_00000000039280b0; alias, 1 drivers
+v0000000003489dc0_0 .net "A1", 0 0, L_000000000391e3a0; alias, 1 drivers
+v000000000348aae0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003863260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a680_0 .net8 "VGND", 0 0, L_0000000003863260; 1 drivers, strength-aware
+L_0000000003861cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489140_0 .net8 "VNB", 0 0, L_0000000003861cf0; 1 drivers, strength-aware
+L_00000000038631f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a2c0_0 .net8 "VPB", 0 0, L_00000000038631f0; 1 drivers, strength-aware
+L_0000000003861970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003489a00_0 .net8 "VPWR", 0 0, L_0000000003861970; 1 drivers, strength-aware
+v000000000348acc0_0 .net "X", 0 0, L_0000000003923810; alias, 1 drivers
+v00000000034898c0_0 .net "mux_2to10_out_X", 0 0, L_0000000003924d80; 1 drivers
+S_000000000349fb60 .scope module, "_333_" "sky130_fd_sc_hd__mux2_1" 3 879, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348a0e0_0 .net "A0", 0 0, L_0000000003923810; alias, 1 drivers
+v0000000003489280_0 .net "A1", 0 0, L_000000000391f360; alias, 1 drivers
+v000000000348b080_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003861b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488d80_0 .net8 "VGND", 0 0, L_0000000003861b30; 1 drivers, strength-aware
+L_0000000003862000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348a180_0 .net8 "VNB", 0 0, L_0000000003862000; 1 drivers, strength-aware
+L_0000000003862070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a360_0 .net8 "VPB", 0 0, L_0000000003862070; 1 drivers, strength-aware
+L_0000000003862cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348b1c0_0 .net8 "VPWR", 0 0, L_0000000003862cb0; 1 drivers, strength-aware
+v000000000348b300_0 .net "X", 0 0, L_0000000003923c70; alias, 1 drivers
+S_000000000349fce0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349fb60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039235e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923810, L_000000000391f360, L_0000000003920e80;
+L_0000000003923c70 .functor BUF 1, L_00000000039235e0, C4<0>, C4<0>, C4<0>;
+v000000000348ad60_0 .net "A0", 0 0, L_0000000003923810; alias, 1 drivers
+v00000000034896e0_0 .net "A1", 0 0, L_000000000391f360; alias, 1 drivers
+v000000000348b120_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003862b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003489960_0 .net8 "VGND", 0 0, L_0000000003862b60; 1 drivers, strength-aware
+L_0000000003862d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348aea0_0 .net8 "VNB", 0 0, L_0000000003862d20; 1 drivers, strength-aware
+L_0000000003862690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348afe0_0 .net8 "VPB", 0 0, L_0000000003862690; 1 drivers, strength-aware
+L_00000000038620e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348a040_0 .net8 "VPWR", 0 0, L_00000000038620e0; 1 drivers, strength-aware
+v0000000003489be0_0 .net "X", 0 0, L_0000000003923c70; alias, 1 drivers
+v0000000003489500_0 .net "mux_2to10_out_X", 0 0, L_00000000039235e0; 1 drivers
+S_00000000034a0be0 .scope module, "_334_" "sky130_fd_sc_hd__mux2_1" 3 885, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348d920_0 .net "A0", 0 0, L_0000000003923420; alias, 1 drivers
+v000000000348cde0_0 .net "A1", 0 0, L_0000000003923c70; alias, 1 drivers
+v000000000348c840_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003861eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348cfc0_0 .net8 "VGND", 0 0, L_0000000003861eb0; 1 drivers, strength-aware
+L_0000000003862150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348cc00_0 .net8 "VNB", 0 0, L_0000000003862150; 1 drivers, strength-aware
+L_00000000038619e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348b580_0 .net8 "VPB", 0 0, L_00000000038619e0; 1 drivers, strength-aware
+L_00000000038623f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c660_0 .net8 "VPWR", 0 0, L_00000000038623f0; 1 drivers, strength-aware
+v000000000348bee0_0 .net "X", 0 0, L_0000000003923650; 1 drivers
+S_000000000349ffe0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034a0be0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923d50 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003923420, L_0000000003923c70, L_000000000391c730;
+L_0000000003923650 .functor BUF 1, L_0000000003923d50, C4<0>, C4<0>, C4<0>;
+v0000000003489460_0 .net "A0", 0 0, L_0000000003923420; alias, 1 drivers
+v0000000003488ec0_0 .net "A1", 0 0, L_0000000003923c70; alias, 1 drivers
+v0000000003489780_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003862460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003488f60_0 .net8 "VGND", 0 0, L_0000000003862460; 1 drivers, strength-aware
+L_00000000038621c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348cac0_0 .net8 "VNB", 0 0, L_00000000038621c0; 1 drivers, strength-aware
+L_0000000003862bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348d9c0_0 .net8 "VPB", 0 0, L_0000000003862bd0; 1 drivers, strength-aware
+L_00000000038628c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c520_0 .net8 "VPWR", 0 0, L_00000000038628c0; 1 drivers, strength-aware
+v000000000348cd40_0 .net "X", 0 0, L_0000000003923650; alias, 1 drivers
+v000000000348cb60_0 .net "mux_2to10_out_X", 0 0, L_0000000003923d50; 1 drivers
+S_00000000034a02e0 .scope module, "_335_" "sky130_fd_sc_hd__mux2_1" 3 891, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348dc40_0 .net "A0", 0 0, L_000000000391fad0; alias, 1 drivers
+v000000000348c3e0_0 .net "A1", 0 0, L_000000000391e790; alias, 1 drivers
+v000000000348bda0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003862230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348c700_0 .net8 "VGND", 0 0, L_0000000003862230; 1 drivers, strength-aware
+L_0000000003861ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348ce80_0 .net8 "VNB", 0 0, L_0000000003861ba0; 1 drivers, strength-aware
+L_0000000003862d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348b8a0_0 .net8 "VPB", 0 0, L_0000000003862d90; 1 drivers, strength-aware
+L_00000000038622a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c8e0_0 .net8 "VPWR", 0 0, L_00000000038622a0; 1 drivers, strength-aware
+v000000000348d7e0_0 .net "X", 0 0, L_0000000003924df0; alias, 1 drivers
+S_00000000034a0460 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034a02e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924e60 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391fad0, L_000000000391e790, L_0000000003920e80;
+L_0000000003924df0 .functor BUF 1, L_0000000003924e60, C4<0>, C4<0>, C4<0>;
+v000000000348cca0_0 .net "A0", 0 0, L_000000000391fad0; alias, 1 drivers
+v000000000348b620_0 .net "A1", 0 0, L_000000000391e790; alias, 1 drivers
+v000000000348da60_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003862380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348bc60_0 .net8 "VGND", 0 0, L_0000000003862380; 1 drivers, strength-aware
+L_0000000003862540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348ca20_0 .net8 "VNB", 0 0, L_0000000003862540; 1 drivers, strength-aware
+L_0000000003862620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c980_0 .net8 "VPB", 0 0, L_0000000003862620; 1 drivers, strength-aware
+L_0000000003862700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c7a0_0 .net8 "VPWR", 0 0, L_0000000003862700; 1 drivers, strength-aware
+v000000000348b6c0_0 .net "X", 0 0, L_0000000003924df0; alias, 1 drivers
+v000000000348d740_0 .net "mux_2to10_out_X", 0 0, L_0000000003924e60; 1 drivers
+S_00000000034a0d60 .scope module, "_336_" "sky130_fd_sc_hd__mux2_1" 3 897, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348cf20_0 .net "A0", 0 0, L_0000000003922b60; alias, 1 drivers
+v000000000348d1a0_0 .net "A1", 0 0, L_0000000003924df0; alias, 1 drivers
+v000000000348d2e0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003862770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348c160_0 .net8 "VGND", 0 0, L_0000000003862770; 1 drivers, strength-aware
+L_0000000003862e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348bb20_0 .net8 "VNB", 0 0, L_0000000003862e70; 1 drivers, strength-aware
+L_00000000038627e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348c480_0 .net8 "VPB", 0 0, L_00000000038627e0; 1 drivers, strength-aware
+L_0000000003862ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348d380_0 .net8 "VPWR", 0 0, L_0000000003862ee0; 1 drivers, strength-aware
+v000000000348c200_0 .net "X", 0 0, L_0000000003924450; 1 drivers
+S_00000000034a0ee0 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034a0d60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925020 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003922b60, L_0000000003924df0, L_000000000391c730;
+L_0000000003924450 .functor BUF 1, L_0000000003925020, C4<0>, C4<0>, C4<0>;
+v000000000348d060_0 .net "A0", 0 0, L_0000000003922b60; alias, 1 drivers
+v000000000348d420_0 .net "A1", 0 0, L_0000000003924df0; alias, 1 drivers
+v000000000348c5c0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003862f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348b800_0 .net8 "VGND", 0 0, L_0000000003862f50; 1 drivers, strength-aware
+L_0000000003862fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348db00_0 .net8 "VNB", 0 0, L_0000000003862fc0; 1 drivers, strength-aware
+L_0000000003863030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348bd00_0 .net8 "VPB", 0 0, L_0000000003863030; 1 drivers, strength-aware
+L_00000000038630a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348d240_0 .net8 "VPWR", 0 0, L_00000000038630a0; 1 drivers, strength-aware
+v000000000348d100_0 .net "X", 0 0, L_0000000003924450; alias, 1 drivers
+v000000000348c2a0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925020; 1 drivers
+S_000000000349b060 .scope module, "_337_" "sky130_fd_sc_hd__mux2_1" 3 903, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348dba0_0 .net "A0", 0 0, L_000000000391ec60; alias, 1 drivers
+v000000000348dce0_0 .net "A1", 0 0, L_000000000391fb40; alias, 1 drivers
+v000000000348b940_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003863420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348b9e0_0 .net8 "VGND", 0 0, L_0000000003863420; 1 drivers, strength-aware
+L_00000000038632d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348c340_0 .net8 "VNB", 0 0, L_00000000038632d0; 1 drivers, strength-aware
+L_0000000003863340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348ba80_0 .net8 "VPB", 0 0, L_0000000003863340; 1 drivers, strength-aware
+L_0000000003863e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348bbc0_0 .net8 "VPWR", 0 0, L_0000000003863e30; 1 drivers, strength-aware
+v000000000348c0c0_0 .net "X", 0 0, L_0000000003923ea0; alias, 1 drivers
+S_000000000349c560 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_000000000349b060;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923dc0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391ec60, L_000000000391fb40, L_0000000003920e80;
+L_0000000003923ea0 .functor BUF 1, L_0000000003923dc0, C4<0>, C4<0>, C4<0>;
+v000000000348d4c0_0 .net "A0", 0 0, L_000000000391ec60; alias, 1 drivers
+v000000000348d560_0 .net "A1", 0 0, L_000000000391fb40; alias, 1 drivers
+v000000000348c020_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003864ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348d6a0_0 .net8 "VGND", 0 0, L_0000000003864ae0; 1 drivers, strength-aware
+L_00000000038648b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348b760_0 .net8 "VNB", 0 0, L_00000000038648b0; 1 drivers, strength-aware
+L_0000000003864ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348d880_0 .net8 "VPB", 0 0, L_0000000003864ca0; 1 drivers, strength-aware
+L_0000000003864920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348be40_0 .net8 "VPWR", 0 0, L_0000000003864920; 1 drivers, strength-aware
+v000000000348d600_0 .net "X", 0 0, L_0000000003923ea0; alias, 1 drivers
+v000000000348bf80_0 .net "mux_2to10_out_X", 0 0, L_0000000003923dc0; 1 drivers
+S_00000000034cc880 .scope module, "_338_" "sky130_fd_sc_hd__mux2_1" 3 909, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348e3c0_0 .net "A0", 0 0, L_0000000003922a10; alias, 1 drivers
+v000000000348e000_0 .net "A1", 0 0, L_0000000003923ea0; alias, 1 drivers
+v000000000348dec0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_0000000003863f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348e460_0 .net8 "VGND", 0 0, L_0000000003863f10; 1 drivers, strength-aware
+L_0000000003864450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003490300_0 .net8 "VNB", 0 0, L_0000000003864450; 1 drivers, strength-aware
+L_00000000038641b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348f2c0_0 .net8 "VPB", 0 0, L_00000000038641b0; 1 drivers, strength-aware
+L_00000000038636c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348e780_0 .net8 "VPWR", 0 0, L_00000000038636c0; 1 drivers, strength-aware
+v000000000348f7c0_0 .net "X", 0 0, L_0000000003924370; 1 drivers
+S_00000000034cfd00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cc880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039241b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003922a10, L_0000000003923ea0, L_000000000391c730;
+L_0000000003924370 .functor BUF 1, L_00000000039241b0, C4<0>, C4<0>, C4<0>;
+v000000000348e320_0 .net "A0", 0 0, L_0000000003922a10; alias, 1 drivers
+v000000000348e960_0 .net "A1", 0 0, L_0000000003923ea0; alias, 1 drivers
+v000000000348fcc0_0 .net "S", 0 0, L_000000000391c730; alias, 1 drivers
+L_00000000038638f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348e6e0_0 .net8 "VGND", 0 0, L_00000000038638f0; 1 drivers, strength-aware
+L_0000000003864a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348f680_0 .net8 "VNB", 0 0, L_0000000003864a00; 1 drivers, strength-aware
+L_0000000003863ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348e8c0_0 .net8 "VPB", 0 0, L_0000000003863ce0; 1 drivers, strength-aware
+L_0000000003863d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348e280_0 .net8 "VPWR", 0 0, L_0000000003863d50; 1 drivers, strength-aware
+v000000000348ff40_0 .net "X", 0 0, L_0000000003924370; alias, 1 drivers
+v00000000034904e0_0 .net "mux_2to10_out_X", 0 0, L_00000000039241b0; 1 drivers
+S_00000000034cc100 .scope module, "_339_" "sky130_fd_sc_hd__mux2_1" 3 915, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348eaa0_0 .net "A0", 0 0, L_00000000039253a0; alias, 1 drivers
+v000000000348f860_0 .net "A1", 0 0, L_0000000003920780; alias, 1 drivers
+v0000000003490120_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348f5e0_0 .net8 "VGND", 0 0, L_0000000003864b50; 1 drivers, strength-aware
+L_0000000003864530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348f040_0 .net8 "VNB", 0 0, L_0000000003864530; 1 drivers, strength-aware
+L_0000000003863490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348f540_0 .net8 "VPB", 0 0, L_0000000003863490; 1 drivers, strength-aware
+L_0000000003863dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348e0a0_0 .net8 "VPWR", 0 0, L_0000000003863dc0; 1 drivers, strength-aware
+v000000000348dd80_0 .net "X", 0 0, L_0000000003923730; 1 drivers
+S_00000000034d0f00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cc100;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924220 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039253a0, L_0000000003920780, L_0000000003922930;
+L_0000000003923730 .functor BUF 1, L_0000000003924220, C4<0>, C4<0>, C4<0>;
+v00000000034901c0_0 .net "A0", 0 0, L_00000000039253a0; alias, 1 drivers
+v000000000348ed20_0 .net "A1", 0 0, L_0000000003920780; alias, 1 drivers
+v000000000348e500_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_00000000038645a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348e5a0_0 .net8 "VGND", 0 0, L_00000000038645a0; 1 drivers, strength-aware
+L_0000000003865020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348e640_0 .net8 "VNB", 0 0, L_0000000003865020; 1 drivers, strength-aware
+L_0000000003864610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348e820_0 .net8 "VPB", 0 0, L_0000000003864610; 1 drivers, strength-aware
+L_00000000038644c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348ea00_0 .net8 "VPWR", 0 0, L_00000000038644c0; 1 drivers, strength-aware
+v0000000003490260_0 .net "X", 0 0, L_0000000003923730; alias, 1 drivers
+v000000000348edc0_0 .net "mux_2to10_out_X", 0 0, L_0000000003924220; 1 drivers
+S_00000000034ce200 .scope module, "_340_" "sky130_fd_sc_hd__mux2_1" 3 921, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348ebe0_0 .net "A0", 0 0, L_0000000003921190; alias, 1 drivers
+v000000000348fb80_0 .net "A1", 0 0, L_000000000391ffa0; alias, 1 drivers
+v000000000348ec80_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348ee60_0 .net8 "VGND", 0 0, L_0000000003864fb0; 1 drivers, strength-aware
+L_0000000003863a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003490440_0 .net8 "VNB", 0 0, L_0000000003863a40; 1 drivers, strength-aware
+L_0000000003864300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348f900_0 .net8 "VPB", 0 0, L_0000000003864300; 1 drivers, strength-aware
+L_0000000003863ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348f0e0_0 .net8 "VPWR", 0 0, L_0000000003863ea0; 1 drivers, strength-aware
+v000000000348fa40_0 .net "X", 0 0, L_0000000003924b50; 1 drivers
+S_00000000034cbc80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034ce200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039243e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003921190, L_000000000391ffa0, L_0000000003922930;
+L_0000000003924b50 .functor BUF 1, L_00000000039243e0, C4<0>, C4<0>, C4<0>;
+v000000000348ffe0_0 .net "A0", 0 0, L_0000000003921190; alias, 1 drivers
+v000000000348fe00_0 .net "A1", 0 0, L_000000000391ffa0; alias, 1 drivers
+v000000000348f720_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003863500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348e140_0 .net8 "VGND", 0 0, L_0000000003863500; 1 drivers, strength-aware
+L_0000000003864370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034903a0_0 .net8 "VNB", 0 0, L_0000000003864370; 1 drivers, strength-aware
+L_0000000003864bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348ef00_0 .net8 "VPB", 0 0, L_0000000003864bc0; 1 drivers, strength-aware
+L_0000000003863f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348f220_0 .net8 "VPWR", 0 0, L_0000000003863f80; 1 drivers, strength-aware
+v000000000348eb40_0 .net "X", 0 0, L_0000000003924b50; alias, 1 drivers
+v000000000348efa0_0 .net "mux_2to10_out_X", 0 0, L_00000000039243e0; 1 drivers
+S_00000000034d0600 .scope module, "_341_" "sky130_fd_sc_hd__mux2_1" 3 927, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000348fd60_0 .net "A0", 0 0, L_0000000003920f60; alias, 1 drivers
+v000000000348fea0_0 .net "A1", 0 0, L_0000000003920ef0; alias, 1 drivers
+v000000000348df60_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003490080_0 .net8 "VGND", 0 0, L_0000000003864a70; 1 drivers, strength-aware
+L_0000000003863650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034912a0_0 .net8 "VNB", 0 0, L_0000000003863650; 1 drivers, strength-aware
+L_0000000003863730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003492240_0 .net8 "VPB", 0 0, L_0000000003863730; 1 drivers, strength-aware
+L_0000000003863ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034906c0_0 .net8 "VPWR", 0 0, L_0000000003863ff0; 1 drivers, strength-aware
+v00000000034915c0_0 .net "X", 0 0, L_00000000039236c0; 1 drivers
+S_00000000034cc400 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924530 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003920f60, L_0000000003920ef0, L_0000000003922930;
+L_00000000039236c0 .functor BUF 1, L_0000000003924530, C4<0>, C4<0>, C4<0>;
+v000000000348f180_0 .net "A0", 0 0, L_0000000003920f60; alias, 1 drivers
+v000000000348f360_0 .net "A1", 0 0, L_0000000003920ef0; alias, 1 drivers
+v000000000348f400_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348f4a0_0 .net8 "VGND", 0 0, L_0000000003864e60; 1 drivers, strength-aware
+L_0000000003864c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000348f9a0_0 .net8 "VNB", 0 0, L_0000000003864c30; 1 drivers, strength-aware
+L_00000000038640d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348de20_0 .net8 "VPB", 0 0, L_00000000038640d0; 1 drivers, strength-aware
+L_0000000003863810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000348fae0_0 .net8 "VPWR", 0 0, L_0000000003863810; 1 drivers, strength-aware
+v000000000348e1e0_0 .net "X", 0 0, L_00000000039236c0; alias, 1 drivers
+v000000000348fc20_0 .net "mux_2to10_out_X", 0 0, L_0000000003924530; 1 drivers
+S_00000000034cfb80 .scope module, "_342_" "sky130_fd_sc_hd__mux2_1" 3 933, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003490ee0_0 .net "A0", 0 0, L_0000000003921040; alias, 1 drivers
+v0000000003490f80_0 .net "A1", 0 0, L_0000000003920630; alias, 1 drivers
+v00000000034917a0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003492560_0 .net8 "VGND", 0 0, L_0000000003864f40; 1 drivers, strength-aware
+L_0000000003863c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003491a20_0 .net8 "VNB", 0 0, L_0000000003863c70; 1 drivers, strength-aware
+L_0000000003864d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003490bc0_0 .net8 "VPB", 0 0, L_0000000003864d10; 1 drivers, strength-aware
+L_00000000038643e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003491c00_0 .net8 "VPWR", 0 0, L_00000000038643e0; 1 drivers, strength-aware
+v0000000003490940_0 .net "X", 0 0, L_0000000003924610; 1 drivers
+S_00000000034cc580 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cfb80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039246f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003921040, L_0000000003920630, L_0000000003922930;
+L_0000000003924610 .functor BUF 1, L_00000000039246f0, C4<0>, C4<0>, C4<0>;
+v0000000003490b20_0 .net "A0", 0 0, L_0000000003921040; alias, 1 drivers
+v00000000034918e0_0 .net "A1", 0 0, L_0000000003920630; alias, 1 drivers
+v0000000003492920_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_00000000038646f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003491480_0 .net8 "VGND", 0 0, L_00000000038646f0; 1 drivers, strength-aware
+L_0000000003864680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003490760_0 .net8 "VNB", 0 0, L_0000000003864680; 1 drivers, strength-aware
+L_0000000003863b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003491660_0 .net8 "VPB", 0 0, L_0000000003863b90; 1 drivers, strength-aware
+L_0000000003864760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003491700_0 .net8 "VPWR", 0 0, L_0000000003864760; 1 drivers, strength-aware
+v0000000003491b60_0 .net "X", 0 0, L_0000000003924610; alias, 1 drivers
+v0000000003491e80_0 .net "mux_2to10_out_X", 0 0, L_00000000039246f0; 1 drivers
+S_00000000034ce980 .scope module, "_343_" "sky130_fd_sc_hd__mux2_1" 3 939, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003491980_0 .net "A0", 0 0, L_0000000003920b70; alias, 1 drivers
+v0000000003491ac0_0 .net "A1", 0 0, L_00000000039229a0; alias, 1 drivers
+v00000000034909e0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003491d40_0 .net8 "VGND", 0 0, L_0000000003864990; 1 drivers, strength-aware
+L_0000000003863570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003490a80_0 .net8 "VNB", 0 0, L_0000000003863570; 1 drivers, strength-aware
+L_00000000038637a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003490da0_0 .net8 "VPB", 0 0, L_00000000038637a0; 1 drivers, strength-aware
+L_00000000038635e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003491de0_0 .net8 "VPWR", 0 0, L_00000000038635e0; 1 drivers, strength-aware
+v0000000003491f20_0 .net "X", 0 0, L_0000000003924ae0; 1 drivers
+S_00000000034cbe00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034ce980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924840 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003920b70, L_00000000039229a0, L_0000000003922930;
+L_0000000003924ae0 .functor BUF 1, L_0000000003924840, C4<0>, C4<0>, C4<0>;
+v00000000034908a0_0 .net "A0", 0 0, L_0000000003920b70; alias, 1 drivers
+v0000000003492060_0 .net "A1", 0 0, L_00000000039229a0; alias, 1 drivers
+v0000000003491ca0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_00000000038647d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003491020_0 .net8 "VGND", 0 0, L_00000000038647d0; 1 drivers, strength-aware
+L_0000000003864d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003491840_0 .net8 "VNB", 0 0, L_0000000003864d80; 1 drivers, strength-aware
+L_0000000003863880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003490800_0 .net8 "VPB", 0 0, L_0000000003863880; 1 drivers, strength-aware
+L_0000000003864840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003490c60_0 .net8 "VPWR", 0 0, L_0000000003864840; 1 drivers, strength-aware
+v0000000003492b00_0 .net "X", 0 0, L_0000000003924ae0; alias, 1 drivers
+v0000000003492c40_0 .net "mux_2to10_out_X", 0 0, L_0000000003924840; 1 drivers
+S_00000000034d0180 .scope module, "_344_" "sky130_fd_sc_hd__mux2_1" 3 945, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003491340_0 .net "A0", 0 0, L_00000000039233b0; alias, 1 drivers
+v0000000003492100_0 .net "A1", 0 0, L_0000000003921970; alias, 1 drivers
+v00000000034921a0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034922e0_0 .net8 "VGND", 0 0, L_0000000003864060; 1 drivers, strength-aware
+L_0000000003864140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003492380_0 .net8 "VNB", 0 0, L_0000000003864140; 1 drivers, strength-aware
+L_0000000003863960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034924c0_0 .net8 "VPB", 0 0, L_0000000003863960; 1 drivers, strength-aware
+L_0000000003864df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003492ba0_0 .net8 "VPWR", 0 0, L_0000000003864df0; 1 drivers, strength-aware
+v0000000003492600_0 .net "X", 0 0, L_0000000003924bc0; 1 drivers
+S_00000000034cfe80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003924ed0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039233b0, L_0000000003921970, L_0000000003922930;
+L_0000000003924bc0 .functor BUF 1, L_0000000003924ed0, C4<0>, C4<0>, C4<0>;
+v0000000003490d00_0 .net "A0", 0 0, L_00000000039233b0; alias, 1 drivers
+v0000000003491fc0_0 .net "A1", 0 0, L_0000000003921970; alias, 1 drivers
+v0000000003490e40_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003864ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034910c0_0 .net8 "VGND", 0 0, L_0000000003864ed0; 1 drivers, strength-aware
+L_00000000038639d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003492420_0 .net8 "VNB", 0 0, L_00000000038639d0; 1 drivers, strength-aware
+L_0000000003863ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003491160_0 .net8 "VPB", 0 0, L_0000000003863ab0; 1 drivers, strength-aware
+L_0000000003864220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003490580_0 .net8 "VPWR", 0 0, L_0000000003864220; 1 drivers, strength-aware
+v0000000003491200_0 .net "X", 0 0, L_0000000003924bc0; alias, 1 drivers
+v0000000003491520_0 .net "mux_2to10_out_X", 0 0, L_0000000003924ed0; 1 drivers
+S_00000000034cd780 .scope module, "_345_" "sky130_fd_sc_hd__mux2_1" 3 951, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003493640_0 .net "A0", 0 0, L_0000000003922f50; alias, 1 drivers
+v00000000034942c0_0 .net "A1", 0 0, L_0000000003922e70; alias, 1 drivers
+v00000000034940e0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003863b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003493320_0 .net8 "VGND", 0 0, L_0000000003863b20; 1 drivers, strength-aware
+L_0000000003863c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003494540_0 .net8 "VNB", 0 0, L_0000000003863c00; 1 drivers, strength-aware
+L_0000000003864290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034949a0_0 .net8 "VPB", 0 0, L_0000000003864290; 1 drivers, strength-aware
+L_0000000003865410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003494b80_0 .net8 "VPWR", 0 0, L_0000000003865410; 1 drivers, strength-aware
+v0000000003493e60_0 .net "X", 0 0, L_0000000003923960; 1 drivers
+S_00000000034ce800 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cd780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003923880 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003922f50, L_0000000003922e70, L_0000000003922930;
+L_0000000003923960 .functor BUF 1, L_0000000003923880, C4<0>, C4<0>, C4<0>;
+v0000000003492ce0_0 .net "A0", 0 0, L_0000000003922f50; alias, 1 drivers
+v00000000034926a0_0 .net "A1", 0 0, L_0000000003922e70; alias, 1 drivers
+v00000000034913e0_0 .net8 "S", 0 0, L_0000000003922930; alias, 1 drivers, strength-aware
+L_0000000003865330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003492740_0 .net8 "VGND", 0 0, L_0000000003865330; 1 drivers, strength-aware
+L_0000000003865b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034927e0_0 .net8 "VNB", 0 0, L_0000000003865b10; 1 drivers, strength-aware
+L_00000000038654f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003492880_0 .net8 "VPB", 0 0, L_00000000038654f0; 1 drivers, strength-aware
+L_0000000003865480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034929c0_0 .net8 "VPWR", 0 0, L_0000000003865480; 1 drivers, strength-aware
+v0000000003492a60_0 .net "X", 0 0, L_0000000003923960; alias, 1 drivers
+v0000000003490620_0 .net "mux_2to10_out_X", 0 0, L_0000000003923880; 1 drivers
+S_00000000034cf580 .scope module, "_346_" "sky130_fd_sc_hd__mux2_1" 3 957, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034954e0_0 .net "A0", 0 0, L_0000000003921580; alias, 1 drivers
+v0000000003493b40_0 .net "A1", 0 0, L_000000000391aac0; alias, 1 drivers
+v00000000034935a0_0 .net "S", 0 0, L_000000000391c110; alias, 1 drivers
+L_0000000003865aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003493820_0 .net8 "VGND", 0 0, L_0000000003865aa0; 1 drivers, strength-aware
+L_0000000003865e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003493280_0 .net8 "VNB", 0 0, L_0000000003865e20; 1 drivers, strength-aware
+L_0000000003865e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493460_0 .net8 "VPB", 0 0, L_0000000003865e90; 1 drivers, strength-aware
+L_0000000003865f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493aa0_0 .net8 "VPWR", 0 0, L_0000000003865f00; 1 drivers, strength-aware
+v0000000003494e00_0 .net "X", 0 0, L_0000000003926280; alias, 1 drivers
+S_00000000034cf100 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cf580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039239d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003921580, L_000000000391aac0, L_000000000391c110;
+L_0000000003926280 .functor BUF 1, L_00000000039239d0, C4<0>, C4<0>, C4<0>;
+v0000000003493780_0 .net "A0", 0 0, L_0000000003921580; alias, 1 drivers
+v00000000034931e0_0 .net "A1", 0 0, L_000000000391aac0; alias, 1 drivers
+v0000000003494220_0 .net "S", 0 0, L_000000000391c110; alias, 1 drivers
+L_00000000038658e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034933c0_0 .net8 "VGND", 0 0, L_00000000038658e0; 1 drivers, strength-aware
+L_0000000003865560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003494360_0 .net8 "VNB", 0 0, L_0000000003865560; 1 drivers, strength-aware
+L_0000000003865bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493500_0 .net8 "VPB", 0 0, L_0000000003865bf0; 1 drivers, strength-aware
+L_00000000038653a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493c80_0 .net8 "VPWR", 0 0, L_00000000038653a0; 1 drivers, strength-aware
+v0000000003493be0_0 .net "X", 0 0, L_0000000003926280; alias, 1 drivers
+v00000000034945e0_0 .net "mux_2to10_out_X", 0 0, L_00000000039239d0; 1 drivers
+S_00000000034d0780 .scope module, "_347_" "sky130_fd_sc_hd__mux2_1" 3 963, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034947c0_0 .net "A0", 0 0, L_000000000391f8a0; alias, 1 drivers
+v00000000034944a0_0 .net "A1", 0 0, L_000000000391f600; alias, 1 drivers
+v0000000003494a40_0 .net "S", 0 0, L_000000000391e870; alias, 1 drivers
+L_0000000003865720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495080_0 .net8 "VGND", 0 0, L_0000000003865720; 1 drivers, strength-aware
+L_0000000003865f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495260_0 .net8 "VNB", 0 0, L_0000000003865f70; 1 drivers, strength-aware
+L_0000000003865790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493dc0_0 .net8 "VPB", 0 0, L_0000000003865790; 1 drivers, strength-aware
+L_00000000038655d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003492ec0_0 .net8 "VPWR", 0 0, L_00000000038655d0; 1 drivers, strength-aware
+v0000000003494180_0 .net "X", 0 0, L_0000000003926bb0; alias, 1 drivers
+S_00000000034cd900 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039264b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f8a0, L_000000000391f600, L_000000000391e870;
+L_0000000003926bb0 .functor BUF 1, L_00000000039264b0, C4<0>, C4<0>, C4<0>;
+v00000000034936e0_0 .net "A0", 0 0, L_000000000391f8a0; alias, 1 drivers
+v0000000003492d80_0 .net "A1", 0 0, L_000000000391f600; alias, 1 drivers
+v00000000034938c0_0 .net "S", 0 0, L_000000000391e870; alias, 1 drivers
+L_0000000003865090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034951c0_0 .net8 "VGND", 0 0, L_0000000003865090; 1 drivers, strength-aware
+L_0000000003865640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003493960_0 .net8 "VNB", 0 0, L_0000000003865640; 1 drivers, strength-aware
+L_00000000038656b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003494400_0 .net8 "VPB", 0 0, L_00000000038656b0; 1 drivers, strength-aware
+L_0000000003865100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003493a00_0 .net8 "VPWR", 0 0, L_0000000003865100; 1 drivers, strength-aware
+v0000000003493d20_0 .net "X", 0 0, L_0000000003926bb0; alias, 1 drivers
+v0000000003494860_0 .net "mux_2to10_out_X", 0 0, L_00000000039264b0; 1 drivers
+S_00000000034cef80 .scope module, "_348_" "sky130_fd_sc_hd__mux2_1" 3 969, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003494720_0 .net "A0", 0 0, L_000000000391f1a0; alias, 1 drivers
+v0000000003492e20_0 .net "A1", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000003494900_0 .net "S", 0 0, L_000000000391eb80; alias, 1 drivers
+L_0000000003865800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034953a0_0 .net8 "VGND", 0 0, L_0000000003865800; 1 drivers, strength-aware
+L_0000000003865870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495300_0 .net8 "VNB", 0 0, L_0000000003865870; 1 drivers, strength-aware
+L_0000000003865950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003494ae0_0 .net8 "VPB", 0 0, L_0000000003865950; 1 drivers, strength-aware
+L_0000000003865db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003494cc0_0 .net8 "VPWR", 0 0, L_0000000003865db0; 1 drivers, strength-aware
+v0000000003494d60_0 .net "X", 0 0, L_00000000039258e0; alias, 1 drivers
+S_00000000034cb800 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cef80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925b10 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f1a0, L_000000000391e4f0, L_000000000391eb80;
+L_00000000039258e0 .functor BUF 1, L_0000000003925b10, C4<0>, C4<0>, C4<0>;
+v0000000003493f00_0 .net "A0", 0 0, L_000000000391f1a0; alias, 1 drivers
+v0000000003493fa0_0 .net "A1", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000003493000_0 .net "S", 0 0, L_000000000391eb80; alias, 1 drivers
+L_00000000038659c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003494040_0 .net8 "VGND", 0 0, L_00000000038659c0; 1 drivers, strength-aware
+L_0000000003865a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003494ea0_0 .net8 "VNB", 0 0, L_0000000003865a30; 1 drivers, strength-aware
+L_0000000003865b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003495440_0 .net8 "VPB", 0 0, L_0000000003865b80; 1 drivers, strength-aware
+L_0000000003865c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003494c20_0 .net8 "VPWR", 0 0, L_0000000003865c60; 1 drivers, strength-aware
+v0000000003495120_0 .net "X", 0 0, L_00000000039258e0; alias, 1 drivers
+v0000000003494680_0 .net "mux_2to10_out_X", 0 0, L_0000000003925b10; 1 drivers
+S_00000000034cd300 .scope module, "_349_" "sky130_fd_sc_hd__mux2_1" 3 975, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003497ba0_0 .net "A0", 0 0, L_000000000391f590; alias, 1 drivers
+v0000000003495f80_0 .net "A1", 0 0, L_000000000391ea30; alias, 1 drivers
+v0000000003496a20_0 .net "S", 0 0, L_000000000391f130; alias, 1 drivers
+L_0000000003865cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495ee0_0 .net8 "VGND", 0 0, L_0000000003865cd0; 1 drivers, strength-aware
+L_0000000003865d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495940_0 .net8 "VNB", 0 0, L_0000000003865d40; 1 drivers, strength-aware
+L_0000000003865170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034968e0_0 .net8 "VPB", 0 0, L_0000000003865170; 1 drivers, strength-aware
+L_00000000038651e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034976a0_0 .net8 "VPWR", 0 0, L_00000000038651e0; 1 drivers, strength-aware
+v0000000003496d40_0 .net "X", 0 0, L_0000000003925480; alias, 1 drivers
+S_00000000034d0480 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cd300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039256b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f590, L_000000000391ea30, L_000000000391f130;
+L_0000000003925480 .functor BUF 1, L_00000000039256b0, C4<0>, C4<0>, C4<0>;
+v0000000003494f40_0 .net "A0", 0 0, L_000000000391f590; alias, 1 drivers
+v0000000003494fe0_0 .net "A1", 0 0, L_000000000391ea30; alias, 1 drivers
+v0000000003492f60_0 .net "S", 0 0, L_000000000391f130; alias, 1 drivers
+L_0000000003865250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034930a0_0 .net8 "VGND", 0 0, L_0000000003865250; 1 drivers, strength-aware
+L_00000000038652c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003493140_0 .net8 "VNB", 0 0, L_00000000038652c0; 1 drivers, strength-aware
+L_0000000003867940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003496840_0 .net8 "VPB", 0 0, L_0000000003867940; 1 drivers, strength-aware
+L_0000000003866980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034958a0_0 .net8 "VPWR", 0 0, L_0000000003866980; 1 drivers, strength-aware
+v0000000003496fc0_0 .net "X", 0 0, L_0000000003925480; alias, 1 drivers
+v0000000003497600_0 .net "mux_2to10_out_X", 0 0, L_00000000039256b0; 1 drivers
+S_00000000034cbb00 .scope module, "_350_" "sky130_fd_sc_hd__mux2_1" 3 981, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003496c00_0 .net "A0", 0 0, L_0000000003927860; alias, 1 drivers
+v0000000003497c40_0 .net "A1", 0 0, L_000000000391d1b0; alias, 1 drivers
+v0000000003496980_0 .net "S", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_00000000038671d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034959e0_0 .net8 "VGND", 0 0, L_00000000038671d0; 1 drivers, strength-aware
+L_0000000003867320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003496520_0 .net8 "VNB", 0 0, L_0000000003867320; 1 drivers, strength-aware
+L_00000000038674e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034965c0_0 .net8 "VPB", 0 0, L_00000000038674e0; 1 drivers, strength-aware
+L_0000000003867a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003496160_0 .net8 "VPWR", 0 0, L_0000000003867a20; 1 drivers, strength-aware
+v0000000003496ca0_0 .net "X", 0 0, L_00000000039263d0; alias, 1 drivers
+S_00000000034cee00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cbb00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039267c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927860, L_000000000391d1b0, L_000000000391d3e0;
+L_00000000039263d0 .functor BUF 1, L_00000000039267c0, C4<0>, C4<0>, C4<0>;
+v0000000003497420_0 .net "A0", 0 0, L_0000000003927860; alias, 1 drivers
+v0000000003495d00_0 .net "A1", 0 0, L_000000000391d1b0; alias, 1 drivers
+v0000000003495800_0 .net "S", 0 0, L_000000000391d3e0; alias, 1 drivers
+L_00000000038662f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003497920_0 .net8 "VGND", 0 0, L_00000000038662f0; 1 drivers, strength-aware
+L_00000000038663d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495bc0_0 .net8 "VNB", 0 0, L_00000000038663d0; 1 drivers, strength-aware
+L_0000000003866b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003497240_0 .net8 "VPB", 0 0, L_0000000003866b40; 1 drivers, strength-aware
+L_0000000003866440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003497060_0 .net8 "VPWR", 0 0, L_0000000003866440; 1 drivers, strength-aware
+v00000000034962a0_0 .net "X", 0 0, L_00000000039263d0; alias, 1 drivers
+v0000000003496480_0 .net "mux_2to10_out_X", 0 0, L_00000000039267c0; 1 drivers
+S_00000000034cf700 .scope module, "_351_" "sky130_fd_sc_hd__mux2_1" 3 987, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003496660_0 .net "A0", 0 0, L_000000000391ea30; alias, 1 drivers
+v0000000003495760_0 .net "A1", 0 0, L_00000000039222a0; alias, 1 drivers
+v0000000003496700_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003867160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003496200_0 .net8 "VGND", 0 0, L_0000000003867160; 1 drivers, strength-aware
+L_0000000003867b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034960c0_0 .net8 "VNB", 0 0, L_0000000003867b70; 1 drivers, strength-aware
+L_0000000003866f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003496e80_0 .net8 "VPB", 0 0, L_0000000003866f30; 1 drivers, strength-aware
+L_0000000003866360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034967a0_0 .net8 "VPWR", 0 0, L_0000000003866360; 1 drivers, strength-aware
+v00000000034977e0_0 .net "X", 0 0, L_0000000003926c20; alias, 1 drivers
+S_00000000034cb980 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cf700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039252c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391ea30, L_00000000039222a0, L_00000000039263d0;
+L_0000000003926c20 .functor BUF 1, L_00000000039252c0, C4<0>, C4<0>, C4<0>;
+v0000000003495b20_0 .net "A0", 0 0, L_000000000391ea30; alias, 1 drivers
+v0000000003496ac0_0 .net "A1", 0 0, L_00000000039222a0; alias, 1 drivers
+v00000000034956c0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003867080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495620_0 .net8 "VGND", 0 0, L_0000000003867080; 1 drivers, strength-aware
+L_0000000003866fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034979c0_0 .net8 "VNB", 0 0, L_0000000003866fa0; 1 drivers, strength-aware
+L_00000000038679b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003495e40_0 .net8 "VPB", 0 0, L_00000000038679b0; 1 drivers, strength-aware
+L_0000000003866ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003496b60_0 .net8 "VPWR", 0 0, L_0000000003866ec0; 1 drivers, strength-aware
+v0000000003496020_0 .net "X", 0 0, L_0000000003926c20; alias, 1 drivers
+v0000000003496de0_0 .net "mux_2to10_out_X", 0 0, L_00000000039252c0; 1 drivers
+S_00000000034cca00 .scope module, "_352_" "sky130_fd_sc_hd__mux2_1" 3 993, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003497560_0 .net "A0", 0 0, L_0000000003926050; alias, 1 drivers
+v0000000003497740_0 .net "A1", 0 0, L_0000000003926670; alias, 1 drivers
+v0000000003497880_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003866590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003495da0_0 .net8 "VGND", 0 0, L_0000000003866590; 1 drivers, strength-aware
+L_0000000003866830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003497a60_0 .net8 "VNB", 0 0, L_0000000003866830; 1 drivers, strength-aware
+L_00000000038660c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003497b00_0 .net8 "VPB", 0 0, L_00000000038660c0; 1 drivers, strength-aware
+L_0000000003866bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003497ce0_0 .net8 "VPWR", 0 0, L_0000000003866bb0; 1 drivers, strength-aware
+v0000000003495580_0 .net "X", 0 0, L_00000000039260c0; alias, 1 drivers
+S_00000000034d0000 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cca00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039254f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926050, L_0000000003926670, L_000000000391fc90;
+L_00000000039260c0 .functor BUF 1, L_00000000039254f0, C4<0>, C4<0>, C4<0>;
+v0000000003495c60_0 .net "A0", 0 0, L_0000000003926050; alias, 1 drivers
+v0000000003496340_0 .net "A1", 0 0, L_0000000003926670; alias, 1 drivers
+v00000000034974c0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003867550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034963e0_0 .net8 "VGND", 0 0, L_0000000003867550; 1 drivers, strength-aware
+L_0000000003866ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003496f20_0 .net8 "VNB", 0 0, L_0000000003866ad0; 1 drivers, strength-aware
+L_0000000003867390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003497100_0 .net8 "VPB", 0 0, L_0000000003867390; 1 drivers, strength-aware
+L_0000000003867be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034971a0_0 .net8 "VPWR", 0 0, L_0000000003867be0; 1 drivers, strength-aware
+v00000000034972e0_0 .net "X", 0 0, L_00000000039260c0; alias, 1 drivers
+v0000000003497380_0 .net "mux_2to10_out_X", 0 0, L_00000000039254f0; 1 drivers
+S_00000000034cf880 .scope module, "_353_" "sky130_fd_sc_hd__mux2_1" 3 999, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000034995e0_0 .net "A0", 0 0, L_000000000391bfc0; alias, 1 drivers
+v0000000003499720_0 .net "A1", 0 0, L_000000000391f8a0; alias, 1 drivers
+v0000000003498be0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003867240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498c80_0 .net8 "VGND", 0 0, L_0000000003867240; 1 drivers, strength-aware
+L_00000000038664b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499040_0 .net8 "VNB", 0 0, L_00000000038664b0; 1 drivers, strength-aware
+L_0000000003866520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499680_0 .net8 "VPB", 0 0, L_0000000003866520; 1 drivers, strength-aware
+L_0000000003867400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034997c0_0 .net8 "VPWR", 0 0, L_0000000003867400; 1 drivers, strength-aware
+v00000000034994a0_0 .net "X", 0 0, L_0000000003925330; alias, 1 drivers
+S_00000000034cbf80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cf880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925e20 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391bfc0, L_000000000391f8a0, L_00000000039263d0;
+L_0000000003925330 .functor BUF 1, L_0000000003925e20, C4<0>, C4<0>, C4<0>;
+v0000000003495a80_0 .net "A0", 0 0, L_000000000391bfc0; alias, 1 drivers
+v0000000003498fa0_0 .net "A1", 0 0, L_000000000391f8a0; alias, 1 drivers
+v0000000003497ec0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003866600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499860_0 .net8 "VGND", 0 0, L_0000000003866600; 1 drivers, strength-aware
+L_0000000003866670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499ae0_0 .net8 "VNB", 0 0, L_0000000003866670; 1 drivers, strength-aware
+L_00000000038672b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499ea0_0 .net8 "VPB", 0 0, L_00000000038672b0; 1 drivers, strength-aware
+L_0000000003867470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003498820_0 .net8 "VPWR", 0 0, L_0000000003867470; 1 drivers, strength-aware
+v00000000034981e0_0 .net "X", 0 0, L_0000000003925330; alias, 1 drivers
+v00000000034988c0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925e20; 1 drivers
+S_00000000034cda80 .scope module, "_354_" "sky130_fd_sc_hd__mux2_1" 3 1005, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003497f60_0 .net "A0", 0 0, L_0000000003925330; alias, 1 drivers
+v0000000003497e20_0 .net "A1", 0 0, L_00000000039270f0; alias, 1 drivers
+v00000000034999a0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003866280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498280_0 .net8 "VGND", 0 0, L_0000000003866280; 1 drivers, strength-aware
+L_00000000038667c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499180_0 .net8 "VNB", 0 0, L_00000000038667c0; 1 drivers, strength-aware
+L_0000000003866130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499c20_0 .net8 "VPB", 0 0, L_0000000003866130; 1 drivers, strength-aware
+L_00000000038661a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003498e60_0 .net8 "VPWR", 0 0, L_00000000038661a0; 1 drivers, strength-aware
+v0000000003498b40_0 .net "X", 0 0, L_0000000003926830; alias, 1 drivers
+S_00000000034ce380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cda80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925560 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925330, L_00000000039270f0, L_000000000391fc90;
+L_0000000003926830 .functor BUF 1, L_0000000003925560, C4<0>, C4<0>, C4<0>;
+v00000000034990e0_0 .net "A0", 0 0, L_0000000003925330; alias, 1 drivers
+v00000000034983c0_0 .net "A1", 0 0, L_00000000039270f0; alias, 1 drivers
+v0000000003498500_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_00000000038675c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000034992c0_0 .net8 "VGND", 0 0, L_00000000038675c0; 1 drivers, strength-aware
+L_00000000038666e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499900_0 .net8 "VNB", 0 0, L_00000000038666e0; 1 drivers, strength-aware
+L_0000000003867630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003498140_0 .net8 "VPB", 0 0, L_0000000003867630; 1 drivers, strength-aware
+L_00000000038676a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499a40_0 .net8 "VPWR", 0 0, L_00000000038676a0; 1 drivers, strength-aware
+v0000000003499f40_0 .net "X", 0 0, L_0000000003926830; alias, 1 drivers
+v0000000003498960_0 .net "mux_2to10_out_X", 0 0, L_0000000003925560; 1 drivers
+S_00000000034cc280 .scope module, "_355_" "sky130_fd_sc_hd__mux2_1" 3 1011, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003498640_0 .net "A0", 0 0, L_000000000391aa50; alias, 1 drivers
+v0000000003498a00_0 .net "A1", 0 0, L_000000000391e800; alias, 1 drivers
+v0000000003498000_0 .net "S", 0 0, L_000000000391eb10; alias, 1 drivers
+L_0000000003866750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498f00_0 .net8 "VGND", 0 0, L_0000000003866750; 1 drivers, strength-aware
+L_00000000038677f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003499540_0 .net8 "VNB", 0 0, L_00000000038677f0; 1 drivers, strength-aware
+L_0000000003866210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000034980a0_0 .net8 "VPB", 0 0, L_0000000003866210; 1 drivers, strength-aware
+L_0000000003867a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499b80_0 .net8 "VPWR", 0 0, L_0000000003867a90; 1 drivers, strength-aware
+v0000000003499cc0_0 .net "X", 0 0, L_0000000003926980; alias, 1 drivers
+S_00000000034ce500 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cc280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925640 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391aa50, L_000000000391e800, L_000000000391eb10;
+L_0000000003926980 .functor BUF 1, L_0000000003925640, C4<0>, C4<0>, C4<0>;
+v0000000003498aa0_0 .net "A0", 0 0, L_000000000391aa50; alias, 1 drivers
+v0000000003498460_0 .net "A1", 0 0, L_000000000391e800; alias, 1 drivers
+v00000000034985a0_0 .net "S", 0 0, L_000000000391eb10; alias, 1 drivers
+L_0000000003866de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498d20_0 .net8 "VGND", 0 0, L_0000000003866de0; 1 drivers, strength-aware
+L_00000000038670f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498780_0 .net8 "VNB", 0 0, L_00000000038670f0; 1 drivers, strength-aware
+L_0000000003867b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003499220_0 .net8 "VPB", 0 0, L_0000000003867b00; 1 drivers, strength-aware
+L_0000000003867710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003498dc0_0 .net8 "VPWR", 0 0, L_0000000003867710; 1 drivers, strength-aware
+v0000000003499400_0 .net "X", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003499360_0 .net "mux_2to10_out_X", 0 0, L_0000000003925640; 1 drivers
+S_00000000034cc700 .scope module, "_356_" "sky130_fd_sc_hd__mux2_1" 3 1017, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003505970_0 .net "A0", 0 0, L_0000000003926360; alias, 1 drivers
+v0000000003504bb0_0 .net "A1", 0 0, L_0000000003922d20; alias, 1 drivers
+v0000000003506d70_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003867c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003504f70_0 .net8 "VGND", 0 0, L_0000000003867c50; 1 drivers, strength-aware
+L_00000000038668a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505150_0 .net8 "VNB", 0 0, L_00000000038668a0; 1 drivers, strength-aware
+L_0000000003866910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506b90_0 .net8 "VPB", 0 0, L_0000000003866910; 1 drivers, strength-aware
+L_00000000038669f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003504c50_0 .net8 "VPWR", 0 0, L_00000000038669f0; 1 drivers, strength-aware
+v0000000003505330_0 .net "X", 0 0, L_0000000003925100; alias, 1 drivers
+S_00000000034ccb80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cc700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926c90 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926360, L_0000000003922d20, L_0000000003920e80;
+L_0000000003925100 .functor BUF 1, L_0000000003926c90, C4<0>, C4<0>, C4<0>;
+v00000000034986e0_0 .net "A0", 0 0, L_0000000003926360; alias, 1 drivers
+v0000000003499d60_0 .net "A1", 0 0, L_0000000003922d20; alias, 1 drivers
+v0000000003499e00_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003866a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003497d80_0 .net8 "VGND", 0 0, L_0000000003866a60; 1 drivers, strength-aware
+L_0000000003866c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003498320_0 .net8 "VNB", 0 0, L_0000000003866c20; 1 drivers, strength-aware
+L_0000000003866c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035069b0_0 .net8 "VPB", 0 0, L_0000000003866c90; 1 drivers, strength-aware
+L_0000000003867780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003505290_0 .net8 "VPWR", 0 0, L_0000000003867780; 1 drivers, strength-aware
+v0000000003506cd0_0 .net "X", 0 0, L_0000000003925100; alias, 1 drivers
+v0000000003504cf0_0 .net "mux_2to10_out_X", 0 0, L_0000000003926c90; 1 drivers
+S_00000000034d0300 .scope module, "_357_" "sky130_fd_sc_hd__mux2_1" 3 1023, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003504a70_0 .net "A0", 0 0, L_0000000003928270; alias, 1 drivers
+v0000000003505010_0 .net "A1", 0 0, L_0000000003922770; alias, 1 drivers
+v0000000003506eb0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003867860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003506ff0_0 .net8 "VGND", 0 0, L_0000000003867860; 1 drivers, strength-aware
+L_00000000038678d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003506870_0 .net8 "VNB", 0 0, L_00000000038678d0; 1 drivers, strength-aware
+L_0000000003867010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506370_0 .net8 "VPB", 0 0, L_0000000003867010; 1 drivers, strength-aware
+L_0000000003866d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003504e30_0 .net8 "VPWR", 0 0, L_0000000003866d00; 1 drivers, strength-aware
+v0000000003504ed0_0 .net "X", 0 0, L_0000000003926ad0; alias, 1 drivers
+S_00000000034cf400 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925a30 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003928270, L_0000000003922770, L_0000000003920e80;
+L_0000000003926ad0 .functor BUF 1, L_0000000003925a30, C4<0>, C4<0>, C4<0>;
+v0000000003504d90_0 .net "A0", 0 0, L_0000000003928270; alias, 1 drivers
+v0000000003505830_0 .net "A1", 0 0, L_0000000003922770; alias, 1 drivers
+v0000000003506230_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003866d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035067d0_0 .net8 "VGND", 0 0, L_0000000003866d70; 1 drivers, strength-aware
+L_0000000003866e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505a10_0 .net8 "VNB", 0 0, L_0000000003866e50; 1 drivers, strength-aware
+L_0000000003867e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506af0_0 .net8 "VPB", 0 0, L_0000000003867e10; 1 drivers, strength-aware
+L_0000000003868820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507090_0 .net8 "VPWR", 0 0, L_0000000003868820; 1 drivers, strength-aware
+v00000000035056f0_0 .net "X", 0 0, L_0000000003926ad0; alias, 1 drivers
+v00000000035050b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925a30; 1 drivers
+S_00000000034cf280 .scope module, "_358_" "sky130_fd_sc_hd__mux2_1" 3 1029, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003505470_0 .net "A0", 0 0, L_0000000003926de0; alias, 1 drivers
+v0000000003504b10_0 .net "A1", 0 0, L_0000000003927da0; alias, 1 drivers
+v00000000035055b0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003868890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505c90_0 .net8 "VGND", 0 0, L_0000000003868890; 1 drivers, strength-aware
+L_0000000003868350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505650_0 .net8 "VNB", 0 0, L_0000000003868350; 1 drivers, strength-aware
+L_0000000003868e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506550_0 .net8 "VPB", 0 0, L_0000000003868e40; 1 drivers, strength-aware
+L_0000000003868c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506050_0 .net8 "VPWR", 0 0, L_0000000003868c80; 1 drivers, strength-aware
+v00000000035062d0_0 .net "X", 0 0, L_0000000003926b40; alias, 1 drivers
+S_00000000034ccd00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cf280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925e90 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926de0, L_0000000003927da0, L_000000000391fc90;
+L_0000000003926b40 .functor BUF 1, L_0000000003925e90, C4<0>, C4<0>, C4<0>;
+v00000000035051f0_0 .net "A0", 0 0, L_0000000003926de0; alias, 1 drivers
+v0000000003505e70_0 .net "A1", 0 0, L_0000000003927da0; alias, 1 drivers
+v00000000035053d0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003868510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505ab0_0 .net8 "VGND", 0 0, L_0000000003868510; 1 drivers, strength-aware
+L_0000000003867e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003505510_0 .net8 "VNB", 0 0, L_0000000003867e80; 1 drivers, strength-aware
+L_0000000003868f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506190_0 .net8 "VPB", 0 0, L_0000000003868f90; 1 drivers, strength-aware
+L_0000000003867f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003505bf0_0 .net8 "VPWR", 0 0, L_0000000003867f60; 1 drivers, strength-aware
+v0000000003506410_0 .net "X", 0 0, L_0000000003926b40; alias, 1 drivers
+v0000000003505fb0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925e90; 1 drivers
+S_00000000034cce80 .scope module, "_359_" "sky130_fd_sc_hd__mux2_1" 3 1035, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000035058d0_0 .net "A0", 0 0, L_00000000039282e0; alias, 1 drivers
+v0000000003505b50_0 .net "A1", 0 0, L_0000000003926050; alias, 1 drivers
+v00000000035060f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003867d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003506f50_0 .net8 "VGND", 0 0, L_0000000003867d30; 1 drivers, strength-aware
+L_00000000038683c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003504930_0 .net8 "VNB", 0 0, L_00000000038683c0; 1 drivers, strength-aware
+L_0000000003868430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506730_0 .net8 "VPB", 0 0, L_0000000003868430; 1 drivers, strength-aware
+L_0000000003867da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003506910_0 .net8 "VPWR", 0 0, L_0000000003867da0; 1 drivers, strength-aware
+v0000000003506c30_0 .net "X", 0 0, L_0000000003925950; alias, 1 drivers
+S_00000000034cd000 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cce80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926520 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039282e0, L_0000000003926050, L_000000000391fc90;
+L_0000000003925950 .functor BUF 1, L_0000000003926520, C4<0>, C4<0>, C4<0>;
+v0000000003505d30_0 .net "A0", 0 0, L_00000000039282e0; alias, 1 drivers
+v0000000003506e10_0 .net "A1", 0 0, L_0000000003926050; alias, 1 drivers
+v0000000003505dd0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003868200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035064b0_0 .net8 "VGND", 0 0, L_0000000003868200; 1 drivers, strength-aware
+L_00000000038692a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003506a50_0 .net8 "VNB", 0 0, L_00000000038692a0; 1 drivers, strength-aware
+L_00000000038682e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003505f10_0 .net8 "VPB", 0 0, L_00000000038682e0; 1 drivers, strength-aware
+L_0000000003867ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035065f0_0 .net8 "VPWR", 0 0, L_0000000003867ef0; 1 drivers, strength-aware
+v0000000003506690_0 .net "X", 0 0, L_0000000003925950; alias, 1 drivers
+v0000000003505790_0 .net "mux_2to10_out_X", 0 0, L_0000000003926520; 1 drivers
+S_00000000034d0c00 .scope module, "_360_" "sky130_fd_sc_hd__mux2_1" 3 1041, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003509070_0 .net "A0", 0 0, L_000000000391fa60; alias, 1 drivers
+v0000000003509390_0 .net "A1", 0 0, L_000000000380c2e0; 1 drivers
+v00000000035097f0_0 .net "S", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_0000000003868b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003507db0_0 .net8 "VGND", 0 0, L_0000000003868b30; 1 drivers, strength-aware
+L_0000000003867fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035076d0_0 .net8 "VNB", 0 0, L_0000000003867fd0; 1 drivers, strength-aware
+L_0000000003869310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003508490_0 .net8 "VPB", 0 0, L_0000000003869310; 1 drivers, strength-aware
+L_0000000003868dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507770_0 .net8 "VPWR", 0 0, L_0000000003868dd0; 1 drivers, strength-aware
+v0000000003508990_0 .net "X", 0 0, L_00000000039253a0; alias, 1 drivers
+S_00000000034cd180 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0c00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925d40 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391fa60, L_000000000380c2e0, L_000000000391e8e0;
+L_00000000039253a0 .functor BUF 1, L_0000000003925d40, C4<0>, C4<0>, C4<0>;
+v00000000035049d0_0 .net "A0", 0 0, L_000000000391fa60; alias, 1 drivers
+v0000000003509610_0 .net "A1", 0 0, L_000000000380c2e0; alias, 1 drivers
+v00000000035088f0_0 .net "S", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_00000000038697e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003509890_0 .net8 "VGND", 0 0, L_00000000038697e0; 1 drivers, strength-aware
+L_0000000003869150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003508530_0 .net8 "VNB", 0 0, L_0000000003869150; 1 drivers, strength-aware
+L_0000000003868eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507450_0 .net8 "VPB", 0 0, L_0000000003868eb0; 1 drivers, strength-aware
+L_0000000003868660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003508df0_0 .net8 "VPWR", 0 0, L_0000000003868660; 1 drivers, strength-aware
+v0000000003507270_0 .net "X", 0 0, L_00000000039253a0; alias, 1 drivers
+v0000000003507f90_0 .net "mux_2to10_out_X", 0 0, L_0000000003925d40; 1 drivers
+S_00000000034cdc00 .scope module, "_361_" "sky130_fd_sc_hd__mux2_1" 3 1047, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003507e50_0 .net "A0", 0 0, L_0000000003925c60; alias, 1 drivers
+v0000000003507810_0 .net "A1", 0 0, L_0000000003925950; alias, 1 drivers
+v0000000003508a30_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003869380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035080d0_0 .net8 "VGND", 0 0, L_0000000003869380; 1 drivers, strength-aware
+L_00000000038690e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003507590_0 .net8 "VNB", 0 0, L_00000000038690e0; 1 drivers, strength-aware
+L_0000000003868740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035082b0_0 .net8 "VPB", 0 0, L_0000000003868740; 1 drivers, strength-aware
+L_00000000038684a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003508350_0 .net8 "VPWR", 0 0, L_00000000038684a0; 1 drivers, strength-aware
+v00000000035087b0_0 .net "X", 0 0, L_0000000003926360; alias, 1 drivers
+S_00000000034cd480 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cdc00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925170 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925c60, L_0000000003925950, L_000000000391eaa0;
+L_0000000003926360 .functor BUF 1, L_0000000003925170, C4<0>, C4<0>, C4<0>;
+v0000000003508210_0 .net "A0", 0 0, L_0000000003925c60; alias, 1 drivers
+v00000000035074f0_0 .net "A1", 0 0, L_0000000003925950; alias, 1 drivers
+v0000000003508670_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003869230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003508030_0 .net8 "VGND", 0 0, L_0000000003869230; 1 drivers, strength-aware
+L_0000000003868f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003508710_0 .net8 "VNB", 0 0, L_0000000003868f20; 1 drivers, strength-aware
+L_0000000003869690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507310_0 .net8 "VPB", 0 0, L_0000000003869690; 1 drivers, strength-aware
+L_0000000003868120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035071d0_0 .net8 "VPWR", 0 0, L_0000000003868120; 1 drivers, strength-aware
+v00000000035094d0_0 .net "X", 0 0, L_0000000003926360; alias, 1 drivers
+v00000000035073b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925170; 1 drivers
+S_00000000034d0900 .scope module, "_362_" "sky130_fd_sc_hd__mux2_1" 3 1053, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003507130_0 .net "A0", 0 0, L_000000000391eaa0; alias, 1 drivers
+v0000000003507ef0_0 .net "A1", 0 0, L_0000000003921510; alias, 1 drivers
+v0000000003507950_0 .net "S", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_0000000003869540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003507bd0_0 .net8 "VGND", 0 0, L_0000000003869540; 1 drivers, strength-aware
+L_0000000003868040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035079f0_0 .net8 "VNB", 0 0, L_0000000003868040; 1 drivers, strength-aware
+L_00000000038680b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507b30_0 .net8 "VPB", 0 0, L_00000000038680b0; 1 drivers, strength-aware
+L_0000000003868580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035083f0_0 .net8 "VPWR", 0 0, L_0000000003868580; 1 drivers, strength-aware
+v00000000035091b0_0 .net "X", 0 0, L_00000000039251e0; alias, 1 drivers
+S_00000000034cd600 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0900;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925720 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391eaa0, L_0000000003921510, L_000000000391e8e0;
+L_00000000039251e0 .functor BUF 1, L_0000000003925720, C4<0>, C4<0>, C4<0>;
+v0000000003507630_0 .net "A0", 0 0, L_000000000391eaa0; alias, 1 drivers
+v00000000035078b0_0 .net "A1", 0 0, L_0000000003921510; alias, 1 drivers
+v0000000003508d50_0 .net "S", 0 0, L_000000000391e8e0; alias, 1 drivers
+L_00000000038685f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003508170_0 .net8 "VGND", 0 0, L_00000000038685f0; 1 drivers, strength-aware
+L_0000000003869070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003507d10_0 .net8 "VNB", 0 0, L_0000000003869070; 1 drivers, strength-aware
+L_0000000003869000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003509110_0 .net8 "VPB", 0 0, L_0000000003869000; 1 drivers, strength-aware
+L_00000000038691c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003507a90_0 .net8 "VPWR", 0 0, L_00000000038691c0; 1 drivers, strength-aware
+v0000000003508ad0_0 .net "X", 0 0, L_00000000039251e0; alias, 1 drivers
+v0000000003508b70_0 .net "mux_2to10_out_X", 0 0, L_0000000003925720; 1 drivers
+S_00000000034cdd80 .scope module, "_363_" "sky130_fd_sc_hd__mux2_1" 3 1059, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003509430_0 .net "A0", 0 0, L_00000000039270f0; alias, 1 drivers
+v0000000003509250_0 .net "A1", 0 0, L_00000000039282e0; alias, 1 drivers
+v00000000035092f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003868ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035096b0_0 .net8 "VGND", 0 0, L_0000000003868ac0; 1 drivers, strength-aware
+L_00000000038686d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003509750_0 .net8 "VNB", 0 0, L_00000000038686d0; 1 drivers, strength-aware
+L_0000000003868190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350a010_0 .net8 "VPB", 0 0, L_0000000003868190; 1 drivers, strength-aware
+L_0000000003868270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350add0_0 .net8 "VPWR", 0 0, L_0000000003868270; 1 drivers, strength-aware
+v000000000350b370_0 .net "X", 0 0, L_0000000003926600; alias, 1 drivers
+S_00000000034cdf00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cdd80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926590 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039270f0, L_00000000039282e0, L_000000000391fc90;
+L_0000000003926600 .functor BUF 1, L_0000000003926590, C4<0>, C4<0>, C4<0>;
+v0000000003507c70_0 .net "A0", 0 0, L_00000000039270f0; alias, 1 drivers
+v0000000003508c10_0 .net "A1", 0 0, L_00000000039282e0; alias, 1 drivers
+v0000000003508850_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_00000000038687b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003509570_0 .net8 "VGND", 0 0, L_00000000038687b0; 1 drivers, strength-aware
+L_0000000003868900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035085d0_0 .net8 "VNB", 0 0, L_0000000003868900; 1 drivers, strength-aware
+L_0000000003868970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003508cb0_0 .net8 "VPB", 0 0, L_0000000003868970; 1 drivers, strength-aware
+L_00000000038689e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003508fd0_0 .net8 "VPWR", 0 0, L_00000000038689e0; 1 drivers, strength-aware
+v0000000003508e90_0 .net "X", 0 0, L_0000000003926600; alias, 1 drivers
+v0000000003508f30_0 .net "mux_2to10_out_X", 0 0, L_0000000003926590; 1 drivers
+S_00000000034d0a80 .scope module, "_364_" "sky130_fd_sc_hd__mux2_1" 3 1065, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350bcd0_0 .net "A0", 0 0, L_0000000003926670; alias, 1 drivers
+v0000000003509d90_0 .net "A1", 0 0, L_0000000003925800; alias, 1 drivers
+v000000000350a330_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_00000000038693f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350b5f0_0 .net8 "VGND", 0 0, L_00000000038693f0; 1 drivers, strength-aware
+L_0000000003868cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350a0b0_0 .net8 "VNB", 0 0, L_0000000003868cf0; 1 drivers, strength-aware
+L_0000000003868a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003509bb0_0 .net8 "VPB", 0 0, L_0000000003868a50; 1 drivers, strength-aware
+L_0000000003868ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350bd70_0 .net8 "VPWR", 0 0, L_0000000003868ba0; 1 drivers, strength-aware
+v0000000003509f70_0 .net "X", 0 0, L_0000000003925c60; alias, 1 drivers
+S_00000000034ce680 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0a80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925b80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926670, L_0000000003925800, L_000000000391fc90;
+L_0000000003925c60 .functor BUF 1, L_0000000003925b80, C4<0>, C4<0>, C4<0>;
+v0000000003509c50_0 .net "A0", 0 0, L_0000000003926670; alias, 1 drivers
+v000000000350a150_0 .net "A1", 0 0, L_0000000003925800; alias, 1 drivers
+v000000000350ae70_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003869460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350a290_0 .net8 "VGND", 0 0, L_0000000003869460; 1 drivers, strength-aware
+L_0000000003868c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003509cf0_0 .net8 "VNB", 0 0, L_0000000003868c10; 1 drivers, strength-aware
+L_0000000003868d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350abf0_0 .net8 "VPB", 0 0, L_0000000003868d60; 1 drivers, strength-aware
+L_00000000038694d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b9b0_0 .net8 "VPWR", 0 0, L_00000000038694d0; 1 drivers, strength-aware
+v000000000350b0f0_0 .net "X", 0 0, L_0000000003925c60; alias, 1 drivers
+v000000000350af10_0 .net "mux_2to10_out_X", 0 0, L_0000000003925b80; 1 drivers
+S_00000000034cb080 .scope module, "_365_" "sky130_fd_sc_hd__mux2_1" 3 1071, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350b550_0 .net "A0", 0 0, L_0000000003922540; alias, 1 drivers
+v000000000350a830_0 .net "A1", 0 0, L_0000000003925c60; alias, 1 drivers
+v000000000350a6f0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038695b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350a1f0_0 .net8 "VGND", 0 0, L_00000000038695b0; 1 drivers, strength-aware
+L_0000000003869620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350a8d0_0 .net8 "VNB", 0 0, L_0000000003869620; 1 drivers, strength-aware
+L_0000000003869700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b230_0 .net8 "VPB", 0 0, L_0000000003869700; 1 drivers, strength-aware
+L_0000000003869770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b7d0_0 .net8 "VPWR", 0 0, L_0000000003869770; 1 drivers, strength-aware
+v000000000350aa10_0 .net "X", 0 0, L_0000000003925cd0; alias, 1 drivers
+S_00000000034ce080 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cb080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925410 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003922540, L_0000000003925c60, L_000000000391eaa0;
+L_0000000003925cd0 .functor BUF 1, L_0000000003925410, C4<0>, C4<0>, C4<0>;
+v000000000350afb0_0 .net "A0", 0 0, L_0000000003922540; alias, 1 drivers
+v000000000350aab0_0 .net "A1", 0 0, L_0000000003925c60; alias, 1 drivers
+v000000000350a510_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003869850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003509ed0_0 .net8 "VGND", 0 0, L_0000000003869850; 1 drivers, strength-aware
+L_0000000003867cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350ad30_0 .net8 "VNB", 0 0, L_0000000003867cc0; 1 drivers, strength-aware
+L_000000000386a730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350a970_0 .net8 "VPB", 0 0, L_000000000386a730; 1 drivers, strength-aware
+L_0000000003869a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350a5b0_0 .net8 "VPWR", 0 0, L_0000000003869a80; 1 drivers, strength-aware
+v000000000350be10_0 .net "X", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000350a650_0 .net "mux_2to10_out_X", 0 0, L_0000000003925410; 1 drivers
+S_00000000034ceb00 .scope module, "_366_" "sky130_fd_sc_hd__mux2_1" 3 1077, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350ac90_0 .net "A0", 0 0, L_000000000391f3d0; alias, 1 drivers
+v000000000350bf50_0 .net "A1", 0 0, L_000000000391f590; alias, 1 drivers
+v000000000350b050_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386af10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350b190_0 .net8 "VGND", 0 0, L_000000000386af10; 1 drivers, strength-aware
+L_000000000386a9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350b2d0_0 .net8 "VNB", 0 0, L_000000000386a9d0; 1 drivers, strength-aware
+L_000000000386b3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b4b0_0 .net8 "VPB", 0 0, L_000000000386b3e0; 1 drivers, strength-aware
+L_000000000386ad50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b690_0 .net8 "VPWR", 0 0, L_000000000386ad50; 1 drivers, strength-aware
+v000000000350b730_0 .net "X", 0 0, L_0000000003926670; alias, 1 drivers
+S_00000000034cec80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034ceb00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039261a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f3d0, L_000000000391f590, L_00000000039263d0;
+L_0000000003926670 .functor BUF 1, L_00000000039261a0, C4<0>, C4<0>, C4<0>;
+v0000000003509e30_0 .net "A0", 0 0, L_000000000391f3d0; alias, 1 drivers
+v000000000350a790_0 .net "A1", 0 0, L_000000000391f590; alias, 1 drivers
+v000000000350beb0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386aa40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350bff0_0 .net8 "VGND", 0 0, L_000000000386aa40; 1 drivers, strength-aware
+L_000000000386a260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350b870_0 .net8 "VNB", 0 0, L_000000000386a260; 1 drivers, strength-aware
+L_000000000386af80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350b410_0 .net8 "VPB", 0 0, L_000000000386af80; 1 drivers, strength-aware
+L_000000000386ace0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350a3d0_0 .net8 "VPWR", 0 0, L_000000000386ace0; 1 drivers, strength-aware
+v000000000350a470_0 .net "X", 0 0, L_0000000003926670; alias, 1 drivers
+v000000000350ab50_0 .net "mux_2to10_out_X", 0 0, L_00000000039261a0; 1 drivers
+S_00000000034d0d80 .scope module, "_367_" "sky130_fd_sc_hd__mux2_1" 3 1083, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003509b10_0 .net "A0", 0 0, L_0000000003925800; alias, 1 drivers
+v000000000350d5d0_0 .net "A1", 0 0, L_0000000003922d90; alias, 1 drivers
+v000000000350c8b0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386a340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d2b0_0 .net8 "VGND", 0 0, L_000000000386a340; 1 drivers, strength-aware
+L_0000000003869f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d3f0_0 .net8 "VNB", 0 0, L_0000000003869f50; 1 drivers, strength-aware
+L_000000000386ae30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e570_0 .net8 "VPB", 0 0, L_000000000386ae30; 1 drivers, strength-aware
+L_0000000003869c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e1b0_0 .net8 "VPWR", 0 0, L_0000000003869c40; 1 drivers, strength-aware
+v000000000350ddf0_0 .net "X", 0 0, L_0000000003926440; alias, 1 drivers
+S_00000000034cfa00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d0d80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039259c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925800, L_0000000003922d90, L_000000000391fc90;
+L_0000000003926440 .functor BUF 1, L_00000000039259c0, C4<0>, C4<0>, C4<0>;
+v000000000350c090_0 .net "A0", 0 0, L_0000000003925800; alias, 1 drivers
+v000000000350b910_0 .net "A1", 0 0, L_0000000003922d90; alias, 1 drivers
+v000000000350ba50_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386a960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350baf0_0 .net8 "VGND", 0 0, L_000000000386a960; 1 drivers, strength-aware
+L_000000000386aab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350bb90_0 .net8 "VNB", 0 0, L_000000000386aab0; 1 drivers, strength-aware
+L_0000000003869af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350bc30_0 .net8 "VPB", 0 0, L_0000000003869af0; 1 drivers, strength-aware
+L_0000000003869fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003509930_0 .net8 "VPWR", 0 0, L_0000000003869fc0; 1 drivers, strength-aware
+v00000000035099d0_0 .net "X", 0 0, L_0000000003926440; alias, 1 drivers
+v0000000003509a70_0 .net "mux_2to10_out_X", 0 0, L_00000000039259c0; 1 drivers
+S_00000000034cb200 .scope module, "_368_" "sky130_fd_sc_hd__mux2_1" 3 1089, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350d350_0 .net "A0", 0 0, L_00000000039230a0; alias, 1 drivers
+v000000000350e750_0 .net "A1", 0 0, L_000000000391ea30; alias, 1 drivers
+v000000000350d490_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_00000000038698c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350c4f0_0 .net8 "VGND", 0 0, L_00000000038698c0; 1 drivers, strength-aware
+L_0000000003869930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d030_0 .net8 "VNB", 0 0, L_0000000003869930; 1 drivers, strength-aware
+L_000000000386ab20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350d170_0 .net8 "VPB", 0 0, L_000000000386ab20; 1 drivers, strength-aware
+L_0000000003869b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350cd10_0 .net8 "VPWR", 0 0, L_0000000003869b60; 1 drivers, strength-aware
+v000000000350c1d0_0 .net "X", 0 0, L_0000000003925800; alias, 1 drivers
+S_00000000034cb380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cb200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039266e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039230a0, L_000000000391ea30, L_00000000039263d0;
+L_0000000003925800 .functor BUF 1, L_00000000039266e0, C4<0>, C4<0>, C4<0>;
+v000000000350c3b0_0 .net "A0", 0 0, L_00000000039230a0; alias, 1 drivers
+v000000000350c130_0 .net "A1", 0 0, L_000000000391ea30; alias, 1 drivers
+v000000000350c310_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386ab90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d0d0_0 .net8 "VGND", 0 0, L_000000000386ab90; 1 drivers, strength-aware
+L_000000000386ac70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350c810_0 .net8 "VNB", 0 0, L_000000000386ac70; 1 drivers, strength-aware
+L_0000000003869e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e610_0 .net8 "VPB", 0 0, L_0000000003869e00; 1 drivers, strength-aware
+L_000000000386aff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e890_0 .net8 "VPWR", 0 0, L_000000000386aff0; 1 drivers, strength-aware
+v000000000350d210_0 .net "X", 0 0, L_0000000003925800; alias, 1 drivers
+v000000000350cbd0_0 .net "mux_2to10_out_X", 0 0, L_00000000039266e0; 1 drivers
+S_00000000034cb500 .scope module, "_369_" "sky130_fd_sc_hd__mux2_1" 3 1095, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350e430_0 .net "A0", 0 0, L_000000000391f590; alias, 1 drivers
+v000000000350dd50_0 .net "A1", 0 0, L_00000000039230a0; alias, 1 drivers
+v000000000350dfd0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_00000000038699a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d530_0 .net8 "VGND", 0 0, L_00000000038699a0; 1 drivers, strength-aware
+L_000000000386b1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d670_0 .net8 "VNB", 0 0, L_000000000386b1b0; 1 drivers, strength-aware
+L_000000000386a5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350dcb0_0 .net8 "VPB", 0 0, L_000000000386a5e0; 1 drivers, strength-aware
+L_000000000386a880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350de90_0 .net8 "VPWR", 0 0, L_000000000386a880; 1 drivers, strength-aware
+v000000000350e110_0 .net "X", 0 0, L_0000000003925250; alias, 1 drivers
+S_00000000034cb680 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cb500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925870 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f590, L_00000000039230a0, L_00000000039263d0;
+L_0000000003925250 .functor BUF 1, L_0000000003925870, C4<0>, C4<0>, C4<0>;
+v000000000350c6d0_0 .net "A0", 0 0, L_000000000391f590; alias, 1 drivers
+v000000000350df30_0 .net "A1", 0 0, L_00000000039230a0; alias, 1 drivers
+v000000000350c950_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386b140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d710_0 .net8 "VGND", 0 0, L_000000000386b140; 1 drivers, strength-aware
+L_000000000386b060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350e070_0 .net8 "VNB", 0 0, L_000000000386b060; 1 drivers, strength-aware
+L_0000000003869e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350c450_0 .net8 "VPB", 0 0, L_0000000003869e70; 1 drivers, strength-aware
+L_000000000386a2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e7f0_0 .net8 "VPWR", 0 0, L_000000000386a2d0; 1 drivers, strength-aware
+v000000000350cdb0_0 .net "X", 0 0, L_0000000003925250; alias, 1 drivers
+v000000000350c770_0 .net "mux_2to10_out_X", 0 0, L_0000000003925870; 1 drivers
+S_00000000034d1f80 .scope module, "_370_" "sky130_fd_sc_hd__mux2_1" 3 1101, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350cb30_0 .net "A0", 0 0, L_00000000039260c0; alias, 1 drivers
+v000000000350cc70_0 .net "A1", 0 0, L_0000000003926600; alias, 1 drivers
+v000000000350cef0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386a490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350d850_0 .net8 "VGND", 0 0, L_000000000386a490; 1 drivers, strength-aware
+L_000000000386a570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350cf90_0 .net8 "VNB", 0 0, L_000000000386a570; 1 drivers, strength-aware
+L_000000000386ac00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350d8f0_0 .net8 "VPB", 0 0, L_000000000386ac00; 1 drivers, strength-aware
+L_000000000386a420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350d990_0 .net8 "VPWR", 0 0, L_000000000386a420; 1 drivers, strength-aware
+v000000000350e250_0 .net "X", 0 0, L_0000000003926910; alias, 1 drivers
+S_00000000034d4200 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1f80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925790 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039260c0, L_0000000003926600, L_000000000391eaa0;
+L_0000000003926910 .functor BUF 1, L_0000000003925790, C4<0>, C4<0>, C4<0>;
+v000000000350c590_0 .net "A0", 0 0, L_00000000039260c0; alias, 1 drivers
+v000000000350e4d0_0 .net "A1", 0 0, L_0000000003926600; alias, 1 drivers
+v000000000350ca90_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003869bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350ce50_0 .net8 "VGND", 0 0, L_0000000003869bd0; 1 drivers, strength-aware
+L_000000000386b370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350c270_0 .net8 "VNB", 0 0, L_000000000386b370; 1 drivers, strength-aware
+L_000000000386a110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350c630_0 .net8 "VPB", 0 0, L_000000000386a110; 1 drivers, strength-aware
+L_000000000386adc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350d7b0_0 .net8 "VPWR", 0 0, L_000000000386adc0; 1 drivers, strength-aware
+v000000000350c9f0_0 .net "X", 0 0, L_0000000003926910; alias, 1 drivers
+v000000000350db70_0 .net "mux_2to10_out_X", 0 0, L_0000000003925790; 1 drivers
+S_00000000034d3a80 .scope module, "_371_" "sky130_fd_sc_hd__mux2_1" 3 1107, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003510ff0_0 .net "A0", 0 0, L_0000000003926910; alias, 1 drivers
+v000000000350ee30_0 .net "A1", 0 0, L_00000000039219e0; alias, 1 drivers
+v000000000350fab0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003869cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003510f50_0 .net8 "VGND", 0 0, L_0000000003869cb0; 1 drivers, strength-aware
+L_0000000003869ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350fc90_0 .net8 "VNB", 0 0, L_0000000003869ee0; 1 drivers, strength-aware
+L_000000000386a3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350fd30_0 .net8 "VPB", 0 0, L_000000000386a3b0; 1 drivers, strength-aware
+L_000000000386b220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035107d0_0 .net8 "VPWR", 0 0, L_000000000386b220; 1 drivers, strength-aware
+v000000000350f970_0 .net "X", 0 0, L_0000000003926750; alias, 1 drivers
+S_00000000034d2100 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3a80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039255d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926910, L_00000000039219e0, L_0000000003920e80;
+L_0000000003926750 .functor BUF 1, L_00000000039255d0, C4<0>, C4<0>, C4<0>;
+v000000000350dc10_0 .net "A0", 0 0, L_0000000003926910; alias, 1 drivers
+v000000000350e2f0_0 .net "A1", 0 0, L_00000000039219e0; alias, 1 drivers
+v000000000350da30_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003869d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350dad0_0 .net8 "VGND", 0 0, L_0000000003869d20; 1 drivers, strength-aware
+L_000000000386a500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350e390_0 .net8 "VNB", 0 0, L_000000000386a500; 1 drivers, strength-aware
+L_0000000003869a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e6b0_0 .net8 "VPB", 0 0, L_0000000003869a10; 1 drivers, strength-aware
+L_000000000386a030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350f150_0 .net8 "VPWR", 0 0, L_000000000386a030; 1 drivers, strength-aware
+v0000000003510e10_0 .net "X", 0 0, L_0000000003926750; alias, 1 drivers
+v0000000003511090_0 .net "mux_2to10_out_X", 0 0, L_00000000039255d0; 1 drivers
+S_00000000034d2280 .scope module, "_372_" "sky130_fd_sc_hd__mux2_1" 3 1113, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000350eed0_0 .net "A0", 0 0, L_000000000391f8a0; alias, 1 drivers
+v00000000035100f0_0 .net "A1", 0 0, L_000000000391c7a0; alias, 1 drivers
+v000000000350f830_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386aea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350eb10_0 .net8 "VGND", 0 0, L_000000000386aea0; 1 drivers, strength-aware
+L_000000000386a650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350fa10_0 .net8 "VNB", 0 0, L_000000000386a650; 1 drivers, strength-aware
+L_000000000386b0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350fb50_0 .net8 "VPB", 0 0, L_000000000386b0d0; 1 drivers, strength-aware
+L_000000000386a6c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350ff10_0 .net8 "VPWR", 0 0, L_000000000386a6c0; 1 drivers, strength-aware
+v0000000003510230_0 .net "X", 0 0, L_00000000039269f0; alias, 1 drivers
+S_00000000034d4b00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039268a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f8a0, L_000000000391c7a0, L_00000000039263d0;
+L_00000000039269f0 .functor BUF 1, L_00000000039268a0, C4<0>, C4<0>, C4<0>;
+v000000000350ecf0_0 .net "A0", 0 0, L_000000000391f8a0; alias, 1 drivers
+v000000000350fe70_0 .net "A1", 0 0, L_000000000391c7a0; alias, 1 drivers
+v000000000350f790_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386a7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350e930_0 .net8 "VGND", 0 0, L_000000000386a7a0; 1 drivers, strength-aware
+L_000000000386a0a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350ea70_0 .net8 "VNB", 0 0, L_000000000386a0a0; 1 drivers, strength-aware
+L_0000000003869d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003510870_0 .net8 "VPB", 0 0, L_0000000003869d90; 1 drivers, strength-aware
+L_000000000386a8f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003510b90_0 .net8 "VPWR", 0 0, L_000000000386a8f0; 1 drivers, strength-aware
+v000000000350f1f0_0 .net "X", 0 0, L_00000000039269f0; alias, 1 drivers
+v000000000350fdd0_0 .net "mux_2to10_out_X", 0 0, L_00000000039268a0; 1 drivers
+S_00000000034d4980 .scope module, "_373_" "sky130_fd_sc_hd__mux2_1" 3 1119, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003510050_0 .net "A0", 0 0, L_00000000039269f0; alias, 1 drivers
+v000000000350f3d0_0 .net "A1", 0 0, L_0000000003926de0; alias, 1 drivers
+v0000000003510190_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386b290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350ed90_0 .net8 "VGND", 0 0, L_000000000386b290; 1 drivers, strength-aware
+L_000000000386a180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350f650_0 .net8 "VNB", 0 0, L_000000000386a180; 1 drivers, strength-aware
+L_000000000386b450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003510eb0_0 .net8 "VPB", 0 0, L_000000000386b450; 1 drivers, strength-aware
+L_000000000386a1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350e9d0_0 .net8 "VPWR", 0 0, L_000000000386a1f0; 1 drivers, strength-aware
+v00000000035109b0_0 .net "X", 0 0, L_0000000003925aa0; alias, 1 drivers
+S_00000000034d2580 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d4980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926a60 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039269f0, L_0000000003926de0, L_000000000391fc90;
+L_0000000003925aa0 .functor BUF 1, L_0000000003926a60, C4<0>, C4<0>, C4<0>;
+v000000000350ffb0_0 .net "A0", 0 0, L_00000000039269f0; alias, 1 drivers
+v000000000350ef70_0 .net "A1", 0 0, L_0000000003926de0; alias, 1 drivers
+v000000000350f510_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386a810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350f0b0_0 .net8 "VGND", 0 0, L_000000000386a810; 1 drivers, strength-aware
+L_000000000386b300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350f8d0_0 .net8 "VNB", 0 0, L_000000000386b300; 1 drivers, strength-aware
+L_000000000386cdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035102d0_0 .net8 "VPB", 0 0, L_000000000386cdb0; 1 drivers, strength-aware
+L_000000000386b990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003510910_0 .net8 "VPWR", 0 0, L_000000000386b990; 1 drivers, strength-aware
+v000000000350fbf0_0 .net "X", 0 0, L_0000000003925aa0; alias, 1 drivers
+v0000000003510370_0 .net "mux_2to10_out_X", 0 0, L_0000000003926a60; 1 drivers
+S_00000000034d1980 .scope module, "_374_" "sky130_fd_sc_hd__mux2_1" 3 1125, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000035105f0_0 .net "A0", 0 0, L_0000000003927c50; alias, 1 drivers
+v0000000003510730_0 .net "A1", 0 0, L_0000000003925aa0; alias, 1 drivers
+v0000000003510690_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386b7d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003510af0_0 .net8 "VGND", 0 0, L_000000000386b7d0; 1 drivers, strength-aware
+L_000000000386c090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003510c30_0 .net8 "VNB", 0 0, L_000000000386c090; 1 drivers, strength-aware
+L_000000000386c100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350ebb0_0 .net8 "VPB", 0 0, L_000000000386c100; 1 drivers, strength-aware
+L_000000000386c250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350ec50_0 .net8 "VPWR", 0 0, L_000000000386c250; 1 drivers, strength-aware
+v000000000350f470_0 .net "X", 0 0, L_0000000003925db0; alias, 1 drivers
+S_00000000034d1800 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925bf0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927c50, L_0000000003925aa0, L_000000000391eaa0;
+L_0000000003925db0 .functor BUF 1, L_0000000003925bf0, C4<0>, C4<0>, C4<0>;
+v0000000003510410_0 .net "A0", 0 0, L_0000000003927c50; alias, 1 drivers
+v0000000003510d70_0 .net "A1", 0 0, L_0000000003925aa0; alias, 1 drivers
+v000000000350f290_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386bca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000350f330_0 .net8 "VGND", 0 0, L_000000000386bca0; 1 drivers, strength-aware
+L_000000000386c2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003510a50_0 .net8 "VNB", 0 0, L_000000000386c2c0; 1 drivers, strength-aware
+L_000000000386c480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000350f010_0 .net8 "VPB", 0 0, L_000000000386c480; 1 drivers, strength-aware
+L_000000000386c330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035104b0_0 .net8 "VPWR", 0 0, L_000000000386c330; 1 drivers, strength-aware
+v0000000003510cd0_0 .net "X", 0 0, L_0000000003925db0; alias, 1 drivers
+v0000000003510550_0 .net "mux_2to10_out_X", 0 0, L_0000000003925bf0; 1 drivers
+S_00000000034d2700 .scope module, "_375_" "sky130_fd_sc_hd__mux2_1" 3 1131, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000035123f0_0 .net "A0", 0 0, L_0000000003925db0; alias, 1 drivers
+v0000000003511590_0 .net "A1", 0 0, L_00000000039232d0; alias, 1 drivers
+v0000000003511e50_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386bd10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035131b0_0 .net8 "VGND", 0 0, L_000000000386bd10; 1 drivers, strength-aware
+L_000000000386bd80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035116d0_0 .net8 "VNB", 0 0, L_000000000386bd80; 1 drivers, strength-aware
+L_000000000386c790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512fd0_0 .net8 "VPB", 0 0, L_000000000386c790; 1 drivers, strength-aware
+L_000000000386ce20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035134d0_0 .net8 "VPWR", 0 0, L_000000000386ce20; 1 drivers, strength-aware
+v0000000003512530_0 .net "X", 0 0, L_0000000003925f70; alias, 1 drivers
+S_00000000034d1b00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925f00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925db0, L_00000000039232d0, L_0000000003920e80;
+L_0000000003925f70 .functor BUF 1, L_0000000003925f00, C4<0>, C4<0>, C4<0>;
+v000000000350f5b0_0 .net "A0", 0 0, L_0000000003925db0; alias, 1 drivers
+v000000000350f6f0_0 .net "A1", 0 0, L_00000000039232d0; alias, 1 drivers
+v0000000003512030_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386ce90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003511f90_0 .net8 "VGND", 0 0, L_000000000386ce90; 1 drivers, strength-aware
+L_000000000386cfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035128f0_0 .net8 "VNB", 0 0, L_000000000386cfe0; 1 drivers, strength-aware
+L_000000000386c410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512210_0 .net8 "VPB", 0 0, L_000000000386c410; 1 drivers, strength-aware
+L_000000000386bdf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512b70_0 .net8 "VPWR", 0 0, L_000000000386bdf0; 1 drivers, strength-aware
+v0000000003511450_0 .net "X", 0 0, L_0000000003925f70; alias, 1 drivers
+v00000000035114f0_0 .net "mux_2to10_out_X", 0 0, L_0000000003925f00; 1 drivers
+S_00000000034d1c80 .scope module, "_376_" "sky130_fd_sc_hd__mux2_1" 3 1137, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003513430_0 .net "A0", 0 0, L_00000000039221c0; alias, 1 drivers
+v00000000035136b0_0 .net "A1", 0 0, L_000000000391e4f0; alias, 1 drivers
+v0000000003511810_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386ca30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035125d0_0 .net8 "VGND", 0 0, L_000000000386ca30; 1 drivers, strength-aware
+L_000000000386ba00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003512cb0_0 .net8 "VNB", 0 0, L_000000000386ba00; 1 drivers, strength-aware
+L_000000000386c170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512350_0 .net8 "VPB", 0 0, L_000000000386c170; 1 drivers, strength-aware
+L_000000000386d050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035111d0_0 .net8 "VPWR", 0 0, L_000000000386d050; 1 drivers, strength-aware
+v00000000035132f0_0 .net "X", 0 0, L_0000000003926050; alias, 1 drivers
+S_00000000034d4e00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003925fe0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039221c0, L_000000000391e4f0, L_00000000039263d0;
+L_0000000003926050 .functor BUF 1, L_0000000003925fe0, C4<0>, C4<0>, C4<0>;
+v0000000003513570_0 .net "A0", 0 0, L_00000000039221c0; alias, 1 drivers
+v0000000003511950_0 .net "A1", 0 0, L_000000000391e4f0; alias, 1 drivers
+v00000000035118b0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386c1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003513070_0 .net8 "VGND", 0 0, L_000000000386c1e0; 1 drivers, strength-aware
+L_000000000386ba70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003511a90_0 .net8 "VNB", 0 0, L_000000000386ba70; 1 drivers, strength-aware
+L_000000000386b530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512c10_0 .net8 "VPB", 0 0, L_000000000386b530; 1 drivers, strength-aware
+L_000000000386be60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003513610_0 .net8 "VPWR", 0 0, L_000000000386be60; 1 drivers, strength-aware
+v0000000003512990_0 .net "X", 0 0, L_0000000003926050; alias, 1 drivers
+v0000000003512490_0 .net "mux_2to10_out_X", 0 0, L_0000000003925fe0; 1 drivers
+S_00000000034d3600 .scope module, "_377_" "sky130_fd_sc_hd__mux2_1" 3 1143, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003513110_0 .net "A0", 0 0, L_0000000003925250; alias, 1 drivers
+v00000000035113b0_0 .net "A1", 0 0, L_0000000003926c20; alias, 1 drivers
+v0000000003512170_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386bae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003511630_0 .net8 "VGND", 0 0, L_000000000386bae0; 1 drivers, strength-aware
+L_000000000386cf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035137f0_0 .net8 "VNB", 0 0, L_000000000386cf70; 1 drivers, strength-aware
+L_000000000386bed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003511bd0_0 .net8 "VPB", 0 0, L_000000000386bed0; 1 drivers, strength-aware
+L_000000000386bf40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512df0_0 .net8 "VPWR", 0 0, L_000000000386bf40; 1 drivers, strength-aware
+v0000000003512e90_0 .net "X", 0 0, L_0000000003926210; alias, 1 drivers
+S_00000000034d2880 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926130 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925250, L_0000000003926c20, L_000000000391fc90;
+L_0000000003926210 .functor BUF 1, L_0000000003926130, C4<0>, C4<0>, C4<0>;
+v0000000003512670_0 .net "A0", 0 0, L_0000000003925250; alias, 1 drivers
+v00000000035119f0_0 .net "A1", 0 0, L_0000000003926c20; alias, 1 drivers
+v0000000003512710_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386bc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003513390_0 .net8 "VGND", 0 0, L_000000000386bc30; 1 drivers, strength-aware
+L_000000000386c950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003513750_0 .net8 "VNB", 0 0, L_000000000386c950; 1 drivers, strength-aware
+L_000000000386bfb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035127b0_0 .net8 "VPB", 0 0, L_000000000386bfb0; 1 drivers, strength-aware
+L_000000000386c720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512d50_0 .net8 "VPWR", 0 0, L_000000000386c720; 1 drivers, strength-aware
+v0000000003513250_0 .net "X", 0 0, L_0000000003926210; alias, 1 drivers
+v0000000003511b30_0 .net "mux_2to10_out_X", 0 0, L_0000000003926130; 1 drivers
+S_00000000034d3780 .scope module, "_378_" "sky130_fd_sc_hd__mux2_1" 3 1149, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003511c70_0 .net "A0", 0 0, L_000000000391c7a0; alias, 1 drivers
+v0000000003512850_0 .net "A1", 0 0, L_000000000391f600; alias, 1 drivers
+v0000000003512a30_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386b4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003511ef0_0 .net8 "VGND", 0 0, L_000000000386b4c0; 1 drivers, strength-aware
+L_000000000386c5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003512ad0_0 .net8 "VNB", 0 0, L_000000000386c5d0; 1 drivers, strength-aware
+L_000000000386b8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003512f30_0 .net8 "VPB", 0 0, L_000000000386b8b0; 1 drivers, strength-aware
+L_000000000386b760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003513bb0_0 .net8 "VPWR", 0 0, L_000000000386b760; 1 drivers, strength-aware
+v0000000003515ff0_0 .net "X", 0 0, L_00000000039270f0; alias, 1 drivers
+S_00000000034d3000 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039262f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391c7a0, L_000000000391f600, L_00000000039263d0;
+L_00000000039270f0 .functor BUF 1, L_00000000039262f0, C4<0>, C4<0>, C4<0>;
+v0000000003513890_0 .net "A0", 0 0, L_000000000391c7a0; alias, 1 drivers
+v0000000003511770_0 .net "A1", 0 0, L_000000000391f600; alias, 1 drivers
+v00000000035120d0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386c800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035122b0_0 .net8 "VGND", 0 0, L_000000000386c800; 1 drivers, strength-aware
+L_000000000386b840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003511d10_0 .net8 "VNB", 0 0, L_000000000386b840; 1 drivers, strength-aware
+L_000000000386cc60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003511130_0 .net8 "VPB", 0 0, L_000000000386cc60; 1 drivers, strength-aware
+L_000000000386c9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003511db0_0 .net8 "VPWR", 0 0, L_000000000386c9c0; 1 drivers, strength-aware
+v0000000003511270_0 .net "X", 0 0, L_00000000039270f0; alias, 1 drivers
+v0000000003511310_0 .net "mux_2to10_out_X", 0 0, L_00000000039262f0; 1 drivers
+S_00000000034d2400 .scope module, "_379_" "sky130_fd_sc_hd__mux2_1" 3 1155, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003515370_0 .net "A0", 0 0, L_0000000003926210; alias, 1 drivers
+v0000000003514290_0 .net "A1", 0 0, L_0000000003927c50; alias, 1 drivers
+v0000000003515690_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386b920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035141f0_0 .net8 "VGND", 0 0, L_000000000386b920; 1 drivers, strength-aware
+L_000000000386cf00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003513930_0 .net8 "VNB", 0 0, L_000000000386cf00; 1 drivers, strength-aware
+L_000000000386b680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515e10_0 .net8 "VPB", 0 0, L_000000000386b680; 1 drivers, strength-aware
+L_000000000386ccd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003513f70_0 .net8 "VPWR", 0 0, L_000000000386ccd0; 1 drivers, strength-aware
+v0000000003514330_0 .net "X", 0 0, L_0000000003927a90; alias, 1 drivers
+S_00000000034d3480 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926ec0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926210, L_0000000003927c50, L_000000000391eaa0;
+L_0000000003927a90 .functor BUF 1, L_0000000003926ec0, C4<0>, C4<0>, C4<0>;
+v0000000003514150_0 .net "A0", 0 0, L_0000000003926210; alias, 1 drivers
+v0000000003514dd0_0 .net "A1", 0 0, L_0000000003927c50; alias, 1 drivers
+v00000000035140b0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386c3a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514ab0_0 .net8 "VGND", 0 0, L_000000000386c3a0; 1 drivers, strength-aware
+L_000000000386c640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514bf0_0 .net8 "VNB", 0 0, L_000000000386c640; 1 drivers, strength-aware
+L_000000000386bb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515d70_0 .net8 "VPB", 0 0, L_000000000386bb50; 1 drivers, strength-aware
+L_000000000386c020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035159b0_0 .net8 "VPWR", 0 0, L_000000000386c020; 1 drivers, strength-aware
+v00000000035155f0_0 .net "X", 0 0, L_0000000003927a90; alias, 1 drivers
+v0000000003515cd0_0 .net "mux_2to10_out_X", 0 0, L_0000000003926ec0; 1 drivers
+S_00000000034d2a00 .scope module, "_380_" "sky130_fd_sc_hd__mux2_1" 3 1161, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003513cf0_0 .net "A0", 0 0, L_0000000003927da0; alias, 1 drivers
+v0000000003514e70_0 .net "A1", 0 0, L_00000000039287b0; alias, 1 drivers
+v0000000003514790_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386c4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514f10_0 .net8 "VGND", 0 0, L_000000000386c4f0; 1 drivers, strength-aware
+L_000000000386c870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514470_0 .net8 "VNB", 0 0, L_000000000386c870; 1 drivers, strength-aware
+L_000000000386c6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035139d0_0 .net8 "VPB", 0 0, L_000000000386c6b0; 1 drivers, strength-aware
+L_000000000386bbc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515eb0_0 .net8 "VPWR", 0 0, L_000000000386bbc0; 1 drivers, strength-aware
+v0000000003513c50_0 .net "X", 0 0, L_0000000003927c50; alias, 1 drivers
+S_00000000034d2b80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2a00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926fa0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927da0, L_00000000039287b0, L_000000000391fc90;
+L_0000000003927c50 .functor BUF 1, L_0000000003926fa0, C4<0>, C4<0>, C4<0>;
+v0000000003514fb0_0 .net "A0", 0 0, L_0000000003927da0; alias, 1 drivers
+v0000000003515f50_0 .net "A1", 0 0, L_00000000039287b0; alias, 1 drivers
+v0000000003513ed0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386caa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514d30_0 .net8 "VGND", 0 0, L_000000000386caa0; 1 drivers, strength-aware
+L_000000000386c560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035157d0_0 .net8 "VNB", 0 0, L_000000000386c560; 1 drivers, strength-aware
+L_000000000386c8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003514510_0 .net8 "VPB", 0 0, L_000000000386c8e0; 1 drivers, strength-aware
+L_000000000386cb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035143d0_0 .net8 "VPWR", 0 0, L_000000000386cb10; 1 drivers, strength-aware
+v0000000003515730_0 .net "X", 0 0, L_0000000003927c50; alias, 1 drivers
+v00000000035154b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003926fa0; 1 drivers
+S_00000000034d1e00 .scope module, "_381_" "sky130_fd_sc_hd__mux2_1" 3 1167, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003515050_0 .net "A0", 0 0, L_000000000391f1a0; alias, 1 drivers
+v0000000003515910_0 .net "A1", 0 0, L_00000000039221c0; alias, 1 drivers
+v00000000035148d0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386cb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514970_0 .net8 "VGND", 0 0, L_000000000386cb80; 1 drivers, strength-aware
+L_000000000386cbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514b50_0 .net8 "VNB", 0 0, L_000000000386cbf0; 1 drivers, strength-aware
+L_000000000386cd40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003514c90_0 .net8 "VPB", 0 0, L_000000000386cd40; 1 drivers, strength-aware
+L_000000000386b5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515230_0 .net8 "VPWR", 0 0, L_000000000386b5a0; 1 drivers, strength-aware
+v0000000003515a50_0 .net "X", 0 0, L_0000000003927da0; alias, 1 drivers
+S_00000000034d1380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927400 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f1a0, L_00000000039221c0, L_00000000039263d0;
+L_0000000003927da0 .functor BUF 1, L_0000000003927400, C4<0>, C4<0>, C4<0>;
+v0000000003514830_0 .net "A0", 0 0, L_000000000391f1a0; alias, 1 drivers
+v0000000003515870_0 .net "A1", 0 0, L_00000000039221c0; alias, 1 drivers
+v00000000035145b0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386b610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003514650_0 .net8 "VGND", 0 0, L_000000000386b610; 1 drivers, strength-aware
+L_000000000386b6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003515550_0 .net8 "VNB", 0 0, L_000000000386b6f0; 1 drivers, strength-aware
+L_000000000386e4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003514a10_0 .net8 "VPB", 0 0, L_000000000386e4e0; 1 drivers, strength-aware
+L_000000000386d280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515b90_0 .net8 "VPWR", 0 0, L_000000000386d280; 1 drivers, strength-aware
+v0000000003513d90_0 .net "X", 0 0, L_0000000003927da0; alias, 1 drivers
+v00000000035146f0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927400; 1 drivers
+S_00000000034d1500 .scope module, "_382_" "sky130_fd_sc_hd__mux2_1" 3 1173, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003513a70_0 .net "A0", 0 0, L_0000000003920cc0; alias, 1 drivers
+v0000000003513b10_0 .net "A1", 0 0, L_000000000391f1a0; alias, 1 drivers
+v0000000003518750_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386eb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518570_0 .net8 "VGND", 0 0, L_000000000386eb70; 1 drivers, strength-aware
+L_000000000386d0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516950_0 .net8 "VNB", 0 0, L_000000000386d0c0; 1 drivers, strength-aware
+L_000000000386d130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517670_0 .net8 "VPB", 0 0, L_000000000386d130; 1 drivers, strength-aware
+L_000000000386df30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035169f0_0 .net8 "VPWR", 0 0, L_000000000386df30; 1 drivers, strength-aware
+v0000000003516630_0 .net "X", 0 0, L_00000000039282e0; alias, 1 drivers
+S_00000000034d3c00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928200 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003920cc0, L_000000000391f1a0, L_00000000039263d0;
+L_00000000039282e0 .functor BUF 1, L_0000000003928200, C4<0>, C4<0>, C4<0>;
+v0000000003513e30_0 .net "A0", 0 0, L_0000000003920cc0; alias, 1 drivers
+v0000000003514010_0 .net "A1", 0 0, L_000000000391f1a0; alias, 1 drivers
+v00000000035150f0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386dde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003515af0_0 .net8 "VGND", 0 0, L_000000000386dde0; 1 drivers, strength-aware
+L_000000000386e2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003515190_0 .net8 "VNB", 0 0, L_000000000386e2b0; 1 drivers, strength-aware
+L_000000000386e320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003515c30_0 .net8 "VPB", 0 0, L_000000000386e320; 1 drivers, strength-aware
+L_000000000386e940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003516090_0 .net8 "VPWR", 0 0, L_000000000386e940; 1 drivers, strength-aware
+v00000000035152d0_0 .net "X", 0 0, L_00000000039282e0; alias, 1 drivers
+v0000000003515410_0 .net "mux_2to10_out_X", 0 0, L_0000000003928200; 1 drivers
+S_00000000034d3900 .scope module, "_383_" "sky130_fd_sc_hd__mux2_1" 3 1179, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003516a90_0 .net "A0", 0 0, L_000000000391f600; alias, 1 drivers
+v0000000003518610_0 .net "A1", 0 0, L_0000000003920cc0; alias, 1 drivers
+v0000000003518890_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386d980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035172b0_0 .net8 "VGND", 0 0, L_000000000386d980; 1 drivers, strength-aware
+L_000000000386e1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516bd0_0 .net8 "VNB", 0 0, L_000000000386e1d0; 1 drivers, strength-aware
+L_000000000386e390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517030_0 .net8 "VPB", 0 0, L_000000000386e390; 1 drivers, strength-aware
+L_000000000386e550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517710_0 .net8 "VPWR", 0 0, L_000000000386e550; 1 drivers, strength-aware
+v00000000035177b0_0 .net "X", 0 0, L_0000000003926de0; alias, 1 drivers
+S_00000000034d3d80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3900;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927320 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391f600, L_0000000003920cc0, L_00000000039263d0;
+L_0000000003926de0 .functor BUF 1, L_0000000003927320, C4<0>, C4<0>, C4<0>;
+v0000000003516130_0 .net "A0", 0 0, L_000000000391f600; alias, 1 drivers
+v0000000003517210_0 .net "A1", 0 0, L_0000000003920cc0; alias, 1 drivers
+v0000000003516810_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386ea20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035175d0_0 .net8 "VGND", 0 0, L_000000000386ea20; 1 drivers, strength-aware
+L_000000000386d2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003517b70_0 .net8 "VNB", 0 0, L_000000000386d2f0; 1 drivers, strength-aware
+L_000000000386d3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517350_0 .net8 "VPB", 0 0, L_000000000386d3d0; 1 drivers, strength-aware
+L_000000000386db40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035161d0_0 .net8 "VPWR", 0 0, L_000000000386db40; 1 drivers, strength-aware
+v00000000035182f0_0 .net "X", 0 0, L_0000000003926de0; alias, 1 drivers
+v0000000003517d50_0 .net "mux_2to10_out_X", 0 0, L_0000000003927320; 1 drivers
+S_00000000034d2d00 .scope module, "_384_" "sky130_fd_sc_hd__mux2_1" 3 1185, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003518390_0 .net "A0", 0 0, L_0000000003927080; alias, 1 drivers
+v00000000035187f0_0 .net "A1", 0 0, L_0000000003926b40; alias, 1 drivers
+v0000000003516db0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386d440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035166d0_0 .net8 "VGND", 0 0, L_000000000386d440; 1 drivers, strength-aware
+L_000000000386e160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516ef0_0 .net8 "VNB", 0 0, L_000000000386e160; 1 drivers, strength-aware
+L_000000000386ebe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003516770_0 .net8 "VPB", 0 0, L_000000000386ebe0; 1 drivers, strength-aware
+L_000000000386dfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035178f0_0 .net8 "VPWR", 0 0, L_000000000386dfa0; 1 drivers, strength-aware
+v00000000035170d0_0 .net "X", 0 0, L_0000000003928270; alias, 1 drivers
+S_00000000034d4080 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2d00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927b70 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927080, L_0000000003926b40, L_000000000391eaa0;
+L_0000000003928270 .functor BUF 1, L_0000000003927b70, C4<0>, C4<0>, C4<0>;
+v00000000035168b0_0 .net "A0", 0 0, L_0000000003927080; alias, 1 drivers
+v0000000003516d10_0 .net "A1", 0 0, L_0000000003926b40; alias, 1 drivers
+v0000000003516b30_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386d360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003517530_0 .net8 "VGND", 0 0, L_000000000386d360; 1 drivers, strength-aware
+L_000000000386e080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516e50_0 .net8 "VNB", 0 0, L_000000000386e080; 1 drivers, strength-aware
+L_000000000386e010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517df0_0 .net8 "VPB", 0 0, L_000000000386e010; 1 drivers, strength-aware
+L_000000000386e9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003516270_0 .net8 "VPWR", 0 0, L_000000000386e9b0; 1 drivers, strength-aware
+v0000000003516f90_0 .net "X", 0 0, L_0000000003928270; alias, 1 drivers
+v0000000003517850_0 .net "mux_2to10_out_X", 0 0, L_0000000003927b70; 1 drivers
+S_00000000034d2e80 .scope module, "_385_" "sky130_fd_sc_hd__mux2_1" 3 1191, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003517fd0_0 .net "A0", 0 0, L_0000000003926440; alias, 1 drivers
+v0000000003517a30_0 .net "A1", 0 0, L_00000000039260c0; alias, 1 drivers
+v0000000003517c10_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386dec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516450_0 .net8 "VGND", 0 0, L_000000000386dec0; 1 drivers, strength-aware
+L_000000000386d590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003516590_0 .net8 "VNB", 0 0, L_000000000386d590; 1 drivers, strength-aware
+L_000000000386d830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517ad0_0 .net8 "VPB", 0 0, L_000000000386d830; 1 drivers, strength-aware
+L_000000000386d1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517cb0_0 .net8 "VPWR", 0 0, L_000000000386d1a0; 1 drivers, strength-aware
+v0000000003517e90_0 .net "X", 0 0, L_0000000003927470; alias, 1 drivers
+S_00000000034d3f00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d2e80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039271d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926440, L_00000000039260c0, L_000000000391eaa0;
+L_0000000003927470 .functor BUF 1, L_00000000039271d0, C4<0>, C4<0>, C4<0>;
+v0000000003518430_0 .net "A0", 0 0, L_0000000003926440; alias, 1 drivers
+v00000000035186b0_0 .net "A1", 0 0, L_00000000039260c0; alias, 1 drivers
+v0000000003516c70_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386dbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003517170_0 .net8 "VGND", 0 0, L_000000000386dbb0; 1 drivers, strength-aware
+L_000000000386e5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518110_0 .net8 "VNB", 0 0, L_000000000386e5c0; 1 drivers, strength-aware
+L_000000000386d4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035173f0_0 .net8 "VPB", 0 0, L_000000000386d4b0; 1 drivers, strength-aware
+L_000000000386ec50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003517490_0 .net8 "VPWR", 0 0, L_000000000386ec50; 1 drivers, strength-aware
+v0000000003517990_0 .net "X", 0 0, L_0000000003927470; alias, 1 drivers
+v00000000035164f0_0 .net "mux_2to10_out_X", 0 0, L_00000000039271d0; 1 drivers
+S_00000000034d3180 .scope module, "_386_" "sky130_fd_sc_hd__mux2_1" 3 1197, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003519a10_0 .net "A0", 0 0, L_00000000039287b0; alias, 1 drivers
+v0000000003519510_0 .net "A1", 0 0, L_0000000003925250; alias, 1 drivers
+v0000000003519790_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386d210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351a910_0 .net8 "VGND", 0 0, L_000000000386d210; 1 drivers, strength-aware
+L_000000000386d520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351ac30_0 .net8 "VNB", 0 0, L_000000000386d520; 1 drivers, strength-aware
+L_000000000386e0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003519fb0_0 .net8 "VPB", 0 0, L_000000000386e0f0; 1 drivers, strength-aware
+L_000000000386de50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351a5f0_0 .net8 "VPWR", 0 0, L_000000000386de50; 1 drivers, strength-aware
+v000000000351acd0_0 .net "X", 0 0, L_0000000003927080; alias, 1 drivers
+S_00000000034d1080 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927a20 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039287b0, L_0000000003925250, L_000000000391fc90;
+L_0000000003927080 .functor BUF 1, L_0000000003927a20, C4<0>, C4<0>, C4<0>;
+v0000000003517f30_0 .net "A0", 0 0, L_00000000039287b0; alias, 1 drivers
+v0000000003518070_0 .net "A1", 0 0, L_0000000003925250; alias, 1 drivers
+v00000000035181b0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386e400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518250_0 .net8 "VGND", 0 0, L_000000000386e400; 1 drivers, strength-aware
+L_000000000386e470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035184d0_0 .net8 "VNB", 0 0, L_000000000386e470; 1 drivers, strength-aware
+L_000000000386ea90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003516310_0 .net8 "VPB", 0 0, L_000000000386ea90; 1 drivers, strength-aware
+L_000000000386d9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035163b0_0 .net8 "VPWR", 0 0, L_000000000386d9f0; 1 drivers, strength-aware
+v000000000351ad70_0 .net "X", 0 0, L_0000000003927080; alias, 1 drivers
+v0000000003519150_0 .net "mux_2to10_out_X", 0 0, L_0000000003927a20; 1 drivers
+S_00000000034d3300 .scope module, "_387_" "sky130_fd_sc_hd__mux2_1" 3 1203, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351a190_0 .net "A0", 0 0, L_0000000003927780; alias, 1 drivers
+v0000000003519e70_0 .net "A1", 0 0, L_0000000003925cd0; alias, 1 drivers
+v000000000351a410_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386e240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351aa50_0 .net8 "VGND", 0 0, L_000000000386e240; 1 drivers, strength-aware
+L_000000000386e630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003519290_0 .net8 "VNB", 0 0, L_000000000386e630; 1 drivers, strength-aware
+L_000000000386e6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351a2d0_0 .net8 "VPB", 0 0, L_000000000386e6a0; 1 drivers, strength-aware
+L_000000000386eb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351a370_0 .net8 "VPWR", 0 0, L_000000000386eb00; 1 drivers, strength-aware
+v0000000003519330_0 .net "X", 0 0, L_0000000003928350; alias, 1 drivers
+S_00000000034d4380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d3300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927f60 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927780, L_0000000003925cd0, L_0000000003920e80;
+L_0000000003928350 .functor BUF 1, L_0000000003927f60, C4<0>, C4<0>, C4<0>;
+v000000000351aaf0_0 .net "A0", 0 0, L_0000000003927780; alias, 1 drivers
+v000000000351a9b0_0 .net "A1", 0 0, L_0000000003925cd0; alias, 1 drivers
+v0000000003518a70_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386d600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351a0f0_0 .net8 "VGND", 0 0, L_000000000386d600; 1 drivers, strength-aware
+L_000000000386d670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518c50_0 .net8 "VNB", 0 0, L_000000000386d670; 1 drivers, strength-aware
+L_000000000386dc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035191f0_0 .net8 "VPB", 0 0, L_000000000386dc20; 1 drivers, strength-aware
+L_000000000386d6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003519ab0_0 .net8 "VPWR", 0 0, L_000000000386d6e0; 1 drivers, strength-aware
+v0000000003519dd0_0 .net "X", 0 0, L_0000000003928350; alias, 1 drivers
+v00000000035190b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927f60; 1 drivers
+S_00000000034d1200 .scope module, "_388_" "sky130_fd_sc_hd__mux2_1" 3 1209, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003518930_0 .net "A0", 0 0, L_0000000003925950; alias, 1 drivers
+v0000000003519bf0_0 .net "A1", 0 0, L_0000000003926830; alias, 1 drivers
+v0000000003519650_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386e710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035196f0_0 .net8 "VGND", 0 0, L_000000000386e710; 1 drivers, strength-aware
+L_000000000386d750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518b10_0 .net8 "VNB", 0 0, L_000000000386d750; 1 drivers, strength-aware
+L_000000000386e780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003518e30_0 .net8 "VPB", 0 0, L_000000000386e780; 1 drivers, strength-aware
+L_000000000386d7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003519c90_0 .net8 "VPWR", 0 0, L_000000000386d7c0; 1 drivers, strength-aware
+v0000000003518cf0_0 .net "X", 0 0, L_0000000003927780; alias, 1 drivers
+S_00000000034d4500 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d1200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928120 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925950, L_0000000003926830, L_000000000391eaa0;
+L_0000000003927780 .functor BUF 1, L_0000000003928120, C4<0>, C4<0>, C4<0>;
+v00000000035193d0_0 .net "A0", 0 0, L_0000000003925950; alias, 1 drivers
+v000000000351ae10_0 .net "A1", 0 0, L_0000000003926830; alias, 1 drivers
+v000000000351a230_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386e7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003519f10_0 .net8 "VGND", 0 0, L_000000000386e7f0; 1 drivers, strength-aware
+L_000000000386e860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003519470_0 .net8 "VNB", 0 0, L_000000000386e860; 1 drivers, strength-aware
+L_000000000386d8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003519b50_0 .net8 "VPB", 0 0, L_000000000386d8a0; 1 drivers, strength-aware
+L_000000000386e8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035195b0_0 .net8 "VPWR", 0 0, L_000000000386e8d0; 1 drivers, strength-aware
+v0000000003519830_0 .net "X", 0 0, L_0000000003927780; alias, 1 drivers
+v000000000351ab90_0 .net "mux_2to10_out_X", 0 0, L_0000000003928120; 1 drivers
+S_00000000034d4680 .scope module, "_389_" "sky130_fd_sc_hd__mux2_1" 3 1215, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003519970_0 .net "A0", 0 0, L_00000000039220e0; alias, 1 drivers
+v000000000351a730_0 .net "A1", 0 0, L_0000000003927080; alias, 1 drivers
+v000000000351a7d0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386d910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035189d0_0 .net8 "VGND", 0 0, L_000000000386d910; 1 drivers, strength-aware
+L_000000000386da60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003518bb0_0 .net8 "VNB", 0 0, L_000000000386da60; 1 drivers, strength-aware
+L_000000000386dad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003518f70_0 .net8 "VPB", 0 0, L_000000000386dad0; 1 drivers, strength-aware
+L_000000000386dc90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351a870_0 .net8 "VPWR", 0 0, L_000000000386dc90; 1 drivers, strength-aware
+v000000000351b090_0 .net "X", 0 0, L_00000000039283c0; alias, 1 drivers
+S_00000000034d4800 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d4680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927390 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039220e0, L_0000000003927080, L_000000000391eaa0;
+L_00000000039283c0 .functor BUF 1, L_0000000003927390, C4<0>, C4<0>, C4<0>;
+v0000000003519d30_0 .net "A0", 0 0, L_00000000039220e0; alias, 1 drivers
+v00000000035198d0_0 .net "A1", 0 0, L_0000000003927080; alias, 1 drivers
+v000000000351a050_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_000000000386dd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351a4b0_0 .net8 "VGND", 0 0, L_000000000386dd00; 1 drivers, strength-aware
+L_000000000386dd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351aeb0_0 .net8 "VNB", 0 0, L_000000000386dd70; 1 drivers, strength-aware
+L_000000000386ff20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351af50_0 .net8 "VPB", 0 0, L_000000000386ff20; 1 drivers, strength-aware
+L_0000000003870770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351a690_0 .net8 "VPWR", 0 0, L_0000000003870770; 1 drivers, strength-aware
+v000000000351aff0_0 .net "X", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000351a550_0 .net "mux_2to10_out_X", 0 0, L_0000000003927390; 1 drivers
+S_00000000034d4c80 .scope module, "_390_" "sky130_fd_sc_hd__mux2_1" 3 1221, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351c670_0 .net "A0", 0 0, L_0000000003928660; alias, 1 drivers
+v000000000351bf90_0 .net "A1", 0 0, L_0000000003927010; alias, 1 drivers
+v000000000351d7f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386fdd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351b270_0 .net8 "VGND", 0 0, L_000000000386fdd0; 1 drivers, strength-aware
+L_000000000386f0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351b1d0_0 .net8 "VNB", 0 0, L_000000000386f0b0; 1 drivers, strength-aware
+L_000000000386ef60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351d390_0 .net8 "VPB", 0 0, L_000000000386ef60; 1 drivers, strength-aware
+L_000000000386ff90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351b9f0_0 .net8 "VPWR", 0 0, L_000000000386ff90; 1 drivers, strength-aware
+v000000000351c5d0_0 .net "X", 0 0, L_0000000003926d70; alias, 1 drivers
+S_00000000034d1680 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034d4c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039274e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003928660, L_0000000003927010, L_000000000391fc90;
+L_0000000003926d70 .functor BUF 1, L_00000000039274e0, C4<0>, C4<0>, C4<0>;
+v0000000003518d90_0 .net "A0", 0 0, L_0000000003928660; alias, 1 drivers
+v0000000003518ed0_0 .net "A1", 0 0, L_0000000003927010; alias, 1 drivers
+v0000000003519010_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386efd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351cfd0_0 .net8 "VGND", 0 0, L_000000000386efd0; 1 drivers, strength-aware
+L_0000000003870460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351c170_0 .net8 "VNB", 0 0, L_0000000003870460; 1 drivers, strength-aware
+L_00000000038701c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351b8b0_0 .net8 "VPB", 0 0, L_00000000038701c0; 1 drivers, strength-aware
+L_000000000386f120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351cf30_0 .net8 "VPWR", 0 0, L_000000000386f120; 1 drivers, strength-aware
+v000000000351ccb0_0 .net "X", 0 0, L_0000000003926d70; alias, 1 drivers
+v000000000351b950_0 .net "mux_2to10_out_X", 0 0, L_00000000039274e0; 1 drivers
+S_00000000034c7f00 .scope module, "_391_" "sky130_fd_sc_hd__mux2_1" 3 1227, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351c030_0 .net "A0", 0 0, L_000000000391aac0; alias, 1 drivers
+v000000000351b6d0_0 .net "A1", 0 0, L_000000000391bfc0; alias, 1 drivers
+v000000000351c850_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003870700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351b4f0_0 .net8 "VGND", 0 0, L_0000000003870700; 1 drivers, strength-aware
+L_000000000386ee80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d110_0 .net8 "VNB", 0 0, L_000000000386ee80; 1 drivers, strength-aware
+L_00000000038704d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351c0d0_0 .net8 "VPB", 0 0, L_00000000038704d0; 1 drivers, strength-aware
+L_000000000386fb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351c8f0_0 .net8 "VPWR", 0 0, L_000000000386fb30; 1 drivers, strength-aware
+v000000000351bc70_0 .net "X", 0 0, L_0000000003927010; alias, 1 drivers
+S_00000000034c8980 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927cc0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391aac0, L_000000000391bfc0, L_00000000039263d0;
+L_0000000003927010 .functor BUF 1, L_0000000003927cc0, C4<0>, C4<0>, C4<0>;
+v000000000351d070_0 .net "A0", 0 0, L_000000000391aac0; alias, 1 drivers
+v000000000351c210_0 .net "A1", 0 0, L_000000000391bfc0; alias, 1 drivers
+v000000000351c2b0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386fe40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351c710_0 .net8 "VGND", 0 0, L_000000000386fe40; 1 drivers, strength-aware
+L_000000000386f2e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351ca30_0 .net8 "VNB", 0 0, L_000000000386f2e0; 1 drivers, strength-aware
+L_000000000386f510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351cd50_0 .net8 "VPB", 0 0, L_000000000386f510; 1 drivers, strength-aware
+L_000000000386f740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351cc10_0 .net8 "VPWR", 0 0, L_000000000386f740; 1 drivers, strength-aware
+v000000000351d570_0 .net "X", 0 0, L_0000000003927010; alias, 1 drivers
+v000000000351c7b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927cc0; 1 drivers
+S_00000000034caf00 .scope module, "_392_" "sky130_fd_sc_hd__mux2_1" 3 1233, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351c350_0 .net "A0", 0 0, L_000000000391e4f0; alias, 1 drivers
+v000000000351b3b0_0 .net "A1", 0 0, L_000000000391f3d0; alias, 1 drivers
+v000000000351d4d0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003870000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351bb30_0 .net8 "VGND", 0 0, L_0000000003870000; 1 drivers, strength-aware
+L_000000000386feb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351bbd0_0 .net8 "VNB", 0 0, L_000000000386feb0; 1 drivers, strength-aware
+L_000000000386f040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351cdf0_0 .net8 "VPB", 0 0, L_000000000386f040; 1 drivers, strength-aware
+L_0000000003870230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351be50_0 .net8 "VPWR", 0 0, L_0000000003870230; 1 drivers, strength-aware
+v000000000351c490_0 .net "X", 0 0, L_00000000039287b0; alias, 1 drivers
+S_00000000034c6280 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034caf00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926f30 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391e4f0, L_000000000391f3d0, L_00000000039263d0;
+L_00000000039287b0 .functor BUF 1, L_0000000003926f30, C4<0>, C4<0>, C4<0>;
+v000000000351c3f0_0 .net "A0", 0 0, L_000000000391e4f0; alias, 1 drivers
+v000000000351b310_0 .net "A1", 0 0, L_000000000391f3d0; alias, 1 drivers
+v000000000351b810_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386f190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d6b0_0 .net8 "VGND", 0 0, L_000000000386f190; 1 drivers, strength-aware
+L_0000000003870070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d890_0 .net8 "VNB", 0 0, L_0000000003870070; 1 drivers, strength-aware
+L_00000000038700e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351ba90_0 .net8 "VPB", 0 0, L_00000000038700e0; 1 drivers, strength-aware
+L_00000000038702a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351cb70_0 .net8 "VPWR", 0 0, L_00000000038702a0; 1 drivers, strength-aware
+v000000000351b590_0 .net "X", 0 0, L_00000000039287b0; alias, 1 drivers
+v000000000351b770_0 .net "mux_2to10_out_X", 0 0, L_0000000003926f30; 1 drivers
+S_00000000034c8200 .scope module, "_393_" "sky130_fd_sc_hd__mux2_1" 3 1239, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351cad0_0 .net "A0", 0 0, L_000000000391d7d0; alias, 1 drivers
+v000000000351bef0_0 .net "A1", 0 0, L_0000000003921580; alias, 1 drivers
+v000000000351ce90_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003870150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d2f0_0 .net8 "VGND", 0 0, L_0000000003870150; 1 drivers, strength-aware
+L_000000000386f890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d430_0 .net8 "VNB", 0 0, L_000000000386f890; 1 drivers, strength-aware
+L_0000000003870310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351c530_0 .net8 "VPB", 0 0, L_0000000003870310; 1 drivers, strength-aware
+L_000000000386f580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351d610_0 .net8 "VPWR", 0 0, L_000000000386f580; 1 drivers, strength-aware
+v000000000351ded0_0 .net "X", 0 0, L_0000000003928430; alias, 1 drivers
+S_00000000034c8b00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c8200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928580 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391d7d0, L_0000000003921580, L_00000000039263d0;
+L_0000000003928430 .functor BUF 1, L_0000000003928580, C4<0>, C4<0>, C4<0>;
+v000000000351b630_0 .net "A0", 0 0, L_000000000391d7d0; alias, 1 drivers
+v000000000351d1b0_0 .net "A1", 0 0, L_0000000003921580; alias, 1 drivers
+v000000000351bd10_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386f7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351bdb0_0 .net8 "VGND", 0 0, L_000000000386f7b0; 1 drivers, strength-aware
+L_0000000003870380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d250_0 .net8 "VNB", 0 0, L_0000000003870380; 1 drivers, strength-aware
+L_00000000038703f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351b130_0 .net8 "VPB", 0 0, L_00000000038703f0; 1 drivers, strength-aware
+L_000000000386f900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351d750_0 .net8 "VPWR", 0 0, L_000000000386f900; 1 drivers, strength-aware
+v000000000351c990_0 .net "X", 0 0, L_0000000003928430; alias, 1 drivers
+v000000000351b450_0 .net "mux_2to10_out_X", 0 0, L_0000000003928580; 1 drivers
+S_00000000034ca600 .scope module, "_394_" "sky130_fd_sc_hd__mux2_1" 3 1245, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351e510_0 .net "A0", 0 0, L_000000000391dca0; alias, 1 drivers
+v000000000351e0b0_0 .net "A1", 0 0, L_000000000391cb20; alias, 1 drivers
+v000000000351e830_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003870540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351e790_0 .net8 "VGND", 0 0, L_0000000003870540; 1 drivers, strength-aware
+L_000000000386f5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351f0f0_0 .net8 "VNB", 0 0, L_000000000386f5f0; 1 drivers, strength-aware
+L_000000000386f820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351ea10_0 .net8 "VPB", 0 0, L_000000000386f820; 1 drivers, strength-aware
+L_00000000038705b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351f370_0 .net8 "VPWR", 0 0, L_00000000038705b0; 1 drivers, strength-aware
+v000000000351dc50_0 .net "X", 0 0, L_00000000039280b0; alias, 1 drivers
+S_00000000034c9400 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034ca600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927fd0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391dca0, L_000000000391cb20, L_000000000391fc90;
+L_00000000039280b0 .functor BUF 1, L_0000000003927fd0, C4<0>, C4<0>, C4<0>;
+v000000000351e5b0_0 .net "A0", 0 0, L_000000000391dca0; alias, 1 drivers
+v000000000351ef10_0 .net "A1", 0 0, L_000000000391cb20; alias, 1 drivers
+v000000000351f5f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_000000000386eef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351f550_0 .net8 "VGND", 0 0, L_000000000386eef0; 1 drivers, strength-aware
+L_00000000038707e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351f410_0 .net8 "VNB", 0 0, L_00000000038707e0; 1 drivers, strength-aware
+L_000000000386ecc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351e290_0 .net8 "VPB", 0 0, L_000000000386ecc0; 1 drivers, strength-aware
+L_000000000386ed30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351e330_0 .net8 "VPWR", 0 0, L_000000000386ed30; 1 drivers, strength-aware
+v000000000351e970_0 .net "X", 0 0, L_00000000039280b0; alias, 1 drivers
+v000000000351f910_0 .net "mux_2to10_out_X", 0 0, L_0000000003927fd0; 1 drivers
+S_00000000034c8500 .scope module, "_395_" "sky130_fd_sc_hd__mux2_1" 3 1251, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351eab0_0 .net "A0", 0 0, L_000000000391ca40; alias, 1 drivers
+v000000000351f190_0 .net "A1", 0 0, L_000000000391aac0; alias, 1 drivers
+v000000000351ee70_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_000000000386fba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351e1f0_0 .net8 "VGND", 0 0, L_000000000386fba0; 1 drivers, strength-aware
+L_000000000386f9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351e3d0_0 .net8 "VNB", 0 0, L_000000000386f9e0; 1 drivers, strength-aware
+L_0000000003870620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351e650_0 .net8 "VPB", 0 0, L_0000000003870620; 1 drivers, strength-aware
+L_0000000003870690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351eb50_0 .net8 "VPWR", 0 0, L_0000000003870690; 1 drivers, strength-aware
+v000000000351f9b0_0 .net "X", 0 0, L_0000000003927160; alias, 1 drivers
+S_00000000034c7d80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c8500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927240 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391ca40, L_000000000391aac0, L_00000000039263d0;
+L_0000000003927160 .functor BUF 1, L_0000000003927240, C4<0>, C4<0>, C4<0>;
+v000000000351e010_0 .net "A0", 0 0, L_000000000391ca40; alias, 1 drivers
+v000000000351df70_0 .net "A1", 0 0, L_000000000391aac0; alias, 1 drivers
+v000000000351f7d0_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003870850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351fcd0_0 .net8 "VGND", 0 0, L_0000000003870850; 1 drivers, strength-aware
+L_000000000386f660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351ed30_0 .net8 "VNB", 0 0, L_000000000386f660; 1 drivers, strength-aware
+L_000000000386eda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351e150_0 .net8 "VPB", 0 0, L_000000000386eda0; 1 drivers, strength-aware
+L_000000000386ee10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351e8d0_0 .net8 "VPWR", 0 0, L_000000000386ee10; 1 drivers, strength-aware
+v000000000351de30_0 .net "X", 0 0, L_0000000003927160; alias, 1 drivers
+v000000000351f4b0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927240; 1 drivers
+S_00000000034c5800 .scope module, "_396_" "sky130_fd_sc_hd__mux2_1" 3 1257, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351e470_0 .net "A0", 0 0, L_0000000003927be0; alias, 1 drivers
+v000000000351dd90_0 .net "A1", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000351ec90_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386f200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351fb90_0 .net8 "VGND", 0 0, L_000000000386f200; 1 drivers, strength-aware
+L_000000000386f270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351fd70_0 .net8 "VNB", 0 0, L_000000000386f270; 1 drivers, strength-aware
+L_000000000386f350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351f050_0 .net8 "VPB", 0 0, L_000000000386f350; 1 drivers, strength-aware
+L_000000000386f3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351f690_0 .net8 "VPWR", 0 0, L_000000000386f3c0; 1 drivers, strength-aware
+v000000000351fc30_0 .net "X", 0 0, L_0000000003928190; alias, 1 drivers
+S_00000000034c7900 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c5800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039275c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927be0, L_0000000003927470, L_0000000003920e80;
+L_0000000003928190 .functor BUF 1, L_00000000039275c0, C4<0>, C4<0>, C4<0>;
+v000000000351edd0_0 .net "A0", 0 0, L_0000000003927be0; alias, 1 drivers
+v000000000351efb0_0 .net "A1", 0 0, L_0000000003927470; alias, 1 drivers
+v000000000351ebf0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386f970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351d9d0_0 .net8 "VGND", 0 0, L_000000000386f970; 1 drivers, strength-aware
+L_000000000386f430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351faf0_0 .net8 "VNB", 0 0, L_000000000386f430; 1 drivers, strength-aware
+L_000000000386fd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351fa50_0 .net8 "VPB", 0 0, L_000000000386fd60; 1 drivers, strength-aware
+L_000000000386f4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351da70_0 .net8 "VPWR", 0 0, L_000000000386f4a0; 1 drivers, strength-aware
+v000000000351f230_0 .net "X", 0 0, L_0000000003928190; alias, 1 drivers
+v000000000351dcf0_0 .net "mux_2to10_out_X", 0 0, L_00000000039275c0; 1 drivers
+S_00000000034c5980 .scope module, "_397_" "sky130_fd_sc_hd__mux2_1" 3 1263, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v000000000351d930_0 .net "A0", 0 0, L_00000000039276a0; alias, 1 drivers
+v000000000351db10_0 .net "A1", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000351dbb0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386fc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035206d0_0 .net8 "VGND", 0 0, L_000000000386fc10; 1 drivers, strength-aware
+L_000000000386f6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521670_0 .net8 "VNB", 0 0, L_000000000386f6d0; 1 drivers, strength-aware
+L_000000000386fc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035224d0_0 .net8 "VPB", 0 0, L_000000000386fc80; 1 drivers, strength-aware
+L_000000000386fcf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003521530_0 .net8 "VPWR", 0 0, L_000000000386fcf0; 1 drivers, strength-aware
+v0000000003521170_0 .net "X", 0 0, L_00000000039285f0; alias, 1 drivers
+S_00000000034c9a00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c5980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927e10 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039276a0, L_00000000039283c0, L_0000000003920e80;
+L_00000000039285f0 .functor BUF 1, L_0000000003927e10, C4<0>, C4<0>, C4<0>;
+v000000000351e6f0_0 .net "A0", 0 0, L_00000000039276a0; alias, 1 drivers
+v000000000351f2d0_0 .net "A1", 0 0, L_00000000039283c0; alias, 1 drivers
+v000000000351f730_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_000000000386fa50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351f870_0 .net8 "VGND", 0 0, L_000000000386fa50; 1 drivers, strength-aware
+L_000000000386fac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000351fe10_0 .net8 "VNB", 0 0, L_000000000386fac0; 1 drivers, strength-aware
+L_0000000003870d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351feb0_0 .net8 "VPB", 0 0, L_0000000003870d90; 1 drivers, strength-aware
+L_0000000003871030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000351ff50_0 .net8 "VPWR", 0 0, L_0000000003871030; 1 drivers, strength-aware
+v000000000351fff0_0 .net "X", 0 0, L_00000000039285f0; alias, 1 drivers
+v0000000003520090_0 .net "mux_2to10_out_X", 0 0, L_0000000003927e10; 1 drivers
+S_00000000034c5e00 .scope module, "_398_" "sky130_fd_sc_hd__mux2_1" 3 1269, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003520a90_0 .net "A0", 0 0, L_000000000391d530; alias, 1 drivers
+v0000000003520d10_0 .net "A1", 0 0, L_0000000003928430; alias, 1 drivers
+v0000000003520270_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_00000000038708c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035215d0_0 .net8 "VGND", 0 0, L_00000000038708c0; 1 drivers, strength-aware
+L_00000000038713b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521350_0 .net8 "VNB", 0 0, L_00000000038713b0; 1 drivers, strength-aware
+L_0000000003871d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003520450_0 .net8 "VPB", 0 0, L_0000000003871d50; 1 drivers, strength-aware
+L_00000000038712d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003521b70_0 .net8 "VPWR", 0 0, L_00000000038712d0; 1 drivers, strength-aware
+v00000000035221b0_0 .net "X", 0 0, L_00000000039286d0; alias, 1 drivers
+S_00000000034c8380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c5e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927ef0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391d530, L_0000000003928430, L_000000000391fc90;
+L_00000000039286d0 .functor BUF 1, L_0000000003927ef0, C4<0>, C4<0>, C4<0>;
+v00000000035210d0_0 .net "A0", 0 0, L_000000000391d530; alias, 1 drivers
+v00000000035208b0_0 .net "A1", 0 0, L_0000000003928430; alias, 1 drivers
+v00000000035209f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003871b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003520630_0 .net8 "VGND", 0 0, L_0000000003871b20; 1 drivers, strength-aware
+L_0000000003872370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521c10_0 .net8 "VNB", 0 0, L_0000000003872370; 1 drivers, strength-aware
+L_00000000038719d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003520f90_0 .net8 "VPB", 0 0, L_00000000038719d0; 1 drivers, strength-aware
+L_0000000003870cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522110_0 .net8 "VPWR", 0 0, L_0000000003870cb0; 1 drivers, strength-aware
+v0000000003522430_0 .net "X", 0 0, L_00000000039286d0; alias, 1 drivers
+v00000000035218f0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927ef0; 1 drivers
+S_00000000034c5b00 .scope module, "_399_" "sky130_fd_sc_hd__mux2_1" 3 1275, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003520b30_0 .net "A0", 0 0, L_0000000003926600; alias, 1 drivers
+v0000000003520130_0 .net "A1", 0 0, L_00000000039284a0; alias, 1 drivers
+v0000000003520310_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003870b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521210_0 .net8 "VGND", 0 0, L_0000000003870b60; 1 drivers, strength-aware
+L_0000000003871b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003520810_0 .net8 "VNB", 0 0, L_0000000003871b90; 1 drivers, strength-aware
+L_0000000003870bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522610_0 .net8 "VPB", 0 0, L_0000000003870bd0; 1 drivers, strength-aware
+L_0000000003872060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522890_0 .net8 "VPWR", 0 0, L_0000000003872060; 1 drivers, strength-aware
+v00000000035212b0_0 .net "X", 0 0, L_0000000003927be0; alias, 1 drivers
+S_00000000034c6880 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c5b00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927b00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926600, L_00000000039284a0, L_000000000391eaa0;
+L_0000000003927be0 .functor BUF 1, L_0000000003927b00, C4<0>, C4<0>, C4<0>;
+v0000000003520950_0 .net "A0", 0 0, L_0000000003926600; alias, 1 drivers
+v00000000035213f0_0 .net "A1", 0 0, L_00000000039284a0; alias, 1 drivers
+v0000000003522250_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003871dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521990_0 .net8 "VGND", 0 0, L_0000000003871dc0; 1 drivers, strength-aware
+L_0000000003870d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521710_0 .net8 "VNB", 0 0, L_0000000003870d20; 1 drivers, strength-aware
+L_0000000003872300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522570_0 .net8 "VPB", 0 0, L_0000000003872300; 1 drivers, strength-aware
+L_0000000003870a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035217b0_0 .net8 "VPWR", 0 0, L_0000000003870a80; 1 drivers, strength-aware
+v0000000003521850_0 .net "X", 0 0, L_0000000003927be0; alias, 1 drivers
+v0000000003521ad0_0 .net "mux_2to10_out_X", 0 0, L_0000000003927b00; 1 drivers
+S_00000000034cad80 .scope module, "_400_" "sky130_fd_sc_hd__mux2_1" 3 1281, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003521030_0 .net "A0", 0 0, L_000000000391d840; alias, 1 drivers
+v0000000003521d50_0 .net "A1", 0 0, L_0000000003928660; alias, 1 drivers
+v0000000003520c70_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_00000000038720d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003521df0_0 .net8 "VGND", 0 0, L_00000000038720d0; 1 drivers, strength-aware
+L_0000000003871730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522070_0 .net8 "VNB", 0 0, L_0000000003871730; 1 drivers, strength-aware
+L_0000000003871a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035203b0_0 .net8 "VPB", 0 0, L_0000000003871a40; 1 drivers, strength-aware
+L_0000000003870ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035227f0_0 .net8 "VPWR", 0 0, L_0000000003870ee0; 1 drivers, strength-aware
+v0000000003520ef0_0 .net "X", 0 0, L_0000000003927940; alias, 1 drivers
+S_00000000034c7a80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034cad80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928040 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000391d840, L_0000000003928660, L_000000000391fc90;
+L_0000000003927940 .functor BUF 1, L_0000000003928040, C4<0>, C4<0>, C4<0>;
+v0000000003520770_0 .net "A0", 0 0, L_000000000391d840; alias, 1 drivers
+v0000000003521a30_0 .net "A1", 0 0, L_0000000003928660; alias, 1 drivers
+v0000000003521490_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003871110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003520db0_0 .net8 "VGND", 0 0, L_0000000003871110; 1 drivers, strength-aware
+L_0000000003871340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003520bd0_0 .net8 "VNB", 0 0, L_0000000003871340; 1 drivers, strength-aware
+L_0000000003871c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003520e50_0 .net8 "VPB", 0 0, L_0000000003871c00; 1 drivers, strength-aware
+L_0000000003871ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035201d0_0 .net8 "VPWR", 0 0, L_0000000003871ab0; 1 drivers, strength-aware
+v00000000035226b0_0 .net "X", 0 0, L_0000000003927940; alias, 1 drivers
+v0000000003521cb0_0 .net "mux_2to10_out_X", 0 0, L_0000000003928040; 1 drivers
+S_00000000034c5680 .scope module, "_401_" "sky130_fd_sc_hd__mux2_1" 3 1287, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000035230b0_0 .net "A0", 0 0, L_0000000003926b40; alias, 1 drivers
+v00000000035247d0_0 .net "A1", 0 0, L_0000000003927550; alias, 1 drivers
+v0000000003523290_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003870c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003523a10_0 .net8 "VGND", 0 0, L_0000000003870c40; 1 drivers, strength-aware
+L_0000000003871e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003523510_0 .net8 "VNB", 0 0, L_0000000003871e30; 1 drivers, strength-aware
+L_0000000003870e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003524190_0 .net8 "VPB", 0 0, L_0000000003870e00; 1 drivers, strength-aware
+L_0000000003871c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003523bf0_0 .net8 "VPWR", 0 0, L_0000000003871c70; 1 drivers, strength-aware
+v0000000003524370_0 .net "X", 0 0, L_00000000039276a0; alias, 1 drivers
+S_00000000034ca480 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c5680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003927d30 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003926b40, L_0000000003927550, L_000000000391eaa0;
+L_00000000039276a0 .functor BUF 1, L_0000000003927d30, C4<0>, C4<0>, C4<0>;
+v0000000003521e90_0 .net "A0", 0 0, L_0000000003926b40; alias, 1 drivers
+v0000000003521f30_0 .net "A1", 0 0, L_0000000003927550; alias, 1 drivers
+v0000000003521fd0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003871ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035222f0_0 .net8 "VGND", 0 0, L_0000000003871ce0; 1 drivers, strength-aware
+L_0000000003871ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522390_0 .net8 "VNB", 0 0, L_0000000003871ea0; 1 drivers, strength-aware
+L_0000000003871880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035204f0_0 .net8 "VPB", 0 0, L_0000000003871880; 1 drivers, strength-aware
+L_00000000038723e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522750_0 .net8 "VPWR", 0 0, L_00000000038723e0; 1 drivers, strength-aware
+v0000000003520590_0 .net "X", 0 0, L_00000000039276a0; alias, 1 drivers
+v0000000003523970_0 .net "mux_2to10_out_X", 0 0, L_0000000003927d30; 1 drivers
+S_00000000034ca780 .scope module, "_402_" "sky130_fd_sc_hd__mux2_1" 3 1293, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003523b50_0 .net "A0", 0 0, L_0000000003927160; alias, 1 drivers
+v0000000003524b90_0 .net "A1", 0 0, L_0000000003925330; alias, 1 drivers
+v0000000003524d70_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003870e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035249b0_0 .net8 "VGND", 0 0, L_0000000003870e70; 1 drivers, strength-aware
+L_00000000038717a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035245f0_0 .net8 "VNB", 0 0, L_00000000038717a0; 1 drivers, strength-aware
+L_0000000003871260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003524a50_0 .net8 "VPB", 0 0, L_0000000003871260; 1 drivers, strength-aware
+L_0000000003872450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035233d0_0 .net8 "VPWR", 0 0, L_0000000003872450; 1 drivers, strength-aware
+v0000000003524cd0_0 .net "X", 0 0, L_00000000039284a0; alias, 1 drivers
+S_00000000034c6100 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034ca780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928890 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927160, L_0000000003925330, L_000000000391fc90;
+L_00000000039284a0 .functor BUF 1, L_0000000003928890, C4<0>, C4<0>, C4<0>;
+v0000000003523d30_0 .net "A0", 0 0, L_0000000003927160; alias, 1 drivers
+v0000000003523c90_0 .net "A1", 0 0, L_0000000003925330; alias, 1 drivers
+v0000000003524af0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003871810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003524550_0 .net8 "VGND", 0 0, L_0000000003871810; 1 drivers, strength-aware
+L_0000000003871f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003523fb0_0 .net8 "VNB", 0 0, L_0000000003871f80; 1 drivers, strength-aware
+L_00000000038711f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035240f0_0 .net8 "VPB", 0 0, L_00000000038711f0; 1 drivers, strength-aware
+L_0000000003871f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522c50_0 .net8 "VPWR", 0 0, L_0000000003871f10; 1 drivers, strength-aware
+v0000000003524f50_0 .net "X", 0 0, L_00000000039284a0; alias, 1 drivers
+v0000000003523330_0 .net "mux_2to10_out_X", 0 0, L_0000000003928890; 1 drivers
+S_00000000034c9b80 .scope module, "_403_" "sky130_fd_sc_hd__mux2_1" 3 1299, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003523e70_0 .net "A0", 0 0, L_0000000003921580; alias, 1 drivers
+v0000000003524870_0 .net "A1", 0 0, L_000000000391ca40; alias, 1 drivers
+v0000000003523f10_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003870af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035235b0_0 .net8 "VGND", 0 0, L_0000000003870af0; 1 drivers, strength-aware
+L_0000000003870f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522930_0 .net8 "VNB", 0 0, L_0000000003870f50; 1 drivers, strength-aware
+L_0000000003871420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035244b0_0 .net8 "VPB", 0 0, L_0000000003871420; 1 drivers, strength-aware
+L_0000000003872290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003523150_0 .net8 "VPWR", 0 0, L_0000000003872290; 1 drivers, strength-aware
+v00000000035242d0_0 .net "X", 0 0, L_0000000003928660; alias, 1 drivers
+S_00000000034c7780 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c9b80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928510 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003921580, L_000000000391ca40, L_00000000039263d0;
+L_0000000003928660 .functor BUF 1, L_0000000003928510, C4<0>, C4<0>, C4<0>;
+v00000000035238d0_0 .net "A0", 0 0, L_0000000003921580; alias, 1 drivers
+v0000000003523010_0 .net "A1", 0 0, L_000000000391ca40; alias, 1 drivers
+v0000000003524e10_0 .net "S", 0 0, L_00000000039263d0; alias, 1 drivers
+L_0000000003871ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003525090_0 .net8 "VGND", 0 0, L_0000000003871ff0; 1 drivers, strength-aware
+L_0000000003871500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003523ab0_0 .net8 "VNB", 0 0, L_0000000003871500; 1 drivers, strength-aware
+L_0000000003870fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003524230_0 .net8 "VPB", 0 0, L_0000000003870fc0; 1 drivers, strength-aware
+L_0000000003870930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003523830_0 .net8 "VPWR", 0 0, L_0000000003870930; 1 drivers, strength-aware
+v0000000003523dd0_0 .net "X", 0 0, L_0000000003928660; alias, 1 drivers
+v0000000003524050_0 .net "mux_2to10_out_X", 0 0, L_0000000003928510; 1 drivers
+S_00000000034c8680 .scope module, "_404_" "sky130_fd_sc_hd__mux2_1" 3 1305, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003524730_0 .net "A0", 0 0, L_0000000003925aa0; alias, 1 drivers
+v0000000003524910_0 .net "A1", 0 0, L_0000000003926d70; alias, 1 drivers
+v00000000035229d0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_00000000038710a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522a70_0 .net8 "VGND", 0 0, L_00000000038710a0; 1 drivers, strength-aware
+L_0000000003872140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522b10_0 .net8 "VNB", 0 0, L_0000000003872140; 1 drivers, strength-aware
+L_00000000038718f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522cf0_0 .net8 "VPB", 0 0, L_00000000038718f0; 1 drivers, strength-aware
+L_00000000038721b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522d90_0 .net8 "VPWR", 0 0, L_00000000038721b0; 1 drivers, strength-aware
+v00000000035236f0_0 .net "X", 0 0, L_0000000003928820; alias, 1 drivers
+S_00000000034c9880 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c8680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003928740 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003925aa0, L_0000000003926d70, L_000000000391eaa0;
+L_0000000003928820 .functor BUF 1, L_0000000003928740, C4<0>, C4<0>, C4<0>;
+v0000000003524410_0 .net "A0", 0 0, L_0000000003925aa0; alias, 1 drivers
+v0000000003524eb0_0 .net "A1", 0 0, L_0000000003926d70; alias, 1 drivers
+v00000000035231f0_0 .net "S", 0 0, L_000000000391eaa0; alias, 1 drivers
+L_0000000003871960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003524690_0 .net8 "VGND", 0 0, L_0000000003871960; 1 drivers, strength-aware
+L_0000000003871180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003523470_0 .net8 "VNB", 0 0, L_0000000003871180; 1 drivers, strength-aware
+L_0000000003872220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003523650_0 .net8 "VPB", 0 0, L_0000000003872220; 1 drivers, strength-aware
+L_00000000038709a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003522bb0_0 .net8 "VPWR", 0 0, L_00000000038709a0; 1 drivers, strength-aware
+v0000000003524ff0_0 .net "X", 0 0, L_0000000003928820; alias, 1 drivers
+v0000000003524c30_0 .net "mux_2to10_out_X", 0 0, L_0000000003928740; 1 drivers
+S_00000000034c9580 .scope module, "_405_" "sky130_fd_sc_hd__mux2_1" 3 1311, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v00000000035276b0_0 .net "A0", 0 0, L_0000000003928820; alias, 1 drivers
+v00000000035277f0_0 .net "A1", 0 0, L_0000000003927a90; alias, 1 drivers
+v0000000003526fd0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003870a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035274d0_0 .net8 "VGND", 0 0, L_0000000003870a10; 1 drivers, strength-aware
+L_0000000003871490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003526530_0 .net8 "VNB", 0 0, L_0000000003871490; 1 drivers, strength-aware
+L_0000000003871570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035256d0_0 .net8 "VPB", 0 0, L_0000000003871570; 1 drivers, strength-aware
+L_00000000038715e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003526030_0 .net8 "VPWR", 0 0, L_00000000038715e0; 1 drivers, strength-aware
+v0000000003525770_0 .net "X", 0 0, L_0000000003926e50; alias, 1 drivers
+S_00000000034c6d00 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c9580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003926d00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003928820, L_0000000003927a90, L_0000000003920e80;
+L_0000000003926e50 .functor BUF 1, L_0000000003926d00, C4<0>, C4<0>, C4<0>;
+v0000000003523790_0 .net "A0", 0 0, L_0000000003928820; alias, 1 drivers
+v0000000003522e30_0 .net "A1", 0 0, L_0000000003927a90; alias, 1 drivers
+v0000000003522ed0_0 .net "S", 0 0, L_0000000003920e80; alias, 1 drivers
+L_0000000003871650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003522f70_0 .net8 "VGND", 0 0, L_0000000003871650; 1 drivers, strength-aware
+L_00000000038716c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003525450_0 .net8 "VNB", 0 0, L_00000000038716c0; 1 drivers, strength-aware
+L_0000000003873410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003525ef0_0 .net8 "VPB", 0 0, L_0000000003873410; 1 drivers, strength-aware
+L_0000000003872ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035258b0_0 .net8 "VPWR", 0 0, L_0000000003872ca0; 1 drivers, strength-aware
+v0000000003525bd0_0 .net "X", 0 0, L_0000000003926e50; alias, 1 drivers
+v0000000003525630_0 .net "mux_2to10_out_X", 0 0, L_0000000003926d00; 1 drivers
+S_00000000034c6700 .scope module, "_406_" "sky130_fd_sc_hd__mux2_1" 3 1317, 4 29526 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+v0000000003525130_0 .net "A0", 0 0, L_0000000003927010; alias, 1 drivers
+v0000000003525310_0 .net "A1", 0 0, L_00000000039269f0; alias, 1 drivers
+v00000000035260d0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003872e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003525810_0 .net8 "VGND", 0 0, L_0000000003872e60; 1 drivers, strength-aware
+L_00000000038726f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003526df0_0 .net8 "VNB", 0 0, L_00000000038726f0; 1 drivers, strength-aware
+L_0000000003873720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003527890_0 .net8 "VPB", 0 0, L_0000000003873720; 1 drivers, strength-aware
+L_0000000003873b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003526210_0 .net8 "VPWR", 0 0, L_0000000003873b10; 1 drivers, strength-aware
+v0000000003525c70_0 .net "X", 0 0, L_0000000003927550; alias, 1 drivers
+S_00000000034c7600 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29544, 4 29836 1, S_00000000034c6700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039272b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003927010, L_00000000039269f0, L_000000000391fc90;
+L_0000000003927550 .functor BUF 1, L_00000000039272b0, C4<0>, C4<0>, C4<0>;
+v00000000035262b0_0 .net "A0", 0 0, L_0000000003927010; alias, 1 drivers
+v00000000035272f0_0 .net "A1", 0 0, L_00000000039269f0; alias, 1 drivers
+v00000000035268f0_0 .net "S", 0 0, L_000000000391fc90; alias, 1 drivers
+L_0000000003873f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035265d0_0 .net8 "VGND", 0 0, L_0000000003873f70; 1 drivers, strength-aware
+L_00000000038736b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003526c10_0 .net8 "VNB", 0 0, L_00000000038736b0; 1 drivers, strength-aware
+L_0000000003872f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003526670_0 .net8 "VPB", 0 0, L_0000000003872f40; 1 drivers, strength-aware
+L_0000000003873560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003526710_0 .net8 "VPWR", 0 0, L_0000000003873560; 1 drivers, strength-aware
+v0000000003526ad0_0 .net "X", 0 0, L_0000000003927550; alias, 1 drivers
+v0000000003526b70_0 .net "mux_2to10_out_X", 0 0, L_00000000039272b0; 1 drivers
+S_00000000034c5c80 .scope module, "_407_" "sky130_fd_sc_hd__mux4_1" 3 1323, 4 9008 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+v00000000035259f0_0 .net "A0", 0 0, L_0000000003926280; alias, 1 drivers
+v0000000003526a30_0 .net "A1", 0 0, L_0000000003926bb0; alias, 1 drivers
+v0000000003525a90_0 .net "A2", 0 0, L_00000000039258e0; alias, 1 drivers
+v0000000003526d50_0 .net "A3", 0 0, L_0000000003925480; alias, 1 drivers
+v0000000003525db0_0 .net "S0", 0 0, L_0000000003926980; alias, 1 drivers
+v00000000035253b0_0 .net "S1", 0 0, L_000000000391eb10; alias, 1 drivers
+L_00000000038727d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003525950_0 .net8 "VGND", 0 0, L_00000000038727d0; 1 drivers, strength-aware
+L_0000000003873870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003526e90_0 .net8 "VNB", 0 0, L_0000000003873870; 1 drivers, strength-aware
+L_0000000003872b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003526350_0 .net8 "VPB", 0 0, L_0000000003872b50; 1 drivers, strength-aware
+L_0000000003872990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003527070_0 .net8 "VPWR", 0 0, L_0000000003872990; 1 drivers, strength-aware
+v00000000035263f0_0 .net "X", 0 0, L_0000000003927860; alias, 1 drivers
+S_00000000034cac00 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9032, 4 8877 1, S_00000000034c5c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+UDP_sky130_fd_sc_hd__udp_mux_4to2 .udp/comb "sky130_fd_sc_hd__udp_mux_4to2", 6
+ ,"0???000"
+ ,"1???001"
+ ,"?0??100"
+ ,"?1??101"
+ ,"??0?010"
+ ,"??1?011"
+ ,"???0110"
+ ,"???1111"
+ ,"0000??0"
+ ,"1111??1"
+ ,"00???00"
+ ,"11???01"
+ ,"??00?10"
+ ,"??11?11"
+ ,"0?0?0?0"
+ ,"1?1?0?1"
+ ,"?0?01?0"
+ ,"?1?11?1";
+L_0000000003927710 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, L_0000000003926280, L_0000000003926bb0, L_00000000039258e0, L_0000000003925480, L_0000000003926980, L_000000000391eb10;
+L_0000000003927860 .functor BUF 1, L_0000000003927710, C4<0>, C4<0>, C4<0>;
+v00000000035267b0_0 .net "A0", 0 0, L_0000000003926280; alias, 1 drivers
+v0000000003526170_0 .net "A1", 0 0, L_0000000003926bb0; alias, 1 drivers
+v0000000003525d10_0 .net "A2", 0 0, L_00000000039258e0; alias, 1 drivers
+v0000000003526f30_0 .net "A3", 0 0, L_0000000003925480; alias, 1 drivers
+v0000000003526cb0_0 .net "S0", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003527750_0 .net "S1", 0 0, L_000000000391eb10; alias, 1 drivers
+L_0000000003873800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003526850_0 .net8 "VGND", 0 0, L_0000000003873800; 1 drivers, strength-aware
+L_0000000003873cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003525e50_0 .net8 "VNB", 0 0, L_0000000003873cd0; 1 drivers, strength-aware
+L_0000000003873950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035254f0_0 .net8 "VPB", 0 0, L_0000000003873950; 1 drivers, strength-aware
+L_0000000003872fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003525270_0 .net8 "VPWR", 0 0, L_0000000003872fb0; 1 drivers, strength-aware
+v0000000003525f90_0 .net "X", 0 0, L_0000000003927860; alias, 1 drivers
+v0000000003526990_0 .net "mux_4to20_out_X", 0 0, L_0000000003927710; 1 drivers
+S_00000000034c9700 .scope module, "_408_" "sky130_fd_sc_hd__mux4_1" 3 1332, 4 9008 1, S_00000000026c0180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+v0000000003528bf0_0 .net "A0", 0 0, L_000000000391c110; alias, 1 drivers
+v0000000003527d90_0 .net "A1", 0 0, L_000000000391e870; alias, 1 drivers
+v0000000003528650_0 .net "A2", 0 0, L_000000000391eb80; alias, 1 drivers
+v00000000035299b0_0 .net "A3", 0 0, L_000000000391f130; alias, 1 drivers
+v0000000003529eb0_0 .net "S0", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003529ff0_0 .net "S1", 0 0, L_000000000391eb10; alias, 1 drivers
+L_0000000003873480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003528e70_0 .net8 "VGND", 0 0, L_0000000003873480; 1 drivers, strength-aware
+L_00000000038731e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003528290_0 .net8 "VNB", 0 0, L_00000000038731e0; 1 drivers, strength-aware
+L_0000000003872760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003529370_0 .net8 "VPB", 0 0, L_0000000003872760; 1 drivers, strength-aware
+L_0000000003872920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003528970_0 .net8 "VPWR", 0 0, L_0000000003872920; 1 drivers, strength-aware
+v0000000003528a10_0 .net "X", 0 0, L_0000000003927630; alias, 1 drivers
+S_00000000034c8800 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9032, 4 8877 1, S_00000000034c9700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+L_00000000039278d0 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, L_000000000391c110, L_000000000391e870, L_000000000391eb80, L_000000000391f130, L_0000000003926980, L_000000000391eb10;
+L_0000000003927630 .functor BUF 1, L_00000000039278d0, C4<0>, C4<0>, C4<0>;
+v0000000003525590_0 .net "A0", 0 0, L_000000000391c110; alias, 1 drivers
+v0000000003525b30_0 .net "A1", 0 0, L_000000000391e870; alias, 1 drivers
+v0000000003527110_0 .net "A2", 0 0, L_000000000391eb80; alias, 1 drivers
+v0000000003526490_0 .net "A3", 0 0, L_000000000391f130; alias, 1 drivers
+v00000000035271b0_0 .net "S0", 0 0, L_0000000003926980; alias, 1 drivers
+v0000000003527250_0 .net "S1", 0 0, L_000000000391eb10; alias, 1 drivers
+L_0000000003874050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003527390_0 .net8 "VGND", 0 0, L_0000000003874050; 1 drivers, strength-aware
+L_00000000038724c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003527430_0 .net8 "VNB", 0 0, L_00000000038724c0; 1 drivers, strength-aware
+L_0000000003872d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003527570_0 .net8 "VPB", 0 0, L_0000000003872d10; 1 drivers, strength-aware
+L_0000000003873b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003527610_0 .net8 "VPWR", 0 0, L_0000000003873b80; 1 drivers, strength-aware
+v00000000035251d0_0 .net "X", 0 0, L_0000000003927630; alias, 1 drivers
+v0000000003527c50_0 .net "mux_4to20_out_X", 0 0, L_00000000039278d0; 1 drivers
+S_00000000026a4f30 .scope module, "sky130_fd_sc_hd__a2111o_1" "sky130_fd_sc_hd__a2111o_1" 4 39193;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003454718 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035300d0_0 .net "A1", 0 0, o0000000003454718; 0 drivers
+o0000000003454748 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000352f9f0_0 .net "A2", 0 0, o0000000003454748; 0 drivers
+o0000000003454778 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000352fb30_0 .net "B1", 0 0, o0000000003454778; 0 drivers
+o00000000034547a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003530210_0 .net "C1", 0 0, o00000000034547a8; 0 drivers
+o00000000034547d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000352fdb0_0 .net "D1", 0 0, o00000000034547d8; 0 drivers
+L_00000000038735d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003530990_0 .net8 "VGND", 0 0, L_00000000038735d0; 1 drivers, strength-aware
+L_0000000003872530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035303f0_0 .net8 "VNB", 0 0, L_0000000003872530; 1 drivers, strength-aware
+L_0000000003872df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003530c10_0 .net8 "VPB", 0 0, L_0000000003872df0; 1 drivers, strength-aware
+L_0000000003873640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035307b0_0 .net8 "VPWR", 0 0, L_0000000003873640; 1 drivers, strength-aware
+v000000000352f130_0 .net "X", 0 0, L_00000000039279b0; 1 drivers
+S_00000000034c7180 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39215, 4 38937 1, S_00000000026a4f30;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_0000000003927e80 .functor AND 1, o0000000003454718, o0000000003454748, C4<1>, C4<1>;
+L_00000000039277f0 .functor OR 1, o00000000034547a8, o0000000003454778, L_0000000003927e80, o00000000034547d8;
+L_00000000039279b0 .functor BUF 1, L_00000000039277f0, C4<0>, C4<0>, C4<0>;
+v000000000352f8b0_0 .net "A1", 0 0, o0000000003454718; alias, 0 drivers
+v0000000003531570_0 .net "A2", 0 0, o0000000003454748; alias, 0 drivers
+v00000000035312f0_0 .net "B1", 0 0, o0000000003454778; alias, 0 drivers
+v000000000352f950_0 .net "C1", 0 0, o00000000034547a8; alias, 0 drivers
+v00000000035316b0_0 .net "D1", 0 0, o00000000034547d8; alias, 0 drivers
+L_00000000038725a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003530670_0 .net8 "VGND", 0 0, L_00000000038725a0; 1 drivers, strength-aware
+L_0000000003873020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000352fa90_0 .net8 "VNB", 0 0, L_0000000003873020; 1 drivers, strength-aware
+L_0000000003872840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003530b70_0 .net8 "VPB", 0 0, L_0000000003872840; 1 drivers, strength-aware
+L_0000000003873790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000352f4f0_0 .net8 "VPWR", 0 0, L_0000000003873790; 1 drivers, strength-aware
+v0000000003530ad0_0 .net "X", 0 0, L_00000000039279b0; alias, 1 drivers
+v0000000003530e90_0 .net "and0_out", 0 0, L_0000000003927e80; 1 drivers
+v0000000003530530_0 .net "or0_out_X", 0 0, L_00000000039277f0; 1 drivers
+S_00000000026a50b0 .scope module, "sky130_fd_sc_hd__a2111o_2" "sky130_fd_sc_hd__a2111o_2" 4 39067;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003454c58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000352fe50_0 .net "A1", 0 0, o0000000003454c58; 0 drivers
+o0000000003454c88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003530d50_0 .net "A2", 0 0, o0000000003454c88; 0 drivers
+o0000000003454cb8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000352ff90_0 .net "B1", 0 0, o0000000003454cb8; 0 drivers
+o0000000003454ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003530df0_0 .net "C1", 0 0, o0000000003454ce8; 0 drivers
+o0000000003454d18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003530170_0 .net "D1", 0 0, o0000000003454d18; 0 drivers
+L_0000000003873fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000352f3b0_0 .net8 "VGND", 0 0, L_0000000003873fe0; 1 drivers, strength-aware
+L_0000000003873330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035314d0_0 .net8 "VNB", 0 0, L_0000000003873330; 1 drivers, strength-aware
+L_00000000038728b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003530710_0 .net8 "VPB", 0 0, L_00000000038728b0; 1 drivers, strength-aware
+L_00000000038734f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003530f30_0 .net8 "VPWR", 0 0, L_00000000038734f0; 1 drivers, strength-aware
+v0000000003530fd0_0 .net "X", 0 0, L_00000000039290e0; 1 drivers
+S_00000000034c8f80 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39089, 4 38937 1, S_00000000026a50b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_00000000039297e0 .functor AND 1, o0000000003454c58, o0000000003454c88, C4<1>, C4<1>;
+L_0000000003929690 .functor OR 1, o0000000003454ce8, o0000000003454cb8, L_00000000039297e0, o0000000003454d18;
+L_00000000039290e0 .functor BUF 1, L_0000000003929690, C4<0>, C4<0>, C4<0>;
+v000000000352f1d0_0 .net "A1", 0 0, o0000000003454c58; alias, 0 drivers
+v0000000003530cb0_0 .net "A2", 0 0, o0000000003454c88; alias, 0 drivers
+v0000000003530850_0 .net "B1", 0 0, o0000000003454cb8; alias, 0 drivers
+v0000000003530a30_0 .net "C1", 0 0, o0000000003454ce8; alias, 0 drivers
+v000000000352f450_0 .net "D1", 0 0, o0000000003454d18; alias, 0 drivers
+L_00000000038733a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000352fbd0_0 .net8 "VGND", 0 0, L_00000000038733a0; 1 drivers, strength-aware
+L_0000000003873db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035302b0_0 .net8 "VNB", 0 0, L_0000000003873db0; 1 drivers, strength-aware
+L_00000000038732c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035305d0_0 .net8 "VPB", 0 0, L_00000000038732c0; 1 drivers, strength-aware
+L_0000000003872a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000352fc70_0 .net8 "VPWR", 0 0, L_0000000003872a00; 1 drivers, strength-aware
+v0000000003530350_0 .net "X", 0 0, L_00000000039290e0; alias, 1 drivers
+v0000000003531390_0 .net "and0_out", 0 0, L_00000000039297e0; 1 drivers
+v0000000003531610_0 .net "or0_out_X", 0 0, L_0000000003929690; 1 drivers
+S_0000000002602720 .scope module, "sky130_fd_sc_hd__a2111o_4" "sky130_fd_sc_hd__a2111o_4" 4 39319;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003455198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003532f10_0 .net "A1", 0 0, o0000000003455198; 0 drivers
+o00000000034551c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533cd0_0 .net "A2", 0 0, o00000000034551c8; 0 drivers
+o00000000034551f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035321f0_0 .net "B1", 0 0, o00000000034551f8; 0 drivers
+o0000000003455228 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035325b0_0 .net "C1", 0 0, o0000000003455228; 0 drivers
+o0000000003455258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003531ed0_0 .net "D1", 0 0, o0000000003455258; 0 drivers
+L_0000000003872c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003532c90_0 .net8 "VGND", 0 0, L_0000000003872c30; 1 drivers, strength-aware
+L_0000000003872610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003531f70_0 .net8 "VNB", 0 0, L_0000000003872610; 1 drivers, strength-aware
+L_0000000003873090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035330f0_0 .net8 "VPB", 0 0, L_0000000003873090; 1 drivers, strength-aware
+L_00000000038739c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003532830_0 .net8 "VPWR", 0 0, L_00000000038739c0; 1 drivers, strength-aware
+v0000000003533730_0 .net "X", 0 0, L_00000000039289e0; 1 drivers
+S_00000000034c5080 .scope module, "base" "sky130_fd_sc_hd__a2111o" 4 39341, 4 38937 1, S_0000000002602720;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000392a340 .functor AND 1, o0000000003455198, o00000000034551c8, C4<1>, C4<1>;
+L_0000000003929ee0 .functor OR 1, o0000000003455228, o00000000034551f8, L_000000000392a340, o0000000003455258;
+L_00000000039289e0 .functor BUF 1, L_0000000003929ee0, C4<0>, C4<0>, C4<0>;
+v00000000035311b0_0 .net "A1", 0 0, o0000000003455198; alias, 0 drivers
+v0000000003531250_0 .net "A2", 0 0, o00000000034551c8; alias, 0 drivers
+v0000000003531430_0 .net "B1", 0 0, o00000000034551f8; alias, 0 drivers
+v0000000003531750_0 .net "C1", 0 0, o0000000003455228; alias, 0 drivers
+v00000000035317f0_0 .net "D1", 0 0, o0000000003455258; alias, 0 drivers
+L_0000000003872ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000352f270_0 .net8 "VGND", 0 0, L_0000000003872ed0; 1 drivers, strength-aware
+L_00000000038738e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003532510_0 .net8 "VNB", 0 0, L_00000000038738e0; 1 drivers, strength-aware
+L_0000000003872680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003534090_0 .net8 "VPB", 0 0, L_0000000003872680; 1 drivers, strength-aware
+L_0000000003873a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003533eb0_0 .net8 "VPWR", 0 0, L_0000000003873a30; 1 drivers, strength-aware
+v0000000003532650_0 .net "X", 0 0, L_00000000039289e0; alias, 1 drivers
+v0000000003531cf0_0 .net "and0_out", 0 0, L_000000000392a340; 1 drivers
+v0000000003532e70_0 .net "or0_out_X", 0 0, L_0000000003929ee0; 1 drivers
+S_00000000026028a0 .scope module, "sky130_fd_sc_hd__a2111oi_0" "sky130_fd_sc_hd__a2111oi_0" 4 35958;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o00000000034556d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003532290_0 .net "A1", 0 0, o00000000034556d8; 0 drivers
+o0000000003455708 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533910_0 .net "A2", 0 0, o0000000003455708; 0 drivers
+o0000000003455738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533370_0 .net "B1", 0 0, o0000000003455738; 0 drivers
+o0000000003455768 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003531c50_0 .net "C1", 0 0, o0000000003455768; 0 drivers
+o0000000003455798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003531930_0 .net "D1", 0 0, o0000000003455798; 0 drivers
+L_0000000003872a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003533d70_0 .net8 "VGND", 0 0, L_0000000003872a70; 1 drivers, strength-aware
+L_0000000003872ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003532330_0 .net8 "VNB", 0 0, L_0000000003872ae0; 1 drivers, strength-aware
+L_0000000003873aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003532dd0_0 .net8 "VPB", 0 0, L_0000000003873aa0; 1 drivers, strength-aware
+L_0000000003872bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003533410_0 .net8 "VPWR", 0 0, L_0000000003872bc0; 1 drivers, strength-aware
+v0000000003532bf0_0 .net "Y", 0 0, L_0000000003928ac0; 1 drivers
+S_00000000034c9d00 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 35980, 4 35828 1, S_00000000026028a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_0000000003929150 .functor AND 1, o00000000034556d8, o0000000003455708, C4<1>, C4<1>;
+L_0000000003928c80 .functor NOR 1, o0000000003455738, o0000000003455768, o0000000003455798, L_0000000003929150;
+L_0000000003928ac0 .functor BUF 1, L_0000000003928c80, C4<0>, C4<0>, C4<0>;
+v0000000003533550_0 .net "A1", 0 0, o00000000034556d8; alias, 0 drivers
+v0000000003532010_0 .net "A2", 0 0, o0000000003455708; alias, 0 drivers
+v0000000003532970_0 .net "B1", 0 0, o0000000003455738; alias, 0 drivers
+v00000000035320b0_0 .net "C1", 0 0, o0000000003455768; alias, 0 drivers
+v00000000035328d0_0 .net "D1", 0 0, o0000000003455798; alias, 0 drivers
+L_0000000003873c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003532a10_0 .net8 "VGND", 0 0, L_0000000003873c60; 1 drivers, strength-aware
+L_0000000003873bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035326f0_0 .net8 "VNB", 0 0, L_0000000003873bf0; 1 drivers, strength-aware
+L_0000000003872d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003532150_0 .net8 "VPB", 0 0, L_0000000003872d80; 1 drivers, strength-aware
+L_0000000003873f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003532ab0_0 .net8 "VPWR", 0 0, L_0000000003873f00; 1 drivers, strength-aware
+v0000000003533230_0 .net "Y", 0 0, L_0000000003928ac0; alias, 1 drivers
+v00000000035337d0_0 .net "and0_out", 0 0, L_0000000003929150; 1 drivers
+v0000000003532b50_0 .net "nor0_out_Y", 0 0, L_0000000003928c80; 1 drivers
+S_0000000002686060 .scope module, "sky130_fd_sc_hd__a2111oi_1" "sky130_fd_sc_hd__a2111oi_1" 4 36084;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003455c18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533870_0 .net "A1", 0 0, o0000000003455c18; 0 drivers
+o0000000003455c48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003531b10_0 .net "A2", 0 0, o0000000003455c48; 0 drivers
+o0000000003455c78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003532470_0 .net "B1", 0 0, o0000000003455c78; 0 drivers
+o0000000003455ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533a50_0 .net "C1", 0 0, o0000000003455ca8; 0 drivers
+o0000000003455cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003533af0_0 .net "D1", 0 0, o0000000003455cd8; 0 drivers
+L_0000000003873100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003533b90_0 .net8 "VGND", 0 0, L_0000000003873100; 1 drivers, strength-aware
+L_0000000003873d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003533c30_0 .net8 "VNB", 0 0, L_0000000003873d40; 1 drivers, strength-aware
+L_0000000003873e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003533e10_0 .net8 "VPB", 0 0, L_0000000003873e20; 1 drivers, strength-aware
+L_0000000003873e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003533ff0_0 .net8 "VPWR", 0 0, L_0000000003873e90; 1 drivers, strength-aware
+v0000000003533f50_0 .net "Y", 0 0, L_0000000003929b60; 1 drivers
+S_00000000034c5380 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36106, 4 35828 1, S_0000000002686060;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_0000000003929d90 .functor AND 1, o0000000003455c18, o0000000003455c48, C4<1>, C4<1>;
+L_0000000003929e70 .functor NOR 1, o0000000003455c78, o0000000003455ca8, o0000000003455cd8, L_0000000003929d90;
+L_0000000003929b60 .functor BUF 1, L_0000000003929e70, C4<0>, C4<0>, C4<0>;
+v0000000003532790_0 .net "A1", 0 0, o0000000003455c18; alias, 0 drivers
+v00000000035323d0_0 .net "A2", 0 0, o0000000003455c48; alias, 0 drivers
+v0000000003532fb0_0 .net "B1", 0 0, o0000000003455c78; alias, 0 drivers
+v0000000003531d90_0 .net "C1", 0 0, o0000000003455ca8; alias, 0 drivers
+v0000000003532d30_0 .net "D1", 0 0, o0000000003455cd8; alias, 0 drivers
+L_0000000003873170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035339b0_0 .net8 "VGND", 0 0, L_0000000003873170; 1 drivers, strength-aware
+L_0000000003873250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003533190_0 .net8 "VNB", 0 0, L_0000000003873250; 1 drivers, strength-aware
+L_0000000003874b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003533050_0 .net8 "VPB", 0 0, L_0000000003874b40; 1 drivers, strength-aware
+L_0000000003875400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035334b0_0 .net8 "VPWR", 0 0, L_0000000003875400; 1 drivers, strength-aware
+v00000000035332d0_0 .net "Y", 0 0, L_0000000003929b60; alias, 1 drivers
+v00000000035335f0_0 .net "and0_out", 0 0, L_0000000003929d90; 1 drivers
+v0000000003533690_0 .net "nor0_out_Y", 0 0, L_0000000003929e70; 1 drivers
+S_00000000026861e0 .scope module, "sky130_fd_sc_hd__a2111oi_2" "sky130_fd_sc_hd__a2111oi_2" 4 36336;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003456158 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003535710_0 .net "A1", 0 0, o0000000003456158; 0 drivers
+o0000000003456188 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035343b0_0 .net "A2", 0 0, o0000000003456188; 0 drivers
+o00000000034561b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035358f0_0 .net "B1", 0 0, o00000000034561b8; 0 drivers
+o00000000034561e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003535d50_0 .net "C1", 0 0, o00000000034561e8; 0 drivers
+o0000000003456218 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003535f30_0 .net "D1", 0 0, o0000000003456218; 0 drivers
+L_0000000003875240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534db0_0 .net8 "VGND", 0 0, L_0000000003875240; 1 drivers, strength-aware
+L_0000000003874440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534c70_0 .net8 "VNB", 0 0, L_0000000003874440; 1 drivers, strength-aware
+L_0000000003875630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535cb0_0 .net8 "VPB", 0 0, L_0000000003875630; 1 drivers, strength-aware
+L_00000000038744b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535e90_0 .net8 "VPWR", 0 0, L_00000000038744b0; 1 drivers, strength-aware
+v0000000003535210_0 .net "Y", 0 0, L_0000000003928eb0; 1 drivers
+S_00000000034c7480 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36358, 4 35828 1, S_00000000026861e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_0000000003929af0 .functor AND 1, o0000000003456158, o0000000003456188, C4<1>, C4<1>;
+L_0000000003929310 .functor NOR 1, o00000000034561b8, o00000000034561e8, o0000000003456218, L_0000000003929af0;
+L_0000000003928eb0 .functor BUF 1, L_0000000003929310, C4<0>, C4<0>, C4<0>;
+v00000000035319d0_0 .net "A1", 0 0, o0000000003456158; alias, 0 drivers
+v0000000003531a70_0 .net "A2", 0 0, o0000000003456188; alias, 0 drivers
+v0000000003531bb0_0 .net "B1", 0 0, o00000000034561b8; alias, 0 drivers
+v0000000003531e30_0 .net "C1", 0 0, o00000000034561e8; alias, 0 drivers
+v0000000003534e50_0 .net "D1", 0 0, o0000000003456218; alias, 0 drivers
+L_0000000003875320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003535df0_0 .net8 "VGND", 0 0, L_0000000003875320; 1 drivers, strength-aware
+L_0000000003875390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534270_0 .net8 "VNB", 0 0, L_0000000003875390; 1 drivers, strength-aware
+L_00000000038756a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003534f90_0 .net8 "VPB", 0 0, L_00000000038756a0; 1 drivers, strength-aware
+L_00000000038752b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535670_0 .net8 "VPWR", 0 0, L_00000000038752b0; 1 drivers, strength-aware
+v0000000003534310_0 .net "Y", 0 0, L_0000000003928eb0; alias, 1 drivers
+v00000000035341d0_0 .net "and0_out", 0 0, L_0000000003929af0; 1 drivers
+v00000000035364d0_0 .net "nor0_out_Y", 0 0, L_0000000003929310; 1 drivers
+S_0000000002686360 .scope module, "sky130_fd_sc_hd__a2111oi_4" "sky130_fd_sc_hd__a2111oi_4" 4 36210;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003456698 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035366b0_0 .net "A1", 0 0, o0000000003456698; 0 drivers
+o00000000034566c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003535850_0 .net "A2", 0 0, o00000000034566c8; 0 drivers
+o00000000034566f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003536570_0 .net "B1", 0 0, o00000000034566f8; 0 drivers
+o0000000003456728 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035344f0_0 .net "C1", 0 0, o0000000003456728; 0 drivers
+o0000000003456758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003534770_0 .net "D1", 0 0, o0000000003456758; 0 drivers
+L_0000000003874c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003536070_0 .net8 "VGND", 0 0, L_0000000003874c90; 1 drivers, strength-aware
+L_0000000003875470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003535490_0 .net8 "VNB", 0 0, L_0000000003875470; 1 drivers, strength-aware
+L_0000000003874910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535030_0 .net8 "VPB", 0 0, L_0000000003874910; 1 drivers, strength-aware
+L_0000000003874bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535990_0 .net8 "VPWR", 0 0, L_0000000003874bb0; 1 drivers, strength-aware
+v0000000003536610_0 .net "Y", 0 0, L_0000000003928900; 1 drivers
+S_00000000034c5f80 .scope module, "base" "sky130_fd_sc_hd__a2111oi" 4 36232, 4 35828 1, S_0000000002686360;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_0000000003928cf0 .functor AND 1, o0000000003456698, o00000000034566c8, C4<1>, C4<1>;
+L_000000000392a260 .functor NOR 1, o00000000034566f8, o0000000003456728, o0000000003456758, L_0000000003928cf0;
+L_0000000003928900 .functor BUF 1, L_000000000392a260, C4<0>, C4<0>, C4<0>;
+v0000000003535fd0_0 .net "A1", 0 0, o0000000003456698; alias, 0 drivers
+v00000000035357b0_0 .net "A2", 0 0, o00000000034566c8; alias, 0 drivers
+v00000000035348b0_0 .net "B1", 0 0, o00000000034566f8; alias, 0 drivers
+v0000000003534a90_0 .net "C1", 0 0, o0000000003456728; alias, 0 drivers
+v0000000003535a30_0 .net "D1", 0 0, o0000000003456758; alias, 0 drivers
+L_00000000038754e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534d10_0 .net8 "VGND", 0 0, L_00000000038754e0; 1 drivers, strength-aware
+L_0000000003874280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534630_0 .net8 "VNB", 0 0, L_0000000003874280; 1 drivers, strength-aware
+L_0000000003875b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035362f0_0 .net8 "VPB", 0 0, L_0000000003875b70; 1 drivers, strength-aware
+L_0000000003874520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003536890_0 .net8 "VPWR", 0 0, L_0000000003874520; 1 drivers, strength-aware
+v0000000003535c10_0 .net "Y", 0 0, L_0000000003928900; alias, 1 drivers
+v0000000003534ef0_0 .net "and0_out", 0 0, L_0000000003928cf0; 1 drivers
+v00000000035346d0_0 .net "nor0_out_Y", 0 0, L_000000000392a260; 1 drivers
+S_000000000263ad30 .scope module, "sky130_fd_sc_hd__a211o_1" "sky130_fd_sc_hd__a211o_1" 4 1907;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003456bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003535ad0_0 .net "A1", 0 0, o0000000003456bd8; 0 drivers
+o0000000003456c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003534450_0 .net "A2", 0 0, o0000000003456c08; 0 drivers
+o0000000003456c38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003534590_0 .net "B1", 0 0, o0000000003456c38; 0 drivers
+o0000000003456c68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035352b0_0 .net "C1", 0 0, o0000000003456c68; 0 drivers
+L_0000000003875080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534810_0 .net8 "VGND", 0 0, L_0000000003875080; 1 drivers, strength-aware
+L_0000000003874de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003535350_0 .net8 "VNB", 0 0, L_0000000003874de0; 1 drivers, strength-aware
+L_00000000038742f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035353f0_0 .net8 "VPB", 0 0, L_00000000038742f0; 1 drivers, strength-aware
+L_0000000003874590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003535530_0 .net8 "VPWR", 0 0, L_0000000003874590; 1 drivers, strength-aware
+v0000000003535b70_0 .net "X", 0 0, L_000000000392a110; 1 drivers
+S_00000000034c6a00 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 1927, 4 2358 1, S_000000000263ad30;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_00000000039295b0 .functor AND 1, o0000000003456bd8, o0000000003456c08, C4<1>, C4<1>;
+L_0000000003928e40 .functor OR 1, L_00000000039295b0, o0000000003456c68, o0000000003456c38, C4<0>;
+L_000000000392a110 .functor BUF 1, L_0000000003928e40, C4<0>, C4<0>, C4<0>;
+v0000000003536750_0 .net "A1", 0 0, o0000000003456bd8; alias, 0 drivers
+v00000000035350d0_0 .net "A2", 0 0, o0000000003456c08; alias, 0 drivers
+v0000000003535170_0 .net "B1", 0 0, o0000000003456c38; alias, 0 drivers
+v0000000003534b30_0 .net "C1", 0 0, o0000000003456c68; alias, 0 drivers
+L_0000000003875c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035367f0_0 .net8 "VGND", 0 0, L_0000000003875c50; 1 drivers, strength-aware
+L_00000000038740c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003534950_0 .net8 "VNB", 0 0, L_00000000038740c0; 1 drivers, strength-aware
+L_0000000003874980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035349f0_0 .net8 "VPB", 0 0, L_0000000003874980; 1 drivers, strength-aware
+L_0000000003875710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003536110_0 .net8 "VPWR", 0 0, L_0000000003875710; 1 drivers, strength-aware
+v0000000003534bd0_0 .net "X", 0 0, L_000000000392a110; alias, 1 drivers
+v00000000035361b0_0 .net "and0_out", 0 0, L_00000000039295b0; 1 drivers
+v0000000003534130_0 .net "or0_out_X", 0 0, L_0000000003928e40; 1 drivers
+S_000000000263aeb0 .scope module, "sky130_fd_sc_hd__a211o_2" "sky130_fd_sc_hd__a211o_2" 4 2027;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003457088 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003536bb0_0 .net "A1", 0 0, o0000000003457088; 0 drivers
+o00000000034570b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035378d0_0 .net "A2", 0 0, o00000000034570b8; 0 drivers
+o00000000034570e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035371f0_0 .net "B1", 0 0, o00000000034570e8; 0 drivers
+o0000000003457118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003538410_0 .net "C1", 0 0, o0000000003457118; 0 drivers
+L_0000000003875160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003537650_0 .net8 "VGND", 0 0, L_0000000003875160; 1 drivers, strength-aware
+L_0000000003874130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035373d0_0 .net8 "VNB", 0 0, L_0000000003874130; 1 drivers, strength-aware
+L_00000000038749f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003537330_0 .net8 "VPB", 0 0, L_00000000038749f0; 1 drivers, strength-aware
+L_00000000038751d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003538ff0_0 .net8 "VPWR", 0 0, L_00000000038751d0; 1 drivers, strength-aware
+v0000000003536e30_0 .net "X", 0 0, L_00000000039293f0; 1 drivers
+S_00000000034c7300 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 2047, 4 2358 1, S_000000000263aeb0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_0000000003928d60 .functor AND 1, o0000000003457088, o00000000034570b8, C4<1>, C4<1>;
+L_0000000003928b30 .functor OR 1, L_0000000003928d60, o0000000003457118, o00000000034570e8, C4<0>;
+L_00000000039293f0 .functor BUF 1, L_0000000003928b30, C4<0>, C4<0>, C4<0>;
+v00000000035355d0_0 .net "A1", 0 0, o0000000003457088; alias, 0 drivers
+v0000000003536250_0 .net "A2", 0 0, o00000000034570b8; alias, 0 drivers
+v0000000003536390_0 .net "B1", 0 0, o00000000034570e8; alias, 0 drivers
+v0000000003536430_0 .net "C1", 0 0, o0000000003457118; alias, 0 drivers
+L_00000000038741a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035380f0_0 .net8 "VGND", 0 0, L_00000000038741a0; 1 drivers, strength-aware
+L_0000000003874600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035385f0_0 .net8 "VNB", 0 0, L_0000000003874600; 1 drivers, strength-aware
+L_0000000003874670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003538cd0_0 .net8 "VPB", 0 0, L_0000000003874670; 1 drivers, strength-aware
+L_00000000038750f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003537d30_0 .net8 "VPWR", 0 0, L_00000000038750f0; 1 drivers, strength-aware
+v0000000003537dd0_0 .net "X", 0 0, L_00000000039293f0; alias, 1 drivers
+v0000000003536cf0_0 .net "and0_out", 0 0, L_0000000003928d60; 1 drivers
+v0000000003537150_0 .net "or0_out_X", 0 0, L_0000000003928b30; 1 drivers
+S_000000000263b030 .scope module, "sky130_fd_sc_hd__a211o_4" "sky130_fd_sc_hd__a211o_4" 4 1787;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003457538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003538050_0 .net "A1", 0 0, o0000000003457538; 0 drivers
+o0000000003457568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003536f70_0 .net "A2", 0 0, o0000000003457568; 0 drivers
+o0000000003457598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003537c90_0 .net "B1", 0 0, o0000000003457598; 0 drivers
+o00000000034575c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003538d70_0 .net "C1", 0 0, o00000000034575c8; 0 drivers
+L_0000000003875550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003538c30_0 .net8 "VGND", 0 0, L_0000000003875550; 1 drivers, strength-aware
+L_0000000003874750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003536a70_0 .net8 "VNB", 0 0, L_0000000003874750; 1 drivers, strength-aware
+L_0000000003874210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003537a10_0 .net8 "VPB", 0 0, L_0000000003874210; 1 drivers, strength-aware
+L_0000000003874830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035375b0_0 .net8 "VPWR", 0 0, L_0000000003874830; 1 drivers, strength-aware
+v0000000003537470_0 .net "X", 0 0, L_0000000003928ba0; 1 drivers
+S_00000000034c8080 .scope module, "base" "sky130_fd_sc_hd__a211o" 4 1807, 4 2358 1, S_000000000263b030;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_0000000003929620 .functor AND 1, o0000000003457538, o0000000003457568, C4<1>, C4<1>;
+L_0000000003928970 .functor OR 1, L_0000000003929620, o00000000034575c8, o0000000003457598, C4<0>;
+L_0000000003928ba0 .functor BUF 1, L_0000000003928970, C4<0>, C4<0>, C4<0>;
+v0000000003537510_0 .net "A1", 0 0, o0000000003457538; alias, 0 drivers
+v0000000003539090_0 .net "A2", 0 0, o0000000003457568; alias, 0 drivers
+v00000000035384b0_0 .net "B1", 0 0, o0000000003457598; alias, 0 drivers
+v0000000003538eb0_0 .net "C1", 0 0, o00000000034575c8; alias, 0 drivers
+L_0000000003874c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003537fb0_0 .net8 "VGND", 0 0, L_0000000003874c20; 1 drivers, strength-aware
+L_00000000038759b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003536d90_0 .net8 "VNB", 0 0, L_00000000038759b0; 1 drivers, strength-aware
+L_0000000003875a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003537e70_0 .net8 "VPB", 0 0, L_0000000003875a20; 1 drivers, strength-aware
+L_00000000038746e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003536ed0_0 .net8 "VPWR", 0 0, L_00000000038746e0; 1 drivers, strength-aware
+v0000000003538730_0 .net "X", 0 0, L_0000000003928ba0; alias, 1 drivers
+v0000000003537290_0 .net "and0_out", 0 0, L_0000000003929620; 1 drivers
+v0000000003537f10_0 .net "or0_out_X", 0 0, L_0000000003928970; 1 drivers
+S_000000000263b1b0 .scope module, "sky130_fd_sc_hd__a211oi_1" "sky130_fd_sc_hd__a211oi_1" 4 13183;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o00000000034579e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003538190_0 .net "A1", 0 0, o00000000034579e8; 0 drivers
+o0000000003457a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003536930_0 .net "A2", 0 0, o0000000003457a18; 0 drivers
+o0000000003457a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003536b10_0 .net "B1", 0 0, o0000000003457a48; 0 drivers
+o0000000003457a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035389b0_0 .net "C1", 0 0, o0000000003457a78; 0 drivers
+L_00000000038743d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035370b0_0 .net8 "VGND", 0 0, L_00000000038743d0; 1 drivers, strength-aware
+L_0000000003874d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003538a50_0 .net8 "VNB", 0 0, L_0000000003874d00; 1 drivers, strength-aware
+L_0000000003874d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003538e10_0 .net8 "VPB", 0 0, L_0000000003874d70; 1 drivers, strength-aware
+L_0000000003874e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035382d0_0 .net8 "VPWR", 0 0, L_0000000003874e50; 1 drivers, strength-aware
+v0000000003537b50_0 .net "Y", 0 0, L_0000000003929460; 1 drivers
+S_00000000034c9e80 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13203, 4 13634 1, S_000000000263b1b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_0000000003928c10 .functor AND 1, o00000000034579e8, o0000000003457a18, C4<1>, C4<1>;
+L_0000000003929770 .functor NOR 1, L_0000000003928c10, o0000000003457a48, o0000000003457a78, C4<0>;
+L_0000000003929460 .functor BUF 1, L_0000000003929770, C4<0>, C4<0>, C4<0>;
+v00000000035376f0_0 .net "A1", 0 0, o00000000034579e8; alias, 0 drivers
+v0000000003538910_0 .net "A2", 0 0, o0000000003457a18; alias, 0 drivers
+v0000000003537830_0 .net "B1", 0 0, o0000000003457a48; alias, 0 drivers
+v0000000003537970_0 .net "C1", 0 0, o0000000003457a78; alias, 0 drivers
+L_00000000038748a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003537790_0 .net8 "VGND", 0 0, L_00000000038748a0; 1 drivers, strength-aware
+L_0000000003874ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003538870_0 .net8 "VNB", 0 0, L_0000000003874ec0; 1 drivers, strength-aware
+L_00000000038755c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003537ab0_0 .net8 "VPB", 0 0, L_00000000038755c0; 1 drivers, strength-aware
+L_0000000003874f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003538230_0 .net8 "VPWR", 0 0, L_0000000003874f30; 1 drivers, strength-aware
+v00000000035387d0_0 .net "Y", 0 0, L_0000000003929460; alias, 1 drivers
+v0000000003537010_0 .net "and0_out", 0 0, L_0000000003928c10; 1 drivers
+v0000000003538af0_0 .net "nor0_out_Y", 0 0, L_0000000003929770; 1 drivers
+S_000000000263b330 .scope module, "sky130_fd_sc_hd__a211oi_2" "sky130_fd_sc_hd__a211oi_2" 4 13303;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003457e98 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353aad0_0 .net "A1", 0 0, o0000000003457e98; 0 drivers
+o0000000003457ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003539950_0 .net "A2", 0 0, o0000000003457ec8; 0 drivers
+o0000000003457ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353ae90_0 .net "B1", 0 0, o0000000003457ef8; 0 drivers
+o0000000003457f28 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353a170_0 .net "C1", 0 0, o0000000003457f28; 0 drivers
+L_0000000003874a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035393b0_0 .net8 "VGND", 0 0, L_0000000003874a60; 1 drivers, strength-aware
+L_0000000003874ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353a0d0_0 .net8 "VNB", 0 0, L_0000000003874ad0; 1 drivers, strength-aware
+L_0000000003875780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539810_0 .net8 "VPB", 0 0, L_0000000003875780; 1 drivers, strength-aware
+L_0000000003875a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353af30_0 .net8 "VPWR", 0 0, L_0000000003875a90; 1 drivers, strength-aware
+v000000000353ac10_0 .net "Y", 0 0, L_0000000003929850; 1 drivers
+S_00000000034c6400 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13323, 4 13634 1, S_000000000263b330;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_0000000003929540 .functor AND 1, o0000000003457e98, o0000000003457ec8, C4<1>, C4<1>;
+L_00000000039292a0 .functor NOR 1, L_0000000003929540, o0000000003457ef8, o0000000003457f28, C4<0>;
+L_0000000003929850 .functor BUF 1, L_00000000039292a0, C4<0>, C4<0>, C4<0>;
+v0000000003538370_0 .net "A1", 0 0, o0000000003457e98; alias, 0 drivers
+v0000000003538550_0 .net "A2", 0 0, o0000000003457ec8; alias, 0 drivers
+v0000000003537bf0_0 .net "B1", 0 0, o0000000003457ef8; alias, 0 drivers
+v0000000003538690_0 .net "C1", 0 0, o0000000003457f28; alias, 0 drivers
+L_0000000003875b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003538b90_0 .net8 "VGND", 0 0, L_0000000003875b00; 1 drivers, strength-aware
+L_0000000003875be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003538f50_0 .net8 "VNB", 0 0, L_0000000003875be0; 1 drivers, strength-aware
+L_0000000003875010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035369d0_0 .net8 "VPB", 0 0, L_0000000003875010; 1 drivers, strength-aware
+L_0000000003874fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003536c50_0 .net8 "VPWR", 0 0, L_0000000003874fa0; 1 drivers, strength-aware
+v000000000353b1b0_0 .net "Y", 0 0, L_0000000003929850; alias, 1 drivers
+v000000000353b250_0 .net "and0_out", 0 0, L_0000000003929540; 1 drivers
+v000000000353adf0_0 .net "nor0_out_Y", 0 0, L_00000000039292a0; 1 drivers
+S_000000000263b4b0 .scope module, "sky130_fd_sc_hd__a211oi_4" "sky130_fd_sc_hd__a211oi_4" 4 13063;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003458348 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353b7f0_0 .net "A1", 0 0, o0000000003458348; 0 drivers
+o0000000003458378 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353a710_0 .net "A2", 0 0, o0000000003458378; 0 drivers
+o00000000034583a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353b4d0_0 .net "B1", 0 0, o00000000034583a8; 0 drivers
+o00000000034583d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035399f0_0 .net "C1", 0 0, o00000000034583d8; 0 drivers
+L_00000000038757f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353a5d0_0 .net8 "VGND", 0 0, L_00000000038757f0; 1 drivers, strength-aware
+L_00000000038747c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035396d0_0 .net8 "VNB", 0 0, L_00000000038747c0; 1 drivers, strength-aware
+L_0000000003875860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539ef0_0 .net8 "VPB", 0 0, L_0000000003875860; 1 drivers, strength-aware
+L_0000000003874360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539450_0 .net8 "VPWR", 0 0, L_0000000003874360; 1 drivers, strength-aware
+v000000000353b570_0 .net "Y", 0 0, L_00000000039291c0; 1 drivers
+S_00000000034c5200 .scope module, "base" "sky130_fd_sc_hd__a211oi" 4 13083, 4 13634 1, S_000000000263b4b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_0000000003928dd0 .functor AND 1, o0000000003458348, o0000000003458378, C4<1>, C4<1>;
+L_00000000039294d0 .functor NOR 1, L_0000000003928dd0, o00000000034583a8, o00000000034583d8, C4<0>;
+L_00000000039291c0 .functor BUF 1, L_00000000039294d0, C4<0>, C4<0>, C4<0>;
+v000000000353a990_0 .net "A1", 0 0, o0000000003458348; alias, 0 drivers
+v000000000353a490_0 .net "A2", 0 0, o0000000003458378; alias, 0 drivers
+v000000000353a530_0 .net "B1", 0 0, o00000000034583a8; alias, 0 drivers
+v000000000353a210_0 .net "C1", 0 0, o00000000034583d8; alias, 0 drivers
+L_00000000038758d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003539d10_0 .net8 "VGND", 0 0, L_00000000038758d0; 1 drivers, strength-aware
+L_0000000003875940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353b890_0 .net8 "VNB", 0 0, L_0000000003875940; 1 drivers, strength-aware
+L_0000000003875cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539db0_0 .net8 "VPB", 0 0, L_0000000003875cc0; 1 drivers, strength-aware
+L_0000000003875e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539130_0 .net8 "VPWR", 0 0, L_0000000003875e10; 1 drivers, strength-aware
+v000000000353b6b0_0 .net "Y", 0 0, L_00000000039291c0; alias, 1 drivers
+v0000000003539e50_0 .net "and0_out", 0 0, L_0000000003928dd0; 1 drivers
+v00000000035394f0_0 .net "nor0_out_Y", 0 0, L_00000000039294d0; 1 drivers
+S_000000000263b630 .scope module, "sky130_fd_sc_hd__a21bo_1" "sky130_fd_sc_hd__a21bo_1" 4 90993;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o00000000034587f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353a8f0_0 .net "A1", 0 0, o00000000034587f8; 0 drivers
+o0000000003458828 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353a2b0_0 .net "A2", 0 0, o0000000003458828; 0 drivers
+o0000000003458858 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353b390_0 .net "B1_N", 0 0, o0000000003458858; 0 drivers
+L_0000000003875da0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003539630_0 .net8 "VGND", 0 0, L_0000000003875da0; 1 drivers, strength-aware
+L_0000000003875d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353acb0_0 .net8 "VNB", 0 0, L_0000000003875d30; 1 drivers, strength-aware
+L_0000000003875f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353ab70_0 .net8 "VPB", 0 0, L_0000000003875f60; 1 drivers, strength-aware
+L_0000000003875e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353b610_0 .net8 "VPWR", 0 0, L_0000000003875e80; 1 drivers, strength-aware
+v000000000353a350_0 .net "X", 0 0, L_00000000039298c0; 1 drivers
+S_00000000034c6e80 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91011, 4 91435 1, S_000000000263b630;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_0000000003929bd0 .functor NAND 1, o0000000003458828, o00000000034587f8, C4<1>, C4<1>;
+L_0000000003928a50 .functor NAND 1, o0000000003458858, L_0000000003929bd0, C4<1>, C4<1>;
+L_00000000039298c0 .functor BUF 1, L_0000000003928a50, C4<0>, C4<0>, C4<0>;
+v000000000353aa30_0 .net "A1", 0 0, o00000000034587f8; alias, 0 drivers
+v000000000353b110_0 .net "A2", 0 0, o0000000003458828; alias, 0 drivers
+v000000000353ad50_0 .net "B1_N", 0 0, o0000000003458858; alias, 0 drivers
+L_0000000003875ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003539770_0 .net8 "VGND", 0 0, L_0000000003875ef0; 1 drivers, strength-aware
+L_000000000388a020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003539f90_0 .net8 "VNB", 0 0, L_000000000388a020; 1 drivers, strength-aware
+L_000000000388a790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353b2f0_0 .net8 "VPB", 0 0, L_000000000388a790; 1 drivers, strength-aware
+L_000000000388b0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353a670_0 .net8 "VPWR", 0 0, L_000000000388b0c0; 1 drivers, strength-aware
+v000000000353afd0_0 .net "X", 0 0, L_00000000039298c0; alias, 1 drivers
+v000000000353a030_0 .net "nand0_out", 0 0, L_0000000003929bd0; 1 drivers
+v0000000003539590_0 .net "nand1_out_X", 0 0, L_0000000003928a50; 1 drivers
+S_000000000263b7b0 .scope module, "sky130_fd_sc_hd__a21bo_2" "sky130_fd_sc_hd__a21bo_2" 4 91108;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o0000000003458c18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003539310_0 .net "A1", 0 0, o0000000003458c18; 0 drivers
+o0000000003458c48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035398b0_0 .net "A2", 0 0, o0000000003458c48; 0 drivers
+o0000000003458c78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003539bd0_0 .net "B1_N", 0 0, o0000000003458c78; 0 drivers
+L_0000000003889e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353a850_0 .net8 "VGND", 0 0, L_0000000003889e60; 1 drivers, strength-aware
+L_000000000388b750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353b930_0 .net8 "VNB", 0 0, L_000000000388b750; 1 drivers, strength-aware
+L_000000000388b520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353dd70_0 .net8 "VPB", 0 0, L_000000000388b520; 1 drivers, strength-aware
+L_000000000388b210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353c010_0 .net8 "VPWR", 0 0, L_000000000388b210; 1 drivers, strength-aware
+v000000000353cdd0_0 .net "X", 0 0, L_0000000003929a10; 1 drivers
+S_00000000034c6580 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91126, 4 91435 1, S_000000000263b7b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_00000000039299a0 .functor NAND 1, o0000000003458c48, o0000000003458c18, C4<1>, C4<1>;
+L_0000000003929700 .functor NAND 1, o0000000003458c78, L_00000000039299a0, C4<1>, C4<1>;
+L_0000000003929a10 .functor BUF 1, L_0000000003929700, C4<0>, C4<0>, C4<0>;
+v000000000353b750_0 .net "A1", 0 0, o0000000003458c18; alias, 0 drivers
+v0000000003539a90_0 .net "A2", 0 0, o0000000003458c48; alias, 0 drivers
+v00000000035391d0_0 .net "B1_N", 0 0, o0000000003458c78; alias, 0 drivers
+L_000000000388ab10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353a7b0_0 .net8 "VGND", 0 0, L_000000000388ab10; 1 drivers, strength-aware
+L_000000000388a9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003539c70_0 .net8 "VNB", 0 0, L_000000000388a9c0; 1 drivers, strength-aware
+L_000000000388ae90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539b30_0 .net8 "VPB", 0 0, L_000000000388ae90; 1 drivers, strength-aware
+L_000000000388af00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003539270_0 .net8 "VPWR", 0 0, L_000000000388af00; 1 drivers, strength-aware
+v000000000353a3f0_0 .net "X", 0 0, L_0000000003929a10; alias, 1 drivers
+v000000000353b070_0 .net "nand0_out", 0 0, L_00000000039299a0; 1 drivers
+v000000000353b430_0 .net "nand1_out_X", 0 0, L_0000000003929700; 1 drivers
+S_000000000263b930 .scope module, "sky130_fd_sc_hd__a21bo_4" "sky130_fd_sc_hd__a21bo_4" 4 91556;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o0000000003459038 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353c8d0_0 .net "A1", 0 0, o0000000003459038; 0 drivers
+o0000000003459068 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353c150_0 .net "A2", 0 0, o0000000003459068; 0 drivers
+o0000000003459098 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353d4b0_0 .net "B1_N", 0 0, o0000000003459098; 0 drivers
+L_000000000388b590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353ca10_0 .net8 "VGND", 0 0, L_000000000388b590; 1 drivers, strength-aware
+L_000000000388a560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353c3d0_0 .net8 "VNB", 0 0, L_000000000388a560; 1 drivers, strength-aware
+L_000000000388adb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353c830_0 .net8 "VPB", 0 0, L_000000000388adb0; 1 drivers, strength-aware
+L_000000000388af70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353ce70_0 .net8 "VPWR", 0 0, L_000000000388af70; 1 drivers, strength-aware
+v000000000353cfb0_0 .net "X", 0 0, L_0000000003929a80; 1 drivers
+S_00000000034c8c80 .scope module, "base" "sky130_fd_sc_hd__a21bo" 4 91574, 4 91435 1, S_000000000263b930;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_0000000003929930 .functor NAND 1, o0000000003459068, o0000000003459038, C4<1>, C4<1>;
+L_0000000003929d20 .functor NAND 1, o0000000003459098, L_0000000003929930, C4<1>, C4<1>;
+L_0000000003929a80 .functor BUF 1, L_0000000003929d20, C4<0>, C4<0>, C4<0>;
+v000000000353cb50_0 .net "A1", 0 0, o0000000003459038; alias, 0 drivers
+v000000000353d9b0_0 .net "A2", 0 0, o0000000003459068; alias, 0 drivers
+v000000000353da50_0 .net "B1_N", 0 0, o0000000003459098; alias, 0 drivers
+L_000000000388b130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353d410_0 .net8 "VGND", 0 0, L_000000000388b130; 1 drivers, strength-aware
+L_000000000388b600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353daf0_0 .net8 "VNB", 0 0, L_000000000388b600; 1 drivers, strength-aware
+L_0000000003889ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353cd30_0 .net8 "VPB", 0 0, L_0000000003889ed0; 1 drivers, strength-aware
+L_0000000003889fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353d2d0_0 .net8 "VPWR", 0 0, L_0000000003889fb0; 1 drivers, strength-aware
+v000000000353d370_0 .net "X", 0 0, L_0000000003929a80; alias, 1 drivers
+v000000000353c290_0 .net "nand0_out", 0 0, L_0000000003929930; 1 drivers
+v000000000353bbb0_0 .net "nand1_out_X", 0 0, L_0000000003929d20; 1 drivers
+S_00000000008d76e0 .scope module, "sky130_fd_sc_hd__a21boi_0" "sky130_fd_sc_hd__a21boi_0" 4 12147;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o0000000003558018 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353cab0_0 .net "A1", 0 0, o0000000003558018; 0 drivers
+o0000000003558048 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353c1f0_0 .net "A2", 0 0, o0000000003558048; 0 drivers
+o0000000003558078 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353d730_0 .net "B1_N", 0 0, o0000000003558078; 0 drivers
+L_000000000388a720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353cc90_0 .net8 "VGND", 0 0, L_000000000388a720; 1 drivers, strength-aware
+L_000000000388a090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353c470_0 .net8 "VNB", 0 0, L_000000000388a090; 1 drivers, strength-aware
+L_000000000388ad40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353d190_0 .net8 "VPB", 0 0, L_000000000388ad40; 1 drivers, strength-aware
+L_000000000388b7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353d230_0 .net8 "VPWR", 0 0, L_000000000388b7c0; 1 drivers, strength-aware
+v000000000353d870_0 .net "Y", 0 0, L_000000000392a3b0; 1 drivers
+S_00000000034c6b80 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 12165, 4 12024 1, S_00000000008d76e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_0000000003929c40 .functor NOT 1, o0000000003558078, C4<0>, C4<0>, C4<0>;
+L_0000000003928f20 .functor AND 1, o0000000003558018, o0000000003558048, C4<1>, C4<1>;
+L_0000000003929cb0 .functor NOR 1, L_0000000003929c40, L_0000000003928f20, C4<0>, C4<0>;
+L_000000000392a3b0 .functor BUF 1, L_0000000003929cb0, C4<0>, C4<0>, C4<0>;
+v000000000353c970_0 .net "A1", 0 0, o0000000003558018; alias, 0 drivers
+v000000000353cbf0_0 .net "A2", 0 0, o0000000003558048; alias, 0 drivers
+v000000000353de10_0 .net "B1_N", 0 0, o0000000003558078; alias, 0 drivers
+L_000000000388ab80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353cf10_0 .net8 "VGND", 0 0, L_000000000388ab80; 1 drivers, strength-aware
+L_000000000388ae20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353d550_0 .net8 "VNB", 0 0, L_000000000388ae20; 1 drivers, strength-aware
+L_000000000388b1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353d050_0 .net8 "VPB", 0 0, L_000000000388b1a0; 1 drivers, strength-aware
+L_000000000388aaa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353d0f0_0 .net8 "VPWR", 0 0, L_000000000388aaa0; 1 drivers, strength-aware
+v000000000353d5f0_0 .net "Y", 0 0, L_000000000392a3b0; alias, 1 drivers
+v000000000353d690_0 .net "and0_out", 0 0, L_0000000003928f20; 1 drivers
+v000000000353d7d0_0 .net "b", 0 0, L_0000000003929c40; 1 drivers
+v000000000353bc50_0 .net "nor0_out_Y", 0 0, L_0000000003929cb0; 1 drivers
+S_00000000008d79e0 .scope module, "sky130_fd_sc_hd__a21boi_1" "sky130_fd_sc_hd__a21boi_1" 4 12262;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o0000000003558468 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353c5b0_0 .net "A1", 0 0, o0000000003558468; 0 drivers
+o0000000003558498 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353c650_0 .net "A2", 0 0, o0000000003558498; 0 drivers
+o00000000035584c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353dc30_0 .net "B1_N", 0 0, o00000000035584c8; 0 drivers
+L_000000000388a330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353bd90_0 .net8 "VGND", 0 0, L_000000000388a330; 1 drivers, strength-aware
+L_000000000388a100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353dcd0_0 .net8 "VNB", 0 0, L_000000000388a100; 1 drivers, strength-aware
+L_000000000388a1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353deb0_0 .net8 "VPB", 0 0, L_000000000388a1e0; 1 drivers, strength-aware
+L_0000000003889df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353be30_0 .net8 "VPWR", 0 0, L_0000000003889df0; 1 drivers, strength-aware
+v000000000353df50_0 .net "Y", 0 0, L_0000000003929f50; 1 drivers
+S_00000000034c8e00 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 12280, 4 12024 1, S_00000000008d79e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_0000000003929e00 .functor NOT 1, o00000000035584c8, C4<0>, C4<0>, C4<0>;
+L_0000000003928f90 .functor AND 1, o0000000003558468, o0000000003558498, C4<1>, C4<1>;
+L_0000000003929000 .functor NOR 1, L_0000000003929e00, L_0000000003928f90, C4<0>, C4<0>;
+L_0000000003929f50 .functor BUF 1, L_0000000003929000, C4<0>, C4<0>, C4<0>;
+v000000000353c6f0_0 .net "A1", 0 0, o0000000003558468; alias, 0 drivers
+v000000000353c0b0_0 .net "A2", 0 0, o0000000003558498; alias, 0 drivers
+v000000000353c510_0 .net "B1_N", 0 0, o00000000035584c8; alias, 0 drivers
+L_000000000388a800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353c330_0 .net8 "VGND", 0 0, L_000000000388a800; 1 drivers, strength-aware
+L_000000000388a870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353d910_0 .net8 "VNB", 0 0, L_000000000388a870; 1 drivers, strength-aware
+L_000000000388a3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353bcf0_0 .net8 "VPB", 0 0, L_000000000388a3a0; 1 drivers, strength-aware
+L_000000000388afe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353db90_0 .net8 "VPWR", 0 0, L_000000000388afe0; 1 drivers, strength-aware
+v000000000353ba70_0 .net "Y", 0 0, L_0000000003929f50; alias, 1 drivers
+v000000000353c790_0 .net "and0_out", 0 0, L_0000000003928f90; 1 drivers
+v000000000353dff0_0 .net "b", 0 0, L_0000000003929e00; 1 drivers
+v000000000353bb10_0 .net "nor0_out_Y", 0 0, L_0000000003929000; 1 drivers
+S_00000000008d7b60 .scope module, "sky130_fd_sc_hd__a21boi_2" "sky130_fd_sc_hd__a21boi_2" 4 11576;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o00000000035588b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353e450_0 .net "A1", 0 0, o00000000035588b8; 0 drivers
+o00000000035588e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353eef0_0 .net "A2", 0 0, o00000000035588e8; 0 drivers
+o0000000003558918 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353ec70_0 .net "B1_N", 0 0, o0000000003558918; 0 drivers
+L_000000000388ac60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003540570_0 .net8 "VGND", 0 0, L_000000000388ac60; 1 drivers, strength-aware
+L_000000000388a4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353ed10_0 .net8 "VNB", 0 0, L_000000000388a4f0; 1 drivers, strength-aware
+L_0000000003889f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353ee50_0 .net8 "VPB", 0 0, L_0000000003889f40; 1 drivers, strength-aware
+L_000000000388b050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035401b0_0 .net8 "VPWR", 0 0, L_000000000388b050; 1 drivers, strength-aware
+v000000000353e770_0 .net "Y", 0 0, L_000000000392a420; 1 drivers
+S_00000000034c9100 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11594, 4 12024 1, S_00000000008d7b60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_0000000003929070 .functor NOT 1, o0000000003558918, C4<0>, C4<0>, C4<0>;
+L_0000000003929fc0 .functor AND 1, o00000000035588b8, o00000000035588e8, C4<1>, C4<1>;
+L_0000000003929230 .functor NOR 1, L_0000000003929070, L_0000000003929fc0, C4<0>, C4<0>;
+L_000000000392a420 .functor BUF 1, L_0000000003929230, C4<0>, C4<0>, C4<0>;
+v000000000353bed0_0 .net "A1", 0 0, o00000000035588b8; alias, 0 drivers
+v000000000353e090_0 .net "A2", 0 0, o00000000035588e8; alias, 0 drivers
+v000000000353b9d0_0 .net "B1_N", 0 0, o0000000003558918; alias, 0 drivers
+L_000000000388a170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353bf70_0 .net8 "VGND", 0 0, L_000000000388a170; 1 drivers, strength-aware
+L_0000000003889d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353f5d0_0 .net8 "VNB", 0 0, L_0000000003889d10; 1 drivers, strength-aware
+L_000000000388a410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353e6d0_0 .net8 "VPB", 0 0, L_000000000388a410; 1 drivers, strength-aware
+L_000000000388a480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353f710_0 .net8 "VPWR", 0 0, L_000000000388a480; 1 drivers, strength-aware
+v000000000353e4f0_0 .net "Y", 0 0, L_000000000392a420; alias, 1 drivers
+v0000000003540070_0 .net "and0_out", 0 0, L_0000000003929fc0; 1 drivers
+v000000000353ef90_0 .net "b", 0 0, L_0000000003929070; 1 drivers
+v000000000353f8f0_0 .net "nor0_out_Y", 0 0, L_0000000003929230; 1 drivers
+S_00000000008d7860 .scope module, "sky130_fd_sc_hd__a21boi_4" "sky130_fd_sc_hd__a21boi_4" 4 11691;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o0000000003558d08 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353ea90_0 .net "A1", 0 0, o0000000003558d08; 0 drivers
+o0000000003558d38 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353fcb0_0 .net "A2", 0 0, o0000000003558d38; 0 drivers
+o0000000003558d68 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353f030_0 .net "B1_N", 0 0, o0000000003558d68; 0 drivers
+L_0000000003889d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353f3f0_0 .net8 "VGND", 0 0, L_0000000003889d80; 1 drivers, strength-aware
+L_000000000388a250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353fb70_0 .net8 "VNB", 0 0, L_000000000388a250; 1 drivers, strength-aware
+L_000000000388b280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353e590_0 .net8 "VPB", 0 0, L_000000000388b280; 1 drivers, strength-aware
+L_000000000388a2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353e130_0 .net8 "VPWR", 0 0, L_000000000388a2c0; 1 drivers, strength-aware
+v000000000353f210_0 .net "Y", 0 0, L_000000000392a030; 1 drivers
+S_00000000034c5500 .scope module, "base" "sky130_fd_sc_hd__a21boi" 4 11709, 4 12024 1, S_00000000008d7860;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000392a180 .functor NOT 1, o0000000003558d68, C4<0>, C4<0>, C4<0>;
+L_0000000003929380 .functor AND 1, o0000000003558d08, o0000000003558d38, C4<1>, C4<1>;
+L_000000000392a0a0 .functor NOR 1, L_000000000392a180, L_0000000003929380, C4<0>, C4<0>;
+L_000000000392a030 .functor BUF 1, L_000000000392a0a0, C4<0>, C4<0>, C4<0>;
+v00000000035406b0_0 .net "A1", 0 0, o0000000003558d08; alias, 0 drivers
+v000000000353f670_0 .net "A2", 0 0, o0000000003558d38; alias, 0 drivers
+v000000000353e810_0 .net "B1_N", 0 0, o0000000003558d68; alias, 0 drivers
+L_000000000388a5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353f7b0_0 .net8 "VGND", 0 0, L_000000000388a5d0; 1 drivers, strength-aware
+L_000000000388abf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353fc10_0 .net8 "VNB", 0 0, L_000000000388abf0; 1 drivers, strength-aware
+L_000000000388a640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353fe90_0 .net8 "VPB", 0 0, L_000000000388a640; 1 drivers, strength-aware
+L_000000000388b2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353f490_0 .net8 "VPWR", 0 0, L_000000000388b2f0; 1 drivers, strength-aware
+v000000000353edb0_0 .net "Y", 0 0, L_000000000392a030; alias, 1 drivers
+v000000000353f850_0 .net "and0_out", 0 0, L_0000000003929380; 1 drivers
+v0000000003540610_0 .net "b", 0 0, L_000000000392a180; 1 drivers
+v000000000353f0d0_0 .net "nor0_out_Y", 0 0, L_000000000392a0a0; 1 drivers
+S_00000000008d7560 .scope module, "sky130_fd_sc_hd__a21o_1" "sky130_fd_sc_hd__a21o_1" 4 46535;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003559158 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353fdf0_0 .net "A1", 0 0, o0000000003559158; 0 drivers
+o0000000003559188 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035404d0_0 .net "A2", 0 0, o0000000003559188; 0 drivers
+o00000000035591b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353eb30_0 .net "B1", 0 0, o00000000035591b8; 0 drivers
+L_000000000388b360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353ff30_0 .net8 "VGND", 0 0, L_000000000388b360; 1 drivers, strength-aware
+L_000000000388b830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353ffd0_0 .net8 "VNB", 0 0, L_000000000388b830; 1 drivers, strength-aware
+L_000000000388b3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003540110_0 .net8 "VPB", 0 0, L_000000000388b3d0; 1 drivers, strength-aware
+L_000000000388b440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353e3b0_0 .net8 "VPWR", 0 0, L_000000000388b440; 1 drivers, strength-aware
+v000000000353f170_0 .net "X", 0 0, L_000000000392a490; 1 drivers
+S_00000000034c9280 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46553, 4 46415 1, S_00000000008d7560;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000392a1f0 .functor AND 1, o0000000003559158, o0000000003559188, C4<1>, C4<1>;
+L_000000000392a2d0 .functor OR 1, L_000000000392a1f0, o00000000035591b8, C4<0>, C4<0>;
+L_000000000392a490 .functor BUF 1, L_000000000392a2d0, C4<0>, C4<0>, C4<0>;
+v000000000353e1d0_0 .net "A1", 0 0, o0000000003559158; alias, 0 drivers
+v000000000353fd50_0 .net "A2", 0 0, o0000000003559188; alias, 0 drivers
+v000000000353f990_0 .net "B1", 0 0, o00000000035591b8; alias, 0 drivers
+L_000000000388a6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353fa30_0 .net8 "VGND", 0 0, L_000000000388a6b0; 1 drivers, strength-aware
+L_000000000388b4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000353e630_0 .net8 "VNB", 0 0, L_000000000388b4b0; 1 drivers, strength-aware
+L_000000000388b670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353e950_0 .net8 "VPB", 0 0, L_000000000388b670; 1 drivers, strength-aware
+L_000000000388a8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000353f2b0_0 .net8 "VPWR", 0 0, L_000000000388a8e0; 1 drivers, strength-aware
+v000000000353fad0_0 .net "X", 0 0, L_000000000392a490; alias, 1 drivers
+v000000000353e8b0_0 .net "and0_out", 0 0, L_000000000392a1f0; 1 drivers
+v000000000353f350_0 .net "or0_out_X", 0 0, L_000000000392a2d0; 1 drivers
+S_0000000002830a50 .scope module, "sky130_fd_sc_hd__a21o_4" "sky130_fd_sc_hd__a21o_4" 4 46649;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003559578 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353e310_0 .net "A1", 0 0, o0000000003559578; 0 drivers
+o00000000035595a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000353e9f0_0 .net "A2", 0 0, o00000000035595a8; 0 drivers
+o00000000035595d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035415b0_0 .net "B1", 0 0, o00000000035595d8; 0 drivers
+L_000000000388a950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003542550_0 .net8 "VGND", 0 0, L_000000000388a950; 1 drivers, strength-aware
+L_000000000388b6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035409d0_0 .net8 "VNB", 0 0, L_000000000388b6e0; 1 drivers, strength-aware
+L_000000000388aa30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035425f0_0 .net8 "VPB", 0 0, L_000000000388aa30; 1 drivers, strength-aware
+L_000000000388acd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003542eb0_0 .net8 "VPWR", 0 0, L_000000000388acd0; 1 drivers, strength-aware
+v0000000003540a70_0 .net "X", 0 0, L_000000000392af80; 1 drivers
+S_00000000034c7000 .scope module, "base" "sky130_fd_sc_hd__a21o" 4 46667, 4 46415 1, S_0000000002830a50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000392b680 .functor AND 1, o0000000003559578, o00000000035595a8, C4<1>, C4<1>;
+L_000000000392a6c0 .functor OR 1, L_000000000392b680, o00000000035595d8, C4<0>, C4<0>;
+L_000000000392af80 .functor BUF 1, L_000000000392a6c0, C4<0>, C4<0>, C4<0>;
+v0000000003540890_0 .net "A1", 0 0, o0000000003559578; alias, 0 drivers
+v000000000353f530_0 .net "A2", 0 0, o00000000035595a8; alias, 0 drivers
+v000000000353ebd0_0 .net "B1", 0 0, o00000000035595d8; alias, 0 drivers
+L_0000000003889ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003540250_0 .net8 "VGND", 0 0, L_0000000003889ca0; 1 drivers, strength-aware
+L_000000000388ba60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035402f0_0 .net8 "VNB", 0 0, L_000000000388ba60; 1 drivers, strength-aware
+L_000000000388bfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003540750_0 .net8 "VPB", 0 0, L_000000000388bfa0; 1 drivers, strength-aware
+L_000000000388b8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003540390_0 .net8 "VPWR", 0 0, L_000000000388b8a0; 1 drivers, strength-aware
+v0000000003540430_0 .net "X", 0 0, L_000000000392af80; alias, 1 drivers
+v000000000353e270_0 .net "and0_out", 0 0, L_000000000392b680; 1 drivers
+v00000000035407f0_0 .net "or0_out_X", 0 0, L_000000000392a6c0; 1 drivers
+S_0000000002830ed0 .scope module, "sky130_fd_sc_hd__a21oi_1" "sky130_fd_sc_hd__a21oi_1" 4 51675;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003559998 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003541290_0 .net "A1", 0 0, o0000000003559998; 0 drivers
+o00000000035599c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003540cf0_0 .net "A2", 0 0, o00000000035599c8; 0 drivers
+o00000000035599f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003541d30_0 .net "B1", 0 0, o00000000035599f8; 0 drivers
+L_000000000388cb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003540ed0_0 .net8 "VGND", 0 0, L_000000000388cb70; 1 drivers, strength-aware
+L_000000000388bbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003541dd0_0 .net8 "VNB", 0 0, L_000000000388bbb0; 1 drivers, strength-aware
+L_000000000388bad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541010_0 .net8 "VPB", 0 0, L_000000000388bad0; 1 drivers, strength-aware
+L_000000000388ca20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541830_0 .net8 "VPWR", 0 0, L_000000000388ca20; 1 drivers, strength-aware
+v00000000035416f0_0 .net "Y", 0 0, L_000000000392b760; 1 drivers
+S_00000000034c7c00 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51693, 4 51555 1, S_0000000002830ed0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000392a730 .functor AND 1, o0000000003559998, o00000000035599c8, C4<1>, C4<1>;
+L_000000000392b0d0 .functor NOR 1, o00000000035599f8, L_000000000392a730, C4<0>, C4<0>;
+L_000000000392b760 .functor BUF 1, L_000000000392b0d0, C4<0>, C4<0>, C4<0>;
+v0000000003540e30_0 .net "A1", 0 0, o0000000003559998; alias, 0 drivers
+v0000000003541bf0_0 .net "A2", 0 0, o00000000035599c8; alias, 0 drivers
+v0000000003542b90_0 .net "B1", 0 0, o00000000035599f8; alias, 0 drivers
+L_000000000388cc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003541790_0 .net8 "VGND", 0 0, L_000000000388cc50; 1 drivers, strength-aware
+L_000000000388bde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003540b10_0 .net8 "VNB", 0 0, L_000000000388bde0; 1 drivers, strength-aware
+L_000000000388cfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541970_0 .net8 "VPB", 0 0, L_000000000388cfd0; 1 drivers, strength-aware
+L_000000000388b910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541a10_0 .net8 "VPWR", 0 0, L_000000000388b910; 1 drivers, strength-aware
+v0000000003541e70_0 .net "Y", 0 0, L_000000000392b760; alias, 1 drivers
+v00000000035420f0_0 .net "and0_out", 0 0, L_000000000392a730; 1 drivers
+v00000000035427d0_0 .net "nor0_out_Y", 0 0, L_000000000392b0d0; 1 drivers
+S_0000000002830bd0 .scope module, "sky130_fd_sc_hd__a21oi_4" "sky130_fd_sc_hd__a21oi_4" 4 51789;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003559db8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003540f70_0 .net "A1", 0 0, o0000000003559db8; 0 drivers
+o0000000003559de8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035410b0_0 .net "A2", 0 0, o0000000003559de8; 0 drivers
+o0000000003559e18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003541510_0 .net "B1", 0 0, o0000000003559e18; 0 drivers
+L_000000000388d190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003541c90_0 .net8 "VGND", 0 0, L_000000000388d190; 1 drivers, strength-aware
+L_000000000388c5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003542870_0 .net8 "VNB", 0 0, L_000000000388c5c0; 1 drivers, strength-aware
+L_000000000388c860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003542f50_0 .net8 "VPB", 0 0, L_000000000388c860; 1 drivers, strength-aware
+L_000000000388d120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003542910_0 .net8 "VPWR", 0 0, L_000000000388d120; 1 drivers, strength-aware
+v0000000003541150_0 .net "Y", 0 0, L_000000000392ab90; 1 drivers
+S_00000000034ca000 .scope module, "base" "sky130_fd_sc_hd__a21oi" 4 51807, 4 51555 1, S_0000000002830bd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000392bb50 .functor AND 1, o0000000003559db8, o0000000003559de8, C4<1>, C4<1>;
+L_000000000392b7d0 .functor NOR 1, o0000000003559e18, L_000000000392bb50, C4<0>, C4<0>;
+L_000000000392ab90 .functor BUF 1, L_000000000392b7d0, C4<0>, C4<0>, C4<0>;
+v0000000003541650_0 .net "A1", 0 0, o0000000003559db8; alias, 0 drivers
+v00000000035413d0_0 .net "A2", 0 0, o0000000003559de8; alias, 0 drivers
+v0000000003542c30_0 .net "B1", 0 0, o0000000003559e18; alias, 0 drivers
+L_000000000388ca90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035429b0_0 .net8 "VGND", 0 0, L_000000000388ca90; 1 drivers, strength-aware
+L_000000000388d270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035418d0_0 .net8 "VNB", 0 0, L_000000000388d270; 1 drivers, strength-aware
+L_000000000388bd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541ab0_0 .net8 "VPB", 0 0, L_000000000388bd00; 1 drivers, strength-aware
+L_000000000388d200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003541b50_0 .net8 "VPWR", 0 0, L_000000000388d200; 1 drivers, strength-aware
+v0000000003541fb0_0 .net "Y", 0 0, L_000000000392ab90; alias, 1 drivers
+v0000000003541470_0 .net "and0_out", 0 0, L_000000000392bb50; 1 drivers
+v00000000035422d0_0 .net "nor0_out_Y", 0 0, L_000000000392b7d0; 1 drivers
+S_0000000002831050 .scope module, "sky130_fd_sc_hd__a221o_1" "sky130_fd_sc_hd__a221o_1" 4 98119;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355a1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003542d70_0 .net "A1", 0 0, o000000000355a1d8; 0 drivers
+o000000000355a208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003542e10_0 .net "A2", 0 0, o000000000355a208; 0 drivers
+o000000000355a238 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003540bb0_0 .net "B1", 0 0, o000000000355a238; 0 drivers
+o000000000355a268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003540930_0 .net "B2", 0 0, o000000000355a268; 0 drivers
+o000000000355a298 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003540c50_0 .net "C1", 0 0, o000000000355a298; 0 drivers
+L_000000000388b980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003540d90_0 .net8 "VGND", 0 0, L_000000000388b980; 1 drivers, strength-aware
+L_000000000388bb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035411f0_0 .net8 "VNB", 0 0, L_000000000388bb40; 1 drivers, strength-aware
+L_000000000388c010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003504750_0 .net8 "VPB", 0 0, L_000000000388c010; 1 drivers, strength-aware
+L_000000000388bf30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003502b30_0 .net8 "VPWR", 0 0, L_000000000388bf30; 1 drivers, strength-aware
+v00000000035035d0_0 .net "X", 0 0, L_000000000392ac00; 1 drivers
+S_00000000034ca900 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98141, 4 97861 1, S_0000000002831050;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392ace0 .functor AND 1, o000000000355a238, o000000000355a268, C4<1>, C4<1>;
+L_000000000392b1b0 .functor AND 1, o000000000355a1d8, o000000000355a208, C4<1>, C4<1>;
+L_000000000392b450 .functor OR 1, L_000000000392b1b0, L_000000000392ace0, o000000000355a298, C4<0>;
+L_000000000392ac00 .functor BUF 1, L_000000000392b450, C4<0>, C4<0>, C4<0>;
+v0000000003541f10_0 .net "A1", 0 0, o000000000355a1d8; alias, 0 drivers
+v0000000003541330_0 .net "A2", 0 0, o000000000355a208; alias, 0 drivers
+v0000000003542cd0_0 .net "B1", 0 0, o000000000355a238; alias, 0 drivers
+v0000000003542050_0 .net "B2", 0 0, o000000000355a268; alias, 0 drivers
+v0000000003542190_0 .net "C1", 0 0, o000000000355a298; alias, 0 drivers
+L_000000000388ccc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003542230_0 .net8 "VGND", 0 0, L_000000000388ccc0; 1 drivers, strength-aware
+L_000000000388bc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003542370_0 .net8 "VNB", 0 0, L_000000000388bc20; 1 drivers, strength-aware
+L_000000000388c320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003542410_0 .net8 "VPB", 0 0, L_000000000388c320; 1 drivers, strength-aware
+L_000000000388bc90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035424b0_0 .net8 "VPWR", 0 0, L_000000000388bc90; 1 drivers, strength-aware
+v0000000003542690_0 .net "X", 0 0, L_000000000392ac00; alias, 1 drivers
+v0000000003542730_0 .net "and0_out", 0 0, L_000000000392ace0; 1 drivers
+v0000000003542a50_0 .net "and1_out", 0 0, L_000000000392b1b0; 1 drivers
+v0000000003542af0_0 .net "or0_out_X", 0 0, L_000000000392b450; 1 drivers
+S_0000000002831c50 .scope module, "sky130_fd_sc_hd__a221o_2" "sky130_fd_sc_hd__a221o_2" 4 98245;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355a748 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003502630_0 .net "A1", 0 0, o000000000355a748; 0 drivers
+o000000000355a778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003503990_0 .net "A2", 0 0, o000000000355a778; 0 drivers
+o000000000355a7a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003503490_0 .net "B1", 0 0, o000000000355a7a8; 0 drivers
+o000000000355a7d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003502310_0 .net "B2", 0 0, o000000000355a7d8; 0 drivers
+o000000000355a808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003503a30_0 .net "C1", 0 0, o000000000355a808; 0 drivers
+L_000000000388c940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035028b0_0 .net8 "VGND", 0 0, L_000000000388c940; 1 drivers, strength-aware
+L_000000000388d350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003502950_0 .net8 "VNB", 0 0, L_000000000388d350; 1 drivers, strength-aware
+L_000000000388c710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003503f30_0 .net8 "VPB", 0 0, L_000000000388c710; 1 drivers, strength-aware
+L_000000000388bd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003503d50_0 .net8 "VPWR", 0 0, L_000000000388bd70; 1 drivers, strength-aware
+v00000000035046b0_0 .net "X", 0 0, L_000000000392ab20; 1 drivers
+S_00000000034caa80 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98267, 4 97861 1, S_0000000002831c50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392b220 .functor AND 1, o000000000355a7a8, o000000000355a7d8, C4<1>, C4<1>;
+L_000000000392b5a0 .functor AND 1, o000000000355a748, o000000000355a778, C4<1>, C4<1>;
+L_000000000392be60 .functor OR 1, L_000000000392b5a0, L_000000000392b220, o000000000355a808, C4<0>;
+L_000000000392ab20 .functor BUF 1, L_000000000392be60, C4<0>, C4<0>, C4<0>;
+v0000000003503c10_0 .net "A1", 0 0, o000000000355a748; alias, 0 drivers
+v0000000003503530_0 .net "A2", 0 0, o000000000355a778; alias, 0 drivers
+v00000000035044d0_0 .net "B1", 0 0, o000000000355a7a8; alias, 0 drivers
+v0000000003503b70_0 .net "B2", 0 0, o000000000355a7d8; alias, 0 drivers
+v0000000003502a90_0 .net "C1", 0 0, o000000000355a808; alias, 0 drivers
+L_000000000388c8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035023b0_0 .net8 "VGND", 0 0, L_000000000388c8d0; 1 drivers, strength-aware
+L_000000000388c780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003503170_0 .net8 "VNB", 0 0, L_000000000388c780; 1 drivers, strength-aware
+L_000000000388d2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003502450_0 .net8 "VPB", 0 0, L_000000000388d2e0; 1 drivers, strength-aware
+L_000000000388c6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003504570_0 .net8 "VPWR", 0 0, L_000000000388c6a0; 1 drivers, strength-aware
+v0000000003502810_0 .net "X", 0 0, L_000000000392ab20; alias, 1 drivers
+v0000000003503df0_0 .net "and0_out", 0 0, L_000000000392b220; 1 drivers
+v0000000003503cb0_0 .net "and1_out", 0 0, L_000000000392b5a0; 1 drivers
+v0000000003502e50_0 .net "or0_out_X", 0 0, L_000000000392be60; 1 drivers
+S_0000000002831dd0 .scope module, "sky130_fd_sc_hd__a221o_4" "sky130_fd_sc_hd__a221o_4" 4 97993;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355acb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035024f0_0 .net "A1", 0 0, o000000000355acb8; 0 drivers
+o000000000355ace8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035037b0_0 .net "A2", 0 0, o000000000355ace8; 0 drivers
+o000000000355ad18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003502ef0_0 .net "B1", 0 0, o000000000355ad18; 0 drivers
+o000000000355ad48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003504110_0 .net "B2", 0 0, o000000000355ad48; 0 drivers
+o000000000355ad78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003503850_0 .net "C1", 0 0, o000000000355ad78; 0 drivers
+L_000000000388be50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003502770_0 .net8 "VGND", 0 0, L_000000000388be50; 1 drivers, strength-aware
+L_000000000388c080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003503ad0_0 .net8 "VNB", 0 0, L_000000000388c080; 1 drivers, strength-aware
+L_000000000388b9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003502590_0 .net8 "VPB", 0 0, L_000000000388b9f0; 1 drivers, strength-aware
+L_000000000388c390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003504070_0 .net8 "VPWR", 0 0, L_000000000388c390; 1 drivers, strength-aware
+v00000000035041b0_0 .net "X", 0 0, L_000000000392b300; 1 drivers
+S_00000000034ca180 .scope module, "base" "sky130_fd_sc_hd__a221o" 4 98015, 4 97861 1, S_0000000002831dd0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392b290 .functor AND 1, o000000000355ad18, o000000000355ad48, C4<1>, C4<1>;
+L_000000000392a7a0 .functor AND 1, o000000000355acb8, o000000000355ace8, C4<1>, C4<1>;
+L_000000000392aff0 .functor OR 1, L_000000000392a7a0, L_000000000392b290, o000000000355ad78, C4<0>;
+L_000000000392b300 .functor BUF 1, L_000000000392aff0, C4<0>, C4<0>, C4<0>;
+v00000000035029f0_0 .net "A1", 0 0, o000000000355acb8; alias, 0 drivers
+v00000000035021d0_0 .net "A2", 0 0, o000000000355ace8; alias, 0 drivers
+v0000000003504390_0 .net "B1", 0 0, o000000000355ad18; alias, 0 drivers
+v00000000035047f0_0 .net "B2", 0 0, o000000000355ad48; alias, 0 drivers
+v0000000003502db0_0 .net "C1", 0 0, o000000000355ad78; alias, 0 drivers
+L_000000000388cd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003503670_0 .net8 "VGND", 0 0, L_000000000388cd30; 1 drivers, strength-aware
+L_000000000388c2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003503710_0 .net8 "VNB", 0 0, L_000000000388c2b0; 1 drivers, strength-aware
+L_000000000388cb00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035026d0_0 .net8 "VPB", 0 0, L_000000000388cb00; 1 drivers, strength-aware
+L_000000000388d3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035038f0_0 .net8 "VPWR", 0 0, L_000000000388d3c0; 1 drivers, strength-aware
+v0000000003503e90_0 .net "X", 0 0, L_000000000392b300; alias, 1 drivers
+v0000000003503fd0_0 .net "and0_out", 0 0, L_000000000392b290; 1 drivers
+v0000000003503210_0 .net "and1_out", 0 0, L_000000000392a7a0; 1 drivers
+v00000000035032b0_0 .net "or0_out_X", 0 0, L_000000000392aff0; 1 drivers
+S_00000000028320d0 .scope module, "sky130_fd_sc_hd__a221oi_1" "sky130_fd_sc_hd__a221oi_1" 4 2612;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355b228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003502130_0 .net "A1", 0 0, o000000000355b228; 0 drivers
+o000000000355b258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003502270_0 .net "A2", 0 0, o000000000355b258; 0 drivers
+o000000000355b288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035aed00_0 .net "B1", 0 0, o000000000355b288; 0 drivers
+o000000000355b2b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035af840_0 .net "B2", 0 0, o000000000355b2b8; 0 drivers
+o000000000355b2e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b0e20_0 .net "C1", 0 0, o000000000355b2e8; 0 drivers
+L_000000000388c9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035afca0_0 .net8 "VGND", 0 0, L_000000000388c9b0; 1 drivers, strength-aware
+L_000000000388bec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035af480_0 .net8 "VNB", 0 0, L_000000000388bec0; 1 drivers, strength-aware
+L_000000000388c0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035afe80_0 .net8 "VPB", 0 0, L_000000000388c0f0; 1 drivers, strength-aware
+L_000000000388cbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b0f60_0 .net8 "VPWR", 0 0, L_000000000388cbe0; 1 drivers, strength-aware
+v00000000035af8e0_0 .net "Y", 0 0, L_000000000392bfb0; 1 drivers
+S_00000000034ca300 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2634, 4 3084 1, S_00000000028320d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392a880 .functor AND 1, o000000000355b288, o000000000355b2b8, C4<1>, C4<1>;
+L_000000000392aea0 .functor AND 1, o000000000355b228, o000000000355b258, C4<1>, C4<1>;
+L_000000000392b840 .functor NOR 1, L_000000000392a880, o000000000355b2e8, L_000000000392aea0, C4<0>;
+L_000000000392bfb0 .functor BUF 1, L_000000000392b840, C4<0>, C4<0>, C4<0>;
+v0000000003503030_0 .net "A1", 0 0, o000000000355b228; alias, 0 drivers
+v00000000035030d0_0 .net "A2", 0 0, o000000000355b258; alias, 0 drivers
+v0000000003502bd0_0 .net "B1", 0 0, o000000000355b288; alias, 0 drivers
+v0000000003503350_0 .net "B2", 0 0, o000000000355b2b8; alias, 0 drivers
+v0000000003502f90_0 .net "C1", 0 0, o000000000355b2e8; alias, 0 drivers
+L_000000000388c160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003504250_0 .net8 "VGND", 0 0, L_000000000388c160; 1 drivers, strength-aware
+L_000000000388d040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035033f0_0 .net8 "VNB", 0 0, L_000000000388d040; 1 drivers, strength-aware
+L_000000000388cda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035042f0_0 .net8 "VPB", 0 0, L_000000000388cda0; 1 drivers, strength-aware
+L_000000000388c1d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003502c70_0 .net8 "VPWR", 0 0, L_000000000388c1d0; 1 drivers, strength-aware
+v0000000003504430_0 .net "Y", 0 0, L_000000000392bfb0; alias, 1 drivers
+v0000000003502d10_0 .net "and0_out", 0 0, L_000000000392a880; 1 drivers
+v0000000003504610_0 .net "and1_out", 0 0, L_000000000392aea0; 1 drivers
+v0000000003504890_0 .net "nor0_out_Y", 0 0, L_000000000392b840; 1 drivers
+S_00000000028302d0 .scope module, "sky130_fd_sc_hd__a221oi_2" "sky130_fd_sc_hd__a221oi_2" 4 2486;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355b798 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035afac0_0 .net "A1", 0 0, o000000000355b798; 0 drivers
+o000000000355b7c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035af340_0 .net "A2", 0 0, o000000000355b7c8; 0 drivers
+o000000000355b7f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035afc00_0 .net "B1", 0 0, o000000000355b7f8; 0 drivers
+o000000000355b828 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b0b00_0 .net "B2", 0 0, o000000000355b828; 0 drivers
+o000000000355b858 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b0ec0_0 .net "C1", 0 0, o000000000355b858; 0 drivers
+L_000000000388d430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035afde0_0 .net8 "VGND", 0 0, L_000000000388d430; 1 drivers, strength-aware
+L_000000000388c240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b04c0_0 .net8 "VNB", 0 0, L_000000000388c240; 1 drivers, strength-aware
+L_000000000388d0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b0a60_0 .net8 "VPB", 0 0, L_000000000388d0b0; 1 drivers, strength-aware
+L_000000000388c7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035af3e0_0 .net8 "VPWR", 0 0, L_000000000388c7f0; 1 drivers, strength-aware
+v00000000035b02e0_0 .net "Y", 0 0, L_000000000392a810; 1 drivers
+S_00000000034dee30 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2508, 4 3084 1, S_00000000028302d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392b6f0 .functor AND 1, o000000000355b7f8, o000000000355b828, C4<1>, C4<1>;
+L_000000000392ac70 .functor AND 1, o000000000355b798, o000000000355b7c8, C4<1>, C4<1>;
+L_000000000392a8f0 .functor NOR 1, L_000000000392b6f0, o000000000355b858, L_000000000392ac70, C4<0>;
+L_000000000392a810 .functor BUF 1, L_000000000392a8f0, C4<0>, C4<0>, C4<0>;
+v00000000035b0920_0 .net "A1", 0 0, o000000000355b798; alias, 0 drivers
+v00000000035b0380_0 .net "A2", 0 0, o000000000355b7c8; alias, 0 drivers
+v00000000035aec60_0 .net "B1", 0 0, o000000000355b7f8; alias, 0 drivers
+v00000000035b0c40_0 .net "B2", 0 0, o000000000355b828; alias, 0 drivers
+v00000000035b0d80_0 .net "C1", 0 0, o000000000355b858; alias, 0 drivers
+L_000000000388ce10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ae9e0_0 .net8 "VGND", 0 0, L_000000000388ce10; 1 drivers, strength-aware
+L_000000000388c400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b0100_0 .net8 "VNB", 0 0, L_000000000388c400; 1 drivers, strength-aware
+L_000000000388c470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035af2a0_0 .net8 "VPB", 0 0, L_000000000388c470; 1 drivers, strength-aware
+L_000000000388c4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035afb60_0 .net8 "VPWR", 0 0, L_000000000388c4e0; 1 drivers, strength-aware
+v00000000035aeda0_0 .net "Y", 0 0, L_000000000392a810; alias, 1 drivers
+v00000000035b0420_0 .net "and0_out", 0 0, L_000000000392b6f0; 1 drivers
+v00000000035b09c0_0 .net "and1_out", 0 0, L_000000000392ac70; 1 drivers
+v00000000035aea80_0 .net "nor0_out_Y", 0 0, L_000000000392a8f0; 1 drivers
+S_0000000002830d50 .scope module, "sky130_fd_sc_hd__a221oi_4" "sky130_fd_sc_hd__a221oi_4" 4 2738;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355bd08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b10a0_0 .net "A1", 0 0, o000000000355bd08; 0 drivers
+o000000000355bd38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b0600_0 .net "A2", 0 0, o000000000355bd38; 0 drivers
+o000000000355bd68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035aee40_0 .net "B1", 0 0, o000000000355bd68; 0 drivers
+o000000000355bd98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b06a0_0 .net "B2", 0 0, o000000000355bd98; 0 drivers
+o000000000355bdc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035aeee0_0 .net "C1", 0 0, o000000000355bdc8; 0 drivers
+L_000000000388ce80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b0740_0 .net8 "VGND", 0 0, L_000000000388ce80; 1 drivers, strength-aware
+L_000000000388cef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035af200_0 .net8 "VNB", 0 0, L_000000000388cef0; 1 drivers, strength-aware
+L_000000000388c550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b07e0_0 .net8 "VPB", 0 0, L_000000000388c550; 1 drivers, strength-aware
+L_000000000388cf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b0880_0 .net8 "VPWR", 0 0, L_000000000388cf60; 1 drivers, strength-aware
+v00000000035aebc0_0 .net "Y", 0 0, L_000000000392c090; 1 drivers
+S_00000000034dd7b0 .scope module, "base" "sky130_fd_sc_hd__a221oi" 4 2760, 4 3084 1, S_0000000002830d50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392a960 .functor AND 1, o000000000355bd68, o000000000355bd98, C4<1>, C4<1>;
+L_000000000392b8b0 .functor AND 1, o000000000355bd08, o000000000355bd38, C4<1>, C4<1>;
+L_000000000392ba70 .functor NOR 1, L_000000000392a960, o000000000355bdc8, L_000000000392b8b0, C4<0>;
+L_000000000392c090 .functor BUF 1, L_000000000392ba70, C4<0>, C4<0>, C4<0>;
+v00000000035af980_0 .net "A1", 0 0, o000000000355bd08; alias, 0 drivers
+v00000000035af160_0 .net "A2", 0 0, o000000000355bd38; alias, 0 drivers
+v00000000035b0560_0 .net "B1", 0 0, o000000000355bd68; alias, 0 drivers
+v00000000035afa20_0 .net "B2", 0 0, o000000000355bd98; alias, 0 drivers
+v00000000035af520_0 .net "C1", 0 0, o000000000355bdc8; alias, 0 drivers
+L_000000000388c630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035afd40_0 .net8 "VGND", 0 0, L_000000000388c630; 1 drivers, strength-aware
+L_000000000388e700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035aff20_0 .net8 "VNB", 0 0, L_000000000388e700; 1 drivers, strength-aware
+L_000000000388e770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035affc0_0 .net8 "VPB", 0 0, L_000000000388e770; 1 drivers, strength-aware
+L_000000000388ea10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b01a0_0 .net8 "VPWR", 0 0, L_000000000388ea10; 1 drivers, strength-aware
+v00000000035b0060_0 .net "Y", 0 0, L_000000000392c090; alias, 1 drivers
+v00000000035b0240_0 .net "and0_out", 0 0, L_000000000392a960; 1 drivers
+v00000000035ae940_0 .net "and1_out", 0 0, L_000000000392b8b0; 1 drivers
+v00000000035b1000_0 .net "nor0_out_Y", 0 0, L_000000000392ba70; 1 drivers
+S_0000000002831350 .scope module, "sky130_fd_sc_hd__a222oi_1" "sky130_fd_sc_hd__a222oi_1" 4 68369;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+ .port_info 6 /INPUT 1 "C2"
+o000000000355c278 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b27c0_0 .net "A1", 0 0, o000000000355c278; 0 drivers
+o000000000355c2a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b29a0_0 .net "A2", 0 0, o000000000355c2a8; 0 drivers
+o000000000355c2d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b1fa0_0 .net "B1", 0 0, o000000000355c2d8; 0 drivers
+o000000000355c308 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b1b40_0 .net "B2", 0 0, o000000000355c308; 0 drivers
+o000000000355c338 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b25e0_0 .net "C1", 0 0, o000000000355c338; 0 drivers
+o000000000355c368 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b18c0_0 .net "C2", 0 0, o000000000355c368; 0 drivers
+L_000000000388e620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b22c0_0 .net8 "VGND", 0 0, L_000000000388e620; 1 drivers, strength-aware
+L_000000000388e070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b2400_0 .net8 "VNB", 0 0, L_000000000388e070; 1 drivers, strength-aware
+L_000000000388ed90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b31c0_0 .net8 "VPB", 0 0, L_000000000388ed90; 1 drivers, strength-aware
+L_000000000388d820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b3260_0 .net8 "VPWR", 0 0, L_000000000388d820; 1 drivers, strength-aware
+v00000000035b2e00_0 .net "Y", 0 0, L_000000000392a500; 1 drivers
+S_00000000034ddf30 .scope module, "base" "sky130_fd_sc_hd__a222oi" 4 68393, 4 68230 1, S_0000000002831350;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+ .port_info 6 /INPUT 1 "C2"
+L_000000000392b920 .functor NAND 1, o000000000355c2a8, o000000000355c278, C4<1>, C4<1>;
+L_000000000392bc30 .functor NAND 1, o000000000355c308, o000000000355c2d8, C4<1>, C4<1>;
+L_000000000392adc0 .functor NAND 1, o000000000355c368, o000000000355c338, C4<1>, C4<1>;
+L_000000000392b4c0 .functor AND 1, L_000000000392b920, L_000000000392bc30, L_000000000392adc0, C4<1>;
+L_000000000392a500 .functor BUF 1, L_000000000392b4c0, C4<0>, C4<0>, C4<0>;
+v00000000035b0ce0_0 .net "A1", 0 0, o000000000355c278; alias, 0 drivers
+v00000000035aeb20_0 .net "A2", 0 0, o000000000355c2a8; alias, 0 drivers
+v00000000035b0ba0_0 .net "B1", 0 0, o000000000355c2d8; alias, 0 drivers
+v00000000035af5c0_0 .net "B2", 0 0, o000000000355c308; alias, 0 drivers
+v00000000035aef80_0 .net "C1", 0 0, o000000000355c338; alias, 0 drivers
+v00000000035af020_0 .net "C2", 0 0, o000000000355c368; alias, 0 drivers
+L_000000000388df90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035af0c0_0 .net8 "VGND", 0 0, L_000000000388df90; 1 drivers, strength-aware
+L_000000000388e8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035af660_0 .net8 "VNB", 0 0, L_000000000388e8c0; 1 drivers, strength-aware
+L_000000000388d660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035af700_0 .net8 "VPB", 0 0, L_000000000388d660; 1 drivers, strength-aware
+L_000000000388ef50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035af7a0_0 .net8 "VPWR", 0 0, L_000000000388ef50; 1 drivers, strength-aware
+v00000000035b2220_0 .net "Y", 0 0, L_000000000392a500; alias, 1 drivers
+v00000000035b1e60_0 .net "and0_out_Y", 0 0, L_000000000392b4c0; 1 drivers
+v00000000035b11e0_0 .net "nand0_out", 0 0, L_000000000392b920; 1 drivers
+v00000000035b2900_0 .net "nand1_out", 0 0, L_000000000392bc30; 1 drivers
+v00000000035b1aa0_0 .net "nand2_out", 0 0, L_000000000392adc0; 1 drivers
+S_00000000028308d0 .scope module, "sky130_fd_sc_hd__a22o_1" "sky130_fd_sc_hd__a22o_1" 4 92137;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355c8a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b2ae0_0 .net "A1", 0 0, o000000000355c8a8; 0 drivers
+o000000000355c8d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b1960_0 .net "A2", 0 0, o000000000355c8d8; 0 drivers
+o000000000355c908 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b1280_0 .net "B1", 0 0, o000000000355c908; 0 drivers
+o000000000355c938 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b2cc0_0 .net "B2", 0 0, o000000000355c938; 0 drivers
+L_000000000388ed20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b1a00_0 .net8 "VGND", 0 0, L_000000000388ed20; 1 drivers, strength-aware
+L_000000000388ea80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b2b80_0 .net8 "VNB", 0 0, L_000000000388ea80; 1 drivers, strength-aware
+L_000000000388e310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b1460_0 .net8 "VPB", 0 0, L_000000000388e310; 1 drivers, strength-aware
+L_000000000388e1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b2f40_0 .net8 "VPWR", 0 0, L_000000000388e1c0; 1 drivers, strength-aware
+v00000000035b1320_0 .net "X", 0 0, L_000000000392aab0; 1 drivers
+S_00000000034defb0 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92157, 4 91890 1, S_00000000028308d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392b990 .functor AND 1, o000000000355c908, o000000000355c938, C4<1>, C4<1>;
+L_000000000392a9d0 .functor AND 1, o000000000355c8a8, o000000000355c8d8, C4<1>, C4<1>;
+L_000000000392bed0 .functor OR 1, L_000000000392a9d0, L_000000000392b990, C4<0>, C4<0>;
+L_000000000392aab0 .functor BUF 1, L_000000000392bed0, C4<0>, C4<0>, C4<0>;
+v00000000035b13c0_0 .net "A1", 0 0, o000000000355c8a8; alias, 0 drivers
+v00000000035b1140_0 .net "A2", 0 0, o000000000355c8d8; alias, 0 drivers
+v00000000035b34e0_0 .net "B1", 0 0, o000000000355c908; alias, 0 drivers
+v00000000035b1820_0 .net "B2", 0 0, o000000000355c938; alias, 0 drivers
+L_000000000388e690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b2ea0_0 .net8 "VGND", 0 0, L_000000000388e690; 1 drivers, strength-aware
+L_000000000388e7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b38a0_0 .net8 "VNB", 0 0, L_000000000388e7e0; 1 drivers, strength-aware
+L_000000000388ee00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b2360_0 .net8 "VPB", 0 0, L_000000000388ee00; 1 drivers, strength-aware
+L_000000000388dd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b1be0_0 .net8 "VPWR", 0 0, L_000000000388dd60; 1 drivers, strength-aware
+v00000000035b1c80_0 .net "X", 0 0, L_000000000392aab0; alias, 1 drivers
+v00000000035b2680_0 .net "and0_out", 0 0, L_000000000392b990; 1 drivers
+v00000000035b2860_0 .net "and1_out", 0 0, L_000000000392a9d0; 1 drivers
+v00000000035b2a40_0 .net "or0_out_X", 0 0, L_000000000392bed0; 1 drivers
+S_00000000028311d0 .scope module, "sky130_fd_sc_hd__a22o_4" "sky130_fd_sc_hd__a22o_4" 4 92257;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355cd88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b20e0_0 .net "A1", 0 0, o000000000355cd88; 0 drivers
+o000000000355cdb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b1640_0 .net "A2", 0 0, o000000000355cdb8; 0 drivers
+o000000000355cde8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b3080_0 .net "B1", 0 0, o000000000355cde8; 0 drivers
+o000000000355ce18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b16e0_0 .net "B2", 0 0, o000000000355ce18; 0 drivers
+L_000000000388e5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b3120_0 .net8 "VGND", 0 0, L_000000000388e5b0; 1 drivers, strength-aware
+L_000000000388e850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b2180_0 .net8 "VNB", 0 0, L_000000000388e850; 1 drivers, strength-aware
+L_000000000388e930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b2540_0 .net8 "VPB", 0 0, L_000000000388e930; 1 drivers, strength-aware
+L_000000000388ee70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b3300_0 .net8 "VPWR", 0 0, L_000000000388ee70; 1 drivers, strength-aware
+v00000000035b33a0_0 .net "X", 0 0, L_000000000392ba00; 1 drivers
+S_00000000034db230 .scope module, "base" "sky130_fd_sc_hd__a22o" 4 92277, 4 91890 1, S_00000000028311d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392ad50 .functor AND 1, o000000000355cde8, o000000000355ce18, C4<1>, C4<1>;
+L_000000000392aa40 .functor AND 1, o000000000355cd88, o000000000355cdb8, C4<1>, C4<1>;
+L_000000000392a570 .functor OR 1, L_000000000392aa40, L_000000000392ad50, C4<0>, C4<0>;
+L_000000000392ba00 .functor BUF 1, L_000000000392a570, C4<0>, C4<0>, C4<0>;
+v00000000035b1d20_0 .net "A1", 0 0, o000000000355cd88; alias, 0 drivers
+v00000000035b1dc0_0 .net "A2", 0 0, o000000000355cdb8; alias, 0 drivers
+v00000000035b2720_0 .net "B1", 0 0, o000000000355cde8; alias, 0 drivers
+v00000000035b1500_0 .net "B2", 0 0, o000000000355ce18; alias, 0 drivers
+L_000000000388d6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b3580_0 .net8 "VGND", 0 0, L_000000000388d6d0; 1 drivers, strength-aware
+L_000000000388dc80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b2040_0 .net8 "VNB", 0 0, L_000000000388dc80; 1 drivers, strength-aware
+L_000000000388de40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b15a0_0 .net8 "VPB", 0 0, L_000000000388de40; 1 drivers, strength-aware
+L_000000000388d740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b24a0_0 .net8 "VPWR", 0 0, L_000000000388d740; 1 drivers, strength-aware
+v00000000035b1f00_0 .net "X", 0 0, L_000000000392ba00; alias, 1 drivers
+v00000000035b2c20_0 .net "and0_out", 0 0, L_000000000392ad50; 1 drivers
+v00000000035b2d60_0 .net "and1_out", 0 0, L_000000000392aa40; 1 drivers
+v00000000035b2fe0_0 .net "or0_out_X", 0 0, L_000000000392a570; 1 drivers
+S_0000000002830450 .scope module, "sky130_fd_sc_hd__a22oi_1" "sky130_fd_sc_hd__a22oi_1" 4 64190;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355d268 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b48e0_0 .net "A1", 0 0, o000000000355d268; 0 drivers
+o000000000355d298 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b4340_0 .net "A2", 0 0, o000000000355d298; 0 drivers
+o000000000355d2c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b5ec0_0 .net "B1", 0 0, o000000000355d2c8; 0 drivers
+o000000000355d2f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b3ee0_0 .net "B2", 0 0, o000000000355d2f8; 0 drivers
+L_000000000388e9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b45c0_0 .net8 "VGND", 0 0, L_000000000388e9a0; 1 drivers, strength-aware
+L_000000000388eaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b5560_0 .net8 "VNB", 0 0, L_000000000388eaf0; 1 drivers, strength-aware
+L_000000000388efc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4fc0_0 .net8 "VPB", 0 0, L_000000000388efc0; 1 drivers, strength-aware
+L_000000000388eb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b51a0_0 .net8 "VPWR", 0 0, L_000000000388eb60; 1 drivers, strength-aware
+v00000000035b6000_0 .net "Y", 0 0, L_000000000392b060; 1 drivers
+S_00000000034db830 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 64210, 4 64063 1, S_0000000002830450;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392af10 .functor NAND 1, o000000000355d298, o000000000355d268, C4<1>, C4<1>;
+L_000000000392a5e0 .functor NAND 1, o000000000355d2f8, o000000000355d2c8, C4<1>, C4<1>;
+L_000000000392ae30 .functor AND 1, L_000000000392af10, L_000000000392a5e0, C4<1>, C4<1>;
+L_000000000392b060 .functor BUF 1, L_000000000392ae30, C4<0>, C4<0>, C4<0>;
+v00000000035b3440_0 .net "A1", 0 0, o000000000355d268; alias, 0 drivers
+v00000000035b1780_0 .net "A2", 0 0, o000000000355d298; alias, 0 drivers
+v00000000035b3620_0 .net "B1", 0 0, o000000000355d2c8; alias, 0 drivers
+v00000000035b36c0_0 .net "B2", 0 0, o000000000355d2f8; alias, 0 drivers
+L_000000000388df20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b3760_0 .net8 "VGND", 0 0, L_000000000388df20; 1 drivers, strength-aware
+L_000000000388e540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b3800_0 .net8 "VNB", 0 0, L_000000000388e540; 1 drivers, strength-aware
+L_000000000388ebd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b3f80_0 .net8 "VPB", 0 0, L_000000000388ebd0; 1 drivers, strength-aware
+L_000000000388e150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b3d00_0 .net8 "VPWR", 0 0, L_000000000388e150; 1 drivers, strength-aware
+v00000000035b4980_0 .net "Y", 0 0, L_000000000392b060; alias, 1 drivers
+v00000000035b5e20_0 .net "and0_out_Y", 0 0, L_000000000392ae30; 1 drivers
+v00000000035b4520_0 .net "nand0_out", 0 0, L_000000000392af10; 1 drivers
+v00000000035b4b60_0 .net "nand1_out", 0 0, L_000000000392a5e0; 1 drivers
+S_0000000002831950 .scope module, "sky130_fd_sc_hd__a22oi_2" "sky130_fd_sc_hd__a22oi_2" 4 64310;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355d748 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b5420_0 .net "A1", 0 0, o000000000355d748; 0 drivers
+o000000000355d778 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b4a20_0 .net "A2", 0 0, o000000000355d778; 0 drivers
+o000000000355d7a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b5240_0 .net "B1", 0 0, o000000000355d7a8; 0 drivers
+o000000000355d7d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b60a0_0 .net "B2", 0 0, o000000000355d7d8; 0 drivers
+L_000000000388db30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b3e40_0 .net8 "VGND", 0 0, L_000000000388db30; 1 drivers, strength-aware
+L_000000000388d970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b52e0_0 .net8 "VNB", 0 0, L_000000000388d970; 1 drivers, strength-aware
+L_000000000388ec40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4660_0 .net8 "VPB", 0 0, L_000000000388ec40; 1 drivers, strength-aware
+L_000000000388ecb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4020_0 .net8 "VPWR", 0 0, L_000000000388ecb0; 1 drivers, strength-aware
+v00000000035b3bc0_0 .net "Y", 0 0, L_000000000392b3e0; 1 drivers
+S_00000000034dc730 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 64330, 4 64063 1, S_0000000002831950;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392b140 .functor NAND 1, o000000000355d778, o000000000355d748, C4<1>, C4<1>;
+L_000000000392b370 .functor NAND 1, o000000000355d7d8, o000000000355d7a8, C4<1>, C4<1>;
+L_000000000392b610 .functor AND 1, L_000000000392b140, L_000000000392b370, C4<1>, C4<1>;
+L_000000000392b3e0 .functor BUF 1, L_000000000392b610, C4<0>, C4<0>, C4<0>;
+v00000000035b4c00_0 .net "A1", 0 0, o000000000355d748; alias, 0 drivers
+v00000000035b5d80_0 .net "A2", 0 0, o000000000355d778; alias, 0 drivers
+v00000000035b4de0_0 .net "B1", 0 0, o000000000355d7a8; alias, 0 drivers
+v00000000035b5ce0_0 .net "B2", 0 0, o000000000355d7d8; alias, 0 drivers
+L_000000000388e2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b4d40_0 .net8 "VGND", 0 0, L_000000000388e2a0; 1 drivers, strength-aware
+L_000000000388d890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b5f60_0 .net8 "VNB", 0 0, L_000000000388d890; 1 drivers, strength-aware
+L_000000000388e460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b3da0_0 .net8 "VPB", 0 0, L_000000000388e460; 1 drivers, strength-aware
+L_000000000388e230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4160_0 .net8 "VPWR", 0 0, L_000000000388e230; 1 drivers, strength-aware
+v00000000035b57e0_0 .net "Y", 0 0, L_000000000392b3e0; alias, 1 drivers
+v00000000035b40c0_0 .net "and0_out_Y", 0 0, L_000000000392b610; 1 drivers
+v00000000035b3940_0 .net "nand0_out", 0 0, L_000000000392b140; 1 drivers
+v00000000035b3b20_0 .net "nand1_out", 0 0, L_000000000392b370; 1 drivers
+S_00000000028305d0 .scope module, "sky130_fd_sc_hd__a22oi_4" "sky130_fd_sc_hd__a22oi_4" 4 63726;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355dc28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b5c40_0 .net "A1", 0 0, o000000000355dc28; 0 drivers
+o000000000355dc58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b3c60_0 .net "A2", 0 0, o000000000355dc58; 0 drivers
+o000000000355dc88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b4ac0_0 .net "B1", 0 0, o000000000355dc88; 0 drivers
+o000000000355dcb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b4480_0 .net "B2", 0 0, o000000000355dcb8; 0 drivers
+L_000000000388d7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b54c0_0 .net8 "VGND", 0 0, L_000000000388d7b0; 1 drivers, strength-aware
+L_000000000388d900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b56a0_0 .net8 "VNB", 0 0, L_000000000388d900; 1 drivers, strength-aware
+L_000000000388f030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4ca0_0 .net8 "VPB", 0 0, L_000000000388f030; 1 drivers, strength-aware
+L_000000000388d4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b5920_0 .net8 "VPWR", 0 0, L_000000000388d4a0; 1 drivers, strength-aware
+v00000000035b5060_0 .net "Y", 0 0, L_000000000392bca0; 1 drivers
+S_00000000034df8b0 .scope module, "base" "sky130_fd_sc_hd__a22oi" 4 63746, 4 64063 1, S_00000000028305d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392bae0 .functor NAND 1, o000000000355dc58, o000000000355dc28, C4<1>, C4<1>;
+L_000000000392b530 .functor NAND 1, o000000000355dcb8, o000000000355dc88, C4<1>, C4<1>;
+L_000000000392bbc0 .functor AND 1, L_000000000392bae0, L_000000000392b530, C4<1>, C4<1>;
+L_000000000392bca0 .functor BUF 1, L_000000000392bbc0, C4<0>, C4<0>, C4<0>;
+v00000000035b39e0_0 .net "A1", 0 0, o000000000355dc28; alias, 0 drivers
+v00000000035b4700_0 .net "A2", 0 0, o000000000355dc58; alias, 0 drivers
+v00000000035b5600_0 .net "B1", 0 0, o000000000355dc88; alias, 0 drivers
+v00000000035b4200_0 .net "B2", 0 0, o000000000355dcb8; alias, 0 drivers
+L_000000000388dcf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b5740_0 .net8 "VGND", 0 0, L_000000000388dcf0; 1 drivers, strength-aware
+L_000000000388eee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b42a0_0 .net8 "VNB", 0 0, L_000000000388eee0; 1 drivers, strength-aware
+L_000000000388d510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b4f20_0 .net8 "VPB", 0 0, L_000000000388d510; 1 drivers, strength-aware
+L_000000000388d580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b5880_0 .net8 "VPWR", 0 0, L_000000000388d580; 1 drivers, strength-aware
+v00000000035b5ba0_0 .net "Y", 0 0, L_000000000392bca0; alias, 1 drivers
+v00000000035b3a80_0 .net "and0_out_Y", 0 0, L_000000000392bbc0; 1 drivers
+v00000000035b47a0_0 .net "nand0_out", 0 0, L_000000000392bae0; 1 drivers
+v00000000035b43e0_0 .net "nand1_out", 0 0, L_000000000392b530; 1 drivers
+S_0000000002831ad0 .scope module, "sky130_fd_sc_hd__a2bb2o_1" "sky130_fd_sc_hd__a2bb2o_1" 4 62763;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355e108 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7680_0 .net "A1_N", 0 0, o000000000355e108; 0 drivers
+o000000000355e138 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b6820_0 .net "A2_N", 0 0, o000000000355e138; 0 drivers
+o000000000355e168 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b88a0_0 .net "B1", 0 0, o000000000355e168; 0 drivers
+o000000000355e198 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7ae0_0 .net "B2", 0 0, o000000000355e198; 0 drivers
+L_000000000388ddd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b7ea0_0 .net8 "VGND", 0 0, L_000000000388ddd0; 1 drivers, strength-aware
+L_000000000388d5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b7360_0 .net8 "VNB", 0 0, L_000000000388d5f0; 1 drivers, strength-aware
+L_000000000388d9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7f40_0 .net8 "VPB", 0 0, L_000000000388d9e0; 1 drivers, strength-aware
+L_000000000388da50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6aa0_0 .net8 "VPWR", 0 0, L_000000000388da50; 1 drivers, strength-aware
+v00000000035b8580_0 .net "X", 0 0, L_000000000392bf40; 1 drivers
+S_00000000034dd4b0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62783, 4 62635 1, S_0000000002831ad0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392bd10 .functor AND 1, o000000000355e168, o000000000355e198, C4<1>, C4<1>;
+L_000000000392bd80 .functor NOR 1, o000000000355e108, o000000000355e138, C4<0>, C4<0>;
+L_000000000392bdf0 .functor OR 1, L_000000000392bd80, L_000000000392bd10, C4<0>, C4<0>;
+L_000000000392bf40 .functor BUF 1, L_000000000392bdf0, C4<0>, C4<0>, C4<0>;
+v00000000035b4840_0 .net "A1_N", 0 0, o000000000355e108; alias, 0 drivers
+v00000000035b59c0_0 .net "A2_N", 0 0, o000000000355e138; alias, 0 drivers
+v00000000035b4e80_0 .net "B1", 0 0, o000000000355e168; alias, 0 drivers
+v00000000035b5a60_0 .net "B2", 0 0, o000000000355e198; alias, 0 drivers
+L_000000000388e4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b5100_0 .net8 "VGND", 0 0, L_000000000388e4d0; 1 drivers, strength-aware
+L_000000000388dac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b5b00_0 .net8 "VNB", 0 0, L_000000000388dac0; 1 drivers, strength-aware
+L_000000000388dba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b5380_0 .net8 "VPB", 0 0, L_000000000388dba0; 1 drivers, strength-aware
+L_000000000388e380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6f00_0 .net8 "VPWR", 0 0, L_000000000388e380; 1 drivers, strength-aware
+v00000000035b6780_0 .net "X", 0 0, L_000000000392bf40; alias, 1 drivers
+v00000000035b66e0_0 .net "and0_out", 0 0, L_000000000392bd10; 1 drivers
+v00000000035b6140_0 .net "nor0_out", 0 0, L_000000000392bd80; 1 drivers
+v00000000035b8300_0 .net "or0_out_X", 0 0, L_000000000392bdf0; 1 drivers
+S_0000000002831f50 .scope module, "sky130_fd_sc_hd__a2bb2o_2" "sky130_fd_sc_hd__a2bb2o_2" 4 62293;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355e5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7d60_0 .net "A1_N", 0 0, o000000000355e5e8; 0 drivers
+o000000000355e618 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7220_0 .net "A2_N", 0 0, o000000000355e618; 0 drivers
+o000000000355e648 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b72c0_0 .net "B1", 0 0, o000000000355e648; 0 drivers
+o000000000355e678 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7cc0_0 .net "B2", 0 0, o000000000355e678; 0 drivers
+L_000000000388deb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b7e00_0 .net8 "VGND", 0 0, L_000000000388deb0; 1 drivers, strength-aware
+L_000000000388dc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b74a0_0 .net8 "VNB", 0 0, L_000000000388dc10; 1 drivers, strength-aware
+L_000000000388e3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7fe0_0 .net8 "VPB", 0 0, L_000000000388e3f0; 1 drivers, strength-aware
+L_000000000388e000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7720_0 .net8 "VPWR", 0 0, L_000000000388e000; 1 drivers, strength-aware
+v00000000035b6b40_0 .net "X", 0 0, L_000000000392d050; 1 drivers
+S_00000000034dbcb0 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62313, 4 62635 1, S_0000000002831f50;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392c020 .functor AND 1, o000000000355e648, o000000000355e678, C4<1>, C4<1>;
+L_000000000392a650 .functor NOR 1, o000000000355e5e8, o000000000355e618, C4<0>, C4<0>;
+L_000000000392d0c0 .functor OR 1, L_000000000392a650, L_000000000392c020, C4<0>, C4<0>;
+L_000000000392d050 .functor BUF 1, L_000000000392d0c0, C4<0>, C4<0>, C4<0>;
+v00000000035b84e0_0 .net "A1_N", 0 0, o000000000355e5e8; alias, 0 drivers
+v00000000035b8120_0 .net "A2_N", 0 0, o000000000355e618; alias, 0 drivers
+v00000000035b7b80_0 .net "B1", 0 0, o000000000355e648; alias, 0 drivers
+v00000000035b6460_0 .net "B2", 0 0, o000000000355e678; alias, 0 drivers
+L_000000000388e0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b61e0_0 .net8 "VGND", 0 0, L_000000000388e0e0; 1 drivers, strength-aware
+L_0000000003890680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b8620_0 .net8 "VNB", 0 0, L_0000000003890680; 1 drivers, strength-aware
+L_000000000388f260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7c20_0 .net8 "VPB", 0 0, L_000000000388f260; 1 drivers, strength-aware
+L_000000000388f2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6500_0 .net8 "VPWR", 0 0, L_000000000388f2d0; 1 drivers, strength-aware
+v00000000035b86c0_0 .net "X", 0 0, L_000000000392d050; alias, 1 drivers
+v00000000035b7400_0 .net "and0_out", 0 0, L_000000000392c020; 1 drivers
+v00000000035b6280_0 .net "nor0_out", 0 0, L_000000000392a650; 1 drivers
+v00000000035b83a0_0 .net "or0_out_X", 0 0, L_000000000392d0c0; 1 drivers
+S_00000000028314d0 .scope module, "sky130_fd_sc_hd__a2bb2o_4" "sky130_fd_sc_hd__a2bb2o_4" 4 62884;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355eac8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b6d20_0 .net "A1_N", 0 0, o000000000355eac8; 0 drivers
+o000000000355eaf8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b65a0_0 .net "A2_N", 0 0, o000000000355eaf8; 0 drivers
+o000000000355eb28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b7040_0 .net "B1", 0 0, o000000000355eb28; 0 drivers
+o000000000355eb58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b81c0_0 .net "B2", 0 0, o000000000355eb58; 0 drivers
+L_000000000388fab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b75e0_0 .net8 "VGND", 0 0, L_000000000388fab0; 1 drivers, strength-aware
+L_0000000003890a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b8260_0 .net8 "VNB", 0 0, L_0000000003890a70; 1 drivers, strength-aware
+L_0000000003890760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6c80_0 .net8 "VPB", 0 0, L_0000000003890760; 1 drivers, strength-aware
+L_000000000388fce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b8760_0 .net8 "VPWR", 0 0, L_000000000388fce0; 1 drivers, strength-aware
+v00000000035b70e0_0 .net "X", 0 0, L_000000000392cf70; 1 drivers
+S_00000000034dbe30 .scope module, "base" "sky130_fd_sc_hd__a2bb2o" 4 62904, 4 62635 1, S_00000000028314d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392c800 .functor AND 1, o000000000355eb28, o000000000355eb58, C4<1>, C4<1>;
+L_000000000392db40 .functor NOR 1, o000000000355eac8, o000000000355eaf8, C4<0>, C4<0>;
+L_000000000392d6e0 .functor OR 1, L_000000000392db40, L_000000000392c800, C4<0>, C4<0>;
+L_000000000392cf70 .functor BUF 1, L_000000000392d6e0, C4<0>, C4<0>, C4<0>;
+v00000000035b68c0_0 .net "A1_N", 0 0, o000000000355eac8; alias, 0 drivers
+v00000000035b6be0_0 .net "A2_N", 0 0, o000000000355eaf8; alias, 0 drivers
+v00000000035b7900_0 .net "B1", 0 0, o000000000355eb28; alias, 0 drivers
+v00000000035b7540_0 .net "B2", 0 0, o000000000355eb58; alias, 0 drivers
+L_000000000388f420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b8080_0 .net8 "VGND", 0 0, L_000000000388f420; 1 drivers, strength-aware
+L_0000000003890b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b6320_0 .net8 "VNB", 0 0, L_0000000003890b50; 1 drivers, strength-aware
+L_000000000388f880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6fa0_0 .net8 "VPB", 0 0, L_000000000388f880; 1 drivers, strength-aware
+L_00000000038908b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b6960_0 .net8 "VPWR", 0 0, L_00000000038908b0; 1 drivers, strength-aware
+v00000000035b79a0_0 .net "X", 0 0, L_000000000392cf70; alias, 1 drivers
+v00000000035b63c0_0 .net "and0_out", 0 0, L_000000000392c800; 1 drivers
+v00000000035b8440_0 .net "nor0_out", 0 0, L_000000000392db40; 1 drivers
+v00000000035b6e60_0 .net "or0_out_X", 0 0, L_000000000392d6e0; 1 drivers
+S_0000000002830750 .scope module, "sky130_fd_sc_hd__a2bb2oi_1" "sky130_fd_sc_hd__a2bb2oi_1" 4 61702;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355efa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035baf60_0 .net "A1_N", 0 0, o000000000355efa8; 0 drivers
+o000000000355efd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b9ac0_0 .net "A2_N", 0 0, o000000000355efd8; 0 drivers
+o000000000355f008 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b92a0_0 .net "B1", 0 0, o000000000355f008; 0 drivers
+o000000000355f038 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b9c00_0 .net "B2", 0 0, o000000000355f038; 0 drivers
+L_000000000388ff80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b9ca0_0 .net8 "VGND", 0 0, L_000000000388ff80; 1 drivers, strength-aware
+L_0000000003890300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bad80_0 .net8 "VNB", 0 0, L_0000000003890300; 1 drivers, strength-aware
+L_000000000388fff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035baa60_0 .net8 "VPB", 0 0, L_000000000388fff0; 1 drivers, strength-aware
+L_000000000388f7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ba600_0 .net8 "VPWR", 0 0, L_000000000388f7a0; 1 drivers, strength-aware
+v00000000035bace0_0 .net "Y", 0 0, L_000000000392ce20; 1 drivers
+S_00000000034df130 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61722, 4 62165 1, S_0000000002830750;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392d210 .functor AND 1, o000000000355f008, o000000000355f038, C4<1>, C4<1>;
+L_000000000392d670 .functor NOR 1, o000000000355efa8, o000000000355efd8, C4<0>, C4<0>;
+L_000000000392cf00 .functor NOR 1, L_000000000392d670, L_000000000392d210, C4<0>, C4<0>;
+L_000000000392ce20 .functor BUF 1, L_000000000392cf00, C4<0>, C4<0>, C4<0>;
+v00000000035b8800_0 .net "A1_N", 0 0, o000000000355efa8; alias, 0 drivers
+v00000000035b6640_0 .net "A2_N", 0 0, o000000000355efd8; alias, 0 drivers
+v00000000035b6a00_0 .net "B1", 0 0, o000000000355f008; alias, 0 drivers
+v00000000035b6dc0_0 .net "B2", 0 0, o000000000355f038; alias, 0 drivers
+L_0000000003890140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b7180_0 .net8 "VGND", 0 0, L_0000000003890140; 1 drivers, strength-aware
+L_00000000038905a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b77c0_0 .net8 "VNB", 0 0, L_00000000038905a0; 1 drivers, strength-aware
+L_000000000388f110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7a40_0 .net8 "VPB", 0 0, L_000000000388f110; 1 drivers, strength-aware
+L_000000000388f340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b7860_0 .net8 "VPWR", 0 0, L_000000000388f340; 1 drivers, strength-aware
+v00000000035b9b60_0 .net "Y", 0 0, L_000000000392ce20; alias, 1 drivers
+v00000000035b8c60_0 .net "and0_out", 0 0, L_000000000392d210; 1 drivers
+v00000000035ba380_0 .net "nor0_out", 0 0, L_000000000392d670; 1 drivers
+v00000000035ba9c0_0 .net "nor1_out_Y", 0 0, L_000000000392cf00; 1 drivers
+S_0000000002831650 .scope module, "sky130_fd_sc_hd__a2bb2oi_2" "sky130_fd_sc_hd__a2bb2oi_2" 4 61581;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355f488 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bb0a0_0 .net "A1_N", 0 0, o000000000355f488; 0 drivers
+o000000000355f4b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ba740_0 .net "A2_N", 0 0, o000000000355f4b8; 0 drivers
+o000000000355f4e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ba7e0_0 .net "B1", 0 0, o000000000355f4e8; 0 drivers
+o000000000355f518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b8940_0 .net "B2", 0 0, o000000000355f518; 0 drivers
+L_0000000003890bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035baec0_0 .net8 "VGND", 0 0, L_0000000003890bc0; 1 drivers, strength-aware
+L_0000000003890370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b9700_0 .net8 "VNB", 0 0, L_0000000003890370; 1 drivers, strength-aware
+L_0000000003890610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b8d00_0 .net8 "VPB", 0 0, L_0000000003890610; 1 drivers, strength-aware
+L_000000000388f490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b9e80_0 .net8 "VPWR", 0 0, L_000000000388f490; 1 drivers, strength-aware
+v00000000035b8ee0_0 .net "Y", 0 0, L_000000000392cb80; 1 drivers
+S_00000000034dc430 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61601, 4 62165 1, S_0000000002831650;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392c480 .functor AND 1, o000000000355f4e8, o000000000355f518, C4<1>, C4<1>;
+L_000000000392caa0 .functor NOR 1, o000000000355f488, o000000000355f4b8, C4<0>, C4<0>;
+L_000000000392d360 .functor NOR 1, L_000000000392caa0, L_000000000392c480, C4<0>, C4<0>;
+L_000000000392cb80 .functor BUF 1, L_000000000392d360, C4<0>, C4<0>, C4<0>;
+v00000000035b90c0_0 .net "A1_N", 0 0, o000000000355f488; alias, 0 drivers
+v00000000035b8bc0_0 .net "A2_N", 0 0, o000000000355f4b8; alias, 0 drivers
+v00000000035b98e0_0 .net "B1", 0 0, o000000000355f4e8; alias, 0 drivers
+v00000000035b9160_0 .net "B2", 0 0, o000000000355f518; alias, 0 drivers
+L_0000000003890060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bae20_0 .net8 "VGND", 0 0, L_0000000003890060; 1 drivers, strength-aware
+L_000000000388f500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b9660_0 .net8 "VNB", 0 0, L_000000000388f500; 1 drivers, strength-aware
+L_00000000038900d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b9840_0 .net8 "VPB", 0 0, L_00000000038900d0; 1 drivers, strength-aware
+L_000000000388fdc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ba240_0 .net8 "VPWR", 0 0, L_000000000388fdc0; 1 drivers, strength-aware
+v00000000035b9980_0 .net "Y", 0 0, L_000000000392cb80; alias, 1 drivers
+v00000000035b8e40_0 .net "and0_out", 0 0, L_000000000392c480; 1 drivers
+v00000000035b9d40_0 .net "nor0_out", 0 0, L_000000000392caa0; 1 drivers
+v00000000035bb000_0 .net "nor1_out_Y", 0 0, L_000000000392d360; 1 drivers
+S_00000000028317d0 .scope module, "sky130_fd_sc_hd__a2bb2oi_4" "sky130_fd_sc_hd__a2bb2oi_4" 4 61823;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000355f968 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b9340_0 .net "A1_N", 0 0, o000000000355f968; 0 drivers
+o000000000355f998 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035b93e0_0 .net "A2_N", 0 0, o000000000355f998; 0 drivers
+o000000000355f9c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ba100_0 .net "B1", 0 0, o000000000355f9c8; 0 drivers
+o000000000355f9f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ba060_0 .net "B2", 0 0, o000000000355f9f8; 0 drivers
+L_000000000388f3b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ba420_0 .net8 "VGND", 0 0, L_000000000388f3b0; 1 drivers, strength-aware
+L_000000000388f570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b8a80_0 .net8 "VNB", 0 0, L_000000000388f570; 1 drivers, strength-aware
+L_0000000003890c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b97a0_0 .net8 "VPB", 0 0, L_0000000003890c30; 1 drivers, strength-aware
+L_000000000388f0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b9020_0 .net8 "VPWR", 0 0, L_000000000388f0a0; 1 drivers, strength-aware
+v00000000035ba1a0_0 .net "Y", 0 0, L_000000000392c560; 1 drivers
+S_00000000034dfbb0 .scope module, "base" "sky130_fd_sc_hd__a2bb2oi" 4 61843, 4 62165 1, S_00000000028317d0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000392cb10 .functor AND 1, o000000000355f9c8, o000000000355f9f8, C4<1>, C4<1>;
+L_000000000392d280 .functor NOR 1, o000000000355f968, o000000000355f998, C4<0>, C4<0>;
+L_000000000392c870 .functor NOR 1, L_000000000392d280, L_000000000392cb10, C4<0>, C4<0>;
+L_000000000392c560 .functor BUF 1, L_000000000392c870, C4<0>, C4<0>, C4<0>;
+v00000000035b89e0_0 .net "A1_N", 0 0, o000000000355f968; alias, 0 drivers
+v00000000035b9200_0 .net "A2_N", 0 0, o000000000355f998; alias, 0 drivers
+v00000000035b95c0_0 .net "B1", 0 0, o000000000355f9c8; alias, 0 drivers
+v00000000035b9f20_0 .net "B2", 0 0, o000000000355f9f8; alias, 0 drivers
+L_000000000388f8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ba2e0_0 .net8 "VGND", 0 0, L_000000000388f8f0; 1 drivers, strength-aware
+L_00000000038906f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ba920_0 .net8 "VNB", 0 0, L_00000000038906f0; 1 drivers, strength-aware
+L_00000000038901b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b8b20_0 .net8 "VPB", 0 0, L_00000000038901b0; 1 drivers, strength-aware
+L_000000000388f180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035b9de0_0 .net8 "VPWR", 0 0, L_000000000388f180; 1 drivers, strength-aware
+v00000000035b8f80_0 .net "Y", 0 0, L_000000000392c560; alias, 1 drivers
+v00000000035b9a20_0 .net "and0_out", 0 0, L_000000000392cb10; 1 drivers
+v00000000035bab00_0 .net "nor0_out", 0 0, L_000000000392d280; 1 drivers
+v00000000035b9fc0_0 .net "nor1_out_Y", 0 0, L_000000000392c870; 1 drivers
+S_0000000002832760 .scope module, "sky130_fd_sc_hd__a311o_1" "sky130_fd_sc_hd__a311o_1" 4 35018;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o000000000355fe48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bd120_0 .net "A1", 0 0, o000000000355fe48; 0 drivers
+o000000000355fe78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bcb80_0 .net "A2", 0 0, o000000000355fe78; 0 drivers
+o000000000355fea8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bb460_0 .net "A3", 0 0, o000000000355fea8; 0 drivers
+o000000000355fed8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bd440_0 .net "B1", 0 0, o000000000355fed8; 0 drivers
+o000000000355ff08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bd580_0 .net "C1", 0 0, o000000000355ff08; 0 drivers
+L_000000000388f9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bb1e0_0 .net8 "VGND", 0 0, L_000000000388f9d0; 1 drivers, strength-aware
+L_0000000003890220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bc900_0 .net8 "VNB", 0 0, L_0000000003890220; 1 drivers, strength-aware
+L_000000000388f1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bbaa0_0 .net8 "VPB", 0 0, L_000000000388f1f0; 1 drivers, strength-aware
+L_0000000003890290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bc360_0 .net8 "VPWR", 0 0, L_0000000003890290; 1 drivers, strength-aware
+v00000000035bb500_0 .net "X", 0 0, L_000000000392d750; 1 drivers
+S_00000000034dfeb0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 35040, 4 35484 1, S_0000000002832760;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392c8e0 .functor AND 1, o000000000355fea8, o000000000355fe48, o000000000355fe78, C4<1>;
+L_000000000392cfe0 .functor OR 1, L_000000000392c8e0, o000000000355ff08, o000000000355fed8, C4<0>;
+L_000000000392d750 .functor BUF 1, L_000000000392cfe0, C4<0>, C4<0>, C4<0>;
+v00000000035ba4c0_0 .net "A1", 0 0, o000000000355fe48; alias, 0 drivers
+v00000000035baba0_0 .net "A2", 0 0, o000000000355fe78; alias, 0 drivers
+v00000000035ba560_0 .net "A3", 0 0, o000000000355fea8; alias, 0 drivers
+v00000000035b8da0_0 .net "B1", 0 0, o000000000355fed8; alias, 0 drivers
+v00000000035b9520_0 .net "C1", 0 0, o000000000355ff08; alias, 0 drivers
+L_00000000038903e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035b9480_0 .net8 "VGND", 0 0, L_00000000038903e0; 1 drivers, strength-aware
+L_000000000388f5e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ba6a0_0 .net8 "VNB", 0 0, L_000000000388f5e0; 1 drivers, strength-aware
+L_000000000388f650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ba880_0 .net8 "VPB", 0 0, L_000000000388f650; 1 drivers, strength-aware
+L_000000000388ff10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bac40_0 .net8 "VPWR", 0 0, L_000000000388ff10; 1 drivers, strength-aware
+v00000000035bcae0_0 .net "X", 0 0, L_000000000392d750; alias, 1 drivers
+v00000000035bc180_0 .net "and0_out", 0 0, L_000000000392c8e0; 1 drivers
+v00000000035bd6c0_0 .net "or0_out_X", 0 0, L_000000000392cfe0; 1 drivers
+S_0000000002833f60 .scope module, "sky130_fd_sc_hd__a311o_2" "sky130_fd_sc_hd__a311o_2" 4 34892;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003560388 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bb320_0 .net "A1", 0 0, o0000000003560388; 0 drivers
+o00000000035603b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bb780_0 .net "A2", 0 0, o00000000035603b8; 0 drivers
+o00000000035603e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bcea0_0 .net "A3", 0 0, o00000000035603e8; 0 drivers
+o0000000003560418 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bd8a0_0 .net "B1", 0 0, o0000000003560418; 0 drivers
+o0000000003560448 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bc220_0 .net "C1", 0 0, o0000000003560448; 0 drivers
+L_000000000388fa40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bca40_0 .net8 "VGND", 0 0, L_000000000388fa40; 1 drivers, strength-aware
+L_000000000388f6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bc040_0 .net8 "VNB", 0 0, L_000000000388f6c0; 1 drivers, strength-aware
+L_0000000003890450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bc680_0 .net8 "VPB", 0 0, L_0000000003890450; 1 drivers, strength-aware
+L_00000000038907d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bc7c0_0 .net8 "VPWR", 0 0, L_00000000038907d0; 1 drivers, strength-aware
+v00000000035bd760_0 .net "X", 0 0, L_000000000392c330; 1 drivers
+S_00000000034e0db0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 34914, 4 35484 1, S_0000000002833f60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392c950 .functor AND 1, o00000000035603e8, o0000000003560388, o00000000035603b8, C4<1>;
+L_000000000392d2f0 .functor OR 1, L_000000000392c950, o0000000003560448, o0000000003560418, C4<0>;
+L_000000000392c330 .functor BUF 1, L_000000000392d2f0, C4<0>, C4<0>, C4<0>;
+v00000000035bbb40_0 .net "A1", 0 0, o0000000003560388; alias, 0 drivers
+v00000000035bc5e0_0 .net "A2", 0 0, o00000000035603b8; alias, 0 drivers
+v00000000035bb5a0_0 .net "A3", 0 0, o00000000035603e8; alias, 0 drivers
+v00000000035bc400_0 .net "B1", 0 0, o0000000003560418; alias, 0 drivers
+v00000000035bd1c0_0 .net "C1", 0 0, o0000000003560448; alias, 0 drivers
+L_000000000388fb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bd260_0 .net8 "VGND", 0 0, L_000000000388fb20; 1 drivers, strength-aware
+L_0000000003890840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bce00_0 .net8 "VNB", 0 0, L_0000000003890840; 1 drivers, strength-aware
+L_000000000388f730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bd4e0_0 .net8 "VPB", 0 0, L_000000000388f730; 1 drivers, strength-aware
+L_000000000388f810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bc540_0 .net8 "VPWR", 0 0, L_000000000388f810; 1 drivers, strength-aware
+v00000000035bd620_0 .net "X", 0 0, L_000000000392c330; alias, 1 drivers
+v00000000035bb640_0 .net "and0_out", 0 0, L_000000000392c950; 1 drivers
+v00000000035bb960_0 .net "or0_out_X", 0 0, L_000000000392d2f0; 1 drivers
+S_0000000002832d60 .scope module, "sky130_fd_sc_hd__a311o_4" "sky130_fd_sc_hd__a311o_4" 4 35144;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o00000000035608c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bb3c0_0 .net "A1", 0 0, o00000000035608c8; 0 drivers
+o00000000035608f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bc9a0_0 .net "A2", 0 0, o00000000035608f8; 0 drivers
+o0000000003560928 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bcd60_0 .net "A3", 0 0, o0000000003560928; 0 drivers
+o0000000003560958 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bc2c0_0 .net "B1", 0 0, o0000000003560958; 0 drivers
+o0000000003560988 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bbdc0_0 .net "C1", 0 0, o0000000003560988; 0 drivers
+L_000000000388fb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bb8c0_0 .net8 "VGND", 0 0, L_000000000388fb90; 1 drivers, strength-aware
+L_0000000003890ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bbbe0_0 .net8 "VNB", 0 0, L_0000000003890ae0; 1 drivers, strength-aware
+L_0000000003890920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bbc80_0 .net8 "VPB", 0 0, L_0000000003890920; 1 drivers, strength-aware
+L_000000000388fd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bbd20_0 .net8 "VPWR", 0 0, L_000000000388fd50; 1 drivers, strength-aware
+v00000000035bbe60_0 .net "X", 0 0, L_000000000392d980; 1 drivers
+S_00000000034dd1b0 .scope module, "base" "sky130_fd_sc_hd__a311o" 4 35166, 4 35484 1, S_0000000002832d60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392c9c0 .functor AND 1, o0000000003560928, o00000000035608c8, o00000000035608f8, C4<1>;
+L_000000000392ce90 .functor OR 1, L_000000000392c9c0, o0000000003560988, o0000000003560958, C4<0>;
+L_000000000392d980 .functor BUF 1, L_000000000392ce90, C4<0>, C4<0>, C4<0>;
+v00000000035bcf40_0 .net "A1", 0 0, o00000000035608c8; alias, 0 drivers
+v00000000035bb140_0 .net "A2", 0 0, o00000000035608f8; alias, 0 drivers
+v00000000035bc720_0 .net "A3", 0 0, o0000000003560928; alias, 0 drivers
+v00000000035bb6e0_0 .net "B1", 0 0, o0000000003560958; alias, 0 drivers
+v00000000035bcfe0_0 .net "C1", 0 0, o0000000003560988; alias, 0 drivers
+L_000000000388f960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bb820_0 .net8 "VGND", 0 0, L_000000000388f960; 1 drivers, strength-aware
+L_000000000388fc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bd080_0 .net8 "VNB", 0 0, L_000000000388fc00; 1 drivers, strength-aware
+L_000000000388fc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bd800_0 .net8 "VPB", 0 0, L_000000000388fc70; 1 drivers, strength-aware
+L_0000000003890990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bb280_0 .net8 "VPWR", 0 0, L_0000000003890990; 1 drivers, strength-aware
+v00000000035bd300_0 .net "X", 0 0, L_000000000392d980; alias, 1 drivers
+v00000000035bd3a0_0 .net "and0_out", 0 0, L_000000000392c9c0; 1 drivers
+v00000000035bba00_0 .net "or0_out_X", 0 0, L_000000000392ce90; 1 drivers
+S_00000000028337e0 .scope module, "sky130_fd_sc_hd__a311oi_1" "sky130_fd_sc_hd__a311oi_1" 4 98967;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003560e08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bf7e0_0 .net "A1", 0 0, o0000000003560e08; 0 drivers
+o0000000003560e38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035be160_0 .net "A2", 0 0, o0000000003560e38; 0 drivers
+o0000000003560e68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bd9e0_0 .net "A3", 0 0, o0000000003560e68; 0 drivers
+o0000000003560e98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bfba0_0 .net "B1", 0 0, o0000000003560e98; 0 drivers
+o0000000003560ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035be200_0 .net "C1", 0 0, o0000000003560ec8; 0 drivers
+L_00000000038904c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035be5c0_0 .net8 "VGND", 0 0, L_00000000038904c0; 1 drivers, strength-aware
+L_0000000003890530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bdee0_0 .net8 "VNB", 0 0, L_0000000003890530; 1 drivers, strength-aware
+L_0000000003890a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035be660_0 .net8 "VPB", 0 0, L_0000000003890a00; 1 drivers, strength-aware
+L_000000000388fe30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bdbc0_0 .net8 "VPWR", 0 0, L_000000000388fe30; 1 drivers, strength-aware
+v00000000035bf100_0 .net "Y", 0 0, L_000000000392c790; 1 drivers
+S_00000000034dd630 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98989, 4 98585 1, S_00000000028337e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392c170 .functor AND 1, o0000000003560e68, o0000000003560e08, o0000000003560e38, C4<1>;
+L_000000000392d130 .functor NOR 1, L_000000000392c170, o0000000003560e98, o0000000003560ec8, C4<0>;
+L_000000000392c790 .functor BUF 1, L_000000000392d130, C4<0>, C4<0>, C4<0>;
+v00000000035bbf00_0 .net "A1", 0 0, o0000000003560e08; alias, 0 drivers
+v00000000035bc860_0 .net "A2", 0 0, o0000000003560e38; alias, 0 drivers
+v00000000035bbfa0_0 .net "A3", 0 0, o0000000003560e68; alias, 0 drivers
+v00000000035bc0e0_0 .net "B1", 0 0, o0000000003560e98; alias, 0 drivers
+v00000000035bc4a0_0 .net "C1", 0 0, o0000000003560ec8; alias, 0 drivers
+L_000000000388fea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bcc20_0 .net8 "VGND", 0 0, L_000000000388fea0; 1 drivers, strength-aware
+L_00000000038921a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bccc0_0 .net8 "VNB", 0 0, L_00000000038921a0; 1 drivers, strength-aware
+L_0000000003890d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035be0c0_0 .net8 "VPB", 0 0, L_0000000003890d10; 1 drivers, strength-aware
+L_0000000003890e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bf740_0 .net8 "VPWR", 0 0, L_0000000003890e60; 1 drivers, strength-aware
+v00000000035c00a0_0 .net "Y", 0 0, L_000000000392c790; alias, 1 drivers
+v00000000035bfec0_0 .net "and0_out", 0 0, L_000000000392c170; 1 drivers
+v00000000035befc0_0 .net "nor0_out_Y", 0 0, L_000000000392d130; 1 drivers
+S_0000000002832ee0 .scope module, "sky130_fd_sc_hd__a311oi_2" "sky130_fd_sc_hd__a311oi_2" 4 98715;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003561348 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bdc60_0 .net "A1", 0 0, o0000000003561348; 0 drivers
+o0000000003561378 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035be700_0 .net "A2", 0 0, o0000000003561378; 0 drivers
+o00000000035613a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035be480_0 .net "A3", 0 0, o00000000035613a8; 0 drivers
+o00000000035613d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bfd80_0 .net "B1", 0 0, o00000000035613d8; 0 drivers
+o0000000003561408 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035be520_0 .net "C1", 0 0, o0000000003561408; 0 drivers
+L_0000000003892750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035beac0_0 .net8 "VGND", 0 0, L_0000000003892750; 1 drivers, strength-aware
+L_0000000003891f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bf9c0_0 .net8 "VNB", 0 0, L_0000000003891f70; 1 drivers, strength-aware
+L_0000000003892210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035be3e0_0 .net8 "VPB", 0 0, L_0000000003892210; 1 drivers, strength-aware
+L_0000000003891020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bee80_0 .net8 "VPWR", 0 0, L_0000000003891020; 1 drivers, strength-aware
+v00000000035beb60_0 .net "Y", 0 0, L_000000000392d3d0; 1 drivers
+S_00000000034dd930 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98737, 4 98585 1, S_0000000002832ee0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392cbf0 .functor AND 1, o00000000035613a8, o0000000003561348, o0000000003561378, C4<1>;
+L_000000000392d1a0 .functor NOR 1, L_000000000392cbf0, o00000000035613d8, o0000000003561408, C4<0>;
+L_000000000392d3d0 .functor BUF 1, L_000000000392d1a0, C4<0>, C4<0>, C4<0>;
+v00000000035bf600_0 .net "A1", 0 0, o0000000003561348; alias, 0 drivers
+v00000000035bea20_0 .net "A2", 0 0, o0000000003561378; alias, 0 drivers
+v00000000035beca0_0 .net "A3", 0 0, o00000000035613a8; alias, 0 drivers
+v00000000035be340_0 .net "B1", 0 0, o00000000035613d8; alias, 0 drivers
+v00000000035be980_0 .net "C1", 0 0, o0000000003561408; alias, 0 drivers
+L_0000000003891bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bdf80_0 .net8 "VGND", 0 0, L_0000000003891bf0; 1 drivers, strength-aware
+L_0000000003891480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035be840_0 .net8 "VNB", 0 0, L_0000000003891480; 1 drivers, strength-aware
+L_0000000003891640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035be020_0 .net8 "VPB", 0 0, L_0000000003891640; 1 drivers, strength-aware
+L_0000000003890ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bef20_0 .net8 "VPWR", 0 0, L_0000000003890ed0; 1 drivers, strength-aware
+v00000000035be2a0_0 .net "Y", 0 0, L_000000000392d3d0; alias, 1 drivers
+v00000000035be8e0_0 .net "and0_out", 0 0, L_000000000392cbf0; 1 drivers
+v00000000035be7a0_0 .net "nor0_out_Y", 0 0, L_000000000392d1a0; 1 drivers
+S_0000000002833960 .scope module, "sky130_fd_sc_hd__a311oi_4" "sky130_fd_sc_hd__a311oi_4" 4 98841;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003561888 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bf240_0 .net "A1", 0 0, o0000000003561888; 0 drivers
+o00000000035618b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bdda0_0 .net "A2", 0 0, o00000000035618b8; 0 drivers
+o00000000035618e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bda80_0 .net "A3", 0 0, o00000000035618e8; 0 drivers
+o0000000003561918 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bf420_0 .net "B1", 0 0, o0000000003561918; 0 drivers
+o0000000003561948 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035bfa60_0 .net "C1", 0 0, o0000000003561948; 0 drivers
+L_0000000003891f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bf4c0_0 .net8 "VGND", 0 0, L_0000000003891f00; 1 drivers, strength-aware
+L_00000000038922f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c0000_0 .net8 "VNB", 0 0, L_00000000038922f0; 1 drivers, strength-aware
+L_00000000038927c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bf560_0 .net8 "VPB", 0 0, L_00000000038927c0; 1 drivers, strength-aware
+L_0000000003891e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bfb00_0 .net8 "VPWR", 0 0, L_0000000003891e90; 1 drivers, strength-aware
+v00000000035bfc40_0 .net "Y", 0 0, L_000000000392d600; 1 drivers
+S_00000000034dcd30 .scope module, "base" "sky130_fd_sc_hd__a311oi" 4 98863, 4 98585 1, S_0000000002833960;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000392d590 .functor AND 1, o00000000035618e8, o0000000003561888, o00000000035618b8, C4<1>;
+L_000000000392cc60 .functor NOR 1, L_000000000392d590, o0000000003561918, o0000000003561948, C4<0>;
+L_000000000392d600 .functor BUF 1, L_000000000392cc60, C4<0>, C4<0>, C4<0>;
+v00000000035bdd00_0 .net "A1", 0 0, o0000000003561888; alias, 0 drivers
+v00000000035bf2e0_0 .net "A2", 0 0, o00000000035618b8; alias, 0 drivers
+v00000000035bf6a0_0 .net "A3", 0 0, o00000000035618e8; alias, 0 drivers
+v00000000035bec00_0 .net "B1", 0 0, o0000000003561918; alias, 0 drivers
+v00000000035bff60_0 .net "C1", 0 0, o0000000003561948; alias, 0 drivers
+L_0000000003891720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bed40_0 .net8 "VGND", 0 0, L_0000000003891720; 1 drivers, strength-aware
+L_0000000003891d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bede0_0 .net8 "VNB", 0 0, L_0000000003891d40; 1 drivers, strength-aware
+L_0000000003891e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bf060_0 .net8 "VPB", 0 0, L_0000000003891e20; 1 drivers, strength-aware
+L_0000000003891950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035bf920_0 .net8 "VPWR", 0 0, L_0000000003891950; 1 drivers, strength-aware
+v00000000035bf380_0 .net "Y", 0 0, L_000000000392d600; alias, 1 drivers
+v00000000035bf1a0_0 .net "and0_out", 0 0, L_000000000392d590; 1 drivers
+v00000000035bf880_0 .net "nor0_out_Y", 0 0, L_000000000392cc60; 1 drivers
+S_00000000028334e0 .scope module, "sky130_fd_sc_hd__a31o_1" "sky130_fd_sc_hd__a31o_1" 4 41662;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003561dc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c28a0_0 .net "A1", 0 0, o0000000003561dc8; 0 drivers
+o0000000003561df8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c1540_0 .net "A2", 0 0, o0000000003561df8; 0 drivers
+o0000000003561e28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c0460_0 .net "A3", 0 0, o0000000003561e28; 0 drivers
+o0000000003561e58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c1680_0 .net "B1", 0 0, o0000000003561e58; 0 drivers
+L_0000000003891330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c06e0_0 .net8 "VGND", 0 0, L_0000000003891330; 1 drivers, strength-aware
+L_0000000003891170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1720_0 .net8 "VNB", 0 0, L_0000000003891170; 1 drivers, strength-aware
+L_0000000003891fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c0960_0 .net8 "VPB", 0 0, L_0000000003891fe0; 1 drivers, strength-aware
+L_00000000038924b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c1860_0 .net8 "VPWR", 0 0, L_00000000038924b0; 1 drivers, strength-aware
+v00000000035c2080_0 .net "X", 0 0, L_000000000392d4b0; 1 drivers
+S_00000000034e0030 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 41682, 4 41993 1, S_00000000028334e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392dbb0 .functor AND 1, o0000000003561e28, o0000000003561dc8, o0000000003561df8, C4<1>;
+L_000000000392d440 .functor OR 1, L_000000000392dbb0, o0000000003561e58, C4<0>, C4<0>;
+L_000000000392d4b0 .functor BUF 1, L_000000000392d440, C4<0>, C4<0>, C4<0>;
+v00000000035bfce0_0 .net "A1", 0 0, o0000000003561dc8; alias, 0 drivers
+v00000000035bfe20_0 .net "A2", 0 0, o0000000003561df8; alias, 0 drivers
+v00000000035bd940_0 .net "A3", 0 0, o0000000003561e28; alias, 0 drivers
+v00000000035bde40_0 .net "B1", 0 0, o0000000003561e58; alias, 0 drivers
+L_0000000003891aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035bdb20_0 .net8 "VGND", 0 0, L_0000000003891aa0; 1 drivers, strength-aware
+L_0000000003890ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c12c0_0 .net8 "VNB", 0 0, L_0000000003890ca0; 1 drivers, strength-aware
+L_0000000003892050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2760_0 .net8 "VPB", 0 0, L_0000000003892050; 1 drivers, strength-aware
+L_0000000003890fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c14a0_0 .net8 "VPWR", 0 0, L_0000000003890fb0; 1 drivers, strength-aware
+v00000000035c17c0_0 .net "X", 0 0, L_000000000392d4b0; alias, 1 drivers
+v00000000035c1a40_0 .net "and0_out", 0 0, L_000000000392dbb0; 1 drivers
+v00000000035c0f00_0 .net "or0_out_X", 0 0, L_000000000392d440; 1 drivers
+S_0000000002833060 .scope module, "sky130_fd_sc_hd__a31o_2" "sky130_fd_sc_hd__a31o_2" 4 42118;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003562278 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c1d60_0 .net "A1", 0 0, o0000000003562278; 0 drivers
+o00000000035622a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c19a0_0 .net "A2", 0 0, o00000000035622a8; 0 drivers
+o00000000035622d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c08c0_0 .net "A3", 0 0, o00000000035622d8; 0 drivers
+o0000000003562308 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c0aa0_0 .net "B1", 0 0, o0000000003562308; 0 drivers
+L_0000000003890f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1ae0_0 .net8 "VGND", 0 0, L_0000000003890f40; 1 drivers, strength-aware
+L_00000000038920c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c0c80_0 .net8 "VNB", 0 0, L_00000000038920c0; 1 drivers, strength-aware
+L_0000000003892130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c0640_0 .net8 "VPB", 0 0, L_0000000003892130; 1 drivers, strength-aware
+L_00000000038911e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2300_0 .net8 "VPWR", 0 0, L_00000000038911e0; 1 drivers, strength-aware
+v00000000035c0140_0 .net "X", 0 0, L_000000000392da60; 1 drivers
+S_00000000034dbfb0 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 42138, 4 41993 1, S_0000000002833060;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392ca30 .functor AND 1, o00000000035622d8, o0000000003562278, o00000000035622a8, C4<1>;
+L_000000000392d520 .functor OR 1, L_000000000392ca30, o0000000003562308, C4<0>, C4<0>;
+L_000000000392da60 .functor BUF 1, L_000000000392d520, C4<0>, C4<0>, C4<0>;
+v00000000035c0780_0 .net "A1", 0 0, o0000000003562278; alias, 0 drivers
+v00000000035c2440_0 .net "A2", 0 0, o00000000035622a8; alias, 0 drivers
+v00000000035c0280_0 .net "A3", 0 0, o00000000035622d8; alias, 0 drivers
+v00000000035c1220_0 .net "B1", 0 0, o0000000003562308; alias, 0 drivers
+L_00000000038923d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1360_0 .net8 "VGND", 0 0, L_00000000038923d0; 1 drivers, strength-aware
+L_0000000003890d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1cc0_0 .net8 "VNB", 0 0, L_0000000003890d80; 1 drivers, strength-aware
+L_0000000003892590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c1e00_0 .net8 "VPB", 0 0, L_0000000003892590; 1 drivers, strength-aware
+L_00000000038919c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2120_0 .net8 "VPWR", 0 0, L_00000000038919c0; 1 drivers, strength-aware
+v00000000035c0320_0 .net "X", 0 0, L_000000000392da60; alias, 1 drivers
+v00000000035c1900_0 .net "and0_out", 0 0, L_000000000392ca30; 1 drivers
+v00000000035c0b40_0 .net "or0_out_X", 0 0, L_000000000392d520; 1 drivers
+S_00000000028328e0 .scope module, "sky130_fd_sc_hd__a31o_4" "sky130_fd_sc_hd__a31o_4" 4 42238;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003562728 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c26c0_0 .net "A1", 0 0, o0000000003562728; 0 drivers
+o0000000003562758 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c0be0_0 .net "A2", 0 0, o0000000003562758; 0 drivers
+o0000000003562788 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c24e0_0 .net "A3", 0 0, o0000000003562788; 0 drivers
+o00000000035627b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c21c0_0 .net "B1", 0 0, o00000000035627b8; 0 drivers
+L_0000000003891c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c2580_0 .net8 "VGND", 0 0, L_0000000003891c60; 1 drivers, strength-aware
+L_0000000003892520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c23a0_0 .net8 "VNB", 0 0, L_0000000003892520; 1 drivers, strength-aware
+L_0000000003892280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2620_0 .net8 "VPB", 0 0, L_0000000003892280; 1 drivers, strength-aware
+L_0000000003892670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2800_0 .net8 "VPWR", 0 0, L_0000000003892670; 1 drivers, strength-aware
+v00000000035c03c0_0 .net "X", 0 0, L_000000000392d7c0; 1 drivers
+S_00000000034db0b0 .scope module, "base" "sky130_fd_sc_hd__a31o" 4 42258, 4 41993 1, S_00000000028328e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392d910 .functor AND 1, o0000000003562788, o0000000003562728, o0000000003562758, C4<1>;
+L_000000000392c1e0 .functor OR 1, L_000000000392d910, o00000000035627b8, C4<0>, C4<0>;
+L_000000000392d7c0 .functor BUF 1, L_000000000392c1e0, C4<0>, C4<0>, C4<0>;
+v00000000035c0820_0 .net "A1", 0 0, o0000000003562728; alias, 0 drivers
+v00000000035c0a00_0 .net "A2", 0 0, o0000000003562758; alias, 0 drivers
+v00000000035c1c20_0 .net "A3", 0 0, o0000000003562788; alias, 0 drivers
+v00000000035c2260_0 .net "B1", 0 0, o00000000035627b8; alias, 0 drivers
+L_0000000003891100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c01e0_0 .net8 "VGND", 0 0, L_0000000003891100; 1 drivers, strength-aware
+L_0000000003892600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1b80_0 .net8 "VNB", 0 0, L_0000000003892600; 1 drivers, strength-aware
+L_0000000003890df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c1ea0_0 .net8 "VPB", 0 0, L_0000000003890df0; 1 drivers, strength-aware
+L_0000000003891090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c15e0_0 .net8 "VPWR", 0 0, L_0000000003891090; 1 drivers, strength-aware
+v00000000035c0d20_0 .net "X", 0 0, L_000000000392d7c0; alias, 1 drivers
+v00000000035c1f40_0 .net "and0_out", 0 0, L_000000000392d910; 1 drivers
+v00000000035c1fe0_0 .net "or0_out_X", 0 0, L_000000000392c1e0; 1 drivers
+S_00000000028340e0 .scope module, "sky130_fd_sc_hd__a31oi_1" "sky130_fd_sc_hd__a31oi_1" 4 72207;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003562bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c32a0_0 .net "A1", 0 0, o0000000003562bd8; 0 drivers
+o0000000003562c08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c42e0_0 .net "A2", 0 0, o0000000003562c08; 0 drivers
+o0000000003562c38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c3160_0 .net "A3", 0 0, o0000000003562c38; 0 drivers
+o0000000003562c68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c4600_0 .net "B1", 0 0, o0000000003562c68; 0 drivers
+L_00000000038913a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c30c0_0 .net8 "VGND", 0 0, L_00000000038913a0; 1 drivers, strength-aware
+L_0000000003891410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c2bc0_0 .net8 "VNB", 0 0, L_0000000003891410; 1 drivers, strength-aware
+L_0000000003892360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c4ce0_0 .net8 "VPB", 0 0, L_0000000003892360; 1 drivers, strength-aware
+L_0000000003892440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2f80_0 .net8 "VPWR", 0 0, L_0000000003892440; 1 drivers, strength-aware
+v00000000035c3200_0 .net "Y", 0 0, L_000000000392ccd0; 1 drivers
+S_00000000034ddc30 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72227, 4 72538 1, S_00000000028340e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392d830 .functor AND 1, o0000000003562c38, o0000000003562bd8, o0000000003562c08, C4<1>;
+L_000000000392c2c0 .functor NOR 1, o0000000003562c68, L_000000000392d830, C4<0>, C4<0>;
+L_000000000392ccd0 .functor BUF 1, L_000000000392c2c0, C4<0>, C4<0>, C4<0>;
+v00000000035c0500_0 .net "A1", 0 0, o0000000003562bd8; alias, 0 drivers
+v00000000035c05a0_0 .net "A2", 0 0, o0000000003562c08; alias, 0 drivers
+v00000000035c0dc0_0 .net "A3", 0 0, o0000000003562c38; alias, 0 drivers
+v00000000035c0fa0_0 .net "B1", 0 0, o0000000003562c68; alias, 0 drivers
+L_00000000038926e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c0e60_0 .net8 "VGND", 0 0, L_00000000038926e0; 1 drivers, strength-aware
+L_0000000003891b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c1040_0 .net8 "VNB", 0 0, L_0000000003891b10; 1 drivers, strength-aware
+L_00000000038914f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c10e0_0 .net8 "VPB", 0 0, L_00000000038914f0; 1 drivers, strength-aware
+L_0000000003891250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c1180_0 .net8 "VPWR", 0 0, L_0000000003891250; 1 drivers, strength-aware
+v00000000035c1400_0 .net "Y", 0 0, L_000000000392ccd0; alias, 1 drivers
+v00000000035c49c0_0 .net "and0_out", 0 0, L_000000000392d830; 1 drivers
+v00000000035c4100_0 .net "nor0_out_Y", 0 0, L_000000000392c2c0; 1 drivers
+S_00000000028331e0 .scope module, "sky130_fd_sc_hd__a31oi_2" "sky130_fd_sc_hd__a31oi_2" 4 72663;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003563088 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c4380_0 .net "A1", 0 0, o0000000003563088; 0 drivers
+o00000000035630b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c3480_0 .net "A2", 0 0, o00000000035630b8; 0 drivers
+o00000000035630e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c4740_0 .net "A3", 0 0, o00000000035630e8; 0 drivers
+o0000000003563118 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c3980_0 .net "B1", 0 0, o0000000003563118; 0 drivers
+L_00000000038912c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c2c60_0 .net8 "VGND", 0 0, L_00000000038912c0; 1 drivers, strength-aware
+L_0000000003891a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c38e0_0 .net8 "VNB", 0 0, L_0000000003891a30; 1 drivers, strength-aware
+L_0000000003892830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c3020_0 .net8 "VPB", 0 0, L_0000000003892830; 1 drivers, strength-aware
+L_0000000003891560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c47e0_0 .net8 "VPWR", 0 0, L_0000000003891560; 1 drivers, strength-aware
+v00000000035c4420_0 .net "Y", 0 0, L_000000000392d9f0; 1 drivers
+S_00000000034decb0 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72683, 4 72538 1, S_00000000028331e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392d8a0 .functor AND 1, o00000000035630e8, o0000000003563088, o00000000035630b8, C4<1>;
+L_000000000392cd40 .functor NOR 1, o0000000003563118, L_000000000392d8a0, C4<0>, C4<0>;
+L_000000000392d9f0 .functor BUF 1, L_000000000392cd40, C4<0>, C4<0>, C4<0>;
+v00000000035c3fc0_0 .net "A1", 0 0, o0000000003563088; alias, 0 drivers
+v00000000035c41a0_0 .net "A2", 0 0, o00000000035630b8; alias, 0 drivers
+v00000000035c37a0_0 .net "A3", 0 0, o00000000035630e8; alias, 0 drivers
+v00000000035c3340_0 .net "B1", 0 0, o0000000003563118; alias, 0 drivers
+L_00000000038915d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c3de0_0 .net8 "VGND", 0 0, L_00000000038915d0; 1 drivers, strength-aware
+L_0000000003891870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c33e0_0 .net8 "VNB", 0 0, L_0000000003891870; 1 drivers, strength-aware
+L_00000000038918e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c3ac0_0 .net8 "VPB", 0 0, L_00000000038918e0; 1 drivers, strength-aware
+L_0000000003891b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c3c00_0 .net8 "VPWR", 0 0, L_0000000003891b80; 1 drivers, strength-aware
+v00000000035c4a60_0 .net "Y", 0 0, L_000000000392d9f0; alias, 1 drivers
+v00000000035c4b00_0 .net "and0_out", 0 0, L_000000000392d8a0; 1 drivers
+v00000000035c46a0_0 .net "nor0_out_Y", 0 0, L_000000000392cd40; 1 drivers
+S_0000000002833ae0 .scope module, "sky130_fd_sc_hd__a31oi_4" "sky130_fd_sc_hd__a31oi_4" 4 72087;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003563538 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c29e0_0 .net "A1", 0 0, o0000000003563538; 0 drivers
+o0000000003563568 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c3f20_0 .net "A2", 0 0, o0000000003563568; 0 drivers
+o0000000003563598 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c4d80_0 .net "A3", 0 0, o0000000003563598; 0 drivers
+o00000000035635c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c3700_0 .net "B1", 0 0, o00000000035635c8; 0 drivers
+L_00000000038916b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c3e80_0 .net8 "VGND", 0 0, L_00000000038916b0; 1 drivers, strength-aware
+L_0000000003891cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c2ee0_0 .net8 "VNB", 0 0, L_0000000003891cd0; 1 drivers, strength-aware
+L_0000000003891db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c3840_0 .net8 "VPB", 0 0, L_0000000003891db0; 1 drivers, strength-aware
+L_0000000003891790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2da0_0 .net8 "VPWR", 0 0, L_0000000003891790; 1 drivers, strength-aware
+v00000000035c4e20_0 .net "Y", 0 0, L_000000000392dc20; 1 drivers
+S_00000000034e0f30 .scope module, "base" "sky130_fd_sc_hd__a31oi" 4 72107, 4 72538 1, S_0000000002833ae0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_000000000392cdb0 .functor AND 1, o0000000003563598, o0000000003563538, o0000000003563568, C4<1>;
+L_000000000392dad0 .functor NOR 1, o00000000035635c8, L_000000000392cdb0, C4<0>, C4<0>;
+L_000000000392dc20 .functor BUF 1, L_000000000392dad0, C4<0>, C4<0>, C4<0>;
+v00000000035c4240_0 .net "A1", 0 0, o0000000003563538; alias, 0 drivers
+v00000000035c3ca0_0 .net "A2", 0 0, o0000000003563568; alias, 0 drivers
+v00000000035c2b20_0 .net "A3", 0 0, o0000000003563598; alias, 0 drivers
+v00000000035c5000_0 .net "B1", 0 0, o00000000035635c8; alias, 0 drivers
+L_0000000003891800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c3520_0 .net8 "VGND", 0 0, L_0000000003891800; 1 drivers, strength-aware
+L_0000000003893080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c50a0_0 .net8 "VNB", 0 0, L_0000000003893080; 1 drivers, strength-aware
+L_0000000003893b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c35c0_0 .net8 "VPB", 0 0, L_0000000003893b70; 1 drivers, strength-aware
+L_0000000003894200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c2940_0 .net8 "VPWR", 0 0, L_0000000003894200; 1 drivers, strength-aware
+v00000000035c4ec0_0 .net "Y", 0 0, L_000000000392dc20; alias, 1 drivers
+v00000000035c3660_0 .net "and0_out", 0 0, L_000000000392cdb0; 1 drivers
+v00000000035c2d00_0 .net "nor0_out_Y", 0 0, L_000000000392dad0; 1 drivers
+S_0000000002832be0 .scope module, "sky130_fd_sc_hd__a32o_1" "sky130_fd_sc_hd__a32o_1" 4 96611;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o00000000035639e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c78a0_0 .net "A1", 0 0, o00000000035639e8; 0 drivers
+o0000000003563a18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c6c20_0 .net "A2", 0 0, o0000000003563a18; 0 drivers
+o0000000003563a48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c69a0_0 .net "A3", 0 0, o0000000003563a48; 0 drivers
+o0000000003563a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5140_0 .net "B1", 0 0, o0000000003563a78; 0 drivers
+o0000000003563aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c7300_0 .net "B2", 0 0, o0000000003563aa8; 0 drivers
+L_0000000003894190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c5820_0 .net8 "VGND", 0 0, L_0000000003894190; 1 drivers, strength-aware
+L_00000000038943c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c76c0_0 .net8 "VNB", 0 0, L_00000000038943c0; 1 drivers, strength-aware
+L_00000000038937f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c7800_0 .net8 "VPB", 0 0, L_00000000038937f0; 1 drivers, strength-aware
+L_00000000038930f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c6cc0_0 .net8 "VPWR", 0 0, L_00000000038930f0; 1 drivers, strength-aware
+v00000000035c7260_0 .net "X", 0 0, L_000000000392c3a0; 1 drivers
+S_00000000034dceb0 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96633, 4 97089 1, S_0000000002832be0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392dc90 .functor AND 1, o0000000003563a48, o00000000035639e8, o0000000003563a18, C4<1>;
+L_000000000392c100 .functor AND 1, o0000000003563a78, o0000000003563aa8, C4<1>, C4<1>;
+L_000000000392c250 .functor OR 1, L_000000000392c100, L_000000000392dc90, C4<0>, C4<0>;
+L_000000000392c3a0 .functor BUF 1, L_000000000392c250, C4<0>, C4<0>, C4<0>;
+v00000000035c44c0_0 .net "A1", 0 0, o00000000035639e8; alias, 0 drivers
+v00000000035c4920_0 .net "A2", 0 0, o0000000003563a18; alias, 0 drivers
+v00000000035c4560_0 .net "A3", 0 0, o0000000003563a48; alias, 0 drivers
+v00000000035c3a20_0 .net "B1", 0 0, o0000000003563a78; alias, 0 drivers
+v00000000035c3b60_0 .net "B2", 0 0, o0000000003563aa8; alias, 0 drivers
+L_0000000003893e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c4ba0_0 .net8 "VGND", 0 0, L_0000000003893e10; 1 drivers, strength-aware
+L_0000000003892d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c4060_0 .net8 "VNB", 0 0, L_0000000003892d70; 1 drivers, strength-aware
+L_00000000038934e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c4880_0 .net8 "VPB", 0 0, L_00000000038934e0; 1 drivers, strength-aware
+L_0000000003894430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c3d40_0 .net8 "VPWR", 0 0, L_0000000003894430; 1 drivers, strength-aware
+v00000000035c2e40_0 .net "X", 0 0, L_000000000392c3a0; alias, 1 drivers
+v00000000035c4c40_0 .net "and0_out", 0 0, L_000000000392dc90; 1 drivers
+v00000000035c4f60_0 .net "and1_out", 0 0, L_000000000392c100; 1 drivers
+v00000000035c2a80_0 .net "or0_out_X", 0 0, L_000000000392c250; 1 drivers
+S_0000000002833360 .scope module, "sky130_fd_sc_hd__a32o_2" "sky130_fd_sc_hd__a32o_2" 4 96484;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003563f58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c55a0_0 .net "A1", 0 0, o0000000003563f58; 0 drivers
+o0000000003563f88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5280_0 .net "A2", 0 0, o0000000003563f88; 0 drivers
+o0000000003563fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c6e00_0 .net "A3", 0 0, o0000000003563fb8; 0 drivers
+o0000000003563fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5320_0 .net "B1", 0 0, o0000000003563fe8; 0 drivers
+o0000000003564018 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c58c0_0 .net "B2", 0 0, o0000000003564018; 0 drivers
+L_0000000003893470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c56e0_0 .net8 "VGND", 0 0, L_0000000003893470; 1 drivers, strength-aware
+L_0000000003892e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c6680_0 .net8 "VNB", 0 0, L_0000000003892e50; 1 drivers, strength-aware
+L_0000000003892910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c5d20_0 .net8 "VPB", 0 0, L_0000000003892910; 1 drivers, strength-aware
+L_00000000038931d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c7440_0 .net8 "VPWR", 0 0, L_00000000038931d0; 1 drivers, strength-aware
+v00000000035c6180_0 .net "X", 0 0, L_000000000392c640; 1 drivers
+S_00000000034de0b0 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96506, 4 97089 1, S_0000000002833360;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392c410 .functor AND 1, o0000000003563fb8, o0000000003563f58, o0000000003563f88, C4<1>;
+L_000000000392c4f0 .functor AND 1, o0000000003563fe8, o0000000003564018, C4<1>, C4<1>;
+L_000000000392c5d0 .functor OR 1, L_000000000392c4f0, L_000000000392c410, C4<0>, C4<0>;
+L_000000000392c640 .functor BUF 1, L_000000000392c5d0, C4<0>, C4<0>, C4<0>;
+v00000000035c6d60_0 .net "A1", 0 0, o0000000003563f58; alias, 0 drivers
+v00000000035c5780_0 .net "A2", 0 0, o0000000003563f88; alias, 0 drivers
+v00000000035c6ae0_0 .net "A3", 0 0, o0000000003563fb8; alias, 0 drivers
+v00000000035c73a0_0 .net "B1", 0 0, o0000000003563fe8; alias, 0 drivers
+v00000000035c5640_0 .net "B2", 0 0, o0000000003564018; alias, 0 drivers
+L_0000000003892ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c6b80_0 .net8 "VGND", 0 0, L_0000000003892ec0; 1 drivers, strength-aware
+L_0000000003894350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c74e0_0 .net8 "VNB", 0 0, L_0000000003894350; 1 drivers, strength-aware
+L_00000000038932b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c6a40_0 .net8 "VPB", 0 0, L_00000000038932b0; 1 drivers, strength-aware
+L_0000000003893160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c6400_0 .net8 "VPWR", 0 0, L_0000000003893160; 1 drivers, strength-aware
+v00000000035c6900_0 .net "X", 0 0, L_000000000392c640; alias, 1 drivers
+v00000000035c5460_0 .net "and0_out", 0 0, L_000000000392c410; 1 drivers
+v00000000035c51e0_0 .net "and1_out", 0 0, L_000000000392c4f0; 1 drivers
+v00000000035c6220_0 .net "or0_out_X", 0 0, L_000000000392c5d0; 1 drivers
+S_0000000002832460 .scope module, "sky130_fd_sc_hd__a32o_4" "sky130_fd_sc_hd__a32o_4" 4 96738;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o00000000035644c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5a00_0 .net "A1", 0 0, o00000000035644c8; 0 drivers
+o00000000035644f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5aa0_0 .net "A2", 0 0, o00000000035644f8; 0 drivers
+o0000000003564528 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c67c0_0 .net "A3", 0 0, o0000000003564528; 0 drivers
+o0000000003564558 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5b40_0 .net "B1", 0 0, o0000000003564558; 0 drivers
+o0000000003564588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c5be0_0 .net "B2", 0 0, o0000000003564588; 0 drivers
+L_0000000003892f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c5c80_0 .net8 "VGND", 0 0, L_0000000003892f30; 1 drivers, strength-aware
+L_0000000003892fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c62c0_0 .net8 "VNB", 0 0, L_0000000003892fa0; 1 drivers, strength-aware
+L_0000000003893010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c65e0_0 .net8 "VPB", 0 0, L_0000000003893010; 1 drivers, strength-aware
+L_0000000003893240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c5dc0_0 .net8 "VPWR", 0 0, L_0000000003893240; 1 drivers, strength-aware
+v00000000035c6360_0 .net "X", 0 0, L_000000000392e390; 1 drivers
+S_00000000034dfa30 .scope module, "base" "sky130_fd_sc_hd__a32o" 4 96760, 4 97089 1, S_0000000002832460;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392c6b0 .functor AND 1, o0000000003564528, o00000000035644c8, o00000000035644f8, C4<1>;
+L_000000000392c720 .functor AND 1, o0000000003564558, o0000000003564588, C4<1>, C4<1>;
+L_000000000392e630 .functor OR 1, L_000000000392c720, L_000000000392c6b0, C4<0>, C4<0>;
+L_000000000392e390 .functor BUF 1, L_000000000392e630, C4<0>, C4<0>, C4<0>;
+v00000000035c5960_0 .net "A1", 0 0, o00000000035644c8; alias, 0 drivers
+v00000000035c6ea0_0 .net "A2", 0 0, o00000000035644f8; alias, 0 drivers
+v00000000035c7580_0 .net "A3", 0 0, o0000000003564528; alias, 0 drivers
+v00000000035c53c0_0 .net "B1", 0 0, o0000000003564558; alias, 0 drivers
+v00000000035c6f40_0 .net "B2", 0 0, o0000000003564588; alias, 0 drivers
+L_0000000003893550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c5fa0_0 .net8 "VGND", 0 0, L_0000000003893550; 1 drivers, strength-aware
+L_0000000003892c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c7120_0 .net8 "VNB", 0 0, L_0000000003892c20; 1 drivers, strength-aware
+L_0000000003893860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c7620_0 .net8 "VPB", 0 0, L_0000000003893860; 1 drivers, strength-aware
+L_00000000038935c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c6fe0_0 .net8 "VPWR", 0 0, L_00000000038935c0; 1 drivers, strength-aware
+v00000000035c7080_0 .net "X", 0 0, L_000000000392e390; alias, 1 drivers
+v00000000035c7760_0 .net "and0_out", 0 0, L_000000000392c6b0; 1 drivers
+v00000000035c5500_0 .net "and1_out", 0 0, L_000000000392c720; 1 drivers
+v00000000035c71c0_0 .net "or0_out_X", 0 0, L_000000000392e630; 1 drivers
+S_0000000002833660 .scope module, "sky130_fd_sc_hd__a32oi_1" "sky130_fd_sc_hd__a32oi_1" 4 101708;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003564a38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8520_0 .net "A1", 0 0, o0000000003564a38; 0 drivers
+o0000000003564a68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8fc0_0 .net "A2", 0 0, o0000000003564a68; 0 drivers
+o0000000003564a98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c9240_0 .net "A3", 0 0, o0000000003564a98; 0 drivers
+o0000000003564ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8020_0 .net "B1", 0 0, o0000000003564ac8; 0 drivers
+o0000000003564af8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c80c0_0 .net "B2", 0 0, o0000000003564af8; 0 drivers
+L_0000000003892ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c85c0_0 .net8 "VGND", 0 0, L_0000000003892ad0; 1 drivers, strength-aware
+L_0000000003892d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c7940_0 .net8 "VNB", 0 0, L_0000000003892d00; 1 drivers, strength-aware
+L_00000000038928a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9ec0_0 .net8 "VPB", 0 0, L_00000000038928a0; 1 drivers, strength-aware
+L_0000000003892980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9060_0 .net8 "VPWR", 0 0, L_0000000003892980; 1 drivers, strength-aware
+v00000000035c7d00_0 .net "Y", 0 0, L_000000000392e240; 1 drivers
+S_00000000034df2b0 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101730, 4 101575 1, S_0000000002833660;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392df30 .functor NAND 1, o0000000003564a68, o0000000003564a38, o0000000003564a98, C4<1>;
+L_000000000392efd0 .functor NAND 1, o0000000003564af8, o0000000003564ac8, C4<1>, C4<1>;
+L_000000000392e2b0 .functor AND 1, L_000000000392df30, L_000000000392efd0, C4<1>, C4<1>;
+L_000000000392e240 .functor BUF 1, L_000000000392e2b0, C4<0>, C4<0>, C4<0>;
+v00000000035c6540_0 .net "A1", 0 0, o0000000003564a38; alias, 0 drivers
+v00000000035c5e60_0 .net "A2", 0 0, o0000000003564a68; alias, 0 drivers
+v00000000035c5f00_0 .net "A3", 0 0, o0000000003564a98; alias, 0 drivers
+v00000000035c6040_0 .net "B1", 0 0, o0000000003564ac8; alias, 0 drivers
+v00000000035c64a0_0 .net "B2", 0 0, o0000000003564af8; alias, 0 drivers
+L_0000000003893320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c60e0_0 .net8 "VGND", 0 0, L_0000000003893320; 1 drivers, strength-aware
+L_0000000003893ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c6720_0 .net8 "VNB", 0 0, L_0000000003893ef0; 1 drivers, strength-aware
+L_0000000003893940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c6860_0 .net8 "VPB", 0 0, L_0000000003893940; 1 drivers, strength-aware
+L_00000000038929f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9600_0 .net8 "VPWR", 0 0, L_00000000038929f0; 1 drivers, strength-aware
+v00000000035ca0a0_0 .net "Y", 0 0, L_000000000392e240; alias, 1 drivers
+v00000000035c8a20_0 .net "and0_out_Y", 0 0, L_000000000392e2b0; 1 drivers
+v00000000035c83e0_0 .net "nand0_out", 0 0, L_000000000392df30; 1 drivers
+v00000000035c8340_0 .net "nand1_out", 0 0, L_000000000392efd0; 1 drivers
+S_0000000002833c60 .scope module, "sky130_fd_sc_hd__a32oi_2" "sky130_fd_sc_hd__a32oi_2" 4 101224;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003564fa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c87a0_0 .net "A1", 0 0, o0000000003564fa8; 0 drivers
+o0000000003564fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c7da0_0 .net "A2", 0 0, o0000000003564fd8; 0 drivers
+o0000000003565008 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8de0_0 .net "A3", 0 0, o0000000003565008; 0 drivers
+o0000000003565038 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c7ee0_0 .net "B1", 0 0, o0000000003565038; 0 drivers
+o0000000003565068 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8f20_0 .net "B2", 0 0, o0000000003565068; 0 drivers
+L_0000000003893390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c8160_0 .net8 "VGND", 0 0, L_0000000003893390; 1 drivers, strength-aware
+L_00000000038939b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c8840_0 .net8 "VNB", 0 0, L_00000000038939b0; 1 drivers, strength-aware
+L_0000000003892a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c88e0_0 .net8 "VPB", 0 0, L_0000000003892a60; 1 drivers, strength-aware
+L_0000000003893a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9100_0 .net8 "VPWR", 0 0, L_0000000003893a20; 1 drivers, strength-aware
+v00000000035c8ac0_0 .net "Y", 0 0, L_000000000392f190; 1 drivers
+S_00000000034dc5b0 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101246, 4 101575 1, S_0000000002833c60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392ecc0 .functor NAND 1, o0000000003564fd8, o0000000003564fa8, o0000000003565008, C4<1>;
+L_000000000392ef60 .functor NAND 1, o0000000003565068, o0000000003565038, C4<1>, C4<1>;
+L_000000000392f040 .functor AND 1, L_000000000392ecc0, L_000000000392ef60, C4<1>, C4<1>;
+L_000000000392f190 .functor BUF 1, L_000000000392f040, C4<0>, C4<0>, C4<0>;
+v00000000035c9ce0_0 .net "A1", 0 0, o0000000003564fa8; alias, 0 drivers
+v00000000035c8200_0 .net "A2", 0 0, o0000000003564fd8; alias, 0 drivers
+v00000000035c8660_0 .net "A3", 0 0, o0000000003565008; alias, 0 drivers
+v00000000035c8e80_0 .net "B1", 0 0, o0000000003565038; alias, 0 drivers
+v00000000035c8ca0_0 .net "B2", 0 0, o0000000003565068; alias, 0 drivers
+L_00000000038938d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c9d80_0 .net8 "VGND", 0 0, L_00000000038938d0; 1 drivers, strength-aware
+L_0000000003892b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c9c40_0 .net8 "VNB", 0 0, L_0000000003892b40; 1 drivers, strength-aware
+L_0000000003893400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9560_0 .net8 "VPB", 0 0, L_0000000003893400; 1 drivers, strength-aware
+L_0000000003893710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9740_0 .net8 "VPWR", 0 0, L_0000000003893710; 1 drivers, strength-aware
+v00000000035c8700_0 .net "Y", 0 0, L_000000000392f190; alias, 1 drivers
+v00000000035c8480_0 .net "and0_out_Y", 0 0, L_000000000392f040; 1 drivers
+v00000000035c94c0_0 .net "nand0_out", 0 0, L_000000000392ecc0; 1 drivers
+v00000000035c96a0_0 .net "nand1_out", 0 0, L_000000000392ef60; 1 drivers
+S_00000000028322e0 .scope module, "sky130_fd_sc_hd__a32oi_4" "sky130_fd_sc_hd__a32oi_4" 4 101097;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003565518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c9420_0 .net "A1", 0 0, o0000000003565518; 0 drivers
+o0000000003565548 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c97e0_0 .net "A2", 0 0, o0000000003565548; 0 drivers
+o0000000003565578 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c8d40_0 .net "A3", 0 0, o0000000003565578; 0 drivers
+o00000000035655a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c9880_0 .net "B1", 0 0, o00000000035655a8; 0 drivers
+o00000000035655d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035c9920_0 .net "B2", 0 0, o00000000035655d8; 0 drivers
+L_0000000003893630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c82a0_0 .net8 "VGND", 0 0, L_0000000003893630; 1 drivers, strength-aware
+L_0000000003892bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c99c0_0 .net8 "VNB", 0 0, L_0000000003892bb0; 1 drivers, strength-aware
+L_0000000003893780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9a60_0 .net8 "VPB", 0 0, L_0000000003893780; 1 drivers, strength-aware
+L_0000000003893f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c9b00_0 .net8 "VPWR", 0 0, L_0000000003893f60; 1 drivers, strength-aware
+v00000000035c9ba0_0 .net "Y", 0 0, L_000000000392e8d0; 1 drivers
+S_00000000034dc130 .scope module, "base" "sky130_fd_sc_hd__a32oi" 4 101119, 4 101575 1, S_00000000028322e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_000000000392e320 .functor NAND 1, o0000000003565548, o0000000003565518, o0000000003565578, C4<1>;
+L_000000000392f5f0 .functor NAND 1, o00000000035655d8, o00000000035655a8, C4<1>, C4<1>;
+L_000000000392f3c0 .functor AND 1, L_000000000392e320, L_000000000392f5f0, C4<1>, C4<1>;
+L_000000000392e8d0 .functor BUF 1, L_000000000392f3c0, C4<0>, C4<0>, C4<0>;
+v00000000035c79e0_0 .net "A1", 0 0, o0000000003565518; alias, 0 drivers
+v00000000035c7a80_0 .net "A2", 0 0, o0000000003565548; alias, 0 drivers
+v00000000035c8980_0 .net "A3", 0 0, o0000000003565578; alias, 0 drivers
+v00000000035c91a0_0 .net "B1", 0 0, o00000000035655a8; alias, 0 drivers
+v00000000035c8c00_0 .net "B2", 0 0, o00000000035655d8; alias, 0 drivers
+L_00000000038936a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c92e0_0 .net8 "VGND", 0 0, L_00000000038936a0; 1 drivers, strength-aware
+L_0000000003893e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035c7c60_0 .net8 "VNB", 0 0, L_0000000003893e80; 1 drivers, strength-aware
+L_0000000003894040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c7b20_0 .net8 "VPB", 0 0, L_0000000003894040; 1 drivers, strength-aware
+L_0000000003893c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035c8b60_0 .net8 "VPWR", 0 0, L_0000000003893c50; 1 drivers, strength-aware
+v00000000035c9380_0 .net "Y", 0 0, L_000000000392e8d0; alias, 1 drivers
+v00000000035c7e40_0 .net "and0_out_Y", 0 0, L_000000000392f3c0; 1 drivers
+v00000000035c9e20_0 .net "nand0_out", 0 0, L_000000000392e320; 1 drivers
+v00000000035c7f80_0 .net "nand1_out", 0 0, L_000000000392f5f0; 1 drivers
+S_0000000002833de0 .scope module, "sky130_fd_sc_hd__a41o_1" "sky130_fd_sc_hd__a41o_1" 4 17450;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003565a88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ca320_0 .net "A1", 0 0, o0000000003565a88; 0 drivers
+o0000000003565ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cc8a0_0 .net "A2", 0 0, o0000000003565ab8; 0 drivers
+o0000000003565ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cbf40_0 .net "A3", 0 0, o0000000003565ae8; 0 drivers
+o0000000003565b18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cbfe0_0 .net "A4", 0 0, o0000000003565b18; 0 drivers
+o0000000003565b48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cbcc0_0 .net "B1", 0 0, o0000000003565b48; 0 drivers
+L_0000000003893a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cc6c0_0 .net8 "VGND", 0 0, L_0000000003893a90; 1 drivers, strength-aware
+L_0000000003894270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cb7c0_0 .net8 "VNB", 0 0, L_0000000003894270; 1 drivers, strength-aware
+L_0000000003893fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ca460_0 .net8 "VPB", 0 0, L_0000000003893fd0; 1 drivers, strength-aware
+L_0000000003893b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cbea0_0 .net8 "VPWR", 0 0, L_0000000003893b00; 1 drivers, strength-aware
+v00000000035ca6e0_0 .net "X", 0 0, L_000000000392e080; 1 drivers
+S_00000000034e0630 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17472, 4 17068 1, S_0000000002833de0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392f890 .functor AND 1, o0000000003565a88, o0000000003565ab8, o0000000003565ae8, o0000000003565b18;
+L_000000000392f0b0 .functor OR 1, L_000000000392f890, o0000000003565b48, C4<0>, C4<0>;
+L_000000000392e080 .functor BUF 1, L_000000000392f0b0, C4<0>, C4<0>, C4<0>;
+v00000000035c9f60_0 .net "A1", 0 0, o0000000003565a88; alias, 0 drivers
+v00000000035c7bc0_0 .net "A2", 0 0, o0000000003565ab8; alias, 0 drivers
+v00000000035ca000_0 .net "A3", 0 0, o0000000003565ae8; alias, 0 drivers
+v00000000035cc4e0_0 .net "A4", 0 0, o0000000003565b18; alias, 0 drivers
+v00000000035ca780_0 .net "B1", 0 0, o0000000003565b48; alias, 0 drivers
+L_0000000003892c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cbe00_0 .net8 "VGND", 0 0, L_0000000003892c90; 1 drivers, strength-aware
+L_0000000003892de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cbc20_0 .net8 "VNB", 0 0, L_0000000003892de0; 1 drivers, strength-aware
+L_0000000003893be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cae60_0 .net8 "VPB", 0 0, L_0000000003893be0; 1 drivers, strength-aware
+L_00000000038940b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb040_0 .net8 "VPWR", 0 0, L_00000000038940b0; 1 drivers, strength-aware
+v00000000035cab40_0 .net "X", 0 0, L_000000000392e080; alias, 1 drivers
+v00000000035cc800_0 .net "and0_out", 0 0, L_000000000392f890; 1 drivers
+v00000000035ca640_0 .net "or0_out_X", 0 0, L_000000000392f0b0; 1 drivers
+S_0000000002832a60 .scope module, "sky130_fd_sc_hd__a41o_2" "sky130_fd_sc_hd__a41o_2" 4 17324;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003565fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cb180_0 .net "A1", 0 0, o0000000003565fc8; 0 drivers
+o0000000003565ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ca8c0_0 .net "A2", 0 0, o0000000003565ff8; 0 drivers
+o0000000003566028 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cc300_0 .net "A3", 0 0, o0000000003566028; 0 drivers
+o0000000003566058 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cb720_0 .net "A4", 0 0, o0000000003566058; 0 drivers
+o0000000003566088 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ca500_0 .net "B1", 0 0, o0000000003566088; 0 drivers
+L_0000000003893cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cb0e0_0 .net8 "VGND", 0 0, L_0000000003893cc0; 1 drivers, strength-aware
+L_0000000003893d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cafa0_0 .net8 "VNB", 0 0, L_0000000003893d30; 1 drivers, strength-aware
+L_0000000003893da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb9a0_0 .net8 "VPB", 0 0, L_0000000003893da0; 1 drivers, strength-aware
+L_0000000003894120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cac80_0 .net8 "VPWR", 0 0, L_0000000003894120; 1 drivers, strength-aware
+v00000000035cbb80_0 .net "X", 0 0, L_000000000392f820; 1 drivers
+S_00000000034dfd30 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17346, 4 17068 1, S_0000000002832a60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392f120 .functor AND 1, o0000000003565fc8, o0000000003565ff8, o0000000003566028, o0000000003566058;
+L_000000000392f7b0 .functor OR 1, L_000000000392f120, o0000000003566088, C4<0>, C4<0>;
+L_000000000392f820 .functor BUF 1, L_000000000392f7b0, C4<0>, C4<0>, C4<0>;
+v00000000035ca140_0 .net "A1", 0 0, o0000000003565fc8; alias, 0 drivers
+v00000000035caa00_0 .net "A2", 0 0, o0000000003565ff8; alias, 0 drivers
+v00000000035cadc0_0 .net "A3", 0 0, o0000000003566028; alias, 0 drivers
+v00000000035ca820_0 .net "A4", 0 0, o0000000003566058; alias, 0 drivers
+v00000000035cb900_0 .net "B1", 0 0, o0000000003566088; alias, 0 drivers
+L_00000000038942e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cbd60_0 .net8 "VGND", 0 0, L_00000000038942e0; 1 drivers, strength-aware
+L_00000000038959a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cc080_0 .net8 "VNB", 0 0, L_00000000038959a0; 1 drivers, strength-aware
+L_0000000003894510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb220_0 .net8 "VPB", 0 0, L_0000000003894510; 1 drivers, strength-aware
+L_0000000003894660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb2c0_0 .net8 "VPWR", 0 0, L_0000000003894660; 1 drivers, strength-aware
+v00000000035cc120_0 .net "X", 0 0, L_000000000392f820; alias, 1 drivers
+v00000000035cc1c0_0 .net "and0_out", 0 0, L_000000000392f120; 1 drivers
+v00000000035cc260_0 .net "or0_out_X", 0 0, L_000000000392f7b0; 1 drivers
+S_00000000028325e0 .scope module, "sky130_fd_sc_hd__a41o_4" "sky130_fd_sc_hd__a41o_4" 4 17198;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003566508 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cc760_0 .net "A1", 0 0, o0000000003566508; 0 drivers
+o0000000003566538 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cb4a0_0 .net "A2", 0 0, o0000000003566538; 0 drivers
+o0000000003566568 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cc580_0 .net "A3", 0 0, o0000000003566568; 0 drivers
+o0000000003566598 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ca280_0 .net "A4", 0 0, o0000000003566598; 0 drivers
+o00000000035665c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ca3c0_0 .net "B1", 0 0, o00000000035665c8; 0 drivers
+L_0000000003895f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cb540_0 .net8 "VGND", 0 0, L_0000000003895f50; 1 drivers, strength-aware
+L_0000000003895770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cb5e0_0 .net8 "VNB", 0 0, L_0000000003895770; 1 drivers, strength-aware
+L_0000000003895a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb680_0 .net8 "VPB", 0 0, L_0000000003895a10; 1 drivers, strength-aware
+L_0000000003894820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cb860_0 .net8 "VPWR", 0 0, L_0000000003894820; 1 drivers, strength-aware
+v00000000035cba40_0 .net "X", 0 0, L_000000000392e6a0; 1 drivers
+S_00000000034deb30 .scope module, "base" "sky130_fd_sc_hd__a41o" 4 17220, 4 17068 1, S_00000000028325e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392ee80 .functor AND 1, o0000000003566508, o0000000003566538, o0000000003566568, o0000000003566598;
+L_000000000392f660 .functor OR 1, L_000000000392ee80, o00000000035665c8, C4<0>, C4<0>;
+L_000000000392e6a0 .functor BUF 1, L_000000000392f660, C4<0>, C4<0>, C4<0>;
+v00000000035cc3a0_0 .net "A1", 0 0, o0000000003566508; alias, 0 drivers
+v00000000035ca960_0 .net "A2", 0 0, o0000000003566538; alias, 0 drivers
+v00000000035caaa0_0 .net "A3", 0 0, o0000000003566568; alias, 0 drivers
+v00000000035cc440_0 .net "A4", 0 0, o0000000003566598; alias, 0 drivers
+v00000000035cabe0_0 .net "B1", 0 0, o00000000035665c8; alias, 0 drivers
+L_00000000038953f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ca1e0_0 .net8 "VGND", 0 0, L_00000000038953f0; 1 drivers, strength-aware
+L_0000000003894c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cb360_0 .net8 "VNB", 0 0, L_0000000003894c80; 1 drivers, strength-aware
+L_0000000003894e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cc620_0 .net8 "VPB", 0 0, L_0000000003894e40; 1 drivers, strength-aware
+L_00000000038946d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cad20_0 .net8 "VPWR", 0 0, L_00000000038946d0; 1 drivers, strength-aware
+v00000000035caf00_0 .net "X", 0 0, L_000000000392e6a0; alias, 1 drivers
+v00000000035ca5a0_0 .net "and0_out", 0 0, L_000000000392ee80; 1 drivers
+v00000000035cb400_0 .net "or0_out_X", 0 0, L_000000000392f660; 1 drivers
+S_0000000002834bf0 .scope module, "sky130_fd_sc_hd__a41oi_1" "sky130_fd_sc_hd__a41oi_1" 4 31700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003566a48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ceec0_0 .net "A1", 0 0, o0000000003566a48; 0 drivers
+o0000000003566a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cd660_0 .net "A2", 0 0, o0000000003566a78; 0 drivers
+o0000000003566aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ce600_0 .net "A3", 0 0, o0000000003566aa8; 0 drivers
+o0000000003566ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ccf80_0 .net "A4", 0 0, o0000000003566ad8; 0 drivers
+o0000000003566b08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ce740_0 .net "B1", 0 0, o0000000003566b08; 0 drivers
+L_0000000003895700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cd160_0 .net8 "VGND", 0 0, L_0000000003895700; 1 drivers, strength-aware
+L_0000000003895af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cdf20_0 .net8 "VNB", 0 0, L_0000000003895af0; 1 drivers, strength-aware
+L_0000000003895fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ce880_0 .net8 "VPB", 0 0, L_0000000003895fc0; 1 drivers, strength-aware
+L_0000000003895690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ceba0_0 .net8 "VPWR", 0 0, L_0000000003895690; 1 drivers, strength-aware
+v00000000035cca80_0 .net "Y", 0 0, L_000000000392e0f0; 1 drivers
+S_00000000034e07b0 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31722, 4 32292 1, S_0000000002834bf0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392e010 .functor AND 1, o0000000003566a48, o0000000003566a78, o0000000003566aa8, o0000000003566ad8;
+L_000000000392e9b0 .functor NOR 1, o0000000003566b08, L_000000000392e010, C4<0>, C4<0>;
+L_000000000392e0f0 .functor BUF 1, L_000000000392e9b0, C4<0>, C4<0>, C4<0>;
+v00000000035cbae0_0 .net "A1", 0 0, o0000000003566a48; alias, 0 drivers
+v00000000035cf0a0_0 .net "A2", 0 0, o0000000003566a78; alias, 0 drivers
+v00000000035cd840_0 .net "A3", 0 0, o0000000003566aa8; alias, 0 drivers
+v00000000035cd340_0 .net "A4", 0 0, o0000000003566ad8; alias, 0 drivers
+v00000000035cf000_0 .net "B1", 0 0, o0000000003566b08; alias, 0 drivers
+L_0000000003894f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cdfc0_0 .net8 "VGND", 0 0, L_0000000003894f20; 1 drivers, strength-aware
+L_0000000003895540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ce1a0_0 .net8 "VNB", 0 0, L_0000000003895540; 1 drivers, strength-aware
+L_0000000003895620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cd520_0 .net8 "VPB", 0 0, L_0000000003895620; 1 drivers, strength-aware
+L_0000000003895150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ccee0_0 .net8 "VPWR", 0 0, L_0000000003895150; 1 drivers, strength-aware
+v00000000035cc940_0 .net "Y", 0 0, L_000000000392e0f0; alias, 1 drivers
+v00000000035cc9e0_0 .net "and0_out", 0 0, L_000000000392e010; 1 drivers
+v00000000035cd020_0 .net "nor0_out_Y", 0 0, L_000000000392e9b0; 1 drivers
+S_0000000002834d70 .scope module, "sky130_fd_sc_hd__a41oi_2" "sky130_fd_sc_hd__a41oi_2" 4 31952;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003566f88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cd980_0 .net "A1", 0 0, o0000000003566f88; 0 drivers
+o0000000003566fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ce240_0 .net "A2", 0 0, o0000000003566fb8; 0 drivers
+o0000000003566fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cd480_0 .net "A3", 0 0, o0000000003566fe8; 0 drivers
+o0000000003567018 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ce380_0 .net "A4", 0 0, o0000000003567018; 0 drivers
+o0000000003567048 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ccc60_0 .net "B1", 0 0, o0000000003567048; 0 drivers
+L_0000000003894b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cd700_0 .net8 "VGND", 0 0, L_0000000003894b30; 1 drivers, strength-aware
+L_0000000003894970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cd200_0 .net8 "VNB", 0 0, L_0000000003894970; 1 drivers, strength-aware
+L_00000000038957e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ce2e0_0 .net8 "VPB", 0 0, L_00000000038957e0; 1 drivers, strength-aware
+L_0000000003895cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ced80_0 .net8 "VPWR", 0 0, L_0000000003895cb0; 1 drivers, strength-aware
+v00000000035ceb00_0 .net "Y", 0 0, L_000000000392eef0; 1 drivers
+S_00000000034dc2b0 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31974, 4 32292 1, S_0000000002834d70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392f510 .functor AND 1, o0000000003566f88, o0000000003566fb8, o0000000003566fe8, o0000000003567018;
+L_000000000392f200 .functor NOR 1, o0000000003567048, L_000000000392f510, C4<0>, C4<0>;
+L_000000000392eef0 .functor BUF 1, L_000000000392f200, C4<0>, C4<0>, C4<0>;
+v00000000035ce560_0 .net "A1", 0 0, o0000000003566f88; alias, 0 drivers
+v00000000035cda20_0 .net "A2", 0 0, o0000000003566fb8; alias, 0 drivers
+v00000000035cdac0_0 .net "A3", 0 0, o0000000003566fe8; alias, 0 drivers
+v00000000035ce4c0_0 .net "A4", 0 0, o0000000003567018; alias, 0 drivers
+v00000000035ce6a0_0 .net "B1", 0 0, o0000000003567048; alias, 0 drivers
+L_00000000038952a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cdb60_0 .net8 "VGND", 0 0, L_00000000038952a0; 1 drivers, strength-aware
+L_0000000003895230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ce7e0_0 .net8 "VNB", 0 0, L_0000000003895230; 1 drivers, strength-aware
+L_0000000003894cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ce060_0 .net8 "VPB", 0 0, L_0000000003894cf0; 1 drivers, strength-aware
+L_0000000003894d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cd3e0_0 .net8 "VPWR", 0 0, L_0000000003894d60; 1 drivers, strength-aware
+v00000000035ccda0_0 .net "Y", 0 0, L_000000000392eef0; alias, 1 drivers
+v00000000035cd0c0_0 .net "and0_out", 0 0, L_000000000392f510; 1 drivers
+v00000000035cd8e0_0 .net "nor0_out_Y", 0 0, L_000000000392f200; 1 drivers
+S_00000000028345f0 .scope module, "sky130_fd_sc_hd__a41oi_4" "sky130_fd_sc_hd__a41oi_4" 4 31826;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o00000000035674c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ce100_0 .net "A1", 0 0, o00000000035674c8; 0 drivers
+o00000000035674f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ccbc0_0 .net "A2", 0 0, o00000000035674f8; 0 drivers
+o0000000003567528 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cee20_0 .net "A3", 0 0, o0000000003567528; 0 drivers
+o0000000003567558 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cdde0_0 .net "A4", 0 0, o0000000003567558; 0 drivers
+o0000000003567588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cea60_0 .net "B1", 0 0, o0000000003567588; 0 drivers
+L_0000000003895850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cde80_0 .net8 "VGND", 0 0, L_0000000003895850; 1 drivers, strength-aware
+L_0000000003895e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cec40_0 .net8 "VNB", 0 0, L_0000000003895e00; 1 drivers, strength-aware
+L_0000000003895d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cece0_0 .net8 "VPB", 0 0, L_0000000003895d90; 1 drivers, strength-aware
+L_0000000003896030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cef60_0 .net8 "VPWR", 0 0, L_0000000003896030; 1 drivers, strength-aware
+v00000000035d07c0_0 .net "Y", 0 0, L_000000000392dfa0; 1 drivers
+S_00000000034df430 .scope module, "base" "sky130_fd_sc_hd__a41oi" 4 31848, 4 32292 1, S_00000000028345f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_000000000392dd00 .functor AND 1, o00000000035674c8, o00000000035674f8, o0000000003567528, o0000000003567558;
+L_000000000392f270 .functor NOR 1, o0000000003567588, L_000000000392dd00, C4<0>, C4<0>;
+L_000000000392dfa0 .functor BUF 1, L_000000000392f270, C4<0>, C4<0>, C4<0>;
+v00000000035ccb20_0 .net "A1", 0 0, o00000000035674c8; alias, 0 drivers
+v00000000035ce420_0 .net "A2", 0 0, o00000000035674f8; alias, 0 drivers
+v00000000035cd5c0_0 .net "A3", 0 0, o0000000003567528; alias, 0 drivers
+v00000000035cd7a0_0 .net "A4", 0 0, o0000000003567558; alias, 0 drivers
+v00000000035ccd00_0 .net "B1", 0 0, o0000000003567588; alias, 0 drivers
+L_0000000003895460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ce920_0 .net8 "VGND", 0 0, L_0000000003895460; 1 drivers, strength-aware
+L_0000000003894dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cd2a0_0 .net8 "VNB", 0 0, L_0000000003894dd0; 1 drivers, strength-aware
+L_0000000003895a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ce9c0_0 .net8 "VPB", 0 0, L_0000000003895a80; 1 drivers, strength-aware
+L_00000000038949e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cdc00_0 .net8 "VPWR", 0 0, L_00000000038949e0; 1 drivers, strength-aware
+v00000000035cce40_0 .net "Y", 0 0, L_000000000392dfa0; alias, 1 drivers
+v00000000035cdca0_0 .net "and0_out", 0 0, L_000000000392dd00; 1 drivers
+v00000000035cdd40_0 .net "nor0_out_Y", 0 0, L_000000000392f270; 1 drivers
+S_0000000002835df0 .scope module, "sky130_fd_sc_hd__and2_0" "sky130_fd_sc_hd__and2_0" 4 52526;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003567a08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cfd20_0 .net "A", 0 0, o0000000003567a08; 0 drivers
+o0000000003567a38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d0860_0 .net "B", 0 0, o0000000003567a38; 0 drivers
+L_00000000038950e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d0ae0_0 .net8 "VGND", 0 0, L_00000000038950e0; 1 drivers, strength-aware
+L_00000000038944a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cf820_0 .net8 "VNB", 0 0, L_00000000038944a0; 1 drivers, strength-aware
+L_0000000003895070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cf960_0 .net8 "VPB", 0 0, L_0000000003895070; 1 drivers, strength-aware
+L_0000000003894a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cfdc0_0 .net8 "VPWR", 0 0, L_0000000003894a50; 1 drivers, strength-aware
+v00000000035cf140_0 .net "X", 0 0, L_000000000392f740; 1 drivers
+S_00000000034dc8b0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52542, 4 52415 1, S_0000000002835df0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392f6d0 .functor AND 1, o0000000003567a08, o0000000003567a38, C4<1>, C4<1>;
+L_000000000392f740 .functor BUF 1, L_000000000392f6d0, C4<0>, C4<0>, C4<0>;
+v00000000035cf8c0_0 .net "A", 0 0, o0000000003567a08; alias, 0 drivers
+v00000000035cf780_0 .net "B", 0 0, o0000000003567a38; alias, 0 drivers
+L_0000000003894580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d0e00_0 .net8 "VGND", 0 0, L_0000000003894580; 1 drivers, strength-aware
+L_0000000003894eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d18a0_0 .net8 "VNB", 0 0, L_0000000003894eb0; 1 drivers, strength-aware
+L_0000000003894ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0220_0 .net8 "VPB", 0 0, L_0000000003894ac0; 1 drivers, strength-aware
+L_00000000038945f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0a40_0 .net8 "VPWR", 0 0, L_00000000038945f0; 1 drivers, strength-aware
+v00000000035d0040_0 .net "X", 0 0, L_000000000392f740; alias, 1 drivers
+v00000000035d05e0_0 .net "and0_out_X", 0 0, L_000000000392f6d0; 1 drivers
+S_00000000028342f0 .scope module, "sky130_fd_sc_hd__and2_1" "sky130_fd_sc_hd__and2_1" 4 52632;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003567d68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d14e0_0 .net "A", 0 0, o0000000003567d68; 0 drivers
+o0000000003567d98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d00e0_0 .net "B", 0 0, o0000000003567d98; 0 drivers
+L_0000000003894f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d0f40_0 .net8 "VGND", 0 0, L_0000000003894f90; 1 drivers, strength-aware
+L_0000000003895000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cff00_0 .net8 "VNB", 0 0, L_0000000003895000; 1 drivers, strength-aware
+L_0000000003894ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cfc80_0 .net8 "VPB", 0 0, L_0000000003894ba0; 1 drivers, strength-aware
+L_0000000003894c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0b80_0 .net8 "VPWR", 0 0, L_0000000003894c10; 1 drivers, strength-aware
+v00000000035d0c20_0 .net "X", 0 0, L_000000000392e400; 1 drivers
+S_00000000034db9b0 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52648, 4 52415 1, S_00000000028342f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392dd70 .functor AND 1, o0000000003567d68, o0000000003567d98, C4<1>, C4<1>;
+L_000000000392e400 .functor BUF 1, L_000000000392dd70, C4<0>, C4<0>, C4<0>;
+v00000000035cf6e0_0 .net "A", 0 0, o0000000003567d68; alias, 0 drivers
+v00000000035d0680_0 .net "B", 0 0, o0000000003567d98; alias, 0 drivers
+L_00000000038951c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cf280_0 .net8 "VGND", 0 0, L_00000000038951c0; 1 drivers, strength-aware
+L_0000000003895310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1080_0 .net8 "VNB", 0 0, L_0000000003895310; 1 drivers, strength-aware
+L_0000000003895380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d13a0_0 .net8 "VPB", 0 0, L_0000000003895380; 1 drivers, strength-aware
+L_00000000038954d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1800_0 .net8 "VPWR", 0 0, L_00000000038954d0; 1 drivers, strength-aware
+v00000000035cfe60_0 .net "X", 0 0, L_000000000392e400; alias, 1 drivers
+v00000000035cfa00_0 .net "and0_out_X", 0 0, L_000000000392dd70; 1 drivers
+S_0000000002834770 .scope module, "sky130_fd_sc_hd__and2_2" "sky130_fd_sc_hd__and2_2" 4 52012;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o00000000035680c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035cf460_0 .net "A", 0 0, o00000000035680c8; 0 drivers
+o00000000035680f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d0180_0 .net "B", 0 0, o00000000035680f8; 0 drivers
+L_00000000038955b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d02c0_0 .net8 "VGND", 0 0, L_00000000038955b0; 1 drivers, strength-aware
+L_00000000038958c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1580_0 .net8 "VNB", 0 0, L_00000000038958c0; 1 drivers, strength-aware
+L_00000000038947b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0360_0 .net8 "VPB", 0 0, L_00000000038947b0; 1 drivers, strength-aware
+L_0000000003894740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0400_0 .net8 "VPWR", 0 0, L_0000000003894740; 1 drivers, strength-aware
+v00000000035d11c0_0 .net "X", 0 0, L_000000000392eb70; 1 drivers
+S_00000000034de530 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52028, 4 52415 1, S_0000000002834770;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392e7f0 .functor AND 1, o00000000035680c8, o00000000035680f8, C4<1>, C4<1>;
+L_000000000392eb70 .functor BUF 1, L_000000000392e7f0, C4<0>, C4<0>, C4<0>;
+v00000000035cf5a0_0 .net "A", 0 0, o00000000035680c8; alias, 0 drivers
+v00000000035d0720_0 .net "B", 0 0, o00000000035680f8; alias, 0 drivers
+L_0000000003895930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cfaa0_0 .net8 "VGND", 0 0, L_0000000003895930; 1 drivers, strength-aware
+L_0000000003895b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cffa0_0 .net8 "VNB", 0 0, L_0000000003895b60; 1 drivers, strength-aware
+L_0000000003894890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cfb40_0 .net8 "VPB", 0 0, L_0000000003894890; 1 drivers, strength-aware
+L_0000000003895bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cfbe0_0 .net8 "VPWR", 0 0, L_0000000003895bd0; 1 drivers, strength-aware
+v00000000035d0cc0_0 .net "X", 0 0, L_000000000392eb70; alias, 1 drivers
+v00000000035d0fe0_0 .net "and0_out_X", 0 0, L_000000000392e7f0; 1 drivers
+S_0000000002834470 .scope module, "sky130_fd_sc_hd__and2_4" "sky130_fd_sc_hd__and2_4" 4 52118;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003568428 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d1260_0 .net "A", 0 0, o0000000003568428; 0 drivers
+o0000000003568458 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d16c0_0 .net "B", 0 0, o0000000003568458; 0 drivers
+L_0000000003895c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1300_0 .net8 "VGND", 0 0, L_0000000003895c40; 1 drivers, strength-aware
+L_0000000003895d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1440_0 .net8 "VNB", 0 0, L_0000000003895d20; 1 drivers, strength-aware
+L_0000000003894900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1760_0 .net8 "VPB", 0 0, L_0000000003894900; 1 drivers, strength-aware
+L_0000000003895e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035cf1e0_0 .net8 "VPWR", 0 0, L_0000000003895e70; 1 drivers, strength-aware
+v00000000035cf320_0 .net "X", 0 0, L_000000000392ed30; 1 drivers
+S_00000000034dd030 .scope module, "base" "sky130_fd_sc_hd__and2" 4 52134, 4 52415 1, S_0000000002834470;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392e710 .functor AND 1, o0000000003568428, o0000000003568458, C4<1>, C4<1>;
+L_000000000392ed30 .functor BUF 1, L_000000000392e710, C4<0>, C4<0>, C4<0>;
+v00000000035d04a0_0 .net "A", 0 0, o0000000003568428; alias, 0 drivers
+v00000000035d1620_0 .net "B", 0 0, o0000000003568458; alias, 0 drivers
+L_0000000003895ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d0540_0 .net8 "VGND", 0 0, L_0000000003895ee0; 1 drivers, strength-aware
+L_0000000003896730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1120_0 .net8 "VNB", 0 0, L_0000000003896730; 1 drivers, strength-aware
+L_0000000003897610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0d60_0 .net8 "VPB", 0 0, L_0000000003897610; 1 drivers, strength-aware
+L_0000000003896b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d0900_0 .net8 "VPWR", 0 0, L_0000000003896b90; 1 drivers, strength-aware
+v00000000035d0ea0_0 .net "X", 0 0, L_000000000392ed30; alias, 1 drivers
+v00000000035d09a0_0 .net "and0_out_X", 0 0, L_000000000392e710; 1 drivers
+S_0000000002834ef0 .scope module, "sky130_fd_sc_hd__and2b_1" "sky130_fd_sc_hd__and2b_1" 4 34775;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o0000000003568788 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d39c0_0 .net "A_N", 0 0, o0000000003568788; 0 drivers
+o00000000035687b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d3a60_0 .net "B", 0 0, o00000000035687b8; 0 drivers
+L_00000000038971b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d3420_0 .net8 "VGND", 0 0, L_00000000038971b0; 1 drivers, strength-aware
+L_0000000003896ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d2d40_0 .net8 "VNB", 0 0, L_0000000003896ab0; 1 drivers, strength-aware
+L_0000000003896ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d2e80_0 .net8 "VPB", 0 0, L_0000000003896ce0; 1 drivers, strength-aware
+L_00000000038965e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1d00_0 .net8 "VPWR", 0 0, L_00000000038965e0; 1 drivers, strength-aware
+v00000000035d2160_0 .net "X", 0 0, L_000000000392f350; 1 drivers
+S_00000000034de9b0 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34791, 4 34662 1, S_0000000002834ef0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392dde0 .functor NOT 1, o0000000003568788, C4<0>, C4<0>, C4<0>;
+L_000000000392f2e0 .functor AND 1, L_000000000392dde0, o00000000035687b8, C4<1>, C4<1>;
+L_000000000392f350 .functor BUF 1, L_000000000392f2e0, C4<0>, C4<0>, C4<0>;
+v00000000035cf3c0_0 .net "A_N", 0 0, o0000000003568788; alias, 0 drivers
+v00000000035cf500_0 .net "B", 0 0, o00000000035687b8; alias, 0 drivers
+L_0000000003896490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035cf640_0 .net8 "VGND", 0 0, L_0000000003896490; 1 drivers, strength-aware
+L_0000000003897060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d31a0_0 .net8 "VNB", 0 0, L_0000000003897060; 1 drivers, strength-aware
+L_0000000003897370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d4000_0 .net8 "VPB", 0 0, L_0000000003897370; 1 drivers, strength-aware
+L_00000000038967a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d3f60_0 .net8 "VPWR", 0 0, L_00000000038967a0; 1 drivers, strength-aware
+v00000000035d2340_0 .net "X", 0 0, L_000000000392f350; alias, 1 drivers
+v00000000035d2de0_0 .net "and0_out_X", 0 0, L_000000000392f2e0; 1 drivers
+v00000000035d22a0_0 .net "not0_out", 0 0, L_000000000392dde0; 1 drivers
+S_0000000002835670 .scope module, "sky130_fd_sc_hd__and2b_2" "sky130_fd_sc_hd__and2b_2" 4 34253;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o0000000003568b18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d3c40_0 .net "A_N", 0 0, o0000000003568b18; 0 drivers
+o0000000003568b48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d34c0_0 .net "B", 0 0, o0000000003568b48; 0 drivers
+L_0000000003897c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d2fc0_0 .net8 "VGND", 0 0, L_0000000003897c30; 1 drivers, strength-aware
+L_0000000003896810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d3ce0_0 .net8 "VNB", 0 0, L_0000000003896810; 1 drivers, strength-aware
+L_0000000003896c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1da0_0 .net8 "VPB", 0 0, L_0000000003896c00; 1 drivers, strength-aware
+L_0000000003896e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d23e0_0 .net8 "VPWR", 0 0, L_0000000003896e30; 1 drivers, strength-aware
+v00000000035d3600_0 .net "X", 0 0, L_000000000392e1d0; 1 drivers
+S_00000000034ddab0 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34269, 4 34662 1, S_0000000002835670;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392e470 .functor NOT 1, o0000000003568b18, C4<0>, C4<0>, C4<0>;
+L_000000000392e780 .functor AND 1, L_000000000392e470, o0000000003568b48, C4<1>, C4<1>;
+L_000000000392e1d0 .functor BUF 1, L_000000000392e780, C4<0>, C4<0>, C4<0>;
+v00000000035d3b00_0 .net "A_N", 0 0, o0000000003568b18; alias, 0 drivers
+v00000000035d3ba0_0 .net "B", 0 0, o0000000003568b48; alias, 0 drivers
+L_0000000003897990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d3240_0 .net8 "VGND", 0 0, L_0000000003897990; 1 drivers, strength-aware
+L_0000000003896570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1c60_0 .net8 "VNB", 0 0, L_0000000003896570; 1 drivers, strength-aware
+L_00000000038963b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d40a0_0 .net8 "VPB", 0 0, L_00000000038963b0; 1 drivers, strength-aware
+L_0000000003896c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d2ac0_0 .net8 "VPWR", 0 0, L_0000000003896c70; 1 drivers, strength-aware
+v00000000035d2f20_0 .net "X", 0 0, L_000000000392e1d0; alias, 1 drivers
+v00000000035d20c0_0 .net "and0_out_X", 0 0, L_000000000392e780; 1 drivers
+v00000000035d2b60_0 .net "not0_out", 0 0, L_000000000392e470; 1 drivers
+S_0000000002835f70 .scope module, "sky130_fd_sc_hd__and2b_4" "sky130_fd_sc_hd__and2b_4" 4 34359;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o0000000003568ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d2700_0 .net "A_N", 0 0, o0000000003568ea8; 0 drivers
+o0000000003568ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d2480_0 .net "B", 0 0, o0000000003568ed8; 0 drivers
+L_0000000003896d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d2520_0 .net8 "VGND", 0 0, L_0000000003896d50; 1 drivers, strength-aware
+L_0000000003896ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d25c0_0 .net8 "VNB", 0 0, L_0000000003896ea0; 1 drivers, strength-aware
+L_0000000003896880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d3060_0 .net8 "VPB", 0 0, L_0000000003896880; 1 drivers, strength-aware
+L_0000000003896f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1ee0_0 .net8 "VPWR", 0 0, L_0000000003896f10; 1 drivers, strength-aware
+v00000000035d36a0_0 .net "X", 0 0, L_000000000392f4a0; 1 drivers
+S_00000000034db530 .scope module, "base" "sky130_fd_sc_hd__and2b" 4 34375, 4 34662 1, S_0000000002835f70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000392f430 .functor NOT 1, o0000000003568ea8, C4<0>, C4<0>, C4<0>;
+L_000000000392e860 .functor AND 1, L_000000000392f430, o0000000003568ed8, C4<1>, C4<1>;
+L_000000000392f4a0 .functor BUF 1, L_000000000392e860, C4<0>, C4<0>, C4<0>;
+v00000000035d2200_0 .net "A_N", 0 0, o0000000003568ea8; alias, 0 drivers
+v00000000035d3560_0 .net "B", 0 0, o0000000003568ed8; alias, 0 drivers
+L_00000000038970d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d2a20_0 .net8 "VGND", 0 0, L_00000000038970d0; 1 drivers, strength-aware
+L_0000000003896260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d32e0_0 .net8 "VNB", 0 0, L_0000000003896260; 1 drivers, strength-aware
+L_00000000038968f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d2840_0 .net8 "VPB", 0 0, L_00000000038968f0; 1 drivers, strength-aware
+L_00000000038960a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1e40_0 .net8 "VPWR", 0 0, L_00000000038960a0; 1 drivers, strength-aware
+v00000000035d2c00_0 .net "X", 0 0, L_000000000392f4a0; alias, 1 drivers
+v00000000035d1940_0 .net "and0_out_X", 0 0, L_000000000392e860; 1 drivers
+v00000000035d2ca0_0 .net "not0_out", 0 0, L_000000000392f430; 1 drivers
+S_00000000028357f0 .scope module, "sky130_fd_sc_hd__and3_1" "sky130_fd_sc_hd__and3_1" 4 9901;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003569238 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d3380_0 .net "A", 0 0, o0000000003569238; 0 drivers
+o0000000003569268 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d37e0_0 .net "B", 0 0, o0000000003569268; 0 drivers
+o0000000003569298 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d3880_0 .net "C", 0 0, o0000000003569298; 0 drivers
+L_00000000038973e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d3920_0 .net8 "VGND", 0 0, L_00000000038973e0; 1 drivers, strength-aware
+L_0000000003896420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d1f80_0 .net8 "VNB", 0 0, L_0000000003896420; 1 drivers, strength-aware
+L_00000000038962d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d2980_0 .net8 "VPB", 0 0, L_00000000038962d0; 1 drivers, strength-aware
+L_0000000003897220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1b20_0 .net8 "VPWR", 0 0, L_0000000003897220; 1 drivers, strength-aware
+v00000000035d2020_0 .net "X", 0 0, L_000000000392eda0; 1 drivers
+S_00000000034de3b0 .scope module, "base" "sky130_fd_sc_hd__and3" 4 9919, 4 10319 1, S_00000000028357f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000392e160 .functor AND 1, o0000000003569298, o0000000003569238, o0000000003569268, C4<1>;
+L_000000000392eda0 .functor BUF 1, L_000000000392e160, C4<0>, C4<0>, C4<0>;
+v00000000035d19e0_0 .net "A", 0 0, o0000000003569238; alias, 0 drivers
+v00000000035d3d80_0 .net "B", 0 0, o0000000003569268; alias, 0 drivers
+v00000000035d1a80_0 .net "C", 0 0, o0000000003569298; alias, 0 drivers
+L_0000000003897450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d2660_0 .net8 "VGND", 0 0, L_0000000003897450; 1 drivers, strength-aware
+L_0000000003896650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d3100_0 .net8 "VNB", 0 0, L_0000000003896650; 1 drivers, strength-aware
+L_00000000038977d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d1bc0_0 .net8 "VPB", 0 0, L_00000000038977d0; 1 drivers, strength-aware
+L_0000000003896110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d3e20_0 .net8 "VPWR", 0 0, L_0000000003896110; 1 drivers, strength-aware
+v00000000035d3ec0_0 .net "X", 0 0, L_000000000392eda0; alias, 1 drivers
+v00000000035d3740_0 .net "and0_out_X", 0 0, L_000000000392e160; 1 drivers
+S_00000000028348f0 .scope module, "sky130_fd_sc_hd__and3_4" "sky130_fd_sc_hd__and3_4" 4 9789;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003569628 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d6800_0 .net "A", 0 0, o0000000003569628; 0 drivers
+o0000000003569658 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d4dc0_0 .net "B", 0 0, o0000000003569658; 0 drivers
+o0000000003569688 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d45a0_0 .net "C", 0 0, o0000000003569688; 0 drivers
+L_0000000003897a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5040_0 .net8 "VGND", 0 0, L_0000000003897a00; 1 drivers, strength-aware
+L_0000000003896dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d6620_0 .net8 "VNB", 0 0, L_0000000003896dc0; 1 drivers, strength-aware
+L_0000000003897140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d54a0_0 .net8 "VPB", 0 0, L_0000000003897140; 1 drivers, strength-aware
+L_0000000003897920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d4c80_0 .net8 "VPWR", 0 0, L_0000000003897920; 1 drivers, strength-aware
+v00000000035d46e0_0 .net "X", 0 0, L_000000000392e4e0; 1 drivers
+S_00000000034dbb30 .scope module, "base" "sky130_fd_sc_hd__and3" 4 9807, 4 10319 1, S_00000000028348f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000392f580 .functor AND 1, o0000000003569688, o0000000003569628, o0000000003569658, C4<1>;
+L_000000000392e4e0 .functor BUF 1, L_000000000392f580, C4<0>, C4<0>, C4<0>;
+v00000000035d27a0_0 .net "A", 0 0, o0000000003569628; alias, 0 drivers
+v00000000035d28e0_0 .net "B", 0 0, o0000000003569658; alias, 0 drivers
+v00000000035d4640_0 .net "C", 0 0, o0000000003569688; alias, 0 drivers
+L_0000000003897290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d4460_0 .net8 "VGND", 0 0, L_0000000003897290; 1 drivers, strength-aware
+L_0000000003897a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d4500_0 .net8 "VNB", 0 0, L_0000000003897a70; 1 drivers, strength-aware
+L_0000000003896500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d4780_0 .net8 "VPB", 0 0, L_0000000003896500; 1 drivers, strength-aware
+L_0000000003897ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d59a0_0 .net8 "VPWR", 0 0, L_0000000003897ae0; 1 drivers, strength-aware
+v00000000035d6580_0 .net "X", 0 0, L_000000000392e4e0; alias, 1 drivers
+v00000000035d4d20_0 .net "and0_out_X", 0 0, L_000000000392f580; 1 drivers
+S_0000000002835c70 .scope module, "sky130_fd_sc_hd__and3b_1" "sky130_fd_sc_hd__and3b_1" 4 40615;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003569a18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d41e0_0 .net "A_N", 0 0, o0000000003569a18; 0 drivers
+o0000000003569a48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d55e0_0 .net "B", 0 0, o0000000003569a48; 0 drivers
+o0000000003569a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d4a00_0 .net "C", 0 0, o0000000003569a78; 0 drivers
+L_0000000003896180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5540_0 .net8 "VGND", 0 0, L_0000000003896180; 1 drivers, strength-aware
+L_0000000003896340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d4aa0_0 .net8 "VNB", 0 0, L_0000000003896340; 1 drivers, strength-aware
+L_0000000003896960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d6440_0 .net8 "VPB", 0 0, L_0000000003896960; 1 drivers, strength-aware
+L_00000000038969d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d5d60_0 .net8 "VPWR", 0 0, L_00000000038969d0; 1 drivers, strength-aware
+v00000000035d5f40_0 .net "X", 0 0, L_000000000392ebe0; 1 drivers
+S_00000000034df5b0 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40633, 4 40385 1, S_0000000002835c70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000392de50 .functor NOT 1, o0000000003569a18, C4<0>, C4<0>, C4<0>;
+L_000000000392dec0 .functor AND 1, o0000000003569a78, L_000000000392de50, o0000000003569a48, C4<1>;
+L_000000000392ebe0 .functor BUF 1, L_000000000392dec0, C4<0>, C4<0>, C4<0>;
+v00000000035d4820_0 .net "A_N", 0 0, o0000000003569a18; alias, 0 drivers
+v00000000035d5ae0_0 .net "B", 0 0, o0000000003569a48; alias, 0 drivers
+v00000000035d4fa0_0 .net "C", 0 0, o0000000003569a78; alias, 0 drivers
+L_00000000038974c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5400_0 .net8 "VGND", 0 0, L_00000000038974c0; 1 drivers, strength-aware
+L_0000000003897300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5b80_0 .net8 "VNB", 0 0, L_0000000003897300; 1 drivers, strength-aware
+L_0000000003897530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d48c0_0 .net8 "VPB", 0 0, L_0000000003897530; 1 drivers, strength-aware
+L_0000000003896f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d4140_0 .net8 "VPWR", 0 0, L_0000000003896f80; 1 drivers, strength-aware
+v00000000035d5220_0 .net "X", 0 0, L_000000000392ebe0; alias, 1 drivers
+v00000000035d4e60_0 .net "and0_out_X", 0 0, L_000000000392dec0; 1 drivers
+v00000000035d4960_0 .net "not0_out", 0 0, L_000000000392de50; 1 drivers
+S_00000000028360f0 .scope module, "sky130_fd_sc_hd__and3b_2" "sky130_fd_sc_hd__and3b_2" 4 40073;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003569e38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d57c0_0 .net "A_N", 0 0, o0000000003569e38; 0 drivers
+o0000000003569e68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d5860_0 .net "B", 0 0, o0000000003569e68; 0 drivers
+o0000000003569e98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d5900_0 .net "C", 0 0, o0000000003569e98; 0 drivers
+L_0000000003896a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5a40_0 .net8 "VGND", 0 0, L_0000000003896a40; 1 drivers, strength-aware
+L_00000000038966c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d5c20_0 .net8 "VNB", 0 0, L_00000000038966c0; 1 drivers, strength-aware
+L_0000000003896b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d5cc0_0 .net8 "VPB", 0 0, L_0000000003896b20; 1 drivers, strength-aware
+L_00000000038976f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d4280_0 .net8 "VPWR", 0 0, L_00000000038976f0; 1 drivers, strength-aware
+v00000000035d5ea0_0 .net "X", 0 0, L_000000000392eb00; 1 drivers
+S_00000000034df730 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40091, 4 40385 1, S_00000000028360f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000392ee10 .functor NOT 1, o0000000003569e38, C4<0>, C4<0>, C4<0>;
+L_000000000392e550 .functor AND 1, o0000000003569e98, L_000000000392ee10, o0000000003569e68, C4<1>;
+L_000000000392eb00 .functor BUF 1, L_000000000392e550, C4<0>, C4<0>, C4<0>;
+v00000000035d52c0_0 .net "A_N", 0 0, o0000000003569e38; alias, 0 drivers
+v00000000035d5680_0 .net "B", 0 0, o0000000003569e68; alias, 0 drivers
+v00000000035d4b40_0 .net "C", 0 0, o0000000003569e98; alias, 0 drivers
+L_0000000003896ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d4be0_0 .net8 "VGND", 0 0, L_0000000003896ff0; 1 drivers, strength-aware
+L_00000000038975a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d4f00_0 .net8 "VNB", 0 0, L_00000000038975a0; 1 drivers, strength-aware
+L_0000000003897680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d5e00_0 .net8 "VPB", 0 0, L_0000000003897680; 1 drivers, strength-aware
+L_0000000003897760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d50e0_0 .net8 "VPWR", 0 0, L_0000000003897760; 1 drivers, strength-aware
+v00000000035d5180_0 .net "X", 0 0, L_000000000392eb00; alias, 1 drivers
+v00000000035d5360_0 .net "and0_out_X", 0 0, L_000000000392e550; 1 drivers
+v00000000035d5720_0 .net "not0_out", 0 0, L_000000000392ee10; 1 drivers
+S_0000000002835af0 .scope module, "sky130_fd_sc_hd__and3b_4" "sky130_fd_sc_hd__and3b_4" 4 40503;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000356a258 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d6760_0 .net "A_N", 0 0, o000000000356a258; 0 drivers
+o000000000356a288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d68a0_0 .net "B", 0 0, o000000000356a288; 0 drivers
+o000000000356a2b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d43c0_0 .net "C", 0 0, o000000000356a2b8; 0 drivers
+L_0000000003897840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d8c40_0 .net8 "VGND", 0 0, L_0000000003897840; 1 drivers, strength-aware
+L_00000000038978b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d8d80_0 .net8 "VNB", 0 0, L_00000000038978b0; 1 drivers, strength-aware
+L_0000000003897b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d69e0_0 .net8 "VPB", 0 0, L_0000000003897b50; 1 drivers, strength-aware
+L_0000000003897bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8100_0 .net8 "VPWR", 0 0, L_0000000003897bc0; 1 drivers, strength-aware
+v00000000035d72a0_0 .net "X", 0 0, L_000000000392ea20; 1 drivers
+S_00000000034dd330 .scope module, "base" "sky130_fd_sc_hd__and3b" 4 40521, 4 40385 1, S_0000000002835af0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000392e940 .functor NOT 1, o000000000356a258, C4<0>, C4<0>, C4<0>;
+L_000000000392e5c0 .functor AND 1, o000000000356a2b8, L_000000000392e940, o000000000356a288, C4<1>;
+L_000000000392ea20 .functor BUF 1, L_000000000392e5c0, C4<0>, C4<0>, C4<0>;
+v00000000035d5fe0_0 .net "A_N", 0 0, o000000000356a258; alias, 0 drivers
+v00000000035d66c0_0 .net "B", 0 0, o000000000356a288; alias, 0 drivers
+v00000000035d6080_0 .net "C", 0 0, o000000000356a2b8; alias, 0 drivers
+L_00000000038961f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d6120_0 .net8 "VGND", 0 0, L_00000000038961f0; 1 drivers, strength-aware
+L_0000000003897ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d61c0_0 .net8 "VNB", 0 0, L_0000000003897ca0; 1 drivers, strength-aware
+L_0000000003897d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d6260_0 .net8 "VPB", 0 0, L_0000000003897d80; 1 drivers, strength-aware
+L_0000000003897df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d6300_0 .net8 "VPWR", 0 0, L_0000000003897df0; 1 drivers, strength-aware
+v00000000035d63a0_0 .net "X", 0 0, L_000000000392ea20; alias, 1 drivers
+v00000000035d64e0_0 .net "and0_out_X", 0 0, L_000000000392e5c0; 1 drivers
+v00000000035d4320_0 .net "not0_out", 0 0, L_000000000392e940; 1 drivers
+S_0000000002835070 .scope module, "sky130_fd_sc_hd__and4_1" "sky130_fd_sc_hd__and4_1" 4 83588;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356a678 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d82e0_0 .net "A", 0 0, o000000000356a678; 0 drivers
+o000000000356a6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d7200_0 .net "B", 0 0, o000000000356a6a8; 0 drivers
+o000000000356a6d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d86a0_0 .net "C", 0 0, o000000000356a6d8; 0 drivers
+o000000000356a708 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d7980_0 .net "D", 0 0, o000000000356a708; 0 drivers
+L_0000000003897d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d6bc0_0 .net8 "VGND", 0 0, L_0000000003897d10; 1 drivers, strength-aware
+L_0000000003897ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d78e0_0 .net8 "VNB", 0 0, L_0000000003897ed0; 1 drivers, strength-aware
+L_0000000003897e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d7020_0 .net8 "VPB", 0 0, L_0000000003897e60; 1 drivers, strength-aware
+L_0000000003897f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8740_0 .net8 "VPWR", 0 0, L_0000000003897f40; 1 drivers, strength-aware
+v00000000035d8420_0 .net "X", 0 0, L_000000000392ec50; 1 drivers
+S_00000000034e01b0 .scope module, "base" "sky130_fd_sc_hd__and4" 4 83608, 4 83903 1, S_0000000002835070;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392ea90 .functor AND 1, o000000000356a678, o000000000356a6a8, o000000000356a6d8, o000000000356a708;
+L_000000000392ec50 .functor BUF 1, L_000000000392ea90, C4<0>, C4<0>, C4<0>;
+v00000000035d81a0_0 .net "A", 0 0, o000000000356a678; alias, 0 drivers
+v00000000035d6c60_0 .net "B", 0 0, o000000000356a6a8; alias, 0 drivers
+v00000000035d7160_0 .net "C", 0 0, o000000000356a6d8; alias, 0 drivers
+v00000000035d7de0_0 .net "D", 0 0, o000000000356a708; alias, 0 drivers
+L_0000000003888180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d7340_0 .net8 "VGND", 0 0, L_0000000003888180; 1 drivers, strength-aware
+L_0000000003888f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d7ac0_0 .net8 "VNB", 0 0, L_0000000003888f10; 1 drivers, strength-aware
+L_0000000003888260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d7c00_0 .net8 "VPB", 0 0, L_0000000003888260; 1 drivers, strength-aware
+L_00000000038896f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d89c0_0 .net8 "VPWR", 0 0, L_00000000038896f0; 1 drivers, strength-aware
+v00000000035d8240_0 .net "X", 0 0, L_000000000392ec50; alias, 1 drivers
+v00000000035d8600_0 .net "and0_out_X", 0 0, L_000000000392ea90; 1 drivers
+S_00000000028351f0 .scope module, "sky130_fd_sc_hd__and4_2" "sky130_fd_sc_hd__and4_2" 4 83470;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356aaf8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d87e0_0 .net "A", 0 0, o000000000356aaf8; 0 drivers
+o000000000356ab28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d73e0_0 .net "B", 0 0, o000000000356ab28; 0 drivers
+o000000000356ab58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d6a80_0 .net "C", 0 0, o000000000356ab58; 0 drivers
+o000000000356ab88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d8ba0_0 .net "D", 0 0, o000000000356ab88; 0 drivers
+L_00000000038891b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d7480_0 .net8 "VGND", 0 0, L_00000000038891b0; 1 drivers, strength-aware
+L_0000000003889bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d8ce0_0 .net8 "VNB", 0 0, L_0000000003889bc0; 1 drivers, strength-aware
+L_0000000003889530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d6f80_0 .net8 "VPB", 0 0, L_0000000003889530; 1 drivers, strength-aware
+L_0000000003889220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d75c0_0 .net8 "VPWR", 0 0, L_0000000003889220; 1 drivers, strength-aware
+v00000000035d8e20_0 .net "X", 0 0, L_000000000392feb0; 1 drivers
+S_00000000034db3b0 .scope module, "base" "sky130_fd_sc_hd__and4" 4 83490, 4 83903 1, S_00000000028351f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392fd60 .functor AND 1, o000000000356aaf8, o000000000356ab28, o000000000356ab58, o000000000356ab88;
+L_000000000392feb0 .functor BUF 1, L_000000000392fd60, C4<0>, C4<0>, C4<0>;
+v00000000035d8380_0 .net "A", 0 0, o000000000356aaf8; alias, 0 drivers
+v00000000035d7ca0_0 .net "B", 0 0, o000000000356ab28; alias, 0 drivers
+v00000000035d6b20_0 .net "C", 0 0, o000000000356ab58; alias, 0 drivers
+v00000000035d9000_0 .net "D", 0 0, o000000000356ab88; alias, 0 drivers
+L_0000000003888a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d70c0_0 .net8 "VGND", 0 0, L_0000000003888a40; 1 drivers, strength-aware
+L_0000000003889760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d90a0_0 .net8 "VNB", 0 0, L_0000000003889760; 1 drivers, strength-aware
+L_00000000038894c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d7520_0 .net8 "VPB", 0 0, L_00000000038894c0; 1 drivers, strength-aware
+L_0000000003888b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d6940_0 .net8 "VPWR", 0 0, L_0000000003888b20; 1 drivers, strength-aware
+v00000000035d8ec0_0 .net "X", 0 0, L_000000000392feb0; alias, 1 drivers
+v00000000035d7660_0 .net "and0_out_X", 0 0, L_000000000392fd60; 1 drivers
+S_0000000002834a70 .scope module, "sky130_fd_sc_hd__and4_4" "sky130_fd_sc_hd__and4_4" 4 84024;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356af78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d7d40_0 .net "A", 0 0, o000000000356af78; 0 drivers
+o000000000356afa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d6d00_0 .net "B", 0 0, o000000000356afa8; 0 drivers
+o000000000356afd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d7f20_0 .net "C", 0 0, o000000000356afd8; 0 drivers
+o000000000356b008 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d8f60_0 .net "D", 0 0, o000000000356b008; 0 drivers
+L_0000000003888730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d6da0_0 .net8 "VGND", 0 0, L_0000000003888730; 1 drivers, strength-aware
+L_0000000003889610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d7e80_0 .net8 "VNB", 0 0, L_0000000003889610; 1 drivers, strength-aware
+L_0000000003888810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8920_0 .net8 "VPB", 0 0, L_0000000003888810; 1 drivers, strength-aware
+L_0000000003888110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8a60_0 .net8 "VPWR", 0 0, L_0000000003888110; 1 drivers, strength-aware
+v00000000035d8b00_0 .net "X", 0 0, L_000000000392fe40; 1 drivers
+S_00000000034dddb0 .scope module, "base" "sky130_fd_sc_hd__and4" 4 84044, 4 83903 1, S_0000000002834a70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392fac0 .functor AND 1, o000000000356af78, o000000000356afa8, o000000000356afd8, o000000000356b008;
+L_000000000392fe40 .functor BUF 1, L_000000000392fac0, C4<0>, C4<0>, C4<0>;
+v00000000035d7b60_0 .net "A", 0 0, o000000000356af78; alias, 0 drivers
+v00000000035d7700_0 .net "B", 0 0, o000000000356afa8; alias, 0 drivers
+v00000000035d7fc0_0 .net "C", 0 0, o000000000356afd8; alias, 0 drivers
+v00000000035d84c0_0 .net "D", 0 0, o000000000356b008; alias, 0 drivers
+L_0000000003889140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d77a0_0 .net8 "VGND", 0 0, L_0000000003889140; 1 drivers, strength-aware
+L_0000000003888880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d7840_0 .net8 "VNB", 0 0, L_0000000003888880; 1 drivers, strength-aware
+L_0000000003889370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8880_0 .net8 "VPB", 0 0, L_0000000003889370; 1 drivers, strength-aware
+L_0000000003889a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d8560_0 .net8 "VPWR", 0 0, L_0000000003889a00; 1 drivers, strength-aware
+v00000000035d7a20_0 .net "X", 0 0, L_000000000392fe40; alias, 1 drivers
+v00000000035d8060_0 .net "and0_out_X", 0 0, L_000000000392fac0; 1 drivers
+S_0000000002835370 .scope module, "sky130_fd_sc_hd__and4b_1" "sky130_fd_sc_hd__and4b_1" 4 73181;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356b3f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035da900_0 .net "A_N", 0 0, o000000000356b3f8; 0 drivers
+o000000000356b428 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035da220_0 .net "B", 0 0, o000000000356b428; 0 drivers
+o000000000356b458 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035db300_0 .net "C", 0 0, o000000000356b458; 0 drivers
+o000000000356b488 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d9460_0 .net "D", 0 0, o000000000356b488; 0 drivers
+L_0000000003889990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dac20_0 .net8 "VGND", 0 0, L_0000000003889990; 1 drivers, strength-aware
+L_0000000003889c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035da9a0_0 .net8 "VNB", 0 0, L_0000000003889c30; 1 drivers, strength-aware
+L_0000000003888ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035db580_0 .net8 "VPB", 0 0, L_0000000003888ff0; 1 drivers, strength-aware
+L_00000000038888f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d9dc0_0 .net8 "VPWR", 0 0, L_00000000038888f0; 1 drivers, strength-aware
+v00000000035d9280_0 .net "X", 0 0, L_000000000392fb30; 1 drivers
+S_00000000034e0330 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73201, 4 73502 1, S_0000000002835370;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392ff20 .functor NOT 1, o000000000356b3f8, C4<0>, C4<0>, C4<0>;
+L_000000000392ff90 .functor AND 1, L_000000000392ff20, o000000000356b428, o000000000356b458, o000000000356b488;
+L_000000000392fb30 .functor BUF 1, L_000000000392ff90, C4<0>, C4<0>, C4<0>;
+v00000000035d6e40_0 .net "A_N", 0 0, o000000000356b3f8; alias, 0 drivers
+v00000000035d6ee0_0 .net "B", 0 0, o000000000356b428; alias, 0 drivers
+v00000000035db120_0 .net "C", 0 0, o000000000356b458; alias, 0 drivers
+v00000000035dad60_0 .net "D", 0 0, o000000000356b488; alias, 0 drivers
+L_0000000003889680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035da720_0 .net8 "VGND", 0 0, L_0000000003889680; 1 drivers, strength-aware
+L_0000000003888570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d9f00_0 .net8 "VNB", 0 0, L_0000000003888570; 1 drivers, strength-aware
+L_0000000003888ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d95a0_0 .net8 "VPB", 0 0, L_0000000003888ce0; 1 drivers, strength-aware
+L_00000000038880a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d96e0_0 .net8 "VPWR", 0 0, L_00000000038880a0; 1 drivers, strength-aware
+v00000000035da040_0 .net "X", 0 0, L_000000000392fb30; alias, 1 drivers
+v00000000035da0e0_0 .net "and0_out_X", 0 0, L_000000000392ff90; 1 drivers
+v00000000035d9d20_0 .net "not0_out", 0 0, L_000000000392ff20; 1 drivers
+S_00000000028354f0 .scope module, "sky130_fd_sc_hd__and4b_2" "sky130_fd_sc_hd__and4b_2" 4 73625;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356b8a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dab80_0 .net "A_N", 0 0, o000000000356b8a8; 0 drivers
+o000000000356b8d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d9500_0 .net "B", 0 0, o000000000356b8d8; 0 drivers
+o000000000356b908 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035db440_0 .net "C", 0 0, o000000000356b908; 0 drivers
+o000000000356b938 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d9e60_0 .net "D", 0 0, o000000000356b938; 0 drivers
+L_0000000003888c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d9320_0 .net8 "VGND", 0 0, L_0000000003888c70; 1 drivers, strength-aware
+L_0000000003888650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035db6c0_0 .net8 "VNB", 0 0, L_0000000003888650; 1 drivers, strength-aware
+L_00000000038881f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d9640_0 .net8 "VPB", 0 0, L_00000000038881f0; 1 drivers, strength-aware
+L_00000000038889d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035da400_0 .net8 "VPWR", 0 0, L_00000000038889d0; 1 drivers, strength-aware
+v00000000035d9820_0 .net "X", 0 0, L_000000000392fc10; 1 drivers
+S_00000000034de230 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73645, 4 73502 1, S_00000000028354f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392fba0 .functor NOT 1, o000000000356b8a8, C4<0>, C4<0>, C4<0>;
+L_000000000392fc80 .functor AND 1, L_000000000392fba0, o000000000356b8d8, o000000000356b908, o000000000356b938;
+L_000000000392fc10 .functor BUF 1, L_000000000392fc80, C4<0>, C4<0>, C4<0>;
+v00000000035da180_0 .net "A_N", 0 0, o000000000356b8a8; alias, 0 drivers
+v00000000035db620_0 .net "B", 0 0, o000000000356b8d8; alias, 0 drivers
+v00000000035da4a0_0 .net "C", 0 0, o000000000356b908; alias, 0 drivers
+v00000000035daf40_0 .net "D", 0 0, o000000000356b938; alias, 0 drivers
+L_00000000038886c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dae00_0 .net8 "VGND", 0 0, L_00000000038886c0; 1 drivers, strength-aware
+L_0000000003889b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d9780_0 .net8 "VNB", 0 0, L_0000000003889b50; 1 drivers, strength-aware
+L_0000000003888ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035daea0_0 .net8 "VPB", 0 0, L_0000000003888ab0; 1 drivers, strength-aware
+L_0000000003888960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d9b40_0 .net8 "VPWR", 0 0, L_0000000003888960; 1 drivers, strength-aware
+v00000000035db260_0 .net "X", 0 0, L_000000000392fc10; alias, 1 drivers
+v00000000035d91e0_0 .net "and0_out_X", 0 0, L_000000000392fc80; 1 drivers
+v00000000035daae0_0 .net "not0_out", 0 0, L_000000000392fba0; 1 drivers
+S_0000000002835970 .scope module, "sky130_fd_sc_hd__and4b_4" "sky130_fd_sc_hd__and4b_4" 4 73743;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356bd58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035da2c0_0 .net "A_N", 0 0, o000000000356bd58; 0 drivers
+o000000000356bd88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035d9a00_0 .net "B", 0 0, o000000000356bd88; 0 drivers
+o000000000356bdb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035db080_0 .net "C", 0 0, o000000000356bdb8; 0 drivers
+o000000000356bde8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035da360_0 .net "D", 0 0, o000000000356bde8; 0 drivers
+L_00000000038887a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d93c0_0 .net8 "VGND", 0 0, L_00000000038887a0; 1 drivers, strength-aware
+L_0000000003888b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035da7c0_0 .net8 "VNB", 0 0, L_0000000003888b90; 1 drivers, strength-aware
+L_0000000003888c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035d9aa0_0 .net8 "VPB", 0 0, L_0000000003888c00; 1 drivers, strength-aware
+L_0000000003888d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035db800_0 .net8 "VPWR", 0 0, L_0000000003888d50; 1 drivers, strength-aware
+v00000000035dacc0_0 .net "X", 0 0, L_000000000392fdd0; 1 drivers
+S_00000000034db6b0 .scope module, "base" "sky130_fd_sc_hd__and4b" 4 73763, 4 73502 1, S_0000000002835970;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392fcf0 .functor NOT 1, o000000000356bd58, C4<0>, C4<0>, C4<0>;
+L_000000000392f900 .functor AND 1, L_000000000392fcf0, o000000000356bd88, o000000000356bdb8, o000000000356bde8;
+L_000000000392fdd0 .functor BUF 1, L_000000000392f900, C4<0>, C4<0>, C4<0>;
+v00000000035d9be0_0 .net "A_N", 0 0, o000000000356bd58; alias, 0 drivers
+v00000000035da5e0_0 .net "B", 0 0, o000000000356bd88; alias, 0 drivers
+v00000000035d98c0_0 .net "C", 0 0, o000000000356bdb8; alias, 0 drivers
+v00000000035da540_0 .net "D", 0 0, o000000000356bde8; alias, 0 drivers
+L_0000000003888dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035db1c0_0 .net8 "VGND", 0 0, L_0000000003888dc0; 1 drivers, strength-aware
+L_0000000003888e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035db3a0_0 .net8 "VNB", 0 0, L_0000000003888e30; 1 drivers, strength-aware
+L_0000000003888ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dafe0_0 .net8 "VPB", 0 0, L_0000000003888ea0; 1 drivers, strength-aware
+L_0000000003888f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035db4e0_0 .net8 "VPWR", 0 0, L_0000000003888f80; 1 drivers, strength-aware
+v00000000035da680_0 .net "X", 0 0, L_000000000392fdd0; alias, 1 drivers
+v00000000035db760_0 .net "and0_out_X", 0 0, L_000000000392f900; 1 drivers
+v00000000035d9960_0 .net "not0_out", 0 0, L_000000000392fcf0; 1 drivers
+S_00000000028179a0 .scope module, "sky130_fd_sc_hd__and4bb_1" "sky130_fd_sc_hd__and4bb_1" 4 42800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356c208 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035de000_0 .net "A_N", 0 0, o000000000356c208; 0 drivers
+o000000000356c238 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dcf20_0 .net "B_N", 0 0, o000000000356c238; 0 drivers
+o000000000356c268 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ddce0_0 .net "C", 0 0, o000000000356c268; 0 drivers
+o000000000356c298 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dc200_0 .net "D", 0 0, o000000000356c298; 0 drivers
+L_00000000038883b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dcde0_0 .net8 "VGND", 0 0, L_00000000038883b0; 1 drivers, strength-aware
+L_00000000038882d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dbee0_0 .net8 "VNB", 0 0, L_00000000038882d0; 1 drivers, strength-aware
+L_0000000003889060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc5c0_0 .net8 "VPB", 0 0, L_0000000003889060; 1 drivers, strength-aware
+L_00000000038895a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dbbc0_0 .net8 "VPWR", 0 0, L_00000000038895a0; 1 drivers, strength-aware
+v00000000035ddd80_0 .net "X", 0 0, L_000000000392fa50; 1 drivers
+S_00000000034dca30 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42820, 4 42559 1, S_00000000028179a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000392f970 .functor NOR 1, o000000000356c208, o000000000356c238, C4<0>, C4<0>;
+L_000000000392f9e0 .functor AND 1, L_000000000392f970, o000000000356c268, o000000000356c298, C4<1>;
+L_000000000392fa50 .functor BUF 1, L_000000000392f9e0, C4<0>, C4<0>, C4<0>;
+v00000000035daa40_0 .net "A_N", 0 0, o000000000356c208; alias, 0 drivers
+v00000000035da860_0 .net "B_N", 0 0, o000000000356c238; alias, 0 drivers
+v00000000035d9c80_0 .net "C", 0 0, o000000000356c268; alias, 0 drivers
+v00000000035db8a0_0 .net "D", 0 0, o000000000356c298; alias, 0 drivers
+L_0000000003888340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d9fa0_0 .net8 "VGND", 0 0, L_0000000003888340; 1 drivers, strength-aware
+L_00000000038885e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035d9140_0 .net8 "VNB", 0 0, L_00000000038885e0; 1 drivers, strength-aware
+L_00000000038890d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc520_0 .net8 "VPB", 0 0, L_00000000038890d0; 1 drivers, strength-aware
+L_0000000003889920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de0a0_0 .net8 "VPWR", 0 0, L_0000000003889920; 1 drivers, strength-aware
+v00000000035ddec0_0 .net "X", 0 0, L_000000000392fa50; alias, 1 drivers
+v00000000035dc660_0 .net "and0_out_X", 0 0, L_000000000392f9e0; 1 drivers
+v00000000035dbd00_0 .net "nor0_out", 0 0, L_000000000392f970; 1 drivers
+S_0000000002816c20 .scope module, "sky130_fd_sc_hd__and4bb_2" "sky130_fd_sc_hd__and4bb_2" 4 42918;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356c6b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dca20_0 .net "A_N", 0 0, o000000000356c6b8; 0 drivers
+o000000000356c6e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ddb00_0 .net "B_N", 0 0, o000000000356c6e8; 0 drivers
+o000000000356c718 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dbc60_0 .net "C", 0 0, o000000000356c718; 0 drivers
+o000000000356c748 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dc020_0 .net "D", 0 0, o000000000356c748; 0 drivers
+L_0000000003888420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd1a0_0 .net8 "VGND", 0 0, L_0000000003888420; 1 drivers, strength-aware
+L_0000000003889290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035db940_0 .net8 "VNB", 0 0, L_0000000003889290; 1 drivers, strength-aware
+L_0000000003888490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ddba0_0 .net8 "VPB", 0 0, L_0000000003888490; 1 drivers, strength-aware
+L_0000000003889300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc7a0_0 .net8 "VPWR", 0 0, L_0000000003889300; 1 drivers, strength-aware
+v00000000035dda60_0 .net "X", 0 0, L_0000000003910db0; 1 drivers
+S_00000000034de6b0 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42938, 4 42559 1, S_0000000002816c20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_0000000003910aa0 .functor NOR 1, o000000000356c6b8, o000000000356c6e8, C4<0>, C4<0>;
+L_00000000039113d0 .functor AND 1, L_0000000003910aa0, o000000000356c718, o000000000356c748, C4<1>;
+L_0000000003910db0 .functor BUF 1, L_00000000039113d0, C4<0>, C4<0>, C4<0>;
+v00000000035dd240_0 .net "A_N", 0 0, o000000000356c6b8; alias, 0 drivers
+v00000000035dd920_0 .net "B_N", 0 0, o000000000356c6e8; alias, 0 drivers
+v00000000035dd560_0 .net "C", 0 0, o000000000356c718; alias, 0 drivers
+v00000000035dbf80_0 .net "D", 0 0, o000000000356c748; alias, 0 drivers
+L_00000000038897d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dc700_0 .net8 "VGND", 0 0, L_00000000038897d0; 1 drivers, strength-aware
+L_00000000038893e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd9c0_0 .net8 "VNB", 0 0, L_00000000038893e0; 1 drivers, strength-aware
+L_0000000003889450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dce80_0 .net8 "VPB", 0 0, L_0000000003889450; 1 drivers, strength-aware
+L_0000000003889840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dd600_0 .net8 "VPWR", 0 0, L_0000000003889840; 1 drivers, strength-aware
+v00000000035dc840_0 .net "X", 0 0, L_0000000003910db0; alias, 1 drivers
+v00000000035dbda0_0 .net "and0_out_X", 0 0, L_00000000039113d0; 1 drivers
+v00000000035dd880_0 .net "nor0_out", 0 0, L_0000000003910aa0; 1 drivers
+S_0000000002816da0 .scope module, "sky130_fd_sc_hd__and4bb_4" "sky130_fd_sc_hd__and4bb_4" 4 42682;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000356cb68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dbe40_0 .net "A_N", 0 0, o000000000356cb68; 0 drivers
+o000000000356cb98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ddc40_0 .net "B_N", 0 0, o000000000356cb98; 0 drivers
+o000000000356cbc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dcc00_0 .net "C", 0 0, o000000000356cbc8; 0 drivers
+o000000000356cbf8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dc160_0 .net "D", 0 0, o000000000356cbf8; 0 drivers
+L_00000000038898b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dba80_0 .net8 "VGND", 0 0, L_00000000038898b0; 1 drivers, strength-aware
+L_0000000003889a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dcd40_0 .net8 "VNB", 0 0, L_0000000003889a70; 1 drivers, strength-aware
+L_0000000003888500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dbb20_0 .net8 "VPB", 0 0, L_0000000003888500; 1 drivers, strength-aware
+L_0000000003889ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc2a0_0 .net8 "VPWR", 0 0, L_0000000003889ae0; 1 drivers, strength-aware
+v00000000035dd6a0_0 .net "X", 0 0, L_0000000003910330; 1 drivers
+S_00000000034dcbb0 .scope module, "base" "sky130_fd_sc_hd__and4bb" 4 42702, 4 42559 1, S_0000000002816da0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_0000000003911980 .functor NOR 1, o000000000356cb68, o000000000356cb98, C4<0>, C4<0>;
+L_0000000003911910 .functor AND 1, L_0000000003911980, o000000000356cbc8, o000000000356cbf8, C4<1>;
+L_0000000003910330 .functor BUF 1, L_0000000003911910, C4<0>, C4<0>, C4<0>;
+v00000000035dde20_0 .net "A_N", 0 0, o000000000356cb68; alias, 0 drivers
+v00000000035dcca0_0 .net "B_N", 0 0, o000000000356cb98; alias, 0 drivers
+v00000000035dd740_0 .net "C", 0 0, o000000000356cbc8; alias, 0 drivers
+v00000000035dc8e0_0 .net "D", 0 0, o000000000356cbf8; alias, 0 drivers
+L_00000000038a4090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dc0c0_0 .net8 "VGND", 0 0, L_00000000038a4090; 1 drivers, strength-aware
+L_00000000038a5590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd2e0_0 .net8 "VNB", 0 0, L_00000000038a5590; 1 drivers, strength-aware
+L_00000000038a4170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc980_0 .net8 "VPB", 0 0, L_00000000038a4170; 1 drivers, strength-aware
+L_00000000038a4410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ddf60_0 .net8 "VPWR", 0 0, L_00000000038a4410; 1 drivers, strength-aware
+v00000000035db9e0_0 .net "X", 0 0, L_0000000003910330; alias, 1 drivers
+v00000000035dcac0_0 .net "and0_out_X", 0 0, L_0000000003911910; 1 drivers
+v00000000035dcb60_0 .net "nor0_out", 0 0, L_0000000003911980; 1 drivers
+S_0000000002817b20 .scope module, "sky130_fd_sc_hd__buf_12" "sky130_fd_sc_hd__buf_12" 4 80560;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356d018 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035dd380_0 .net "A", 0 0, o000000000356d018; 0 drivers
+L_00000000038a41e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd4c0_0 .net8 "VGND", 0 0, L_00000000038a41e0; 1 drivers, strength-aware
+L_00000000038a4790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd7e0_0 .net8 "VNB", 0 0, L_00000000038a4790; 1 drivers, strength-aware
+L_00000000038a5130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035df5e0_0 .net8 "VPB", 0 0, L_00000000038a5130; 1 drivers, strength-aware
+L_00000000038a46b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dfc20_0 .net8 "VPWR", 0 0, L_00000000038a46b0; 1 drivers, strength-aware
+v00000000035df540_0 .net "X", 0 0, L_00000000039103a0; 1 drivers
+S_00000000034e0c30 .scope module, "base" "sky130_fd_sc_hd__buf" 4 80574, 4 80948 1, S_0000000002817b20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910640 .functor BUF 1, o000000000356d018, C4<0>, C4<0>, C4<0>;
+L_00000000039103a0 .functor BUF 1, L_0000000003910640, C4<0>, C4<0>, C4<0>;
+v00000000035dcfc0_0 .net "A", 0 0, o000000000356d018; alias, 0 drivers
+L_00000000038a4f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dc340_0 .net8 "VGND", 0 0, L_00000000038a4f00; 1 drivers, strength-aware
+L_00000000038a5750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dd060_0 .net8 "VNB", 0 0, L_00000000038a5750; 1 drivers, strength-aware
+L_00000000038a4db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc3e0_0 .net8 "VPB", 0 0, L_00000000038a4db0; 1 drivers, strength-aware
+L_00000000038a4100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dc480_0 .net8 "VPWR", 0 0, L_00000000038a4100; 1 drivers, strength-aware
+v00000000035dd420_0 .net "X", 0 0, L_00000000039103a0; alias, 1 drivers
+v00000000035dd100_0 .net "buf0_out_X", 0 0, L_0000000003910640; 1 drivers
+S_00000000028176a0 .scope module, "sky130_fd_sc_hd__buf_16" "sky130_fd_sc_hd__buf_16" 4 80660;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356d2e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035deb40_0 .net "A", 0 0, o000000000356d2e8; 0 drivers
+L_00000000038a3f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df680_0 .net8 "VGND", 0 0, L_00000000038a3f40; 1 drivers, strength-aware
+L_00000000038a4f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df2c0_0 .net8 "VNB", 0 0, L_00000000038a4f70; 1 drivers, strength-aware
+L_00000000038a3fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ded20_0 .net8 "VPB", 0 0, L_00000000038a3fb0; 1 drivers, strength-aware
+L_00000000038a5440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de6e0_0 .net8 "VPWR", 0 0, L_00000000038a5440; 1 drivers, strength-aware
+v00000000035de140_0 .net "X", 0 0, L_0000000003911520; 1 drivers
+S_00000000034de830 .scope module, "base" "sky130_fd_sc_hd__buf" 4 80674, 4 80948 1, S_00000000028176a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039109c0 .functor BUF 1, o000000000356d2e8, C4<0>, C4<0>, C4<0>;
+L_0000000003911520 .functor BUF 1, L_00000000039109c0, C4<0>, C4<0>, C4<0>;
+v00000000035dfe00_0 .net "A", 0 0, o000000000356d2e8; alias, 0 drivers
+L_00000000038a4aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df180_0 .net8 "VGND", 0 0, L_00000000038a4aa0; 1 drivers, strength-aware
+L_00000000038a4020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035de320_0 .net8 "VNB", 0 0, L_00000000038a4020; 1 drivers, strength-aware
+L_00000000038a4c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de780_0 .net8 "VPB", 0 0, L_00000000038a4c60; 1 drivers, strength-aware
+L_00000000038a49c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de960_0 .net8 "VPWR", 0 0, L_00000000038a49c0; 1 drivers, strength-aware
+v00000000035dfcc0_0 .net "X", 0 0, L_0000000003911520; alias, 1 drivers
+v00000000035dee60_0 .net "buf0_out_X", 0 0, L_00000000039109c0; 1 drivers
+S_0000000002817220 .scope module, "sky130_fd_sc_hd__buf_4" "sky130_fd_sc_hd__buf_4" 4 81054;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356d5b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e0080_0 .net "A", 0 0, o000000000356d5b8; 0 drivers
+L_00000000038a3ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035de3c0_0 .net8 "VGND", 0 0, L_00000000038a3ed0; 1 drivers, strength-aware
+L_00000000038a4250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df720_0 .net8 "VNB", 0 0, L_00000000038a4250; 1 drivers, strength-aware
+L_00000000038a5830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de820_0 .net8 "VPB", 0 0, L_00000000038a5830; 1 drivers, strength-aware
+L_00000000038a3ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dedc0_0 .net8 "VPWR", 0 0, L_00000000038a3ca0; 1 drivers, strength-aware
+v00000000035de8c0_0 .net "X", 0 0, L_0000000003910cd0; 1 drivers
+S_00000000034e04b0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81068, 4 80948 1, S_0000000002817220;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039110c0 .functor BUF 1, o000000000356d5b8, C4<0>, C4<0>, C4<0>;
+L_0000000003910cd0 .functor BUF 1, L_00000000039110c0, C4<0>, C4<0>, C4<0>;
+v00000000035dfd60_0 .net "A", 0 0, o000000000356d5b8; alias, 0 drivers
+L_00000000038a44f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e06c0_0 .net8 "VGND", 0 0, L_00000000038a44f0; 1 drivers, strength-aware
+L_00000000038a52f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035def00_0 .net8 "VNB", 0 0, L_00000000038a52f0; 1 drivers, strength-aware
+L_00000000038a4d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dfea0_0 .net8 "VPB", 0 0, L_00000000038a4d40; 1 drivers, strength-aware
+L_00000000038a3d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de280_0 .net8 "VPWR", 0 0, L_00000000038a3d10; 1 drivers, strength-aware
+v00000000035dff40_0 .net "X", 0 0, L_0000000003910cd0; alias, 1 drivers
+v00000000035e0800_0 .net "buf0_out_X", 0 0, L_00000000039110c0; 1 drivers
+S_0000000002816020 .scope module, "sky130_fd_sc_hd__buf_6" "sky130_fd_sc_hd__buf_6" 4 81254;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356d888 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035df860_0 .net "A", 0 0, o000000000356d888; 0 drivers
+L_00000000038a45d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035deaa0_0 .net8 "VGND", 0 0, L_00000000038a45d0; 1 drivers, strength-aware
+L_00000000038a4e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df0e0_0 .net8 "VNB", 0 0, L_00000000038a4e20; 1 drivers, strength-aware
+L_00000000038a3d80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e01c0_0 .net8 "VPB", 0 0, L_00000000038a3d80; 1 drivers, strength-aware
+L_00000000038a4e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035debe0_0 .net8 "VPWR", 0 0, L_00000000038a4e90; 1 drivers, strength-aware
+v00000000035df900_0 .net "X", 0 0, L_0000000003910480; 1 drivers
+S_00000000034e0930 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81268, 4 80948 1, S_0000000002816020;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910410 .functor BUF 1, o000000000356d888, C4<0>, C4<0>, C4<0>;
+L_0000000003910480 .functor BUF 1, L_0000000003910410, C4<0>, C4<0>, C4<0>;
+v00000000035defa0_0 .net "A", 0 0, o000000000356d888; alias, 0 drivers
+L_00000000038a4cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df7c0_0 .net8 "VGND", 0 0, L_00000000038a4cd0; 1 drivers, strength-aware
+L_00000000038a57c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dffe0_0 .net8 "VNB", 0 0, L_00000000038a57c0; 1 drivers, strength-aware
+L_00000000038a42c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035df220_0 .net8 "VPB", 0 0, L_00000000038a42c0; 1 drivers, strength-aware
+L_00000000038a4b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e0120_0 .net8 "VPWR", 0 0, L_00000000038a4b10; 1 drivers, strength-aware
+v00000000035dea00_0 .net "X", 0 0, L_0000000003910480; alias, 1 drivers
+v00000000035df040_0 .net "buf0_out_X", 0 0, L_0000000003910410; 1 drivers
+S_0000000002817ca0 .scope module, "sky130_fd_sc_hd__buf_8" "sky130_fd_sc_hd__buf_8" 4 81454;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356db58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e0260_0 .net "A", 0 0, o000000000356db58; 0 drivers
+L_00000000038a4640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035df4a0_0 .net8 "VGND", 0 0, L_00000000038a4640; 1 drivers, strength-aware
+L_00000000038a3df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e0620_0 .net8 "VNB", 0 0, L_00000000038a3df0; 1 drivers, strength-aware
+L_00000000038a4330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035df9a0_0 .net8 "VPB", 0 0, L_00000000038a4330; 1 drivers, strength-aware
+L_00000000038a4720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035dfa40_0 .net8 "VPWR", 0 0, L_00000000038a4720; 1 drivers, strength-aware
+v00000000035e03a0_0 .net "X", 0 0, L_0000000003911440; 1 drivers
+S_00000000034e0ab0 .scope module, "base" "sky130_fd_sc_hd__buf" 4 81468, 4 80948 1, S_0000000002817ca0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911ad0 .functor BUF 1, o000000000356db58, C4<0>, C4<0>, C4<0>;
+L_0000000003911440 .functor BUF 1, L_0000000003911ad0, C4<0>, C4<0>, C4<0>;
+v00000000035df360_0 .net "A", 0 0, o000000000356db58; alias, 0 drivers
+L_00000000038a4800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dec80_0 .net8 "VGND", 0 0, L_00000000038a4800; 1 drivers, strength-aware
+L_00000000038a5280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e0580_0 .net8 "VNB", 0 0, L_00000000038a5280; 1 drivers, strength-aware
+L_00000000038a54b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e0300_0 .net8 "VPB", 0 0, L_00000000038a54b0; 1 drivers, strength-aware
+L_00000000038a5050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035df400_0 .net8 "VPWR", 0 0, L_00000000038a5050; 1 drivers, strength-aware
+v00000000035e0760_0 .net "X", 0 0, L_0000000003911440; alias, 1 drivers
+v00000000035e08a0_0 .net "buf0_out_X", 0 0, L_0000000003911ad0; 1 drivers
+S_0000000002816620 .scope module, "sky130_fd_sc_hd__bufbuf_16" "sky130_fd_sc_hd__bufbuf_16" 4 70555;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356de28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035de5a0_0 .net "A", 0 0, o000000000356de28; 0 drivers
+L_00000000038a4870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035de640_0 .net8 "VGND", 0 0, L_00000000038a4870; 1 drivers, strength-aware
+L_00000000038a5670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e12a0_0 .net8 "VNB", 0 0, L_00000000038a5670; 1 drivers, strength-aware
+L_00000000038a5360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e1c00_0 .net8 "VPB", 0 0, L_00000000038a5360; 1 drivers, strength-aware
+L_00000000038a48e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e0c60_0 .net8 "VPWR", 0 0, L_00000000038a48e0; 1 drivers, strength-aware
+v00000000035e2560_0 .net "X", 0 0, L_0000000003910f70; 1 drivers
+S_00000000034e5730 .scope module, "base" "sky130_fd_sc_hd__bufbuf" 4 70569, 4 70449 1, S_0000000002816620;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910d40 .functor BUF 1, o000000000356de28, C4<0>, C4<0>, C4<0>;
+L_0000000003910f70 .functor BUF 1, L_0000000003910d40, C4<0>, C4<0>, C4<0>;
+v00000000035de1e0_0 .net "A", 0 0, o000000000356de28; alias, 0 drivers
+L_00000000038a43a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035dfae0_0 .net8 "VGND", 0 0, L_00000000038a43a0; 1 drivers, strength-aware
+L_00000000038a3e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e04e0_0 .net8 "VNB", 0 0, L_00000000038a3e60; 1 drivers, strength-aware
+L_00000000038a4480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e0440_0 .net8 "VPB", 0 0, L_00000000038a4480; 1 drivers, strength-aware
+L_00000000038a5520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035de460_0 .net8 "VPWR", 0 0, L_00000000038a5520; 1 drivers, strength-aware
+v00000000035dfb80_0 .net "X", 0 0, L_0000000003910f70; alias, 1 drivers
+v00000000035de500_0 .net "buf0_out_X", 0 0, L_0000000003910d40; 1 drivers
+S_0000000002816aa0 .scope module, "sky130_fd_sc_hd__bufbuf_8" "sky130_fd_sc_hd__bufbuf_8" 4 70161;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356e0f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e0bc0_0 .net "A", 0 0, o000000000356e0f8; 0 drivers
+L_00000000038a4b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e1e80_0 .net8 "VGND", 0 0, L_00000000038a4b80; 1 drivers, strength-aware
+L_00000000038a4fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e0f80_0 .net8 "VNB", 0 0, L_00000000038a4fe0; 1 drivers, strength-aware
+L_00000000038a4bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e1ca0_0 .net8 "VPB", 0 0, L_00000000038a4bf0; 1 drivers, strength-aware
+L_00000000038a4560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e1020_0 .net8 "VPWR", 0 0, L_00000000038a4560; 1 drivers, strength-aware
+v00000000035e2c40_0 .net "X", 0 0, L_0000000003911130; 1 drivers
+S_00000000034e49b0 .scope module, "base" "sky130_fd_sc_hd__bufbuf" 4 70175, 4 70449 1, S_0000000002816aa0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039114b0 .functor BUF 1, o000000000356e0f8, C4<0>, C4<0>, C4<0>;
+L_0000000003911130 .functor BUF 1, L_00000000039114b0, C4<0>, C4<0>, C4<0>;
+v00000000035e1160_0 .net "A", 0 0, o000000000356e0f8; alias, 0 drivers
+L_00000000038a50c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e1de0_0 .net8 "VGND", 0 0, L_00000000038a50c0; 1 drivers, strength-aware
+L_00000000038a51a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e10c0_0 .net8 "VNB", 0 0, L_00000000038a51a0; 1 drivers, strength-aware
+L_00000000038a4950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e0ee0_0 .net8 "VPB", 0 0, L_00000000038a4950; 1 drivers, strength-aware
+L_00000000038a4a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2740_0 .net8 "VPWR", 0 0, L_00000000038a4a30; 1 drivers, strength-aware
+v00000000035e1200_0 .net "X", 0 0, L_0000000003911130; alias, 1 drivers
+v00000000035e1f20_0 .net "buf0_out_X", 0 0, L_00000000039114b0; 1 drivers
+S_00000000028167a0 .scope module, "sky130_fd_sc_hd__bufinv_16" "sky130_fd_sc_hd__bufinv_16" 4 37202;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000356e3c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e13e0_0 .net "A", 0 0, o000000000356e3c8; 0 drivers
+L_00000000038a5210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e1520_0 .net8 "VGND", 0 0, L_00000000038a5210; 1 drivers, strength-aware
+L_00000000038a53d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2880_0 .net8 "VNB", 0 0, L_00000000038a53d0; 1 drivers, strength-aware
+L_00000000038a5600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e17a0_0 .net8 "VPB", 0 0, L_00000000038a5600; 1 drivers, strength-aware
+L_00000000038a56e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2100_0 .net8 "VPWR", 0 0, L_00000000038a56e0; 1 drivers, strength-aware
+v00000000035e1ac0_0 .net "Y", 0 0, L_0000000003911360; 1 drivers
+S_00000000034e3930 .scope module, "base" "sky130_fd_sc_hd__bufinv" 4 37216, 4 37490 1, S_00000000028167a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911b40 .functor NOT 1, o000000000356e3c8, C4<0>, C4<0>, C4<0>;
+L_0000000003911360 .functor BUF 1, L_0000000003911b40, C4<0>, C4<0>, C4<0>;
+v00000000035e1fc0_0 .net "A", 0 0, o000000000356e3c8; alias, 0 drivers
+L_00000000038a67f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2600_0 .net8 "VGND", 0 0, L_00000000038a67f0; 1 drivers, strength-aware
+L_00000000038a6080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e1a20_0 .net8 "VNB", 0 0, L_00000000038a6080; 1 drivers, strength-aware
+L_00000000038a6240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e1d40_0 .net8 "VPB", 0 0, L_00000000038a6240; 1 drivers, strength-aware
+L_00000000038a5ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e1340_0 .net8 "VPWR", 0 0, L_00000000038a5ad0; 1 drivers, strength-aware
+v00000000035e1980_0 .net "Y", 0 0, L_0000000003911360; alias, 1 drivers
+v00000000035e2920_0 .net "not0_out_Y", 0 0, L_0000000003911b40; 1 drivers
+S_0000000002816f20 .scope module, "sky130_fd_sc_hd__bufinv_8" "sky130_fd_sc_hd__bufinv_8" 4 37102;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000356e698 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e1b60_0 .net "A", 0 0, o000000000356e698; 0 drivers
+L_00000000038a6b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2e20_0 .net8 "VGND", 0 0, L_00000000038a6b00; 1 drivers, strength-aware
+L_00000000038a6ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e21a0_0 .net8 "VNB", 0 0, L_00000000038a6ef0; 1 drivers, strength-aware
+L_00000000038a7350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e27e0_0 .net8 "VPB", 0 0, L_00000000038a7350; 1 drivers, strength-aware
+L_00000000038a6a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e26a0_0 .net8 "VPWR", 0 0, L_00000000038a6a90; 1 drivers, strength-aware
+v00000000035e1700_0 .net "Y", 0 0, L_0000000003910c60; 1 drivers
+S_00000000034e6f30 .scope module, "base" "sky130_fd_sc_hd__bufinv" 4 37116, 4 37490 1, S_0000000002816f20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910170 .functor NOT 1, o000000000356e698, C4<0>, C4<0>, C4<0>;
+L_0000000003910c60 .functor BUF 1, L_0000000003910170, C4<0>, C4<0>, C4<0>;
+v00000000035e1480_0 .net "A", 0 0, o000000000356e698; alias, 0 drivers
+L_00000000038a6320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2d80_0 .net8 "VGND", 0 0, L_00000000038a6320; 1 drivers, strength-aware
+L_00000000038a6940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2b00_0 .net8 "VNB", 0 0, L_00000000038a6940; 1 drivers, strength-aware
+L_00000000038a6a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e15c0_0 .net8 "VPB", 0 0, L_00000000038a6a20; 1 drivers, strength-aware
+L_00000000038a6550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2ec0_0 .net8 "VPWR", 0 0, L_00000000038a6550; 1 drivers, strength-aware
+v00000000035e2060_0 .net "Y", 0 0, L_0000000003910c60; alias, 1 drivers
+v00000000035e1660_0 .net "not0_out_Y", 0 0, L_0000000003910170; 1 drivers
+S_0000000002817820 .scope module, "sky130_fd_sc_hd__clkbuf_1" "sky130_fd_sc_hd__clkbuf_1" 4 94876;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356e968 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e0d00_0 .net "A", 0 0, o000000000356e968; 0 drivers
+L_00000000038a5f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e18e0_0 .net8 "VGND", 0 0, L_00000000038a5f30; 1 drivers, strength-aware
+L_00000000038a5d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2420_0 .net8 "VNB", 0 0, L_00000000038a5d70; 1 drivers, strength-aware
+L_00000000038a6be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2ba0_0 .net8 "VPB", 0 0, L_00000000038a6be0; 1 drivers, strength-aware
+L_00000000038a70b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2a60_0 .net8 "VPWR", 0 0, L_00000000038a70b0; 1 drivers, strength-aware
+v00000000035e0a80_0 .net "X", 0 0, L_0000000003910e90; 1 drivers
+S_00000000034e37b0 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94890, 4 95264 1, S_0000000002817820;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039104f0 .functor BUF 1, o000000000356e968, C4<0>, C4<0>, C4<0>;
+L_0000000003910e90 .functor BUF 1, L_00000000039104f0, C4<0>, C4<0>, C4<0>;
+v00000000035e1840_0 .net "A", 0 0, o000000000356e968; alias, 0 drivers
+L_00000000038a66a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2ce0_0 .net8 "VGND", 0 0, L_00000000038a66a0; 1 drivers, strength-aware
+L_00000000038a5fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e29c0_0 .net8 "VNB", 0 0, L_00000000038a5fa0; 1 drivers, strength-aware
+L_00000000038a5c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2380_0 .net8 "VPB", 0 0, L_00000000038a5c90; 1 drivers, strength-aware
+L_00000000038a62b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e2240_0 .net8 "VPWR", 0 0, L_00000000038a62b0; 1 drivers, strength-aware
+v00000000035e0940_0 .net "X", 0 0, L_0000000003910e90; alias, 1 drivers
+v00000000035e22e0_0 .net "buf0_out_X", 0 0, L_00000000039104f0; 1 drivers
+S_0000000002815ea0 .scope module, "sky130_fd_sc_hd__clkbuf_16" "sky130_fd_sc_hd__clkbuf_16" 4 94776;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356ec38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e0e40_0 .net "A", 0 0, o000000000356ec38; 0 drivers
+L_00000000038a6f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4b80_0 .net8 "VGND", 0 0, L_00000000038a6f60; 1 drivers, strength-aware
+L_00000000038a6400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4fe0_0 .net8 "VNB", 0 0, L_00000000038a6400; 1 drivers, strength-aware
+L_00000000038a6470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e38c0_0 .net8 "VPB", 0 0, L_00000000038a6470; 1 drivers, strength-aware
+L_00000000038a6010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3140_0 .net8 "VPWR", 0 0, L_00000000038a6010; 1 drivers, strength-aware
+v00000000035e54e0_0 .net "X", 0 0, L_00000000039111a0; 1 drivers
+S_00000000034e3330 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94790, 4 95264 1, S_0000000002815ea0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911600 .functor BUF 1, o000000000356ec38, C4<0>, C4<0>, C4<0>;
+L_00000000039111a0 .functor BUF 1, L_0000000003911600, C4<0>, C4<0>, C4<0>;
+v00000000035e24c0_0 .net "A", 0 0, o000000000356ec38; alias, 0 drivers
+L_00000000038a6b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e2f60_0 .net8 "VGND", 0 0, L_00000000038a6b70; 1 drivers, strength-aware
+L_00000000038a6860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3000_0 .net8 "VNB", 0 0, L_00000000038a6860; 1 drivers, strength-aware
+L_00000000038a60f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e30a0_0 .net8 "VPB", 0 0, L_00000000038a60f0; 1 drivers, strength-aware
+L_00000000038a5a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e09e0_0 .net8 "VPWR", 0 0, L_00000000038a5a60; 1 drivers, strength-aware
+v00000000035e0b20_0 .net "X", 0 0, L_00000000039111a0; alias, 1 drivers
+v00000000035e0da0_0 .net "buf0_out_X", 0 0, L_0000000003911600; 1 drivers
+S_00000000028161a0 .scope module, "sky130_fd_sc_hd__clkbuf_2" "sky130_fd_sc_hd__clkbuf_2" 4 95370;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356ef08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e3f00_0 .net "A", 0 0, o000000000356ef08; 0 drivers
+L_00000000038a6c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3960_0 .net8 "VGND", 0 0, L_00000000038a6c50; 1 drivers, strength-aware
+L_00000000038a5b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3d20_0 .net8 "VNB", 0 0, L_00000000038a5b40; 1 drivers, strength-aware
+L_00000000038a5910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3a00_0 .net8 "VPB", 0 0, L_00000000038a5910; 1 drivers, strength-aware
+L_00000000038a6160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e4540_0 .net8 "VPWR", 0 0, L_00000000038a6160; 1 drivers, strength-aware
+v00000000035e3460_0 .net "X", 0 0, L_00000000039119f0; 1 drivers
+S_00000000034e55b0 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 95384, 4 95264 1, S_00000000028161a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039106b0 .functor BUF 1, o000000000356ef08, C4<0>, C4<0>, C4<0>;
+L_00000000039119f0 .functor BUF 1, L_00000000039106b0, C4<0>, C4<0>, C4<0>;
+v00000000035e4220_0 .net "A", 0 0, o000000000356ef08; alias, 0 drivers
+L_00000000038a61d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4a40_0 .net8 "VGND", 0 0, L_00000000038a61d0; 1 drivers, strength-aware
+L_00000000038a5980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e5800_0 .net8 "VNB", 0 0, L_00000000038a5980; 1 drivers, strength-aware
+L_00000000038a5de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e47c0_0 .net8 "VPB", 0 0, L_00000000038a5de0; 1 drivers, strength-aware
+L_00000000038a6e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e49a0_0 .net8 "VPWR", 0 0, L_00000000038a6e80; 1 drivers, strength-aware
+v00000000035e44a0_0 .net "X", 0 0, L_00000000039119f0; alias, 1 drivers
+v00000000035e4860_0 .net "buf0_out_X", 0 0, L_00000000039106b0; 1 drivers
+S_0000000002816320 .scope module, "sky130_fd_sc_hd__clkbuf_4" "sky130_fd_sc_hd__clkbuf_4" 4 94976;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356f1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e31e0_0 .net "A", 0 0, o000000000356f1d8; 0 drivers
+L_00000000038a5ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4c20_0 .net8 "VGND", 0 0, L_00000000038a5ec0; 1 drivers, strength-aware
+L_00000000038a59f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4ae0_0 .net8 "VNB", 0 0, L_00000000038a59f0; 1 drivers, strength-aware
+L_00000000038a6710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e4cc0_0 .net8 "VPB", 0 0, L_00000000038a6710; 1 drivers, strength-aware
+L_00000000038a5bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e35a0_0 .net8 "VPWR", 0 0, L_00000000038a5bb0; 1 drivers, strength-aware
+v00000000035e3aa0_0 .net "X", 0 0, L_0000000003911210; 1 drivers
+S_00000000034e2d30 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 94990, 4 95264 1, S_0000000002816320;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910fe0 .functor BUF 1, o000000000356f1d8, C4<0>, C4<0>, C4<0>;
+L_0000000003911210 .functor BUF 1, L_0000000003910fe0, C4<0>, C4<0>, C4<0>;
+v00000000035e4400_0 .net "A", 0 0, o000000000356f1d8; alias, 0 drivers
+L_00000000038a6fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4900_0 .net8 "VGND", 0 0, L_00000000038a6fd0; 1 drivers, strength-aware
+L_00000000038a69b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4e00_0 .net8 "VNB", 0 0, L_00000000038a69b0; 1 drivers, strength-aware
+L_00000000038a73c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e42c0_0 .net8 "VPB", 0 0, L_00000000038a73c0; 1 drivers, strength-aware
+L_00000000038a6d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3e60_0 .net8 "VPWR", 0 0, L_00000000038a6d30; 1 drivers, strength-aware
+v00000000035e3500_0 .net "X", 0 0, L_0000000003911210; alias, 1 drivers
+v00000000035e5620_0 .net "buf0_out_X", 0 0, L_0000000003910fe0; 1 drivers
+S_00000000028170a0 .scope module, "sky130_fd_sc_hd__clkbuf_8" "sky130_fd_sc_hd__clkbuf_8" 4 95470;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356f4a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e4ea0_0 .net "A", 0 0, o000000000356f4a8; 0 drivers
+L_00000000038a6cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4180_0 .net8 "VGND", 0 0, L_00000000038a6cc0; 1 drivers, strength-aware
+L_00000000038a6390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3320_0 .net8 "VNB", 0 0, L_00000000038a6390; 1 drivers, strength-aware
+L_00000000038a7040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3780_0 .net8 "VPB", 0 0, L_00000000038a7040; 1 drivers, strength-aware
+L_00000000038a6da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3b40_0 .net8 "VPWR", 0 0, L_00000000038a6da0; 1 drivers, strength-aware
+v00000000035e4d60_0 .net "X", 0 0, L_00000000039105d0; 1 drivers
+S_00000000034e2730 .scope module, "base" "sky130_fd_sc_hd__clkbuf" 4 95484, 4 95264 1, S_00000000028170a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039102c0 .functor BUF 1, o000000000356f4a8, C4<0>, C4<0>, C4<0>;
+L_00000000039105d0 .functor BUF 1, L_00000000039102c0, C4<0>, C4<0>, C4<0>;
+v00000000035e45e0_0 .net "A", 0 0, o000000000356f4a8; alias, 0 drivers
+L_00000000038a64e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e5580_0 .net8 "VGND", 0 0, L_00000000038a64e0; 1 drivers, strength-aware
+L_00000000038a65c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4680_0 .net8 "VNB", 0 0, L_00000000038a65c0; 1 drivers, strength-aware
+L_00000000038a6e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e56c0_0 .net8 "VPB", 0 0, L_00000000038a6e10; 1 drivers, strength-aware
+L_00000000038a6630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e4720_0 .net8 "VPWR", 0 0, L_00000000038a6630; 1 drivers, strength-aware
+v00000000035e5760_0 .net "X", 0 0, L_00000000039105d0; alias, 1 drivers
+v00000000035e3640_0 .net "buf0_out_X", 0 0, L_00000000039102c0; 1 drivers
+S_00000000028173a0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s15_1" "sky130_fd_sc_hd__clkdlybuf4s15_1" 4 81656;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356f778 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e51c0_0 .net "A", 0 0, o000000000356f778; 0 drivers
+L_00000000038a5c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e58a0_0 .net8 "VGND", 0 0, L_00000000038a5c20; 1 drivers, strength-aware
+L_00000000038a7120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4040_0 .net8 "VNB", 0 0, L_00000000038a7120; 1 drivers, strength-aware
+L_00000000038a5d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5260_0 .net8 "VPB", 0 0, L_00000000038a5d00; 1 drivers, strength-aware
+L_00000000038a6780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e33c0_0 .net8 "VPWR", 0 0, L_00000000038a6780; 1 drivers, strength-aware
+v00000000035e5300_0 .net "X", 0 0, L_0000000003910b10; 1 drivers
+S_00000000034e2a30 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s15" 4 81670, 4 81949 1, S_00000000028173a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911050 .functor BUF 1, o000000000356f778, C4<0>, C4<0>, C4<0>;
+L_0000000003910b10 .functor BUF 1, L_0000000003911050, C4<0>, C4<0>, C4<0>;
+v00000000035e4f40_0 .net "A", 0 0, o000000000356f778; alias, 0 drivers
+L_00000000038a58a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e4360_0 .net8 "VGND", 0 0, L_00000000038a58a0; 1 drivers, strength-aware
+L_00000000038a7190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3dc0_0 .net8 "VNB", 0 0, L_00000000038a7190; 1 drivers, strength-aware
+L_00000000038a5e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5080_0 .net8 "VPB", 0 0, L_00000000038a5e50; 1 drivers, strength-aware
+L_00000000038a68d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3280_0 .net8 "VPWR", 0 0, L_00000000038a68d0; 1 drivers, strength-aware
+v00000000035e3fa0_0 .net "X", 0 0, L_0000000003910b10; alias, 1 drivers
+v00000000035e5120_0 .net "buf0_out_X", 0 0, L_0000000003911050; 1 drivers
+S_0000000002816920 .scope module, "sky130_fd_sc_hd__clkdlybuf4s15_2" "sky130_fd_sc_hd__clkdlybuf4s15_2" 4 81555;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356fa48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e65c0_0 .net "A", 0 0, o000000000356fa48; 0 drivers
+L_00000000038a7200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6f20_0 .net8 "VGND", 0 0, L_00000000038a7200; 1 drivers, strength-aware
+L_00000000038a7270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e7600_0 .net8 "VNB", 0 0, L_00000000038a7270; 1 drivers, strength-aware
+L_00000000038a72e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e6a20_0 .net8 "VPB", 0 0, L_00000000038a72e0; 1 drivers, strength-aware
+L_00000000038a7430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7560_0 .net8 "VPWR", 0 0, L_00000000038a7430; 1 drivers, strength-aware
+v00000000035e5ee0_0 .net "X", 0 0, L_00000000039101e0; 1 drivers
+S_00000000034e4530 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s15" 4 81569, 4 81949 1, S_0000000002816920;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911280 .functor BUF 1, o000000000356fa48, C4<0>, C4<0>, C4<0>;
+L_00000000039101e0 .functor BUF 1, L_0000000003911280, C4<0>, C4<0>, C4<0>;
+v00000000035e36e0_0 .net "A", 0 0, o000000000356fa48; alias, 0 drivers
+L_00000000038a74a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e53a0_0 .net8 "VGND", 0 0, L_00000000038a74a0; 1 drivers, strength-aware
+L_00000000038a8d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e3820_0 .net8 "VNB", 0 0, L_00000000038a8d90; 1 drivers, strength-aware
+L_00000000038a81c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5440_0 .net8 "VPB", 0 0, L_00000000038a81c0; 1 drivers, strength-aware
+L_00000000038a8460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e3be0_0 .net8 "VPWR", 0 0, L_00000000038a8460; 1 drivers, strength-aware
+v00000000035e3c80_0 .net "X", 0 0, L_00000000039101e0; alias, 1 drivers
+v00000000035e40e0_0 .net "buf0_out_X", 0 0, L_0000000003911280; 1 drivers
+S_0000000002817520 .scope module, "sky130_fd_sc_hd__clkdlybuf4s18_1" "sky130_fd_sc_hd__clkdlybuf4s18_1" 4 21940;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356fd18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e6700_0 .net "A", 0 0, o000000000356fd18; 0 drivers
+L_00000000038a8d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6480_0 .net8 "VGND", 0 0, L_00000000038a8d20; 1 drivers, strength-aware
+L_00000000038a8690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e7d80_0 .net8 "VNB", 0 0, L_00000000038a8690; 1 drivers, strength-aware
+L_00000000038a8e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7b00_0 .net8 "VPB", 0 0, L_00000000038a8e70; 1 drivers, strength-aware
+L_00000000038a7900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e6660_0 .net8 "VPWR", 0 0, L_00000000038a7900; 1 drivers, strength-aware
+v00000000035e7ec0_0 .net "X", 0 0, L_00000000039112f0; 1 drivers
+S_00000000034e5d30 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s18" 4 21954, 4 22233 1, S_0000000002817520;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911590 .functor BUF 1, o000000000356fd18, C4<0>, C4<0>, C4<0>;
+L_00000000039112f0 .functor BUF 1, L_0000000003911590, C4<0>, C4<0>, C4<0>;
+v00000000035e5f80_0 .net "A", 0 0, o000000000356fd18; alias, 0 drivers
+L_00000000038a8e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6520_0 .net8 "VGND", 0 0, L_00000000038a8e00; 1 drivers, strength-aware
+L_00000000038a7580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e7880_0 .net8 "VNB", 0 0, L_00000000038a7580; 1 drivers, strength-aware
+L_00000000038a76d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e67a0_0 .net8 "VPB", 0 0, L_00000000038a76d0; 1 drivers, strength-aware
+L_00000000038a7ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7100_0 .net8 "VPWR", 0 0, L_00000000038a7ba0; 1 drivers, strength-aware
+v00000000035e6ac0_0 .net "X", 0 0, L_00000000039112f0; alias, 1 drivers
+v00000000035e7380_0 .net "buf0_out_X", 0 0, L_0000000003911590; 1 drivers
+S_00000000028164a0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s18_2" "sky130_fd_sc_hd__clkdlybuf4s18_2" 4 21839;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000356ffe8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e7f60_0 .net "A", 0 0, o000000000356ffe8; 0 drivers
+L_00000000038a7b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e60c0_0 .net8 "VGND", 0 0, L_00000000038a7b30; 1 drivers, strength-aware
+L_00000000038a8850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6160_0 .net8 "VNB", 0 0, L_00000000038a8850; 1 drivers, strength-aware
+L_00000000038a8620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e62a0_0 .net8 "VPB", 0 0, L_00000000038a8620; 1 drivers, strength-aware
+L_00000000038a8ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7240_0 .net8 "VPWR", 0 0, L_00000000038a8ee0; 1 drivers, strength-aware
+v00000000035e6840_0 .net "X", 0 0, L_00000000039108e0; 1 drivers
+S_00000000034e2eb0 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s18" 4 21853, 4 22233 1, S_00000000028164a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910790 .functor BUF 1, o000000000356ffe8, C4<0>, C4<0>, C4<0>;
+L_00000000039108e0 .functor BUF 1, L_0000000003910790, C4<0>, C4<0>, C4<0>;
+v00000000035e6980_0 .net "A", 0 0, o000000000356ffe8; alias, 0 drivers
+L_00000000038a8700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e7e20_0 .net8 "VGND", 0 0, L_00000000038a8700; 1 drivers, strength-aware
+L_00000000038a7820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6ca0_0 .net8 "VNB", 0 0, L_00000000038a7820; 1 drivers, strength-aware
+L_00000000038a8a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7740_0 .net8 "VPB", 0 0, L_00000000038a8a10; 1 drivers, strength-aware
+L_00000000038a7890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e76a0_0 .net8 "VPWR", 0 0, L_00000000038a7890; 1 drivers, strength-aware
+v00000000035e6020_0 .net "X", 0 0, L_00000000039108e0; alias, 1 drivers
+v00000000035e77e0_0 .net "buf0_out_X", 0 0, L_0000000003910790; 1 drivers
+S_0000000002818930 .scope module, "sky130_fd_sc_hd__clkdlybuf4s25_1" "sky130_fd_sc_hd__clkdlybuf4s25_1" 4 38508;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000035702b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e80a0_0 .net "A", 0 0, o00000000035702b8; 0 drivers
+L_00000000038a8770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e72e0_0 .net8 "VGND", 0 0, L_00000000038a8770; 1 drivers, strength-aware
+L_00000000038a87e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6c00_0 .net8 "VNB", 0 0, L_00000000038a87e0; 1 drivers, strength-aware
+L_00000000038a8a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e6d40_0 .net8 "VPB", 0 0, L_00000000038a8a80; 1 drivers, strength-aware
+L_00000000038a88c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5c60_0 .net8 "VPWR", 0 0, L_00000000038a88c0; 1 drivers, strength-aware
+v00000000035e74c0_0 .net "X", 0 0, L_0000000003911670; 1 drivers
+S_00000000034e1830 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s25" 4 38522, 4 38401 1, S_0000000002818930;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911a60 .functor BUF 1, o00000000035702b8, C4<0>, C4<0>, C4<0>;
+L_0000000003911670 .functor BUF 1, L_0000000003911a60, C4<0>, C4<0>, C4<0>;
+v00000000035e6200_0 .net "A", 0 0, o00000000035702b8; alias, 0 drivers
+L_00000000038a8070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6340_0 .net8 "VGND", 0 0, L_00000000038a8070; 1 drivers, strength-aware
+L_00000000038a8f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e68e0_0 .net8 "VNB", 0 0, L_00000000038a8f50; 1 drivers, strength-aware
+L_00000000038a7970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e6b60_0 .net8 "VPB", 0 0, L_00000000038a7970; 1 drivers, strength-aware
+L_00000000038a7f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e79c0_0 .net8 "VPWR", 0 0, L_00000000038a7f90; 1 drivers, strength-aware
+v00000000035e8000_0 .net "X", 0 0, L_0000000003911670; alias, 1 drivers
+v00000000035e7420_0 .net "buf0_out_X", 0 0, L_0000000003911a60; 1 drivers
+S_00000000028190b0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s25_2" "sky130_fd_sc_hd__clkdlybuf4s25_2" 4 38609;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003570588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e5a80_0 .net "A", 0 0, o0000000003570588; 0 drivers
+L_00000000038a8930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e5940_0 .net8 "VGND", 0 0, L_00000000038a8930; 1 drivers, strength-aware
+L_00000000038a7660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6e80_0 .net8 "VNB", 0 0, L_00000000038a7660; 1 drivers, strength-aware
+L_00000000038a8fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5d00_0 .net8 "VPB", 0 0, L_00000000038a8fc0; 1 drivers, strength-aware
+L_00000000038a9030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7ba0_0 .net8 "VPWR", 0 0, L_00000000038a9030; 1 drivers, strength-aware
+v00000000035e6fc0_0 .net "X", 0 0, L_0000000003910e20; 1 drivers
+S_00000000034e28b0 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s25" 4 38623, 4 38401 1, S_00000000028190b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911bb0 .functor BUF 1, o0000000003570588, C4<0>, C4<0>, C4<0>;
+L_0000000003910e20 .functor BUF 1, L_0000000003911bb0, C4<0>, C4<0>, C4<0>;
+v00000000035e59e0_0 .net "A", 0 0, o0000000003570588; alias, 0 drivers
+L_00000000038a8af0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e6de0_0 .net8 "VGND", 0 0, L_00000000038a8af0; 1 drivers, strength-aware
+L_00000000038a8310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e71a0_0 .net8 "VNB", 0 0, L_00000000038a8310; 1 drivers, strength-aware
+L_00000000038a8230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7c40_0 .net8 "VPB", 0 0, L_00000000038a8230; 1 drivers, strength-aware
+L_00000000038a89a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e7920_0 .net8 "VPWR", 0 0, L_00000000038a89a0; 1 drivers, strength-aware
+v00000000035e7a60_0 .net "X", 0 0, L_0000000003910e20; alias, 1 drivers
+v00000000035e7ce0_0 .net "buf0_out_X", 0 0, L_0000000003911bb0; 1 drivers
+S_0000000002818ab0 .scope module, "sky130_fd_sc_hd__clkdlybuf4s50_1" "sky130_fd_sc_hd__clkdlybuf4s50_1" 4 90585;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003570858 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e9540_0 .net "A", 0 0, o0000000003570858; 0 drivers
+L_00000000038a8b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8500_0 .net8 "VGND", 0 0, L_00000000038a8b60; 1 drivers, strength-aware
+L_00000000038a7510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8aa0_0 .net8 "VNB", 0 0, L_00000000038a7510; 1 drivers, strength-aware
+L_00000000038a7d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e83c0_0 .net8 "VPB", 0 0, L_00000000038a7d60; 1 drivers, strength-aware
+L_00000000038a85b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e9180_0 .net8 "VPWR", 0 0, L_00000000038a85b0; 1 drivers, strength-aware
+v00000000035e8320_0 .net "X", 0 0, L_0000000003910560; 1 drivers
+S_00000000034e19b0 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s50" 4 90599, 4 90878 1, S_0000000002818ab0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911c20 .functor BUF 1, o0000000003570858, C4<0>, C4<0>, C4<0>;
+L_0000000003910560 .functor BUF 1, L_0000000003911c20, C4<0>, C4<0>, C4<0>;
+v00000000035e7060_0 .net "A", 0 0, o0000000003570858; alias, 0 drivers
+L_00000000038a8bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e63e0_0 .net8 "VGND", 0 0, L_00000000038a8bd0; 1 drivers, strength-aware
+L_00000000038a8c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e5b20_0 .net8 "VNB", 0 0, L_00000000038a8c40; 1 drivers, strength-aware
+L_00000000038a75f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5bc0_0 .net8 "VPB", 0 0, L_00000000038a75f0; 1 drivers, strength-aware
+L_00000000038a7740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e5da0_0 .net8 "VPWR", 0 0, L_00000000038a7740; 1 drivers, strength-aware
+v00000000035e5e40_0 .net "X", 0 0, L_0000000003910560; alias, 1 drivers
+v00000000035e9c20_0 .net "buf0_out_X", 0 0, L_0000000003911c20; 1 drivers
+S_0000000002819230 .scope module, "sky130_fd_sc_hd__clkdlybuf4s50_2" "sky130_fd_sc_hd__clkdlybuf4s50_2" 4 90484;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003570b28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ea800_0 .net "A", 0 0, o0000000003570b28; 0 drivers
+L_00000000038a77b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9f40_0 .net8 "VGND", 0 0, L_00000000038a77b0; 1 drivers, strength-aware
+L_00000000038a7f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9fe0_0 .net8 "VNB", 0 0, L_00000000038a7f20; 1 drivers, strength-aware
+L_00000000038a79e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea8a0_0 .net8 "VPB", 0 0, L_00000000038a79e0; 1 drivers, strength-aware
+L_00000000038a8540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea6c0_0 .net8 "VPWR", 0 0, L_00000000038a8540; 1 drivers, strength-aware
+v00000000035e8f00_0 .net "X", 0 0, L_0000000003910100; 1 drivers
+S_00000000034e2430 .scope module, "base" "sky130_fd_sc_hd__clkdlybuf4s50" 4 90498, 4 90878 1, S_0000000002819230;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911c90 .functor BUF 1, o0000000003570b28, C4<0>, C4<0>, C4<0>;
+L_0000000003910100 .functor BUF 1, L_0000000003911c90, C4<0>, C4<0>, C4<0>;
+v00000000035e8e60_0 .net "A", 0 0, o0000000003570b28; alias, 0 drivers
+L_00000000038a7a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8be0_0 .net8 "VGND", 0 0, L_00000000038a7a50; 1 drivers, strength-aware
+L_00000000038a8380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9040_0 .net8 "VNB", 0 0, L_00000000038a8380; 1 drivers, strength-aware
+L_00000000038a7ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e8640_0 .net8 "VPB", 0 0, L_00000000038a7ac0; 1 drivers, strength-aware
+L_00000000038a84d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e92c0_0 .net8 "VPWR", 0 0, L_00000000038a84d0; 1 drivers, strength-aware
+v00000000035e8d20_0 .net "X", 0 0, L_0000000003910100; alias, 1 drivers
+v00000000035e86e0_0 .net "buf0_out_X", 0 0, L_0000000003911c90; 1 drivers
+S_00000000028184b0 .scope module, "sky130_fd_sc_hd__clkinv_1" "sky130_fd_sc_hd__clkinv_1" 4 18836;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003570df8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e9900_0 .net "A", 0 0, o0000000003570df8; 0 drivers
+L_00000000038a83f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9d60_0 .net8 "VGND", 0 0, L_00000000038a83f0; 1 drivers, strength-aware
+L_00000000038a7c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9220_0 .net8 "VNB", 0 0, L_00000000038a7c10; 1 drivers, strength-aware
+L_00000000038a7c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e9360_0 .net8 "VPB", 0 0, L_00000000038a7c80; 1 drivers, strength-aware
+L_00000000038a7cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e97c0_0 .net8 "VPWR", 0 0, L_00000000038a7cf0; 1 drivers, strength-aware
+v00000000035e9e00_0 .net "Y", 0 0, L_0000000003910250; 1 drivers
+S_00000000034e13b0 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18850, 4 18530 1, S_00000000028184b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039116e0 .functor NOT 1, o0000000003570df8, C4<0>, C4<0>, C4<0>;
+L_0000000003910250 .functor BUF 1, L_00000000039116e0, C4<0>, C4<0>, C4<0>;
+v00000000035e8140_0 .net "A", 0 0, o0000000003570df8; alias, 0 drivers
+L_00000000038a7dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9720_0 .net8 "VGND", 0 0, L_00000000038a7dd0; 1 drivers, strength-aware
+L_00000000038a7e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ea4e0_0 .net8 "VNB", 0 0, L_00000000038a7e40; 1 drivers, strength-aware
+L_00000000038a8000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e8a00_0 .net8 "VPB", 0 0, L_00000000038a8000; 1 drivers, strength-aware
+L_00000000038a8cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e95e0_0 .net8 "VPWR", 0 0, L_00000000038a8cb0; 1 drivers, strength-aware
+v00000000035e8780_0 .net "Y", 0 0, L_0000000003910250; alias, 1 drivers
+v00000000035e8dc0_0 .net "not0_out_Y", 0 0, L_00000000039116e0; 1 drivers
+S_0000000002819530 .scope module, "sky130_fd_sc_hd__clkinv_16" "sky130_fd_sc_hd__clkinv_16" 4 18936;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o00000000035710c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e81e0_0 .net "A", 0 0, o00000000035710c8; 0 drivers
+L_00000000038a7eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9860_0 .net8 "VGND", 0 0, L_00000000038a7eb0; 1 drivers, strength-aware
+L_00000000038a80e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8b40_0 .net8 "VNB", 0 0, L_00000000038a80e0; 1 drivers, strength-aware
+L_00000000038a8150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e99a0_0 .net8 "VPB", 0 0, L_00000000038a8150; 1 drivers, strength-aware
+L_00000000038a82a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e9a40_0 .net8 "VPWR", 0 0, L_00000000038a82a0; 1 drivers, strength-aware
+v00000000035ea760_0 .net "Y", 0 0, L_0000000003910800; 1 drivers
+S_00000000034e5430 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18950, 4 18530 1, S_0000000002819530;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910720 .functor NOT 1, o00000000035710c8, C4<0>, C4<0>, C4<0>;
+L_0000000003910800 .functor BUF 1, L_0000000003910720, C4<0>, C4<0>, C4<0>;
+v00000000035e8fa0_0 .net "A", 0 0, o00000000035710c8; alias, 0 drivers
+L_00000000038a9490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ea120_0 .net8 "VGND", 0 0, L_00000000038a9490; 1 drivers, strength-aware
+L_00000000038a9340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e90e0_0 .net8 "VNB", 0 0, L_00000000038a9340; 1 drivers, strength-aware
+L_00000000038aa300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e9400_0 .net8 "VPB", 0 0, L_00000000038aa300; 1 drivers, strength-aware
+L_00000000038a93b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e94a0_0 .net8 "VPWR", 0 0, L_00000000038a93b0; 1 drivers, strength-aware
+v00000000035e9680_0 .net "Y", 0 0, L_0000000003910800; alias, 1 drivers
+v00000000035e8820_0 .net "not0_out_Y", 0 0, L_0000000003910720; 1 drivers
+S_00000000028193b0 .scope module, "sky130_fd_sc_hd__clkinv_2" "sky130_fd_sc_hd__clkinv_2" 4 18242;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003571398 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035e9ea0_0 .net "A", 0 0, o0000000003571398; 0 drivers
+L_00000000038aa840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8960_0 .net8 "VGND", 0 0, L_00000000038aa840; 1 drivers, strength-aware
+L_00000000038aa5a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ea080_0 .net8 "VNB", 0 0, L_00000000038aa5a0; 1 drivers, strength-aware
+L_00000000038a9500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e8c80_0 .net8 "VPB", 0 0, L_00000000038a9500; 1 drivers, strength-aware
+L_00000000038aaae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea1c0_0 .net8 "VPWR", 0 0, L_00000000038aaae0; 1 drivers, strength-aware
+v00000000035ea260_0 .net "Y", 0 0, L_0000000003910950; 1 drivers
+S_00000000034e1530 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18256, 4 18530 1, S_00000000028193b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910870 .functor NOT 1, o0000000003571398, C4<0>, C4<0>, C4<0>;
+L_0000000003910950 .functor BUF 1, L_0000000003910870, C4<0>, C4<0>, C4<0>;
+v00000000035e88c0_0 .net "A", 0 0, o0000000003571398; alias, 0 drivers
+L_00000000038a9260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e8280_0 .net8 "VGND", 0 0, L_00000000038a9260; 1 drivers, strength-aware
+L_00000000038aa8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035e9cc0_0 .net8 "VNB", 0 0, L_00000000038aa8b0; 1 drivers, strength-aware
+L_00000000038a9f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e8460_0 .net8 "VPB", 0 0, L_00000000038a9f10; 1 drivers, strength-aware
+L_00000000038aa220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035e9ae0_0 .net8 "VPWR", 0 0, L_00000000038aa220; 1 drivers, strength-aware
+v00000000035e85a0_0 .net "Y", 0 0, L_0000000003910950; alias, 1 drivers
+v00000000035e9b80_0 .net "not0_out_Y", 0 0, L_0000000003910870; 1 drivers
+S_00000000028199b0 .scope module, "sky130_fd_sc_hd__clkinv_4" "sky130_fd_sc_hd__clkinv_4" 4 18636;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003571668 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035eb2a0_0 .net "A", 0 0, o0000000003571668; 0 drivers
+L_00000000038a96c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ead00_0 .net8 "VGND", 0 0, L_00000000038a96c0; 1 drivers, strength-aware
+L_00000000038a98f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ebd40_0 .net8 "VNB", 0 0, L_00000000038a98f0; 1 drivers, strength-aware
+L_00000000038a9b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eae40_0 .net8 "VPB", 0 0, L_00000000038a9b20; 1 drivers, strength-aware
+L_00000000038aa3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ebde0_0 .net8 "VPWR", 0 0, L_00000000038aa3e0; 1 drivers, strength-aware
+v00000000035eb020_0 .net "Y", 0 0, L_0000000003910a30; 1 drivers
+S_00000000034e16b0 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18650, 4 18530 1, S_00000000028199b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911750 .functor NOT 1, o0000000003571668, C4<0>, C4<0>, C4<0>;
+L_0000000003910a30 .functor BUF 1, L_0000000003911750, C4<0>, C4<0>, C4<0>;
+v00000000035ea300_0 .net "A", 0 0, o0000000003571668; alias, 0 drivers
+L_00000000038a9ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ea3a0_0 .net8 "VGND", 0 0, L_00000000038a9ff0; 1 drivers, strength-aware
+L_00000000038a9880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ea440_0 .net8 "VNB", 0 0, L_00000000038a9880; 1 drivers, strength-aware
+L_00000000038a9a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea580_0 .net8 "VPB", 0 0, L_00000000038a9a40; 1 drivers, strength-aware
+L_00000000038a92d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea620_0 .net8 "VPWR", 0 0, L_00000000038a92d0; 1 drivers, strength-aware
+v00000000035ec7e0_0 .net "Y", 0 0, L_0000000003910a30; alias, 1 drivers
+v00000000035eab20_0 .net "not0_out_Y", 0 0, L_0000000003911750; 1 drivers
+S_0000000002818330 .scope module, "sky130_fd_sc_hd__clkinv_8" "sky130_fd_sc_hd__clkinv_8" 4 18736;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003571938 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035eaf80_0 .net "A", 0 0, o0000000003571938; 0 drivers
+L_00000000038aa370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec2e0_0 .net8 "VGND", 0 0, L_00000000038aa370; 1 drivers, strength-aware
+L_00000000038aa6f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec920_0 .net8 "VNB", 0 0, L_00000000038aa6f0; 1 drivers, strength-aware
+L_00000000038aab50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eb8e0_0 .net8 "VPB", 0 0, L_00000000038aab50; 1 drivers, strength-aware
+L_00000000038aa290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ec240_0 .net8 "VPWR", 0 0, L_00000000038aa290; 1 drivers, strength-aware
+v00000000035eb520_0 .net "Y", 0 0, L_0000000003910bf0; 1 drivers
+S_00000000034e4cb0 .scope module, "base" "sky130_fd_sc_hd__clkinv" 4 18750, 4 18530 1, S_0000000002818330;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910b80 .functor NOT 1, o0000000003571938, C4<0>, C4<0>, C4<0>;
+L_0000000003910bf0 .functor BUF 1, L_0000000003910b80, C4<0>, C4<0>, C4<0>;
+v00000000035eada0_0 .net "A", 0 0, o0000000003571938; alias, 0 drivers
+L_00000000038a9b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eac60_0 .net8 "VGND", 0 0, L_00000000038a9b90; 1 drivers, strength-aware
+L_00000000038aa140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eb660_0 .net8 "VNB", 0 0, L_00000000038aa140; 1 drivers, strength-aware
+L_00000000038aa450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eb3e0_0 .net8 "VPB", 0 0, L_00000000038aa450; 1 drivers, strength-aware
+L_00000000038a9d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eaee0_0 .net8 "VPWR", 0 0, L_00000000038a9d50; 1 drivers, strength-aware
+v00000000035eb480_0 .net "Y", 0 0, L_0000000003910bf0; alias, 1 drivers
+v00000000035ea9e0_0 .net "not0_out_Y", 0 0, L_0000000003910b80; 1 drivers
+S_00000000028196b0 .scope module, "sky130_fd_sc_hd__clkinvlp_2" "sky130_fd_sc_hd__clkinvlp_2" 4 87943;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003571c08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035eb200_0 .net "A", 0 0, o0000000003571c08; 0 drivers
+L_00000000038a9730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ecb00_0 .net8 "VGND", 0 0, L_00000000038a9730; 1 drivers, strength-aware
+L_00000000038a9570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eb700_0 .net8 "VNB", 0 0, L_00000000038a9570; 1 drivers, strength-aware
+L_00000000038aa4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eabc0_0 .net8 "VPB", 0 0, L_00000000038aa4c0; 1 drivers, strength-aware
+L_00000000038aa920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ecce0_0 .net8 "VPWR", 0 0, L_00000000038aa920; 1 drivers, strength-aware
+v00000000035ebac0_0 .net "Y", 0 0, L_00000000039117c0; 1 drivers
+S_00000000034e1b30 .scope module, "base" "sky130_fd_sc_hd__clkinvlp" 4 87957, 4 87837 1, S_00000000028196b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003910f00 .functor NOT 1, o0000000003571c08, C4<0>, C4<0>, C4<0>;
+L_00000000039117c0 .functor BUF 1, L_0000000003910f00, C4<0>, C4<0>, C4<0>;
+v00000000035eb0c0_0 .net "A", 0 0, o0000000003571c08; alias, 0 drivers
+L_00000000038a9ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eb340_0 .net8 "VGND", 0 0, L_00000000038a9ea0; 1 drivers, strength-aware
+L_00000000038a9420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ecd80_0 .net8 "VNB", 0 0, L_00000000038a9420; 1 drivers, strength-aware
+L_00000000038aa060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eb160_0 .net8 "VPB", 0 0, L_00000000038aa060; 1 drivers, strength-aware
+L_00000000038a9dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eb5c0_0 .net8 "VPWR", 0 0, L_00000000038a9dc0; 1 drivers, strength-aware
+v00000000035ec060_0 .net "Y", 0 0, L_00000000039117c0; alias, 1 drivers
+v00000000035ebb60_0 .net "not0_out_Y", 0 0, L_0000000003910f00; 1 drivers
+S_0000000002819cb0 .scope module, "sky130_fd_sc_hd__clkinvlp_4" "sky130_fd_sc_hd__clkinvlp_4" 4 88043;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003571ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ec880_0 .net "A", 0 0, o0000000003571ed8; 0 drivers
+L_00000000038a95e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec380_0 .net8 "VGND", 0 0, L_00000000038a95e0; 1 drivers, strength-aware
+L_00000000038a9650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ebe80_0 .net8 "VNB", 0 0, L_00000000038a9650; 1 drivers, strength-aware
+L_00000000038aac30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ecba0_0 .net8 "VPB", 0 0, L_00000000038aac30; 1 drivers, strength-aware
+L_00000000038a90a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ebf20_0 .net8 "VPWR", 0 0, L_00000000038a90a0; 1 drivers, strength-aware
+v00000000035ebfc0_0 .net "Y", 0 0, L_00000000039118a0; 1 drivers
+S_00000000034e4fb0 .scope module, "base" "sky130_fd_sc_hd__clkinvlp" 4 88057, 4 87837 1, S_0000000002819cb0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003911830 .functor NOT 1, o0000000003571ed8, C4<0>, C4<0>, C4<0>;
+L_00000000039118a0 .functor BUF 1, L_0000000003911830, C4<0>, C4<0>, C4<0>;
+v00000000035ec100_0 .net "A", 0 0, o0000000003571ed8; alias, 0 drivers
+L_00000000038a9960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eb7a0_0 .net8 "VGND", 0 0, L_00000000038a9960; 1 drivers, strength-aware
+L_00000000038aa760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035eb840_0 .net8 "VNB", 0 0, L_00000000038aa760; 1 drivers, strength-aware
+L_00000000038aa1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ebca0_0 .net8 "VPB", 0 0, L_00000000038aa1b0; 1 drivers, strength-aware
+L_00000000038a9110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eb980_0 .net8 "VPWR", 0 0, L_00000000038a9110; 1 drivers, strength-aware
+v00000000035eba20_0 .net "Y", 0 0, L_00000000039118a0; alias, 1 drivers
+v00000000035ebc00_0 .net "not0_out_Y", 0 0, L_0000000003911830; 1 drivers
+S_00000000028187b0 .scope module, "sky130_fd_sc_hd__decap_12" "sky130_fd_sc_hd__decap_12" 4 83287;
+ .timescale -9 -12;
+L_00000000038a99d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec4c0_0 .net8 "VGND", 0 0, L_00000000038a99d0; 1 drivers, strength-aware
+L_00000000038aa530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ece20_0 .net8 "VNB", 0 0, L_00000000038aa530; 1 drivers, strength-aware
+L_00000000038a9180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ec560_0 .net8 "VPB", 0 0, L_00000000038a9180; 1 drivers, strength-aware
+L_00000000038aa610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ec600_0 .net8 "VPWR", 0 0, L_00000000038aa610; 1 drivers, strength-aware
+S_00000000034e3ab0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83294, 4 82949 1, S_00000000028187b0;
+ .timescale -9 -12;
+L_00000000038aa0d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec9c0_0 .net8 "VGND", 0 0, L_00000000038aa0d0; 1 drivers, strength-aware
+L_00000000038aabc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ecec0_0 .net8 "VNB", 0 0, L_00000000038aabc0; 1 drivers, strength-aware
+L_00000000038a97a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ec1a0_0 .net8 "VPB", 0 0, L_00000000038a97a0; 1 drivers, strength-aware
+L_00000000038a9f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ec420_0 .net8 "VPWR", 0 0, L_00000000038a9f80; 1 drivers, strength-aware
+S_0000000002819830 .scope module, "sky130_fd_sc_hd__decap_3" "sky130_fd_sc_hd__decap_3" 4 83035;
+ .timescale -9 -12;
+L_00000000038a9ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ecc40_0 .net8 "VGND", 0 0, L_00000000038a9ab0; 1 drivers, strength-aware
+L_00000000038a91f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ecf60_0 .net8 "VNB", 0 0, L_00000000038a91f0; 1 drivers, strength-aware
+L_00000000038a9810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ea940_0 .net8 "VPB", 0 0, L_00000000038a9810; 1 drivers, strength-aware
+L_00000000038a9c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ad900_0 .net8 "VPWR", 0 0, L_00000000038a9c00; 1 drivers, strength-aware
+S_00000000034e58b0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83042, 4 82949 1, S_0000000002819830;
+ .timescale -9 -12;
+L_00000000038a9c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec6a0_0 .net8 "VGND", 0 0, L_00000000038a9c70; 1 drivers, strength-aware
+L_00000000038aa680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ec740_0 .net8 "VNB", 0 0, L_00000000038aa680; 1 drivers, strength-aware
+L_00000000038aa990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eca60_0 .net8 "VPB", 0 0, L_00000000038aa990; 1 drivers, strength-aware
+L_00000000038aa7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035eaa80_0 .net8 "VPWR", 0 0, L_00000000038aa7d0; 1 drivers, strength-aware
+S_0000000002819b30 .scope module, "sky130_fd_sc_hd__decap_4" "sky130_fd_sc_hd__decap_4" 4 83119;
+ .timescale -9 -12;
+L_00000000038a9ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ad360_0 .net8 "VGND", 0 0, L_00000000038a9ce0; 1 drivers, strength-aware
+L_00000000038aaa70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ac500_0 .net8 "VNB", 0 0, L_00000000038aaa70; 1 drivers, strength-aware
+L_00000000038aaa00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035add60_0 .net8 "VPB", 0 0, L_00000000038aaa00; 1 drivers, strength-aware
+L_00000000038a9e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ac280_0 .net8 "VPWR", 0 0, L_00000000038a9e30; 1 drivers, strength-aware
+S_00000000034e1cb0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83126, 4 82949 1, S_0000000002819b30;
+ .timescale -9 -12;
+L_00000000038ab020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ae440_0 .net8 "VGND", 0 0, L_00000000038ab020; 1 drivers, strength-aware
+L_00000000038ac750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ace60_0 .net8 "VNB", 0 0, L_00000000038ac750; 1 drivers, strength-aware
+L_00000000038ab480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ac460_0 .net8 "VPB", 0 0, L_00000000038ab480; 1 drivers, strength-aware
+L_00000000038ac4b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035acaa0_0 .net8 "VPWR", 0 0, L_00000000038ac4b0; 1 drivers, strength-aware
+S_0000000002818c30 .scope module, "sky130_fd_sc_hd__decap_6" "sky130_fd_sc_hd__decap_6" 4 83203;
+ .timescale -9 -12;
+L_00000000038abb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ad400_0 .net8 "VGND", 0 0, L_00000000038abb80; 1 drivers, strength-aware
+L_00000000038abf00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ae1c0_0 .net8 "VNB", 0 0, L_00000000038abf00; 1 drivers, strength-aware
+L_00000000038abbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ae260_0 .net8 "VPB", 0 0, L_00000000038abbf0; 1 drivers, strength-aware
+L_00000000038ab3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035adc20_0 .net8 "VPWR", 0 0, L_00000000038ab3a0; 1 drivers, strength-aware
+S_00000000034e4b30 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83210, 4 82949 1, S_0000000002818c30;
+ .timescale -9 -12;
+L_00000000038abd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035acfa0_0 .net8 "VGND", 0 0, L_00000000038abd40; 1 drivers, strength-aware
+L_00000000038ac1a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035acb40_0 .net8 "VNB", 0 0, L_00000000038ac1a0; 1 drivers, strength-aware
+L_00000000038aad10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ad5e0_0 .net8 "VPB", 0 0, L_00000000038aad10; 1 drivers, strength-aware
+L_00000000038aae60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ac5a0_0 .net8 "VPWR", 0 0, L_00000000038aae60; 1 drivers, strength-aware
+S_0000000002818db0 .scope module, "sky130_fd_sc_hd__decap_8" "sky130_fd_sc_hd__decap_8" 4 83371;
+ .timescale -9 -12;
+L_00000000038ac7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ad180_0 .net8 "VGND", 0 0, L_00000000038ac7c0; 1 drivers, strength-aware
+L_00000000038abf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ac320_0 .net8 "VNB", 0 0, L_00000000038abf70; 1 drivers, strength-aware
+L_00000000038ac210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ac780_0 .net8 "VPB", 0 0, L_00000000038ac210; 1 drivers, strength-aware
+L_00000000038ab090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ade00_0 .net8 "VPWR", 0 0, L_00000000038ab090; 1 drivers, strength-aware
+S_00000000034e5eb0 .scope module, "base" "sky130_fd_sc_hd__decap" 4 83378, 4 82949 1, S_0000000002818db0;
+ .timescale -9 -12;
+L_00000000038ac440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ad540_0 .net8 "VGND", 0 0, L_00000000038ac440; 1 drivers, strength-aware
+L_00000000038ac280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ac640_0 .net8 "VNB", 0 0, L_00000000038ac280; 1 drivers, strength-aware
+L_00000000038ab100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035acbe0_0 .net8 "VPB", 0 0, L_00000000038ab100; 1 drivers, strength-aware
+L_00000000038ac6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ac3c0_0 .net8 "VPWR", 0 0, L_00000000038ac6e0; 1 drivers, strength-aware
+S_0000000002818630 .scope module, "sky130_fd_sc_hd__dfbbn_1" "sky130_fd_sc_hd__dfbbn_1" 4 64432;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK_N"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003572958 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ad2c0_0 .net "CLK_N", 0 0, o0000000003572958; 0 drivers
+o00000000035729b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035adcc0_0 .net "D", 0 0, o00000000035729b8; 0 drivers
+v00000000035adfe0_0 .net "Q", 0 0, L_00000000039519b0; 1 drivers
+v00000000035adb80_0 .net "Q_N", 0 0, L_0000000003950670; 1 drivers
+o0000000003572aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ae120_0 .net "RESET_B", 0 0, o0000000003572aa8; 0 drivers
+o0000000003572b38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ae300_0 .net "SET_B", 0 0, o0000000003572b38; 0 drivers
+L_00000000038aaed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ae3a0_0 .net8 "VGND", 0 0, L_00000000038aaed0; 1 drivers, strength-aware
+L_00000000038ac520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ae4e0_0 .net8 "VNB", 0 0, L_00000000038ac520; 1 drivers, strength-aware
+L_00000000038abb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ae580_0 .net8 "VPB", 0 0, L_00000000038abb10; 1 drivers, strength-aware
+L_00000000038abe20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ae620_0 .net8 "VPWR", 0 0, L_00000000038abe20; 1 drivers, strength-aware
+S_00000000034e5130 .scope module, "base" "sky130_fd_sc_hd__dfbbn" 4 64454, 4 64795 1, S_0000000002818630;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK_N"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003572ad8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950280 .functor NOT 1, o0000000003572ad8, C4<0>, C4<0>, C4<0>;
+o0000000003572b68 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950600 .functor NOT 1, o0000000003572b68, C4<0>, C4<0>, C4<0>;
+o0000000003572988 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951a20 .functor NOT 1, o0000000003572988, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N", 7, 2
+ ,"?01b??100"
+ ,"00*???100"
+ ,"?1?b??101"
+ ,"1*0???101"
+ ,"11?n??101"
+ ,"0?1n??100"
+ ,"1x?n??101"
+ ,"0?xn??100"
+ ,"?0?r0?100"
+ ,"??0r1?101"
+ ,"00?p0?100"
+ ,"1?0p1?101"
+ ,"10?x0?10x"
+ ,"0?0x1?10x"
+ ,"?00n??10-"
+ ,"?00?*?10-"
+ ,"???????*x";
+o00000000035729e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038abfe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ab2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003950ad0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000003950600, L_0000000003950280, L_0000000003951a20, o00000000035729e8, v00000000035adae0_0, L_00000000038abfe0, L_00000000038ab2c0;
+L_0000000003950520 .functor AND 1, L_000000000380ada0, L_000000000380b7a0, C4<1>, C4<1>;
+L_0000000003951470 .functor AND 1, L_000000000380ada0, L_000000000380a940, C4<1>, C4<1>;
+L_0000000003950130 .functor AND 1, L_0000000003950520, L_0000000003951470, C4<1>, C4<1>;
+L_00000000039519b0 .functor BUF 1, L_0000000003950ad0, C4<0>, C4<0>, C4<0>;
+L_0000000003950670 .functor NOT 1, L_0000000003950ad0, C4<0>, C4<0>, C4<0>;
+v00000000035acc80_0 .net "CLK", 0 0, L_0000000003951a20; 1 drivers
+v00000000035ad040_0 .net "CLK_N", 0 0, o0000000003572958; alias, 0 drivers
+v00000000035ac6e0_0 .net "CLK_N_delayed", 0 0, o0000000003572988; 0 drivers
+v00000000035ad9a0_0 .net "D", 0 0, o00000000035729b8; alias, 0 drivers
+v00000000035acd20_0 .net "D_delayed", 0 0, o00000000035729e8; 0 drivers
+v00000000035ad7c0_0 .net "Q", 0 0, L_00000000039519b0; alias, 1 drivers
+v00000000035ac140_0 .net "Q_N", 0 0, L_0000000003950670; alias, 1 drivers
+v00000000035ae800_0 .net "RESET", 0 0, L_0000000003950280; 1 drivers
+v00000000035ac820_0 .net "RESET_B", 0 0, o0000000003572aa8; alias, 0 drivers
+v00000000035ae8a0_0 .net "RESET_B_delayed", 0 0, o0000000003572ad8; 0 drivers
+v00000000035acdc0_0 .net "SET", 0 0, L_0000000003950600; 1 drivers
+v00000000035ac1e0_0 .net "SET_B", 0 0, o0000000003572b38; alias, 0 drivers
+v00000000035ae6c0_0 .net "SET_B_delayed", 0 0, o0000000003572b68; 0 drivers
+v00000000035ad860_0 .net8 "VGND", 0 0, L_00000000038ab2c0; 1 drivers, strength-aware
+L_00000000038ab4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035ac8c0_0 .net8 "VNB", 0 0, L_00000000038ab4f0; 1 drivers, strength-aware
+L_00000000038ab720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035adea0_0 .net8 "VPB", 0 0, L_00000000038ab720; 1 drivers, strength-aware
+v00000000035ac960_0 .net8 "VPWR", 0 0, L_00000000038abfe0; 1 drivers, strength-aware
+v00000000035adf40_0 .net *"_s10", 0 0, L_000000000380b7a0; 1 drivers
+L_00000000039700f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035aca00_0 .net/2u *"_s14", 0 0, L_00000000039700f8; 1 drivers
+v00000000035ad720_0 .net *"_s16", 0 0, L_000000000380a940; 1 drivers
+L_0000000003970068 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035ae080_0 .net/2u *"_s4", 0 0, L_0000000003970068; 1 drivers
+L_00000000039700b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035acf00_0 .net/2u *"_s8", 0 0, L_00000000039700b0; 1 drivers
+v00000000035ad680_0 .net "awake", 0 0, L_000000000380ada0; 1 drivers
+v00000000035ad0e0_0 .net "buf_Q", 0 0, L_0000000003950ad0; 1 drivers
+v00000000035ada40_0 .net "cond0", 0 0, L_0000000003950520; 1 drivers
+v00000000035ad4a0_0 .net "cond1", 0 0, L_0000000003951470; 1 drivers
+v00000000035ad220_0 .net "condb", 0 0, L_0000000003950130; 1 drivers
+v00000000035adae0_0 .var "notifier", 0 0;
+L_000000000380ada0 .cmp/eeq 1, L_00000000038abfe0, L_0000000003970068;
+L_000000000380b7a0 .cmp/eeq 1, o0000000003572ad8, L_00000000039700b0;
+L_000000000380a940 .cmp/eeq 1, o0000000003572b68, L_00000000039700f8;
+S_0000000002817eb0 .scope module, "sky130_fd_sc_hd__dfbbn_2" "sky130_fd_sc_hd__dfbbn_2" 4 64942;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK_N"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003573198 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f6380_0 .net "CLK_N", 0 0, o0000000003573198; 0 drivers
+o00000000035731f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f5200_0 .net "D", 0 0, o00000000035731f8; 0 drivers
+v00000000035f6600_0 .net "Q", 0 0, L_00000000039508a0; 1 drivers
+v00000000035f5980_0 .net "Q_N", 0 0, L_0000000003950750; 1 drivers
+o00000000035732e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f4c60_0 .net "RESET_B", 0 0, o00000000035732e8; 0 drivers
+o0000000003573378 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f58e0_0 .net "SET_B", 0 0, o0000000003573378; 0 drivers
+L_00000000038abe90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f5340_0 .net8 "VGND", 0 0, L_00000000038abe90; 1 drivers, strength-aware
+L_00000000038ab170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f66a0_0 .net8 "VNB", 0 0, L_00000000038ab170; 1 drivers, strength-aware
+L_00000000038ac2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f6420_0 .net8 "VPB", 0 0, L_00000000038ac2f0; 1 drivers, strength-aware
+L_00000000038ab1e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f5a20_0 .net8 "VPWR", 0 0, L_00000000038ab1e0; 1 drivers, strength-aware
+S_00000000034e34b0 .scope module, "base" "sky130_fd_sc_hd__dfbbn" 4 64964, 4 64795 1, S_0000000002817eb0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK_N"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003573318 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950830 .functor NOT 1, o0000000003573318, C4<0>, C4<0>, C4<0>;
+o00000000035733a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039514e0 .functor NOT 1, o00000000035733a8, C4<0>, C4<0>, C4<0>;
+o00000000035731c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039515c0 .functor NOT 1, o00000000035731c8, C4<0>, C4<0>, C4<0>;
+o0000000003573228 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ac130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ac050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951a90 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_00000000039514e0, L_0000000003950830, L_00000000039515c0, o0000000003573228, v00000000035f5e80_0, L_00000000038ac130, L_00000000038ac050;
+L_00000000039501a0 .functor AND 1, L_000000000380ac60, L_000000000380aee0, C4<1>, C4<1>;
+L_0000000003950fa0 .functor AND 1, L_000000000380ac60, L_000000000380bc00, C4<1>, C4<1>;
+L_00000000039506e0 .functor AND 1, L_00000000039501a0, L_0000000003950fa0, C4<1>, C4<1>;
+L_00000000039508a0 .functor BUF 1, L_0000000003951a90, C4<0>, C4<0>, C4<0>;
+L_0000000003950750 .functor NOT 1, L_0000000003951a90, C4<0>, C4<0>, C4<0>;
+v00000000035ae760_0 .net "CLK", 0 0, L_00000000039515c0; 1 drivers
+v00000000035f6240_0 .net "CLK_N", 0 0, o0000000003573198; alias, 0 drivers
+v00000000035f6920_0 .net "CLK_N_delayed", 0 0, o00000000035731c8; 0 drivers
+v00000000035f5480_0 .net "D", 0 0, o00000000035731f8; alias, 0 drivers
+v00000000035f4ee0_0 .net "D_delayed", 0 0, o0000000003573228; 0 drivers
+v00000000035f5520_0 .net "Q", 0 0, L_00000000039508a0; alias, 1 drivers
+v00000000035f4a80_0 .net "Q_N", 0 0, L_0000000003950750; alias, 1 drivers
+v00000000035f5020_0 .net "RESET", 0 0, L_0000000003950830; 1 drivers
+v00000000035f6c40_0 .net "RESET_B", 0 0, o00000000035732e8; alias, 0 drivers
+v00000000035f5660_0 .net "RESET_B_delayed", 0 0, o0000000003573318; 0 drivers
+v00000000035f49e0_0 .net "SET", 0 0, L_00000000039514e0; 1 drivers
+v00000000035f6100_0 .net "SET_B", 0 0, o0000000003573378; alias, 0 drivers
+v00000000035f52a0_0 .net "SET_B_delayed", 0 0, o00000000035733a8; 0 drivers
+v00000000035f5b60_0 .net8 "VGND", 0 0, L_00000000038ac050; 1 drivers, strength-aware
+L_00000000038ac0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f4b20_0 .net8 "VNB", 0 0, L_00000000038ac0c0; 1 drivers, strength-aware
+L_00000000038ac360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f6b00_0 .net8 "VPB", 0 0, L_00000000038ac360; 1 drivers, strength-aware
+v00000000035f6560_0 .net8 "VPWR", 0 0, L_00000000038ac130; 1 drivers, strength-aware
+v00000000035f4bc0_0 .net *"_s10", 0 0, L_000000000380aee0; 1 drivers
+L_00000000039701d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f61a0_0 .net/2u *"_s14", 0 0, L_00000000039701d0; 1 drivers
+v00000000035f57a0_0 .net *"_s16", 0 0, L_000000000380bc00; 1 drivers
+L_0000000003970140 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f5160_0 .net/2u *"_s4", 0 0, L_0000000003970140; 1 drivers
+L_0000000003970188 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f5de0_0 .net/2u *"_s8", 0 0, L_0000000003970188; 1 drivers
+v00000000035f50c0_0 .net "awake", 0 0, L_000000000380ac60; 1 drivers
+v00000000035f5ac0_0 .net "buf_Q", 0 0, L_0000000003951a90; 1 drivers
+v00000000035f5c00_0 .net "cond0", 0 0, L_00000000039501a0; 1 drivers
+v00000000035f69c0_0 .net "cond1", 0 0, L_0000000003950fa0; 1 drivers
+v00000000035f62e0_0 .net "condb", 0 0, L_00000000039506e0; 1 drivers
+v00000000035f5e80_0 .var "notifier", 0 0;
+L_000000000380ac60 .cmp/eeq 1, L_00000000038ac130, L_0000000003970140;
+L_000000000380aee0 .cmp/eeq 1, o0000000003573318, L_0000000003970188;
+L_000000000380bc00 .cmp/eeq 1, o00000000035733a8, L_00000000039701d0;
+S_0000000002818f30 .scope module, "sky130_fd_sc_hd__dfbbp_1" "sky130_fd_sc_hd__dfbbp_1" 4 44024;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o00000000035739a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f8d60_0 .net "CLK", 0 0, o00000000035739a8; 0 drivers
+o0000000003573a08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f76e0_0 .net "D", 0 0, o0000000003573a08; 0 drivers
+v00000000035f8180_0 .net "Q", 0 0, L_0000000003950910; 1 drivers
+v00000000035f7780_0 .net "Q_N", 0 0, L_0000000003951390; 1 drivers
+o0000000003573af8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f8040_0 .net "RESET_B", 0 0, o0000000003573af8; 0 drivers
+o0000000003573b88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f80e0_0 .net "SET_B", 0 0, o0000000003573b88; 0 drivers
+L_00000000038ab870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f7d20_0 .net8 "VGND", 0 0, L_00000000038ab870; 1 drivers, strength-aware
+L_00000000038ac590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f78c0_0 .net8 "VNB", 0 0, L_00000000038ac590; 1 drivers, strength-aware
+L_00000000038ab250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f8220_0 .net8 "VPB", 0 0, L_00000000038ab250; 1 drivers, strength-aware
+L_00000000038ab790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f8a40_0 .net8 "VPWR", 0 0, L_00000000038ab790; 1 drivers, strength-aware
+S_00000000034e46b0 .scope module, "base" "sky130_fd_sc_hd__dfbbp" 4 44046, 4 44381 1, S_0000000002818f30;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "CLK"
+ .port_info 4 /INPUT 1 "SET_B"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003573b28 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950590 .functor NOT 1, o0000000003573b28, C4<0>, C4<0>, C4<0>;
+o0000000003573bb8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951010 .functor NOT 1, o0000000003573bb8, C4<0>, C4<0>, C4<0>;
+o00000000035739d8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003573a38 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ac600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ac3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039511d0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000003951010, L_0000000003950590, o00000000035739d8, o0000000003573a38, v00000000035f6f60_0, L_00000000038ac600, L_00000000038ac3d0;
+L_0000000003951b00 .functor AND 1, L_000000000380af80, L_000000000380b2a0, C4<1>, C4<1>;
+L_0000000003951be0 .functor AND 1, L_000000000380af80, L_000000000380b520, C4<1>, C4<1>;
+L_00000000039507c0 .functor AND 1, L_0000000003951b00, L_0000000003951be0, C4<1>, C4<1>;
+L_0000000003950910 .functor BUF 1, L_00000000039511d0, C4<0>, C4<0>, C4<0>;
+L_0000000003951390 .functor NOT 1, L_00000000039511d0, C4<0>, C4<0>, C4<0>;
+v00000000035f5ca0_0 .net "CLK", 0 0, o00000000035739a8; alias, 0 drivers
+v00000000035f4d00_0 .net "CLK_delayed", 0 0, o00000000035739d8; 0 drivers
+v00000000035f7000_0 .net "D", 0 0, o0000000003573a08; alias, 0 drivers
+v00000000035f6740_0 .net "D_delayed", 0 0, o0000000003573a38; 0 drivers
+v00000000035f70a0_0 .net "Q", 0 0, L_0000000003950910; alias, 1 drivers
+v00000000035f64c0_0 .net "Q_N", 0 0, L_0000000003951390; alias, 1 drivers
+v00000000035f53e0_0 .net "RESET", 0 0, L_0000000003950590; 1 drivers
+v00000000035f5d40_0 .net "RESET_B", 0 0, o0000000003573af8; alias, 0 drivers
+v00000000035f5700_0 .net "RESET_B_delayed", 0 0, o0000000003573b28; 0 drivers
+v00000000035f67e0_0 .net "SET", 0 0, L_0000000003951010; 1 drivers
+v00000000035f4da0_0 .net "SET_B", 0 0, o0000000003573b88; alias, 0 drivers
+v00000000035f5840_0 .net "SET_B_delayed", 0 0, o0000000003573bb8; 0 drivers
+v00000000035f5f20_0 .net8 "VGND", 0 0, L_00000000038ac3d0; 1 drivers, strength-aware
+L_00000000038aaf40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f55c0_0 .net8 "VNB", 0 0, L_00000000038aaf40; 1 drivers, strength-aware
+L_00000000038ac830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f5fc0_0 .net8 "VPB", 0 0, L_00000000038ac830; 1 drivers, strength-aware
+v00000000035f6880_0 .net8 "VPWR", 0 0, L_00000000038ac600; 1 drivers, strength-aware
+v00000000035f6ba0_0 .net *"_s10", 0 0, L_000000000380b2a0; 1 drivers
+L_00000000039702a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f4940_0 .net/2u *"_s14", 0 0, L_00000000039702a8; 1 drivers
+v00000000035f6060_0 .net *"_s16", 0 0, L_000000000380b520; 1 drivers
+L_0000000003970218 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f6a60_0 .net/2u *"_s4", 0 0, L_0000000003970218; 1 drivers
+L_0000000003970260 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f4e40_0 .net/2u *"_s8", 0 0, L_0000000003970260; 1 drivers
+v00000000035f6ce0_0 .net "awake", 0 0, L_000000000380af80; 1 drivers
+v00000000035f6d80_0 .net "buf_Q", 0 0, L_00000000039511d0; 1 drivers
+v00000000035f4f80_0 .net "cond0", 0 0, L_0000000003951b00; 1 drivers
+v00000000035f6e20_0 .net "cond1", 0 0, L_0000000003951be0; 1 drivers
+v00000000035f6ec0_0 .net "condb", 0 0, L_00000000039507c0; 1 drivers
+v00000000035f6f60_0 .var "notifier", 0 0;
+L_000000000380af80 .cmp/eeq 1, L_00000000038ac600, L_0000000003970218;
+L_000000000380b2a0 .cmp/eeq 1, o0000000003573b28, L_0000000003970260;
+L_000000000380b520 .cmp/eeq 1, o0000000003573bb8, L_00000000039702a8;
+S_0000000002818030 .scope module, "sky130_fd_sc_hd__dfrbp_1" "sky130_fd_sc_hd__dfrbp_1" 4 15271;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "RESET_B"
+o00000000035741b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f8e00_0 .net "CLK", 0 0, o00000000035741b8; 0 drivers
+o0000000003574218 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f7be0_0 .net "D", 0 0, o0000000003574218; 0 drivers
+v00000000035f82c0_0 .net "Q", 0 0, L_0000000003950980; 1 drivers
+v00000000035f7640_0 .net "Q_N", 0 0, L_0000000003951160; 1 drivers
+o0000000003574308 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f8360_0 .net "RESET_B", 0 0, o0000000003574308; 0 drivers
+L_00000000038ac670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f7f00_0 .net8 "VGND", 0 0, L_00000000038ac670; 1 drivers, strength-aware
+L_00000000038abc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f7a00_0 .net8 "VNB", 0 0, L_00000000038abc60; 1 drivers, strength-aware
+L_00000000038ab9c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f7320_0 .net8 "VPB", 0 0, L_00000000038ab9c0; 1 drivers, strength-aware
+L_00000000038aaca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f8cc0_0 .net8 "VPWR", 0 0, L_00000000038aaca0; 1 drivers, strength-aware
+S_00000000034e5a30 .scope module, "base" "sky130_fd_sc_hd__dfrbp" 4 15291, 4 15138 1, S_0000000002818030;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "RESET_B"
+o0000000003574338 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039503d0 .functor NOT 1, o0000000003574338, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$PR_pp$PG$N", 6, 2
+ ,"?*b0?10-"
+ ,"??_0?10-"
+ ,"??b_?10-"
+ ,"???1?100"
+ ,"?0r??100"
+ ,"?1r0?101"
+ ,"00R??100"
+ ,"11R0?101"
+ ,"00x??100"
+ ,"11x0?101"
+ ,"0?b%?100"
+ ,"0?_x?100"
+ ,"??????*x";
+o0000000003574248 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000035741e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038abdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038aad80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951080 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003574248, o00000000035741e8, L_00000000039503d0, v00000000035f89a0_0, L_00000000038abdb0, L_00000000038aad80;
+o00000000035744e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039502f0 .functor AND 1, o00000000035744e8, L_000000000380b5c0, C4<1>, C4<1>;
+L_0000000003951630 .functor AND 1, o00000000035744e8, L_000000000380bca0, C4<1>, C4<1>;
+L_0000000003950980 .functor BUF 1, L_0000000003951080, C4<0>, C4<0>, C4<0>;
+L_0000000003951160 .functor NOT 1, L_0000000003951080, C4<0>, C4<0>, C4<0>;
+v00000000035f7c80_0 .net "CLK", 0 0, o00000000035741b8; alias, 0 drivers
+v00000000035f9580_0 .net "CLK_delayed", 0 0, o00000000035741e8; 0 drivers
+v00000000035f9300_0 .net "D", 0 0, o0000000003574218; alias, 0 drivers
+v00000000035f7820_0 .net "D_delayed", 0 0, o0000000003574248; 0 drivers
+v00000000035f96c0_0 .net "Q", 0 0, L_0000000003950980; alias, 1 drivers
+v00000000035f8680_0 .net "Q_N", 0 0, L_0000000003951160; alias, 1 drivers
+v00000000035f7dc0_0 .net "RESET", 0 0, L_00000000039503d0; 1 drivers
+v00000000035f9260_0 .net "RESET_B", 0 0, o0000000003574308; alias, 0 drivers
+v00000000035f98a0_0 .net "RESET_B_delayed", 0 0, o0000000003574338; 0 drivers
+v00000000035f8ae0_0 .net8 "VGND", 0 0, L_00000000038aad80; 1 drivers, strength-aware
+L_00000000038aadf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f8ea0_0 .net8 "VNB", 0 0, L_00000000038aadf0; 1 drivers, strength-aware
+L_00000000038ab560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f84a0_0 .net8 "VPB", 0 0, L_00000000038ab560; 1 drivers, strength-aware
+v00000000035f7e60_0 .net8 "VPWR", 0 0, L_00000000038abdb0; 1 drivers, strength-aware
+L_0000000003970338 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f7460_0 .net/2u *"_s10", 0 0, L_0000000003970338; 1 drivers
+v00000000035f8b80_0 .net *"_s12", 0 0, L_000000000380bca0; 1 drivers
+L_00000000039702f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f7960_0 .net/2u *"_s4", 0 0, L_00000000039702f0; 1 drivers
+v00000000035f7b40_0 .net *"_s6", 0 0, L_000000000380b5c0; 1 drivers
+v00000000035f9760_0 .net "awake", 0 0, o00000000035744e8; 0 drivers
+v00000000035f71e0_0 .net "buf_Q", 0 0, L_0000000003951080; 1 drivers
+v00000000035f8c20_0 .net "cond0", 0 0, L_00000000039502f0; 1 drivers
+v00000000035f94e0_0 .net "cond1", 0 0, L_0000000003951630; 1 drivers
+v00000000035f89a0_0 .var "notifier", 0 0;
+L_000000000380b5c0 .cmp/eeq 1, o0000000003574338, L_00000000039702f0;
+L_000000000380bca0 .cmp/eeq 1, o0000000003574308, L_0000000003970338;
+S_00000000028181b0 .scope module, "sky130_fd_sc_hd__dfrbp_2" "sky130_fd_sc_hd__dfrbp_2" 4 15389;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "RESET_B"
+o0000000003574878 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f7140_0 .net "CLK", 0 0, o0000000003574878; 0 drivers
+o00000000035748d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fade0_0 .net "D", 0 0, o00000000035748d8; 0 drivers
+v00000000035f9ee0_0 .net "Q", 0 0, L_00000000039509f0; 1 drivers
+v00000000035fa520_0 .net "Q_N", 0 0, L_00000000039517f0; 1 drivers
+o00000000035749c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fa0c0_0 .net "RESET_B", 0 0, o00000000035749c8; 0 drivers
+L_00000000038aafb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fa2a0_0 .net8 "VGND", 0 0, L_00000000038aafb0; 1 drivers, strength-aware
+L_00000000038ab330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fb240_0 .net8 "VNB", 0 0, L_00000000038ab330; 1 drivers, strength-aware
+L_00000000038ab410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fb7e0_0 .net8 "VPB", 0 0, L_00000000038ab410; 1 drivers, strength-aware
+L_00000000038ab5d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035faa20_0 .net8 "VPWR", 0 0, L_00000000038ab5d0; 1 drivers, strength-aware
+S_00000000034e52b0 .scope module, "base" "sky130_fd_sc_hd__dfrbp" 4 15409, 4 15138 1, S_00000000028181b0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "RESET_B"
+o00000000035749f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950440 .functor NOT 1, o00000000035749f8, C4<0>, C4<0>, C4<0>;
+o0000000003574908 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000035748a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ab8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ab640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003950360 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003574908, o00000000035748a8, L_0000000003950440, v00000000035f9440_0, L_00000000038ab8e0, L_00000000038ab640;
+o0000000003574ba8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951320 .functor AND 1, o0000000003574ba8, L_000000000380b980, C4<1>, C4<1>;
+L_00000000039512b0 .functor AND 1, o0000000003574ba8, L_000000000380bac0, C4<1>, C4<1>;
+L_00000000039509f0 .functor BUF 1, L_0000000003950360, C4<0>, C4<0>, C4<0>;
+L_00000000039517f0 .functor NOT 1, L_0000000003950360, C4<0>, C4<0>, C4<0>;
+v00000000035f87c0_0 .net "CLK", 0 0, o0000000003574878; alias, 0 drivers
+v00000000035f7500_0 .net "CLK_delayed", 0 0, o00000000035748a8; 0 drivers
+v00000000035f7280_0 .net "D", 0 0, o00000000035748d8; alias, 0 drivers
+v00000000035f8f40_0 .net "D_delayed", 0 0, o0000000003574908; 0 drivers
+v00000000035f9800_0 .net "Q", 0 0, L_00000000039509f0; alias, 1 drivers
+v00000000035f8720_0 .net "Q_N", 0 0, L_00000000039517f0; alias, 1 drivers
+v00000000035f9080_0 .net "RESET", 0 0, L_0000000003950440; 1 drivers
+v00000000035f93a0_0 .net "RESET_B", 0 0, o00000000035749c8; alias, 0 drivers
+v00000000035f7aa0_0 .net "RESET_B_delayed", 0 0, o00000000035749f8; 0 drivers
+v00000000035f7fa0_0 .net8 "VGND", 0 0, L_00000000038ab640; 1 drivers, strength-aware
+L_00000000038ab800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f8400_0 .net8 "VNB", 0 0, L_00000000038ab800; 1 drivers, strength-aware
+L_00000000038ab6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f8540_0 .net8 "VPB", 0 0, L_00000000038ab6b0; 1 drivers, strength-aware
+v00000000035f73c0_0 .net8 "VPWR", 0 0, L_00000000038ab8e0; 1 drivers, strength-aware
+L_00000000039703c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f9620_0 .net/2u *"_s10", 0 0, L_00000000039703c8; 1 drivers
+v00000000035f85e0_0 .net *"_s12", 0 0, L_000000000380bac0; 1 drivers
+L_0000000003970380 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f75a0_0 .net/2u *"_s4", 0 0, L_0000000003970380; 1 drivers
+v00000000035f8860_0 .net *"_s6", 0 0, L_000000000380b980; 1 drivers
+v00000000035f8900_0 .net "awake", 0 0, o0000000003574ba8; 0 drivers
+v00000000035f8fe0_0 .net "buf_Q", 0 0, L_0000000003950360; 1 drivers
+v00000000035f9120_0 .net "cond0", 0 0, L_0000000003951320; 1 drivers
+v00000000035f91c0_0 .net "cond1", 0 0, L_00000000039512b0; 1 drivers
+v00000000035f9440_0 .var "notifier", 0 0;
+L_000000000380b980 .cmp/eeq 1, o00000000035749f8, L_0000000003970380;
+L_000000000380bac0 .cmp/eeq 1, o00000000035749c8, L_00000000039703c8;
+S_0000000002819ec0 .scope module, "sky130_fd_sc_hd__dfrtn_1" "sky130_fd_sc_hd__dfrtn_1" 4 94319;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003574f38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fb380_0 .net "CLK_N", 0 0, o0000000003574f38; 0 drivers
+o0000000003574f98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fb1a0_0 .net "D", 0 0, o0000000003574f98; 0 drivers
+v00000000035f9da0_0 .net "Q", 0 0, L_0000000003951400; 1 drivers
+o0000000003575058 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f99e0_0 .net "RESET_B", 0 0, o0000000003575058; 0 drivers
+L_00000000038ab950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fbb00_0 .net8 "VGND", 0 0, L_00000000038ab950; 1 drivers, strength-aware
+L_00000000038abcd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fbba0_0 .net8 "VNB", 0 0, L_00000000038abcd0; 1 drivers, strength-aware
+L_00000000038aba30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f9b20_0 .net8 "VPB", 0 0, L_00000000038aba30; 1 drivers, strength-aware
+L_00000000038abaa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fb4c0_0 .net8 "VPWR", 0 0, L_00000000038abaa0; 1 drivers, strength-aware
+S_00000000034e1fb0 .scope module, "base" "sky130_fd_sc_hd__dfrtn" 4 94337, 4 94652 1, S_0000000002819ec0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003575088 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951b70 .functor NOT 1, o0000000003575088, C4<0>, C4<0>, C4<0>;
+o0000000003574f68 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950a60 .functor NOT 1, o0000000003574f68, C4<0>, C4<0>, C4<0>;
+o0000000003574fc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038acd70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ad710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951240 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003574fc8, L_0000000003950a60, L_0000000003951b70, v00000000035f9d00_0, L_00000000038acd70, L_00000000038ad710;
+L_0000000003951cc0 .functor AND 1, L_000000000380de60, L_000000000380f620, C4<1>, C4<1>;
+L_0000000003950b40 .functor AND 1, L_000000000380de60, L_000000000380ee00, C4<1>, C4<1>;
+L_0000000003951400 .functor BUF 1, L_0000000003951240, C4<0>, C4<0>, C4<0>;
+v00000000035f9940_0 .net "CLK_N", 0 0, o0000000003574f38; alias, 0 drivers
+v00000000035f9a80_0 .net "CLK_N_delayed", 0 0, o0000000003574f68; 0 drivers
+v00000000035fb9c0_0 .net "D", 0 0, o0000000003574f98; alias, 0 drivers
+v00000000035fc000_0 .net "D_delayed", 0 0, o0000000003574fc8; 0 drivers
+v00000000035fb420_0 .net "Q", 0 0, L_0000000003951400; alias, 1 drivers
+v00000000035fba60_0 .net "RESET", 0 0, L_0000000003951b70; 1 drivers
+v00000000035fc0a0_0 .net "RESET_B", 0 0, o0000000003575058; alias, 0 drivers
+v00000000035fa840_0 .net "RESET_B_delayed", 0 0, o0000000003575088; 0 drivers
+v00000000035fbe20_0 .net8 "VGND", 0 0, L_00000000038ad710; 1 drivers, strength-aware
+L_00000000038acc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035faca0_0 .net8 "VNB", 0 0, L_00000000038acc90; 1 drivers, strength-aware
+L_00000000038ae190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fa480_0 .net8 "VPB", 0 0, L_00000000038ae190; 1 drivers, strength-aware
+v00000000035f9c60_0 .net8 "VPWR", 0 0, L_00000000038acd70; 1 drivers, strength-aware
+v00000000035fa5c0_0 .net *"_s10", 0 0, L_000000000380f620; 1 drivers
+L_00000000039704a0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f9f80_0 .net/2u *"_s14", 0 0, L_00000000039704a0; 1 drivers
+v00000000035fb2e0_0 .net *"_s16", 0 0, L_000000000380ee00; 1 drivers
+L_0000000003970410 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fa980_0 .net/2u *"_s4", 0 0, L_0000000003970410; 1 drivers
+L_0000000003970458 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035f9e40_0 .net/2u *"_s8", 0 0, L_0000000003970458; 1 drivers
+v00000000035fa660_0 .net "awake", 0 0, L_000000000380de60; 1 drivers
+v00000000035fa7a0_0 .net "buf_Q", 0 0, L_0000000003951240; 1 drivers
+v00000000035fb920_0 .net "cond0", 0 0, L_0000000003951cc0; 1 drivers
+v00000000035fbc40_0 .net "cond1", 0 0, L_0000000003950b40; 1 drivers
+v00000000035fb100_0 .net "intclk", 0 0, L_0000000003950a60; 1 drivers
+v00000000035f9d00_0 .var "notifier", 0 0;
+L_000000000380de60 .cmp/eeq 1, L_00000000038acd70, L_0000000003970410;
+L_000000000380f620 .cmp/eeq 1, o0000000003575088, L_0000000003970458;
+L_000000000380ee00 .cmp/eeq 1, o0000000003575058, L_00000000039704a0;
+S_000000000281b240 .scope module, "sky130_fd_sc_hd__dfrtp_1" "sky130_fd_sc_hd__dfrtp_1" 4 27830;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o00000000035755c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fab60_0 .net "CLK", 0 0, o00000000035755c8; 0 drivers
+o0000000003575628 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fafc0_0 .net "D", 0 0, o0000000003575628; 0 drivers
+v00000000035fb060_0 .net "Q", 0 0, L_0000000003950d70; 1 drivers
+o00000000035756e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fc140_0 .net "RESET_B", 0 0, o00000000035756e8; 0 drivers
+L_00000000038ad010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fe300_0 .net8 "VGND", 0 0, L_00000000038ad010; 1 drivers, strength-aware
+L_00000000038acde0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fc820_0 .net8 "VNB", 0 0, L_00000000038acde0; 1 drivers, strength-aware
+L_00000000038ad390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fe6c0_0 .net8 "VPB", 0 0, L_00000000038ad390; 1 drivers, strength-aware
+L_00000000038add30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fe800_0 .net8 "VPWR", 0 0, L_00000000038add30; 1 drivers, strength-aware
+S_00000000034e3c30 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 27848, 4 28152 1, S_000000000281b240;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003575718 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003950bb0 .functor NOT 1, o0000000003575718, C4<0>, C4<0>, C4<0>;
+o0000000003575658 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000035755f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ad9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ad2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039516a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003575658, o00000000035755f8, L_0000000003950bb0, v00000000035fa8e0_0, L_00000000038ad9b0, L_00000000038ad2b0;
+L_0000000003950c20 .functor AND 1, L_000000000380f4e0, L_000000000380eea0, C4<1>, C4<1>;
+L_0000000003950c90 .functor AND 1, L_000000000380f4e0, L_000000000380f580, C4<1>, C4<1>;
+L_0000000003950d70 .functor BUF 1, L_00000000039516a0, C4<0>, C4<0>, C4<0>;
+v00000000035fa020_0 .net "CLK", 0 0, o00000000035755c8; alias, 0 drivers
+v00000000035fac00_0 .net "CLK_delayed", 0 0, o00000000035755f8; 0 drivers
+v00000000035fbd80_0 .net "D", 0 0, o0000000003575628; alias, 0 drivers
+v00000000035fae80_0 .net "D_delayed", 0 0, o0000000003575658; 0 drivers
+v00000000035fb560_0 .net "Q", 0 0, L_0000000003950d70; alias, 1 drivers
+v00000000035fad40_0 .net "RESET", 0 0, L_0000000003950bb0; 1 drivers
+v00000000035faf20_0 .net "RESET_B", 0 0, o00000000035756e8; alias, 0 drivers
+v00000000035fb600_0 .net "RESET_B_delayed", 0 0, o0000000003575718; 0 drivers
+v00000000035fb6a0_0 .net8 "VGND", 0 0, L_00000000038ad2b0; 1 drivers, strength-aware
+L_00000000038adb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fb880_0 .net8 "VNB", 0 0, L_00000000038adb00; 1 drivers, strength-aware
+L_00000000038ae350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f9bc0_0 .net8 "VPB", 0 0, L_00000000038ae350; 1 drivers, strength-aware
+v00000000035faac0_0 .net8 "VPWR", 0 0, L_00000000038ad9b0; 1 drivers, strength-aware
+v00000000035fa160_0 .net *"_s10", 0 0, L_000000000380eea0; 1 drivers
+L_0000000003970578 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fbce0_0 .net/2u *"_s14", 0 0, L_0000000003970578; 1 drivers
+v00000000035fa200_0 .net *"_s16", 0 0, L_000000000380f580; 1 drivers
+L_00000000039704e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fb740_0 .net/2u *"_s4", 0 0, L_00000000039704e8; 1 drivers
+L_0000000003970530 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fa340_0 .net/2u *"_s8", 0 0, L_0000000003970530; 1 drivers
+v00000000035fa3e0_0 .net "awake", 0 0, L_000000000380f4e0; 1 drivers
+v00000000035fbec0_0 .net "buf_Q", 0 0, L_00000000039516a0; 1 drivers
+v00000000035fa700_0 .net "cond0", 0 0, L_0000000003950c20; 1 drivers
+v00000000035fbf60_0 .net "cond1", 0 0, L_0000000003950c90; 1 drivers
+v00000000035fa8e0_0 .var "notifier", 0 0;
+L_000000000380f4e0 .cmp/eeq 1, L_00000000038ad9b0, L_00000000039704e8;
+L_000000000380eea0 .cmp/eeq 1, o0000000003575718, L_0000000003970530;
+L_000000000380f580 .cmp/eeq 1, o00000000035756e8, L_0000000003970578;
+S_000000000281ac40 .scope module, "sky130_fd_sc_hd__dfrtp_2" "sky130_fd_sc_hd__dfrtp_2" 4 28280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003575c28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fe8a0_0 .net "CLK", 0 0, o0000000003575c28; 0 drivers
+o0000000003575c88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fe760_0 .net "D", 0 0, o0000000003575c88; 0 drivers
+v00000000035fd2c0_0 .net "Q", 0 0, L_0000000003950e50; 1 drivers
+o0000000003575d48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fcaa0_0 .net "RESET_B", 0 0, o0000000003575d48; 0 drivers
+L_00000000038acd00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fc780_0 .net8 "VGND", 0 0, L_00000000038acd00; 1 drivers, strength-aware
+L_00000000038acb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fd540_0 .net8 "VNB", 0 0, L_00000000038acb40; 1 drivers, strength-aware
+L_00000000038adb70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fe1c0_0 .net8 "VPB", 0 0, L_00000000038adb70; 1 drivers, strength-aware
+L_00000000038acbb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fd900_0 .net8 "VPWR", 0 0, L_00000000038acbb0; 1 drivers, strength-aware
+S_00000000034e10b0 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 28298, 4 28152 1, S_000000000281ac40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003575d78 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039504b0 .functor NOT 1, o0000000003575d78, C4<0>, C4<0>, C4<0>;
+o0000000003575cb8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003575c58 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ace50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ada20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951710 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003575cb8, o0000000003575c58, L_00000000039504b0, v00000000035fdcc0_0, L_00000000038ace50, L_00000000038ada20;
+L_0000000003951780 .functor AND 1, L_000000000380d500, L_000000000380e4a0, C4<1>, C4<1>;
+L_0000000003950de0 .functor AND 1, L_000000000380d500, L_000000000380ec20, C4<1>, C4<1>;
+L_0000000003950e50 .functor BUF 1, L_0000000003951710, C4<0>, C4<0>, C4<0>;
+v00000000035fdea0_0 .net "CLK", 0 0, o0000000003575c28; alias, 0 drivers
+v00000000035fd360_0 .net "CLK_delayed", 0 0, o0000000003575c58; 0 drivers
+v00000000035fc460_0 .net "D", 0 0, o0000000003575c88; alias, 0 drivers
+v00000000035fdae0_0 .net "D_delayed", 0 0, o0000000003575cb8; 0 drivers
+v00000000035fc8c0_0 .net "Q", 0 0, L_0000000003950e50; alias, 1 drivers
+v00000000035fcb40_0 .net "RESET", 0 0, L_00000000039504b0; 1 drivers
+v00000000035fe260_0 .net "RESET_B", 0 0, o0000000003575d48; alias, 0 drivers
+v00000000035fc640_0 .net "RESET_B_delayed", 0 0, o0000000003575d78; 0 drivers
+v00000000035fc6e0_0 .net8 "VGND", 0 0, L_00000000038ada20; 1 drivers, strength-aware
+L_00000000038ad860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fe4e0_0 .net8 "VNB", 0 0, L_00000000038ad860; 1 drivers, strength-aware
+L_00000000038ae3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fd9a0_0 .net8 "VPB", 0 0, L_00000000038ae3c0; 1 drivers, strength-aware
+v00000000035fd400_0 .net8 "VPWR", 0 0, L_00000000038ace50; 1 drivers, strength-aware
+v00000000035fdb80_0 .net *"_s10", 0 0, L_000000000380e4a0; 1 drivers
+L_0000000003970650 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fd7c0_0 .net/2u *"_s14", 0 0, L_0000000003970650; 1 drivers
+v00000000035fc1e0_0 .net *"_s16", 0 0, L_000000000380ec20; 1 drivers
+L_00000000039705c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fd220_0 .net/2u *"_s4", 0 0, L_00000000039705c0; 1 drivers
+L_0000000003970608 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fdc20_0 .net/2u *"_s8", 0 0, L_0000000003970608; 1 drivers
+v00000000035fe620_0 .net "awake", 0 0, L_000000000380d500; 1 drivers
+v00000000035fc5a0_0 .net "buf_Q", 0 0, L_0000000003951710; 1 drivers
+v00000000035fd4a0_0 .net "cond0", 0 0, L_0000000003951780; 1 drivers
+v00000000035fc500_0 .net "cond1", 0 0, L_0000000003950de0; 1 drivers
+v00000000035fdcc0_0 .var "notifier", 0 0;
+L_000000000380d500 .cmp/eeq 1, L_00000000038ace50, L_00000000039705c0;
+L_000000000380e4a0 .cmp/eeq 1, o0000000003575d78, L_0000000003970608;
+L_000000000380ec20 .cmp/eeq 1, o0000000003575d48, L_0000000003970650;
+S_000000000281b6c0 .scope module, "sky130_fd_sc_hd__dfrtp_4" "sky130_fd_sc_hd__dfrtp_4" 4 28392;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o0000000003576288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fde00_0 .net "CLK", 0 0, o0000000003576288; 0 drivers
+o00000000035762e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fdfe0_0 .net "D", 0 0, o00000000035762e8; 0 drivers
+v00000000035fe080_0 .net "Q", 0 0, L_00000000039518d0; 1 drivers
+o00000000035763a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fe120_0 .net "RESET_B", 0 0, o00000000035763a8; 0 drivers
+L_00000000038ad780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fe3a0_0 .net8 "VGND", 0 0, L_00000000038ad780; 1 drivers, strength-aware
+L_00000000038ad240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fe580_0 .net8 "VNB", 0 0, L_00000000038ad240; 1 drivers, strength-aware
+L_00000000038ae430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fe440_0 .net8 "VPB", 0 0, L_00000000038ae430; 1 drivers, strength-aware
+L_00000000038acec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003601000_0 .net8 "VPWR", 0 0, L_00000000038acec0; 1 drivers, strength-aware
+S_00000000034e40b0 .scope module, "base" "sky130_fd_sc_hd__dfrtp" 4 28410, 4 28152 1, S_000000000281b6c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "RESET_B"
+o00000000035763d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951c50 .functor NOT 1, o00000000035763d8, C4<0>, C4<0>, C4<0>;
+o0000000003576318 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000035762b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ae040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ad320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003950ec0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, o0000000003576318, o00000000035762b8, L_0000000003951c50, v00000000035fdd60_0, L_00000000038ae040, L_00000000038ad320;
+L_0000000003950f30 .functor AND 1, L_000000000380ecc0, L_000000000380e400, C4<1>, C4<1>;
+L_0000000003951860 .functor AND 1, L_000000000380ecc0, L_000000000380d1e0, C4<1>, C4<1>;
+L_00000000039518d0 .functor BUF 1, L_0000000003950ec0, C4<0>, C4<0>, C4<0>;
+v00000000035fc960_0 .net "CLK", 0 0, o0000000003576288; alias, 0 drivers
+v00000000035fcbe0_0 .net "CLK_delayed", 0 0, o00000000035762b8; 0 drivers
+v00000000035fc3c0_0 .net "D", 0 0, o00000000035762e8; alias, 0 drivers
+v00000000035fc280_0 .net "D_delayed", 0 0, o0000000003576318; 0 drivers
+v00000000035fc320_0 .net "Q", 0 0, L_00000000039518d0; alias, 1 drivers
+v00000000035fca00_0 .net "RESET", 0 0, L_0000000003951c50; 1 drivers
+v00000000035fcc80_0 .net "RESET_B", 0 0, o00000000035763a8; alias, 0 drivers
+v00000000035fcd20_0 .net "RESET_B_delayed", 0 0, o00000000035763d8; 0 drivers
+v00000000035fcdc0_0 .net8 "VGND", 0 0, L_00000000038ad320; 1 drivers, strength-aware
+L_00000000038ad1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fd040_0 .net8 "VNB", 0 0, L_00000000038ad1d0; 1 drivers, strength-aware
+L_00000000038ade80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035fda40_0 .net8 "VPB", 0 0, L_00000000038ade80; 1 drivers, strength-aware
+v00000000035fd0e0_0 .net8 "VPWR", 0 0, L_00000000038ae040; 1 drivers, strength-aware
+v00000000035fd5e0_0 .net *"_s10", 0 0, L_000000000380e400; 1 drivers
+L_0000000003970728 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fd860_0 .net/2u *"_s14", 0 0, L_0000000003970728; 1 drivers
+v00000000035fce60_0 .net *"_s16", 0 0, L_000000000380d1e0; 1 drivers
+L_0000000003970698 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fd680_0 .net/2u *"_s4", 0 0, L_0000000003970698; 1 drivers
+L_00000000039706e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fcf00_0 .net/2u *"_s8", 0 0, L_00000000039706e0; 1 drivers
+v00000000035fcfa0_0 .net "awake", 0 0, L_000000000380ecc0; 1 drivers
+v00000000035fdf40_0 .net "buf_Q", 0 0, L_0000000003950ec0; 1 drivers
+v00000000035fd180_0 .net "cond0", 0 0, L_0000000003950f30; 1 drivers
+v00000000035fd720_0 .net "cond1", 0 0, L_0000000003951860; 1 drivers
+v00000000035fdd60_0 .var "notifier", 0 0;
+L_000000000380ecc0 .cmp/eeq 1, L_00000000038ae040, L_0000000003970698;
+L_000000000380e400 .cmp/eeq 1, o00000000035763d8, L_00000000039706e0;
+L_000000000380d1e0 .cmp/eeq 1, o00000000035763a8, L_0000000003970728;
+S_000000000281aac0 .scope module, "sky130_fd_sc_hd__dfsbp_1" "sky130_fd_sc_hd__dfsbp_1" 4 21611;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SET_B"
+o00000000035768e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036006a0_0 .net "CLK", 0 0, o00000000035768e8; 0 drivers
+o0000000003576948 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036010a0_0 .net "D", 0 0, o0000000003576948; 0 drivers
+v00000000035ff8e0_0 .net "Q", 0 0, L_0000000003952040; 1 drivers
+v00000000035ff340_0 .net "Q_N", 0 0, L_0000000003952510; 1 drivers
+o0000000003576a38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035fe9e0_0 .net "SET_B", 0 0, o0000000003576a38; 0 drivers
+L_00000000038adc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fffc0_0 .net8 "VGND", 0 0, L_00000000038adc50; 1 drivers, strength-aware
+L_00000000038ad400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036001a0_0 .net8 "VNB", 0 0, L_00000000038ad400; 1 drivers, strength-aware
+L_00000000038ae270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ff520_0 .net8 "VPB", 0 0, L_00000000038ae270; 1 drivers, strength-aware
+L_00000000038adf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ff020_0 .net8 "VPWR", 0 0, L_00000000038adf60; 1 drivers, strength-aware
+S_00000000034e3f30 .scope module, "base" "sky130_fd_sc_hd__dfsbp" 4 21631, 4 21477 1, S_000000000281aac0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SET_B"
+o0000000003576a68 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003951940 .functor NOT 1, o0000000003576a68, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$PS_pp$PG$N", 6, 2
+ ,"?*b0?10-"
+ ,"??_0?10-"
+ ,"??b_?10-"
+ ,"???1?101"
+ ,"?0r0?100"
+ ,"?1r??101"
+ ,"00R0?100"
+ ,"11R??101"
+ ,"00x0?100"
+ ,"11x??101"
+ ,"1?b%?101"
+ ,"1?_x?101"
+ ,"??????*x";
+o0000000003576978 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003576918 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ad080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ad4e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003950210 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003576978, o0000000003576918, L_0000000003951940, v00000000035fe940_0, L_00000000038ad080, L_00000000038ad4e0;
+L_0000000003952040 .functor BUF 1, L_0000000003950210, C4<0>, C4<0>, C4<0>;
+L_0000000003952510 .functor NOT 1, L_0000000003950210, C4<0>, C4<0>, C4<0>;
+v0000000003600c40_0 .net "CLK", 0 0, o00000000035768e8; alias, 0 drivers
+v00000000035fea80_0 .net "CLK_delayed", 0 0, o0000000003576918; 0 drivers
+v00000000035ffa20_0 .net "D", 0 0, o0000000003576948; alias, 0 drivers
+v00000000035ff480_0 .net "D_delayed", 0 0, o0000000003576978; 0 drivers
+v00000000036004c0_0 .net "Q", 0 0, L_0000000003952040; alias, 1 drivers
+v0000000003600420_0 .net "Q_N", 0 0, L_0000000003952510; alias, 1 drivers
+v00000000035ffac0_0 .net "SET", 0 0, L_0000000003951940; 1 drivers
+v0000000003600560_0 .net "SET_B", 0 0, o0000000003576a38; alias, 0 drivers
+v00000000035fff20_0 .net "SET_B_delayed", 0 0, o0000000003576a68; 0 drivers
+v00000000035ff700_0 .net8 "VGND", 0 0, L_00000000038ad4e0; 1 drivers, strength-aware
+L_00000000038acc20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035feda0_0 .net8 "VNB", 0 0, L_00000000038acc20; 1 drivers, strength-aware
+L_00000000038ac8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035feee0_0 .net8 "VPB", 0 0, L_00000000038ac8a0; 1 drivers, strength-aware
+v00000000035ff840_0 .net8 "VPWR", 0 0, L_00000000038ad080; 1 drivers, strength-aware
+L_0000000003970800 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035fef80_0 .net/2u *"_s12", 0 0, L_0000000003970800; 1 drivers
+L_0000000003970770 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036009c0_0 .net/2u *"_s4", 0 0, L_0000000003970770; 1 drivers
+L_00000000039707b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035ffd40_0 .net/2u *"_s8", 0 0, L_00000000039707b8; 1 drivers
+v00000000035fed00_0 .net "awake", 0 0, L_000000000380f6c0; 1 drivers
+v00000000035ff2a0_0 .net "buf_Q", 0 0, L_0000000003950210; 1 drivers
+v0000000003600600_0 .net "cond0", 0 0, L_000000000380e220; 1 drivers
+v00000000035ff0c0_0 .net "cond1", 0 0, L_000000000380e540; 1 drivers
+v00000000035fe940_0 .var "notifier", 0 0;
+L_000000000380f6c0 .cmp/eeq 1, L_00000000038ad080, L_0000000003970770;
+L_000000000380e220 .cmp/eeq 1, o0000000003576a68, L_00000000039707b8;
+L_000000000380e540 .cmp/eeq 1, o0000000003576a38, L_0000000003970800;
+S_000000000281b840 .scope module, "sky130_fd_sc_hd__dfsbp_2" "sky130_fd_sc_hd__dfsbp_2" 4 21729;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SET_B"
+o0000000003576f78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003600380_0 .net "CLK", 0 0, o0000000003576f78; 0 drivers
+o0000000003576fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035ffca0_0 .net "D", 0 0, o0000000003576fd8; 0 drivers
+v0000000003600920_0 .net "Q", 0 0, L_0000000003953770; 1 drivers
+v0000000003600740_0 .net "Q_N", 0 0, L_00000000039532a0; 1 drivers
+o00000000035770c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036007e0_0 .net "SET_B", 0 0, o00000000035770c8; 0 drivers
+L_00000000038ae0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003600a60_0 .net8 "VGND", 0 0, L_00000000038ae0b0; 1 drivers, strength-aware
+L_00000000038ad7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003600b00_0 .net8 "VNB", 0 0, L_00000000038ad7f0; 1 drivers, strength-aware
+L_00000000038adbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003600ba0_0 .net8 "VPB", 0 0, L_00000000038adbe0; 1 drivers, strength-aware
+L_00000000038ad8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003600d80_0 .net8 "VPWR", 0 0, L_00000000038ad8d0; 1 drivers, strength-aware
+S_00000000034e22b0 .scope module, "base" "sky130_fd_sc_hd__dfsbp" 4 21749, 4 21477 1, S_000000000281b840;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SET_B"
+o00000000035770f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039538c0 .functor NOT 1, o00000000035770f8, C4<0>, C4<0>, C4<0>;
+o0000000003577008 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003576fa8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ac910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038acfa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952f20 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003577008, o0000000003576fa8, L_00000000039538c0, v00000000036002e0_0, L_00000000038ac910, L_00000000038acfa0;
+L_0000000003953770 .functor BUF 1, L_0000000003952f20, C4<0>, C4<0>, C4<0>;
+L_00000000039532a0 .functor NOT 1, L_0000000003952f20, C4<0>, C4<0>, C4<0>;
+v00000000035feb20_0 .net "CLK", 0 0, o0000000003576f78; alias, 0 drivers
+v00000000035ffde0_0 .net "CLK_delayed", 0 0, o0000000003576fa8; 0 drivers
+v00000000035fec60_0 .net "D", 0 0, o0000000003576fd8; alias, 0 drivers
+v00000000035ffe80_0 .net "D_delayed", 0 0, o0000000003577008; 0 drivers
+v00000000035ff160_0 .net "Q", 0 0, L_0000000003953770; alias, 1 drivers
+v0000000003600060_0 .net "Q_N", 0 0, L_00000000039532a0; alias, 1 drivers
+v00000000035ff200_0 .net "SET", 0 0, L_00000000039538c0; 1 drivers
+v0000000003600100_0 .net "SET_B", 0 0, o00000000035770c8; alias, 0 drivers
+v0000000003600880_0 .net "SET_B_delayed", 0 0, o00000000035770f8; 0 drivers
+v00000000035febc0_0 .net8 "VGND", 0 0, L_00000000038acfa0; 1 drivers, strength-aware
+L_00000000038ad940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035fee40_0 .net8 "VNB", 0 0, L_00000000038ad940; 1 drivers, strength-aware
+L_00000000038adda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035ff5c0_0 .net8 "VPB", 0 0, L_00000000038adda0; 1 drivers, strength-aware
+v00000000035ff3e0_0 .net8 "VPWR", 0 0, L_00000000038ac910; 1 drivers, strength-aware
+L_00000000039708d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035ff660_0 .net/2u *"_s12", 0 0, L_00000000039708d8; 1 drivers
+L_0000000003970848 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000035ff7a0_0 .net/2u *"_s4", 0 0, L_0000000003970848; 1 drivers
+L_0000000003970890 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003600ce0_0 .net/2u *"_s8", 0 0, L_0000000003970890; 1 drivers
+v00000000035ff980_0 .net "awake", 0 0, L_000000000380d8c0; 1 drivers
+v00000000035ffb60_0 .net "buf_Q", 0 0, L_0000000003952f20; 1 drivers
+v00000000035ffc00_0 .net "cond0", 0 0, L_000000000380f760; 1 drivers
+v0000000003600240_0 .net "cond1", 0 0, L_000000000380d280; 1 drivers
+v00000000036002e0_0 .var "notifier", 0 0;
+L_000000000380d8c0 .cmp/eeq 1, L_00000000038ac910, L_0000000003970848;
+L_000000000380f760 .cmp/eeq 1, o00000000035770f8, L_0000000003970890;
+L_000000000380d280 .cmp/eeq 1, o00000000035770c8, L_00000000039708d8;
+S_000000000281af40 .scope module, "sky130_fd_sc_hd__dfstp_1" "sky130_fd_sc_hd__dfstp_1" 4 27718;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003577608 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003603440_0 .net "CLK", 0 0, o0000000003577608; 0 drivers
+o0000000003577668 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036027c0_0 .net "D", 0 0, o0000000003577668; 0 drivers
+v0000000003601140_0 .net "Q", 0 0, L_0000000003953310; 1 drivers
+o0000000003577728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003603580_0 .net "SET_B", 0 0, o0000000003577728; 0 drivers
+L_00000000038aca60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003602cc0_0 .net8 "VGND", 0 0, L_00000000038aca60; 1 drivers, strength-aware
+L_00000000038ac980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003602900_0 .net8 "VNB", 0 0, L_00000000038ac980; 1 drivers, strength-aware
+L_00000000038adcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003601aa0_0 .net8 "VPB", 0 0, L_00000000038adcc0; 1 drivers, strength-aware
+L_00000000038ade10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003602400_0 .net8 "VPWR", 0 0, L_00000000038ade10; 1 drivers, strength-aware
+S_00000000034e4e30 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27736, 4 27590 1, S_000000000281af40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003577758 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952200 .functor NOT 1, o0000000003577758, C4<0>, C4<0>, C4<0>;
+o0000000003577698 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003577638 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ad470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038acf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952ba0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003577698, o0000000003577638, L_0000000003952200, v0000000003602b80_0, L_00000000038ad470, L_00000000038acf30;
+L_0000000003953310 .functor BUF 1, L_0000000003952ba0, C4<0>, C4<0>, C4<0>;
+v0000000003600e20_0 .net "CLK", 0 0, o0000000003577608; alias, 0 drivers
+v0000000003600ec0_0 .net "CLK_delayed", 0 0, o0000000003577638; 0 drivers
+v0000000003600f60_0 .net "D", 0 0, o0000000003577668; alias, 0 drivers
+v0000000003601e60_0 .net "D_delayed", 0 0, o0000000003577698; 0 drivers
+v00000000036031c0_0 .net "Q", 0 0, L_0000000003953310; alias, 1 drivers
+v0000000003603800_0 .net "SET", 0 0, L_0000000003952200; 1 drivers
+v0000000003602c20_0 .net "SET_B", 0 0, o0000000003577728; alias, 0 drivers
+v0000000003601780_0 .net "SET_B_delayed", 0 0, o0000000003577758; 0 drivers
+v0000000003601500_0 .net8 "VGND", 0 0, L_00000000038acf30; 1 drivers, strength-aware
+L_00000000038ada90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003602040_0 .net8 "VNB", 0 0, L_00000000038ada90; 1 drivers, strength-aware
+L_00000000038ad0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003603620_0 .net8 "VPB", 0 0, L_00000000038ad0f0; 1 drivers, strength-aware
+v0000000003601d20_0 .net8 "VPWR", 0 0, L_00000000038ad470; 1 drivers, strength-aware
+L_00000000039709b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003602360_0 .net/2u *"_s12", 0 0, L_00000000039709b0; 1 drivers
+L_0000000003970920 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003601460_0 .net/2u *"_s4", 0 0, L_0000000003970920; 1 drivers
+L_0000000003970968 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003602ae0_0 .net/2u *"_s8", 0 0, L_0000000003970968; 1 drivers
+v0000000003602ea0_0 .net "awake", 0 0, L_000000000380d960; 1 drivers
+v0000000003601b40_0 .net "buf_Q", 0 0, L_0000000003952ba0; 1 drivers
+v00000000036036c0_0 .net "cond0", 0 0, L_000000000380f120; 1 drivers
+v00000000036011e0_0 .net "cond1", 0 0, L_000000000380da00; 1 drivers
+v0000000003602b80_0 .var "notifier", 0 0;
+L_000000000380d960 .cmp/eeq 1, L_00000000038ad470, L_0000000003970920;
+L_000000000380f120 .cmp/eeq 1, o0000000003577758, L_0000000003970968;
+L_000000000380da00 .cmp/eeq 1, o0000000003577728, L_00000000039709b0;
+S_000000000281b540 .scope module, "sky130_fd_sc_hd__dfstp_2" "sky130_fd_sc_hd__dfstp_2" 4 27156;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003577c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003601fa0_0 .net "CLK", 0 0, o0000000003577c08; 0 drivers
+o0000000003577c68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003601dc0_0 .net "D", 0 0, o0000000003577c68; 0 drivers
+v0000000003602680_0 .net "Q", 0 0, L_00000000039520b0; 1 drivers
+o0000000003577d28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003601820_0 .net "SET_B", 0 0, o0000000003577d28; 0 drivers
+L_00000000038acad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003602720_0 .net8 "VGND", 0 0, L_00000000038acad0; 1 drivers, strength-aware
+L_00000000038adef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036033a0_0 .net8 "VNB", 0 0, L_00000000038adef0; 1 drivers, strength-aware
+L_00000000038adfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003602a40_0 .net8 "VPB", 0 0, L_00000000038adfd0; 1 drivers, strength-aware
+L_00000000038ac9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003602fe0_0 .net8 "VPWR", 0 0, L_00000000038ac9f0; 1 drivers, strength-aware
+S_00000000034e6030 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27174, 4 27590 1, S_000000000281b540;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003577d58 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952dd0 .functor NOT 1, o0000000003577d58, C4<0>, C4<0>, C4<0>;
+o0000000003577c98 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003577c38 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ae2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ae120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039524a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003577c98, o0000000003577c38, L_0000000003952dd0, v0000000003603300_0, L_00000000038ae2e0, L_00000000038ae120;
+L_00000000039520b0 .functor BUF 1, L_00000000039524a0, C4<0>, C4<0>, C4<0>;
+v00000000036038a0_0 .net "CLK", 0 0, o0000000003577c08; alias, 0 drivers
+v0000000003603760_0 .net "CLK_delayed", 0 0, o0000000003577c38; 0 drivers
+v00000000036022c0_0 .net "D", 0 0, o0000000003577c68; alias, 0 drivers
+v0000000003601be0_0 .net "D_delayed", 0 0, o0000000003577c98; 0 drivers
+v00000000036015a0_0 .net "Q", 0 0, L_00000000039520b0; alias, 1 drivers
+v00000000036024a0_0 .net "SET", 0 0, L_0000000003952dd0; 1 drivers
+v0000000003603260_0 .net "SET_B", 0 0, o0000000003577d28; alias, 0 drivers
+v00000000036029a0_0 .net "SET_B_delayed", 0 0, o0000000003577d58; 0 drivers
+v00000000036025e0_0 .net8 "VGND", 0 0, L_00000000038ae120; 1 drivers, strength-aware
+L_00000000038ad550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003602d60_0 .net8 "VNB", 0 0, L_00000000038ad550; 1 drivers, strength-aware
+L_00000000038ae200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003602860_0 .net8 "VPB", 0 0, L_00000000038ae200; 1 drivers, strength-aware
+v0000000003602e00_0 .net8 "VPWR", 0 0, L_00000000038ae2e0; 1 drivers, strength-aware
+L_0000000003970a88 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036034e0_0 .net/2u *"_s12", 0 0, L_0000000003970a88; 1 drivers
+L_00000000039709f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003601f00_0 .net/2u *"_s4", 0 0, L_00000000039709f8; 1 drivers
+L_0000000003970a40 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003601640_0 .net/2u *"_s8", 0 0, L_0000000003970a40; 1 drivers
+v0000000003601c80_0 .net "awake", 0 0, L_000000000380d780; 1 drivers
+v0000000003602540_0 .net "buf_Q", 0 0, L_00000000039524a0; 1 drivers
+v00000000036016e0_0 .net "cond0", 0 0, L_000000000380db40; 1 drivers
+v0000000003602f40_0 .net "cond1", 0 0, L_000000000380f800; 1 drivers
+v0000000003603300_0 .var "notifier", 0 0;
+L_000000000380d780 .cmp/eeq 1, L_00000000038ae2e0, L_00000000039709f8;
+L_000000000380db40 .cmp/eeq 1, o0000000003577d58, L_0000000003970a40;
+L_000000000380f800 .cmp/eeq 1, o0000000003577d28, L_0000000003970a88;
+S_000000000281b9c0 .scope module, "sky130_fd_sc_hd__dfstp_4" "sky130_fd_sc_hd__dfstp_4" 4 27268;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003578208 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003604660_0 .net "CLK", 0 0, o0000000003578208; 0 drivers
+o0000000003578268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003605600_0 .net "D", 0 0, o0000000003578268; 0 drivers
+v0000000003603f80_0 .net "Q", 0 0, L_0000000003952cf0; 1 drivers
+o0000000003578328 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003604e80_0 .net "SET_B", 0 0, o0000000003578328; 0 drivers
+L_00000000038ad5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003604160_0 .net8 "VGND", 0 0, L_00000000038ad5c0; 1 drivers, strength-aware
+L_00000000038ad160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036039e0_0 .net8 "VNB", 0 0, L_00000000038ad160; 1 drivers, strength-aware
+L_00000000038ad630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003605ce0_0 .net8 "VPB", 0 0, L_00000000038ad630; 1 drivers, strength-aware
+L_00000000038ad6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003603bc0_0 .net8 "VPWR", 0 0, L_00000000038ad6a0; 1 drivers, strength-aware
+S_00000000034e4230 .scope module, "base" "sky130_fd_sc_hd__dfstp" 4 27286, 4 27590 1, S_000000000281b9c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SET_B"
+o0000000003578358 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953540 .functor NOT 1, o0000000003578358, C4<0>, C4<0>, C4<0>;
+o0000000003578298 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003578238 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038af460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038afcb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951d30 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, o0000000003578298, o0000000003578238, L_0000000003953540, v0000000003604520_0, L_00000000038af460, L_00000000038afcb0;
+L_0000000003952cf0 .functor BUF 1, L_0000000003951d30, C4<0>, C4<0>, C4<0>;
+v0000000003601960_0 .net "CLK", 0 0, o0000000003578208; alias, 0 drivers
+v0000000003603080_0 .net "CLK_delayed", 0 0, o0000000003578238; 0 drivers
+v0000000003602180_0 .net "D", 0 0, o0000000003578268; alias, 0 drivers
+v0000000003601320_0 .net "D_delayed", 0 0, o0000000003578298; 0 drivers
+v00000000036020e0_0 .net "Q", 0 0, L_0000000003952cf0; alias, 1 drivers
+v0000000003601a00_0 .net "SET", 0 0, L_0000000003953540; 1 drivers
+v0000000003601280_0 .net "SET_B", 0 0, o0000000003578328; alias, 0 drivers
+v00000000036013c0_0 .net "SET_B_delayed", 0 0, o0000000003578358; 0 drivers
+v0000000003602220_0 .net8 "VGND", 0 0, L_00000000038afcb0; 1 drivers, strength-aware
+L_00000000038af2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003603120_0 .net8 "VNB", 0 0, L_00000000038af2a0; 1 drivers, strength-aware
+L_00000000038ae820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036018c0_0 .net8 "VPB", 0 0, L_00000000038ae820; 1 drivers, strength-aware
+v0000000003604de0_0 .net8 "VPWR", 0 0, L_00000000038af460; 1 drivers, strength-aware
+L_0000000003970b60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003604fc0_0 .net/2u *"_s12", 0 0, L_0000000003970b60; 1 drivers
+L_0000000003970ad0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003605f60_0 .net/2u *"_s4", 0 0, L_0000000003970ad0; 1 drivers
+L_0000000003970b18 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003603ee0_0 .net/2u *"_s8", 0 0, L_0000000003970b18; 1 drivers
+v0000000003603940_0 .net "awake", 0 0, L_000000000380f260; 1 drivers
+v0000000003606000_0 .net "buf_Q", 0 0, L_0000000003951d30; 1 drivers
+v0000000003605740_0 .net "cond0", 0 0, L_000000000380daa0; 1 drivers
+v00000000036060a0_0 .net "cond1", 0 0, L_000000000380ef40; 1 drivers
+v0000000003604520_0 .var "notifier", 0 0;
+L_000000000380f260 .cmp/eeq 1, L_00000000038af460, L_0000000003970ad0;
+L_000000000380daa0 .cmp/eeq 1, o0000000003578358, L_0000000003970b18;
+L_000000000380ef40 .cmp/eeq 1, o0000000003578328, L_0000000003970b60;
+S_000000000281bb40 .scope module, "sky130_fd_sc_hd__dfxbp_1" "sky130_fd_sc_hd__dfxbp_1" 4 43145;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+o0000000003578808 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036048e0_0 .net "CLK", 0 0, o0000000003578808; 0 drivers
+o0000000003578868 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003605240_0 .net "D", 0 0, o0000000003578868; 0 drivers
+v0000000003604480_0 .net "Q", 0 0, L_00000000039523c0; 1 drivers
+v0000000003603e40_0 .net "Q_N", 0 0, L_0000000003952820; 1 drivers
+L_00000000038af1c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036052e0_0 .net8 "VGND", 0 0, L_00000000038af1c0; 1 drivers, strength-aware
+L_00000000038ae6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036059c0_0 .net8 "VNB", 0 0, L_00000000038ae6d0; 1 drivers, strength-aware
+L_00000000038ae900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003604200_0 .net8 "VPB", 0 0, L_00000000038ae900; 1 drivers, strength-aware
+L_00000000038b0030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036051a0_0 .net8 "VPWR", 0 0, L_00000000038b0030; 1 drivers, strength-aware
+S_00000000034e2bb0 .scope module, "base" "sky130_fd_sc_hd__dfxbp" 4 43163, 4 43459 1, S_000000000281bb40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dff$P_pp$PG$N", 5, 2
+ ,"?1r?101"
+ ,"?0r?100"
+ ,"11R?101"
+ ,"00R?100"
+ ,"11Q?101"
+ ,"00Q?100"
+ ,"00x?100"
+ ,"11x?101"
+ ,"??_?10-"
+ ,"?*b?10-"
+ ,"?????*x";
+o0000000003578898 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003578838 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038af540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038ae4a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952900 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003578898, o0000000003578838, v00000000036040c0_0, L_00000000038af540, L_00000000038ae4a0;
+L_00000000039523c0 .functor BUF 1, L_0000000003952900, C4<0>, C4<0>, C4<0>;
+L_0000000003952820 .functor NOT 1, L_0000000003952900, C4<0>, C4<0>, C4<0>;
+v0000000003605100_0 .net "CLK", 0 0, o0000000003578808; alias, 0 drivers
+v0000000003605560_0 .net "CLK_delayed", 0 0, o0000000003578838; 0 drivers
+v0000000003604a20_0 .net "D", 0 0, o0000000003578868; alias, 0 drivers
+v0000000003604ac0_0 .net "D_delayed", 0 0, o0000000003578898; 0 drivers
+v0000000003604f20_0 .net "Q", 0 0, L_00000000039523c0; alias, 1 drivers
+v00000000036056a0_0 .net "Q_N", 0 0, L_0000000003952820; alias, 1 drivers
+v0000000003605920_0 .net8 "VGND", 0 0, L_00000000038ae4a0; 1 drivers, strength-aware
+L_00000000038aecf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003603b20_0 .net8 "VNB", 0 0, L_00000000038aecf0; 1 drivers, strength-aware
+L_00000000038afaf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003604ca0_0 .net8 "VPB", 0 0, L_00000000038afaf0; 1 drivers, strength-aware
+v0000000003604340_0 .net8 "VPWR", 0 0, L_00000000038af540; 1 drivers, strength-aware
+L_0000000003970ba8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003604980_0 .net/2u *"_s4", 0 0, L_0000000003970ba8; 1 drivers
+v0000000003604020_0 .net "awake", 0 0, L_000000000380e5e0; 1 drivers
+v0000000003604840_0 .net "buf_Q", 0 0, L_0000000003952900; 1 drivers
+v00000000036040c0_0 .var "notifier", 0 0;
+L_000000000380e5e0 .cmp/eeq 1, L_00000000038af540, L_0000000003970ba8;
+S_000000000281a040 .scope module, "sky130_fd_sc_hd__dfxbp_2" "sky130_fd_sc_hd__dfxbp_2" 4 43033;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+o0000000003578ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003605060_0 .net "CLK", 0 0, o0000000003578ce8; 0 drivers
+o0000000003578d48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003605880_0 .net "D", 0 0, o0000000003578d48; 0 drivers
+v0000000003605420_0 .net "Q", 0 0, L_0000000003952c10; 1 drivers
+v00000000036057e0_0 .net "Q_N", 0 0, L_0000000003952e40; 1 drivers
+L_00000000038ae510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036054c0_0 .net8 "VGND", 0 0, L_00000000038ae510; 1 drivers, strength-aware
+L_00000000038aedd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003605b00_0 .net8 "VNB", 0 0, L_00000000038aedd0; 1 drivers, strength-aware
+L_00000000038af5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003605ba0_0 .net8 "VPB", 0 0, L_00000000038af5b0; 1 drivers, strength-aware
+L_00000000038ae580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003605c40_0 .net8 "VPWR", 0 0, L_00000000038ae580; 1 drivers, strength-aware
+S_00000000034e3030 .scope module, "base" "sky130_fd_sc_hd__dfxbp" 4 43051, 4 43459 1, S_000000000281a040;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+o0000000003578d78 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003578d18 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038aeac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038aea50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952430 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003578d78, o0000000003578d18, v0000000003604c00_0, L_00000000038aeac0, L_00000000038aea50;
+L_0000000003952c10 .functor BUF 1, L_0000000003952430, C4<0>, C4<0>, C4<0>;
+L_0000000003952e40 .functor NOT 1, L_0000000003952430, C4<0>, C4<0>, C4<0>;
+v0000000003603a80_0 .net "CLK", 0 0, o0000000003578ce8; alias, 0 drivers
+v00000000036045c0_0 .net "CLK_delayed", 0 0, o0000000003578d18; 0 drivers
+v0000000003603d00_0 .net "D", 0 0, o0000000003578d48; alias, 0 drivers
+v0000000003604b60_0 .net "D_delayed", 0 0, o0000000003578d78; 0 drivers
+v0000000003605e20_0 .net "Q", 0 0, L_0000000003952c10; alias, 1 drivers
+v0000000003604d40_0 .net "Q_N", 0 0, L_0000000003952e40; alias, 1 drivers
+v0000000003604700_0 .net8 "VGND", 0 0, L_00000000038aea50; 1 drivers, strength-aware
+L_00000000038ae5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003603c60_0 .net8 "VNB", 0 0, L_00000000038ae5f0; 1 drivers, strength-aware
+L_00000000038aee40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036047a0_0 .net8 "VPB", 0 0, L_00000000038aee40; 1 drivers, strength-aware
+v00000000036042a0_0 .net8 "VPWR", 0 0, L_00000000038aeac0; 1 drivers, strength-aware
+L_0000000003970bf0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003605380_0 .net/2u *"_s4", 0 0, L_0000000003970bf0; 1 drivers
+v0000000003605a60_0 .net "awake", 0 0, L_000000000380e7c0; 1 drivers
+v00000000036043e0_0 .net "buf_Q", 0 0, L_0000000003952430; 1 drivers
+v0000000003604c00_0 .var "notifier", 0 0;
+L_000000000380e7c0 .cmp/eeq 1, L_00000000038aeac0, L_0000000003970bf0;
+S_000000000281bcc0 .scope module, "sky130_fd_sc_hd__dfxtp_1" "sky130_fd_sc_hd__dfxtp_1" 4 58198;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o00000000035791c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036066e0_0 .net "CLK", 0 0, o00000000035791c8; 0 drivers
+o0000000003579228 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036084e0_0 .net "D", 0 0, o0000000003579228; 0 drivers
+v0000000003608120_0 .net "Q", 0 0, L_0000000003952ac0; 1 drivers
+L_00000000038aff50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607b80_0 .net8 "VGND", 0 0, L_00000000038aff50; 1 drivers, strength-aware
+L_00000000038aeeb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036077c0_0 .net8 "VNB", 0 0, L_00000000038aeeb0; 1 drivers, strength-aware
+L_00000000038aec80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003606140_0 .net8 "VPB", 0 0, L_00000000038aec80; 1 drivers, strength-aware
+L_00000000038aeb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003607220_0 .net8 "VPWR", 0 0, L_00000000038aeb30; 1 drivers, strength-aware
+S_00000000034e1230 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 58214, 4 58082 1, S_000000000281bcc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o0000000003579258 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000035791f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038af070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038aeba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952f90 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003579258, o00000000035791f8, v0000000003606b40_0, L_00000000038af070, L_00000000038aeba0;
+L_0000000003952ac0 .functor BUF 1, L_0000000003952f90, C4<0>, C4<0>, C4<0>;
+v0000000003605d80_0 .net "CLK", 0 0, o00000000035791c8; alias, 0 drivers
+v0000000003605ec0_0 .net "CLK_delayed", 0 0, o00000000035791f8; 0 drivers
+v0000000003603da0_0 .net "D", 0 0, o0000000003579228; alias, 0 drivers
+v0000000003608260_0 .net "D_delayed", 0 0, o0000000003579258; 0 drivers
+v00000000036088a0_0 .net "Q", 0 0, L_0000000003952ac0; alias, 1 drivers
+v0000000003607ae0_0 .net8 "VGND", 0 0, L_00000000038aeba0; 1 drivers, strength-aware
+L_00000000038aec10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607ea0_0 .net8 "VNB", 0 0, L_00000000038aec10; 1 drivers, strength-aware
+L_00000000038aef20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036074a0_0 .net8 "VPB", 0 0, L_00000000038aef20; 1 drivers, strength-aware
+v0000000003606c80_0 .net8 "VPWR", 0 0, L_00000000038af070; 1 drivers, strength-aware
+L_0000000003970c38 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003607d60_0 .net/2u *"_s4", 0 0, L_0000000003970c38; 1 drivers
+v0000000003606780_0 .net "awake", 0 0, L_000000000380e180; 1 drivers
+v0000000003607f40_0 .net "buf_Q", 0 0, L_0000000003952f90; 1 drivers
+v0000000003606b40_0 .var "notifier", 0 0;
+L_000000000380e180 .cmp/eeq 1, L_00000000038af070, L_0000000003970c38;
+S_000000000281a4c0 .scope module, "sky130_fd_sc_hd__dfxtp_2" "sky130_fd_sc_hd__dfxtp_2" 4 57780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o0000000003579618 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003607540_0 .net "CLK", 0 0, o0000000003579618; 0 drivers
+o0000000003579678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003608620_0 .net "D", 0 0, o0000000003579678; 0 drivers
+v0000000003607c20_0 .net "Q", 0 0, L_0000000003952120; 1 drivers
+L_00000000038af150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607fe0_0 .net8 "VGND", 0 0, L_00000000038af150; 1 drivers, strength-aware
+L_00000000038af230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036063c0_0 .net8 "VNB", 0 0, L_00000000038af230; 1 drivers, strength-aware
+L_00000000038af310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036061e0_0 .net8 "VPB", 0 0, L_00000000038af310; 1 drivers, strength-aware
+L_00000000038ae7b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003606320_0 .net8 "VPWR", 0 0, L_00000000038ae7b0; 1 drivers, strength-aware
+S_00000000034e5bb0 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 57796, 4 58082 1, S_000000000281a4c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o00000000035796a8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003579648 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038ae740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038affc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039531c0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o00000000035796a8, o0000000003579648, v0000000003608440_0, L_00000000038ae740, L_00000000038affc0;
+L_0000000003952120 .functor BUF 1, L_00000000039531c0, C4<0>, C4<0>, C4<0>;
+v0000000003607400_0 .net "CLK", 0 0, o0000000003579618; alias, 0 drivers
+v0000000003608300_0 .net "CLK_delayed", 0 0, o0000000003579648; 0 drivers
+v00000000036081c0_0 .net "D", 0 0, o0000000003579678; alias, 0 drivers
+v00000000036079a0_0 .net "D_delayed", 0 0, o00000000035796a8; 0 drivers
+v0000000003608800_0 .net "Q", 0 0, L_0000000003952120; alias, 1 drivers
+v0000000003608760_0 .net8 "VGND", 0 0, L_00000000038affc0; 1 drivers, strength-aware
+L_00000000038aed60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003606be0_0 .net8 "VNB", 0 0, L_00000000038aed60; 1 drivers, strength-aware
+L_00000000038af930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036075e0_0 .net8 "VPB", 0 0, L_00000000038af930; 1 drivers, strength-aware
+v0000000003606aa0_0 .net8 "VPWR", 0 0, L_00000000038ae740; 1 drivers, strength-aware
+L_0000000003970c80 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036072c0_0 .net/2u *"_s4", 0 0, L_0000000003970c80; 1 drivers
+v00000000036083a0_0 .net "awake", 0 0, L_000000000380ea40; 1 drivers
+v0000000003608580_0 .net "buf_Q", 0 0, L_00000000039531c0; 1 drivers
+v0000000003608440_0 .var "notifier", 0 0;
+L_000000000380ea40 .cmp/eeq 1, L_00000000038ae740, L_0000000003970c80;
+S_000000000281a340 .scope module, "sky130_fd_sc_hd__dfxtp_4" "sky130_fd_sc_hd__dfxtp_4" 4 57674;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o0000000003579a68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036065a0_0 .net "CLK", 0 0, o0000000003579a68; 0 drivers
+o0000000003579ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003606640_0 .net "D", 0 0, o0000000003579ac8; 0 drivers
+v0000000003606820_0 .net "Q", 0 0, L_0000000003953000; 1 drivers
+L_00000000038ae9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003606a00_0 .net8 "VGND", 0 0, L_00000000038ae9e0; 1 drivers, strength-aware
+L_00000000038aef90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607720_0 .net8 "VNB", 0 0, L_00000000038aef90; 1 drivers, strength-aware
+L_00000000038afd20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036068c0_0 .net8 "VPB", 0 0, L_00000000038afd20; 1 drivers, strength-aware
+L_00000000038ae890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003606d20_0 .net8 "VPWR", 0 0, L_00000000038ae890; 1 drivers, strength-aware
+S_00000000034e61b0 .scope module, "base" "sky130_fd_sc_hd__dfxtp" 4 57690, 4 58082 1, S_000000000281a340;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+o0000000003579af8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003579a98 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038afa10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038af0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953230 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, o0000000003579af8, o0000000003579a98, v0000000003606960_0, L_00000000038afa10, L_00000000038af0e0;
+L_0000000003953000 .functor BUF 1, L_0000000003953230, C4<0>, C4<0>, C4<0>;
+v0000000003607360_0 .net "CLK", 0 0, o0000000003579a68; alias, 0 drivers
+v0000000003607a40_0 .net "CLK_delayed", 0 0, o0000000003579a98; 0 drivers
+v0000000003606280_0 .net "D", 0 0, o0000000003579ac8; alias, 0 drivers
+v0000000003607860_0 .net "D_delayed", 0 0, o0000000003579af8; 0 drivers
+v0000000003607cc0_0 .net "Q", 0 0, L_0000000003953000; alias, 1 drivers
+v0000000003607680_0 .net8 "VGND", 0 0, L_00000000038af0e0; 1 drivers, strength-aware
+L_00000000038ae660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607900_0 .net8 "VNB", 0 0, L_00000000038ae660; 1 drivers, strength-aware
+L_00000000038af000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003606460_0 .net8 "VPB", 0 0, L_00000000038af000; 1 drivers, strength-aware
+v0000000003606500_0 .net8 "VPWR", 0 0, L_00000000038afa10; 1 drivers, strength-aware
+L_0000000003970cc8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003608080_0 .net/2u *"_s4", 0 0, L_0000000003970cc8; 1 drivers
+v00000000036086c0_0 .net "awake", 0 0, L_000000000380e680; 1 drivers
+v0000000003607e00_0 .net "buf_Q", 0 0, L_0000000003953230; 1 drivers
+v0000000003606960_0 .var "notifier", 0 0;
+L_000000000380e680 .cmp/eeq 1, L_00000000038afa10, L_0000000003970cc8;
+S_000000000281a1c0 .scope module, "sky130_fd_sc_hd__diode_2" "sky130_fd_sc_hd__diode_2" 4 759;
+ .timescale -9 -12;
+ .port_info 0 /INPUT 1 "DIODE"
+o0000000003579eb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036070e0_0 .net "DIODE", 0 0, o0000000003579eb8; 0 drivers
+L_00000000038af380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003607180_0 .net8 "VGND", 0 0, L_00000000038af380; 1 drivers, strength-aware
+L_00000000038af620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003609ca0_0 .net8 "VNB", 0 0, L_00000000038af620; 1 drivers, strength-aware
+L_00000000038af3f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003609340_0 .net8 "VPB", 0 0, L_00000000038af3f0; 1 drivers, strength-aware
+L_00000000038af4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003609980_0 .net8 "VPWR", 0 0, L_00000000038af4d0; 1 drivers, strength-aware
+S_00000000034e31b0 .scope module, "base" "sky130_fd_sc_hd__diode" 4 771, 4 1009 1, S_000000000281a1c0;
+ .timescale -9 -12;
+ .port_info 0 /INPUT 1 "DIODE"
+v0000000003606dc0_0 .net "DIODE", 0 0, o0000000003579eb8; alias, 0 drivers
+L_00000000038af690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003606e60_0 .net8 "VGND", 0 0, L_00000000038af690; 1 drivers, strength-aware
+L_00000000038ae970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003606f00_0 .net8 "VNB", 0 0, L_00000000038ae970; 1 drivers, strength-aware
+L_00000000038af700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003606fa0_0 .net8 "VPB", 0 0, L_00000000038af700; 1 drivers, strength-aware
+L_00000000038af770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003607040_0 .net8 "VPWR", 0 0, L_00000000038af770; 1 drivers, strength-aware
+S_000000000281b0c0 .scope module, "sky130_fd_sc_hd__dlclkp_1" "sky130_fd_sc_hd__dlclkp_1" 4 4641;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a0c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360a2e0_0 .net "CLK", 0 0, o000000000357a0c8; 0 drivers
+o000000000357a128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003609700_0 .net "GATE", 0 0, o000000000357a128; 0 drivers
+v0000000003609480_0 .net "GCLK", 0 0, L_0000000003953070; 1 drivers
+L_00000000038afbd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360a560_0 .net8 "VGND", 0 0, L_00000000038afbd0; 1 drivers, strength-aware
+L_00000000038af7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360a380_0 .net8 "VNB", 0 0, L_00000000038af7e0; 1 drivers, strength-aware
+L_00000000038af850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360a6a0_0 .net8 "VPB", 0 0, L_00000000038af850; 1 drivers, strength-aware
+L_00000000038af8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036093e0_0 .net8 "VPWR", 0 0, L_00000000038af8c0; 1 drivers, strength-aware
+S_00000000034e3630 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4657, 4 4949 1, S_000000000281b0c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a0f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952580 .functor NOT 1, o000000000357a0f8, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N", 5, 2
+ ,"?*0?10-"
+ ,"??_?10-"
+ ,"??M?10-"
+ ,"00Q?100"
+ ,"11Q?101"
+ ,"?0R?100"
+ ,"?1R?101"
+ ,"?_1?100"
+ ,"?+1?101"
+ ,"?0r?100"
+ ,"?1r?101"
+ ,"1+x?101"
+ ,"0_x?100"
+ ,"?11?+01"
+ ,"?01?1_0"
+ ,"?11?1_1";
+o000000000357a158 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038afb60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038af9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039525f0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357a158, L_0000000003952580, v0000000003609020_0, L_00000000038afb60, L_00000000038af9a0;
+L_0000000003953070 .functor AND 1, L_00000000039525f0, o000000000357a0f8, C4<1>, C4<1>;
+v0000000003609520_0 .net "CLK", 0 0, o000000000357a0c8; alias, 0 drivers
+v000000000360a7e0_0 .net "CLK_delayed", 0 0, o000000000357a0f8; 0 drivers
+v0000000003608da0_0 .net "GATE", 0 0, o000000000357a128; alias, 0 drivers
+v000000000360a240_0 .net "GATE_delayed", 0 0, o000000000357a158; 0 drivers
+v000000000360a100_0 .net "GCLK", 0 0, L_0000000003953070; alias, 1 drivers
+v0000000003608f80_0 .net8 "VGND", 0 0, L_00000000038af9a0; 1 drivers, strength-aware
+L_00000000038afd90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360a1a0_0 .net8 "VNB", 0 0, L_00000000038afd90; 1 drivers, strength-aware
+L_00000000038afa80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360ad80_0 .net8 "VPB", 0 0, L_00000000038afa80; 1 drivers, strength-aware
+v00000000036095c0_0 .net8 "VPWR", 0 0, L_00000000038afb60; 1 drivers, strength-aware
+L_0000000003970d10 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003609660_0 .net/2u *"_s4", 0 0, L_0000000003970d10; 1 drivers
+v000000000360aec0_0 .net "awake", 0 0, L_000000000380e900; 1 drivers
+v000000000360b000_0 .net "clkn", 0 0, L_0000000003952580; 1 drivers
+v000000000360a420_0 .net "m0", 0 0, L_00000000039525f0; 1 drivers
+v0000000003609020_0 .var "notifier", 0 0;
+L_000000000380e900 .cmp/eeq 1, L_00000000038afb60, L_0000000003970d10;
+S_000000000281a640 .scope module, "sky130_fd_sc_hd__dlclkp_2" "sky130_fd_sc_hd__dlclkp_2" 4 4535;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a548 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036097a0_0 .net "CLK", 0 0, o000000000357a548; 0 drivers
+o000000000357a5a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003609de0_0 .net "GATE", 0 0, o000000000357a5a8; 0 drivers
+v0000000003608d00_0 .net "GCLK", 0 0, L_00000000039530e0; 1 drivers
+L_00000000038afc40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003609c00_0 .net8 "VGND", 0 0, L_00000000038afc40; 1 drivers, strength-aware
+L_00000000038afe00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360aa60_0 .net8 "VNB", 0 0, L_00000000038afe00; 1 drivers, strength-aware
+L_00000000038afe70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360ab00_0 .net8 "VPB", 0 0, L_00000000038afe70; 1 drivers, strength-aware
+L_00000000038afee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360a920_0 .net8 "VPWR", 0 0, L_00000000038afee0; 1 drivers, strength-aware
+S_00000000034e1e30 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4551, 4 4949 1, S_000000000281a640;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a578 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953380 .functor NOT 1, o000000000357a578, C4<0>, C4<0>, C4<0>;
+o000000000357a5d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b08f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b0e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951fd0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357a5d8, L_0000000003953380, v000000000360a880_0, L_00000000038b08f0, L_00000000038b0e30;
+L_00000000039530e0 .functor AND 1, L_0000000003951fd0, o000000000357a578, C4<1>, C4<1>;
+v000000000360a4c0_0 .net "CLK", 0 0, o000000000357a548; alias, 0 drivers
+v000000000360ac40_0 .net "CLK_delayed", 0 0, o000000000357a578; 0 drivers
+v0000000003609fc0_0 .net "GATE", 0 0, o000000000357a5a8; alias, 0 drivers
+v0000000003608940_0 .net "GATE_delayed", 0 0, o000000000357a5d8; 0 drivers
+v0000000003609a20_0 .net "GCLK", 0 0, L_00000000039530e0; alias, 1 drivers
+v000000000360a600_0 .net8 "VGND", 0 0, L_00000000038b0e30; 1 drivers, strength-aware
+L_00000000038b1060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003608c60_0 .net8 "VNB", 0 0, L_00000000038b1060; 1 drivers, strength-aware
+L_00000000038b0ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360ae20_0 .net8 "VPB", 0 0, L_00000000038b0ea0; 1 drivers, strength-aware
+v0000000003608e40_0 .net8 "VPWR", 0 0, L_00000000038b08f0; 1 drivers, strength-aware
+L_0000000003970d58 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036089e0_0 .net/2u *"_s4", 0 0, L_0000000003970d58; 1 drivers
+v000000000360a740_0 .net "awake", 0 0, L_000000000380efe0; 1 drivers
+v000000000360a9c0_0 .net "clkn", 0 0, L_0000000003953380; 1 drivers
+v0000000003608a80_0 .net "m0", 0 0, L_0000000003951fd0; 1 drivers
+v000000000360a880_0 .var "notifier", 0 0;
+L_000000000380efe0 .cmp/eeq 1, L_00000000038b08f0, L_0000000003970d58;
+S_000000000281a7c0 .scope module, "sky130_fd_sc_hd__dlclkp_4" "sky130_fd_sc_hd__dlclkp_4" 4 4429;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a9c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036092a0_0 .net "CLK", 0 0, o000000000357a9c8; 0 drivers
+o000000000357aa28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003609840_0 .net "GATE", 0 0, o000000000357aa28; 0 drivers
+v0000000003609e80_0 .net "GCLK", 0 0, L_0000000003952350; 1 drivers
+L_00000000038b0880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003609f20_0 .net8 "VGND", 0 0, L_00000000038b0880; 1 drivers, strength-aware
+L_00000000038b1370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360a060_0 .net8 "VNB", 0 0, L_00000000038b1370; 1 drivers, strength-aware
+L_00000000038b1a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360c540_0 .net8 "VPB", 0 0, L_00000000038b1a00; 1 drivers, strength-aware
+L_00000000038b1990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360be60_0 .net8 "VPWR", 0 0, L_00000000038b1990; 1 drivers, strength-aware
+S_00000000034e43b0 .scope module, "base" "sky130_fd_sc_hd__dlclkp" 4 4445, 4 4949 1, S_000000000281a7c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "GATE"
+ .port_info 2 /INPUT 1 "CLK"
+o000000000357a9f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952190 .functor NOT 1, o000000000357a9f8, C4<0>, C4<0>, C4<0>;
+o000000000357aa58 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b1610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b1bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039533f0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357aa58, L_0000000003952190, v00000000036090c0_0, L_00000000038b1610, L_00000000038b1bc0;
+L_0000000003952350 .functor AND 1, L_00000000039533f0, o000000000357a9f8, C4<1>, C4<1>;
+v0000000003609160_0 .net "CLK", 0 0, o000000000357a9c8; alias, 0 drivers
+v000000000360aba0_0 .net "CLK_delayed", 0 0, o000000000357a9f8; 0 drivers
+v0000000003609ac0_0 .net "GATE", 0 0, o000000000357aa28; alias, 0 drivers
+v0000000003608b20_0 .net "GATE_delayed", 0 0, o000000000357aa58; 0 drivers
+v00000000036098e0_0 .net "GCLK", 0 0, L_0000000003952350; alias, 1 drivers
+v0000000003609200_0 .net8 "VGND", 0 0, L_00000000038b1bc0; 1 drivers, strength-aware
+L_00000000038b0ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360af60_0 .net8 "VNB", 0 0, L_00000000038b0ff0; 1 drivers, strength-aware
+L_00000000038b0960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360b0a0_0 .net8 "VPB", 0 0, L_00000000038b0960; 1 drivers, strength-aware
+v0000000003609b60_0 .net8 "VPWR", 0 0, L_00000000038b1610; 1 drivers, strength-aware
+L_0000000003970da0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360ace0_0 .net/2u *"_s4", 0 0, L_0000000003970da0; 1 drivers
+v0000000003608bc0_0 .net "awake", 0 0, L_000000000380e9a0; 1 drivers
+v0000000003608ee0_0 .net "clkn", 0 0, L_0000000003952190; 1 drivers
+v0000000003609d40_0 .net "m0", 0 0, L_00000000039533f0; 1 drivers
+v00000000036090c0_0 .var "notifier", 0 0;
+L_000000000380e9a0 .cmp/eeq 1, L_00000000038b1610, L_0000000003970da0;
+S_000000000281a940 .scope module, "sky130_fd_sc_hd__dlrbn_1" "sky130_fd_sc_hd__dlrbn_1" 4 68978;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE_N"
+o000000000357ae48 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360cea0_0 .net "D", 0 0, o000000000357ae48; 0 drivers
+o000000000357aea8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360c400_0 .net "GATE_N", 0 0, o000000000357aea8; 0 drivers
+v000000000360b3c0_0 .net "Q", 0 0, L_00000000039529e0; 1 drivers
+v000000000360b780_0 .net "Q_N", 0 0, L_0000000003952740; 1 drivers
+o000000000357af98 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360ba00_0 .net "RESET_B", 0 0, o000000000357af98; 0 drivers
+L_00000000038b0570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360cc20_0 .net8 "VGND", 0 0, L_00000000038b0570; 1 drivers, strength-aware
+L_00000000038b0ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360bfa0_0 .net8 "VNB", 0 0, L_00000000038b0ce0; 1 drivers, strength-aware
+L_00000000038b1c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360c0e0_0 .net8 "VPB", 0 0, L_00000000038b1c30; 1 drivers, strength-aware
+L_00000000038b0c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360cae0_0 .net8 "VPWR", 0 0, L_00000000038b0c70; 1 drivers, strength-aware
+S_00000000034e2130 .scope module, "base" "sky130_fd_sc_hd__dlrbn" 4 68998, 4 68840 1, S_000000000281a940;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE_N"
+o000000000357afc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953460 .functor NOT 1, o000000000357afc8, C4<0>, C4<0>, C4<0>;
+o000000000357aed8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039534d0 .functor NOT 1, o000000000357aed8, C4<0>, C4<0>, C4<0>;
+UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N", 6, 2
+ ,"?*00?10-"
+ ,"???1?100"
+ ,"??_0?10-"
+ ,"??M0?10-"
+ ,"00Q0?100"
+ ,"11Q0?101"
+ ,"?0R0?100"
+ ,"?1R0?101"
+ ,"?_10?100"
+ ,"?+10?101"
+ ,"?0r0?100"
+ ,"?1r0?101"
+ ,"0?0%?100"
+ ,"0*0x?100"
+ ,"?0+x?100"
+ ,"?_1x?100"
+ ,"?01%?100"
+ ,"??0_?10-"
+ ,"?01_?100"
+ ,"?11_?101"
+ ,"1+x0?101"
+ ,"0_x0?100"
+ ,"?110?+01"
+ ,"?010?1_0"
+ ,"?110?1_1";
+o000000000357ae78 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b06c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b18b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039526d0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357ae78, L_00000000039534d0, L_0000000003953460, v000000000360bf00_0, L_00000000038b06c0, L_00000000038b18b0;
+L_0000000003953150 .functor AND 1, L_000000000380df00, L_000000000380dfa0, C4<1>, C4<1>;
+L_0000000003952970 .functor AND 1, L_000000000380df00, L_000000000380e040, C4<1>, C4<1>;
+L_00000000039529e0 .functor BUF 1, L_00000000039526d0, C4<0>, C4<0>, C4<0>;
+L_0000000003952740 .functor NOT 1, L_00000000039526d0, C4<0>, C4<0>, C4<0>;
+v000000000360b960_0 .net "D", 0 0, o000000000357ae48; alias, 0 drivers
+v000000000360b1e0_0 .net "D_delayed", 0 0, o000000000357ae78; 0 drivers
+v000000000360d3a0_0 .net "GATE_N", 0 0, o000000000357aea8; alias, 0 drivers
+v000000000360d800_0 .net "GATE_N_delayed", 0 0, o000000000357aed8; 0 drivers
+v000000000360bd20_0 .net "Q", 0 0, L_00000000039529e0; alias, 1 drivers
+v000000000360c2c0_0 .net "Q_N", 0 0, L_0000000003952740; alias, 1 drivers
+v000000000360bdc0_0 .net "RESET", 0 0, L_0000000003953460; 1 drivers
+v000000000360d300_0 .net "RESET_B", 0 0, o000000000357af98; alias, 0 drivers
+v000000000360c900_0 .net "RESET_B_delayed", 0 0, o000000000357afc8; 0 drivers
+v000000000360cd60_0 .net8 "VGND", 0 0, L_00000000038b18b0; 1 drivers, strength-aware
+L_00000000038b0f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360cf40_0 .net8 "VNB", 0 0, L_00000000038b0f10; 1 drivers, strength-aware
+L_00000000038b1220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360c220_0 .net8 "VPB", 0 0, L_00000000038b1220; 1 drivers, strength-aware
+v000000000360c360_0 .net8 "VPWR", 0 0, L_00000000038b06c0; 1 drivers, strength-aware
+v000000000360c720_0 .net *"_s10", 0 0, L_000000000380dfa0; 1 drivers
+L_0000000003970e78 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360ca40_0 .net/2u *"_s14", 0 0, L_0000000003970e78; 1 drivers
+v000000000360d120_0 .net *"_s16", 0 0, L_000000000380e040; 1 drivers
+L_0000000003970de8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360b320_0 .net/2u *"_s4", 0 0, L_0000000003970de8; 1 drivers
+L_0000000003970e30 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360b6e0_0 .net/2u *"_s8", 0 0, L_0000000003970e30; 1 drivers
+v000000000360c180_0 .net "awake", 0 0, L_000000000380df00; 1 drivers
+v000000000360d1c0_0 .net "buf_Q", 0 0, L_00000000039526d0; 1 drivers
+v000000000360c5e0_0 .net "cond0", 0 0, L_0000000003953150; 1 drivers
+v000000000360ce00_0 .net "cond1", 0 0, L_0000000003952970; 1 drivers
+v000000000360c040_0 .net "intgate", 0 0, L_00000000039534d0; 1 drivers
+v000000000360bf00_0 .var "notifier", 0 0;
+L_000000000380df00 .cmp/eeq 1, L_00000000038b06c0, L_0000000003970de8;
+L_000000000380dfa0 .cmp/eeq 1, o000000000357afc8, L_0000000003970e30;
+L_000000000380e040 .cmp/eeq 1, o000000000357af98, L_0000000003970e78;
+S_000000000281adc0 .scope module, "sky130_fd_sc_hd__dlrbn_2" "sky130_fd_sc_hd__dlrbn_2" 4 68494;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE_N"
+o000000000357b568 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360d620_0 .net "D", 0 0, o000000000357b568; 0 drivers
+o000000000357b5c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360d760_0 .net "GATE_N", 0 0, o000000000357b5c8; 0 drivers
+v000000000360b8c0_0 .net "Q", 0 0, L_0000000003952b30; 1 drivers
+v000000000360bbe0_0 .net "Q_N", 0 0, L_0000000003953620; 1 drivers
+o000000000357b6b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360bc80_0 .net "RESET_B", 0 0, o000000000357b6b8; 0 drivers
+L_00000000038b09d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360e840_0 .net8 "VGND", 0 0, L_00000000038b09d0; 1 drivers, strength-aware
+L_00000000038b0b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360dee0_0 .net8 "VNB", 0 0, L_00000000038b0b20; 1 drivers, strength-aware
+L_00000000038b13e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360ef20_0 .net8 "VPB", 0 0, L_00000000038b13e0; 1 drivers, strength-aware
+L_00000000038b1290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360dd00_0 .net8 "VPWR", 0 0, L_00000000038b1290; 1 drivers, strength-aware
+S_00000000034e6c30 .scope module, "base" "sky130_fd_sc_hd__dlrbn" 4 68514, 4 68840 1, S_000000000281adc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE_N"
+o000000000357b6e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953690 .functor NOT 1, o000000000357b6e8, C4<0>, C4<0>, C4<0>;
+o000000000357b5f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952a50 .functor NOT 1, o000000000357b5f8, C4<0>, C4<0>, C4<0>;
+o000000000357b598 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b1300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b0420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039537e0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357b598, L_0000000003952a50, L_0000000003953690, v000000000360cb80_0, L_00000000038b1300, L_00000000038b0420;
+L_00000000039535b0 .functor AND 1, L_000000000380dc80, L_000000000380f3a0, C4<1>, C4<1>;
+L_0000000003952890 .functor AND 1, L_000000000380dc80, L_000000000380d140, C4<1>, C4<1>;
+L_0000000003952b30 .functor BUF 1, L_00000000039537e0, C4<0>, C4<0>, C4<0>;
+L_0000000003953620 .functor NOT 1, L_00000000039537e0, C4<0>, C4<0>, C4<0>;
+v000000000360b460_0 .net "D", 0 0, o000000000357b568; alias, 0 drivers
+v000000000360d8a0_0 .net "D_delayed", 0 0, o000000000357b598; 0 drivers
+v000000000360cfe0_0 .net "GATE_N", 0 0, o000000000357b5c8; alias, 0 drivers
+v000000000360d080_0 .net "GATE_N_delayed", 0 0, o000000000357b5f8; 0 drivers
+v000000000360ccc0_0 .net "Q", 0 0, L_0000000003952b30; alias, 1 drivers
+v000000000360d6c0_0 .net "Q_N", 0 0, L_0000000003953620; alias, 1 drivers
+v000000000360c7c0_0 .net "RESET", 0 0, L_0000000003953690; 1 drivers
+v000000000360b500_0 .net "RESET_B", 0 0, o000000000357b6b8; alias, 0 drivers
+v000000000360d260_0 .net "RESET_B_delayed", 0 0, o000000000357b6e8; 0 drivers
+v000000000360b820_0 .net8 "VGND", 0 0, L_00000000038b0420; 1 drivers, strength-aware
+L_00000000038b1680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360d440_0 .net8 "VNB", 0 0, L_00000000038b1680; 1 drivers, strength-aware
+L_00000000038b0490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360b140_0 .net8 "VPB", 0 0, L_00000000038b0490; 1 drivers, strength-aware
+v000000000360b280_0 .net8 "VPWR", 0 0, L_00000000038b1300; 1 drivers, strength-aware
+v000000000360b5a0_0 .net *"_s10", 0 0, L_000000000380f3a0; 1 drivers
+L_0000000003970f50 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360d4e0_0 .net/2u *"_s14", 0 0, L_0000000003970f50; 1 drivers
+v000000000360baa0_0 .net *"_s16", 0 0, L_000000000380d140; 1 drivers
+L_0000000003970ec0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360c680_0 .net/2u *"_s4", 0 0, L_0000000003970ec0; 1 drivers
+L_0000000003970f08 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360d580_0 .net/2u *"_s8", 0 0, L_0000000003970f08; 1 drivers
+v000000000360bb40_0 .net "awake", 0 0, L_000000000380dc80; 1 drivers
+v000000000360c9a0_0 .net "buf_Q", 0 0, L_00000000039537e0; 1 drivers
+v000000000360c4a0_0 .net "cond0", 0 0, L_00000000039535b0; 1 drivers
+v000000000360b640_0 .net "cond1", 0 0, L_0000000003952890; 1 drivers
+v000000000360c860_0 .net "intgate", 0 0, L_0000000003952a50; 1 drivers
+v000000000360cb80_0 .var "notifier", 0 0;
+L_000000000380dc80 .cmp/eeq 1, L_00000000038b1300, L_0000000003970ec0;
+L_000000000380f3a0 .cmp/eeq 1, o000000000357b6e8, L_0000000003970f08;
+L_000000000380d140 .cmp/eeq 1, o000000000357b6b8, L_0000000003970f50;
+S_000000000281b3c0 .scope module, "sky130_fd_sc_hd__dlrbp_1" "sky130_fd_sc_hd__dlrbp_1" 4 59598;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE"
+o000000000357bc88 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360f100_0 .net "D", 0 0, o000000000357bc88; 0 drivers
+o000000000357bce8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360f600_0 .net "GATE", 0 0, o000000000357bce8; 0 drivers
+v000000000360ea20_0 .net "Q", 0 0, L_0000000003951e80; 1 drivers
+v000000000360f380_0 .net "Q_N", 0 0, L_0000000003952270; 1 drivers
+o000000000357bdd8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360dc60_0 .net "RESET_B", 0 0, o000000000357bdd8; 0 drivers
+L_00000000038b1450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360e2a0_0 .net8 "VGND", 0 0, L_00000000038b1450; 1 drivers, strength-aware
+L_00000000038b16f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360eb60_0 .net8 "VNB", 0 0, L_00000000038b16f0; 1 drivers, strength-aware
+L_00000000038b14c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360d9e0_0 .net8 "VPB", 0 0, L_00000000038b14c0; 1 drivers, strength-aware
+L_00000000038b0d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360fb00_0 .net8 "VPWR", 0 0, L_00000000038b0d50; 1 drivers, strength-aware
+S_00000000034e3db0 .scope module, "base" "sky130_fd_sc_hd__dlrbp" 4 59618, 4 59938 1, S_000000000281b3c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE"
+o000000000357be08 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953700 .functor NOT 1, o000000000357be08, C4<0>, C4<0>, C4<0>;
+o000000000357bcb8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357bd18 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b1530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b1a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003952eb0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357bcb8, o000000000357bd18, L_0000000003953700, v000000000360e5c0_0, L_00000000038b1530, L_00000000038b1a70;
+L_00000000039527b0 .functor AND 1, L_000000000380f080, L_000000000380f1c0, C4<1>, C4<1>;
+L_0000000003953850 .functor AND 1, L_000000000380f080, L_000000000380e0e0, C4<1>, C4<1>;
+L_0000000003951e80 .functor BUF 1, L_0000000003952eb0, C4<0>, C4<0>, C4<0>;
+L_0000000003952270 .functor NOT 1, L_0000000003952eb0, C4<0>, C4<0>, C4<0>;
+v000000000360f240_0 .net "D", 0 0, o000000000357bc88; alias, 0 drivers
+v000000000360f920_0 .net "D_delayed", 0 0, o000000000357bcb8; 0 drivers
+v000000000360e480_0 .net "GATE", 0 0, o000000000357bce8; alias, 0 drivers
+v000000000360fd80_0 .net "GATE_delayed", 0 0, o000000000357bd18; 0 drivers
+v000000000360e520_0 .net "Q", 0 0, L_0000000003951e80; alias, 1 drivers
+v000000000360e660_0 .net "Q_N", 0 0, L_0000000003952270; alias, 1 drivers
+v000000000360f9c0_0 .net "RESET", 0 0, L_0000000003953700; 1 drivers
+v000000000360df80_0 .net "RESET_B", 0 0, o000000000357bdd8; alias, 0 drivers
+v000000000360ee80_0 .net "RESET_B_delayed", 0 0, o000000000357be08; 0 drivers
+v000000000360e020_0 .net8 "VGND", 0 0, L_00000000038b1a70; 1 drivers, strength-aware
+L_00000000038b0500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360dda0_0 .net8 "VNB", 0 0, L_00000000038b0500; 1 drivers, strength-aware
+L_00000000038b0b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360e980_0 .net8 "VPB", 0 0, L_00000000038b0b90; 1 drivers, strength-aware
+v000000000360f2e0_0 .net8 "VPWR", 0 0, L_00000000038b1530; 1 drivers, strength-aware
+v000000000360f6a0_0 .net *"_s10", 0 0, L_000000000380f1c0; 1 drivers
+L_0000000003971028 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360eca0_0 .net/2u *"_s14", 0 0, L_0000000003971028; 1 drivers
+v000000000360f740_0 .net *"_s16", 0 0, L_000000000380e0e0; 1 drivers
+L_0000000003970f98 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360f560_0 .net/2u *"_s4", 0 0, L_0000000003970f98; 1 drivers
+L_0000000003970fe0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360e0c0_0 .net/2u *"_s8", 0 0, L_0000000003970fe0; 1 drivers
+v000000000360e340_0 .net "awake", 0 0, L_000000000380f080; 1 drivers
+v000000000360fa60_0 .net "buf_Q", 0 0, L_0000000003952eb0; 1 drivers
+v000000000360de40_0 .net "cond0", 0 0, L_00000000039527b0; 1 drivers
+v000000000360e160_0 .net "cond1", 0 0, L_0000000003953850; 1 drivers
+v000000000360e5c0_0 .var "notifier", 0 0;
+L_000000000380f080 .cmp/eeq 1, L_00000000038b1530, L_0000000003970f98;
+L_000000000380f1c0 .cmp/eeq 1, o000000000357be08, L_0000000003970fe0;
+L_000000000380e0e0 .cmp/eeq 1, o000000000357bdd8, L_0000000003971028;
+S_0000000002765e70 .scope module, "sky130_fd_sc_hd__dlrbp_2" "sky130_fd_sc_hd__dlrbp_2" 4 59479;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE"
+o000000000357c378 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036100a0_0 .net "D", 0 0, o000000000357c378; 0 drivers
+o000000000357c3d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360da80_0 .net "GATE", 0 0, o000000000357c3d8; 0 drivers
+v000000000360f060_0 .net "Q", 0 0, L_0000000003951f60; 1 drivers
+v000000000360db20_0 .net "Q_N", 0 0, L_0000000003952c80; 1 drivers
+o000000000357c4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000360dbc0_0 .net "RESET_B", 0 0, o000000000357c4c8; 0 drivers
+L_00000000038b0260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003611ae0_0 .net8 "VGND", 0 0, L_00000000038b0260; 1 drivers, strength-aware
+L_00000000038b1b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036108c0_0 .net8 "VNB", 0 0, L_00000000038b1b50; 1 drivers, strength-aware
+L_00000000038b1920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003611b80_0 .net8 "VPB", 0 0, L_00000000038b1920; 1 drivers, strength-aware
+L_00000000038b1760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003611180_0 .net8 "VPWR", 0 0, L_00000000038b1760; 1 drivers, strength-aware
+S_00000000034e25b0 .scope module, "base" "sky130_fd_sc_hd__dlrbp" 4 59499, 4 59938 1, S_0000000002765e70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "RESET_B"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "GATE"
+o000000000357c4f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003952d60 .functor NOT 1, o000000000357c4f8, C4<0>, C4<0>, C4<0>;
+o000000000357c3a8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357c408 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b17d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b0f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003951da0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357c3a8, o000000000357c408, L_0000000003952d60, v000000000360efc0_0, L_00000000038b17d0, L_00000000038b0f80;
+L_0000000003951e10 .functor AND 1, L_000000000380e2c0, L_000000000380d640, C4<1>, C4<1>;
+L_0000000003951ef0 .functor AND 1, L_000000000380e2c0, L_000000000380ed60, C4<1>, C4<1>;
+L_0000000003951f60 .functor BUF 1, L_0000000003951da0, C4<0>, C4<0>, C4<0>;
+L_0000000003952c80 .functor NOT 1, L_0000000003951da0, C4<0>, C4<0>, C4<0>;
+v000000000360eac0_0 .net "D", 0 0, o000000000357c378; alias, 0 drivers
+v000000000360e3e0_0 .net "D_delayed", 0 0, o000000000357c3a8; 0 drivers
+v000000000360ec00_0 .net "GATE", 0 0, o000000000357c3d8; alias, 0 drivers
+v000000000360fba0_0 .net "GATE_delayed", 0 0, o000000000357c408; 0 drivers
+v000000000360fe20_0 .net "Q", 0 0, L_0000000003951f60; alias, 1 drivers
+v000000000360ede0_0 .net "Q_N", 0 0, L_0000000003952c80; alias, 1 drivers
+v000000000360f420_0 .net "RESET", 0 0, L_0000000003952d60; 1 drivers
+v000000000360fc40_0 .net "RESET_B", 0 0, o000000000357c4c8; alias, 0 drivers
+v000000000360e700_0 .net "RESET_B_delayed", 0 0, o000000000357c4f8; 0 drivers
+v000000000360f4c0_0 .net8 "VGND", 0 0, L_00000000038b0f80; 1 drivers, strength-aware
+L_00000000038b0dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000360f7e0_0 .net8 "VNB", 0 0, L_00000000038b0dc0; 1 drivers, strength-aware
+L_00000000038b15a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000360e7a0_0 .net8 "VPB", 0 0, L_00000000038b15a0; 1 drivers, strength-aware
+v000000000360f880_0 .net8 "VPWR", 0 0, L_00000000038b17d0; 1 drivers, strength-aware
+v000000000360ed40_0 .net *"_s10", 0 0, L_000000000380d640; 1 drivers
+L_0000000003971100 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360e200_0 .net/2u *"_s14", 0 0, L_0000000003971100; 1 drivers
+v000000000360fce0_0 .net *"_s16", 0 0, L_000000000380ed60; 1 drivers
+L_0000000003971070 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360fec0_0 .net/2u *"_s4", 0 0, L_0000000003971070; 1 drivers
+L_00000000039710b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000360f1a0_0 .net/2u *"_s8", 0 0, L_00000000039710b8; 1 drivers
+v000000000360d940_0 .net "awake", 0 0, L_000000000380e2c0; 1 drivers
+v000000000360ff60_0 .net "buf_Q", 0 0, L_0000000003951da0; 1 drivers
+v000000000360e8e0_0 .net "cond0", 0 0, L_0000000003951e10; 1 drivers
+v0000000003610000_0 .net "cond1", 0 0, L_0000000003951ef0; 1 drivers
+v000000000360efc0_0 .var "notifier", 0 0;
+L_000000000380e2c0 .cmp/eeq 1, L_00000000038b17d0, L_0000000003971070;
+L_000000000380d640 .cmp/eeq 1, o000000000357c4f8, L_00000000039710b8;
+L_000000000380ed60 .cmp/eeq 1, o000000000357c4c8, L_0000000003971100;
+S_00000000027671f0 .scope module, "sky130_fd_sc_hd__dlrtn_1" "sky130_fd_sc_hd__dlrtn_1" 4 12374;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357ca68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003611e00_0 .net "D", 0 0, o000000000357ca68; 0 drivers
+o000000000357cac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003611fe0_0 .net "GATE_N", 0 0, o000000000357cac8; 0 drivers
+v0000000003610a00_0 .net "Q", 0 0, L_0000000003954b90; 1 drivers
+o000000000357cb88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036103c0_0 .net "RESET_B", 0 0, o000000000357cb88; 0 drivers
+L_00000000038b1ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036124e0_0 .net8 "VGND", 0 0, L_00000000038b1ae0; 1 drivers, strength-aware
+L_00000000038b0a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003610820_0 .net8 "VNB", 0 0, L_00000000038b0a40; 1 drivers, strength-aware
+L_00000000038b11b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003611ea0_0 .net8 "VPB", 0 0, L_00000000038b11b0; 1 drivers, strength-aware
+L_00000000038b1840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003611f40_0 .net8 "VPWR", 0 0, L_00000000038b1840; 1 drivers, strength-aware
+S_00000000034e4830 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12392, 4 12703 1, S_00000000027671f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357cbb8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039522e0 .functor NOT 1, o000000000357cbb8, C4<0>, C4<0>, C4<0>;
+o000000000357caf8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953e70 .functor NOT 1, o000000000357caf8, C4<0>, C4<0>, C4<0>;
+o000000000357ca98 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b03b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b00a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003955220 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357ca98, L_0000000003953e70, L_00000000039522e0, v0000000003612260_0, L_00000000038b03b0, L_00000000038b00a0;
+L_00000000039543b0 .functor AND 1, L_000000000380f8a0, L_000000000380f300, C4<1>, C4<1>;
+L_0000000003953cb0 .functor AND 1, L_000000000380f8a0, L_000000000380e720, C4<1>, C4<1>;
+L_0000000003954b90 .functor BUF 1, L_0000000003955220, C4<0>, C4<0>, C4<0>;
+v0000000003611c20_0 .net "D", 0 0, o000000000357ca68; alias, 0 drivers
+v0000000003610460_0 .net "D_delayed", 0 0, o000000000357ca98; 0 drivers
+v0000000003612440_0 .net "GATE_N", 0 0, o000000000357cac8; alias, 0 drivers
+v0000000003610e60_0 .net "GATE_N_delayed", 0 0, o000000000357caf8; 0 drivers
+v00000000036101e0_0 .net "Q", 0 0, L_0000000003954b90; alias, 1 drivers
+v0000000003612620_0 .net "RESET", 0 0, L_00000000039522e0; 1 drivers
+v00000000036105a0_0 .net "RESET_B", 0 0, o000000000357cb88; alias, 0 drivers
+v0000000003611400_0 .net "RESET_B_delayed", 0 0, o000000000357cbb8; 0 drivers
+v0000000003610500_0 .net8 "VGND", 0 0, L_00000000038b00a0; 1 drivers, strength-aware
+L_00000000038b0110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003611d60_0 .net8 "VNB", 0 0, L_00000000038b0110; 1 drivers, strength-aware
+L_00000000038b02d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036117c0_0 .net8 "VPB", 0 0, L_00000000038b02d0; 1 drivers, strength-aware
+v00000000036119a0_0 .net8 "VPWR", 0 0, L_00000000038b03b0; 1 drivers, strength-aware
+v0000000003612800_0 .net *"_s10", 0 0, L_000000000380f300; 1 drivers
+L_00000000039711d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003610fa0_0 .net/2u *"_s14", 0 0, L_00000000039711d8; 1 drivers
+v0000000003610b40_0 .net *"_s16", 0 0, L_000000000380e720; 1 drivers
+L_0000000003971148 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036115e0_0 .net/2u *"_s4", 0 0, L_0000000003971148; 1 drivers
+L_0000000003971190 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003610960_0 .net/2u *"_s8", 0 0, L_0000000003971190; 1 drivers
+v00000000036114a0_0 .net "awake", 0 0, L_000000000380f8a0; 1 drivers
+v00000000036121c0_0 .net "buf_Q", 0 0, L_0000000003955220; 1 drivers
+v0000000003611900_0 .net "cond0", 0 0, L_00000000039543b0; 1 drivers
+v0000000003611680_0 .net "cond1", 0 0, L_0000000003953cb0; 1 drivers
+v0000000003611cc0_0 .net "intgate", 0 0, L_0000000003953e70; 1 drivers
+v0000000003612260_0 .var "notifier", 0 0;
+L_000000000380f8a0 .cmp/eeq 1, L_00000000038b03b0, L_0000000003971148;
+L_000000000380f300 .cmp/eeq 1, o000000000357cbb8, L_0000000003971190;
+L_000000000380e720 .cmp/eeq 1, o000000000357cb88, L_00000000039711d8;
+S_0000000002765ff0 .scope module, "sky130_fd_sc_hd__dlrtn_2" "sky130_fd_sc_hd__dlrtn_2" 4 12946;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357d0f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003611220_0 .net "D", 0 0, o000000000357d0f8; 0 drivers
+o000000000357d158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036112c0_0 .net "GATE_N", 0 0, o000000000357d158; 0 drivers
+v0000000003611360_0 .net "Q", 0 0, L_0000000003953c40; 1 drivers
+o000000000357d218 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036123a0_0 .net "RESET_B", 0 0, o000000000357d218; 0 drivers
+L_00000000038b0c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003612580_0 .net8 "VGND", 0 0, L_00000000038b0c00; 1 drivers, strength-aware
+L_00000000038b05e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036126c0_0 .net8 "VNB", 0 0, L_00000000038b05e0; 1 drivers, strength-aware
+L_00000000038b1140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003613ca0_0 .net8 "VPB", 0 0, L_00000000038b1140; 1 drivers, strength-aware
+L_00000000038b0180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003612ee0_0 .net8 "VPWR", 0 0, L_00000000038b0180; 1 drivers, strength-aware
+S_00000000034e6330 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12964, 4 12703 1, S_0000000002765ff0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357d248 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954f80 .functor NOT 1, o000000000357d248, C4<0>, C4<0>, C4<0>;
+o000000000357d188 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953ee0 .functor NOT 1, o000000000357d188, C4<0>, C4<0>, C4<0>;
+o000000000357d128 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b0650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b10d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003954ea0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357d128, L_0000000003953ee0, L_0000000003954f80, v00000000036110e0_0, L_00000000038b0650, L_00000000038b10d0;
+L_0000000003953d90 .functor AND 1, L_000000000380dbe0, L_000000000380d6e0, C4<1>, C4<1>;
+L_0000000003954730 .functor AND 1, L_000000000380dbe0, L_000000000380d3c0, C4<1>, C4<1>;
+L_0000000003953c40 .functor BUF 1, L_0000000003954ea0, C4<0>, C4<0>, C4<0>;
+v0000000003611860_0 .net "D", 0 0, o000000000357d0f8; alias, 0 drivers
+v0000000003612760_0 .net "D_delayed", 0 0, o000000000357d128; 0 drivers
+v00000000036106e0_0 .net "GATE_N", 0 0, o000000000357d158; alias, 0 drivers
+v0000000003610140_0 .net "GATE_N_delayed", 0 0, o000000000357d188; 0 drivers
+v00000000036128a0_0 .net "Q", 0 0, L_0000000003953c40; alias, 1 drivers
+v0000000003612080_0 .net "RESET", 0 0, L_0000000003954f80; 1 drivers
+v0000000003610280_0 .net "RESET_B", 0 0, o000000000357d218; alias, 0 drivers
+v0000000003610d20_0 .net "RESET_B_delayed", 0 0, o000000000357d248; 0 drivers
+v0000000003610320_0 .net8 "VGND", 0 0, L_00000000038b10d0; 1 drivers, strength-aware
+L_00000000038b0340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003611540_0 .net8 "VNB", 0 0, L_00000000038b0340; 1 drivers, strength-aware
+L_00000000038b01f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003610f00_0 .net8 "VPB", 0 0, L_00000000038b01f0; 1 drivers, strength-aware
+v0000000003610640_0 .net8 "VPWR", 0 0, L_00000000038b0650; 1 drivers, strength-aware
+v0000000003611720_0 .net *"_s10", 0 0, L_000000000380d6e0; 1 drivers
+L_00000000039712b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003610780_0 .net/2u *"_s14", 0 0, L_00000000039712b0; 1 drivers
+v0000000003611a40_0 .net *"_s16", 0 0, L_000000000380d3c0; 1 drivers
+L_0000000003971220 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003610aa0_0 .net/2u *"_s4", 0 0, L_0000000003971220; 1 drivers
+L_0000000003971268 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003610be0_0 .net/2u *"_s8", 0 0, L_0000000003971268; 1 drivers
+v0000000003610c80_0 .net "awake", 0 0, L_000000000380dbe0; 1 drivers
+v0000000003610dc0_0 .net "buf_Q", 0 0, L_0000000003954ea0; 1 drivers
+v0000000003611040_0 .net "cond0", 0 0, L_0000000003953d90; 1 drivers
+v0000000003612120_0 .net "cond1", 0 0, L_0000000003954730; 1 drivers
+v0000000003612300_0 .net "intgate", 0 0, L_0000000003953ee0; 1 drivers
+v00000000036110e0_0 .var "notifier", 0 0;
+L_000000000380dbe0 .cmp/eeq 1, L_00000000038b0650, L_0000000003971220;
+L_000000000380d6e0 .cmp/eeq 1, o000000000357d248, L_0000000003971268;
+L_000000000380d3c0 .cmp/eeq 1, o000000000357d218, L_00000000039712b0;
+S_00000000027665f0 .scope module, "sky130_fd_sc_hd__dlrtn_4" "sky130_fd_sc_hd__dlrtn_4" 4 12834;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357d788 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003613c00_0 .net "D", 0 0, o000000000357d788; 0 drivers
+o000000000357d7e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003614b00_0 .net "GATE_N", 0 0, o000000000357d7e8; 0 drivers
+v00000000036149c0_0 .net "Q", 0 0, L_00000000039554c0; 1 drivers
+o000000000357d8a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003614240_0 .net "RESET_B", 0 0, o000000000357d8a8; 0 drivers
+L_00000000038b0730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003615000_0 .net8 "VGND", 0 0, L_00000000038b0730; 1 drivers, strength-aware
+L_00000000038b07a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003614f60_0 .net8 "VNB", 0 0, L_00000000038b07a0; 1 drivers, strength-aware
+L_00000000038b0810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036133e0_0 .net8 "VPB", 0 0, L_00000000038b0810; 1 drivers, strength-aware
+L_00000000038b0ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003613de0_0 .net8 "VPWR", 0 0, L_00000000038b0ab0; 1 drivers, strength-aware
+S_00000000034e64b0 .scope module, "base" "sky130_fd_sc_hd__dlrtn" 4 12852, 4 12703 1, S_00000000027665f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357d8d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954110 .functor NOT 1, o000000000357d8d8, C4<0>, C4<0>, C4<0>;
+o000000000357d818 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003955140 .functor NOT 1, o000000000357d818, C4<0>, C4<0>, C4<0>;
+o000000000357d7b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038b1df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038b1d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953f50 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357d7b8, L_0000000003955140, L_0000000003954110, v00000000036129e0_0, L_00000000038b1df0, L_00000000038b1d10;
+L_00000000039548f0 .functor AND 1, L_000000000380ddc0, L_000000000380f440, C4<1>, C4<1>;
+L_0000000003955300 .functor AND 1, L_000000000380ddc0, L_000000000380e360, C4<1>, C4<1>;
+L_00000000039554c0 .functor BUF 1, L_0000000003953f50, C4<0>, C4<0>, C4<0>;
+v0000000003613f20_0 .net "D", 0 0, o000000000357d788; alias, 0 drivers
+v00000000036130c0_0 .net "D_delayed", 0 0, o000000000357d7b8; 0 drivers
+v00000000036132a0_0 .net "GATE_N", 0 0, o000000000357d7e8; alias, 0 drivers
+v0000000003614100_0 .net "GATE_N_delayed", 0 0, o000000000357d818; 0 drivers
+v00000000036142e0_0 .net "Q", 0 0, L_00000000039554c0; alias, 1 drivers
+v0000000003613520_0 .net "RESET", 0 0, L_0000000003954110; 1 drivers
+v0000000003613b60_0 .net "RESET_B", 0 0, o000000000357d8a8; alias, 0 drivers
+v0000000003614740_0 .net "RESET_B_delayed", 0 0, o000000000357d8d8; 0 drivers
+v0000000003614560_0 .net8 "VGND", 0 0, L_00000000038b1d10; 1 drivers, strength-aware
+L_00000000038b1d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003612f80_0 .net8 "VNB", 0 0, L_00000000038b1d80; 1 drivers, strength-aware
+L_00000000038b1ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036146a0_0 .net8 "VPB", 0 0, L_00000000038b1ed0; 1 drivers, strength-aware
+v0000000003613340_0 .net8 "VPWR", 0 0, L_00000000038b1df0; 1 drivers, strength-aware
+v0000000003614a60_0 .net *"_s10", 0 0, L_000000000380f440; 1 drivers
+L_0000000003971388 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003612e40_0 .net/2u *"_s14", 0 0, L_0000000003971388; 1 drivers
+v0000000003614380_0 .net *"_s16", 0 0, L_000000000380e360; 1 drivers
+L_00000000039712f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003614ce0_0 .net/2u *"_s4", 0 0, L_00000000039712f8; 1 drivers
+L_0000000003971340 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003614920_0 .net/2u *"_s8", 0 0, L_0000000003971340; 1 drivers
+v00000000036141a0_0 .net "awake", 0 0, L_000000000380ddc0; 1 drivers
+v0000000003612c60_0 .net "buf_Q", 0 0, L_0000000003953f50; 1 drivers
+v0000000003612940_0 .net "cond0", 0 0, L_00000000039548f0; 1 drivers
+v0000000003613a20_0 .net "cond1", 0 0, L_0000000003955300; 1 drivers
+v0000000003613660_0 .net "intgate", 0 0, L_0000000003955140; 1 drivers
+v00000000036129e0_0 .var "notifier", 0 0;
+L_000000000380ddc0 .cmp/eeq 1, L_00000000038b1df0, L_00000000039712f8;
+L_000000000380f440 .cmp/eeq 1, o000000000357d8d8, L_0000000003971340;
+L_000000000380e360 .cmp/eeq 1, o000000000357d8a8, L_0000000003971388;
+S_0000000002766170 .scope module, "sky130_fd_sc_hd__dlrtp_1" "sky130_fd_sc_hd__dlrtp_1" 4 58879;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357de18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036135c0_0 .net "D", 0 0, o000000000357de18; 0 drivers
+o000000000357de78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036147e0_0 .net "GATE", 0 0, o000000000357de78; 0 drivers
+v0000000003613700_0 .net "Q", 0 0, L_0000000003954490; 1 drivers
+o000000000357df38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036137a0_0 .net "RESET_B", 0 0, o000000000357df38; 0 drivers
+L_00000000038b1e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036138e0_0 .net8 "VGND", 0 0, L_00000000038b1e60; 1 drivers, strength-aware
+L_00000000038b1f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003613980_0 .net8 "VNB", 0 0, L_00000000038b1f40; 1 drivers, strength-aware
+L_00000000038b1ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003614060_0 .net8 "VPB", 0 0, L_00000000038b1ca0; 1 drivers, strength-aware
+L_00000000038a2880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003614880_0 .net8 "VPWR", 0 0, L_00000000038a2880; 1 drivers, strength-aware
+S_00000000034e6630 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58897, 4 58749 1, S_0000000002766170;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357df68 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954d50 .functor NOT 1, o000000000357df68, C4<0>, C4<0>, C4<0>;
+o000000000357de48 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357dea8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a2ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a38b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003954ff0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357de48, o000000000357dea8, L_0000000003954d50, v0000000003612da0_0, L_00000000038a2ff0, L_00000000038a38b0;
+L_0000000003954880 .functor AND 1, L_000000000380d460, L_000000000380d320, C4<1>, C4<1>;
+L_00000000039539a0 .functor AND 1, L_000000000380d460, L_000000000380eb80, C4<1>, C4<1>;
+L_0000000003954490 .functor BUF 1, L_0000000003954ff0, C4<0>, C4<0>, C4<0>;
+v0000000003614ba0_0 .net "D", 0 0, o000000000357de18; alias, 0 drivers
+v0000000003614420_0 .net "D_delayed", 0 0, o000000000357de48; 0 drivers
+v0000000003613d40_0 .net "GATE", 0 0, o000000000357de78; alias, 0 drivers
+v0000000003614d80_0 .net "GATE_delayed", 0 0, o000000000357dea8; 0 drivers
+v0000000003612d00_0 .net "Q", 0 0, L_0000000003954490; alias, 1 drivers
+v0000000003613480_0 .net "RESET", 0 0, L_0000000003954d50; 1 drivers
+v0000000003614600_0 .net "RESET_B", 0 0, o000000000357df38; alias, 0 drivers
+v0000000003613160_0 .net "RESET_B_delayed", 0 0, o000000000357df68; 0 drivers
+v0000000003612a80_0 .net8 "VGND", 0 0, L_00000000038a38b0; 1 drivers, strength-aware
+L_00000000038a2f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003614e20_0 .net8 "VNB", 0 0, L_00000000038a2f80; 1 drivers, strength-aware
+L_00000000038a3300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003613020_0 .net8 "VPB", 0 0, L_00000000038a3300; 1 drivers, strength-aware
+v0000000003613200_0 .net8 "VPWR", 0 0, L_00000000038a2ff0; 1 drivers, strength-aware
+v0000000003614ec0_0 .net *"_s10", 0 0, L_000000000380d320; 1 drivers
+L_0000000003971460 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036150a0_0 .net/2u *"_s14", 0 0, L_0000000003971460; 1 drivers
+v0000000003613840_0 .net *"_s16", 0 0, L_000000000380eb80; 1 drivers
+L_00000000039713d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036144c0_0 .net/2u *"_s4", 0 0, L_00000000039713d0; 1 drivers
+L_0000000003971418 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003612b20_0 .net/2u *"_s8", 0 0, L_0000000003971418; 1 drivers
+v0000000003613ac0_0 .net "awake", 0 0, L_000000000380d460; 1 drivers
+v0000000003612bc0_0 .net "buf_Q", 0 0, L_0000000003954ff0; 1 drivers
+v0000000003613e80_0 .net "cond0", 0 0, L_0000000003954880; 1 drivers
+v0000000003613fc0_0 .net "cond1", 0 0, L_00000000039539a0; 1 drivers
+v0000000003612da0_0 .var "notifier", 0 0;
+L_000000000380d460 .cmp/eeq 1, L_00000000038a2ff0, L_00000000039713d0;
+L_000000000380d320 .cmp/eeq 1, o000000000357df68, L_0000000003971418;
+L_000000000380eb80 .cmp/eeq 1, o000000000357df38, L_0000000003971460;
+S_00000000027659f0 .scope module, "sky130_fd_sc_hd__dlrtp_2" "sky130_fd_sc_hd__dlrtp_2" 4 58308;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357e478 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003615640_0 .net "D", 0 0, o000000000357e478; 0 drivers
+o000000000357e4d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003616e00_0 .net "GATE", 0 0, o000000000357e4d8; 0 drivers
+v0000000003615e60_0 .net "Q", 0 0, L_0000000003954810; 1 drivers
+o000000000357e598 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036169a0_0 .net "RESET_B", 0 0, o000000000357e598; 0 drivers
+L_00000000038a27a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003617580_0 .net8 "VGND", 0 0, L_00000000038a27a0; 1 drivers, strength-aware
+L_00000000038a3140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003617300_0 .net8 "VNB", 0 0, L_00000000038a3140; 1 drivers, strength-aware
+L_00000000038a35a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003616180_0 .net8 "VPB", 0 0, L_00000000038a35a0; 1 drivers, strength-aware
+L_00000000038a2110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036171c0_0 .net8 "VPWR", 0 0, L_00000000038a2110; 1 drivers, strength-aware
+S_00000000034e67b0 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58326, 4 58749 1, S_00000000027659f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357e5c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954420 .functor NOT 1, o000000000357e5c8, C4<0>, C4<0>, C4<0>;
+o000000000357e4a8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357e508 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a2c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a2490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003955370 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357e4a8, o000000000357e508, L_0000000003954420, v0000000003615fa0_0, L_00000000038a2c00, L_00000000038a2490;
+L_0000000003954f10 .functor AND 1, L_000000000380d5a0, L_000000000380dd20, C4<1>, C4<1>;
+L_0000000003955290 .functor AND 1, L_000000000380d5a0, L_000000000380e860, C4<1>, C4<1>;
+L_0000000003954810 .functor BUF 1, L_0000000003955370, C4<0>, C4<0>, C4<0>;
+v0000000003614c40_0 .net "D", 0 0, o000000000357e478; alias, 0 drivers
+v0000000003616720_0 .net "D_delayed", 0 0, o000000000357e4a8; 0 drivers
+v00000000036165e0_0 .net "GATE", 0 0, o000000000357e4d8; alias, 0 drivers
+v00000000036174e0_0 .net "GATE_delayed", 0 0, o000000000357e508; 0 drivers
+v0000000003617440_0 .net "Q", 0 0, L_0000000003954810; alias, 1 drivers
+v0000000003615280_0 .net "RESET", 0 0, L_0000000003954420; 1 drivers
+v0000000003616220_0 .net "RESET_B", 0 0, o000000000357e598; alias, 0 drivers
+v0000000003615dc0_0 .net "RESET_B_delayed", 0 0, o000000000357e5c8; 0 drivers
+v0000000003615c80_0 .net8 "VGND", 0 0, L_00000000038a2490; 1 drivers, strength-aware
+L_00000000038a2a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003616a40_0 .net8 "VNB", 0 0, L_00000000038a2a40; 1 drivers, strength-aware
+L_00000000038a36f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003616c20_0 .net8 "VPB", 0 0, L_00000000038a36f0; 1 drivers, strength-aware
+v00000000036162c0_0 .net8 "VPWR", 0 0, L_00000000038a2c00; 1 drivers, strength-aware
+v0000000003616d60_0 .net *"_s10", 0 0, L_000000000380dd20; 1 drivers
+L_0000000003971538 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036167c0_0 .net/2u *"_s14", 0 0, L_0000000003971538; 1 drivers
+v0000000003615f00_0 .net *"_s16", 0 0, L_000000000380e860; 1 drivers
+L_00000000039714a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036155a0_0 .net/2u *"_s4", 0 0, L_00000000039714a8; 1 drivers
+L_00000000039714f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003616680_0 .net/2u *"_s8", 0 0, L_00000000039714f0; 1 drivers
+v0000000003616040_0 .net "awake", 0 0, L_000000000380d5a0; 1 drivers
+v0000000003615d20_0 .net "buf_Q", 0 0, L_0000000003955370; 1 drivers
+v00000000036158c0_0 .net "cond0", 0 0, L_0000000003954f10; 1 drivers
+v00000000036160e0_0 .net "cond1", 0 0, L_0000000003955290; 1 drivers
+v0000000003615fa0_0 .var "notifier", 0 0;
+L_000000000380d5a0 .cmp/eeq 1, L_00000000038a2c00, L_00000000039714a8;
+L_000000000380dd20 .cmp/eeq 1, o000000000357e5c8, L_00000000039714f0;
+L_000000000380e860 .cmp/eeq 1, o000000000357e598, L_0000000003971538;
+S_00000000027662f0 .scope module, "sky130_fd_sc_hd__dlrtp_4" "sky130_fd_sc_hd__dlrtp_4" 4 58421;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357ead8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036153c0_0 .net "D", 0 0, o000000000357ead8; 0 drivers
+o000000000357eb38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003616540_0 .net "GATE", 0 0, o000000000357eb38; 0 drivers
+v0000000003615b40_0 .net "Q", 0 0, L_0000000003954260; 1 drivers
+o000000000357ebf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003616900_0 .net "RESET_B", 0 0, o000000000357ebf8; 0 drivers
+L_00000000038a2c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003616cc0_0 .net8 "VGND", 0 0, L_00000000038a2c70; 1 drivers, strength-aware
+L_00000000038a2730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003615500_0 .net8 "VNB", 0 0, L_00000000038a2730; 1 drivers, strength-aware
+L_00000000038a3220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003616fe0_0 .net8 "VPB", 0 0, L_00000000038a3220; 1 drivers, strength-aware
+L_00000000038a2420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003617080_0 .net8 "VPWR", 0 0, L_00000000038a2420; 1 drivers, strength-aware
+S_00000000034e6930 .scope module, "base" "sky130_fd_sc_hd__dlrtp" 4 58439, 4 58749 1, S_00000000027662f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "RESET_B"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357ec28 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039553e0 .functor NOT 1, o000000000357ec28, C4<0>, C4<0>, C4<0>;
+o000000000357eb08 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357eb68 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a2340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a2500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003954500 .udp UDP_sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N, o000000000357eb08, o000000000357eb68, L_00000000039553e0, v00000000036164a0_0, L_00000000038a2340, L_00000000038a2500;
+L_00000000039551b0 .functor AND 1, L_000000000380d820, L_000000000380eae0, C4<1>, C4<1>;
+L_0000000003955450 .functor AND 1, L_000000000380d820, L_000000000380f9e0, C4<1>, C4<1>;
+L_0000000003954260 .functor BUF 1, L_0000000003954500, C4<0>, C4<0>, C4<0>;
+v00000000036173a0_0 .net "D", 0 0, o000000000357ead8; alias, 0 drivers
+v0000000003617260_0 .net "D_delayed", 0 0, o000000000357eb08; 0 drivers
+v0000000003616ae0_0 .net "GATE", 0 0, o000000000357eb38; alias, 0 drivers
+v0000000003615460_0 .net "GATE_delayed", 0 0, o000000000357eb68; 0 drivers
+v0000000003617760_0 .net "Q", 0 0, L_0000000003954260; alias, 1 drivers
+v0000000003616360_0 .net "RESET", 0 0, L_00000000039553e0; 1 drivers
+v0000000003616860_0 .net "RESET_B", 0 0, o000000000357ebf8; alias, 0 drivers
+v0000000003615960_0 .net "RESET_B_delayed", 0 0, o000000000357ec28; 0 drivers
+v0000000003616400_0 .net8 "VGND", 0 0, L_00000000038a2500; 1 drivers, strength-aware
+L_00000000038a2260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003617620_0 .net8 "VNB", 0 0, L_00000000038a2260; 1 drivers, strength-aware
+L_00000000038a3370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036176c0_0 .net8 "VPB", 0 0, L_00000000038a3370; 1 drivers, strength-aware
+v0000000003617800_0 .net8 "VPWR", 0 0, L_00000000038a2340; 1 drivers, strength-aware
+v0000000003616ea0_0 .net *"_s10", 0 0, L_000000000380eae0; 1 drivers
+L_0000000003971610 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036178a0_0 .net/2u *"_s14", 0 0, L_0000000003971610; 1 drivers
+v0000000003615aa0_0 .net *"_s16", 0 0, L_000000000380f9e0; 1 drivers
+L_0000000003971580 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003615140_0 .net/2u *"_s4", 0 0, L_0000000003971580; 1 drivers
+L_00000000039715c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003616b80_0 .net/2u *"_s8", 0 0, L_00000000039715c8; 1 drivers
+v0000000003616f40_0 .net "awake", 0 0, L_000000000380d820; 1 drivers
+v0000000003615a00_0 .net "buf_Q", 0 0, L_0000000003954500; 1 drivers
+v00000000036151e0_0 .net "cond0", 0 0, L_00000000039551b0; 1 drivers
+v0000000003615320_0 .net "cond1", 0 0, L_0000000003955450; 1 drivers
+v00000000036164a0_0 .var "notifier", 0 0;
+L_000000000380d820 .cmp/eeq 1, L_00000000038a2340, L_0000000003971580;
+L_000000000380eae0 .cmp/eeq 1, o000000000357ec28, L_00000000039715c8;
+L_000000000380f9e0 .cmp/eeq 1, o000000000357ebf8, L_0000000003971610;
+S_0000000002766a70 .scope module, "sky130_fd_sc_hd__dlxbn_1" "sky130_fd_sc_hd__dlxbn_1" 4 67766;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357f138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003618fc0_0 .net "D", 0 0, o000000000357f138; 0 drivers
+o000000000357f1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003619600_0 .net "GATE_N", 0 0, o000000000357f1c8; 0 drivers
+v0000000003618a20_0 .net "Q", 0 0, L_0000000003954dc0; 1 drivers
+v0000000003618ca0_0 .net "Q_N", 0 0, L_0000000003954180; 1 drivers
+L_00000000038a2180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003617ee0_0 .net8 "VGND", 0 0, L_00000000038a2180; 1 drivers, strength-aware
+L_00000000038a2810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003618980_0 .net8 "VNB", 0 0, L_00000000038a2810; 1 drivers, strength-aware
+L_00000000038a28f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003619920_0 .net8 "VPB", 0 0, L_00000000038a28f0; 1 drivers, strength-aware
+L_00000000038a21f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003619060_0 .net8 "VPWR", 0 0, L_00000000038a21f0; 1 drivers, strength-aware
+S_00000000034e6ab0 .scope module, "base" "sky130_fd_sc_hd__dlxbn" 4 67784, 4 67641 1, S_0000000002766a70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357f1f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954960 .functor NOT 1, o000000000357f1f8, C4<0>, C4<0>, C4<0>;
+o000000000357f168 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a22d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a25e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953b60 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357f168, L_0000000003954960, v0000000003619560_0, L_00000000038a22d0, L_00000000038a25e0;
+L_0000000003954dc0 .functor BUF 1, L_0000000003953b60, C4<0>, C4<0>, C4<0>;
+L_0000000003954180 .functor NOT 1, L_0000000003953b60, C4<0>, C4<0>, C4<0>;
+v0000000003617120_0 .net "D", 0 0, o000000000357f138; alias, 0 drivers
+v00000000036156e0_0 .net "D_delayed", 0 0, o000000000357f168; 0 drivers
+v0000000003615780_0 .net "GATE", 0 0, L_0000000003954960; 1 drivers
+v0000000003615820_0 .net "GATE_N", 0 0, o000000000357f1c8; alias, 0 drivers
+v0000000003615be0_0 .net "GATE_N_delayed", 0 0, o000000000357f1f8; 0 drivers
+v0000000003619740_0 .net "Q", 0 0, L_0000000003954dc0; alias, 1 drivers
+v000000000361a000_0 .net "Q_N", 0 0, L_0000000003954180; alias, 1 drivers
+v0000000003617a80_0 .net8 "VGND", 0 0, L_00000000038a25e0; 1 drivers, strength-aware
+L_00000000038a3680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036179e0_0 .net8 "VNB", 0 0, L_00000000038a3680; 1 drivers, strength-aware
+L_00000000038a26c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003619ba0_0 .net8 "VPB", 0 0, L_00000000038a26c0; 1 drivers, strength-aware
+v0000000003618200_0 .net8 "VPWR", 0 0, L_00000000038a22d0; 1 drivers, strength-aware
+v0000000003618de0_0 .net *"_s4", 31 0, L_000000000380fc60; 1 drivers
+L_0000000003971658 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000000003618f20_0 .net *"_s7", 30 0, L_0000000003971658; 1 drivers
+L_00000000039716a0 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000000003618e80_0 .net/2u *"_s8", 31 0, L_00000000039716a0; 1 drivers
+v0000000003619ce0_0 .net "awake", 0 0, L_0000000003810ca0; 1 drivers
+v0000000003619c40_0 .net "buf_Q", 0 0, L_0000000003953b60; 1 drivers
+v0000000003619560_0 .var "notifier", 0 0;
+L_000000000380fc60 .concat [ 1 31 0 0], L_00000000038a22d0, L_0000000003971658;
+L_0000000003810ca0 .cmp/eeq 32, L_000000000380fc60, L_00000000039716a0;
+S_0000000002766470 .scope module, "sky130_fd_sc_hd__dlxbn_2" "sky130_fd_sc_hd__dlxbn_2" 4 67878;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357f6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036185c0_0 .net "D", 0 0, o000000000357f6a8; 0 drivers
+o000000000357f738 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036180c0_0 .net "GATE_N", 0 0, o000000000357f738; 0 drivers
+v0000000003618340_0 .net "Q", 0 0, L_0000000003953930; 1 drivers
+v0000000003619ec0_0 .net "Q_N", 0 0, L_00000000039542d0; 1 drivers
+L_00000000038a2f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003617b20_0 .net8 "VGND", 0 0, L_00000000038a2f10; 1 drivers, strength-aware
+L_00000000038a23b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003618700_0 .net8 "VNB", 0 0, L_00000000038a23b0; 1 drivers, strength-aware
+L_00000000038a3760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003618840_0 .net8 "VPB", 0 0, L_00000000038a3760; 1 drivers, strength-aware
+L_00000000038a31b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003619b00_0 .net8 "VPWR", 0 0, L_00000000038a31b0; 1 drivers, strength-aware
+S_00000000034e6db0 .scope module, "base" "sky130_fd_sc_hd__dlxbn" 4 67896, 4 67641 1, S_0000000002766470;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE_N"
+o000000000357f768 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954570 .functor NOT 1, o000000000357f768, C4<0>, C4<0>, C4<0>;
+o000000000357f6d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a2ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a3bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953bd0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357f6d8, L_0000000003954570, v00000000036196a0_0, L_00000000038a2ab0, L_00000000038a3bc0;
+L_0000000003953930 .functor BUF 1, L_0000000003953bd0, C4<0>, C4<0>, C4<0>;
+L_00000000039542d0 .functor NOT 1, L_0000000003953bd0, C4<0>, C4<0>, C4<0>;
+v00000000036187a0_0 .net "D", 0 0, o000000000357f6a8; alias, 0 drivers
+v00000000036197e0_0 .net "D_delayed", 0 0, o000000000357f6d8; 0 drivers
+v0000000003617da0_0 .net "GATE", 0 0, L_0000000003954570; 1 drivers
+v0000000003619240_0 .net "GATE_N", 0 0, o000000000357f738; alias, 0 drivers
+v0000000003619100_0 .net "GATE_N_delayed", 0 0, o000000000357f768; 0 drivers
+v0000000003617f80_0 .net "Q", 0 0, L_0000000003953930; alias, 1 drivers
+v00000000036191a0_0 .net "Q_N", 0 0, L_00000000039542d0; alias, 1 drivers
+v0000000003619d80_0 .net8 "VGND", 0 0, L_00000000038a3bc0; 1 drivers, strength-aware
+L_00000000038a3530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003618520_0 .net8 "VNB", 0 0, L_00000000038a3530; 1 drivers, strength-aware
+L_00000000038a3290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003618660_0 .net8 "VPB", 0 0, L_00000000038a3290; 1 drivers, strength-aware
+v00000000036199c0_0 .net8 "VPWR", 0 0, L_00000000038a2ab0; 1 drivers, strength-aware
+v0000000003618020_0 .net *"_s4", 31 0, L_0000000003810d40; 1 drivers
+L_00000000039716e8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000000003619420_0 .net *"_s7", 30 0, L_00000000039716e8; 1 drivers
+L_0000000003971730 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000000003619a60_0 .net/2u *"_s8", 31 0, L_0000000003971730; 1 drivers
+v0000000003618ac0_0 .net "awake", 0 0, L_0000000003810020; 1 drivers
+v00000000036192e0_0 .net "buf_Q", 0 0, L_0000000003953bd0; 1 drivers
+v00000000036196a0_0 .var "notifier", 0 0;
+L_0000000003810d40 .concat [ 1 31 0 0], L_00000000038a2ab0, L_00000000039716e8;
+L_0000000003810020 .cmp/eeq 32, L_0000000003810d40, L_0000000003971730;
+S_0000000002766bf0 .scope module, "sky130_fd_sc_hd__dlxbp_1" "sky130_fd_sc_hd__dlxbp_1" 4 43581;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357fc18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003617940_0 .net "D", 0 0, o000000000357fc18; 0 drivers
+o000000000357fc78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003617bc0_0 .net "GATE", 0 0, o000000000357fc78; 0 drivers
+v000000000361a0a0_0 .net "Q", 0 0, L_0000000003953e00; 1 drivers
+v0000000003617e40_0 .net "Q_N", 0 0, L_0000000003954c00; 1 drivers
+L_00000000038a37d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003618480_0 .net8 "VGND", 0 0, L_00000000038a37d0; 1 drivers, strength-aware
+L_00000000038a34c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361c260_0 .net8 "VNB", 0 0, L_00000000038a34c0; 1 drivers, strength-aware
+L_00000000038a2b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361c8a0_0 .net8 "VPB", 0 0, L_00000000038a2b20; 1 drivers, strength-aware
+L_00000000038a2960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361b040_0 .net8 "VPWR", 0 0, L_00000000038a2960; 1 drivers, strength-aware
+S_00000000034e9db0 .scope module, "base" "sky130_fd_sc_hd__dlxbp" 4 43599, 4 43895 1, S_0000000002766bf0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "GATE"
+o000000000357fc48 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000357fca8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a33e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a3610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003955060 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o000000000357fc48, o000000000357fca8, v0000000003619f60_0, L_00000000038a33e0, L_00000000038a3610;
+L_0000000003953e00 .functor BUF 1, L_0000000003955060, C4<0>, C4<0>, C4<0>;
+L_0000000003954c00 .functor NOT 1, L_0000000003955060, C4<0>, C4<0>, C4<0>;
+v00000000036188e0_0 .net "D", 0 0, o000000000357fc18; alias, 0 drivers
+v0000000003617c60_0 .net "D_delayed", 0 0, o000000000357fc48; 0 drivers
+v00000000036182a0_0 .net "GATE", 0 0, o000000000357fc78; alias, 0 drivers
+v0000000003618c00_0 .net "GATE_delayed", 0 0, o000000000357fca8; 0 drivers
+v0000000003617d00_0 .net "Q", 0 0, L_0000000003953e00; alias, 1 drivers
+v0000000003618b60_0 .net "Q_N", 0 0, L_0000000003954c00; alias, 1 drivers
+v0000000003618160_0 .net8 "VGND", 0 0, L_00000000038a3610; 1 drivers, strength-aware
+L_00000000038a29d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003618d40_0 .net8 "VNB", 0 0, L_00000000038a29d0; 1 drivers, strength-aware
+L_00000000038a2570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003619380_0 .net8 "VPB", 0 0, L_00000000038a2570; 1 drivers, strength-aware
+v0000000003619880_0 .net8 "VPWR", 0 0, L_00000000038a33e0; 1 drivers, strength-aware
+L_0000000003971778 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036194c0_0 .net/2u *"_s4", 0 0, L_0000000003971778; 1 drivers
+v00000000036183e0_0 .net "awake", 0 0, L_00000000038107a0; 1 drivers
+v0000000003619e20_0 .net "buf_Q", 0 0, L_0000000003955060; 1 drivers
+v0000000003619f60_0 .var "notifier", 0 0;
+L_00000000038107a0 .cmp/eeq 1, L_00000000038a33e0, L_0000000003971778;
+S_00000000027674f0 .scope module, "sky130_fd_sc_hd__dlxtn_1" "sky130_fd_sc_hd__dlxtn_1" 4 26941;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o00000000035800f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361b4a0_0 .net "D", 0 0, o00000000035800f8; 0 drivers
+o0000000003580188 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361c300_0 .net "GATE_N", 0 0, o0000000003580188; 0 drivers
+v000000000361c1c0_0 .net "Q", 0 0, L_00000000039549d0; 1 drivers
+L_00000000038a2650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ba40_0 .net8 "VGND", 0 0, L_00000000038a2650; 1 drivers, strength-aware
+L_00000000038a2b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361c800_0 .net8 "VNB", 0 0, L_00000000038a2b90; 1 drivers, strength-aware
+L_00000000038a20a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361c760_0 .net8 "VPB", 0 0, L_00000000038a20a0; 1 drivers, strength-aware
+L_00000000038a3450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361ab40_0 .net8 "VPWR", 0 0, L_00000000038a3450; 1 drivers, strength-aware
+S_00000000034e8130 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 26957, 4 26717 1, S_00000000027674f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o00000000035801b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003953fc0 .functor NOT 1, o00000000035801b8, C4<0>, C4<0>, C4<0>;
+o0000000003580128 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a3920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a2ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953af0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003580128, L_0000000003953fc0, v000000000361a500_0, L_00000000038a3920, L_00000000038a2ce0;
+L_00000000039549d0 .functor BUF 1, L_0000000003953af0, C4<0>, C4<0>, C4<0>;
+v000000000361bae0_0 .net "D", 0 0, o00000000035800f8; alias, 0 drivers
+v000000000361bea0_0 .net "D_delayed", 0 0, o0000000003580128; 0 drivers
+v000000000361b180_0 .net "GATE", 0 0, L_0000000003953fc0; 1 drivers
+v000000000361a640_0 .net "GATE_N", 0 0, o0000000003580188; alias, 0 drivers
+v000000000361a6e0_0 .net "GATE_N_delayed", 0 0, o00000000035801b8; 0 drivers
+v000000000361c4e0_0 .net "Q", 0 0, L_00000000039549d0; alias, 1 drivers
+v000000000361b9a0_0 .net8 "VGND", 0 0, L_00000000038a2ce0; 1 drivers, strength-aware
+L_00000000038a2d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361b400_0 .net8 "VNB", 0 0, L_00000000038a2d50; 1 drivers, strength-aware
+L_00000000038a3840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361bb80_0 .net8 "VPB", 0 0, L_00000000038a3840; 1 drivers, strength-aware
+v000000000361a460_0 .net8 "VPWR", 0 0, L_00000000038a3920; 1 drivers, strength-aware
+L_00000000039717c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000361a140_0 .net/2u *"_s4", 0 0, L_00000000039717c0; 1 drivers
+v000000000361c580_0 .net "awake", 0 0, L_0000000003810f20; 1 drivers
+v000000000361bc20_0 .net "buf_Q", 0 0, L_0000000003953af0; 1 drivers
+v000000000361a500_0 .var "notifier", 0 0;
+L_0000000003810f20 .cmp/eeq 1, L_00000000038a3920, L_00000000039717c0;
+S_0000000002766d70 .scope module, "sky130_fd_sc_hd__dlxtn_2" "sky130_fd_sc_hd__dlxtn_2" 4 26835;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o0000000003580578 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361abe0_0 .net "D", 0 0, o0000000003580578; 0 drivers
+o0000000003580608 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361b0e0_0 .net "GATE_N", 0 0, o0000000003580608; 0 drivers
+v000000000361a820_0 .net "Q", 0 0, L_0000000003953a80; 1 drivers
+L_00000000038a2dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361bd60_0 .net8 "VGND", 0 0, L_00000000038a2dc0; 1 drivers, strength-aware
+L_00000000038a3990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ad20_0 .net8 "VNB", 0 0, L_00000000038a3990; 1 drivers, strength-aware
+L_00000000038a2e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361b7c0_0 .net8 "VPB", 0 0, L_00000000038a2e30; 1 drivers, strength-aware
+L_00000000038a3a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361a280_0 .net8 "VPWR", 0 0, L_00000000038a3a00; 1 drivers, strength-aware
+S_00000000034e7530 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 26851, 4 26717 1, S_0000000002766d70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o0000000003580638 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954030 .functor NOT 1, o0000000003580638, C4<0>, C4<0>, C4<0>;
+o00000000035805a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038a3ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038a2ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953a10 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o00000000035805a8, L_0000000003954030, v000000000361c620_0, L_00000000038a3ae0, L_00000000038a2ea0;
+L_0000000003953a80 .functor BUF 1, L_0000000003953a10, C4<0>, C4<0>, C4<0>;
+v000000000361c3a0_0 .net "D", 0 0, o0000000003580578; alias, 0 drivers
+v000000000361c440_0 .net "D_delayed", 0 0, o00000000035805a8; 0 drivers
+v000000000361bcc0_0 .net "GATE", 0 0, L_0000000003954030; 1 drivers
+v000000000361b540_0 .net "GATE_N", 0 0, o0000000003580608; alias, 0 drivers
+v000000000361b5e0_0 .net "GATE_N_delayed", 0 0, o0000000003580638; 0 drivers
+v000000000361a5a0_0 .net "Q", 0 0, L_0000000003953a80; alias, 1 drivers
+v000000000361a960_0 .net8 "VGND", 0 0, L_00000000038a2ea0; 1 drivers, strength-aware
+L_00000000038a3060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361bfe0_0 .net8 "VNB", 0 0, L_00000000038a3060; 1 drivers, strength-aware
+L_00000000038a3a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361a3c0_0 .net8 "VPB", 0 0, L_00000000038a3a70; 1 drivers, strength-aware
+v000000000361a1e0_0 .net8 "VPWR", 0 0, L_00000000038a3ae0; 1 drivers, strength-aware
+L_0000000003971808 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000361a320_0 .net/2u *"_s4", 0 0, L_0000000003971808; 1 drivers
+v000000000361a780_0 .net "awake", 0 0, L_000000000380fa80; 1 drivers
+v000000000361aa00_0 .net "buf_Q", 0 0, L_0000000003953a10; 1 drivers
+v000000000361c620_0 .var "notifier", 0 0;
+L_000000000380fa80 .cmp/eeq 1, L_00000000038a3ae0, L_0000000003971808;
+S_0000000002766770 .scope module, "sky130_fd_sc_hd__dlxtn_4" "sky130_fd_sc_hd__dlxtn_4" 4 27047;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o00000000035809f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361b220_0 .net "D", 0 0, o00000000035809f8; 0 drivers
+o0000000003580a88 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361c120_0 .net "GATE_N", 0 0, o0000000003580a88; 0 drivers
+v000000000361b2c0_0 .net "Q", 0 0, L_00000000039540a0; 1 drivers
+L_00000000038a3b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361c6c0_0 .net8 "VGND", 0 0, L_00000000038a3b50; 1 drivers, strength-aware
+L_00000000038a30d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361b360_0 .net8 "VNB", 0 0, L_00000000038a30d0; 1 drivers, strength-aware
+L_00000000038a3c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361e920_0 .net8 "VPB", 0 0, L_00000000038a3c30; 1 drivers, strength-aware
+L_00000000038c5370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361cb20_0 .net8 "VPWR", 0 0, L_00000000038c5370; 1 drivers, strength-aware
+S_00000000034e7b30 .scope module, "base" "sky130_fd_sc_hd__dlxtn" 4 27063, 4 26717 1, S_0000000002766770;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE_N"
+o0000000003580ab8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003954a40 .functor NOT 1, o0000000003580ab8, C4<0>, C4<0>, C4<0>;
+o0000000003580a28 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038c4490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038c4880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003953d20 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003580a28, L_0000000003954a40, v000000000361bf40_0, L_00000000038c4490, L_00000000038c4880;
+L_00000000039540a0 .functor BUF 1, L_0000000003953d20, C4<0>, C4<0>, C4<0>;
+v000000000361a8c0_0 .net "D", 0 0, o00000000035809f8; alias, 0 drivers
+v000000000361b680_0 .net "D_delayed", 0 0, o0000000003580a28; 0 drivers
+v000000000361aaa0_0 .net "GATE", 0 0, L_0000000003954a40; 1 drivers
+v000000000361b720_0 .net "GATE_N", 0 0, o0000000003580a88; alias, 0 drivers
+v000000000361ac80_0 .net "GATE_N_delayed", 0 0, o0000000003580ab8; 0 drivers
+v000000000361b860_0 .net "Q", 0 0, L_00000000039540a0; alias, 1 drivers
+v000000000361adc0_0 .net8 "VGND", 0 0, L_00000000038c4880; 1 drivers, strength-aware
+L_00000000038c4ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361b900_0 .net8 "VNB", 0 0, L_00000000038c4ce0; 1 drivers, strength-aware
+L_00000000038c45e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361c080_0 .net8 "VPB", 0 0, L_00000000038c45e0; 1 drivers, strength-aware
+v000000000361ae60_0 .net8 "VPWR", 0 0, L_00000000038c4490; 1 drivers, strength-aware
+L_0000000003971850 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000361af00_0 .net/2u *"_s4", 0 0, L_0000000003971850; 1 drivers
+v000000000361afa0_0 .net "awake", 0 0, L_0000000003810700; 1 drivers
+v000000000361be00_0 .net "buf_Q", 0 0, L_0000000003953d20; 1 drivers
+v000000000361bf40_0 .var "notifier", 0 0;
+L_0000000003810700 .cmp/eeq 1, L_00000000038c4490, L_0000000003971850;
+S_00000000027656f0 .scope module, "sky130_fd_sc_hd__dlxtp_1" "sky130_fd_sc_hd__dlxtp_1" 4 92369;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE"
+o0000000003580e78 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361d5c0_0 .net "D", 0 0, o0000000003580e78; 0 drivers
+o0000000003580ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361dfc0_0 .net "GATE", 0 0, o0000000003580ed8; 0 drivers
+v000000000361e600_0 .net "Q", 0 0, L_0000000003954340; 1 drivers
+L_00000000038c5060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361da20_0 .net8 "VGND", 0 0, L_00000000038c5060; 1 drivers, strength-aware
+L_00000000038c4ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361e560_0 .net8 "VNB", 0 0, L_00000000038c4ab0; 1 drivers, strength-aware
+L_00000000038c57d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361cf80_0 .net8 "VPB", 0 0, L_00000000038c57d0; 1 drivers, strength-aware
+L_00000000038c5c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361d700_0 .net8 "VPWR", 0 0, L_00000000038c5c30; 1 drivers, strength-aware
+S_00000000034e85b0 .scope module, "base" "sky130_fd_sc_hd__dlxtp" 4 92385, 4 92671 1, S_00000000027656f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "GATE"
+o0000000003580ea8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003580f08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038c48f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038c4d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039541f0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, o0000000003580ea8, o0000000003580f08, v000000000361d840_0, L_00000000038c48f0, L_00000000038c4d50;
+L_0000000003954340 .functor BUF 1, L_00000000039541f0, C4<0>, C4<0>, C4<0>;
+v000000000361dde0_0 .net "D", 0 0, o0000000003580e78; alias, 0 drivers
+v000000000361cee0_0 .net "D_delayed", 0 0, o0000000003580ea8; 0 drivers
+v000000000361de80_0 .net "GATE", 0 0, o0000000003580ed8; alias, 0 drivers
+v000000000361ca80_0 .net "GATE_delayed", 0 0, o0000000003580f08; 0 drivers
+v000000000361c9e0_0 .net "Q", 0 0, L_0000000003954340; alias, 1 drivers
+v000000000361eba0_0 .net8 "VGND", 0 0, L_00000000038c4d50; 1 drivers, strength-aware
+L_00000000038c4b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361d200_0 .net8 "VNB", 0 0, L_00000000038c4b20; 1 drivers, strength-aware
+L_00000000038c4650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361df20_0 .net8 "VPB", 0 0, L_00000000038c4650; 1 drivers, strength-aware
+v000000000361cbc0_0 .net8 "VPWR", 0 0, L_00000000038c48f0; 1 drivers, strength-aware
+L_0000000003971898 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v000000000361e420_0 .net/2u *"_s4", 0 0, L_0000000003971898; 1 drivers
+v000000000361d2a0_0 .net "awake", 0 0, L_00000000038100c0; 1 drivers
+v000000000361e100_0 .net "buf_Q", 0 0, L_00000000039541f0; 1 drivers
+v000000000361d840_0 .var "notifier", 0 0;
+L_00000000038100c0 .cmp/eeq 1, L_00000000038c48f0, L_0000000003971898;
+S_0000000002765870 .scope module, "sky130_fd_sc_hd__dlygate4sd1_1" "sky130_fd_sc_hd__dlygate4sd1_1" 4 88901;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000035812c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361d480_0 .net "A", 0 0, o00000000035812c8; 0 drivers
+L_00000000038c58b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ed80_0 .net8 "VGND", 0 0, L_00000000038c58b0; 1 drivers, strength-aware
+L_00000000038c4f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361eb00_0 .net8 "VNB", 0 0, L_00000000038c4f80; 1 drivers, strength-aware
+L_00000000038c5300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361d020_0 .net8 "VPB", 0 0, L_00000000038c5300; 1 drivers, strength-aware
+L_00000000038c4ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361eec0_0 .net8 "VPWR", 0 0, L_00000000038c4ff0; 1 drivers, strength-aware
+v000000000361e060_0 .net "X", 0 0, L_00000000039545e0; 1 drivers
+S_00000000034e88b0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd1" 4 88915, 4 89189 1, S_0000000002765870;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039550d0 .functor BUF 1, o00000000035812c8, C4<0>, C4<0>, C4<0>;
+L_00000000039545e0 .functor BUF 1, L_00000000039550d0, C4<0>, C4<0>, C4<0>;
+v000000000361d520_0 .net "A", 0 0, o00000000035812c8; alias, 0 drivers
+L_00000000038c47a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361e880_0 .net8 "VGND", 0 0, L_00000000038c47a0; 1 drivers, strength-aware
+L_00000000038c5140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361d7a0_0 .net8 "VNB", 0 0, L_00000000038c5140; 1 drivers, strength-aware
+L_00000000038c55a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361e7e0_0 .net8 "VPB", 0 0, L_00000000038c55a0; 1 drivers, strength-aware
+L_00000000038c4110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361dac0_0 .net8 "VPWR", 0 0, L_00000000038c4110; 1 drivers, strength-aware
+v000000000361d3e0_0 .net "X", 0 0, L_00000000039545e0; alias, 1 drivers
+v000000000361e6a0_0 .net "buf0_out_X", 0 0, L_00000000039550d0; 1 drivers
+S_0000000002765b70 .scope module, "sky130_fd_sc_hd__dlygate4sd2_1" "sky130_fd_sc_hd__dlygate4sd2_1" 4 33428;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003581598 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361d160_0 .net "A", 0 0, o0000000003581598; 0 drivers
+L_00000000038c4260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ece0_0 .net8 "VGND", 0 0, L_00000000038c4260; 1 drivers, strength-aware
+L_00000000038c5b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361e9c0_0 .net8 "VNB", 0 0, L_00000000038c5b50; 1 drivers, strength-aware
+L_00000000038c53e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361e380_0 .net8 "VPB", 0 0, L_00000000038c53e0; 1 drivers, strength-aware
+L_00000000038c5610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361e1a0_0 .net8 "VPWR", 0 0, L_00000000038c5610; 1 drivers, strength-aware
+v000000000361c940_0 .net "X", 0 0, L_0000000003954e30; 1 drivers
+S_00000000034e76b0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd2" 4 33442, 4 33322 1, S_0000000002765b70;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003954650 .functor BUF 1, o0000000003581598, C4<0>, C4<0>, C4<0>;
+L_0000000003954e30 .functor BUF 1, L_0000000003954650, C4<0>, C4<0>, C4<0>;
+v000000000361ee20_0 .net "A", 0 0, o0000000003581598; alias, 0 drivers
+L_00000000038c4420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361dca0_0 .net8 "VGND", 0 0, L_00000000038c4420; 1 drivers, strength-aware
+L_00000000038c50d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361e740_0 .net8 "VNB", 0 0, L_00000000038c50d0; 1 drivers, strength-aware
+L_00000000038c4960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361d660_0 .net8 "VPB", 0 0, L_00000000038c4960; 1 drivers, strength-aware
+L_00000000038c4a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361d0c0_0 .net8 "VPWR", 0 0, L_00000000038c4a40; 1 drivers, strength-aware
+v000000000361e2e0_0 .net "X", 0 0, L_0000000003954e30; alias, 1 drivers
+v000000000361d980_0 .net "buf0_out_X", 0 0, L_0000000003954650; 1 drivers
+S_0000000002765cf0 .scope module, "sky130_fd_sc_hd__dlygate4sd3_1" "sky130_fd_sc_hd__dlygate4sd3_1" 4 56297;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003581868 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361e240_0 .net "A", 0 0, o0000000003581868; 0 drivers
+L_00000000038c42d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361db60_0 .net8 "VGND", 0 0, L_00000000038c42d0; 1 drivers, strength-aware
+L_00000000038c5450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361dd40_0 .net8 "VNB", 0 0, L_00000000038c5450; 1 drivers, strength-aware
+L_00000000038c56f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361ef60_0 .net8 "VPB", 0 0, L_00000000038c56f0; 1 drivers, strength-aware
+L_00000000038c5bc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361e4c0_0 .net8 "VPWR", 0 0, L_00000000038c5bc0; 1 drivers, strength-aware
+v000000000361f0a0_0 .net "X", 0 0, L_00000000039547a0; 1 drivers
+S_00000000034e97b0 .scope module, "base" "sky130_fd_sc_hd__dlygate4sd3" 4 56311, 4 56191 1, S_0000000002765cf0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039546c0 .functor BUF 1, o0000000003581868, C4<0>, C4<0>, C4<0>;
+L_00000000039547a0 .functor BUF 1, L_00000000039546c0, C4<0>, C4<0>, C4<0>;
+v000000000361d340_0 .net "A", 0 0, o0000000003581868; alias, 0 drivers
+L_00000000038c5290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361dc00_0 .net8 "VGND", 0 0, L_00000000038c5290; 1 drivers, strength-aware
+L_00000000038c4b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ec40_0 .net8 "VNB", 0 0, L_00000000038c4b90; 1 drivers, strength-aware
+L_00000000038c51b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361ea60_0 .net8 "VPB", 0 0, L_00000000038c51b0; 1 drivers, strength-aware
+L_00000000038c5220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361cc60_0 .net8 "VPWR", 0 0, L_00000000038c5220; 1 drivers, strength-aware
+v000000000361f000_0 .net "X", 0 0, L_00000000039547a0; alias, 1 drivers
+v000000000361d8e0_0 .net "buf0_out_X", 0 0, L_00000000039546c0; 1 drivers
+S_00000000027668f0 .scope module, "sky130_fd_sc_hd__dlymetal6s2s_1" "sky130_fd_sc_hd__dlymetal6s2s_1" 4 84134;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003581b38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003620220_0 .net "A", 0 0, o0000000003581b38; 0 drivers
+L_00000000038c4dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620a40_0 .net8 "VGND", 0 0, L_00000000038c4dc0; 1 drivers, strength-aware
+L_00000000038c4730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621800_0 .net8 "VNB", 0 0, L_00000000038c4730; 1 drivers, strength-aware
+L_00000000038c4570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036207c0_0 .net8 "VPB", 0 0, L_00000000038c4570; 1 drivers, strength-aware
+L_00000000038c54c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036209a0_0 .net8 "VPWR", 0 0, L_00000000038c54c0; 1 drivers, strength-aware
+v00000000036204a0_0 .net "X", 0 0, L_0000000003954b20; 1 drivers
+S_00000000034e7fb0 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s2s" 4 84148, 4 84427 1, S_00000000027668f0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003954ab0 .functor BUF 1, o0000000003581b38, C4<0>, C4<0>, C4<0>;
+L_0000000003954b20 .functor BUF 1, L_0000000003954ab0, C4<0>, C4<0>, C4<0>;
+v000000000361cd00_0 .net "A", 0 0, o0000000003581b38; alias, 0 drivers
+L_00000000038c5920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361cda0_0 .net8 "VGND", 0 0, L_00000000038c5920; 1 drivers, strength-aware
+L_00000000038c4ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361ce40_0 .net8 "VNB", 0 0, L_00000000038c4ea0; 1 drivers, strength-aware
+L_00000000038c4500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361f3c0_0 .net8 "VPB", 0 0, L_00000000038c4500; 1 drivers, strength-aware
+L_00000000038c5530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036214e0_0 .net8 "VPWR", 0 0, L_00000000038c5530; 1 drivers, strength-aware
+v000000000361f820_0 .net "X", 0 0, L_0000000003954b20; alias, 1 drivers
+v0000000003620e00_0 .net "buf0_out_X", 0 0, L_0000000003954ab0; 1 drivers
+S_0000000002766ef0 .scope module, "sky130_fd_sc_hd__dlymetal6s4s_1" "sky130_fd_sc_hd__dlymetal6s4s_1" 4 9683;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003581e08 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361f780_0 .net "A", 0 0, o0000000003581e08; 0 drivers
+L_00000000038c4e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620ae0_0 .net8 "VGND", 0 0, L_00000000038c4e30; 1 drivers, strength-aware
+L_00000000038c4340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621260_0 .net8 "VNB", 0 0, L_00000000038c4340; 1 drivers, strength-aware
+L_00000000038c46c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361f1e0_0 .net8 "VPB", 0 0, L_00000000038c46c0; 1 drivers, strength-aware
+L_00000000038c40a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620b80_0 .net8 "VPWR", 0 0, L_00000000038c40a0; 1 drivers, strength-aware
+v000000000361ffa0_0 .net "X", 0 0, L_0000000003954ce0; 1 drivers
+S_00000000034e9930 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s4s" 4 9697, 4 9576 1, S_0000000002766ef0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003954c70 .functor BUF 1, o0000000003581e08, C4<0>, C4<0>, C4<0>;
+L_0000000003954ce0 .functor BUF 1, L_0000000003954c70, C4<0>, C4<0>, C4<0>;
+v000000000361f8c0_0 .net "A", 0 0, o0000000003581e08; alias, 0 drivers
+L_00000000038c4180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361fd20_0 .net8 "VGND", 0 0, L_00000000038c4180; 1 drivers, strength-aware
+L_00000000038c49d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361f960_0 .net8 "VNB", 0 0, L_00000000038c49d0; 1 drivers, strength-aware
+L_00000000038c5760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620860_0 .net8 "VPB", 0 0, L_00000000038c5760; 1 drivers, strength-aware
+L_00000000038c5680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361f460_0 .net8 "VPWR", 0 0, L_00000000038c5680; 1 drivers, strength-aware
+v0000000003620680_0 .net "X", 0 0, L_0000000003954ce0; alias, 1 drivers
+v000000000361f6e0_0 .net "buf0_out_X", 0 0, L_0000000003954c70; 1 drivers
+S_0000000002767070 .scope module, "sky130_fd_sc_hd__dlymetal6s6s_1" "sky130_fd_sc_hd__dlymetal6s6s_1" 4 73072;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000035820d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361f500_0 .net "A", 0 0, o00000000035820d8; 0 drivers
+L_00000000038c41f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036218a0_0 .net8 "VGND", 0 0, L_00000000038c41f0; 1 drivers, strength-aware
+L_00000000038c4c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621760_0 .net8 "VNB", 0 0, L_00000000038c4c00; 1 drivers, strength-aware
+L_00000000038c5840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036202c0_0 .net8 "VPB", 0 0, L_00000000038c5840; 1 drivers, strength-aware
+L_00000000038c43b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036205e0_0 .net8 "VPWR", 0 0, L_00000000038c43b0; 1 drivers, strength-aware
+v000000000361f640_0 .net "X", 0 0, L_0000000003955fb0; 1 drivers
+S_00000000034e9ab0 .scope module, "base" "sky130_fd_sc_hd__dlymetal6s6s" 4 73086, 4 72965 1, S_0000000002767070;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003956800 .functor BUF 1, o00000000035820d8, C4<0>, C4<0>, C4<0>;
+L_0000000003955fb0 .functor BUF 1, L_0000000003956800, C4<0>, C4<0>, C4<0>;
+v000000000361f140_0 .net "A", 0 0, o00000000035820d8; alias, 0 drivers
+L_00000000038c5990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621580_0 .net8 "VGND", 0 0, L_00000000038c5990; 1 drivers, strength-aware
+L_00000000038c4810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361f280_0 .net8 "VNB", 0 0, L_00000000038c4810; 1 drivers, strength-aware
+L_00000000038c5a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003621620_0 .net8 "VPB", 0 0, L_00000000038c5a00; 1 drivers, strength-aware
+L_00000000038c4c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361f5a0_0 .net8 "VPWR", 0 0, L_00000000038c4c70; 1 drivers, strength-aware
+v000000000361f320_0 .net "X", 0 0, L_0000000003955fb0; alias, 1 drivers
+v0000000003621300_0 .net "buf0_out_X", 0 0, L_0000000003956800; 1 drivers
+S_0000000002767370 .scope module, "sky130_fd_sc_hd__ebufn_1" "sky130_fd_sc_hd__ebufn_1" 4 48128;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o00000000035823a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036200e0_0 .net "A", 0 0, o00000000035823a8; 0 drivers
+o00000000035823d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000361fbe0_0 .net "TE_B", 0 0, o00000000035823d8; 0 drivers
+L_00000000038c4f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620c20_0 .net8 "VGND", 0 0, L_00000000038c4f10; 1 drivers, strength-aware
+L_00000000038c5a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620360_0 .net8 "VNB", 0 0, L_00000000038c5a70; 1 drivers, strength-aware
+L_00000000038c5ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361fc80_0 .net8 "VPB", 0 0, L_00000000038c5ae0; 1 drivers, strength-aware
+L_00000000038c6250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620040_0 .net8 "VPWR", 0 0, L_00000000038c6250; 1 drivers, strength-aware
+v0000000003620720_0 .net8 "Z", 0 0, L_0000000003956aa0; 1 drivers, strength-aware
+S_00000000034ea3b0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 48144, 4 48021 1, S_0000000002767370;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003956aa0 .functor BUFIF0 1, o00000000035823a8, o00000000035823d8, C4<0>, C4<0>;
+v0000000003620ea0_0 .net "A", 0 0, o00000000035823a8; alias, 0 drivers
+v00000000036211c0_0 .net "TE_B", 0 0, o00000000035823d8; alias, 0 drivers
+L_00000000038c66b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620540_0 .net8 "VGND", 0 0, L_00000000038c66b0; 1 drivers, strength-aware
+L_00000000038c65d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361fa00_0 .net8 "VNB", 0 0, L_00000000038c65d0; 1 drivers, strength-aware
+L_00000000038c7280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000361faa0_0 .net8 "VPB", 0 0, L_00000000038c7280; 1 drivers, strength-aware
+L_00000000038c7440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620f40_0 .net8 "VPWR", 0 0, L_00000000038c7440; 1 drivers, strength-aware
+v000000000361fb40_0 .net8 "Z", 0 0, L_0000000003956aa0; alias, 1 drivers, strength-aware
+S_0000000002769500 .scope module, "sky130_fd_sc_hd__ebufn_2" "sky130_fd_sc_hd__ebufn_2" 4 47728;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o00000000035826d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003620d60_0 .net "A", 0 0, o00000000035826d8; 0 drivers
+o0000000003582708 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003620fe0_0 .net "TE_B", 0 0, o0000000003582708; 0 drivers
+L_00000000038c7050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621080_0 .net8 "VGND", 0 0, L_00000000038c7050; 1 drivers, strength-aware
+L_00000000038c6720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621120_0 .net8 "VNB", 0 0, L_00000000038c6720; 1 drivers, strength-aware
+L_00000000038c7670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036213a0_0 .net8 "VPB", 0 0, L_00000000038c7670; 1 drivers, strength-aware
+L_00000000038c7360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003621440_0 .net8 "VPWR", 0 0, L_00000000038c7360; 1 drivers, strength-aware
+v00000000036216c0_0 .net8 "Z", 0 0, L_0000000003956e20; 1 drivers, strength-aware
+S_00000000034e82b0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47744, 4 48021 1, S_0000000002769500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003956e20 .functor BUFIF0 1, o00000000035826d8, o0000000003582708, C4<0>, C4<0>;
+v000000000361fdc0_0 .net "A", 0 0, o00000000035826d8; alias, 0 drivers
+v000000000361ff00_0 .net "TE_B", 0 0, o0000000003582708; alias, 0 drivers
+L_00000000038c6870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000361fe60_0 .net8 "VGND", 0 0, L_00000000038c6870; 1 drivers, strength-aware
+L_00000000038c6d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003620180_0 .net8 "VNB", 0 0, L_00000000038c6d40; 1 drivers, strength-aware
+L_00000000038c7130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620400_0 .net8 "VPB", 0 0, L_00000000038c7130; 1 drivers, strength-aware
+L_00000000038c6480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003620900_0 .net8 "VPWR", 0 0, L_00000000038c6480; 1 drivers, strength-aware
+v0000000003620cc0_0 .net8 "Z", 0 0, L_0000000003956e20; alias, 1 drivers, strength-aware
+S_0000000002768300 .scope module, "sky130_fd_sc_hd__ebufn_4" "sky130_fd_sc_hd__ebufn_4" 4 47622;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003582a08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003622700_0 .net "A", 0 0, o0000000003582a08; 0 drivers
+o0000000003582a38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036239c0_0 .net "TE_B", 0 0, o0000000003582a38; 0 drivers
+L_00000000038c6a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036228e0_0 .net8 "VGND", 0 0, L_00000000038c6a30; 1 drivers, strength-aware
+L_00000000038c6c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003622980_0 .net8 "VNB", 0 0, L_00000000038c6c60; 1 drivers, strength-aware
+L_00000000038c6aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003622520_0 .net8 "VPB", 0 0, L_00000000038c6aa0; 1 drivers, strength-aware
+L_00000000038c64f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003623880_0 .net8 "VPWR", 0 0, L_00000000038c64f0; 1 drivers, strength-aware
+v00000000036222a0_0 .net8 "Z", 0 0, L_0000000003955ed0; 1 drivers, strength-aware
+S_00000000034e8430 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47638, 4 48021 1, S_0000000002768300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003955ed0 .functor BUFIF0 1, o0000000003582a08, o0000000003582a38, C4<0>, C4<0>;
+v0000000003622840_0 .net "A", 0 0, o0000000003582a08; alias, 0 drivers
+v0000000003623740_0 .net "TE_B", 0 0, o0000000003582a38; alias, 0 drivers
+L_00000000038c6560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036225c0_0 .net8 "VGND", 0 0, L_00000000038c6560; 1 drivers, strength-aware
+L_00000000038c6f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003622f20_0 .net8 "VNB", 0 0, L_00000000038c6f70; 1 drivers, strength-aware
+L_00000000038c7600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003623240_0 .net8 "VPB", 0 0, L_00000000038c7600; 1 drivers, strength-aware
+L_00000000038c7590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003623920_0 .net8 "VPWR", 0 0, L_00000000038c7590; 1 drivers, strength-aware
+v0000000003621b20_0 .net8 "Z", 0 0, L_0000000003955ed0; alias, 1 drivers, strength-aware
+S_0000000002767700 .scope module, "sky130_fd_sc_hd__ebufn_8" "sky130_fd_sc_hd__ebufn_8" 4 47516;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003582d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003621f80_0 .net "A", 0 0, o0000000003582d38; 0 drivers
+o0000000003582d68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036240a0_0 .net "TE_B", 0 0, o0000000003582d68; 0 drivers
+L_00000000038c77c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036232e0_0 .net8 "VGND", 0 0, L_00000000038c77c0; 1 drivers, strength-aware
+L_00000000038c6bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036227a0_0 .net8 "VNB", 0 0, L_00000000038c6bf0; 1 drivers, strength-aware
+L_00000000038c6640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003622b60_0 .net8 "VPB", 0 0, L_00000000038c6640; 1 drivers, strength-aware
+L_00000000038c7210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003621da0_0 .net8 "VPWR", 0 0, L_00000000038c7210; 1 drivers, strength-aware
+v0000000003622c00_0 .net8 "Z", 0 0, L_0000000003956870; 1 drivers, strength-aware
+S_00000000034e8bb0 .scope module, "base" "sky130_fd_sc_hd__ebufn" 4 47532, 4 48021 1, S_0000000002767700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003956870 .functor BUFIF0 1, o0000000003582d38, o0000000003582d68, C4<0>, C4<0>;
+v0000000003623560_0 .net "A", 0 0, o0000000003582d38; alias, 0 drivers
+v0000000003622660_0 .net "TE_B", 0 0, o0000000003582d68; alias, 0 drivers
+L_00000000038c6170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036231a0_0 .net8 "VGND", 0 0, L_00000000038c6170; 1 drivers, strength-aware
+L_00000000038c68e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621940_0 .net8 "VNB", 0 0, L_00000000038c68e0; 1 drivers, strength-aware
+L_00000000038c7830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003623b00_0 .net8 "VPB", 0 0, L_00000000038c7830; 1 drivers, strength-aware
+L_00000000038c6950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003622020_0 .net8 "VPWR", 0 0, L_00000000038c6950; 1 drivers, strength-aware
+v0000000003623ec0_0 .net8 "Z", 0 0, L_0000000003956870; alias, 1 drivers, strength-aware
+S_0000000002767e80 .scope module, "sky130_fd_sc_hd__edfxbp_1" "sky130_fd_sc_hd__edfxbp_1" 4 19397;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+o0000000003583068 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036223e0_0 .net "CLK", 0 0, o0000000003583068; 0 drivers
+o00000000035830c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003622a20_0 .net "D", 0 0, o00000000035830c8; 0 drivers
+o00000000035830f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003621e40_0 .net "DE", 0 0, o00000000035830f8; 0 drivers
+v00000000036234c0_0 .net "Q", 0 0, L_0000000003955a70; 1 drivers
+v0000000003622fc0_0 .net "Q_N", 0 0, L_0000000003956db0; 1 drivers
+L_00000000038c62c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003623060_0 .net8 "VGND", 0 0, L_00000000038c62c0; 1 drivers, strength-aware
+L_00000000038c5d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003621a80_0 .net8 "VNB", 0 0, L_00000000038c5d10; 1 drivers, strength-aware
+L_00000000038c6790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003621bc0_0 .net8 "VPB", 0 0, L_00000000038c6790; 1 drivers, strength-aware
+L_00000000038c6330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003622480_0 .net8 "VPWR", 0 0, L_00000000038c6330; 1 drivers, strength-aware
+S_00000000034ea530 .scope module, "base" "sky130_fd_sc_hd__edfxbp" 4 19417, 4 19264 1, S_0000000002767e80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+o0000000003583158 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003583128 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003955530 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_00000000039558b0, o0000000003583158, o0000000003583128;
+o0000000003583098 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038c63a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038c7750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039558b0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000003955530, o0000000003583098, v0000000003622200_0, L_00000000038c63a0, L_00000000038c7750;
+L_00000000039570c0 .functor AND 1, L_00000000038120a0, L_0000000003810480, C4<1>, C4<1>;
+L_0000000003955a70 .functor BUF 1, L_00000000039558b0, C4<0>, C4<0>, C4<0>;
+L_0000000003956db0 .functor NOT 1, L_00000000039558b0, C4<0>, C4<0>, C4<0>;
+v0000000003624000_0 .net "CLK", 0 0, o0000000003583068; alias, 0 drivers
+v0000000003623f60_0 .net "CLK_delayed", 0 0, o0000000003583098; 0 drivers
+v0000000003622ac0_0 .net "D", 0 0, o00000000035830c8; alias, 0 drivers
+v0000000003622340_0 .net "DE", 0 0, o00000000035830f8; alias, 0 drivers
+v0000000003621c60_0 .net "DE_delayed", 0 0, o0000000003583128; 0 drivers
+v0000000003622ca0_0 .net "D_delayed", 0 0, o0000000003583158; 0 drivers
+v0000000003623a60_0 .net "Q", 0 0, L_0000000003955a70; alias, 1 drivers
+v0000000003623100_0 .net "Q_N", 0 0, L_0000000003956db0; alias, 1 drivers
+v0000000003622de0_0 .net8 "VGND", 0 0, L_00000000038c7750; 1 drivers, strength-aware
+L_00000000038c6800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003623ce0_0 .net8 "VNB", 0 0, L_00000000038c6800; 1 drivers, strength-aware
+L_00000000038c69c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003622d40_0 .net8 "VPB", 0 0, L_00000000038c69c0; 1 drivers, strength-aware
+v0000000003622e80_0 .net8 "VPWR", 0 0, L_00000000038c63a0; 1 drivers, strength-aware
+v0000000003623380_0 .net *"_s10", 0 0, L_0000000003810480; 1 drivers
+L_00000000039718e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003623420_0 .net/2u *"_s4", 0 0, L_00000000039718e0; 1 drivers
+L_0000000003971928 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000036237e0_0 .net/2u *"_s8", 0 0, L_0000000003971928; 1 drivers
+v00000000036220c0_0 .net "awake", 0 0, L_00000000038120a0; 1 drivers
+v00000000036219e0_0 .net "buf_Q", 0 0, L_00000000039558b0; 1 drivers
+v0000000003623d80_0 .net "cond0", 0 0, L_00000000039570c0; 1 drivers
+v0000000003622160_0 .net "mux_out", 0 0, L_0000000003955530; 1 drivers
+v0000000003622200_0 .var "notifier", 0 0;
+L_00000000038120a0 .cmp/eeq 1, L_00000000038c63a0, L_00000000039718e0;
+L_0000000003810480 .cmp/eeq 1, o0000000003583128, L_0000000003971928;
+S_0000000002768180 .scope module, "sky130_fd_sc_hd__edfxtp_1" "sky130_fd_sc_hd__edfxtp_1" 4 96363;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+o00000000035836c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036246e0_0 .net "CLK", 0 0, o00000000035836c8; 0 drivers
+o0000000003583728 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003625180_0 .net "D", 0 0, o0000000003583728; 0 drivers
+o0000000003583758 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003624780_0 .net "DE", 0 0, o0000000003583758; 0 drivers
+v0000000003625e00_0 .net "Q", 0 0, L_0000000003955ae0; 1 drivers
+L_00000000038c6410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003625040_0 .net8 "VGND", 0 0, L_00000000038c6410; 1 drivers, strength-aware
+L_00000000038c6b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003624500_0 .net8 "VNB", 0 0, L_00000000038c6b10; 1 drivers, strength-aware
+L_00000000038c6b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003626080_0 .net8 "VPB", 0 0, L_00000000038c6b80; 1 drivers, strength-aware
+L_00000000038c6cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624aa0_0 .net8 "VPWR", 0 0, L_00000000038c6cd0; 1 drivers, strength-aware
+S_00000000034eab30 .scope module, "base" "sky130_fd_sc_hd__edfxtp" 4 96381, 4 96236 1, S_0000000002768180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+o00000000035837b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003583788 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039555a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_0000000003956100, o00000000035837b8, o0000000003583788;
+o00000000035836f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038c5fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038c6db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003956100 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_00000000039555a0, o00000000035836f8, v0000000003625c20_0, L_00000000038c5fb0, L_00000000038c6db0;
+L_00000000039568e0 .functor AND 1, L_000000000380fd00, L_0000000003811e20, C4<1>, C4<1>;
+L_0000000003955ae0 .functor BUF 1, L_0000000003956100, C4<0>, C4<0>, C4<0>;
+v0000000003621d00_0 .net "CLK", 0 0, o00000000035836c8; alias, 0 drivers
+v0000000003621ee0_0 .net "CLK_delayed", 0 0, o00000000035836f8; 0 drivers
+v0000000003623ba0_0 .net "D", 0 0, o0000000003583728; alias, 0 drivers
+v0000000003623600_0 .net "DE", 0 0, o0000000003583758; alias, 0 drivers
+v00000000036236a0_0 .net "DE_delayed", 0 0, o0000000003583788; 0 drivers
+v0000000003623e20_0 .net "D_delayed", 0 0, o00000000035837b8; 0 drivers
+v0000000003623c40_0 .net "Q", 0 0, L_0000000003955ae0; alias, 1 drivers
+v0000000003626800_0 .net8 "VGND", 0 0, L_00000000038c6db0; 1 drivers, strength-aware
+L_00000000038c6e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626760_0 .net8 "VNB", 0 0, L_00000000038c6e20; 1 drivers, strength-aware
+L_00000000038c6e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003625a40_0 .net8 "VPB", 0 0, L_00000000038c6e90; 1 drivers, strength-aware
+v00000000036255e0_0 .net8 "VPWR", 0 0, L_00000000038c5fb0; 1 drivers, strength-aware
+v0000000003624a00_0 .net *"_s10", 0 0, L_0000000003811e20; 1 drivers
+L_0000000003971970 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003625900_0 .net/2u *"_s4", 0 0, L_0000000003971970; 1 drivers
+L_00000000039719b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003625d60_0 .net/2u *"_s8", 0 0, L_00000000039719b8; 1 drivers
+v0000000003625220_0 .net "awake", 0 0, L_000000000380fd00; 1 drivers
+v0000000003624dc0_0 .net "buf_Q", 0 0, L_0000000003956100; 1 drivers
+v0000000003624c80_0 .net "cond0", 0 0, L_00000000039568e0; 1 drivers
+v0000000003625ae0_0 .net "mux_out", 0 0, L_00000000039555a0; 1 drivers
+v0000000003625c20_0 .var "notifier", 0 0;
+L_000000000380fd00 .cmp/eeq 1, L_00000000038c5fb0, L_0000000003971970;
+L_0000000003811e20 .cmp/eeq 1, o0000000003583788, L_00000000039719b8;
+S_0000000002768780 .scope module, "sky130_fd_sc_hd__einvn_0" "sky130_fd_sc_hd__einvn_0" 4 52738;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003583c98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003626260_0 .net "A", 0 0, o0000000003583c98; 0 drivers
+o0000000003583cc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036252c0_0 .net "TE_B", 0 0, o0000000003583cc8; 0 drivers
+L_00000000038c5ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626620_0 .net8 "VGND", 0 0, L_00000000038c5ca0; 1 drivers, strength-aware
+L_00000000038c6f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036254a0_0 .net8 "VNB", 0 0, L_00000000038c6f00; 1 drivers, strength-aware
+L_00000000038c71a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624e60_0 .net8 "VPB", 0 0, L_00000000038c71a0; 1 drivers, strength-aware
+L_00000000038c5ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003625ea0_0 .net8 "VPWR", 0 0, L_00000000038c5ed0; 1 drivers, strength-aware
+v0000000003625b80_0 .net "Z", 0 0, L_00000000039563a0; 1 drivers
+S_00000000034e7830 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52754, 4 53243 1, S_0000000002768780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_00000000039563a0 .functor NOTIF0 1, o0000000003583c98, o0000000003583cc8, C4<0>, C4<0>;
+v00000000036259a0_0 .net "A", 0 0, o0000000003583c98; alias, 0 drivers
+v0000000003624820_0 .net "TE_B", 0 0, o0000000003583cc8; alias, 0 drivers
+L_00000000038c61e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036248c0_0 .net8 "VGND", 0 0, L_00000000038c61e0; 1 drivers, strength-aware
+L_00000000038c6fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003624d20_0 .net8 "VNB", 0 0, L_00000000038c6fe0; 1 drivers, strength-aware
+L_00000000038c7520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624280_0 .net8 "VPB", 0 0, L_00000000038c7520; 1 drivers, strength-aware
+L_00000000038c5f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036261c0_0 .net8 "VPWR", 0 0, L_00000000038c5f40; 1 drivers, strength-aware
+v0000000003624960_0 .net "Z", 0 0, L_00000000039563a0; alias, 1 drivers
+S_0000000002768480 .scope module, "sky130_fd_sc_hd__einvn_1" "sky130_fd_sc_hd__einvn_1" 4 52950;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003583fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003625f40_0 .net "A", 0 0, o0000000003583fc8; 0 drivers
+o0000000003583ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003625fe0_0 .net "TE_B", 0 0, o0000000003583ff8; 0 drivers
+L_00000000038c70c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003625400_0 .net8 "VGND", 0 0, L_00000000038c70c0; 1 drivers, strength-aware
+L_00000000038c5d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626300_0 .net8 "VNB", 0 0, L_00000000038c5d80; 1 drivers, strength-aware
+L_00000000038c72f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036250e0_0 .net8 "VPB", 0 0, L_00000000038c72f0; 1 drivers, strength-aware
+L_00000000038c73d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624640_0 .net8 "VPWR", 0 0, L_00000000038c73d0; 1 drivers, strength-aware
+v0000000003625540_0 .net "Z", 0 0, L_0000000003955920; 1 drivers
+S_00000000034e8a30 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52966, 4 53243 1, S_0000000002768480;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003955920 .functor NOTIF0 1, o0000000003583fc8, o0000000003583ff8, C4<0>, C4<0>;
+v0000000003624b40_0 .net "A", 0 0, o0000000003583fc8; alias, 0 drivers
+v00000000036264e0_0 .net "TE_B", 0 0, o0000000003583ff8; alias, 0 drivers
+L_00000000038c74b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626120_0 .net8 "VGND", 0 0, L_00000000038c74b0; 1 drivers, strength-aware
+L_00000000038c76e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003625cc0_0 .net8 "VNB", 0 0, L_00000000038c76e0; 1 drivers, strength-aware
+L_00000000038c5df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036257c0_0 .net8 "VPB", 0 0, L_00000000038c5df0; 1 drivers, strength-aware
+L_00000000038c5e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624140_0 .net8 "VPWR", 0 0, L_00000000038c5e60; 1 drivers, strength-aware
+v0000000003625360_0 .net "Z", 0 0, L_0000000003955920; alias, 1 drivers
+S_0000000002767b80 .scope module, "sky130_fd_sc_hd__einvn_2" "sky130_fd_sc_hd__einvn_2" 4 53350;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o00000000035842f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003625860_0 .net "A", 0 0, o00000000035842f8; 0 drivers
+o0000000003584328 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003624320_0 .net "TE_B", 0 0, o0000000003584328; 0 drivers
+L_00000000038c6020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626440_0 .net8 "VGND", 0 0, L_00000000038c6020; 1 drivers, strength-aware
+L_00000000038c6090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036243c0_0 .net8 "VNB", 0 0, L_00000000038c6090; 1 drivers, strength-aware
+L_00000000038c6100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036268a0_0 .net8 "VPB", 0 0, L_00000000038c6100; 1 drivers, strength-aware
+L_00000000038c82b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036245a0_0 .net8 "VPWR", 0 0, L_00000000038c82b0; 1 drivers, strength-aware
+v0000000003626580_0 .net "Z", 0 0, L_0000000003956330; 1 drivers
+S_00000000034e9330 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 53366, 4 53243 1, S_0000000002767b80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003956330 .functor NOTIF0 1, o00000000035842f8, o0000000003584328, C4<0>, C4<0>;
+v0000000003624f00_0 .net "A", 0 0, o00000000035842f8; alias, 0 drivers
+v0000000003624be0_0 .net "TE_B", 0 0, o0000000003584328; alias, 0 drivers
+L_00000000038c8fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003624fa0_0 .net8 "VGND", 0 0, L_00000000038c8fd0; 1 drivers, strength-aware
+L_00000000038c9430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003625680_0 .net8 "VNB", 0 0, L_00000000038c9430; 1 drivers, strength-aware
+L_00000000038c8010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003625720_0 .net8 "VPB", 0 0, L_00000000038c8010; 1 drivers, strength-aware
+L_00000000038c8400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003624460_0 .net8 "VPWR", 0 0, L_00000000038c8400; 1 drivers, strength-aware
+v00000000036263a0_0 .net "Z", 0 0, L_0000000003956330; alias, 1 drivers
+S_0000000002768600 .scope module, "sky130_fd_sc_hd__einvn_4" "sky130_fd_sc_hd__einvn_4" 4 52844;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003584628 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036289c0_0 .net "A", 0 0, o0000000003584628; 0 drivers
+o0000000003584658 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003627840_0 .net "TE_B", 0 0, o0000000003584658; 0 drivers
+L_00000000038c8630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036278e0_0 .net8 "VGND", 0 0, L_00000000038c8630; 1 drivers, strength-aware
+L_00000000038c9190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626d00_0 .net8 "VNB", 0 0, L_00000000038c9190; 1 drivers, strength-aware
+L_00000000038c7d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628880_0 .net8 "VPB", 0 0, L_00000000038c7d70; 1 drivers, strength-aware
+L_00000000038c7bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036277a0_0 .net8 "VPWR", 0 0, L_00000000038c7bb0; 1 drivers, strength-aware
+v0000000003628100_0 .net "Z", 0 0, L_00000000039557d0; 1 drivers
+S_00000000034e9630 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 52860, 4 53243 1, S_0000000002768600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_00000000039557d0 .functor NOTIF0 1, o0000000003584628, o0000000003584658, C4<0>, C4<0>;
+v00000000036266c0_0 .net "A", 0 0, o0000000003584628; alias, 0 drivers
+v00000000036241e0_0 .net "TE_B", 0 0, o0000000003584658; alias, 0 drivers
+L_00000000038c7f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003627f20_0 .net8 "VGND", 0 0, L_00000000038c7f30; 1 drivers, strength-aware
+L_00000000038c7c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628600_0 .net8 "VNB", 0 0, L_00000000038c7c90; 1 drivers, strength-aware
+L_00000000038c8240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628920_0 .net8 "VPB", 0 0, L_00000000038c8240; 1 drivers, strength-aware
+L_00000000038c8ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628560_0 .net8 "VPWR", 0 0, L_00000000038c8ef0; 1 drivers, strength-aware
+v0000000003627fc0_0 .net "Z", 0 0, L_00000000039557d0; alias, 1 drivers
+S_0000000002768c00 .scope module, "sky130_fd_sc_hd__einvn_8" "sky130_fd_sc_hd__einvn_8" 4 53456;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+o0000000003584958 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036290a0_0 .net "A", 0 0, o0000000003584958; 0 drivers
+o0000000003584988 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036282e0_0 .net "TE_B", 0 0, o0000000003584988; 0 drivers
+L_00000000038c8470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036275c0_0 .net8 "VGND", 0 0, L_00000000038c8470; 1 drivers, strength-aware
+L_00000000038c84e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003627480_0 .net8 "VNB", 0 0, L_00000000038c84e0; 1 drivers, strength-aware
+L_00000000038c7fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003626c60_0 .net8 "VPB", 0 0, L_00000000038c7fa0; 1 drivers, strength-aware
+L_00000000038c8a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628380_0 .net8 "VPWR", 0 0, L_00000000038c8a20; 1 drivers, strength-aware
+v00000000036270c0_0 .net "Z", 0 0, L_0000000003956e90; 1 drivers
+S_00000000034e8730 .scope module, "base" "sky130_fd_sc_hd__einvn" 4 53472, 4 53243 1, S_0000000002768c00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE_B"
+L_0000000003956e90 .functor NOTIF0 1, o0000000003584958, o0000000003584988, C4<0>, C4<0>;
+v0000000003627520_0 .net "A", 0 0, o0000000003584958; alias, 0 drivers
+v00000000036281a0_0 .net "TE_B", 0 0, o0000000003584988; alias, 0 drivers
+L_00000000038c7c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626940_0 .net8 "VGND", 0 0, L_00000000038c7c20; 1 drivers, strength-aware
+L_00000000038c7d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626a80_0 .net8 "VNB", 0 0, L_00000000038c7d00; 1 drivers, strength-aware
+L_00000000038c7a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627020_0 .net8 "VPB", 0 0, L_00000000038c7a60; 1 drivers, strength-aware
+L_00000000038c8b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003626ee0_0 .net8 "VPWR", 0 0, L_00000000038c8b70; 1 drivers, strength-aware
+v0000000003627e80_0 .net "Z", 0 0, L_0000000003956e90; alias, 1 drivers
+S_0000000002768900 .scope module, "sky130_fd_sc_hd__einvp_1" "sky130_fd_sc_hd__einvp_1" 4 100473;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+o0000000003584c88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036272a0_0 .net "A", 0 0, o0000000003584c88; 0 drivers
+o0000000003584cb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003627c00_0 .net "TE", 0 0, o0000000003584cb8; 0 drivers
+L_00000000038c7b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628b00_0 .net8 "VGND", 0 0, L_00000000038c7b40; 1 drivers, strength-aware
+L_00000000038c7910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628a60_0 .net8 "VNB", 0 0, L_00000000038c7910; 1 drivers, strength-aware
+L_00000000038c8080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003626b20_0 .net8 "VPB", 0 0, L_00000000038c8080; 1 drivers, strength-aware
+L_00000000038c80f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003629000_0 .net8 "VPWR", 0 0, L_00000000038c80f0; 1 drivers, strength-aware
+v0000000003627980_0 .net "Z", 0 0, L_0000000003956090; 1 drivers
+S_00000000034eacb0 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100489, 4 100978 1, S_0000000002768900;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+L_0000000003956090 .functor NOTIF1 1, o0000000003584c88, o0000000003584cb8, C4<0>, C4<0>;
+v0000000003627660_0 .net "A", 0 0, o0000000003584c88; alias, 0 drivers
+v0000000003628240_0 .net "TE", 0 0, o0000000003584cb8; alias, 0 drivers
+L_00000000038c7980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628c40_0 .net8 "VGND", 0 0, L_00000000038c7980; 1 drivers, strength-aware
+L_00000000038c7de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628060_0 .net8 "VNB", 0 0, L_00000000038c7de0; 1 drivers, strength-aware
+L_00000000038c8e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036286a0_0 .net8 "VPB", 0 0, L_00000000038c8e80; 1 drivers, strength-aware
+L_00000000038c7ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627a20_0 .net8 "VPWR", 0 0, L_00000000038c7ec0; 1 drivers, strength-aware
+v0000000003627700_0 .net "Z", 0 0, L_0000000003956090; alias, 1 drivers
+S_0000000002768d80 .scope module, "sky130_fd_sc_hd__einvp_2" "sky130_fd_sc_hd__einvp_2" 4 100579;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+o0000000003584fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003628740_0 .net "A", 0 0, o0000000003584fb8; 0 drivers
+o0000000003584fe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003627ac0_0 .net "TE", 0 0, o0000000003584fe8; 0 drivers
+L_00000000038c79f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626bc0_0 .net8 "VGND", 0 0, L_00000000038c79f0; 1 drivers, strength-aware
+L_00000000038c8710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626f80_0 .net8 "VNB", 0 0, L_00000000038c8710; 1 drivers, strength-aware
+L_00000000038c7ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627160_0 .net8 "VPB", 0 0, L_00000000038c7ad0; 1 drivers, strength-aware
+L_00000000038c8f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628e20_0 .net8 "VPWR", 0 0, L_00000000038c8f60; 1 drivers, strength-aware
+v00000000036287e0_0 .net "Z", 0 0, L_0000000003955f40; 1 drivers
+S_00000000034e9030 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100595, 4 100978 1, S_0000000002768d80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+L_0000000003955f40 .functor NOTIF1 1, o0000000003584fb8, o0000000003584fe8, C4<0>, C4<0>;
+v0000000003627b60_0 .net "A", 0 0, o0000000003584fb8; alias, 0 drivers
+v0000000003628ba0_0 .net "TE", 0 0, o0000000003584fe8; alias, 0 drivers
+L_00000000038c89b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628ce0_0 .net8 "VGND", 0 0, L_00000000038c89b0; 1 drivers, strength-aware
+L_00000000038c93c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003628420_0 .net8 "VNB", 0 0, L_00000000038c93c0; 1 drivers, strength-aware
+L_00000000038c8d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003628d80_0 .net8 "VPB", 0 0, L_00000000038c8d30; 1 drivers, strength-aware
+L_00000000038c8a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627d40_0 .net8 "VPWR", 0 0, L_00000000038c8a90; 1 drivers, strength-aware
+v00000000036284c0_0 .net "Z", 0 0, L_0000000003955f40; alias, 1 drivers
+S_0000000002767880 .scope module, "sky130_fd_sc_hd__einvp_4" "sky130_fd_sc_hd__einvp_4" 4 100367;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+o00000000035852e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036273e0_0 .net "A", 0 0, o00000000035852e8; 0 drivers
+o0000000003585318 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036269e0_0 .net "TE", 0 0, o0000000003585318; 0 drivers
+L_00000000038c8320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626e40_0 .net8 "VGND", 0 0, L_00000000038c8320; 1 drivers, strength-aware
+L_00000000038c9040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362a9a0_0 .net8 "VNB", 0 0, L_00000000038c9040; 1 drivers, strength-aware
+L_00000000038c8cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003629d20_0 .net8 "VPB", 0 0, L_00000000038c8cc0; 1 drivers, strength-aware
+L_00000000038c8390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362a7c0_0 .net8 "VPWR", 0 0, L_00000000038c8390; 1 drivers, strength-aware
+v0000000003629140_0 .net "Z", 0 0, L_0000000003955a00; 1 drivers
+S_00000000034e91b0 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100383, 4 100978 1, S_0000000002767880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+L_0000000003955a00 .functor NOTIF1 1, o00000000035852e8, o0000000003585318, C4<0>, C4<0>;
+v0000000003627200_0 .net "A", 0 0, o00000000035852e8; alias, 0 drivers
+v0000000003628ec0_0 .net "TE", 0 0, o0000000003585318; alias, 0 drivers
+L_00000000038c8160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003627ca0_0 .net8 "VGND", 0 0, L_00000000038c8160; 1 drivers, strength-aware
+L_00000000038c8e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003626da0_0 .net8 "VNB", 0 0, L_00000000038c8e10; 1 drivers, strength-aware
+L_00000000038c81d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627de0_0 .net8 "VPB", 0 0, L_00000000038c81d0; 1 drivers, strength-aware
+L_00000000038c7e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003627340_0 .net8 "VPWR", 0 0, L_00000000038c7e50; 1 drivers, strength-aware
+v0000000003628f60_0 .net "Z", 0 0, L_0000000003955a00; alias, 1 drivers
+S_0000000002768f00 .scope module, "sky130_fd_sc_hd__einvp_8" "sky130_fd_sc_hd__einvp_8" 4 100685;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+o0000000003585618 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362b3a0_0 .net "A", 0 0, o0000000003585618; 0 drivers
+o0000000003585648 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362b800_0 .net "TE", 0 0, o0000000003585648; 0 drivers
+L_00000000038c8940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003629280_0 .net8 "VGND", 0 0, L_00000000038c8940; 1 drivers, strength-aware
+L_00000000038c8550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362ac20_0 .net8 "VNB", 0 0, L_00000000038c8550; 1 drivers, strength-aware
+L_00000000038c85c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003629c80_0 .net8 "VPB", 0 0, L_00000000038c85c0; 1 drivers, strength-aware
+L_00000000038c78a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362a900_0 .net8 "VPWR", 0 0, L_00000000038c78a0; 1 drivers, strength-aware
+v000000000362a040_0 .net "Z", 0 0, L_0000000003956170; 1 drivers
+S_00000000034e7cb0 .scope module, "base" "sky130_fd_sc_hd__einvp" 4 100701, 4 100978 1, S_0000000002768f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Z"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "TE"
+L_0000000003956170 .functor NOTIF1 1, o0000000003585618, o0000000003585648, C4<0>, C4<0>;
+v000000000362b8a0_0 .net "A", 0 0, o0000000003585618; alias, 0 drivers
+v000000000362a540_0 .net "TE", 0 0, o0000000003585648; alias, 0 drivers
+L_00000000038c8be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003629460_0 .net8 "VGND", 0 0, L_00000000038c8be0; 1 drivers, strength-aware
+L_00000000038c86a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362a680_0 .net8 "VNB", 0 0, L_00000000038c86a0; 1 drivers, strength-aware
+L_00000000038c8780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036296e0_0 .net8 "VPB", 0 0, L_00000000038c8780; 1 drivers, strength-aware
+L_00000000038c8b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362a720_0 .net8 "VPWR", 0 0, L_00000000038c8b00; 1 drivers, strength-aware
+v0000000003629960_0 .net "Z", 0 0, L_0000000003956170; alias, 1 drivers
+S_0000000002768a80 .scope module, "sky130_fd_sc_hd__fa_1" "sky130_fd_sc_hd__fa_1" 4 55192;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+o0000000003585948 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362b580_0 .net "A", 0 0, o0000000003585948; 0 drivers
+o0000000003585978 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362b300_0 .net "B", 0 0, o0000000003585978; 0 drivers
+o00000000035859a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003629820_0 .net "CIN", 0 0, o00000000035859a8; 0 drivers
+v00000000036298c0_0 .net "COUT", 0 0, L_0000000003956480; 1 drivers
+v000000000362a860_0 .net "SUM", 0 0, L_0000000003955840; 1 drivers
+L_00000000038c8c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003629a00_0 .net8 "VGND", 0 0, L_00000000038c8c50; 1 drivers, strength-aware
+L_00000000038c87f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036295a0_0 .net8 "VNB", 0 0, L_00000000038c87f0; 1 drivers, strength-aware
+L_00000000038c90b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362a180_0 .net8 "VPB", 0 0, L_00000000038c90b0; 1 drivers, strength-aware
+L_00000000038c8860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362acc0_0 .net8 "VPWR", 0 0, L_00000000038c8860; 1 drivers, strength-aware
+S_00000000034e8d30 .scope module, "base" "sky130_fd_sc_hd__fa" 4 55212, 4 55556 1, S_0000000002768a80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+L_00000000039565d0 .functor OR 1, o00000000035859a8, o0000000003585978, C4<0>, C4<0>;
+L_0000000003955d10 .functor AND 1, L_00000000039565d0, o0000000003585948, C4<1>, C4<1>;
+L_00000000039562c0 .functor AND 1, o0000000003585978, o00000000035859a8, C4<1>, C4<1>;
+L_00000000039564f0 .functor OR 1, L_00000000039562c0, L_0000000003955d10, C4<0>, C4<0>;
+L_0000000003956480 .functor BUF 1, L_00000000039564f0, C4<0>, C4<0>, C4<0>;
+L_0000000003956020 .functor AND 1, o00000000035859a8, o0000000003585948, o0000000003585978, C4<1>;
+L_0000000003955d80 .functor NOR 1, o0000000003585948, L_00000000039565d0, C4<0>, C4<0>;
+L_0000000003956f00 .functor NOR 1, L_0000000003955d80, L_0000000003956480, C4<0>, C4<0>;
+L_0000000003956410 .functor OR 1, L_0000000003956f00, L_0000000003956020, C4<0>, C4<0>;
+L_0000000003955840 .functor BUF 1, L_0000000003956410, C4<0>, C4<0>, C4<0>;
+v000000000362aa40_0 .net "A", 0 0, o0000000003585948; alias, 0 drivers
+v000000000362b120_0 .net "B", 0 0, o0000000003585978; alias, 0 drivers
+v000000000362ad60_0 .net "CIN", 0 0, o00000000035859a8; alias, 0 drivers
+v0000000003629780_0 .net "COUT", 0 0, L_0000000003956480; alias, 1 drivers
+v0000000003629f00_0 .net "SUM", 0 0, L_0000000003955840; alias, 1 drivers
+L_00000000038c9200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362b1c0_0 .net8 "VGND", 0 0, L_00000000038c9200; 1 drivers, strength-aware
+L_00000000038c88d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362a5e0_0 .net8 "VNB", 0 0, L_00000000038c88d0; 1 drivers, strength-aware
+L_00000000038c8da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362ae00_0 .net8 "VPB", 0 0, L_00000000038c8da0; 1 drivers, strength-aware
+L_00000000038c9120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362a0e0_0 .net8 "VPWR", 0 0, L_00000000038c9120; 1 drivers, strength-aware
+v0000000003629500_0 .net "and0_out", 0 0, L_0000000003955d10; 1 drivers
+v000000000362b080_0 .net "and1_out", 0 0, L_00000000039562c0; 1 drivers
+v0000000003629aa0_0 .net "and2_out", 0 0, L_0000000003956020; 1 drivers
+v000000000362aae0_0 .net "nor0_out", 0 0, L_0000000003955d80; 1 drivers
+v000000000362afe0_0 .net "nor1_out", 0 0, L_0000000003956f00; 1 drivers
+v000000000362a220_0 .net "or0_out", 0 0, L_00000000039565d0; 1 drivers
+v0000000003629640_0 .net "or1_out_COUT", 0 0, L_00000000039564f0; 1 drivers
+v000000000362ab80_0 .net "or2_out_SUM", 0 0, L_0000000003956410; 1 drivers
+S_0000000002767a00 .scope module, "sky130_fd_sc_hd__fa_2" "sky130_fd_sc_hd__fa_2" 4 54956;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+o0000000003585f18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036293c0_0 .net "A", 0 0, o0000000003585f18; 0 drivers
+o0000000003585f48 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362a360_0 .net "B", 0 0, o0000000003585f48; 0 drivers
+o0000000003585f78 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362a4a0_0 .net "CIN", 0 0, o0000000003585f78; 0 drivers
+v000000000362c2a0_0 .net "COUT", 0 0, L_0000000003955ca0; 1 drivers
+v000000000362bc60_0 .net "SUM", 0 0, L_0000000003955760; 1 drivers
+L_00000000038c9270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362cc00_0 .net8 "VGND", 0 0, L_00000000038c9270; 1 drivers, strength-aware
+L_00000000038c92e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362d9c0_0 .net8 "VNB", 0 0, L_00000000038c92e0; 1 drivers, strength-aware
+L_00000000038c9350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362d100_0 .net8 "VPB", 0 0, L_00000000038c9350; 1 drivers, strength-aware
+L_00000000038cad20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362d1a0_0 .net8 "VPWR", 0 0, L_00000000038cad20; 1 drivers, strength-aware
+S_00000000034e9c30 .scope module, "base" "sky130_fd_sc_hd__fa" 4 54976, 4 55556 1, S_0000000002767a00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+L_00000000039556f0 .functor OR 1, o0000000003585f78, o0000000003585f48, C4<0>, C4<0>;
+L_0000000003956950 .functor AND 1, L_00000000039556f0, o0000000003585f18, C4<1>, C4<1>;
+L_0000000003956b10 .functor AND 1, o0000000003585f48, o0000000003585f78, C4<1>, C4<1>;
+L_00000000039561e0 .functor OR 1, L_0000000003956b10, L_0000000003956950, C4<0>, C4<0>;
+L_0000000003955ca0 .functor BUF 1, L_00000000039561e0, C4<0>, C4<0>, C4<0>;
+L_0000000003955610 .functor AND 1, o0000000003585f78, o0000000003585f18, o0000000003585f48, C4<1>;
+L_0000000003955680 .functor NOR 1, o0000000003585f18, L_00000000039556f0, C4<0>, C4<0>;
+L_0000000003956250 .functor NOR 1, L_0000000003955680, L_0000000003955ca0, C4<0>, C4<0>;
+L_0000000003956640 .functor OR 1, L_0000000003956250, L_0000000003955610, C4<0>, C4<0>;
+L_0000000003955760 .functor BUF 1, L_0000000003956640, C4<0>, C4<0>, C4<0>;
+v000000000362aea0_0 .net "A", 0 0, o0000000003585f18; alias, 0 drivers
+v000000000362a2c0_0 .net "B", 0 0, o0000000003585f48; alias, 0 drivers
+v0000000003629b40_0 .net "CIN", 0 0, o0000000003585f78; alias, 0 drivers
+v000000000362af40_0 .net "COUT", 0 0, L_0000000003955ca0; alias, 1 drivers
+v000000000362b4e0_0 .net "SUM", 0 0, L_0000000003955760; alias, 1 drivers
+L_00000000038ca8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362b260_0 .net8 "VGND", 0 0, L_00000000038ca8c0; 1 drivers, strength-aware
+L_00000000038c9f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362b440_0 .net8 "VNB", 0 0, L_00000000038c9f90; 1 drivers, strength-aware
+L_00000000038c9ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362b620_0 .net8 "VPB", 0 0, L_00000000038c9ba0; 1 drivers, strength-aware
+L_00000000038c9b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003629be0_0 .net8 "VPWR", 0 0, L_00000000038c9b30; 1 drivers, strength-aware
+v000000000362b6c0_0 .net "and0_out", 0 0, L_0000000003956950; 1 drivers
+v000000000362b760_0 .net "and1_out", 0 0, L_0000000003956b10; 1 drivers
+v00000000036291e0_0 .net "and2_out", 0 0, L_0000000003955610; 1 drivers
+v0000000003629dc0_0 .net "nor0_out", 0 0, L_0000000003955680; 1 drivers
+v0000000003629320_0 .net "nor1_out", 0 0, L_0000000003956250; 1 drivers
+v0000000003629e60_0 .net "or0_out", 0 0, L_00000000039556f0; 1 drivers
+v000000000362a400_0 .net "or1_out_COUT", 0 0, L_00000000039561e0; 1 drivers
+v0000000003629fa0_0 .net "or2_out_SUM", 0 0, L_0000000003956640; 1 drivers
+S_0000000002767d00 .scope module, "sky130_fd_sc_hd__fa_4" "sky130_fd_sc_hd__fa_4" 4 55074;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+o00000000035864e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362e000_0 .net "A", 0 0, o00000000035864e8; 0 drivers
+o0000000003586518 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362cfc0_0 .net "B", 0 0, o0000000003586518; 0 drivers
+o0000000003586548 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362df60_0 .net "CIN", 0 0, o0000000003586548; 0 drivers
+v000000000362bee0_0 .net "COUT", 0 0, L_0000000003956560; 1 drivers
+v000000000362bbc0_0 .net "SUM", 0 0, L_0000000003955bc0; 1 drivers
+L_00000000038ca850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362e0a0_0 .net8 "VGND", 0 0, L_00000000038ca850; 1 drivers, strength-aware
+L_00000000038ca620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362c200_0 .net8 "VNB", 0 0, L_00000000038ca620; 1 drivers, strength-aware
+L_00000000038cad90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362c3e0_0 .net8 "VPB", 0 0, L_00000000038cad90; 1 drivers, strength-aware
+L_00000000038ca2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362d7e0_0 .net8 "VPWR", 0 0, L_00000000038ca2a0; 1 drivers, strength-aware
+S_00000000034e94b0 .scope module, "base" "sky130_fd_sc_hd__fa" 4 55094, 4 55556 1, S_0000000002767d00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+L_0000000003956720 .functor OR 1, o0000000003586548, o0000000003586518, C4<0>, C4<0>;
+L_0000000003955990 .functor AND 1, L_0000000003956720, o00000000035864e8, C4<1>, C4<1>;
+L_0000000003956f70 .functor AND 1, o0000000003586518, o0000000003586548, C4<1>, C4<1>;
+L_00000000039569c0 .functor OR 1, L_0000000003956f70, L_0000000003955990, C4<0>, C4<0>;
+L_0000000003956560 .functor BUF 1, L_00000000039569c0, C4<0>, C4<0>, C4<0>;
+L_00000000039566b0 .functor AND 1, o0000000003586548, o00000000035864e8, o0000000003586518, C4<1>;
+L_0000000003955b50 .functor NOR 1, o00000000035864e8, L_0000000003956720, C4<0>, C4<0>;
+L_0000000003956790 .functor NOR 1, L_0000000003955b50, L_0000000003956560, C4<0>, C4<0>;
+L_0000000003956b80 .functor OR 1, L_0000000003956790, L_00000000039566b0, C4<0>, C4<0>;
+L_0000000003955bc0 .functor BUF 1, L_0000000003956b80, C4<0>, C4<0>, C4<0>;
+v000000000362cac0_0 .net "A", 0 0, o00000000035864e8; alias, 0 drivers
+v000000000362db00_0 .net "B", 0 0, o0000000003586518; alias, 0 drivers
+v000000000362d240_0 .net "CIN", 0 0, o0000000003586548; alias, 0 drivers
+v000000000362d600_0 .net "COUT", 0 0, L_0000000003956560; alias, 1 drivers
+v000000000362dce0_0 .net "SUM", 0 0, L_0000000003955bc0; alias, 1 drivers
+L_00000000038ca700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362c340_0 .net8 "VGND", 0 0, L_00000000038ca700; 1 drivers, strength-aware
+L_00000000038ca770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362dd80_0 .net8 "VNB", 0 0, L_00000000038ca770; 1 drivers, strength-aware
+L_00000000038caa10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362bd00_0 .net8 "VPB", 0 0, L_00000000038caa10; 1 drivers, strength-aware
+L_00000000038ca690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362c160_0 .net8 "VPWR", 0 0, L_00000000038ca690; 1 drivers, strength-aware
+v000000000362d6a0_0 .net "and0_out", 0 0, L_0000000003955990; 1 drivers
+v000000000362c0c0_0 .net "and1_out", 0 0, L_0000000003956f70; 1 drivers
+v000000000362b940_0 .net "and2_out", 0 0, L_00000000039566b0; 1 drivers
+v000000000362bb20_0 .net "nor0_out", 0 0, L_0000000003955b50; 1 drivers
+v000000000362c8e0_0 .net "nor1_out", 0 0, L_0000000003956790; 1 drivers
+v000000000362c020_0 .net "or0_out", 0 0, L_0000000003956720; 1 drivers
+v000000000362d740_0 .net "or1_out_COUT", 0 0, L_00000000039569c0; 1 drivers
+v000000000362d420_0 .net "or2_out_SUM", 0 0, L_0000000003956b80; 1 drivers
+S_0000000002768000 .scope module, "sky130_fd_sc_hd__fah_1" "sky130_fd_sc_hd__fah_1" 4 13757;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CI"
+o0000000003586ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362d920_0 .net "A", 0 0, o0000000003586ab8; 0 drivers
+o0000000003586ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362cb60_0 .net "B", 0 0, o0000000003586ae8; 0 drivers
+o0000000003586b18 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362cca0_0 .net "CI", 0 0, o0000000003586b18; 0 drivers
+v000000000362c520_0 .net "COUT", 0 0, L_0000000003955df0; 1 drivers
+v000000000362c980_0 .net "SUM", 0 0, L_0000000003956a30; 1 drivers
+L_00000000038ca070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362c5c0_0 .net8 "VGND", 0 0, L_00000000038ca070; 1 drivers, strength-aware
+L_00000000038cae00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362cd40_0 .net8 "VNB", 0 0, L_00000000038cae00; 1 drivers, strength-aware
+L_00000000038c9820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362c660_0 .net8 "VPB", 0 0, L_00000000038c9820; 1 drivers, strength-aware
+L_00000000038ca000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362d060_0 .net8 "VPWR", 0 0, L_00000000038ca000; 1 drivers, strength-aware
+S_00000000034e79b0 .scope module, "base" "sky130_fd_sc_hd__fah" 4 13777, 4 14103 1, S_0000000002768000;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CI"
+L_0000000003955c30 .functor XOR 1, o0000000003586ab8, o0000000003586ae8, o0000000003586b18, C4<0>;
+L_0000000003956a30 .functor BUF 1, L_0000000003955c30, C4<0>, C4<0>, C4<0>;
+L_0000000003956bf0 .functor AND 1, o0000000003586ab8, o0000000003586ae8, C4<1>, C4<1>;
+L_0000000003956c60 .functor AND 1, o0000000003586ab8, o0000000003586b18, C4<1>, C4<1>;
+L_0000000003956cd0 .functor AND 1, o0000000003586ae8, o0000000003586b18, C4<1>, C4<1>;
+L_0000000003956d40 .functor OR 1, L_0000000003956bf0, L_0000000003956c60, L_0000000003956cd0, C4<0>;
+L_0000000003955df0 .functor BUF 1, L_0000000003956d40, C4<0>, C4<0>, C4<0>;
+v000000000362bf80_0 .net "A", 0 0, o0000000003586ab8; alias, 0 drivers
+v000000000362ce80_0 .net "B", 0 0, o0000000003586ae8; alias, 0 drivers
+v000000000362ba80_0 .net "CI", 0 0, o0000000003586b18; alias, 0 drivers
+v000000000362d880_0 .net "COUT", 0 0, L_0000000003955df0; alias, 1 drivers
+v000000000362dba0_0 .net "SUM", 0 0, L_0000000003956a30; alias, 1 drivers
+L_00000000038ca930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362b9e0_0 .net8 "VGND", 0 0, L_00000000038ca930; 1 drivers, strength-aware
+L_00000000038c9660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362bda0_0 .net8 "VNB", 0 0, L_00000000038c9660; 1 drivers, strength-aware
+L_00000000038caf50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362cf20_0 .net8 "VPB", 0 0, L_00000000038caf50; 1 drivers, strength-aware
+L_00000000038cae70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362d4c0_0 .net8 "VPWR", 0 0, L_00000000038cae70; 1 drivers, strength-aware
+v000000000362c480_0 .net "a_b", 0 0, L_0000000003956bf0; 1 drivers
+v000000000362d2e0_0 .net "a_ci", 0 0, L_0000000003956c60; 1 drivers
+v000000000362c840_0 .net "b_ci", 0 0, L_0000000003956cd0; 1 drivers
+v000000000362be40_0 .net "or0_out_COUT", 0 0, L_0000000003956d40; 1 drivers
+v000000000362ca20_0 .net "xor0_out_SUM", 0 0, L_0000000003955c30; 1 drivers
+S_0000000002769080 .scope module, "sky130_fd_sc_hd__fahcin_1" "sky130_fd_sc_hd__fahcin_1" 4 59360;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+o0000000003586ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362ed20_0 .net "A", 0 0, o0000000003586ff8; 0 drivers
+o0000000003587028 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362e8c0_0 .net "B", 0 0, o0000000003587028; 0 drivers
+o0000000003587058 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362eb40_0 .net "CIN", 0 0, o0000000003587058; 0 drivers
+v00000000036306c0_0 .net "COUT", 0 0, L_0000000003958be0; 1 drivers
+v000000000362e1e0_0 .net "SUM", 0 0, L_0000000003957050; 1 drivers
+L_00000000038caa80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362edc0_0 .net8 "VGND", 0 0, L_00000000038caa80; 1 drivers, strength-aware
+L_00000000038ca310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362efa0_0 .net8 "VNB", 0 0, L_00000000038ca310; 1 drivers, strength-aware
+L_00000000038ca1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630120_0 .net8 "VPB", 0 0, L_00000000038ca1c0; 1 drivers, strength-aware
+L_00000000038ca7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630440_0 .net8 "VPWR", 0 0, L_00000000038ca7e0; 1 drivers, strength-aware
+S_00000000034e9f30 .scope module, "base" "sky130_fd_sc_hd__fahcin" 4 59380, 4 59228 1, S_0000000002769080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CIN"
+L_0000000003956fe0 .functor NOT 1, o0000000003587058, C4<0>, C4<0>, C4<0>;
+L_0000000003955e60 .functor XOR 1, o0000000003586ff8, o0000000003587028, L_0000000003956fe0, C4<0>;
+L_0000000003957050 .functor BUF 1, L_0000000003955e60, C4<0>, C4<0>, C4<0>;
+L_0000000003957590 .functor AND 1, o0000000003586ff8, o0000000003587028, C4<1>, C4<1>;
+L_0000000003958b70 .functor AND 1, o0000000003586ff8, L_0000000003956fe0, C4<1>, C4<1>;
+L_00000000039571a0 .functor AND 1, o0000000003587028, L_0000000003956fe0, C4<1>, C4<1>;
+L_0000000003958c50 .functor OR 1, L_0000000003957590, L_0000000003958b70, L_00000000039571a0, C4<0>;
+L_0000000003958be0 .functor BUF 1, L_0000000003958c50, C4<0>, C4<0>, C4<0>;
+v000000000362c700_0 .net "A", 0 0, o0000000003586ff8; alias, 0 drivers
+v000000000362d560_0 .net "B", 0 0, o0000000003587028; alias, 0 drivers
+v000000000362c7a0_0 .net "CIN", 0 0, o0000000003587058; alias, 0 drivers
+v000000000362d380_0 .net "COUT", 0 0, L_0000000003958be0; alias, 1 drivers
+v000000000362de20_0 .net "SUM", 0 0, L_0000000003957050; alias, 1 drivers
+L_00000000038ca9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362dc40_0 .net8 "VGND", 0 0, L_00000000038ca9a0; 1 drivers, strength-aware
+L_00000000038caee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362cde0_0 .net8 "VNB", 0 0, L_00000000038caee0; 1 drivers, strength-aware
+L_00000000038c9d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362da60_0 .net8 "VPB", 0 0, L_00000000038c9d60; 1 drivers, strength-aware
+L_00000000038ca5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362dec0_0 .net8 "VPWR", 0 0, L_00000000038ca5b0; 1 drivers, strength-aware
+v000000000362fc20_0 .net "a_b", 0 0, L_0000000003957590; 1 drivers
+v000000000362e780_0 .net "a_ci", 0 0, L_0000000003958b70; 1 drivers
+v000000000362e500_0 .net "b_ci", 0 0, L_00000000039571a0; 1 drivers
+v000000000362f180_0 .net "ci", 0 0, L_0000000003956fe0; 1 drivers
+v000000000362fae0_0 .net "or0_out_COUT", 0 0, L_0000000003958c50; 1 drivers
+v000000000362fea0_0 .net "xor0_out_SUM", 0 0, L_0000000003955e60; 1 drivers
+S_0000000002769200 .scope module, "sky130_fd_sc_hd__fahcon_1" "sky130_fd_sc_hd__fahcon_1" 4 11458;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT_N"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CI"
+o0000000003587568 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362f360_0 .net "A", 0 0, o0000000003587568; 0 drivers
+o0000000003587598 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362ee60_0 .net "B", 0 0, o0000000003587598; 0 drivers
+o00000000035875c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000362f7c0_0 .net "CI", 0 0, o00000000035875c8; 0 drivers
+v000000000362fa40_0 .net "COUT_N", 0 0, L_0000000003957c20; 1 drivers
+v000000000362ef00_0 .net "SUM", 0 0, L_0000000003958400; 1 drivers
+L_00000000038caaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362e960_0 .net8 "VGND", 0 0, L_00000000038caaf0; 1 drivers, strength-aware
+L_00000000038cab60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362ff40_0 .net8 "VNB", 0 0, L_00000000038cab60; 1 drivers, strength-aware
+L_00000000038cafc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362fcc0_0 .net8 "VPB", 0 0, L_00000000038cafc0; 1 drivers, strength-aware
+L_00000000038c96d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362ea00_0 .net8 "VPWR", 0 0, L_00000000038c96d0; 1 drivers, strength-aware
+S_00000000034ea9b0 .scope module, "base" "sky130_fd_sc_hd__fahcon" 4 11478, 4 11328 1, S_0000000002769200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT_N"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+ .port_info 4 /INPUT 1 "CI"
+L_00000000039586a0 .functor XOR 1, o0000000003587568, o0000000003587598, o00000000035875c8, C4<0>;
+L_0000000003958400 .functor BUF 1, L_00000000039586a0, C4<0>, C4<0>, C4<0>;
+L_0000000003957e50 .functor NOR 1, o0000000003587568, o0000000003587598, C4<0>, C4<0>;
+L_0000000003957d00 .functor NOR 1, o0000000003587568, o00000000035875c8, C4<0>, C4<0>;
+L_0000000003958710 .functor NOR 1, o0000000003587598, o00000000035875c8, C4<0>, C4<0>;
+L_0000000003958780 .functor OR 1, L_0000000003957e50, L_0000000003957d00, L_0000000003958710, C4<0>;
+L_0000000003957c20 .functor BUF 1, L_0000000003958780, C4<0>, C4<0>, C4<0>;
+v000000000362f900_0 .net "A", 0 0, o0000000003587568; alias, 0 drivers
+v000000000362e5a0_0 .net "B", 0 0, o0000000003587598; alias, 0 drivers
+v000000000362e280_0 .net "CI", 0 0, o00000000035875c8; alias, 0 drivers
+v000000000362fb80_0 .net "COUT_N", 0 0, L_0000000003957c20; alias, 1 drivers
+v00000000036301c0_0 .net "SUM", 0 0, L_0000000003958400; alias, 1 drivers
+L_00000000038c97b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362e3c0_0 .net8 "VGND", 0 0, L_00000000038c97b0; 1 drivers, strength-aware
+L_00000000038c9f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f220_0 .net8 "VNB", 0 0, L_00000000038c9f20; 1 drivers, strength-aware
+L_00000000038c9890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362e460_0 .net8 "VPB", 0 0, L_00000000038c9890; 1 drivers, strength-aware
+L_00000000038c9a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036304e0_0 .net8 "VPWR", 0 0, L_00000000038c9a50; 1 drivers, strength-aware
+v0000000003630580_0 .net "a_b", 0 0, L_0000000003957e50; 1 drivers
+v0000000003630620_0 .net "a_ci", 0 0, L_0000000003957d00; 1 drivers
+v000000000362e820_0 .net "b_ci", 0 0, L_0000000003958710; 1 drivers
+v000000000362f2c0_0 .net "or0_out_coutn", 0 0, L_0000000003958780; 1 drivers
+v000000000362ebe0_0 .net "xor0_out_SUM", 0 0, L_00000000039586a0; 1 drivers
+S_0000000002769380 .scope module, "sky130_fd_sc_hd__fill_1" "sky130_fd_sc_hd__fill_1" 4 3690;
+ .timescale -9 -12;
+L_00000000038ca0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362ec80_0 .net8 "VGND", 0 0, L_00000000038ca0e0; 1 drivers, strength-aware
+L_00000000038ca380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630760_0 .net8 "VNB", 0 0, L_00000000038ca380; 1 drivers, strength-aware
+L_00000000038c9740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362fd60_0 .net8 "VPB", 0 0, L_00000000038c9740; 1 drivers, strength-aware
+L_00000000038ca460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362f040_0 .net8 "VPWR", 0 0, L_00000000038ca460; 1 drivers, strength-aware
+S_00000000034e7230 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3697, 4 3352 1, S_0000000002769380;
+ .timescale -9 -12;
+L_00000000038ca3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362ffe0_0 .net8 "VGND", 0 0, L_00000000038ca3f0; 1 drivers, strength-aware
+L_00000000038c9900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362eaa0_0 .net8 "VNB", 0 0, L_00000000038c9900; 1 drivers, strength-aware
+L_00000000038cb030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362e320_0 .net8 "VPB", 0 0, L_00000000038cb030; 1 drivers, strength-aware
+L_00000000038c9970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036303a0_0 .net8 "VPWR", 0 0, L_00000000038c9970; 1 drivers, strength-aware
+S_0000000002769d10 .scope module, "sky130_fd_sc_hd__fill_2" "sky130_fd_sc_hd__fill_2" 4 3606;
+ .timescale -9 -12;
+L_00000000038c9c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362fe00_0 .net8 "VGND", 0 0, L_00000000038c9c10; 1 drivers, strength-aware
+L_00000000038c99e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630260_0 .net8 "VNB", 0 0, L_00000000038c99e0; 1 drivers, strength-aware
+L_00000000038ca150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630300_0 .net8 "VPB", 0 0, L_00000000038ca150; 1 drivers, strength-aware
+L_00000000038cabd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362e6e0_0 .net8 "VPWR", 0 0, L_00000000038cabd0; 1 drivers, strength-aware
+S_00000000034ea830 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3613, 4 3352 1, S_0000000002769d10;
+ .timescale -9 -12;
+L_00000000038c9eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f0e0_0 .net8 "VGND", 0 0, L_00000000038c9eb0; 1 drivers, strength-aware
+L_00000000038cac40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630080_0 .net8 "VNB", 0 0, L_00000000038cac40; 1 drivers, strength-aware
+L_00000000038c94a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362f400_0 .net8 "VPB", 0 0, L_00000000038c94a0; 1 drivers, strength-aware
+L_00000000038c9510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362f720_0 .net8 "VPWR", 0 0, L_00000000038c9510; 1 drivers, strength-aware
+S_000000000276a790 .scope module, "sky130_fd_sc_hd__fill_4" "sky130_fd_sc_hd__fill_4" 4 3438;
+ .timescale -9 -12;
+L_00000000038c9580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036308a0_0 .net8 "VGND", 0 0, L_00000000038c9580; 1 drivers, strength-aware
+L_00000000038c9ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f5e0_0 .net8 "VNB", 0 0, L_00000000038c9ac0; 1 drivers, strength-aware
+L_00000000038cacb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362e140_0 .net8 "VPB", 0 0, L_00000000038cacb0; 1 drivers, strength-aware
+L_00000000038c9c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362f680_0 .net8 "VPWR", 0 0, L_00000000038c9c80; 1 drivers, strength-aware
+S_00000000034e8eb0 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3445, 4 3352 1, S_000000000276a790;
+ .timescale -9 -12;
+L_00000000038c95f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630800_0 .net8 "VGND", 0 0, L_00000000038c95f0; 1 drivers, strength-aware
+L_00000000038c9cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f4a0_0 .net8 "VNB", 0 0, L_00000000038c9cf0; 1 drivers, strength-aware
+L_00000000038c9dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362f540_0 .net8 "VPB", 0 0, L_00000000038c9dd0; 1 drivers, strength-aware
+L_00000000038c9e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000362e640_0 .net8 "VPWR", 0 0, L_00000000038c9e40; 1 drivers, strength-aware
+S_000000000276a310 .scope module, "sky130_fd_sc_hd__fill_8" "sky130_fd_sc_hd__fill_8" 4 3522;
+ .timescale -9 -12;
+L_00000000038ca230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036309e0_0 .net8 "VGND", 0 0, L_00000000038ca230; 1 drivers, strength-aware
+L_00000000038ca4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003632880_0 .net8 "VNB", 0 0, L_00000000038ca4d0; 1 drivers, strength-aware
+L_00000000038ca540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630c60_0 .net8 "VPB", 0 0, L_00000000038ca540; 1 drivers, strength-aware
+L_00000000038cc220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631b60_0 .net8 "VPWR", 0 0, L_00000000038cc220; 1 drivers, strength-aware
+S_00000000034ea0b0 .scope module, "base" "sky130_fd_sc_hd__fill" 4 3529, 4 3352 1, S_000000000276a310;
+ .timescale -9 -12;
+L_00000000038cb6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f9a0_0 .net8 "VGND", 0 0, L_00000000038cb6c0; 1 drivers, strength-aware
+L_00000000038cb8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000362f860_0 .net8 "VNB", 0 0, L_00000000038cb8f0; 1 drivers, strength-aware
+L_00000000038cbb20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630e40_0 .net8 "VPB", 0 0, L_00000000038cbb20; 1 drivers, strength-aware
+L_00000000038cc3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631480_0 .net8 "VPWR", 0 0, L_00000000038cc3e0; 1 drivers, strength-aware
+S_000000000276a190 .scope module, "sky130_fd_sc_hd__ha_1" "sky130_fd_sc_hd__ha_1" 4 10435;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+o000000000364e0c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036318e0_0 .net "A", 0 0, o000000000364e0c8; 0 drivers
+o000000000364e0f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003631520_0 .net "B", 0 0, o000000000364e0f8; 0 drivers
+v0000000003631980_0 .net "COUT", 0 0, L_0000000003957130; 1 drivers
+v0000000003630f80_0 .net "SUM", 0 0, L_0000000003958b00; 1 drivers
+L_00000000038cc290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003631c00_0 .net8 "VGND", 0 0, L_00000000038cc290; 1 drivers, strength-aware
+L_00000000038cb420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003631660_0 .net8 "VNB", 0 0, L_00000000038cb420; 1 drivers, strength-aware
+L_00000000038cc610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631020_0 .net8 "VPB", 0 0, L_00000000038cc610; 1 drivers, strength-aware
+L_00000000038cb490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630da0_0 .net8 "VPWR", 0 0, L_00000000038cb490; 1 drivers, strength-aware
+S_00000000034ea6b0 .scope module, "base" "sky130_fd_sc_hd__ha" 4 10453, 4 10866 1, S_000000000276a190;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+L_0000000003957ec0 .functor AND 1, o000000000364e0c8, o000000000364e0f8, C4<1>, C4<1>;
+L_0000000003957130 .functor BUF 1, L_0000000003957ec0, C4<0>, C4<0>, C4<0>;
+L_0000000003958320 .functor XOR 1, o000000000364e0f8, o000000000364e0c8, C4<0>, C4<0>;
+L_0000000003958b00 .functor BUF 1, L_0000000003958320, C4<0>, C4<0>, C4<0>;
+v00000000036324c0_0 .net "A", 0 0, o000000000364e0c8; alias, 0 drivers
+v0000000003632920_0 .net "B", 0 0, o000000000364e0f8; alias, 0 drivers
+v0000000003631ca0_0 .net "COUT", 0 0, L_0000000003957130; alias, 1 drivers
+v00000000036315c0_0 .net "SUM", 0 0, L_0000000003958b00; alias, 1 drivers
+L_00000000038cc370 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630d00_0 .net8 "VGND", 0 0, L_00000000038cc370; 1 drivers, strength-aware
+L_00000000038cca00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036322e0_0 .net8 "VNB", 0 0, L_00000000038cca00; 1 drivers, strength-aware
+L_00000000038cc990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036310c0_0 .net8 "VPB", 0 0, L_00000000038cc990; 1 drivers, strength-aware
+L_00000000038ccbc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003630940_0 .net8 "VPWR", 0 0, L_00000000038ccbc0; 1 drivers, strength-aware
+v0000000003630bc0_0 .net "and0_out_COUT", 0 0, L_0000000003957ec0; 1 drivers
+v0000000003631840_0 .net "xor0_out_SUM", 0 0, L_0000000003958320; 1 drivers
+S_0000000002769b90 .scope module, "sky130_fd_sc_hd__ha_2" "sky130_fd_sc_hd__ha_2" 4 10985;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+o000000000364e4e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003632380_0 .net "A", 0 0, o000000000364e4e8; 0 drivers
+o000000000364e518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036312a0_0 .net "B", 0 0, o000000000364e518; 0 drivers
+v0000000003632ce0_0 .net "COUT", 0 0, L_00000000039577c0; 1 drivers
+v00000000036317a0_0 .net "SUM", 0 0, L_0000000003957830; 1 drivers
+L_00000000038cbff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036313e0_0 .net8 "VGND", 0 0, L_00000000038cbff0; 1 drivers, strength-aware
+L_00000000038cb880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003632ec0_0 .net8 "VNB", 0 0, L_00000000038cb880; 1 drivers, strength-aware
+L_00000000038cc680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631700_0 .net8 "VPB", 0 0, L_00000000038cc680; 1 drivers, strength-aware
+L_00000000038cb570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631d40_0 .net8 "VPWR", 0 0, L_00000000038cb570; 1 drivers, strength-aware
+S_00000000034e7e30 .scope module, "base" "sky130_fd_sc_hd__ha" 4 11003, 4 10866 1, S_0000000002769b90;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+L_0000000003958cc0 .functor AND 1, o000000000364e4e8, o000000000364e518, C4<1>, C4<1>;
+L_00000000039577c0 .functor BUF 1, L_0000000003958cc0, C4<0>, C4<0>, C4<0>;
+L_0000000003957c90 .functor XOR 1, o000000000364e518, o000000000364e4e8, C4<0>, C4<0>;
+L_0000000003957830 .functor BUF 1, L_0000000003957c90, C4<0>, C4<0>, C4<0>;
+v0000000003630a80_0 .net "A", 0 0, o000000000364e4e8; alias, 0 drivers
+v0000000003631e80_0 .net "B", 0 0, o000000000364e518; alias, 0 drivers
+v0000000003630ee0_0 .net "COUT", 0 0, L_00000000039577c0; alias, 1 drivers
+v0000000003631fc0_0 .net "SUM", 0 0, L_0000000003957830; alias, 1 drivers
+L_00000000038cbce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003631160_0 .net8 "VGND", 0 0, L_00000000038cbce0; 1 drivers, strength-aware
+L_00000000038ccc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003631f20_0 .net8 "VNB", 0 0, L_00000000038ccc30; 1 drivers, strength-aware
+L_00000000038cbc70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003631340_0 .net8 "VPB", 0 0, L_00000000038cbc70; 1 drivers, strength-aware
+L_00000000038cb650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003632060_0 .net8 "VPWR", 0 0, L_00000000038cb650; 1 drivers, strength-aware
+v00000000036329c0_0 .net "and0_out_COUT", 0 0, L_0000000003958cc0; 1 drivers
+v0000000003631200_0 .net "xor0_out_SUM", 0 0, L_0000000003957c90; 1 drivers
+S_0000000002769e90 .scope module, "sky130_fd_sc_hd__ha_4" "sky130_fd_sc_hd__ha_4" 4 10547;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+o000000000364e908 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003632f60_0 .net "A", 0 0, o000000000364e908; 0 drivers
+o000000000364e938 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003632240_0 .net "B", 0 0, o000000000364e938; 0 drivers
+v0000000003632420_0 .net "COUT", 0 0, L_0000000003957210; 1 drivers
+v0000000003632560_0 .net "SUM", 0 0, L_00000000039584e0; 1 drivers
+L_00000000038cb110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003632d80_0 .net8 "VGND", 0 0, L_00000000038cb110; 1 drivers, strength-aware
+L_00000000038cb9d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003632600_0 .net8 "VNB", 0 0, L_00000000038cb9d0; 1 drivers, strength-aware
+L_00000000038cb730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003632740_0 .net8 "VPB", 0 0, L_00000000038cb730; 1 drivers, strength-aware
+L_00000000038ccb50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036327e0_0 .net8 "VPWR", 0 0, L_00000000038ccb50; 1 drivers, strength-aware
+S_00000000034ea230 .scope module, "base" "sky130_fd_sc_hd__ha" 4 10565, 4 10866 1, S_0000000002769e90;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "COUT"
+ .port_info 1 /OUTPUT 1 "SUM"
+ .port_info 2 /INPUT 1 "A"
+ .port_info 3 /INPUT 1 "B"
+L_0000000003957670 .functor AND 1, o000000000364e908, o000000000364e938, C4<1>, C4<1>;
+L_0000000003957210 .functor BUF 1, L_0000000003957670, C4<0>, C4<0>, C4<0>;
+L_0000000003958080 .functor XOR 1, o000000000364e938, o000000000364e908, C4<0>, C4<0>;
+L_00000000039584e0 .functor BUF 1, L_0000000003958080, C4<0>, C4<0>, C4<0>;
+v0000000003631a20_0 .net "A", 0 0, o000000000364e908; alias, 0 drivers
+v0000000003631ac0_0 .net "B", 0 0, o000000000364e938; alias, 0 drivers
+v0000000003632100_0 .net "COUT", 0 0, L_0000000003957210; alias, 1 drivers
+v0000000003631de0_0 .net "SUM", 0 0, L_00000000039584e0; alias, 1 drivers
+L_00000000038cbab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036321a0_0 .net8 "VGND", 0 0, L_00000000038cbab0; 1 drivers, strength-aware
+L_00000000038cb960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003632ba0_0 .net8 "VNB", 0 0, L_00000000038cb960; 1 drivers, strength-aware
+L_00000000038cb7a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003632e20_0 .net8 "VPB", 0 0, L_00000000038cb7a0; 1 drivers, strength-aware
+L_00000000038cb810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003632a60_0 .net8 "VPWR", 0 0, L_00000000038cb810; 1 drivers, strength-aware
+v00000000036326a0_0 .net "and0_out_COUT", 0 0, L_0000000003957670; 1 drivers
+v0000000003632b00_0 .net "xor0_out_SUM", 0 0, L_0000000003958080; 1 drivers
+S_000000000276a010 .scope module, "sky130_fd_sc_hd__inv_1" "sky130_fd_sc_hd__inv_1" 4 53953;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364ed28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f2960_0 .net "A", 0 0, o000000000364ed28; 0 drivers
+L_00000000038cba40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f37c0_0 .net8 "VGND", 0 0, L_00000000038cba40; 1 drivers, strength-aware
+L_00000000038cbb90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f2500_0 .net8 "VNB", 0 0, L_00000000038cbb90; 1 drivers, strength-aware
+L_00000000038cbd50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2280_0 .net8 "VPB", 0 0, L_00000000038cbd50; 1 drivers, strength-aware
+L_00000000038cbdc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2fa0_0 .net8 "VPWR", 0 0, L_00000000038cbdc0; 1 drivers, strength-aware
+v00000000035f21e0_0 .net "Y", 0 0, L_00000000039578a0; 1 drivers
+S_00000000034eae30 .scope module, "base" "sky130_fd_sc_hd__inv" 4 53967, 4 54841 1, S_000000000276a010;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957280 .functor NOT 1, o000000000364ed28, C4<0>, C4<0>, C4<0>;
+L_00000000039578a0 .functor BUF 1, L_0000000003957280, C4<0>, C4<0>, C4<0>;
+v0000000003632c40_0 .net "A", 0 0, o000000000364ed28; alias, 0 drivers
+L_00000000038cbe30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003630b20_0 .net8 "VGND", 0 0, L_00000000038cbe30; 1 drivers, strength-aware
+L_00000000038cbea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f26e0_0 .net8 "VNB", 0 0, L_00000000038cbea0; 1 drivers, strength-aware
+L_00000000038cb3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2140_0 .net8 "VPB", 0 0, L_00000000038cb3b0; 1 drivers, strength-aware
+L_00000000038cb0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f4800_0 .net8 "VPWR", 0 0, L_00000000038cb0a0; 1 drivers, strength-aware
+v00000000035f3f40_0 .net "Y", 0 0, L_00000000039578a0; alias, 1 drivers
+v00000000035f48a0_0 .net "not0_out_Y", 0 0, L_0000000003957280; 1 drivers
+S_000000000276b390 .scope module, "sky130_fd_sc_hd__inv_12" "sky130_fd_sc_hd__inv_12" 4 54553;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364eff8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f2c80_0 .net "A", 0 0, o000000000364eff8; 0 drivers
+L_00000000038cbc00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f3a40_0 .net8 "VGND", 0 0, L_00000000038cbc00; 1 drivers, strength-aware
+L_00000000038cc530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f4120_0 .net8 "VNB", 0 0, L_00000000038cc530; 1 drivers, strength-aware
+L_00000000038cb2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f3e00_0 .net8 "VPB", 0 0, L_00000000038cb2d0; 1 drivers, strength-aware
+L_00000000038cb5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f3720_0 .net8 "VPWR", 0 0, L_00000000038cb5e0; 1 drivers, strength-aware
+v00000000035f2f00_0 .net "Y", 0 0, L_0000000003957d70; 1 drivers
+S_00000000034e70b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54567, 4 54841 1, S_000000000276b390;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003958550 .functor NOT 1, o000000000364eff8, C4<0>, C4<0>, C4<0>;
+L_0000000003957d70 .functor BUF 1, L_0000000003958550, C4<0>, C4<0>, C4<0>;
+v00000000035f2320_0 .net "A", 0 0, o000000000364eff8; alias, 0 drivers
+L_00000000038cbf10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f23c0_0 .net8 "VGND", 0 0, L_00000000038cbf10; 1 drivers, strength-aware
+L_00000000038cc920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f3c20_0 .net8 "VNB", 0 0, L_00000000038cc920; 1 drivers, strength-aware
+L_00000000038cb340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2a00_0 .net8 "VPB", 0 0, L_00000000038cb340; 1 drivers, strength-aware
+L_00000000038cbf80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f3900_0 .net8 "VPWR", 0 0, L_00000000038cbf80; 1 drivers, strength-aware
+v00000000035f3d60_0 .net "Y", 0 0, L_0000000003957d70; alias, 1 drivers
+v00000000035f3fe0_0 .net "not0_out_Y", 0 0, L_0000000003958550; 1 drivers
+S_000000000276b210 .scope module, "sky130_fd_sc_hd__inv_16" "sky130_fd_sc_hd__inv_16" 4 54253;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364f2c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f2780_0 .net "A", 0 0, o000000000364f2c8; 0 drivers
+L_00000000038cb180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f2820_0 .net8 "VGND", 0 0, L_00000000038cb180; 1 drivers, strength-aware
+L_00000000038cc060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f2dc0_0 .net8 "VNB", 0 0, L_00000000038cc060; 1 drivers, strength-aware
+L_00000000038cc6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f4760_0 .net8 "VPB", 0 0, L_00000000038cc6f0; 1 drivers, strength-aware
+L_00000000038cc0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f25a0_0 .net8 "VPWR", 0 0, L_00000000038cc0d0; 1 drivers, strength-aware
+v00000000035f2b40_0 .net "Y", 0 0, L_0000000003958390; 1 drivers
+S_00000000034e73b0 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54267, 4 54841 1, S_000000000276b210;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957600 .functor NOT 1, o000000000364f2c8, C4<0>, C4<0>, C4<0>;
+L_0000000003958390 .functor BUF 1, L_0000000003957600, C4<0>, C4<0>, C4<0>;
+v00000000035f3860_0 .net "A", 0 0, o000000000364f2c8; alias, 0 drivers
+L_00000000038cc450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f28c0_0 .net8 "VGND", 0 0, L_00000000038cc450; 1 drivers, strength-aware
+L_00000000038cc140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f2aa0_0 .net8 "VNB", 0 0, L_00000000038cc140; 1 drivers, strength-aware
+L_00000000038cc1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f39a0_0 .net8 "VPB", 0 0, L_00000000038cc1b0; 1 drivers, strength-aware
+L_00000000038cc300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2d20_0 .net8 "VPWR", 0 0, L_00000000038cc300; 1 drivers, strength-aware
+v00000000035f2640_0 .net "Y", 0 0, L_0000000003958390; alias, 1 drivers
+v00000000035f3ae0_0 .net "not0_out_Y", 0 0, L_0000000003957600; 1 drivers
+S_000000000276a490 .scope module, "sky130_fd_sc_hd__inv_4" "sky130_fd_sc_hd__inv_4" 4 54353;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364f598 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f3040_0 .net "A", 0 0, o000000000364f598; 0 drivers
+L_00000000038cb500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f44e0_0 .net8 "VGND", 0 0, L_00000000038cb500; 1 drivers, strength-aware
+L_00000000038cc4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f41c0_0 .net8 "VNB", 0 0, L_00000000038cc4c0; 1 drivers, strength-aware
+L_00000000038cc5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f3cc0_0 .net8 "VPB", 0 0, L_00000000038cc5a0; 1 drivers, strength-aware
+L_00000000038cc7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f3ea0_0 .net8 "VPWR", 0 0, L_00000000038cc7d0; 1 drivers, strength-aware
+v00000000035f46c0_0 .net "Y", 0 0, L_0000000003957520; 1 drivers
+S_00000000036aa480 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54367, 4 54841 1, S_000000000276a490;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957b40 .functor NOT 1, o000000000364f598, C4<0>, C4<0>, C4<0>;
+L_0000000003957520 .functor BUF 1, L_0000000003957b40, C4<0>, C4<0>, C4<0>;
+v00000000035f4620_0 .net "A", 0 0, o000000000364f598; alias, 0 drivers
+L_00000000038cb1f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f34a0_0 .net8 "VGND", 0 0, L_00000000038cb1f0; 1 drivers, strength-aware
+L_00000000038cc760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f4080_0 .net8 "VNB", 0 0, L_00000000038cc760; 1 drivers, strength-aware
+L_00000000038cc840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2e60_0 .net8 "VPB", 0 0, L_00000000038cc840; 1 drivers, strength-aware
+L_00000000038cc8b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f2be0_0 .net8 "VPWR", 0 0, L_00000000038cc8b0; 1 drivers, strength-aware
+v00000000035f3b80_0 .net "Y", 0 0, L_0000000003957520; alias, 1 drivers
+v00000000035f3180_0 .net "not0_out_Y", 0 0, L_0000000003957b40; 1 drivers
+S_000000000276a610 .scope module, "sky130_fd_sc_hd__inv_6" "sky130_fd_sc_hd__inv_6" 4 54153;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364f868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000035f3400_0 .net "A", 0 0, o000000000364f868; 0 drivers
+L_00000000038cca70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f4300_0 .net8 "VGND", 0 0, L_00000000038cca70; 1 drivers, strength-aware
+L_00000000038ccae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f3540_0 .net8 "VNB", 0 0, L_00000000038ccae0; 1 drivers, strength-aware
+L_00000000038cb260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f35e0_0 .net8 "VPB", 0 0, L_00000000038cb260; 1 drivers, strength-aware
+L_00000000038cd870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f43a0_0 .net8 "VPWR", 0 0, L_00000000038cd870; 1 drivers, strength-aware
+v00000000035f3680_0 .net "Y", 0 0, L_0000000003958470; 1 drivers
+S_00000000036a8b00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54167, 4 54841 1, S_000000000276a610;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957910 .functor NOT 1, o000000000364f868, C4<0>, C4<0>, C4<0>;
+L_0000000003958470 .functor BUF 1, L_0000000003957910, C4<0>, C4<0>, C4<0>;
+v00000000035f2460_0 .net "A", 0 0, o000000000364f868; alias, 0 drivers
+L_00000000038cdd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f4580_0 .net8 "VGND", 0 0, L_00000000038cdd40; 1 drivers, strength-aware
+L_00000000038ce130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000035f3220_0 .net8 "VNB", 0 0, L_00000000038ce130; 1 drivers, strength-aware
+L_00000000038cd480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f30e0_0 .net8 "VPB", 0 0, L_00000000038cd480; 1 drivers, strength-aware
+L_00000000038cda30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000035f32c0_0 .net8 "VPWR", 0 0, L_00000000038cda30; 1 drivers, strength-aware
+v00000000035f3360_0 .net "Y", 0 0, L_0000000003958470; alias, 1 drivers
+v00000000035f4260_0 .net "not0_out_Y", 0 0, L_0000000003957910; 1 drivers
+S_000000000276b510 .scope module, "sky130_fd_sc_hd__inv_8" "sky130_fd_sc_hd__inv_8" 4 54453;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o000000000364fb38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b48b0_0 .net "A", 0 0, o000000000364fb38; 0 drivers
+L_00000000038cdc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2290_0 .net8 "VGND", 0 0, L_00000000038cdc60; 1 drivers, strength-aware
+L_00000000038cdaa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b3c30_0 .net8 "VNB", 0 0, L_00000000038cdaa0; 1 drivers, strength-aware
+L_00000000038cd4f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2a10_0 .net8 "VPB", 0 0, L_00000000038cd4f0; 1 drivers, strength-aware
+L_00000000038cd560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3910_0 .net8 "VPWR", 0 0, L_00000000038cd560; 1 drivers, strength-aware
+v00000000036b3d70_0 .net "Y", 0 0, L_0000000003957980; 1 drivers
+S_00000000036a9d00 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54467, 4 54841 1, S_000000000276b510;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039585c0 .functor NOT 1, o000000000364fb38, C4<0>, C4<0>, C4<0>;
+L_0000000003957980 .functor BUF 1, L_00000000039585c0, C4<0>, C4<0>, C4<0>;
+v00000000035f4440_0 .net "A", 0 0, o000000000364fb38; alias, 0 drivers
+L_00000000038ccca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b4590_0 .net8 "VGND", 0 0, L_00000000038ccca0; 1 drivers, strength-aware
+L_00000000038cd5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2f10_0 .net8 "VNB", 0 0, L_00000000038cd5d0; 1 drivers, strength-aware
+L_00000000038cddb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3f50_0 .net8 "VPB", 0 0, L_00000000038cddb0; 1 drivers, strength-aware
+L_00000000038ce830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4810_0 .net8 "VPWR", 0 0, L_00000000038ce830; 1 drivers, strength-aware
+v00000000036b3730_0 .net "Y", 0 0, L_0000000003957980; alias, 1 drivers
+v00000000036b4090_0 .net "not0_out_Y", 0 0, L_00000000039585c0; 1 drivers
+S_000000000276af10 .scope module, "sky130_fd_sc_hd__lpflow_bleeder_1" "sky130_fd_sc_hd__lpflow_bleeder_1" 4 74255;
+ .timescale -9 -12;
+ .port_info 0 /INPUT 1 "SHORT"
+o000000000364fe08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b2330_0 .net "SHORT", 0 0, o000000000364fe08; 0 drivers
+L_00000000038cde20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b37d0_0 .net8 "VGND", 0 0, L_00000000038cde20; 1 drivers, strength-aware
+L_00000000038cd330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2fb0_0 .net8 "VNB", 0 0, L_00000000038cd330; 1 drivers, strength-aware
+L_00000000038ce360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4130_0 .net8 "VPB", 0 0, L_00000000038ce360; 1 drivers, strength-aware
+S_00000000036a9e80 .scope module, "base" "sky130_fd_sc_hd__lpflow_bleeder" 4 74267, 4 74479 1, S_000000000276af10;
+ .timescale -9 -12;
+ .port_info 0 /INPUT 1 "SHORT"
+v00000000036b3a50_0 .net "SHORT", 0 0, o000000000364fe08; alias, 0 drivers
+S_000000000276aa90 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_1" "sky130_fd_sc_hd__lpflow_clkbufkapwr_1" 4 7217;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000364ff28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b4630_0 .net "A", 0 0, o000000000364ff28; 0 drivers
+L_00000000038cd250 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4310_0 .net8 "KAPWR", 0 0, L_00000000038cd250; 1 drivers, strength-aware
+L_00000000038cdb10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b41d0_0 .net8 "VGND", 0 0, L_00000000038cdb10; 1 drivers, strength-aware
+L_00000000038cd640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b3190_0 .net8 "VNB", 0 0, L_00000000038cd640; 1 drivers, strength-aware
+L_00000000038ccd10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3cd0_0 .net8 "VPB", 0 0, L_00000000038ccd10; 1 drivers, strength-aware
+L_00000000038cd2c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3e10_0 .net8 "VPWR", 0 0, L_00000000038cd2c0; 1 drivers, strength-aware
+v00000000036b30f0_0 .net "X", 0 0, L_0000000003957360; 1 drivers
+S_00000000036ac400 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7232, 4 7510 1, S_000000000276aa90;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039579f0 .functor BUF 1, o000000000364ff28, C4<0>, C4<0>, C4<0>;
+L_0000000003957360 .functor BUF 1, L_00000000039579f0, C4<0>, C4<0>, C4<0>;
+v00000000036b2510_0 .net "A", 0 0, o000000000364ff28; alias, 0 drivers
+L_00000000038cd6b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3050_0 .net8 "KAPWR", 0 0, L_00000000038cd6b0; 1 drivers, strength-aware
+L_00000000038cd720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b3af0_0 .net8 "VGND", 0 0, L_00000000038cd720; 1 drivers, strength-aware
+L_00000000038ce280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2c90_0 .net8 "VNB", 0 0, L_00000000038ce280; 1 drivers, strength-aware
+L_00000000038ce440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b25b0_0 .net8 "VPB", 0 0, L_00000000038ce440; 1 drivers, strength-aware
+L_00000000038ce050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3b90_0 .net8 "VPWR", 0 0, L_00000000038ce050; 1 drivers, strength-aware
+v00000000036b39b0_0 .net "X", 0 0, L_0000000003957360; alias, 1 drivers
+v00000000036b2d30_0 .net "buf0_out_X", 0 0, L_00000000039579f0; 1 drivers
+S_0000000002769890 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_16" "sky130_fd_sc_hd__lpflow_clkbufkapwr_16" 4 7113;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003650258 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b3410_0 .net "A", 0 0, o0000000003650258; 0 drivers
+L_00000000038cd790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4270_0 .net8 "KAPWR", 0 0, L_00000000038cd790; 1 drivers, strength-aware
+L_00000000038ce670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b43b0_0 .net8 "VGND", 0 0, L_00000000038ce670; 1 drivers, strength-aware
+L_00000000038ce3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b32d0_0 .net8 "VNB", 0 0, L_00000000038ce3d0; 1 drivers, strength-aware
+L_00000000038cd8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3370_0 .net8 "VPB", 0 0, L_00000000038cd8e0; 1 drivers, strength-aware
+L_00000000038cd800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2470_0 .net8 "VPWR", 0 0, L_00000000038cd800; 1 drivers, strength-aware
+v00000000036b46d0_0 .net "X", 0 0, L_0000000003957750; 1 drivers
+S_00000000036ad900 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7128, 4 7510 1, S_0000000002769890;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039573d0 .functor BUF 1, o0000000003650258, C4<0>, C4<0>, C4<0>;
+L_0000000003957750 .functor BUF 1, L_00000000039573d0, C4<0>, C4<0>, C4<0>;
+v00000000036b2dd0_0 .net "A", 0 0, o0000000003650258; alias, 0 drivers
+L_00000000038cd3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3eb0_0 .net8 "KAPWR", 0 0, L_00000000038cd3a0; 1 drivers, strength-aware
+L_00000000038cd950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2790_0 .net8 "VGND", 0 0, L_00000000038cd950; 1 drivers, strength-aware
+L_00000000038ce4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b3ff0_0 .net8 "VNB", 0 0, L_00000000038ce4b0; 1 drivers, strength-aware
+L_00000000038cdb80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3230_0 .net8 "VPB", 0 0, L_00000000038cdb80; 1 drivers, strength-aware
+L_00000000038cdf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2650_0 .net8 "VPWR", 0 0, L_00000000038cdf00; 1 drivers, strength-aware
+v00000000036b26f0_0 .net "X", 0 0, L_0000000003957750; alias, 1 drivers
+v00000000036b2e70_0 .net "buf0_out_X", 0 0, L_00000000039573d0; 1 drivers
+S_0000000002769710 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_2" "sky130_fd_sc_hd__lpflow_clkbufkapwr_2" 4 7724;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003650588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b4770_0 .net "A", 0 0, o0000000003650588; 0 drivers
+L_00000000038cdbf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2150_0 .net8 "KAPWR", 0 0, L_00000000038cdbf0; 1 drivers, strength-aware
+L_00000000038cd410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b21f0_0 .net8 "VGND", 0 0, L_00000000038cd410; 1 drivers, strength-aware
+L_00000000038cde90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b23d0_0 .net8 "VNB", 0 0, L_00000000038cde90; 1 drivers, strength-aware
+L_00000000038ce1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2b50_0 .net8 "VPB", 0 0, L_00000000038ce1a0; 1 drivers, strength-aware
+L_00000000038ccd80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b35f0_0 .net8 "VPWR", 0 0, L_00000000038ccd80; 1 drivers, strength-aware
+v00000000036b3690_0 .net "X", 0 0, L_00000000039574b0; 1 drivers
+S_00000000036a8200 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7739, 4 7510 1, S_0000000002769710;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957440 .functor BUF 1, o0000000003650588, C4<0>, C4<0>, C4<0>;
+L_00000000039574b0 .functor BUF 1, L_0000000003957440, C4<0>, C4<0>, C4<0>;
+v00000000036b4450_0 .net "A", 0 0, o0000000003650588; alias, 0 drivers
+L_00000000038cce60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b44f0_0 .net8 "KAPWR", 0 0, L_00000000038cce60; 1 drivers, strength-aware
+L_00000000038ce750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2830_0 .net8 "VGND", 0 0, L_00000000038ce750; 1 drivers, strength-aware
+L_00000000038cdf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b2970_0 .net8 "VNB", 0 0, L_00000000038cdf70; 1 drivers, strength-aware
+L_00000000038ce210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b34b0_0 .net8 "VPB", 0 0, L_00000000038ce210; 1 drivers, strength-aware
+L_00000000038cd020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b2ab0_0 .net8 "VPWR", 0 0, L_00000000038cd020; 1 drivers, strength-aware
+v00000000036b28d0_0 .net "X", 0 0, L_00000000039574b0; alias, 1 drivers
+v00000000036b3550_0 .net "buf0_out_X", 0 0, L_0000000003957440; 1 drivers
+S_000000000276a910 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_4" "sky130_fd_sc_hd__lpflow_clkbufkapwr_4" 4 7828;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000036508b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b57b0_0 .net "A", 0 0, o00000000036508b8; 0 drivers
+L_00000000038cdcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b67f0_0 .net8 "KAPWR", 0 0, L_00000000038cdcd0; 1 drivers, strength-aware
+L_00000000038cd9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b4db0_0 .net8 "VGND", 0 0, L_00000000038cd9c0; 1 drivers, strength-aware
+L_00000000038cdfe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b6250_0 .net8 "VNB", 0 0, L_00000000038cdfe0; 1 drivers, strength-aware
+L_00000000038cced0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6110_0 .net8 "VPB", 0 0, L_00000000038cced0; 1 drivers, strength-aware
+L_00000000038ce0c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4f90_0 .net8 "VPWR", 0 0, L_00000000038ce0c0; 1 drivers, strength-aware
+v00000000036b61b0_0 .net "X", 0 0, L_0000000003958630; 1 drivers
+S_00000000036abc80 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7843, 4 7510 1, S_000000000276a910;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039576e0 .functor BUF 1, o00000000036508b8, C4<0>, C4<0>, C4<0>;
+L_0000000003958630 .functor BUF 1, L_00000000039576e0, C4<0>, C4<0>, C4<0>;
+v00000000036b2bf0_0 .net "A", 0 0, o00000000036508b8; alias, 0 drivers
+L_00000000038ce2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b3870_0 .net8 "KAPWR", 0 0, L_00000000038ce2f0; 1 drivers, strength-aware
+L_00000000038ce7c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5710_0 .net8 "VGND", 0 0, L_00000000038ce7c0; 1 drivers, strength-aware
+L_00000000038ce520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b6930_0 .net8 "VNB", 0 0, L_00000000038ce520; 1 drivers, strength-aware
+L_00000000038ce590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5df0_0 .net8 "VPB", 0 0, L_00000000038ce590; 1 drivers, strength-aware
+L_00000000038ce600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4ef0_0 .net8 "VPWR", 0 0, L_00000000038ce600; 1 drivers, strength-aware
+v00000000036b5f30_0 .net "X", 0 0, L_0000000003958630; alias, 1 drivers
+v00000000036b4d10_0 .net "buf0_out_X", 0 0, L_00000000039576e0; 1 drivers
+S_000000000276ac10 .scope module, "sky130_fd_sc_hd__lpflow_clkbufkapwr_8" "sky130_fd_sc_hd__lpflow_clkbufkapwr_8" 4 7620;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003650be8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b6430_0 .net "A", 0 0, o0000000003650be8; 0 drivers
+L_00000000038ce6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6750_0 .net8 "KAPWR", 0 0, L_00000000038ce6e0; 1 drivers, strength-aware
+L_00000000038ccdf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5990_0 .net8 "VGND", 0 0, L_00000000038ccdf0; 1 drivers, strength-aware
+L_00000000038ccf40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b4e50_0 .net8 "VNB", 0 0, L_00000000038ccf40; 1 drivers, strength-aware
+L_00000000038cd170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5030_0 .net8 "VPB", 0 0, L_00000000038cd170; 1 drivers, strength-aware
+L_00000000038ccfb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6cf0_0 .net8 "VPWR", 0 0, L_00000000038ccfb0; 1 drivers, strength-aware
+v00000000036b6570_0 .net "X", 0 0, L_0000000003957a60; 1 drivers
+S_00000000036ad180 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkbufkapwr" 4 7635, 4 7510 1, S_000000000276ac10;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957f30 .functor BUF 1, o0000000003650be8, C4<0>, C4<0>, C4<0>;
+L_0000000003957a60 .functor BUF 1, L_0000000003957f30, C4<0>, C4<0>, C4<0>;
+v00000000036b5cb0_0 .net "A", 0 0, o0000000003650be8; alias, 0 drivers
+L_00000000038cd090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b64d0_0 .net8 "KAPWR", 0 0, L_00000000038cd090; 1 drivers, strength-aware
+L_00000000038cd100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b62f0_0 .net8 "VGND", 0 0, L_00000000038cd100; 1 drivers, strength-aware
+L_00000000038cd1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b6390_0 .net8 "VNB", 0 0, L_00000000038cd1e0; 1 drivers, strength-aware
+L_00000000038cf860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b49f0_0 .net8 "VPB", 0 0, L_00000000038cf860; 1 drivers, strength-aware
+L_00000000038cf5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b66b0_0 .net8 "VPWR", 0 0, L_00000000038cf5c0; 1 drivers, strength-aware
+v00000000036b5d50_0 .net "X", 0 0, L_0000000003957a60; alias, 1 drivers
+v00000000036b5490_0 .net "buf0_out_X", 0 0, L_0000000003957f30; 1 drivers
+S_000000000276ad90 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_1" "sky130_fd_sc_hd__lpflow_clkinvkapwr_1" 4 60782;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003650f18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b7010_0 .net "A", 0 0, o0000000003650f18; 0 drivers
+L_00000000038cead0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6f70_0 .net8 "KAPWR", 0 0, L_00000000038cead0; 1 drivers, strength-aware
+L_00000000038ced00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5ad0_0 .net8 "VGND", 0 0, L_00000000038ced00; 1 drivers, strength-aware
+L_00000000038d0430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5350_0 .net8 "VNB", 0 0, L_00000000038d0430; 1 drivers, strength-aware
+L_00000000038ce8a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5170_0 .net8 "VPB", 0 0, L_00000000038ce8a0; 1 drivers, strength-aware
+L_00000000038cf0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5c10_0 .net8 "VPWR", 0 0, L_00000000038cf0f0; 1 drivers, strength-aware
+v00000000036b6a70_0 .net "Y", 0 0, L_0000000003958860; 1 drivers
+S_00000000036ab980 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60797, 4 60360 1, S_000000000276ad90;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039587f0 .functor NOT 1, o0000000003650f18, C4<0>, C4<0>, C4<0>;
+L_0000000003958860 .functor BUF 1, L_00000000039587f0, C4<0>, C4<0>, C4<0>;
+v00000000036b6c50_0 .net "A", 0 0, o0000000003650f18; alias, 0 drivers
+L_00000000038cfef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5670_0 .net8 "KAPWR", 0 0, L_00000000038cfef0; 1 drivers, strength-aware
+L_00000000038cf940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b4c70_0 .net8 "VGND", 0 0, L_00000000038cf940; 1 drivers, strength-aware
+L_00000000038d0200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b52b0_0 .net8 "VNB", 0 0, L_00000000038d0200; 1 drivers, strength-aware
+L_00000000038d0190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5b70_0 .net8 "VPB", 0 0, L_00000000038d0190; 1 drivers, strength-aware
+L_00000000038d03c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b50d0_0 .net8 "VPWR", 0 0, L_00000000038d03c0; 1 drivers, strength-aware
+v00000000036b6610_0 .net "Y", 0 0, L_0000000003958860; alias, 1 drivers
+v00000000036b69d0_0 .net "not0_out_Y", 0 0, L_00000000039587f0; 1 drivers
+S_000000000276b090 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_16" "sky130_fd_sc_hd__lpflow_clkinvkapwr_16" 4 60678;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003651248 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b5a30_0 .net "A", 0 0, o0000000003651248; 0 drivers
+L_00000000038cf7f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5e90_0 .net8 "KAPWR", 0 0, L_00000000038cf7f0; 1 drivers, strength-aware
+L_00000000038cf080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b6b10_0 .net8 "VGND", 0 0, L_00000000038cf080; 1 drivers, strength-aware
+L_00000000038cfe10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b70b0_0 .net8 "VNB", 0 0, L_00000000038cfe10; 1 drivers, strength-aware
+L_00000000038ced70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b55d0_0 .net8 "VPB", 0 0, L_00000000038ced70; 1 drivers, strength-aware
+L_00000000038cf4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6bb0_0 .net8 "VPWR", 0 0, L_00000000038cf4e0; 1 drivers, strength-aware
+v00000000036b58f0_0 .net "Y", 0 0, L_00000000039588d0; 1 drivers
+S_00000000036ac580 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60693, 4 60360 1, S_000000000276b090;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957ad0 .functor NOT 1, o0000000003651248, C4<0>, C4<0>, C4<0>;
+L_00000000039588d0 .functor BUF 1, L_0000000003957ad0, C4<0>, C4<0>, C4<0>;
+v00000000036b53f0_0 .net "A", 0 0, o0000000003651248; alias, 0 drivers
+L_00000000038ce910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6e30_0 .net8 "KAPWR", 0 0, L_00000000038ce910; 1 drivers, strength-aware
+L_00000000038cf470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5210_0 .net8 "VGND", 0 0, L_00000000038cf470; 1 drivers, strength-aware
+L_00000000038cee50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b6890_0 .net8 "VNB", 0 0, L_00000000038cee50; 1 drivers, strength-aware
+L_00000000038ce980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b5530_0 .net8 "VPB", 0 0, L_00000000038ce980; 1 drivers, strength-aware
+L_00000000038cf1d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4bd0_0 .net8 "VPWR", 0 0, L_00000000038cf1d0; 1 drivers, strength-aware
+v00000000036b6d90_0 .net "Y", 0 0, L_00000000039588d0; alias, 1 drivers
+v00000000036b5850_0 .net "not0_out_Y", 0 0, L_0000000003957ad0; 1 drivers
+S_0000000002769a10 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_2" "sky130_fd_sc_hd__lpflow_clkinvkapwr_2" 4 60067;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003651578 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b7290_0 .net "A", 0 0, o0000000003651578; 0 drivers
+L_00000000038ceec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9090_0 .net8 "KAPWR", 0 0, L_00000000038ceec0; 1 drivers, strength-aware
+L_00000000038d0350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b73d0_0 .net8 "VGND", 0 0, L_00000000038d0350; 1 drivers, strength-aware
+L_00000000038cf2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b85f0_0 .net8 "VNB", 0 0, L_00000000038cf2b0; 1 drivers, strength-aware
+L_00000000038cf160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7330_0 .net8 "VPB", 0 0, L_00000000038cf160; 1 drivers, strength-aware
+L_00000000038cef30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8c30_0 .net8 "VPWR", 0 0, L_00000000038cef30; 1 drivers, strength-aware
+v00000000036b7c90_0 .net "Y", 0 0, L_0000000003957bb0; 1 drivers
+S_00000000036a8080 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60082, 4 60360 1, S_0000000002769a10;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039581d0 .functor NOT 1, o0000000003651578, C4<0>, C4<0>, C4<0>;
+L_0000000003957bb0 .functor BUF 1, L_00000000039581d0, C4<0>, C4<0>, C4<0>;
+v00000000036b6ed0_0 .net "A", 0 0, o0000000003651578; alias, 0 drivers
+L_00000000038cefa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4950_0 .net8 "KAPWR", 0 0, L_00000000038cefa0; 1 drivers, strength-aware
+L_00000000038cf010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b4a90_0 .net8 "VGND", 0 0, L_00000000038cf010; 1 drivers, strength-aware
+L_00000000038cf240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b5fd0_0 .net8 "VNB", 0 0, L_00000000038cf240; 1 drivers, strength-aware
+L_00000000038cf550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b4b30_0 .net8 "VPB", 0 0, L_00000000038cf550; 1 drivers, strength-aware
+L_00000000038cf630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b6070_0 .net8 "VPWR", 0 0, L_00000000038cf630; 1 drivers, strength-aware
+v00000000036b7f10_0 .net "Y", 0 0, L_0000000003957bb0; alias, 1 drivers
+v00000000036b7fb0_0 .net "not0_out_Y", 0 0, L_00000000039581d0; 1 drivers
+S_00000000026a7600 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_4" "sky130_fd_sc_hd__lpflow_clkinvkapwr_4" 4 60470;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o00000000036518a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b8190_0 .net "A", 0 0, o00000000036518a8; 0 drivers
+L_00000000038cf6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b76f0_0 .net8 "KAPWR", 0 0, L_00000000038cf6a0; 1 drivers, strength-aware
+L_00000000038cf710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b8d70_0 .net8 "VGND", 0 0, L_00000000038cf710; 1 drivers, strength-aware
+L_00000000038cebb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b87d0_0 .net8 "VNB", 0 0, L_00000000038cebb0; 1 drivers, strength-aware
+L_00000000038ce9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7510_0 .net8 "VPB", 0 0, L_00000000038ce9f0; 1 drivers, strength-aware
+L_00000000038cf320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b80f0_0 .net8 "VPWR", 0 0, L_00000000038cf320; 1 drivers, strength-aware
+v00000000036b8230_0 .net "Y", 0 0, L_0000000003958940; 1 drivers
+S_00000000036a9b80 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60485, 4 60360 1, S_00000000026a7600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003957de0 .functor NOT 1, o00000000036518a8, C4<0>, C4<0>, C4<0>;
+L_0000000003958940 .functor BUF 1, L_0000000003957de0, C4<0>, C4<0>, C4<0>;
+v00000000036b8050_0 .net "A", 0 0, o00000000036518a8; alias, 0 drivers
+L_00000000038cfd30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8f50_0 .net8 "KAPWR", 0 0, L_00000000038cfd30; 1 drivers, strength-aware
+L_00000000038ceb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b7dd0_0 .net8 "VGND", 0 0, L_00000000038ceb40; 1 drivers, strength-aware
+L_00000000038cede0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b8730_0 .net8 "VNB", 0 0, L_00000000038cede0; 1 drivers, strength-aware
+L_00000000038cf390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8a50_0 .net8 "VPB", 0 0, L_00000000038cf390; 1 drivers, strength-aware
+L_00000000038d0120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9130_0 .net8 "VPWR", 0 0, L_00000000038d0120; 1 drivers, strength-aware
+v00000000036b7470_0 .net "Y", 0 0, L_0000000003958940; alias, 1 drivers
+v00000000036b84b0_0 .net "not0_out_Y", 0 0, L_0000000003957de0; 1 drivers
+S_00000000026a7780 .scope module, "sky130_fd_sc_hd__lpflow_clkinvkapwr_8" "sky130_fd_sc_hd__lpflow_clkinvkapwr_8" 4 60574;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+o0000000003651bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036b71f0_0 .net "A", 0 0, o0000000003651bd8; 0 drivers
+L_00000000038cec20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b82d0_0 .net8 "KAPWR", 0 0, L_00000000038cec20; 1 drivers, strength-aware
+L_00000000038cf780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9630_0 .net8 "VGND", 0 0, L_00000000038cf780; 1 drivers, strength-aware
+L_00000000038cea60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b8690_0 .net8 "VNB", 0 0, L_00000000038cea60; 1 drivers, strength-aware
+L_00000000038cf400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7e70_0 .net8 "VPB", 0 0, L_00000000038cf400; 1 drivers, strength-aware
+L_00000000038cfe80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8eb0_0 .net8 "VPWR", 0 0, L_00000000038cfe80; 1 drivers, strength-aware
+v00000000036b8af0_0 .net "Y", 0 0, L_0000000003957fa0; 1 drivers
+S_00000000036aa900 .scope module, "base" "sky130_fd_sc_hd__lpflow_clkinvkapwr" 4 60589, 4 60360 1, S_00000000026a7780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039589b0 .functor NOT 1, o0000000003651bd8, C4<0>, C4<0>, C4<0>;
+L_0000000003957fa0 .functor BUF 1, L_00000000039589b0, C4<0>, C4<0>, C4<0>;
+v00000000036b8e10_0 .net "A", 0 0, o0000000003651bd8; alias, 0 drivers
+L_00000000038cf8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7d30_0 .net8 "KAPWR", 0 0, L_00000000038cf8d0; 1 drivers, strength-aware
+L_00000000038cfb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b89b0_0 .net8 "VGND", 0 0, L_00000000038cfb70; 1 drivers, strength-aware
+L_00000000038cf9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b7150_0 .net8 "VNB", 0 0, L_00000000038cf9b0; 1 drivers, strength-aware
+L_00000000038cfa20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9310_0 .net8 "VPB", 0 0, L_00000000038cfa20; 1 drivers, strength-aware
+L_00000000038cfa90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b91d0_0 .net8 "VPWR", 0 0, L_00000000038cfa90; 1 drivers, strength-aware
+v00000000036b8550_0 .net "Y", 0 0, L_0000000003957fa0; alias, 1 drivers
+v00000000036b7970_0 .net "not0_out_Y", 0 0, L_00000000039589b0; 1 drivers
+S_00000000026a6a00 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_12" "sky130_fd_sc_hd__lpflow_decapkapwr_12" 4 157;
+ .timescale -9 -12;
+L_00000000038cec90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8870_0 .net8 "KAPWR", 0 0, L_00000000038cec90; 1 drivers, strength-aware
+L_00000000038cfb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b75b0_0 .net8 "VGND", 0 0, L_00000000038cfb00; 1 drivers, strength-aware
+L_00000000038cfbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9590_0 .net8 "VNB", 0 0, L_00000000038cfbe0; 1 drivers, strength-aware
+L_00000000038cffd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7650_0 .net8 "VPB", 0 0, L_00000000038cffd0; 1 drivers, strength-aware
+L_00000000038cfc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8910_0 .net8 "VPWR", 0 0, L_00000000038cfc50; 1 drivers, strength-aware
+S_00000000036a9880 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 165, 4 580 1, S_00000000026a6a00;
+ .timescale -9 -12;
+L_00000000038cfcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b96d0_0 .net8 "KAPWR", 0 0, L_00000000038cfcc0; 1 drivers, strength-aware
+L_00000000038cfda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b7790_0 .net8 "VGND", 0 0, L_00000000038cfda0; 1 drivers, strength-aware
+L_00000000038cff60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b94f0_0 .net8 "VNB", 0 0, L_00000000038cff60; 1 drivers, strength-aware
+L_00000000038d0270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9270_0 .net8 "VPB", 0 0, L_00000000038d0270; 1 drivers, strength-aware
+L_00000000038d0040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9450_0 .net8 "VPWR", 0 0, L_00000000038d0040; 1 drivers, strength-aware
+S_00000000026a8f80 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_3" "sky130_fd_sc_hd__lpflow_decapkapwr_3" 4 247;
+ .timescale -9 -12;
+L_00000000038d00b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7a10_0 .net8 "KAPWR", 0 0, L_00000000038d00b0; 1 drivers, strength-aware
+L_00000000038d02e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b93b0_0 .net8 "VGND", 0 0, L_00000000038d02e0; 1 drivers, strength-aware
+L_00000000038d1540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b7ab0_0 .net8 "VNB", 0 0, L_00000000038d1540; 1 drivers, strength-aware
+L_00000000038d1930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8370_0 .net8 "VPB", 0 0, L_00000000038d1930; 1 drivers, strength-aware
+L_00000000038d0c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9770_0 .net8 "VPWR", 0 0, L_00000000038d0c80; 1 drivers, strength-aware
+S_00000000036a8c80 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 255, 4 580 1, S_00000000026a8f80;
+ .timescale -9 -12;
+L_00000000038d1230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7830_0 .net8 "KAPWR", 0 0, L_00000000038d1230; 1 drivers, strength-aware
+L_00000000038d1460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b8b90_0 .net8 "VGND", 0 0, L_00000000038d1460; 1 drivers, strength-aware
+L_00000000038d12a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b8cd0_0 .net8 "VNB", 0 0, L_00000000038d12a0; 1 drivers, strength-aware
+L_00000000038d0cf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8ff0_0 .net8 "VPB", 0 0, L_00000000038d0cf0; 1 drivers, strength-aware
+L_00000000038d0d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b78d0_0 .net8 "VPWR", 0 0, L_00000000038d0d60; 1 drivers, strength-aware
+S_00000000026a5f80 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_4" "sky130_fd_sc_hd__lpflow_decapkapwr_4" 4 336;
+ .timescale -9 -12;
+L_00000000038d1770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb390_0 .net8 "KAPWR", 0 0, L_00000000038d1770; 1 drivers, strength-aware
+L_00000000038d0f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ba990_0 .net8 "VGND", 0 0, L_00000000038d0f20; 1 drivers, strength-aware
+L_00000000038d17e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9b30_0 .net8 "VNB", 0 0, L_00000000038d17e0; 1 drivers, strength-aware
+L_00000000038d1620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba7b0_0 .net8 "VPB", 0 0, L_00000000038d1620; 1 drivers, strength-aware
+L_00000000038d0820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bbcf0_0 .net8 "VPWR", 0 0, L_00000000038d0820; 1 drivers, strength-aware
+S_00000000036abb00 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 344, 4 580 1, S_00000000026a5f80;
+ .timescale -9 -12;
+L_00000000038d1a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9810_0 .net8 "KAPWR", 0 0, L_00000000038d1a10; 1 drivers, strength-aware
+L_00000000038d0890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b98b0_0 .net8 "VGND", 0 0, L_00000000038d0890; 1 drivers, strength-aware
+L_00000000038d1700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b7b50_0 .net8 "VNB", 0 0, L_00000000038d1700; 1 drivers, strength-aware
+L_00000000038d1850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b8410_0 .net8 "VPB", 0 0, L_00000000038d1850; 1 drivers, strength-aware
+L_00000000038d1a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b7bf0_0 .net8 "VPWR", 0 0, L_00000000038d1a80; 1 drivers, strength-aware
+S_00000000026a6280 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_6" "sky130_fd_sc_hd__lpflow_decapkapwr_6" 4 68;
+ .timescale -9 -12;
+L_00000000038d1690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bacb0_0 .net8 "KAPWR", 0 0, L_00000000038d1690; 1 drivers, strength-aware
+L_00000000038d1070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9bd0_0 .net8 "VGND", 0 0, L_00000000038d1070; 1 drivers, strength-aware
+L_00000000038d1d90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bc0b0_0 .net8 "VNB", 0 0, L_00000000038d1d90; 1 drivers, strength-aware
+L_00000000038d0900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb750_0 .net8 "VPB", 0 0, L_00000000038d0900; 1 drivers, strength-aware
+L_00000000038d0f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9950_0 .net8 "VPWR", 0 0, L_00000000038d0f90; 1 drivers, strength-aware
+S_00000000036aa780 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 76, 4 580 1, S_00000000026a6280;
+ .timescale -9 -12;
+L_00000000038d18c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036baa30_0 .net8 "KAPWR", 0 0, L_00000000038d18c0; 1 drivers, strength-aware
+L_00000000038d0660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb250_0 .net8 "VGND", 0 0, L_00000000038d0660; 1 drivers, strength-aware
+L_00000000038d1f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bc010_0 .net8 "VNB", 0 0, L_00000000038d1f50; 1 drivers, strength-aware
+L_00000000038d1d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bafd0_0 .net8 "VPB", 0 0, L_00000000038d1d20; 1 drivers, strength-aware
+L_00000000038d1af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb1b0_0 .net8 "VPWR", 0 0, L_00000000038d1af0; 1 drivers, strength-aware
+S_00000000026a6e80 .scope module, "sky130_fd_sc_hd__lpflow_decapkapwr_8" "sky130_fd_sc_hd__lpflow_decapkapwr_8" 4 671;
+ .timescale -9 -12;
+L_00000000038d1310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba170_0 .net8 "KAPWR", 0 0, L_00000000038d1310; 1 drivers, strength-aware
+L_00000000038d11c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b99f0_0 .net8 "VGND", 0 0, L_00000000038d11c0; 1 drivers, strength-aware
+L_00000000038d19a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bbbb0_0 .net8 "VNB", 0 0, L_00000000038d19a0; 1 drivers, strength-aware
+L_00000000038d1b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9a90_0 .net8 "VPB", 0 0, L_00000000038d1b60; 1 drivers, strength-aware
+L_00000000038d1e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bbf70_0 .net8 "VPWR", 0 0, L_00000000038d1e00; 1 drivers, strength-aware
+S_00000000036ac280 .scope module, "base" "sky130_fd_sc_hd__lpflow_decapkapwr" 4 679, 4 580 1, S_00000000026a6e80;
+ .timescale -9 -12;
+L_00000000038d0dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bbed0_0 .net8 "KAPWR", 0 0, L_00000000038d0dd0; 1 drivers, strength-aware
+L_00000000038d15b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb4d0_0 .net8 "VGND", 0 0, L_00000000038d15b0; 1 drivers, strength-aware
+L_00000000038d1bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb930_0 .net8 "VNB", 0 0, L_00000000038d1bd0; 1 drivers, strength-aware
+L_00000000038d1c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9ef0_0 .net8 "VPB", 0 0, L_00000000038d1c40; 1 drivers, strength-aware
+L_00000000038d1e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb7f0_0 .net8 "VPWR", 0 0, L_00000000038d1e70; 1 drivers, strength-aware
+S_00000000026a7300 .scope module, "sky130_fd_sc_hd__lpflow_inputiso0n_1" "sky130_fd_sc_hd__lpflow_inputiso0n_1" 4 85208;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003652868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bbe30_0 .net "A", 0 0, o0000000003652868; 0 drivers
+o0000000003652898 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036badf0_0 .net "SLEEP_B", 0 0, o0000000003652898; 0 drivers
+L_00000000038d06d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb890_0 .net8 "VGND", 0 0, L_00000000038d06d0; 1 drivers, strength-aware
+L_00000000038d07b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ba5d0_0 .net8 "VNB", 0 0, L_00000000038d07b0; 1 drivers, strength-aware
+L_00000000038d1000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba030_0 .net8 "VPB", 0 0, L_00000000038d1000; 1 drivers, strength-aware
+L_00000000038d0970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb2f0_0 .net8 "VPWR", 0 0, L_00000000038d0970; 1 drivers, strength-aware
+v00000000036baad0_0 .net "X", 0 0, L_0000000003958010; 1 drivers
+S_00000000036abe00 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso0n" 4 85224, 4 85507 1, S_00000000026a7300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+L_0000000003958010 .functor AND 1, o0000000003652868, o0000000003652898, C4<1>, C4<1>;
+v00000000036b9f90_0 .net "A", 0 0, o0000000003652868; alias, 0 drivers
+v00000000036ba530_0 .net "SLEEP_B", 0 0, o0000000003652898; alias, 0 drivers
+L_00000000038d0a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9c70_0 .net8 "VGND", 0 0, L_00000000038d0a50; 1 drivers, strength-aware
+L_00000000038d10e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bad50_0 .net8 "VNB", 0 0, L_00000000038d10e0; 1 drivers, strength-aware
+L_00000000038d1380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba210_0 .net8 "VPB", 0 0, L_00000000038d1380; 1 drivers, strength-aware
+L_00000000038d0740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036b9d10_0 .net8 "VPWR", 0 0, L_00000000038d0740; 1 drivers, strength-aware
+v00000000036b9db0_0 .net "X", 0 0, L_0000000003958010; alias, 1 drivers
+S_00000000026a5e00 .scope module, "sky130_fd_sc_hd__lpflow_inputiso0p_1" "sky130_fd_sc_hd__lpflow_inputiso0p_1" 4 70058;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP"
+o0000000003652b98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bbb10_0 .net "A", 0 0, o0000000003652b98; 0 drivers
+o0000000003652bc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bba70_0 .net "SLEEP", 0 0, o0000000003652bc8; 0 drivers
+L_00000000038d14d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb570_0 .net8 "VGND", 0 0, L_00000000038d14d0; 1 drivers, strength-aware
+L_00000000038d13f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ba350_0 .net8 "VNB", 0 0, L_00000000038d13f0; 1 drivers, strength-aware
+L_00000000038d09e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba3f0_0 .net8 "VPB", 0 0, L_00000000038d09e0; 1 drivers, strength-aware
+L_00000000038d1ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bab70_0 .net8 "VPWR", 0 0, L_00000000038d1ee0; 1 drivers, strength-aware
+v00000000036bae90_0 .net "X", 0 0, L_0000000003958a20; 1 drivers
+S_00000000036abf80 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso0p" 4 70074, 4 69945 1, S_00000000026a5e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP"
+L_00000000039580f0 .functor NOT 1, o0000000003652bc8, C4<0>, C4<0>, C4<0>;
+L_0000000003958a20 .functor AND 1, o0000000003652b98, L_00000000039580f0, C4<1>, C4<1>;
+v00000000036bb9d0_0 .net "A", 0 0, o0000000003652b98; alias, 0 drivers
+v00000000036bb430_0 .net "SLEEP", 0 0, o0000000003652bc8; alias, 0 drivers
+L_00000000038d0ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036b9e50_0 .net8 "VGND", 0 0, L_00000000038d0ac0; 1 drivers, strength-aware
+L_00000000038d0c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bbc50_0 .net8 "VNB", 0 0, L_00000000038d0c10; 1 drivers, strength-aware
+L_00000000038d0b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bbd90_0 .net8 "VPB", 0 0, L_00000000038d0b30; 1 drivers, strength-aware
+L_00000000038d1150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ba0d0_0 .net8 "VPWR", 0 0, L_00000000038d1150; 1 drivers, strength-aware
+v00000000036bb110_0 .net "X", 0 0, L_0000000003958a20; alias, 1 drivers
+v00000000036ba2b0_0 .net "sleepn", 0 0, L_00000000039580f0; 1 drivers
+S_00000000026a7000 .scope module, "sky130_fd_sc_hd__lpflow_inputiso1n_1" "sky130_fd_sc_hd__lpflow_inputiso1n_1" 4 97212;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003652ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ba8f0_0 .net "A", 0 0, o0000000003652ef8; 0 drivers
+o0000000003652f58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ba850_0 .net "SLEEP_B", 0 0, o0000000003652f58; 0 drivers
+L_00000000038d1cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bd190_0 .net8 "VGND", 0 0, L_00000000038d1cb0; 1 drivers, strength-aware
+L_00000000038d0eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bd230_0 .net8 "VNB", 0 0, L_00000000038d0eb0; 1 drivers, strength-aware
+L_00000000038d1fc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bcbf0_0 .net8 "VPB", 0 0, L_00000000038d1fc0; 1 drivers, strength-aware
+L_00000000038d2030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bd050_0 .net8 "VPWR", 0 0, L_00000000038d2030; 1 drivers, strength-aware
+v00000000036bd5f0_0 .net "X", 0 0, L_0000000003958240; 1 drivers
+S_00000000036aad80 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso1n" 4 97228, 4 97519 1, S_00000000026a7000;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+L_0000000003958160 .functor NOT 1, o0000000003652f58, C4<0>, C4<0>, C4<0>;
+L_0000000003958240 .functor OR 1, o0000000003652ef8, L_0000000003958160, C4<0>, C4<0>;
+v00000000036ba490_0 .net "A", 0 0, o0000000003652ef8; alias, 0 drivers
+v00000000036bb610_0 .net "SLEEP", 0 0, L_0000000003958160; 1 drivers
+v00000000036baf30_0 .net "SLEEP_B", 0 0, o0000000003652f58; alias, 0 drivers
+L_00000000038d04a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bb070_0 .net8 "VGND", 0 0, L_00000000038d04a0; 1 drivers, strength-aware
+L_00000000038d0510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ba670_0 .net8 "VNB", 0 0, L_00000000038d0510; 1 drivers, strength-aware
+L_00000000038d0ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bac10_0 .net8 "VPB", 0 0, L_00000000038d0ba0; 1 drivers, strength-aware
+L_00000000038d0580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bb6b0_0 .net8 "VPWR", 0 0, L_00000000038d0580; 1 drivers, strength-aware
+v00000000036ba710_0 .net "X", 0 0, L_0000000003958240; alias, 1 drivers
+S_00000000026a8680 .scope module, "sky130_fd_sc_hd__lpflow_inputiso1p_1" "sky130_fd_sc_hd__lpflow_inputiso1p_1" 4 49258;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP"
+o0000000003653258 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bc6f0_0 .net "A", 0 0, o0000000003653258; 0 drivers
+o0000000003653288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bd690_0 .net "SLEEP", 0 0, o0000000003653288; 0 drivers
+L_00000000038d0e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bc290_0 .net8 "VGND", 0 0, L_00000000038d0e40; 1 drivers, strength-aware
+L_00000000038d05f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036be090_0 .net8 "VNB", 0 0, L_00000000038d05f0; 1 drivers, strength-aware
+L_00000000038d35a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036be3b0_0 .net8 "VPB", 0 0, L_00000000038d35a0; 1 drivers, strength-aware
+L_00000000038d2500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036be810_0 .net8 "VPWR", 0 0, L_00000000038d2500; 1 drivers, strength-aware
+v00000000036be770_0 .net "X", 0 0, L_00000000039582b0; 1 drivers
+S_00000000036aa000 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputiso1p" 4 49274, 4 49149 1, S_00000000026a8680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "SLEEP"
+L_00000000039582b0 .functor OR 1, o0000000003653258, o0000000003653288, C4<0>, C4<0>;
+v00000000036bc150_0 .net "A", 0 0, o0000000003653258; alias, 0 drivers
+v00000000036bcf10_0 .net "SLEEP", 0 0, o0000000003653288; alias, 0 drivers
+L_00000000038d3ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bc8d0_0 .net8 "VGND", 0 0, L_00000000038d3ae0; 1 drivers, strength-aware
+L_00000000038d2260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bcd30_0 .net8 "VNB", 0 0, L_00000000038d2260; 1 drivers, strength-aware
+L_00000000038d38b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036be8b0_0 .net8 "VPB", 0 0, L_00000000038d38b0; 1 drivers, strength-aware
+L_00000000038d2f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bc5b0_0 .net8 "VPWR", 0 0, L_00000000038d2f10; 1 drivers, strength-aware
+v00000000036bdcd0_0 .net "X", 0 0, L_00000000039582b0; alias, 1 drivers
+S_00000000026a8800 .scope module, "sky130_fd_sc_hd__lpflow_inputisolatch_1" "sky130_fd_sc_hd__lpflow_inputisolatch_1" 4 78940;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+o0000000003653588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bd370_0 .net "D", 0 0, o0000000003653588; 0 drivers
+v00000000036bc510_0 .net "Q", 0 0, L_0000000003959f20; 1 drivers
+o0000000003653618 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bd410_0 .net "SLEEP_B", 0 0, o0000000003653618; 0 drivers
+L_00000000038d3220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bdaf0_0 .net8 "VGND", 0 0, L_00000000038d3220; 1 drivers, strength-aware
+L_00000000038d26c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bdff0_0 .net8 "VNB", 0 0, L_00000000038d26c0; 1 drivers, strength-aware
+L_00000000038d28f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bc650_0 .net8 "VPB", 0 0, L_00000000038d28f0; 1 drivers, strength-aware
+L_00000000038d3760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bcc90_0 .net8 "VPWR", 0 0, L_00000000038d3760; 1 drivers, strength-aware
+S_00000000036aa180 .scope module, "base" "sky130_fd_sc_hd__lpflow_inputisolatch" 4 78956, 4 78826 1, S_00000000026a8800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "D"
+ .port_info 2 /INPUT 1 "SLEEP_B"
+UDP_sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N .udp/sequ "sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N", 5, 2
+ ,"?*0?10-"
+ ,"??_?10-"
+ ,"??M?10-"
+ ,"00Q?100"
+ ,"11Q?101"
+ ,"?0R?100"
+ ,"?1R?101"
+ ,"?_1?100"
+ ,"?+1?101"
+ ,"?0r?100"
+ ,"?1r?101"
+ ,"1+x?101"
+ ,"0_x?100"
+ ,"?????*x";
+o00000000036535b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003653648 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000038d3c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000038d2650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003958a90 .udp UDP_sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N, o00000000036535b8, o0000000003653648, v00000000036be1d0_0, L_00000000038d3c30, L_00000000038d2650;
+L_0000000003959f20 .functor BUF 1, L_0000000003958a90, C4<0>, C4<0>, C4<0>;
+v00000000036bd0f0_0 .net "D", 0 0, o0000000003653588; alias, 0 drivers
+v00000000036bdf50_0 .net "D_delayed", 0 0, o00000000036535b8; 0 drivers
+v00000000036bcdd0_0 .net "Q", 0 0, L_0000000003959f20; alias, 1 drivers
+v00000000036bd730_0 .net "SLEEP_B", 0 0, o0000000003653618; alias, 0 drivers
+v00000000036bda50_0 .net "SLEEP_B_delayed", 0 0, o0000000003653648; 0 drivers
+v00000000036be130_0 .net8 "VGND", 0 0, L_00000000038d2650; 1 drivers, strength-aware
+L_00000000038d2f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bc330_0 .net8 "VNB", 0 0, L_00000000038d2f80; 1 drivers, strength-aware
+L_00000000038d2a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bd4b0_0 .net8 "VPB", 0 0, L_00000000038d2a40; 1 drivers, strength-aware
+v00000000036bc790_0 .net8 "VPWR", 0 0, L_00000000038d3c30; 1 drivers, strength-aware
+v00000000036bd2d0_0 .net "buf_Q", 0 0, L_0000000003958a90; 1 drivers
+v00000000036be1d0_0 .var "notifier", 0 0;
+S_00000000026a8200 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_1" "sky130_fd_sc_hd__lpflow_isobufsrc_1" 4 79705;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o0000000003653978 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bdd70_0 .net "A", 0 0, o0000000003653978; 0 drivers
+o00000000036539a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036be6d0_0 .net "SLEEP", 0 0, o00000000036539a8; 0 drivers
+L_00000000038d2730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bde10_0 .net8 "VGND", 0 0, L_00000000038d2730; 1 drivers, strength-aware
+L_00000000038d2ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036be270_0 .net8 "VNB", 0 0, L_00000000038d2ab0; 1 drivers, strength-aware
+L_00000000038d29d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bd910_0 .net8 "VPB", 0 0, L_00000000038d29d0; 1 drivers, strength-aware
+L_00000000038d3680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036be310_0 .net8 "VPWR", 0 0, L_00000000038d3680; 1 drivers, strength-aware
+v00000000036bc470_0 .net "X", 0 0, L_00000000039599e0; 1 drivers
+S_00000000036ada80 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79721, 4 80234 1, S_00000000026a8200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_00000000039593c0 .functor NOT 1, o00000000036539a8, C4<0>, C4<0>, C4<0>;
+L_0000000003959510 .functor AND 1, L_00000000039593c0, o0000000003653978, C4<1>, C4<1>;
+L_00000000039599e0 .functor BUF 1, L_0000000003959510, C4<0>, C4<0>, C4<0>;
+v00000000036bd550_0 .net "A", 0 0, o0000000003653978; alias, 0 drivers
+v00000000036bcb50_0 .net "SLEEP", 0 0, o00000000036539a8; alias, 0 drivers
+L_00000000038d3840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bd7d0_0 .net8 "VGND", 0 0, L_00000000038d3840; 1 drivers, strength-aware
+L_00000000038d3450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bd870_0 .net8 "VNB", 0 0, L_00000000038d3450; 1 drivers, strength-aware
+L_00000000038d2b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bc1f0_0 .net8 "VPB", 0 0, L_00000000038d2b20; 1 drivers, strength-aware
+L_00000000038d3a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bc830_0 .net8 "VPWR", 0 0, L_00000000038d3a70; 1 drivers, strength-aware
+v00000000036bc3d0_0 .net "X", 0 0, L_00000000039599e0; alias, 1 drivers
+v00000000036bdb90_0 .net "and0_out_X", 0 0, L_0000000003959510; 1 drivers
+v00000000036bcfb0_0 .net "not0_out", 0 0, L_00000000039593c0; 1 drivers
+S_00000000026a5980 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_16" "sky130_fd_sc_hd__lpflow_isobufsrc_16" 4 79921;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o0000000003653d08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bca10_0 .net "A", 0 0, o0000000003653d08; 0 drivers
+o0000000003653d38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bcab0_0 .net "SLEEP", 0 0, o0000000003653d38; 0 drivers
+L_00000000038d37d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bf350_0 .net8 "VGND", 0 0, L_00000000038d37d0; 1 drivers, strength-aware
+L_00000000038d2ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bedb0_0 .net8 "VNB", 0 0, L_00000000038d2ce0; 1 drivers, strength-aware
+L_00000000038d2b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036beef0_0 .net8 "VPB", 0 0, L_00000000038d2b90; 1 drivers, strength-aware
+L_00000000038d27a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c0570_0 .net8 "VPWR", 0 0, L_00000000038d27a0; 1 drivers, strength-aware
+v00000000036bf850_0 .net "X", 0 0, L_000000000395a540; 1 drivers
+S_00000000036ad600 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79937, 4 80234 1, S_00000000026a5980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_00000000039596d0 .functor NOT 1, o0000000003653d38, C4<0>, C4<0>, C4<0>;
+L_0000000003959040 .functor AND 1, L_00000000039596d0, o0000000003653d08, C4<1>, C4<1>;
+L_000000000395a540 .functor BUF 1, L_0000000003959040, C4<0>, C4<0>, C4<0>;
+v00000000036bd9b0_0 .net "A", 0 0, o0000000003653d08; alias, 0 drivers
+v00000000036bdc30_0 .net "SLEEP", 0 0, o0000000003653d38; alias, 0 drivers
+L_00000000038d2880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bdeb0_0 .net8 "VGND", 0 0, L_00000000038d2880; 1 drivers, strength-aware
+L_00000000038d3920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036be4f0_0 .net8 "VNB", 0 0, L_00000000038d3920; 1 drivers, strength-aware
+L_00000000038d2ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036be450_0 .net8 "VPB", 0 0, L_00000000038d2ff0; 1 drivers, strength-aware
+L_00000000038d3300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bc970_0 .net8 "VPWR", 0 0, L_00000000038d3300; 1 drivers, strength-aware
+v00000000036be590_0 .net "X", 0 0, L_000000000395a540; alias, 1 drivers
+v00000000036bce70_0 .net "and0_out_X", 0 0, L_0000000003959040; 1 drivers
+v00000000036be630_0 .net "not0_out", 0 0, L_00000000039596d0; 1 drivers
+S_00000000026a8b00 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_2" "sky130_fd_sc_hd__lpflow_isobufsrc_2" 4 79813;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o0000000003654098 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c06b0_0 .net "A", 0 0, o0000000003654098; 0 drivers
+o00000000036540c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036be9f0_0 .net "SLEEP", 0 0, o00000000036540c8; 0 drivers
+L_00000000038d3060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bf990_0 .net8 "VGND", 0 0, L_00000000038d3060; 1 drivers, strength-aware
+L_00000000038d2810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0e30_0 .net8 "VNB", 0 0, L_00000000038d2810; 1 drivers, strength-aware
+L_00000000038d3140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bf530_0 .net8 "VPB", 0 0, L_00000000038d3140; 1 drivers, strength-aware
+L_00000000038d3610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bf490_0 .net8 "VPWR", 0 0, L_00000000038d3610; 1 drivers, strength-aware
+v00000000036bec70_0 .net "X", 0 0, L_0000000003959430; 1 drivers
+S_00000000036aa600 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 79829, 4 80234 1, S_00000000026a8b00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_000000000395a000 .functor NOT 1, o00000000036540c8, C4<0>, C4<0>, C4<0>;
+L_0000000003959ac0 .functor AND 1, L_000000000395a000, o0000000003654098, C4<1>, C4<1>;
+L_0000000003959430 .functor BUF 1, L_0000000003959ac0, C4<0>, C4<0>, C4<0>;
+v00000000036c07f0_0 .net "A", 0 0, o0000000003654098; alias, 0 drivers
+v00000000036bee50_0 .net "SLEEP", 0 0, o00000000036540c8; alias, 0 drivers
+L_00000000038d2110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0250_0 .net8 "VGND", 0 0, L_00000000038d2110; 1 drivers, strength-aware
+L_00000000038d22d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0930_0 .net8 "VNB", 0 0, L_00000000038d22d0; 1 drivers, strength-aware
+L_00000000038d3b50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bef90_0 .net8 "VPB", 0 0, L_00000000038d3b50; 1 drivers, strength-aware
+L_00000000038d3370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bf030_0 .net8 "VPWR", 0 0, L_00000000038d3370; 1 drivers, strength-aware
+v00000000036be950_0 .net "X", 0 0, L_0000000003959430; alias, 1 drivers
+v00000000036c0b10_0 .net "and0_out_X", 0 0, L_0000000003959ac0; 1 drivers
+v00000000036c0f70_0 .net "not0_out", 0 0, L_000000000395a000; 1 drivers
+S_00000000026a7c00 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_4" "sky130_fd_sc_hd__lpflow_isobufsrc_4" 4 80457;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o0000000003654428 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bf2b0_0 .net "A", 0 0, o0000000003654428; 0 drivers
+o0000000003654458 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bfc10_0 .net "SLEEP", 0 0, o0000000003654458; 0 drivers
+L_00000000038d36f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0bb0_0 .net8 "VGND", 0 0, L_00000000038d36f0; 1 drivers, strength-aware
+L_00000000038d2420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0a70_0 .net8 "VNB", 0 0, L_00000000038d2420; 1 drivers, strength-aware
+L_00000000038d30d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bea90_0 .net8 "VPB", 0 0, L_00000000038d30d0; 1 drivers, strength-aware
+L_00000000038d2960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c10b0_0 .net8 "VPWR", 0 0, L_00000000038d2960; 1 drivers, strength-aware
+v00000000036bf7b0_0 .net "X", 0 0, L_0000000003958d30; 1 drivers
+S_00000000036ac700 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 80473, 4 80234 1, S_00000000026a7c00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_00000000039594a0 .functor NOT 1, o0000000003654458, C4<0>, C4<0>, C4<0>;
+L_0000000003958da0 .functor AND 1, L_00000000039594a0, o0000000003654428, C4<1>, C4<1>;
+L_0000000003958d30 .functor BUF 1, L_0000000003958da0, C4<0>, C4<0>, C4<0>;
+v00000000036c0ed0_0 .net "A", 0 0, o0000000003654428; alias, 0 drivers
+v00000000036bf0d0_0 .net "SLEEP", 0 0, o0000000003654458; alias, 0 drivers
+L_00000000038d2c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0cf0_0 .net8 "VGND", 0 0, L_00000000038d2c00; 1 drivers, strength-aware
+L_00000000038d2340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c09d0_0 .net8 "VNB", 0 0, L_00000000038d2340; 1 drivers, strength-aware
+L_00000000038d33e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c0c50_0 .net8 "VPB", 0 0, L_00000000038d33e0; 1 drivers, strength-aware
+L_00000000038d3990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bffd0_0 .net8 "VPWR", 0 0, L_00000000038d3990; 1 drivers, strength-aware
+v00000000036c0610_0 .net "X", 0 0, L_0000000003958d30; alias, 1 drivers
+v00000000036c0d90_0 .net "and0_out_X", 0 0, L_0000000003958da0; 1 drivers
+v00000000036c1010_0 .net "not0_out", 0 0, L_00000000039594a0; 1 drivers
+S_00000000026a8380 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrc_8" "sky130_fd_sc_hd__lpflow_isobufsrc_8" 4 80349;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o00000000036547b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bf3f0_0 .net "A", 0 0, o00000000036547b8; 0 drivers
+o00000000036547e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036bf8f0_0 .net "SLEEP", 0 0, o00000000036547e8; 0 drivers
+L_00000000038d3bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bf5d0_0 .net8 "VGND", 0 0, L_00000000038d3bc0; 1 drivers, strength-aware
+L_00000000038d3290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bf670_0 .net8 "VNB", 0 0, L_00000000038d3290; 1 drivers, strength-aware
+L_00000000038d2c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bf710_0 .net8 "VPB", 0 0, L_00000000038d2c70; 1 drivers, strength-aware
+L_00000000038d31b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bfa30_0 .net8 "VPWR", 0 0, L_00000000038d31b0; 1 drivers, strength-aware
+v00000000036bfad0_0 .net "X", 0 0, L_0000000003958e10; 1 drivers
+S_00000000036ab200 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrc" 4 80365, 4 80234 1, S_00000000026a8380;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_0000000003959820 .functor NOT 1, o00000000036547e8, C4<0>, C4<0>, C4<0>;
+L_0000000003959a50 .functor AND 1, L_0000000003959820, o00000000036547b8, C4<1>, C4<1>;
+L_0000000003958e10 .functor BUF 1, L_0000000003959a50, C4<0>, C4<0>, C4<0>;
+v00000000036bfb70_0 .net "A", 0 0, o00000000036547b8; alias, 0 drivers
+v00000000036beb30_0 .net "SLEEP", 0 0, o00000000036547e8; alias, 0 drivers
+L_00000000038d34c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036bebd0_0 .net8 "VGND", 0 0, L_00000000038d34c0; 1 drivers, strength-aware
+L_00000000038d2d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0430_0 .net8 "VNB", 0 0, L_00000000038d2d50; 1 drivers, strength-aware
+L_00000000038d2dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bed10_0 .net8 "VPB", 0 0, L_00000000038d2dc0; 1 drivers, strength-aware
+L_00000000038d2570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bfd50_0 .net8 "VPWR", 0 0, L_00000000038d2570; 1 drivers, strength-aware
+v00000000036bf170_0 .net "X", 0 0, L_0000000003958e10; alias, 1 drivers
+v00000000036bf210_0 .net "and0_out_X", 0 0, L_0000000003959a50; 1 drivers
+v00000000036bfcb0_0 .net "not0_out", 0 0, L_0000000003959820; 1 drivers
+S_00000000026a7480 .scope module, "sky130_fd_sc_hd__lpflow_isobufsrckapwr_16" "sky130_fd_sc_hd__lpflow_isobufsrckapwr_16" 4 95579;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+o0000000003654b48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c0750_0 .net "A", 0 0, o0000000003654b48; 0 drivers
+L_00000000038d3530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2230_0 .net8 "KAPWR", 0 0, L_00000000038d3530; 1 drivers, strength-aware
+o0000000003654ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c1c90_0 .net "SLEEP", 0 0, o0000000003654ba8; 0 drivers
+L_00000000038d3a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c2a50_0 .net8 "VGND", 0 0, L_00000000038d3a00; 1 drivers, strength-aware
+L_00000000038d2ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c2c30_0 .net8 "VNB", 0 0, L_00000000038d2ea0; 1 drivers, strength-aware
+L_00000000038d2490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1330_0 .net8 "VPB", 0 0, L_00000000038d2490; 1 drivers, strength-aware
+L_00000000038d20a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c24b0_0 .net8 "VPWR", 0 0, L_00000000038d20a0; 1 drivers, strength-aware
+v00000000036c16f0_0 .net "X", 0 0, L_0000000003959b30; 1 drivers
+S_00000000036ab680 .scope module, "base" "sky130_fd_sc_hd__lpflow_isobufsrckapwr" 4 95596, 4 95906 1, S_00000000026a7480;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "SLEEP"
+ .port_info 2 /INPUT 1 "A"
+L_0000000003959f90 .functor NOT 1, o0000000003654ba8, C4<0>, C4<0>, C4<0>;
+L_0000000003959580 .functor AND 1, L_0000000003959f90, o0000000003654b48, C4<1>, C4<1>;
+L_0000000003959b30 .functor BUF 1, L_0000000003959580, C4<0>, C4<0>, C4<0>;
+v00000000036bfdf0_0 .net "A", 0 0, o0000000003654b48; alias, 0 drivers
+L_00000000038d2e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036bfe90_0 .net8 "KAPWR", 0 0, L_00000000038d2e30; 1 drivers, strength-aware
+v00000000036bff30_0 .net "SLEEP", 0 0, o0000000003654ba8; alias, 0 drivers
+L_00000000038d23b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0890_0 .net8 "VGND", 0 0, L_00000000038d23b0; 1 drivers, strength-aware
+L_00000000038d25e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c0070_0 .net8 "VNB", 0 0, L_00000000038d25e0; 1 drivers, strength-aware
+L_00000000038d2180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c0110_0 .net8 "VPB", 0 0, L_00000000038d2180; 1 drivers, strength-aware
+L_00000000038d21f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c01b0_0 .net8 "VPWR", 0 0, L_00000000038d21f0; 1 drivers, strength-aware
+v00000000036c02f0_0 .net "X", 0 0, L_0000000003959b30; alias, 1 drivers
+v00000000036c04d0_0 .net "and0_out_X", 0 0, L_0000000003959580; 1 drivers
+v00000000036c0390_0 .net "not0_out", 0 0, L_0000000003959f90; 1 drivers
+S_00000000026a6880 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1" 4 38004;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003654f38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c2b90_0 .net "A", 0 0, o0000000003654f38; 0 drivers
+L_00000000038d3d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3130_0 .net8 "VGND", 0 0, L_00000000038d3d80; 1 drivers, strength-aware
+L_00000000038d3ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1d30_0 .net8 "VPB", 0 0, L_00000000038d3ed0; 1 drivers, strength-aware
+L_00000000038d3e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3590_0 .net8 "VPWR", 0 0, L_00000000038d3e60; 1 drivers, strength-aware
+v00000000036c1dd0_0 .net "X", 0 0, L_000000000395a150; 1 drivers
+S_00000000036a8e00 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 38018, 4 37899 1, S_00000000026a6880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_000000000395a150 .functor BUF 1, o0000000003654f38, C4<0>, C4<0>, C4<0>;
+v00000000036c2050_0 .net "A", 0 0, o0000000003654f38; alias, 0 drivers
+L_00000000038d3ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c1510_0 .net8 "VGND", 0 0, L_00000000038d3ca0; 1 drivers, strength-aware
+L_00000000038d3df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c20f0_0 .net8 "VPB", 0 0, L_00000000038d3df0; 1 drivers, strength-aware
+L_00000000038d3f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2af0_0 .net8 "VPWR", 0 0, L_00000000038d3f40; 1 drivers, strength-aware
+v00000000036c2ff0_0 .net "X", 0 0, L_000000000395a150; alias, 1 drivers
+S_00000000026a5800 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2" 4 37600;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003655178 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c1e70_0 .net "A", 0 0, o0000000003655178; 0 drivers
+L_00000000038d3d10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c18d0_0 .net8 "VGND", 0 0, L_00000000038d3d10; 1 drivers, strength-aware
+L_00000000038d76d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1b50_0 .net8 "VPB", 0 0, L_00000000038d76d0; 1 drivers, strength-aware
+L_00000000038d7120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c36d0_0 .net8 "VPWR", 0 0, L_00000000038d7120; 1 drivers, strength-aware
+v00000000036c13d0_0 .net "X", 0 0, L_00000000039595f0; 1 drivers
+S_00000000036aaf00 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 37614, 4 37899 1, S_00000000026a5800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_00000000039595f0 .functor BUF 1, o0000000003655178, C4<0>, C4<0>, C4<0>;
+v00000000036c11f0_0 .net "A", 0 0, o0000000003655178; alias, 0 drivers
+L_00000000038d7890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c2190_0 .net8 "VGND", 0 0, L_00000000038d7890; 1 drivers, strength-aware
+L_00000000038d6470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1290_0 .net8 "VPB", 0 0, L_00000000038d6470; 1 drivers, strength-aware
+L_00000000038d6860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2eb0_0 .net8 "VPWR", 0 0, L_00000000038d6860; 1 drivers, strength-aware
+v00000000036c2550_0 .net "X", 0 0, L_00000000039595f0; alias, 1 drivers
+S_00000000026a6100 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4" 4 38108;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000036553b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c2410_0 .net "A", 0 0, o00000000036553b8; 0 drivers
+L_00000000038d6a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3310_0 .net8 "VGND", 0 0, L_00000000038d6a90; 1 drivers, strength-aware
+L_00000000038d75f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c31d0_0 .net8 "VPB", 0 0, L_00000000038d75f0; 1 drivers, strength-aware
+L_00000000038d61d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c29b0_0 .net8 "VPWR", 0 0, L_00000000038d61d0; 1 drivers, strength-aware
+v00000000036c3810_0 .net "X", 0 0, L_0000000003959ba0; 1 drivers
+S_00000000036ac100 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap" 4 38122, 4 37899 1, S_00000000026a6100;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003959ba0 .functor BUF 1, o00000000036553b8, C4<0>, C4<0>, C4<0>;
+v00000000036c2910_0 .net "A", 0 0, o00000000036553b8; alias, 0 drivers
+L_00000000038d6010 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c2e10_0 .net8 "VGND", 0 0, L_00000000038d6010; 1 drivers, strength-aware
+L_00000000038d68d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c22d0_0 .net8 "VPB", 0 0, L_00000000038d68d0; 1 drivers, strength-aware
+L_00000000038d6da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2cd0_0 .net8 "VPWR", 0 0, L_00000000038d6da0; 1 drivers, strength-aware
+v00000000036c1470_0 .net "X", 0 0, L_0000000003959ba0; alias, 1 drivers
+S_00000000026a7d80 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4" 4 74157;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o00000000036555f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c1f10_0 .net "A", 0 0, o00000000036555f8; 0 drivers
+L_00000000038d7190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c2370_0 .net8 "VGND", 0 0, L_00000000038d7190; 1 drivers, strength-aware
+L_00000000038d64e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c1650_0 .net8 "VNB", 0 0, L_00000000038d64e0; 1 drivers, strength-aware
+L_00000000038d6b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1150_0 .net8 "VPB", 0 0, L_00000000038d6b00; 1 drivers, strength-aware
+L_00000000038d6cc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1790_0 .net8 "VPWR", 0 0, L_00000000038d6cc0; 1 drivers, strength-aware
+v00000000036c1fb0_0 .net "X", 0 0, L_0000000003959740; 1 drivers
+S_00000000036aaa80 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell" 4 74172, 4 74050 1, S_00000000026a7d80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003959740 .functor BUF 1, o00000000036555f8, C4<0>, C4<0>, C4<0>;
+v00000000036c15b0_0 .net "A", 0 0, o00000000036555f8; alias, 0 drivers
+L_00000000038d6b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c25f0_0 .net8 "VGND", 0 0, L_00000000038d6b70; 1 drivers, strength-aware
+L_00000000038d6550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3630_0 .net8 "VNB", 0 0, L_00000000038d6550; 1 drivers, strength-aware
+L_00000000038d65c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2690_0 .net8 "VPB", 0 0, L_00000000038d65c0; 1 drivers, strength-aware
+L_00000000038d6fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2d70_0 .net8 "VPWR", 0 0, L_00000000038d6fd0; 1 drivers, strength-aware
+v00000000036c2730_0 .net "X", 0 0, L_0000000003959740; alias, 1 drivers
+S_00000000026a6580 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1" 4 41019;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003655898 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c3090_0 .net "A", 0 0, o0000000003655898; 0 drivers
+L_00000000038d7660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3450_0 .net8 "VGND", 0 0, L_00000000038d7660; 1 drivers, strength-aware
+L_00000000038d7740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1970_0 .net8 "VPB", 0 0, L_00000000038d7740; 1 drivers, strength-aware
+L_00000000038d7820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3270_0 .net8 "VPWR", 0 0, L_00000000038d7820; 1 drivers, strength-aware
+v00000000036c33b0_0 .net "X", 0 0, L_0000000003959eb0; 1 drivers
+S_00000000036aac00 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41033, 4 40915 1, S_00000000026a6580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003959eb0 .functor BUF 1, o0000000003655898, C4<0>, C4<0>, C4<0>;
+v00000000036c1bf0_0 .net "A", 0 0, o0000000003655898; alias, 0 drivers
+L_00000000038d6c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c27d0_0 .net8 "VGND", 0 0, L_00000000038d6c50; 1 drivers, strength-aware
+L_00000000038d6630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1830_0 .net8 "VPB", 0 0, L_00000000038d6630; 1 drivers, strength-aware
+L_00000000038d7270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c2f50_0 .net8 "VPWR", 0 0, L_00000000038d7270; 1 drivers, strength-aware
+v00000000036c2870_0 .net "X", 0 0, L_0000000003959eb0; alias, 1 drivers
+S_00000000026a7a80 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2" 4 41225;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003655ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c40d0_0 .net "A", 0 0, o0000000003655ad8; 0 drivers
+L_00000000038d6240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c42b0_0 .net8 "VGND", 0 0, L_00000000038d6240; 1 drivers, strength-aware
+L_00000000038d6940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5110_0 .net8 "VPB", 0 0, L_00000000038d6940; 1 drivers, strength-aware
+L_00000000038d5d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4a30_0 .net8 "VPWR", 0 0, L_00000000038d5d00; 1 drivers, strength-aware
+v00000000036c3e50_0 .net "X", 0 0, L_0000000003958e80; 1 drivers
+S_00000000036ac880 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41239, 4 40915 1, S_00000000026a7a80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003958e80 .functor BUF 1, o0000000003655ad8, C4<0>, C4<0>, C4<0>;
+v00000000036c34f0_0 .net "A", 0 0, o0000000003655ad8; alias, 0 drivers
+L_00000000038d69b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3770_0 .net8 "VGND", 0 0, L_00000000038d69b0; 1 drivers, strength-aware
+L_00000000038d62b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c1a10_0 .net8 "VPB", 0 0, L_00000000038d62b0; 1 drivers, strength-aware
+L_00000000038d5d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c38b0_0 .net8 "VPWR", 0 0, L_00000000038d5d70; 1 drivers, strength-aware
+v00000000036c1ab0_0 .net "X", 0 0, L_0000000003958e80; alias, 1 drivers
+S_00000000026a6400 .scope module, "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4" 4 41122;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o0000000003655d18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c5390_0 .net "A", 0 0, o0000000003655d18; 0 drivers
+L_00000000038d66a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c52f0_0 .net8 "VGND", 0 0, L_00000000038d66a0; 1 drivers, strength-aware
+L_00000000038d6320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4530_0 .net8 "VPB", 0 0, L_00000000038d6320; 1 drivers, strength-aware
+L_00000000038d77b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4490_0 .net8 "VPWR", 0 0, L_00000000038d77b0; 1 drivers, strength-aware
+v00000000036c3c70_0 .net "X", 0 0, L_0000000003959200; 1 drivers
+S_00000000036aa300 .scope module, "base" "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap" 4 41136, 4 40915 1, S_00000000026a6400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003959200 .functor BUF 1, o0000000003655d18, C4<0>, C4<0>, C4<0>;
+v00000000036c5d90_0 .net "A", 0 0, o0000000003655d18; alias, 0 drivers
+L_00000000038d6710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5b10_0 .net8 "VGND", 0 0, L_00000000038d6710; 1 drivers, strength-aware
+L_00000000038d6780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5890_0 .net8 "VPB", 0 0, L_00000000038d6780; 1 drivers, strength-aware
+L_00000000038d6390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4990_0 .net8 "VPWR", 0 0, L_00000000038d6390; 1 drivers, strength-aware
+v00000000036c54d0_0 .net "X", 0 0, L_0000000003959200; alias, 1 drivers
+S_00000000026a7f00 .scope module, "sky130_fd_sc_hd__macro_sparecell" "sky130_fd_sc_hd__macro_sparecell" 4 29409;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "LO"
+L_0000000003959900 .functor BUFT 1, C8<550>, C4<0>, C4<0>, C4<0>;
+L_0000000003959970 .functor BUF 1, L_0000000003959900, C4<0>, C4<0>, C4<0>;
+v00000000036c6bf0_0 .net "LO", 0 0, L_0000000003959970; 1 drivers
+v00000000036c6290_0 .net "invleft", 0 0, L_000000000395a4d0; 1 drivers
+v00000000036c6f10_0 .net "invright", 0 0, L_00000000039597b0; 1 drivers
+v00000000036c6c90_0 .net "nd2left", 0 0, L_0000000003959cf0; 1 drivers
+v00000000036c77d0_0 .net "nd2right", 0 0, L_0000000003959890; 1 drivers
+L_0000000003959c80 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
+v00000000036c7cd0_0 .net8 "net7", 0 0, L_0000000003959c80; 1 drivers, strength-aware
+v00000000036c7730_0 .net "nor2left", 0 0, L_0000000003959660; 1 drivers
+v00000000036c7870_0 .net "nor2right", 0 0, L_0000000003959dd0; 1 drivers
+v00000000036c7d70_0 .net8 "tielo", 0 0, L_0000000003959900; 1 drivers, strength-aware
+S_00000000036aca00 .scope module, "conb0" "sky130_fd_sc_hd__conb_1" 4 29433, 4 20862 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v00000000036c3d10_0 .net8 "HI", 0 0, L_0000000003959c80; alias, 1 drivers, strength-aware
+v00000000036c4350_0 .net8 "LO", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d8620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c4c10_0 .net8 "VGND", 0 0, L_00000000038d8620; 1 drivers, strength-aware
+L_00000000038d88c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5bb0_0 .net8 "VNB", 0 0, L_00000000038d88c0; 1 drivers, strength-aware
+L_00000000038d9180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5570_0 .net8 "VPB", 0 0, L_00000000038d9180; 1 drivers, strength-aware
+L_00000000038d8af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3a90_0 .net8 "VPWR", 0 0, L_00000000038d8af0; 1 drivers, strength-aware
+S_00000000036adc00 .scope module, "base" "sky130_fd_sc_hd__conb" 4 20876, 4 21149 1, S_00000000036aca00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "HI"
+ .port_info 1 /OUTPUT 1 "LO"
+v00000000036c45d0_0 .net8 "HI", 0 0, L_0000000003959c80; alias, 1 drivers, strength-aware
+v00000000036c51b0_0 .net8 "LO", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d92d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5c50_0 .net8 "VGND", 0 0, L_00000000038d92d0; 1 drivers, strength-aware
+L_00000000038d8690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c4fd0_0 .net8 "VNB", 0 0, L_00000000038d8690; 1 drivers, strength-aware
+L_00000000038d9340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5610_0 .net8 "VPB", 0 0, L_00000000038d9340; 1 drivers, strength-aware
+L_00000000038d8d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4ad0_0 .net8 "VPWR", 0 0, L_00000000038d8d90; 1 drivers, strength-aware
+S_00000000036ab080 .scope module, "inv0" "sky130_fd_sc_hd__inv_2" 4 29427, 4 54053 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v00000000036c4cb0_0 .net "A", 0 0, L_0000000003959660; alias, 1 drivers
+L_00000000038d6400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3bd0_0 .net8 "VGND", 0 0, L_00000000038d6400; 1 drivers, strength-aware
+L_00000000038d67f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c3950_0 .net8 "VNB", 0 0, L_00000000038d67f0; 1 drivers, strength-aware
+L_00000000038d6a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5ed0_0 .net8 "VPB", 0 0, L_00000000038d6a20; 1 drivers, strength-aware
+L_00000000038d6be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c47b0_0 .net8 "VPWR", 0 0, L_00000000038d6be0; 1 drivers, strength-aware
+v00000000036c5750_0 .net "Y", 0 0, L_000000000395a4d0; alias, 1 drivers
+S_00000000036ab380 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000036ab080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000395a620 .functor NOT 1, L_0000000003959660, C4<0>, C4<0>, C4<0>;
+L_000000000395a4d0 .functor BUF 1, L_000000000395a620, C4<0>, C4<0>, C4<0>;
+v00000000036c4b70_0 .net "A", 0 0, L_0000000003959660; alias, 1 drivers
+L_00000000038d6d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5cf0_0 .net8 "VGND", 0 0, L_00000000038d6d30; 1 drivers, strength-aware
+L_00000000038d6e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5250_0 .net8 "VNB", 0 0, L_00000000038d6e10; 1 drivers, strength-aware
+L_00000000038d6e80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c56b0_0 .net8 "VPB", 0 0, L_00000000038d6e80; 1 drivers, strength-aware
+L_00000000038d6080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5e30_0 .net8 "VPWR", 0 0, L_00000000038d6080; 1 drivers, strength-aware
+v00000000036c43f0_0 .net "Y", 0 0, L_000000000395a4d0; alias, 1 drivers
+v00000000036c4e90_0 .net "not0_out_Y", 0 0, L_000000000395a620; 1 drivers
+S_00000000036ab500 .scope module, "inv1" "sky130_fd_sc_hd__inv_2" 4 29428, 4 54053 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+v00000000036c5f70_0 .net "A", 0 0, L_0000000003959dd0; alias, 1 drivers
+L_00000000038d5de0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5930_0 .net8 "VGND", 0 0, L_00000000038d5de0; 1 drivers, strength-aware
+L_00000000038d6ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c59d0_0 .net8 "VNB", 0 0, L_00000000038d6ef0; 1 drivers, strength-aware
+L_00000000038d7200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3ef0_0 .net8 "VPB", 0 0, L_00000000038d7200; 1 drivers, strength-aware
+L_00000000038d5f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5a70_0 .net8 "VPWR", 0 0, L_00000000038d5f30; 1 drivers, strength-aware
+v00000000036c4210_0 .net "Y", 0 0, L_00000000039597b0; alias, 1 drivers
+S_00000000036ab800 .scope module, "base" "sky130_fd_sc_hd__inv" 4 54067, 4 54841 1, S_00000000036ab500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+L_000000000395a0e0 .functor NOT 1, L_0000000003959dd0, C4<0>, C4<0>, C4<0>;
+L_00000000039597b0 .functor BUF 1, L_000000000395a0e0, C4<0>, C4<0>, C4<0>;
+v00000000036c4d50_0 .net "A", 0 0, L_0000000003959dd0; alias, 1 drivers
+L_00000000038d6f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c4670_0 .net8 "VGND", 0 0, L_00000000038d6f60; 1 drivers, strength-aware
+L_00000000038d7040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c5070_0 .net8 "VNB", 0 0, L_00000000038d7040; 1 drivers, strength-aware
+L_00000000038d7580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c5430_0 .net8 "VPB", 0 0, L_00000000038d7580; 1 drivers, strength-aware
+L_00000000038d5fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c4710_0 .net8 "VPWR", 0 0, L_00000000038d5fa0; 1 drivers, strength-aware
+v00000000036c4170_0 .net "Y", 0 0, L_00000000039597b0; alias, 1 drivers
+v00000000036c57f0_0 .net "not0_out_Y", 0 0, L_000000000395a0e0; 1 drivers
+S_00000000036ad780 .scope module, "nand20" "sky130_fd_sc_hd__nand2_2" 4 29431, 4 8552 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000036c4030_0 .net8 "A", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+v00000000036c48f0_0 .net8 "B", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d8e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c4f30_0 .net8 "VGND", 0 0, L_00000000038d8e70; 1 drivers, strength-aware
+L_00000000038d8070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c6510_0 .net8 "VNB", 0 0, L_00000000038d8070; 1 drivers, strength-aware
+L_00000000038d7970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c8090_0 .net8 "VPB", 0 0, L_00000000038d7970; 1 drivers, strength-aware
+L_00000000038d89a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6fb0_0 .net8 "VPWR", 0 0, L_00000000038d89a0; 1 drivers, strength-aware
+v00000000036c7910_0 .net "Y", 0 0, L_0000000003959890; alias, 1 drivers
+S_00000000036add80 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_00000000036ad780;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395a1c0 .functor NAND 1, L_0000000003959900, L_0000000003959900, C4<1>, C4<1>;
+L_0000000003959890 .functor BUF 1, L_000000000395a1c0, C4<0>, C4<0>, C4<0>;
+v00000000036c6010_0 .net8 "A", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+v00000000036c4850_0 .net8 "B", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d7ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c60b0_0 .net8 "VGND", 0 0, L_00000000038d7ac0; 1 drivers, strength-aware
+L_00000000038d8000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c39f0_0 .net8 "VNB", 0 0, L_00000000038d8000; 1 drivers, strength-aware
+L_00000000038d7900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3b30_0 .net8 "VPB", 0 0, L_00000000038d7900; 1 drivers, strength-aware
+L_00000000038d8bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c3db0_0 .net8 "VPWR", 0 0, L_00000000038d8bd0; 1 drivers, strength-aware
+v00000000036c4df0_0 .net "Y", 0 0, L_0000000003959890; alias, 1 drivers
+v00000000036c3f90_0 .net "nand0_out_Y", 0 0, L_000000000395a1c0; 1 drivers
+S_00000000036a9a00 .scope module, "nand21" "sky130_fd_sc_hd__nand2_2" 4 29432, 4 8552 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000036c7f50_0 .net8 "A", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+v00000000036c7370_0 .net8 "B", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d7c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c7ff0_0 .net8 "VGND", 0 0, L_00000000038d7c10; 1 drivers, strength-aware
+L_00000000038d7b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c6dd0_0 .net8 "VNB", 0 0, L_00000000038d7b30; 1 drivers, strength-aware
+L_00000000038d8a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6790_0 .net8 "VPB", 0 0, L_00000000038d8a80; 1 drivers, strength-aware
+L_00000000038d8cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c7af0_0 .net8 "VPWR", 0 0, L_00000000038d8cb0; 1 drivers, strength-aware
+v00000000036c7230_0 .net "Y", 0 0, L_0000000003959cf0; alias, 1 drivers
+S_00000000036acb80 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8568, 4 8441 1, S_00000000036a9a00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003959c10 .functor NAND 1, L_0000000003959900, L_0000000003959900, C4<1>, C4<1>;
+L_0000000003959cf0 .functor BUF 1, L_0000000003959c10, C4<0>, C4<0>, C4<0>;
+v00000000036c8590_0 .net8 "A", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+v00000000036c6d30_0 .net8 "B", 0 0, L_0000000003959900; alias, 1 drivers, strength-aware
+L_00000000038d7e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c70f0_0 .net8 "VGND", 0 0, L_00000000038d7e40; 1 drivers, strength-aware
+L_00000000038d90a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c65b0_0 .net8 "VNB", 0 0, L_00000000038d90a0; 1 drivers, strength-aware
+L_00000000038d79e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c7190_0 .net8 "VPB", 0 0, L_00000000038d79e0; 1 drivers, strength-aware
+L_00000000038d91f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c7eb0_0 .net8 "VPWR", 0 0, L_00000000038d91f0; 1 drivers, strength-aware
+v00000000036c79b0_0 .net "Y", 0 0, L_0000000003959cf0; alias, 1 drivers
+v00000000036c7050_0 .net "nand0_out_Y", 0 0, L_0000000003959c10; 1 drivers
+S_00000000036acd00 .scope module, "nor20" "sky130_fd_sc_hd__nor2_2" 4 29429, 4 30285 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000036c81d0_0 .net "A", 0 0, L_0000000003959cf0; alias, 1 drivers
+v00000000036c7b90_0 .net "B", 0 0, L_0000000003959cf0; alias, 1 drivers
+L_00000000038d70b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c8810_0 .net8 "VGND", 0 0, L_00000000038d70b0; 1 drivers, strength-aware
+L_00000000038d5e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c8770_0 .net8 "VNB", 0 0, L_00000000038d5e50; 1 drivers, strength-aware
+L_00000000038d72e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6b50_0 .net8 "VPB", 0 0, L_00000000038d72e0; 1 drivers, strength-aware
+L_00000000038d5ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c75f0_0 .net8 "VPWR", 0 0, L_00000000038d5ec0; 1 drivers, strength-aware
+v00000000036c68d0_0 .net "Y", 0 0, L_0000000003959660; alias, 1 drivers
+S_00000000036ace80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000036acd00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395a700 .functor NOR 1, L_0000000003959cf0, L_0000000003959cf0, C4<0>, C4<0>;
+L_0000000003959660 .functor BUF 1, L_000000000395a700, C4<0>, C4<0>, C4<0>;
+v00000000036c7a50_0 .net "A", 0 0, L_0000000003959cf0; alias, 1 drivers
+v00000000036c7e10_0 .net "B", 0 0, L_0000000003959cf0; alias, 1 drivers
+L_00000000038d7350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c8450_0 .net8 "VGND", 0 0, L_00000000038d7350; 1 drivers, strength-aware
+L_00000000038d73c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c6e70_0 .net8 "VNB", 0 0, L_00000000038d73c0; 1 drivers, strength-aware
+L_00000000038d7430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c61f0_0 .net8 "VPB", 0 0, L_00000000038d7430; 1 drivers, strength-aware
+L_00000000038d74a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c8630_0 .net8 "VPWR", 0 0, L_00000000038d74a0; 1 drivers, strength-aware
+v00000000036c6650_0 .net "Y", 0 0, L_0000000003959660; alias, 1 drivers
+v00000000036c7410_0 .net "nor0_out_Y", 0 0, L_000000000395a700; 1 drivers
+S_00000000036ad300 .scope module, "nor21" "sky130_fd_sc_hd__nor2_2" 4 29430, 4 30285 1, S_00000000026a7f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+v00000000036c8130_0 .net "A", 0 0, L_0000000003959890; alias, 1 drivers
+v00000000036c6a10_0 .net "B", 0 0, L_0000000003959890; alias, 1 drivers
+L_00000000038d7510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c72d0_0 .net8 "VGND", 0 0, L_00000000038d7510; 1 drivers, strength-aware
+L_00000000038d60f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c7c30_0 .net8 "VNB", 0 0, L_00000000038d60f0; 1 drivers, strength-aware
+L_00000000038d6160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c74b0_0 .net8 "VPB", 0 0, L_00000000038d6160; 1 drivers, strength-aware
+L_00000000038d8310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6ab0_0 .net8 "VPWR", 0 0, L_00000000038d8310; 1 drivers, strength-aware
+v00000000036c7690_0 .net "Y", 0 0, L_0000000003959dd0; alias, 1 drivers
+S_00000000036ad000 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30301, 4 30688 1, S_00000000036ad300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395a070 .functor NOR 1, L_0000000003959890, L_0000000003959890, C4<0>, C4<0>;
+L_0000000003959dd0 .functor BUF 1, L_000000000395a070, C4<0>, C4<0>, C4<0>;
+v00000000036c8270_0 .net "A", 0 0, L_0000000003959890; alias, 1 drivers
+v00000000036c7550_0 .net "B", 0 0, L_0000000003959890; alias, 1 drivers
+L_00000000038d9030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c86d0_0 .net8 "VGND", 0 0, L_00000000038d9030; 1 drivers, strength-aware
+L_00000000038d8d20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c66f0_0 .net8 "VNB", 0 0, L_00000000038d8d20; 1 drivers, strength-aware
+L_00000000038d8380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6830_0 .net8 "VPB", 0 0, L_00000000038d8380; 1 drivers, strength-aware
+L_00000000038d7f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c6970_0 .net8 "VPWR", 0 0, L_00000000038d7f90; 1 drivers, strength-aware
+v00000000036c6150_0 .net "Y", 0 0, L_0000000003959dd0; alias, 1 drivers
+v00000000036c6330_0 .net "nor0_out_Y", 0 0, L_000000000395a070; 1 drivers
+S_00000000026a7180 .scope module, "sky130_fd_sc_hd__maj3_1" "sky130_fd_sc_hd__maj3_1" 4 84985;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003657398 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ca7f0_0 .net "A", 0 0, o0000000003657398; 0 drivers
+o00000000036573c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c9530_0 .net "B", 0 0, o00000000036573c8; 0 drivers
+o00000000036573f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c90d0_0 .net "C", 0 0, o00000000036573f8; 0 drivers
+L_00000000038d83f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9350_0 .net8 "VGND", 0 0, L_00000000038d83f0; 1 drivers, strength-aware
+L_00000000038d80e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036caa70_0 .net8 "VNB", 0 0, L_00000000038d80e0; 1 drivers, strength-aware
+L_00000000038d8150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c89f0_0 .net8 "VPB", 0 0, L_00000000038d8150; 1 drivers, strength-aware
+L_00000000038d8e00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ca2f0_0 .net8 "VPWR", 0 0, L_00000000038d8e00; 1 drivers, strength-aware
+v00000000036cacf0_0 .net "X", 0 0, L_0000000003958fd0; 1 drivers
+S_00000000036ad480 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 85003, 4 84751 1, S_00000000026a7180;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_0000000003958ef0 .functor OR 1, o00000000036573c8, o0000000003657398, C4<0>, C4<0>;
+L_0000000003958f60 .functor AND 1, L_0000000003958ef0, o00000000036573f8, C4<1>, C4<1>;
+L_0000000003959350 .functor AND 1, o0000000003657398, o00000000036573c8, C4<1>, C4<1>;
+L_000000000395a5b0 .functor OR 1, L_0000000003959350, L_0000000003958f60, C4<0>, C4<0>;
+L_0000000003958fd0 .functor BUF 1, L_000000000395a5b0, C4<0>, C4<0>, C4<0>;
+v00000000036c8310_0 .net "A", 0 0, o0000000003657398; alias, 0 drivers
+v00000000036c63d0_0 .net "B", 0 0, o00000000036573c8; alias, 0 drivers
+v00000000036c83b0_0 .net "C", 0 0, o00000000036573f8; alias, 0 drivers
+L_00000000038d8b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c6470_0 .net8 "VGND", 0 0, L_00000000038d8b60; 1 drivers, strength-aware
+L_00000000038d9260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c88b0_0 .net8 "VNB", 0 0, L_00000000038d9260; 1 drivers, strength-aware
+L_00000000038d8700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c84f0_0 .net8 "VPB", 0 0, L_00000000038d8700; 1 drivers, strength-aware
+L_00000000038d81c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ca250_0 .net8 "VPWR", 0 0, L_00000000038d81c0; 1 drivers, strength-aware
+v00000000036c9df0_0 .net "X", 0 0, L_0000000003958fd0; alias, 1 drivers
+v00000000036c9210_0 .net "and0_out", 0 0, L_0000000003958f60; 1 drivers
+v00000000036cac50_0 .net "and1_out", 0 0, L_0000000003959350; 1 drivers
+v00000000036ca570_0 .net "or0_out", 0 0, L_0000000003958ef0; 1 drivers
+v00000000036ca750_0 .net "or1_out_X", 0 0, L_000000000395a5b0; 1 drivers
+S_00000000026a7900 .scope module, "sky130_fd_sc_hd__maj3_2" "sky130_fd_sc_hd__maj3_2" 4 85097;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003657818 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c8db0_0 .net "A", 0 0, o0000000003657818; 0 drivers
+o0000000003657848 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c9c10_0 .net "B", 0 0, o0000000003657848; 0 drivers
+o0000000003657878 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cae30_0 .net "C", 0 0, o0000000003657878; 0 drivers
+L_00000000038d7cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9e90_0 .net8 "VGND", 0 0, L_00000000038d7cf0; 1 drivers, strength-aware
+L_00000000038d82a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ca430_0 .net8 "VNB", 0 0, L_00000000038d82a0; 1 drivers, strength-aware
+L_00000000038d8f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c9d50_0 .net8 "VPB", 0 0, L_00000000038d8f50; 1 drivers, strength-aware
+L_00000000038d8460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c9f30_0 .net8 "VPWR", 0 0, L_00000000038d8460; 1 drivers, strength-aware
+v00000000036caed0_0 .net "X", 0 0, L_000000000395a2a0; 1 drivers
+S_00000000036adf00 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 85115, 4 84751 1, S_00000000026a7900;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_00000000039590b0 .functor OR 1, o0000000003657848, o0000000003657818, C4<0>, C4<0>;
+L_0000000003959d60 .functor AND 1, L_00000000039590b0, o0000000003657878, C4<1>, C4<1>;
+L_0000000003959e40 .functor AND 1, o0000000003657818, o0000000003657848, C4<1>, C4<1>;
+L_000000000395a230 .functor OR 1, L_0000000003959e40, L_0000000003959d60, C4<0>, C4<0>;
+L_000000000395a2a0 .functor BUF 1, L_000000000395a230, C4<0>, C4<0>, C4<0>;
+v00000000036cad90_0 .net "A", 0 0, o0000000003657818; alias, 0 drivers
+v00000000036c9670_0 .net "B", 0 0, o0000000003657848; alias, 0 drivers
+v00000000036c8c70_0 .net "C", 0 0, o0000000003657878; alias, 0 drivers
+L_00000000038d84d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c92b0_0 .net8 "VGND", 0 0, L_00000000038d84d0; 1 drivers, strength-aware
+L_00000000038d8230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9b70_0 .net8 "VNB", 0 0, L_00000000038d8230; 1 drivers, strength-aware
+L_00000000038d8c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c8d10_0 .net8 "VPB", 0 0, L_00000000038d8c40; 1 drivers, strength-aware
+L_00000000038d7c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ca390_0 .net8 "VPWR", 0 0, L_00000000038d7c80; 1 drivers, strength-aware
+v00000000036ca9d0_0 .net "X", 0 0, L_000000000395a2a0; alias, 1 drivers
+v00000000036c8a90_0 .net "and0_out", 0 0, L_0000000003959d60; 1 drivers
+v00000000036cb010_0 .net "and1_out", 0 0, L_0000000003959e40; 1 drivers
+v00000000036c97b0_0 .net "or0_out", 0 0, L_00000000039590b0; 1 drivers
+v00000000036c9170_0 .net "or1_out_X", 0 0, L_000000000395a230; 1 drivers
+S_00000000026a8080 .scope module, "sky130_fd_sc_hd__maj3_4" "sky130_fd_sc_hd__maj3_4" 4 84873;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003657c98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ca890_0 .net "A", 0 0, o0000000003657c98; 0 drivers
+o0000000003657cc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ca1b0_0 .net "B", 0 0, o0000000003657cc8; 0 drivers
+o0000000003657cf8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c8bd0_0 .net "C", 0 0, o0000000003657cf8; 0 drivers
+L_00000000038d7d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c8e50_0 .net8 "VGND", 0 0, L_00000000038d7d60; 1 drivers, strength-aware
+L_00000000038d7ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ca610_0 .net8 "VNB", 0 0, L_00000000038d7ba0; 1 drivers, strength-aware
+L_00000000038d8ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ca930_0 .net8 "VPB", 0 0, L_00000000038d8ee0; 1 drivers, strength-aware
+L_00000000038d7dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c9710_0 .net8 "VPWR", 0 0, L_00000000038d7dd0; 1 drivers, strength-aware
+v00000000036c9990_0 .net "X", 0 0, L_000000000395a770; 1 drivers
+S_00000000036a8680 .scope module, "base" "sky130_fd_sc_hd__maj3" 4 84891, 4 84751 1, S_00000000026a8080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_0000000003959120 .functor OR 1, o0000000003657cc8, o0000000003657c98, C4<0>, C4<0>;
+L_000000000395a310 .functor AND 1, L_0000000003959120, o0000000003657cf8, C4<1>, C4<1>;
+L_000000000395a380 .functor AND 1, o0000000003657c98, o0000000003657cc8, C4<1>, C4<1>;
+L_000000000395a690 .functor OR 1, L_000000000395a380, L_000000000395a310, C4<0>, C4<0>;
+L_000000000395a770 .functor BUF 1, L_000000000395a690, C4<0>, C4<0>, C4<0>;
+v00000000036c8b30_0 .net "A", 0 0, o0000000003657c98; alias, 0 drivers
+v00000000036c9850_0 .net "B", 0 0, o0000000003657cc8; alias, 0 drivers
+v00000000036ca6b0_0 .net "C", 0 0, o0000000003657cf8; alias, 0 drivers
+L_00000000038d7a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9030_0 .net8 "VGND", 0 0, L_00000000038d7a50; 1 drivers, strength-aware
+L_00000000038d8540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9a30_0 .net8 "VNB", 0 0, L_00000000038d8540; 1 drivers, strength-aware
+L_00000000038d85b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ca4d0_0 .net8 "VPB", 0 0, L_00000000038d85b0; 1 drivers, strength-aware
+L_00000000038d7eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c98f0_0 .net8 "VPWR", 0 0, L_00000000038d7eb0; 1 drivers, strength-aware
+v00000000036c9fd0_0 .net "X", 0 0, L_000000000395a770; alias, 1 drivers
+v00000000036ca070_0 .net "and0_out", 0 0, L_000000000395a310; 1 drivers
+v00000000036caf70_0 .net "and1_out", 0 0, L_000000000395a380; 1 drivers
+v00000000036c9cb0_0 .net "or0_out", 0 0, L_0000000003959120; 1 drivers
+v00000000036ca110_0 .net "or1_out_X", 0 0, L_000000000395a690; 1 drivers
+S_00000000026a8500 .scope module, "sky130_fd_sc_hd__mux2_2" "sky130_fd_sc_hd__mux2_2" 4 29952;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o0000000003658118 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036c8f90_0 .net "A0", 0 0, o0000000003658118; 0 drivers
+o0000000003658148 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ccd70_0 .net "A1", 0 0, o0000000003658148; 0 drivers
+o0000000003658178 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cb6f0_0 .net "S", 0 0, o0000000003658178; 0 drivers
+L_00000000038d7f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cc190_0 .net8 "VGND", 0 0, L_00000000038d7f20; 1 drivers, strength-aware
+L_00000000038d8fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cd130_0 .net8 "VNB", 0 0, L_00000000038d8fc0; 1 drivers, strength-aware
+L_00000000038d8770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cc050_0 .net8 "VPB", 0 0, L_00000000038d8770; 1 drivers, strength-aware
+L_00000000038d87e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cb790_0 .net8 "VPWR", 0 0, L_00000000038d87e0; 1 drivers, strength-aware
+v00000000036cc730_0 .net "X", 0 0, L_000000000395a8c0; 1 drivers
+S_00000000036a8380 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 29970, 4 29836 1, S_00000000026a8500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_000000000395a3f0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003658118, o0000000003658148, o0000000003658178;
+L_000000000395a8c0 .functor BUF 1, L_000000000395a3f0, C4<0>, C4<0>, C4<0>;
+v00000000036c93f0_0 .net "A0", 0 0, o0000000003658118; alias, 0 drivers
+v00000000036cb0b0_0 .net "A1", 0 0, o0000000003658148; alias, 0 drivers
+v00000000036cab10_0 .net "S", 0 0, o0000000003658178; alias, 0 drivers
+L_00000000038d8850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c9490_0 .net8 "VGND", 0 0, L_00000000038d8850; 1 drivers, strength-aware
+L_00000000038d8930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036c8950_0 .net8 "VNB", 0 0, L_00000000038d8930; 1 drivers, strength-aware
+L_00000000038d9110 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c9ad0_0 .net8 "VPB", 0 0, L_00000000038d9110; 1 drivers, strength-aware
+L_00000000038d8a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036c8ef0_0 .net8 "VPWR", 0 0, L_00000000038d8a10; 1 drivers, strength-aware
+v00000000036cabb0_0 .net "X", 0 0, L_000000000395a8c0; alias, 1 drivers
+v00000000036c95d0_0 .net "mux_2to10_out_X", 0 0, L_000000000395a3f0; 1 drivers
+S_00000000026a8c80 .scope module, "sky130_fd_sc_hd__mux2_4" "sky130_fd_sc_hd__mux2_4" 4 30176;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o0000000003658508 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cb1f0_0 .net "A0", 0 0, o0000000003658508; 0 drivers
+o0000000003658538 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cc2d0_0 .net "A1", 0 0, o0000000003658538; 0 drivers
+o0000000003658568 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd630_0 .net "S", 0 0, o0000000003658568; 0 drivers
+L_00000000038d9420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cc4b0_0 .net8 "VGND", 0 0, L_00000000038d9420; 1 drivers, strength-aware
+L_00000000038d93b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cccd0_0 .net8 "VNB", 0 0, L_00000000038d93b0; 1 drivers, strength-aware
+L_00000000038d9490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ccc30_0 .net8 "VPB", 0 0, L_00000000038d9490; 1 drivers, strength-aware
+L_00000000038d9ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cc370_0 .net8 "VPWR", 0 0, L_00000000038d9ea0; 1 drivers, strength-aware
+v00000000036cce10_0 .net "X", 0 0, L_0000000003959270; 1 drivers
+S_00000000036a8500 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 30194, 4 29836 1, S_00000000026a8c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_0000000003959190 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003658508, o0000000003658538, o0000000003658568;
+L_0000000003959270 .functor BUF 1, L_0000000003959190, C4<0>, C4<0>, C4<0>;
+v00000000036cc230_0 .net "A0", 0 0, o0000000003658508; alias, 0 drivers
+v00000000036cbbf0_0 .net "A1", 0 0, o0000000003658538; alias, 0 drivers
+v00000000036cc910_0 .net "S", 0 0, o0000000003658568; alias, 0 drivers
+L_00000000038dab50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cb830_0 .net8 "VGND", 0 0, L_00000000038dab50; 1 drivers, strength-aware
+L_00000000038d9ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cc9b0_0 .net8 "VNB", 0 0, L_00000000038d9ce0; 1 drivers, strength-aware
+L_00000000038dad10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cb150_0 .net8 "VPB", 0 0, L_00000000038dad10; 1 drivers, strength-aware
+L_00000000038da3e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cd310_0 .net8 "VPWR", 0 0, L_00000000038da3e0; 1 drivers, strength-aware
+v00000000036cd770_0 .net "X", 0 0, L_0000000003959270; alias, 1 drivers
+v00000000036cb510_0 .net "mux_2to10_out_X", 0 0, L_0000000003959190; 1 drivers
+S_00000000026a8980 .scope module, "sky130_fd_sc_hd__mux2_8" "sky130_fd_sc_hd__mux2_8" 4 30064;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o00000000036588f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd590_0 .net "A0", 0 0, o00000000036588f8; 0 drivers
+o0000000003658928 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd3b0_0 .net "A1", 0 0, o0000000003658928; 0 drivers
+o0000000003658958 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd090_0 .net "S", 0 0, o0000000003658958; 0 drivers
+L_00000000038da760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cc410_0 .net8 "VGND", 0 0, L_00000000038da760; 1 drivers, strength-aware
+L_00000000038da450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ccff0_0 .net8 "VNB", 0 0, L_00000000038da450; 1 drivers, strength-aware
+L_00000000038d9c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ccaf0_0 .net8 "VPB", 0 0, L_00000000038d9c00; 1 drivers, strength-aware
+L_00000000038da5a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cc0f0_0 .net8 "VPWR", 0 0, L_00000000038da5a0; 1 drivers, strength-aware
+v00000000036cc550_0 .net "X", 0 0, L_000000000395a460; 1 drivers
+S_00000000036a8f80 .scope module, "base" "sky130_fd_sc_hd__mux2" 4 30082, 4 29836 1, S_00000000026a8980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_00000000039592e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000036588f8, o0000000003658928, o0000000003658958;
+L_000000000395a460 .functor BUF 1, L_00000000039592e0, C4<0>, C4<0>, C4<0>;
+v00000000036cceb0_0 .net "A0", 0 0, o00000000036588f8; alias, 0 drivers
+v00000000036cc7d0_0 .net "A1", 0 0, o0000000003658928; alias, 0 drivers
+v00000000036cb8d0_0 .net "S", 0 0, o0000000003658958; alias, 0 drivers
+L_00000000038daa00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cbab0_0 .net8 "VGND", 0 0, L_00000000038daa00; 1 drivers, strength-aware
+L_00000000038d9570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cca50_0 .net8 "VNB", 0 0, L_00000000038d9570; 1 drivers, strength-aware
+L_00000000038d96c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cbc90_0 .net8 "VPB", 0 0, L_00000000038d96c0; 1 drivers, strength-aware
+L_00000000038dafb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cb5b0_0 .net8 "VPWR", 0 0, L_00000000038dafb0; 1 drivers, strength-aware
+v00000000036cbd30_0 .net "X", 0 0, L_000000000395a460; alias, 1 drivers
+v00000000036ccf50_0 .net "mux_2to10_out_X", 0 0, L_00000000039592e0; 1 drivers
+S_00000000026a9100 .scope module, "sky130_fd_sc_hd__mux2i_1" "sky130_fd_sc_hd__mux2i_1" 4 20050;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o0000000003658ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cc5f0_0 .net "A0", 0 0, o0000000003658ce8; 0 drivers
+o0000000003658d18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ccb90_0 .net "A1", 0 0, o0000000003658d18; 0 drivers
+o0000000003658d48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd270_0 .net "S", 0 0, o0000000003658d48; 0 drivers
+L_00000000038da7d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cb650_0 .net8 "VGND", 0 0, L_00000000038da7d0; 1 drivers, strength-aware
+L_00000000038daa70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cc690_0 .net8 "VNB", 0 0, L_00000000038daa70; 1 drivers, strength-aware
+L_00000000038d9880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cd4f0_0 .net8 "VPB", 0 0, L_00000000038d9880; 1 drivers, strength-aware
+L_00000000038da4c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cd810_0 .net8 "VPWR", 0 0, L_00000000038da4c0; 1 drivers, strength-aware
+v00000000036cc870_0 .net "Y", 0 0, L_000000000395a850; 1 drivers
+S_00000000036a8800 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 20068, 4 19934 1, S_00000000026a9100;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+UDP_sky130_fd_sc_hd__udp_mux_2to1_N .udp/comb "sky130_fd_sc_hd__udp_mux_2to1_N", 3
+ ,"0?01"
+ ,"1?00"
+ ,"?011"
+ ,"?110"
+ ,"00?1"
+ ,"11?0";
+L_000000000395a7e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o0000000003658ce8, o0000000003658d18, o0000000003658d48;
+L_000000000395a850 .functor BUF 1, L_000000000395a7e0, C4<0>, C4<0>, C4<0>;
+v00000000036cbdd0_0 .net "A0", 0 0, o0000000003658ce8; alias, 0 drivers
+v00000000036cb970_0 .net "A1", 0 0, o0000000003658d18; alias, 0 drivers
+v00000000036cbb50_0 .net "S", 0 0, o0000000003658d48; alias, 0 drivers
+L_00000000038d9d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cd6d0_0 .net8 "VGND", 0 0, L_00000000038d9d50; 1 drivers, strength-aware
+L_00000000038d9f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cb290_0 .net8 "VNB", 0 0, L_00000000038d9f10; 1 drivers, strength-aware
+L_00000000038d9730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cbe70_0 .net8 "VPB", 0 0, L_00000000038d9730; 1 drivers, strength-aware
+L_00000000038da840 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cbfb0_0 .net8 "VPWR", 0 0, L_00000000038da840; 1 drivers, strength-aware
+v00000000036cd1d0_0 .net "Y", 0 0, L_000000000395a850; alias, 1 drivers
+v00000000036cd450_0 .net "mux_2to1_n0_out_Y", 0 0, L_000000000395a7e0; 1 drivers
+S_00000000026a8e00 .scope module, "sky130_fd_sc_hd__mux2i_2" "sky130_fd_sc_hd__mux2i_2" 4 19512;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o00000000036590d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cdbd0_0 .net "A0", 0 0, o00000000036590d8; 0 drivers
+o0000000003659108 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd950_0 .net "A1", 0 0, o0000000003659108; 0 drivers
+o0000000003659138 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cfcf0_0 .net "S", 0 0, o0000000003659138; 0 drivers
+L_00000000038dabc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ce990_0 .net8 "VGND", 0 0, L_00000000038dabc0; 1 drivers, strength-aware
+L_00000000038db020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cf6b0_0 .net8 "VNB", 0 0, L_00000000038db020; 1 drivers, strength-aware
+L_00000000038da6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ce030_0 .net8 "VPB", 0 0, L_00000000038da6f0; 1 drivers, strength-aware
+L_00000000038d9f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cea30_0 .net8 "VPWR", 0 0, L_00000000038d9f80; 1 drivers, strength-aware
+v00000000036ce3f0_0 .net "Y", 0 0, L_000000000395b2d0; 1 drivers
+S_00000000036a8980 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 19530, 4 19934 1, S_00000000026a8e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_000000000395c4c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o00000000036590d8, o0000000003659108, o0000000003659138;
+L_000000000395b2d0 .functor BUF 1, L_000000000395c4c0, C4<0>, C4<0>, C4<0>;
+v00000000036cd8b0_0 .net "A0", 0 0, o00000000036590d8; alias, 0 drivers
+v00000000036cb470_0 .net "A1", 0 0, o0000000003659108; alias, 0 drivers
+v00000000036cb330_0 .net "S", 0 0, o0000000003659138; alias, 0 drivers
+L_00000000038da610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cb3d0_0 .net8 "VGND", 0 0, L_00000000038da610; 1 drivers, strength-aware
+L_00000000038da680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cba10_0 .net8 "VNB", 0 0, L_00000000038da680; 1 drivers, strength-aware
+L_00000000038da1b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cbf10_0 .net8 "VPB", 0 0, L_00000000038da1b0; 1 drivers, strength-aware
+L_00000000038d9b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cf9d0_0 .net8 "VPWR", 0 0, L_00000000038d9b90; 1 drivers, strength-aware
+v00000000036ce2b0_0 .net "Y", 0 0, L_000000000395b2d0; alias, 1 drivers
+v00000000036cee90_0 .net "mux_2to1_n0_out_Y", 0 0, L_000000000395c4c0; 1 drivers
+S_00000000026a5b00 .scope module, "sky130_fd_sc_hd__mux2i_4" "sky130_fd_sc_hd__mux2i_4" 4 19624;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+o00000000036594c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cf7f0_0 .net "A0", 0 0, o00000000036594c8; 0 drivers
+o00000000036594f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ce170_0 .net "A1", 0 0, o00000000036594f8; 0 drivers
+o0000000003659528 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cd9f0_0 .net "S", 0 0, o0000000003659528; 0 drivers
+L_00000000038d99d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cfbb0_0 .net8 "VGND", 0 0, L_00000000038d99d0; 1 drivers, strength-aware
+L_00000000038da8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ce210_0 .net8 "VNB", 0 0, L_00000000038da8b0; 1 drivers, strength-aware
+L_00000000038dad80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cff70_0 .net8 "VPB", 0 0, L_00000000038dad80; 1 drivers, strength-aware
+L_00000000038da300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cef30_0 .net8 "VPWR", 0 0, L_00000000038da300; 1 drivers, strength-aware
+v00000000036cf430_0 .net "Y", 0 0, L_000000000395b030; 1 drivers
+S_00000000036a9100 .scope module, "base" "sky130_fd_sc_hd__mux2i" 4 19642, 4 19934 1, S_00000000026a5b00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "S"
+L_000000000395bb90 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1_N, o00000000036594c8, o00000000036594f8, o0000000003659528;
+L_000000000395b030 .functor BUF 1, L_000000000395bb90, C4<0>, C4<0>, C4<0>;
+v00000000036cecb0_0 .net "A0", 0 0, o00000000036594c8; alias, 0 drivers
+v00000000036cdb30_0 .net "A1", 0 0, o00000000036594f8; alias, 0 drivers
+v00000000036d0010_0 .net "S", 0 0, o0000000003659528; alias, 0 drivers
+L_00000000038d98f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cf750_0 .net8 "VGND", 0 0, L_00000000038d98f0; 1 drivers, strength-aware
+L_00000000038da530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cdd10_0 .net8 "VNB", 0 0, L_00000000038da530; 1 drivers, strength-aware
+L_00000000038da220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cf390_0 .net8 "VPB", 0 0, L_00000000038da220; 1 drivers, strength-aware
+L_00000000038d97a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ced50_0 .net8 "VPWR", 0 0, L_00000000038d97a0; 1 drivers, strength-aware
+v00000000036cddb0_0 .net "Y", 0 0, L_000000000395b030; alias, 1 drivers
+v00000000036cf4d0_0 .net "mux_2to1_n0_out_Y", 0 0, L_000000000395bb90; 1 drivers
+S_00000000026a5500 .scope module, "sky130_fd_sc_hd__mux4_2" "sky130_fd_sc_hd__mux4_2" 4 9268;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+o00000000036598b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ce7b0_0 .net "A0", 0 0, o00000000036598b8; 0 drivers
+o00000000036598e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cf890_0 .net "A1", 0 0, o00000000036598e8; 0 drivers
+o0000000003659918 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ce0d0_0 .net "A2", 0 0, o0000000003659918; 0 drivers
+o0000000003659948 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ce850_0 .net "A3", 0 0, o0000000003659948; 0 drivers
+o0000000003659978 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cf250_0 .net "S0", 0 0, o0000000003659978; 0 drivers
+o00000000036599a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d00b0_0 .net "S1", 0 0, o00000000036599a8; 0 drivers
+L_00000000038d9960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cdf90_0 .net8 "VGND", 0 0, L_00000000038d9960; 1 drivers, strength-aware
+L_00000000038db090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cec10_0 .net8 "VNB", 0 0, L_00000000038db090; 1 drivers, strength-aware
+L_00000000038d9500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cda90_0 .net8 "VPB", 0 0, L_00000000038d9500; 1 drivers, strength-aware
+L_00000000038d9dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ce350_0 .net8 "VPWR", 0 0, L_00000000038d9dc0; 1 drivers, strength-aware
+v00000000036cdc70_0 .net "X", 0 0, L_000000000395ae00; 1 drivers
+S_00000000036a9280 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9292, 4 8877 1, S_00000000026a5500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+L_000000000395bce0 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, o00000000036598b8, o00000000036598e8, o0000000003659918, o0000000003659948, o0000000003659978, o00000000036599a8;
+L_000000000395ae00 .functor BUF 1, L_000000000395bce0, C4<0>, C4<0>, C4<0>;
+v00000000036cead0_0 .net "A0", 0 0, o00000000036598b8; alias, 0 drivers
+v00000000036ce490_0 .net "A1", 0 0, o00000000036598e8; alias, 0 drivers
+v00000000036ceb70_0 .net "A2", 0 0, o0000000003659918; alias, 0 drivers
+v00000000036cfa70_0 .net "A3", 0 0, o0000000003659948; alias, 0 drivers
+v00000000036cf110_0 .net "S0", 0 0, o0000000003659978; alias, 0 drivers
+v00000000036cf610_0 .net "S1", 0 0, o00000000036599a8; alias, 0 drivers
+L_00000000038dac30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cfd90_0 .net8 "VGND", 0 0, L_00000000038dac30; 1 drivers, strength-aware
+L_00000000038da920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cedf0_0 .net8 "VNB", 0 0, L_00000000038da920; 1 drivers, strength-aware
+L_00000000038d95e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cefd0_0 .net8 "VPB", 0 0, L_00000000038d95e0; 1 drivers, strength-aware
+L_00000000038d9e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ce670_0 .net8 "VPWR", 0 0, L_00000000038d9e30; 1 drivers, strength-aware
+v00000000036cde50_0 .net "X", 0 0, L_000000000395ae00; alias, 1 drivers
+v00000000036cdef0_0 .net "mux_4to20_out_X", 0 0, L_000000000395bce0; 1 drivers
+S_00000000026a5380 .scope module, "sky130_fd_sc_hd__mux4_4" "sky130_fd_sc_hd__mux4_4" 4 9138;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+o0000000003659e58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036cfed0_0 .net "A0", 0 0, o0000000003659e58; 0 drivers
+o0000000003659e88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d1230_0 .net "A1", 0 0, o0000000003659e88; 0 drivers
+o0000000003659eb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d0c90_0 .net "A2", 0 0, o0000000003659eb8; 0 drivers
+o0000000003659ee8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d1a50_0 .net "A3", 0 0, o0000000003659ee8; 0 drivers
+o0000000003659f18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d1c30_0 .net "S0", 0 0, o0000000003659f18; 0 drivers
+o0000000003659f48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d0330_0 .net "S1", 0 0, o0000000003659f48; 0 drivers
+L_00000000038da990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d14b0_0 .net8 "VGND", 0 0, L_00000000038da990; 1 drivers, strength-aware
+L_00000000038d9810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d06f0_0 .net8 "VNB", 0 0, L_00000000038d9810; 1 drivers, strength-aware
+L_00000000038da290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0f10_0 .net8 "VPB", 0 0, L_00000000038da290; 1 drivers, strength-aware
+L_00000000038d9c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2130_0 .net8 "VPWR", 0 0, L_00000000038d9c70; 1 drivers, strength-aware
+v00000000036d15f0_0 .net "X", 0 0, L_000000000395ad20; 1 drivers
+S_00000000036a9400 .scope module, "base" "sky130_fd_sc_hd__mux4" 4 9162, 4 8877 1, S_00000000026a5380;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A0"
+ .port_info 2 /INPUT 1 "A1"
+ .port_info 3 /INPUT 1 "A2"
+ .port_info 4 /INPUT 1 "A3"
+ .port_info 5 /INPUT 1 "S0"
+ .port_info 6 /INPUT 1 "S1"
+L_000000000395bc00 .udp UDP_sky130_fd_sc_hd__udp_mux_4to2, o0000000003659e58, o0000000003659e88, o0000000003659eb8, o0000000003659ee8, o0000000003659f18, o0000000003659f48;
+L_000000000395ad20 .functor BUF 1, L_000000000395bc00, C4<0>, C4<0>, C4<0>;
+v00000000036ce530_0 .net "A0", 0 0, o0000000003659e58; alias, 0 drivers
+v00000000036cf070_0 .net "A1", 0 0, o0000000003659e88; alias, 0 drivers
+v00000000036ce5d0_0 .net "A2", 0 0, o0000000003659eb8; alias, 0 drivers
+v00000000036ce8f0_0 .net "A3", 0 0, o0000000003659ee8; alias, 0 drivers
+v00000000036cf1b0_0 .net "S0", 0 0, o0000000003659f18; alias, 0 drivers
+v00000000036ce710_0 .net "S1", 0 0, o0000000003659f48; alias, 0 drivers
+L_00000000038daca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cf2f0_0 .net8 "VGND", 0 0, L_00000000038daca0; 1 drivers, strength-aware
+L_00000000038d9ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036cfe30_0 .net8 "VNB", 0 0, L_00000000038d9ab0; 1 drivers, strength-aware
+L_00000000038da370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cf570_0 .net8 "VPB", 0 0, L_00000000038da370; 1 drivers, strength-aware
+L_00000000038d9ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036cf930_0 .net8 "VPWR", 0 0, L_00000000038d9ff0; 1 drivers, strength-aware
+v00000000036cfb10_0 .net "X", 0 0, L_000000000395ad20; alias, 1 drivers
+v00000000036cfc50_0 .net "mux_4to20_out_X", 0 0, L_000000000395bc00; 1 drivers
+S_00000000026a5680 .scope module, "sky130_fd_sc_hd__nand2_1" "sky130_fd_sc_hd__nand2_1" 4 8144;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000365a3f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d1190_0 .net "A", 0 0, o000000000365a3f8; 0 drivers
+o000000000365a428 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d1eb0_0 .net "B", 0 0, o000000000365a428; 0 drivers
+L_00000000038d9650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d01f0_0 .net8 "VGND", 0 0, L_00000000038d9650; 1 drivers, strength-aware
+L_00000000038d9b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d12d0_0 .net8 "VNB", 0 0, L_00000000038d9b20; 1 drivers, strength-aware
+L_00000000038da060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d1b90_0 .net8 "VPB", 0 0, L_00000000038da060; 1 drivers, strength-aware
+L_00000000038da0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0d30_0 .net8 "VPWR", 0 0, L_00000000038da0d0; 1 drivers, strength-aware
+v00000000036d1370_0 .net "Y", 0 0, L_000000000395b810; 1 drivers
+S_00000000036a9580 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8160, 4 8441 1, S_00000000026a5680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395b110 .functor NAND 1, o000000000365a428, o000000000365a3f8, C4<1>, C4<1>;
+L_000000000395b810 .functor BUF 1, L_000000000395b110, C4<0>, C4<0>, C4<0>;
+v00000000036d1ff0_0 .net "A", 0 0, o000000000365a3f8; alias, 0 drivers
+v00000000036d05b0_0 .net "B", 0 0, o000000000365a428; alias, 0 drivers
+L_00000000038daae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d1af0_0 .net8 "VGND", 0 0, L_00000000038daae0; 1 drivers, strength-aware
+L_00000000038dadf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d21d0_0 .net8 "VNB", 0 0, L_00000000038dadf0; 1 drivers, strength-aware
+L_00000000038dae60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0790_0 .net8 "VPB", 0 0, L_00000000038dae60; 1 drivers, strength-aware
+L_00000000038da140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0830_0 .net8 "VPWR", 0 0, L_00000000038da140; 1 drivers, strength-aware
+v00000000036d0150_0 .net "Y", 0 0, L_000000000395b810; alias, 1 drivers
+v00000000036d2310_0 .net "nand0_out_Y", 0 0, L_000000000395b110; 1 drivers
+S_00000000026a5c80 .scope module, "sky130_fd_sc_hd__nand2_4" "sky130_fd_sc_hd__nand2_4" 4 7932;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000365a758 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d0e70_0 .net "A", 0 0, o000000000365a758; 0 drivers
+o000000000365a788 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d0510_0 .net "B", 0 0, o000000000365a788; 0 drivers
+L_00000000038daed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d0ab0_0 .net8 "VGND", 0 0, L_00000000038daed0; 1 drivers, strength-aware
+L_00000000038daf40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d1410_0 .net8 "VNB", 0 0, L_00000000038daf40; 1 drivers, strength-aware
+L_00000000038d9a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0650_0 .net8 "VPB", 0 0, L_00000000038d9a40; 1 drivers, strength-aware
+L_00000000038dbb10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d1d70_0 .net8 "VPWR", 0 0, L_00000000038dbb10; 1 drivers, strength-aware
+v00000000036d17d0_0 .net "Y", 0 0, L_000000000395be30; 1 drivers
+S_00000000036a9700 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 7948, 4 8441 1, S_00000000026a5c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395a9a0 .functor NAND 1, o000000000365a788, o000000000365a758, C4<1>, C4<1>;
+L_000000000395be30 .functor BUF 1, L_000000000395a9a0, C4<0>, C4<0>, C4<0>;
+v00000000036d0b50_0 .net "A", 0 0, o000000000365a758; alias, 0 drivers
+v00000000036d26d0_0 .net "B", 0 0, o000000000365a788; alias, 0 drivers
+L_00000000038db6b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d08d0_0 .net8 "VGND", 0 0, L_00000000038db6b0; 1 drivers, strength-aware
+L_00000000038dc050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d24f0_0 .net8 "VNB", 0 0, L_00000000038dc050; 1 drivers, strength-aware
+L_00000000038db8e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d19b0_0 .net8 "VPB", 0 0, L_00000000038db8e0; 1 drivers, strength-aware
+L_00000000038dc670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2450_0 .net8 "VPWR", 0 0, L_00000000038dc670; 1 drivers, strength-aware
+v00000000036d1910_0 .net "Y", 0 0, L_000000000395be30; alias, 1 drivers
+v00000000036d0470_0 .net "nand0_out_Y", 0 0, L_000000000395a9a0; 1 drivers
+S_00000000026a6b80 .scope module, "sky130_fd_sc_hd__nand2_8" "sky130_fd_sc_hd__nand2_8" 4 8038;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000365aab8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d2270_0 .net "A", 0 0, o000000000365aab8; 0 drivers
+o000000000365aae8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d23b0_0 .net "B", 0 0, o000000000365aae8; 0 drivers
+L_00000000038db5d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d1e10_0 .net8 "VGND", 0 0, L_00000000038db5d0; 1 drivers, strength-aware
+L_00000000038dbd40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d1870_0 .net8 "VNB", 0 0, L_00000000038dbd40; 1 drivers, strength-aware
+L_00000000038dcc20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d1f50_0 .net8 "VPB", 0 0, L_00000000038dcc20; 1 drivers, strength-aware
+L_00000000038dbcd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d0fb0_0 .net8 "VPWR", 0 0, L_00000000038dbcd0; 1 drivers, strength-aware
+v00000000036d0dd0_0 .net "Y", 0 0, L_000000000395c290; 1 drivers
+S_00000000036af700 .scope module, "base" "sky130_fd_sc_hd__nand2" 4 8054, 4 8441 1, S_00000000026a6b80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395b9d0 .functor NAND 1, o000000000365aae8, o000000000365aab8, C4<1>, C4<1>;
+L_000000000395c290 .functor BUF 1, L_000000000395b9d0, C4<0>, C4<0>, C4<0>;
+v00000000036d1690_0 .net "A", 0 0, o000000000365aab8; alias, 0 drivers
+v00000000036d0970_0 .net "B", 0 0, o000000000365aae8; alias, 0 drivers
+L_00000000038db720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d1cd0_0 .net8 "VGND", 0 0, L_00000000038db720; 1 drivers, strength-aware
+L_00000000038db170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d0a10_0 .net8 "VNB", 0 0, L_00000000038db170; 1 drivers, strength-aware
+L_00000000038dba30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2770_0 .net8 "VPB", 0 0, L_00000000038dba30; 1 drivers, strength-aware
+L_00000000038db790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d1550_0 .net8 "VPWR", 0 0, L_00000000038db790; 1 drivers, strength-aware
+v00000000036d1730_0 .net "Y", 0 0, L_000000000395c290; alias, 1 drivers
+v00000000036d0bf0_0 .net "nand0_out_Y", 0 0, L_000000000395b9d0; 1 drivers
+S_00000000026a6d00 .scope module, "sky130_fd_sc_hd__nand2b_1" "sky130_fd_sc_hd__nand2b_1" 4 50222;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o000000000365ae18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d2950_0 .net "A_N", 0 0, o000000000365ae18; 0 drivers
+o000000000365ae48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d3710_0 .net "B", 0 0, o000000000365ae48; 0 drivers
+L_00000000038dcbb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d3e90_0 .net8 "VGND", 0 0, L_00000000038dcbb0; 1 drivers, strength-aware
+L_00000000038dbb80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d2d10_0 .net8 "VNB", 0 0, L_00000000038dbb80; 1 drivers, strength-aware
+L_00000000038db950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d29f0_0 .net8 "VPB", 0 0, L_00000000038db950; 1 drivers, strength-aware
+L_00000000038db800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2db0_0 .net8 "VPWR", 0 0, L_00000000038db800; 1 drivers, strength-aware
+v00000000036d44d0_0 .net "Y", 0 0, L_000000000395b340; 1 drivers
+S_00000000036afa00 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50238, 4 50525 1, S_00000000026a6d00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395c140 .functor NOT 1, o000000000365ae48, C4<0>, C4<0>, C4<0>;
+L_000000000395aa10 .functor OR 1, L_000000000395c140, o000000000365ae18, C4<0>, C4<0>;
+L_000000000395b340 .functor BUF 1, L_000000000395aa10, C4<0>, C4<0>, C4<0>;
+v00000000036d10f0_0 .net "A_N", 0 0, o000000000365ae18; alias, 0 drivers
+v00000000036d2590_0 .net "B", 0 0, o000000000365ae48; alias, 0 drivers
+L_00000000038db870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d2090_0 .net8 "VGND", 0 0, L_00000000038db870; 1 drivers, strength-aware
+L_00000000038db9c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d2630_0 .net8 "VNB", 0 0, L_00000000038db9c0; 1 drivers, strength-aware
+L_00000000038dbaa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d1050_0 .net8 "VPB", 0 0, L_00000000038dbaa0; 1 drivers, strength-aware
+L_00000000038dbdb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2810_0 .net8 "VPWR", 0 0, L_00000000038dbdb0; 1 drivers, strength-aware
+v00000000036d28b0_0 .net "Y", 0 0, L_000000000395b340; alias, 1 drivers
+v00000000036d0290_0 .net "not0_out", 0 0, L_000000000395c140; 1 drivers
+v00000000036d03d0_0 .net "or0_out_Y", 0 0, L_000000000395aa10; 1 drivers
+S_00000000026a6700 .scope module, "sky130_fd_sc_hd__nand2b_2" "sky130_fd_sc_hd__nand2b_2" 4 50010;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o000000000365b1a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d3a30_0 .net "A_N", 0 0, o000000000365b1a8; 0 drivers
+o000000000365b1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d3490_0 .net "B", 0 0, o000000000365b1d8; 0 drivers
+L_00000000038dbe20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d42f0_0 .net8 "VGND", 0 0, L_00000000038dbe20; 1 drivers, strength-aware
+L_00000000038dbe90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4930_0 .net8 "VNB", 0 0, L_00000000038dbe90; 1 drivers, strength-aware
+L_00000000038dbf00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2b30_0 .net8 "VPB", 0 0, L_00000000038dbf00; 1 drivers, strength-aware
+L_00000000038db410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d3f30_0 .net8 "VPWR", 0 0, L_00000000038db410; 1 drivers, strength-aware
+v00000000036d3350_0 .net "Y", 0 0, L_000000000395b650; 1 drivers
+S_00000000036ae800 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50026, 4 50525 1, S_00000000026a6700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395b180 .functor NOT 1, o000000000365b1d8, C4<0>, C4<0>, C4<0>;
+L_000000000395b730 .functor OR 1, L_000000000395b180, o000000000365b1a8, C4<0>, C4<0>;
+L_000000000395b650 .functor BUF 1, L_000000000395b730, C4<0>, C4<0>, C4<0>;
+v00000000036d3170_0 .net "A_N", 0 0, o000000000365b1a8; alias, 0 drivers
+v00000000036d2a90_0 .net "B", 0 0, o000000000365b1d8; alias, 0 drivers
+L_00000000038dcc90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4bb0_0 .net8 "VGND", 0 0, L_00000000038dcc90; 1 drivers, strength-aware
+L_00000000038dbbf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d5010_0 .net8 "VNB", 0 0, L_00000000038dbbf0; 1 drivers, strength-aware
+L_00000000038dc590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4f70_0 .net8 "VPB", 0 0, L_00000000038dc590; 1 drivers, strength-aware
+L_00000000038db330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4250_0 .net8 "VPWR", 0 0, L_00000000038db330; 1 drivers, strength-aware
+v00000000036d3df0_0 .net "Y", 0 0, L_000000000395b650; alias, 1 drivers
+v00000000036d3210_0 .net "not0_out", 0 0, L_000000000395b180; 1 drivers
+v00000000036d4110_0 .net "or0_out_Y", 0 0, L_000000000395b730; 1 drivers
+S_00000000026f8e60 .scope module, "sky130_fd_sc_hd__nand2b_4" "sky130_fd_sc_hd__nand2b_4" 4 50116;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+o000000000365b538 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d3670_0 .net "A_N", 0 0, o000000000365b538; 0 drivers
+o000000000365b568 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d50b0_0 .net "B", 0 0, o000000000365b568; 0 drivers
+L_00000000038db640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d3cb0_0 .net8 "VGND", 0 0, L_00000000038db640; 1 drivers, strength-aware
+L_00000000038dbc60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4570_0 .net8 "VNB", 0 0, L_00000000038dbc60; 1 drivers, strength-aware
+L_00000000038dc980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2bd0_0 .net8 "VPB", 0 0, L_00000000038dc980; 1 drivers, strength-aware
+L_00000000038db3a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d3850_0 .net8 "VPWR", 0 0, L_00000000038db3a0; 1 drivers, strength-aware
+v00000000036d3990_0 .net "Y", 0 0, L_000000000395b260; 1 drivers
+S_00000000036b0000 .scope module, "base" "sky130_fd_sc_hd__nand2b" 4 50132, 4 50525 1, S_00000000026f8e60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395acb0 .functor NOT 1, o000000000365b568, C4<0>, C4<0>, C4<0>;
+L_000000000395bc70 .functor OR 1, L_000000000395acb0, o000000000365b538, C4<0>, C4<0>;
+L_000000000395b260 .functor BUF 1, L_000000000395bc70, C4<0>, C4<0>, C4<0>;
+v00000000036d3fd0_0 .net "A_N", 0 0, o000000000365b538; alias, 0 drivers
+v00000000036d30d0_0 .net "B", 0 0, o000000000365b568; alias, 0 drivers
+L_00000000038dbf70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d32b0_0 .net8 "VGND", 0 0, L_00000000038dbf70; 1 drivers, strength-aware
+L_00000000038db1e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d41b0_0 .net8 "VNB", 0 0, L_00000000038db1e0; 1 drivers, strength-aware
+L_00000000038dbfe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d3530_0 .net8 "VPB", 0 0, L_00000000038dbfe0; 1 drivers, strength-aware
+L_00000000038db100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d2e50_0 .net8 "VPWR", 0 0, L_00000000038db100; 1 drivers, strength-aware
+v00000000036d4390_0 .net "Y", 0 0, L_000000000395b260; alias, 1 drivers
+v00000000036d4430_0 .net "not0_out", 0 0, L_000000000395acb0; 1 drivers
+v00000000036d35d0_0 .net "or0_out_Y", 0 0, L_000000000395bc70; 1 drivers
+S_00000000026fb860 .scope module, "sky130_fd_sc_hd__nand3_1" "sky130_fd_sc_hd__nand3_1" 4 4208;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365b8c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d4c50_0 .net "A", 0 0, o000000000365b8c8; 0 drivers
+o000000000365b8f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d37b0_0 .net "B", 0 0, o000000000365b8f8; 0 drivers
+o000000000365b928 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d2c70_0 .net "C", 0 0, o000000000365b928; 0 drivers
+L_00000000038dc0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d33f0_0 .net8 "VGND", 0 0, L_00000000038dc0c0; 1 drivers, strength-aware
+L_00000000038dc3d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d3b70_0 .net8 "VNB", 0 0, L_00000000038dc3d0; 1 drivers, strength-aware
+L_00000000038dc130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d3030_0 .net8 "VPB", 0 0, L_00000000038dc130; 1 drivers, strength-aware
+L_00000000038dc1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4890_0 .net8 "VPWR", 0 0, L_00000000038dc1a0; 1 drivers, strength-aware
+v00000000036d49d0_0 .net "Y", 0 0, L_000000000395b3b0; 1 drivers
+S_00000000036afe80 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4226, 4 3980 1, S_00000000026fb860;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395bd50 .functor NAND 1, o000000000365b8f8, o000000000365b8c8, o000000000365b928, C4<1>;
+L_000000000395b3b0 .functor BUF 1, L_000000000395bd50, C4<0>, C4<0>, C4<0>;
+v00000000036d4610_0 .net "A", 0 0, o000000000365b8c8; alias, 0 drivers
+v00000000036d2f90_0 .net "B", 0 0, o000000000365b8f8; alias, 0 drivers
+v00000000036d46b0_0 .net "C", 0 0, o000000000365b928; alias, 0 drivers
+L_00000000038dc210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4a70_0 .net8 "VGND", 0 0, L_00000000038dc210; 1 drivers, strength-aware
+L_00000000038db4f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d2ef0_0 .net8 "VNB", 0 0, L_00000000038db4f0; 1 drivers, strength-aware
+L_00000000038dc280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4750_0 .net8 "VPB", 0 0, L_00000000038dc280; 1 drivers, strength-aware
+L_00000000038dc2f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4cf0_0 .net8 "VPWR", 0 0, L_00000000038dc2f0; 1 drivers, strength-aware
+v00000000036d47f0_0 .net "Y", 0 0, L_000000000395b3b0; alias, 1 drivers
+v00000000036d3c10_0 .net "nand0_out_Y", 0 0, L_000000000395bd50; 1 drivers
+S_00000000026f9760 .scope module, "sky130_fd_sc_hd__nand3_2" "sky130_fd_sc_hd__nand3_2" 4 4096;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365bcb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6410_0 .net "A", 0 0, o000000000365bcb8; 0 drivers
+o000000000365bce8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d7310_0 .net "B", 0 0, o000000000365bce8; 0 drivers
+o000000000365bd18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d71d0_0 .net "C", 0 0, o000000000365bd18; 0 drivers
+L_00000000038dc830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d69b0_0 .net8 "VGND", 0 0, L_00000000038dc830; 1 drivers, strength-aware
+L_00000000038db250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d7810_0 .net8 "VNB", 0 0, L_00000000038db250; 1 drivers, strength-aware
+L_00000000038dc360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d7770_0 .net8 "VPB", 0 0, L_00000000038dc360; 1 drivers, strength-aware
+L_00000000038dc440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5b50_0 .net8 "VPWR", 0 0, L_00000000038dc440; 1 drivers, strength-aware
+v00000000036d65f0_0 .net "Y", 0 0, L_000000000395b0a0; 1 drivers
+S_00000000036aef80 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4114, 4 3980 1, S_00000000026f9760;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395b500 .functor NAND 1, o000000000365bce8, o000000000365bcb8, o000000000365bd18, C4<1>;
+L_000000000395b0a0 .functor BUF 1, L_000000000395b500, C4<0>, C4<0>, C4<0>;
+v00000000036d38f0_0 .net "A", 0 0, o000000000365bcb8; alias, 0 drivers
+v00000000036d3ad0_0 .net "B", 0 0, o000000000365bce8; alias, 0 drivers
+v00000000036d4b10_0 .net "C", 0 0, o000000000365bd18; alias, 0 drivers
+L_00000000038dc4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4d90_0 .net8 "VGND", 0 0, L_00000000038dc4b0; 1 drivers, strength-aware
+L_00000000038dc9f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d4e30_0 .net8 "VNB", 0 0, L_00000000038dc9f0; 1 drivers, strength-aware
+L_00000000038dc520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d4ed0_0 .net8 "VPB", 0 0, L_00000000038dc520; 1 drivers, strength-aware
+L_00000000038db480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d3d50_0 .net8 "VPWR", 0 0, L_00000000038db480; 1 drivers, strength-aware
+v00000000036d4070_0 .net "Y", 0 0, L_000000000395b0a0; alias, 1 drivers
+v00000000036d6af0_0 .net "nand0_out_Y", 0 0, L_000000000395b500; 1 drivers
+S_00000000026faf60 .scope module, "sky130_fd_sc_hd__nand3_4" "sky130_fd_sc_hd__nand3_4" 4 4320;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365c0a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6eb0_0 .net "A", 0 0, o000000000365c0a8; 0 drivers
+o000000000365c0d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d5830_0 .net "B", 0 0, o000000000365c0d8; 0 drivers
+o000000000365c108 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6050_0 .net "C", 0 0, o000000000365c108; 0 drivers
+L_00000000038dc600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d5bf0_0 .net8 "VGND", 0 0, L_00000000038dc600; 1 drivers, strength-aware
+L_00000000038dc6e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d78b0_0 .net8 "VNB", 0 0, L_00000000038dc6e0; 1 drivers, strength-aware
+L_00000000038dc750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d67d0_0 .net8 "VPB", 0 0, L_00000000038dc750; 1 drivers, strength-aware
+L_00000000038dc7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d6a50_0 .net8 "VPWR", 0 0, L_00000000038dc7c0; 1 drivers, strength-aware
+v00000000036d5d30_0 .net "Y", 0 0, L_000000000395b7a0; 1 drivers
+S_00000000036afd00 .scope module, "base" "sky130_fd_sc_hd__nand3" 4 4338, 4 3980 1, S_00000000026faf60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395bff0 .functor NAND 1, o000000000365c0d8, o000000000365c0a8, o000000000365c108, C4<1>;
+L_000000000395b7a0 .functor BUF 1, L_000000000395bff0, C4<0>, C4<0>, C4<0>;
+v00000000036d7270_0 .net "A", 0 0, o000000000365c0a8; alias, 0 drivers
+v00000000036d6c30_0 .net "B", 0 0, o000000000365c0d8; alias, 0 drivers
+v00000000036d6550_0 .net "C", 0 0, o000000000365c108; alias, 0 drivers
+L_00000000038dc8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d6690_0 .net8 "VGND", 0 0, L_00000000038dc8a0; 1 drivers, strength-aware
+L_00000000038dc910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d5e70_0 .net8 "VNB", 0 0, L_00000000038dc910; 1 drivers, strength-aware
+L_00000000038dca60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d6370_0 .net8 "VPB", 0 0, L_00000000038dca60; 1 drivers, strength-aware
+L_00000000038dcad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d6b90_0 .net8 "VPWR", 0 0, L_00000000038dcad0; 1 drivers, strength-aware
+v00000000036d58d0_0 .net "Y", 0 0, L_000000000395b7a0; alias, 1 drivers
+v00000000036d5150_0 .net "nand0_out_Y", 0 0, L_000000000395bff0; 1 drivers
+S_00000000026fac60 .scope module, "sky130_fd_sc_hd__nand3b_1" "sky130_fd_sc_hd__nand3b_1" 4 69205;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365c498 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6870_0 .net "A_N", 0 0, o000000000365c498; 0 drivers
+o000000000365c4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6910_0 .net "B", 0 0, o000000000365c4c8; 0 drivers
+o000000000365c4f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d6e10_0 .net "C", 0 0, o000000000365c4f8; 0 drivers
+L_00000000038dcb40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d74f0_0 .net8 "VGND", 0 0, L_00000000038dcb40; 1 drivers, strength-aware
+L_00000000038db2c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d7450_0 .net8 "VNB", 0 0, L_00000000038db2c0; 1 drivers, strength-aware
+L_00000000038db560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5290_0 .net8 "VPB", 0 0, L_00000000038db560; 1 drivers, strength-aware
+L_00000000038de5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d6230_0 .net8 "VPWR", 0 0, L_00000000038de5f0; 1 drivers, strength-aware
+v00000000036d5dd0_0 .net "Y", 0 0, L_000000000395b420; 1 drivers
+S_00000000036b1e00 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69223, 4 69517 1, S_00000000026fac60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395bdc0 .functor NOT 1, o000000000365c498, C4<0>, C4<0>, C4<0>;
+L_000000000395b570 .functor NAND 1, o000000000365c4c8, L_000000000395bdc0, o000000000365c4f8, C4<1>;
+L_000000000395b420 .functor BUF 1, L_000000000395b570, C4<0>, C4<0>, C4<0>;
+v00000000036d5510_0 .net "A_N", 0 0, o000000000365c498; alias, 0 drivers
+v00000000036d6cd0_0 .net "B", 0 0, o000000000365c4c8; alias, 0 drivers
+v00000000036d73b0_0 .net "C", 0 0, o000000000365c4f8; alias, 0 drivers
+L_00000000038de820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d6d70_0 .net8 "VGND", 0 0, L_00000000038de820; 1 drivers, strength-aware
+L_00000000038de580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d7590_0 .net8 "VNB", 0 0, L_00000000038de580; 1 drivers, strength-aware
+L_00000000038de270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5f10_0 .net8 "VPB", 0 0, L_00000000038de270; 1 drivers, strength-aware
+L_00000000038ddb70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5fb0_0 .net8 "VPWR", 0 0, L_00000000038ddb70; 1 drivers, strength-aware
+v00000000036d6730_0 .net "Y", 0 0, L_000000000395b420; alias, 1 drivers
+v00000000036d5970_0 .net "nand0_out_Y", 0 0, L_000000000395b570; 1 drivers
+v00000000036d51f0_0 .net "not0_out", 0 0, L_000000000395bdc0; 1 drivers
+S_00000000026fbce0 .scope module, "sky130_fd_sc_hd__nand3b_2" "sky130_fd_sc_hd__nand3b_2" 4 69635;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365c8b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d76d0_0 .net "A_N", 0 0, o000000000365c8b8; 0 drivers
+o000000000365c8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d5330_0 .net "B", 0 0, o000000000365c8e8; 0 drivers
+o000000000365c918 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d60f0_0 .net "C", 0 0, o000000000365c918; 0 drivers
+L_00000000038dda20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d53d0_0 .net8 "VGND", 0 0, L_00000000038dda20; 1 drivers, strength-aware
+L_00000000038ddef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d6190_0 .net8 "VNB", 0 0, L_00000000038ddef0; 1 drivers, strength-aware
+L_00000000038ddf60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5470_0 .net8 "VPB", 0 0, L_00000000038ddf60; 1 drivers, strength-aware
+L_00000000038de660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d56f0_0 .net8 "VPWR", 0 0, L_00000000038de660; 1 drivers, strength-aware
+v00000000036d62d0_0 .net "Y", 0 0, L_000000000395b5e0; 1 drivers
+S_00000000036b0a80 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69653, 4 69517 1, S_00000000026fbce0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395b490 .functor NOT 1, o000000000365c8b8, C4<0>, C4<0>, C4<0>;
+L_000000000395bea0 .functor NAND 1, o000000000365c8e8, L_000000000395b490, o000000000365c918, C4<1>;
+L_000000000395b5e0 .functor BUF 1, L_000000000395bea0, C4<0>, C4<0>, C4<0>;
+v00000000036d64b0_0 .net "A_N", 0 0, o000000000365c8b8; alias, 0 drivers
+v00000000036d5c90_0 .net "B", 0 0, o000000000365c8e8; alias, 0 drivers
+v00000000036d55b0_0 .net "C", 0 0, o000000000365c918; alias, 0 drivers
+L_00000000038dd5c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d6f50_0 .net8 "VGND", 0 0, L_00000000038dd5c0; 1 drivers, strength-aware
+L_00000000038dde10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d6ff0_0 .net8 "VNB", 0 0, L_00000000038dde10; 1 drivers, strength-aware
+L_00000000038ddfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d7090_0 .net8 "VPB", 0 0, L_00000000038ddfd0; 1 drivers, strength-aware
+L_00000000038de120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d5650_0 .net8 "VPWR", 0 0, L_00000000038de120; 1 drivers, strength-aware
+v00000000036d7130_0 .net "Y", 0 0, L_000000000395b5e0; alias, 1 drivers
+v00000000036d5ab0_0 .net "nand0_out_Y", 0 0, L_000000000395bea0; 1 drivers
+v00000000036d7630_0 .net "not0_out", 0 0, L_000000000395b490; 1 drivers
+S_00000000026fade0 .scope module, "sky130_fd_sc_hd__nand3b_4" "sky130_fd_sc_hd__nand3b_4" 4 69093;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000365ccd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d9b10_0 .net "A_N", 0 0, o000000000365ccd8; 0 drivers
+o000000000365cd08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d91b0_0 .net "B", 0 0, o000000000365cd08; 0 drivers
+o000000000365cd38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d9610_0 .net "C", 0 0, o000000000365cd38; 0 drivers
+L_00000000038de6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d99d0_0 .net8 "VGND", 0 0, L_00000000038de6d0; 1 drivers, strength-aware
+L_00000000038dcf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d82b0_0 .net8 "VNB", 0 0, L_00000000038dcf30; 1 drivers, strength-aware
+L_00000000038dd010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9e30_0 .net8 "VPB", 0 0, L_00000000038dd010; 1 drivers, strength-aware
+L_00000000038dcfa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9d90_0 .net8 "VPWR", 0 0, L_00000000038dcfa0; 1 drivers, strength-aware
+v00000000036d8b70_0 .net "Y", 0 0, L_000000000395c060; 1 drivers
+S_00000000036af880 .scope module, "base" "sky130_fd_sc_hd__nand3b" 4 69111, 4 69517 1, S_00000000026fade0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395b6c0 .functor NOT 1, o000000000365ccd8, C4<0>, C4<0>, C4<0>;
+L_000000000395b880 .functor NAND 1, o000000000365cd08, L_000000000395b6c0, o000000000365cd38, C4<1>;
+L_000000000395c060 .functor BUF 1, L_000000000395b880, C4<0>, C4<0>, C4<0>;
+v00000000036d5790_0 .net "A_N", 0 0, o000000000365ccd8; alias, 0 drivers
+v00000000036d5a10_0 .net "B", 0 0, o000000000365cd08; alias, 0 drivers
+v00000000036d9750_0 .net "C", 0 0, o000000000365cd38; alias, 0 drivers
+L_00000000038de190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8530_0 .net8 "VGND", 0 0, L_00000000038de190; 1 drivers, strength-aware
+L_00000000038dd2b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8fd0_0 .net8 "VNB", 0 0, L_00000000038dd2b0; 1 drivers, strength-aware
+L_00000000038dd940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9110_0 .net8 "VPB", 0 0, L_00000000038dd940; 1 drivers, strength-aware
+L_00000000038ddbe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d7c70_0 .net8 "VPWR", 0 0, L_00000000038ddbe0; 1 drivers, strength-aware
+v00000000036d9f70_0 .net "Y", 0 0, L_000000000395c060; alias, 1 drivers
+v00000000036d8350_0 .net "nand0_out_Y", 0 0, L_000000000395b880; 1 drivers
+v00000000036d8df0_0 .net "not0_out", 0 0, L_000000000395b6c0; 1 drivers
+S_00000000026fb6e0 .scope module, "sky130_fd_sc_hd__nand4_1" "sky130_fd_sc_hd__nand4_1" 4 25605;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365d0f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d8f30_0 .net "A", 0 0, o000000000365d0f8; 0 drivers
+o000000000365d128 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d7d10_0 .net "B", 0 0, o000000000365d128; 0 drivers
+o000000000365d158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d8cb0_0 .net "C", 0 0, o000000000365d158; 0 drivers
+o000000000365d188 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d7950_0 .net "D", 0 0, o000000000365d188; 0 drivers
+L_00000000038dd080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d9390_0 .net8 "VGND", 0 0, L_00000000038dd080; 1 drivers, strength-aware
+L_00000000038ddcc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8670_0 .net8 "VNB", 0 0, L_00000000038ddcc0; 1 drivers, strength-aware
+L_00000000038ddc50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d7ef0_0 .net8 "VPB", 0 0, L_00000000038ddc50; 1 drivers, strength-aware
+L_00000000038dd0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d97f0_0 .net8 "VPWR", 0 0, L_00000000038dd0f0; 1 drivers, strength-aware
+v00000000036da010_0 .net "Y", 0 0, L_000000000395b8f0; 1 drivers
+S_00000000036ae380 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25625, 4 25484 1, S_00000000026fb6e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395bf10 .functor NAND 1, o000000000365d188, o000000000365d158, o000000000365d128, o000000000365d0f8;
+L_000000000395b8f0 .functor BUF 1, L_000000000395bf10, C4<0>, C4<0>, C4<0>;
+v00000000036d8990_0 .net "A", 0 0, o000000000365d0f8; alias, 0 drivers
+v00000000036d9ed0_0 .net "B", 0 0, o000000000365d128; alias, 0 drivers
+v00000000036d87b0_0 .net "C", 0 0, o000000000365d158; alias, 0 drivers
+v00000000036d83f0_0 .net "D", 0 0, o000000000365d188; alias, 0 drivers
+L_00000000038de740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8490_0 .net8 "VGND", 0 0, L_00000000038de740; 1 drivers, strength-aware
+L_00000000038dd1d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8e90_0 .net8 "VNB", 0 0, L_00000000038dd1d0; 1 drivers, strength-aware
+L_00000000038dd470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9070_0 .net8 "VPB", 0 0, L_00000000038dd470; 1 drivers, strength-aware
+L_00000000038dd240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9250_0 .net8 "VPWR", 0 0, L_00000000038dd240; 1 drivers, strength-aware
+v00000000036d85d0_0 .net "Y", 0 0, L_000000000395b8f0; alias, 1 drivers
+v00000000036d92f0_0 .net "nand0_out_Y", 0 0, L_000000000395bf10; 1 drivers
+S_00000000026fb9e0 .scope module, "sky130_fd_sc_hd__nand4_2" "sky130_fd_sc_hd__nand4_2" 4 25169;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365d578 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d8710_0 .net "A", 0 0, o000000000365d578; 0 drivers
+o000000000365d5a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d9a70_0 .net "B", 0 0, o000000000365d5a8; 0 drivers
+o000000000365d5d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d88f0_0 .net "C", 0 0, o000000000365d5d8; 0 drivers
+o000000000365d608 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036d8c10_0 .net "D", 0 0, o000000000365d608; 0 drivers
+L_00000000038dd7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8d50_0 .net8 "VGND", 0 0, L_00000000038dd7f0; 1 drivers, strength-aware
+L_00000000038de200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d9890_0 .net8 "VNB", 0 0, L_00000000038de200; 1 drivers, strength-aware
+L_00000000038dd710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9bb0_0 .net8 "VPB", 0 0, L_00000000038dd710; 1 drivers, strength-aware
+L_00000000038de040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9c50_0 .net8 "VPWR", 0 0, L_00000000038de040; 1 drivers, strength-aware
+v00000000036da0b0_0 .net "Y", 0 0, L_000000000395bf80; 1 drivers
+S_00000000036aee00 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25189, 4 25484 1, S_00000000026fb9e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395ac40 .functor NAND 1, o000000000365d608, o000000000365d5d8, o000000000365d5a8, o000000000365d578;
+L_000000000395bf80 .functor BUF 1, L_000000000395ac40, C4<0>, C4<0>, C4<0>;
+v00000000036d9430_0 .net "A", 0 0, o000000000365d578; alias, 0 drivers
+v00000000036d94d0_0 .net "B", 0 0, o000000000365d5a8; alias, 0 drivers
+v00000000036d9cf0_0 .net "C", 0 0, o000000000365d5d8; alias, 0 drivers
+v00000000036d8850_0 .net "D", 0 0, o000000000365d608; alias, 0 drivers
+L_00000000038de7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d7a90_0 .net8 "VGND", 0 0, L_00000000038de7b0; 1 drivers, strength-aware
+L_00000000038de890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8a30_0 .net8 "VNB", 0 0, L_00000000038de890; 1 drivers, strength-aware
+L_00000000038dcd00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d8ad0_0 .net8 "VPB", 0 0, L_00000000038dcd00; 1 drivers, strength-aware
+L_00000000038dd160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d9570_0 .net8 "VPWR", 0 0, L_00000000038dd160; 1 drivers, strength-aware
+v00000000036d96b0_0 .net "Y", 0 0, L_000000000395bf80; alias, 1 drivers
+v00000000036d9930_0 .net "nand0_out_Y", 0 0, L_000000000395ac40; 1 drivers
+S_00000000026f83e0 .scope module, "sky130_fd_sc_hd__nand4_4" "sky130_fd_sc_hd__nand4_4" 4 25723;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365d9f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dad30_0 .net "A", 0 0, o000000000365d9f8; 0 drivers
+o000000000365da28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036da8d0_0 .net "B", 0 0, o000000000365da28; 0 drivers
+o000000000365da58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dab50_0 .net "C", 0 0, o000000000365da58; 0 drivers
+o000000000365da88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dc6d0_0 .net "D", 0 0, o000000000365da88; 0 drivers
+L_00000000038de0b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036da1f0_0 .net8 "VGND", 0 0, L_00000000038de0b0; 1 drivers, strength-aware
+L_00000000038dd320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dadd0_0 .net8 "VNB", 0 0, L_00000000038dd320; 1 drivers, strength-aware
+L_00000000038de4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dafb0_0 .net8 "VPB", 0 0, L_00000000038de4a0; 1 drivers, strength-aware
+L_00000000038de2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dc130_0 .net8 "VPWR", 0 0, L_00000000038de2e0; 1 drivers, strength-aware
+v00000000036dc450_0 .net "Y", 0 0, L_000000000395ab60; 1 drivers
+S_00000000036b1200 .scope module, "base" "sky130_fd_sc_hd__nand4" 4 25743, 4 25484 1, S_00000000026f83e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395c0d0 .functor NAND 1, o000000000365da88, o000000000365da58, o000000000365da28, o000000000365d9f8;
+L_000000000395ab60 .functor BUF 1, L_000000000395c0d0, C4<0>, C4<0>, C4<0>;
+v00000000036d7f90_0 .net "A", 0 0, o000000000365d9f8; alias, 0 drivers
+v00000000036d79f0_0 .net "B", 0 0, o000000000365da28; alias, 0 drivers
+v00000000036d7b30_0 .net "C", 0 0, o000000000365da58; alias, 0 drivers
+v00000000036d7bd0_0 .net "D", 0 0, o000000000365da88; alias, 0 drivers
+L_00000000038dd390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d8170_0 .net8 "VGND", 0 0, L_00000000038dd390; 1 drivers, strength-aware
+L_00000000038dcd70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036d7db0_0 .net8 "VNB", 0 0, L_00000000038dcd70; 1 drivers, strength-aware
+L_00000000038dcec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d7e50_0 .net8 "VPB", 0 0, L_00000000038dcec0; 1 drivers, strength-aware
+L_00000000038de510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036d8030_0 .net8 "VPWR", 0 0, L_00000000038de510; 1 drivers, strength-aware
+v00000000036d80d0_0 .net "Y", 0 0, L_000000000395ab60; alias, 1 drivers
+v00000000036d8210_0 .net "nand0_out_Y", 0 0, L_000000000395c0d0; 1 drivers
+S_00000000026f9d60 .scope module, "sky130_fd_sc_hd__nand4b_1" "sky130_fd_sc_hd__nand4b_1" 4 6883;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365de78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036da150_0 .net "A_N", 0 0, o000000000365de78; 0 drivers
+o000000000365dea8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dc590_0 .net "B", 0 0, o000000000365dea8; 0 drivers
+o000000000365ded8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036da3d0_0 .net "C", 0 0, o000000000365ded8; 0 drivers
+o000000000365df08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dc630_0 .net "D", 0 0, o000000000365df08; 0 drivers
+L_00000000038ddd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036da650_0 .net8 "VGND", 0 0, L_00000000038ddd30; 1 drivers, strength-aware
+L_00000000038dde80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036da470_0 .net8 "VNB", 0 0, L_00000000038dde80; 1 drivers, strength-aware
+L_00000000038dd400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dc310_0 .net8 "VPB", 0 0, L_00000000038dd400; 1 drivers, strength-aware
+L_00000000038dd550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dbd70_0 .net8 "VPWR", 0 0, L_00000000038dd550; 1 drivers, strength-aware
+v00000000036db7d0_0 .net "Y", 0 0, L_000000000395a930; 1 drivers
+S_00000000036b1980 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 6903, 4 6642 1, S_00000000026f9d60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395b1f0 .functor NOT 1, o000000000365de78, C4<0>, C4<0>, C4<0>;
+L_000000000395c1b0 .functor NAND 1, o000000000365df08, o000000000365ded8, o000000000365dea8, L_000000000395b1f0;
+L_000000000395a930 .functor BUF 1, L_000000000395c1b0, C4<0>, C4<0>, C4<0>;
+v00000000036db910_0 .net "A_N", 0 0, o000000000365de78; alias, 0 drivers
+v00000000036da5b0_0 .net "B", 0 0, o000000000365dea8; alias, 0 drivers
+v00000000036da290_0 .net "C", 0 0, o000000000365ded8; alias, 0 drivers
+v00000000036dbb90_0 .net "D", 0 0, o000000000365df08; alias, 0 drivers
+L_00000000038dd780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dbeb0_0 .net8 "VGND", 0 0, L_00000000038dd780; 1 drivers, strength-aware
+L_00000000038de350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036db190_0 .net8 "VNB", 0 0, L_00000000038de350; 1 drivers, strength-aware
+L_00000000038de3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dc770_0 .net8 "VPB", 0 0, L_00000000038de3c0; 1 drivers, strength-aware
+L_00000000038dd4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036da330_0 .net8 "VPWR", 0 0, L_00000000038dd4e0; 1 drivers, strength-aware
+v00000000036dbaf0_0 .net "Y", 0 0, L_000000000395a930; alias, 1 drivers
+v00000000036db050_0 .net "nand0_out_Y", 0 0, L_000000000395c1b0; 1 drivers
+v00000000036dc1d0_0 .net "not0_out", 0 0, L_000000000395b1f0; 1 drivers
+S_00000000026fa4e0 .scope module, "sky130_fd_sc_hd__nand4b_2" "sky130_fd_sc_hd__nand4b_2" 4 7001;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365e328 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036db0f0_0 .net "A_N", 0 0, o000000000365e328; 0 drivers
+o000000000365e358 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dbf50_0 .net "B", 0 0, o000000000365e358; 0 drivers
+o000000000365e388 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036daa10_0 .net "C", 0 0, o000000000365e388; 0 drivers
+o000000000365e3b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036db230_0 .net "D", 0 0, o000000000365e3b8; 0 drivers
+L_00000000038de430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dba50_0 .net8 "VGND", 0 0, L_00000000038de430; 1 drivers, strength-aware
+L_00000000038dd630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036da790_0 .net8 "VNB", 0 0, L_00000000038dd630; 1 drivers, strength-aware
+L_00000000038dcde0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036daab0_0 .net8 "VPB", 0 0, L_00000000038dcde0; 1 drivers, strength-aware
+L_00000000038dce50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036db2d0_0 .net8 "VPWR", 0 0, L_00000000038dce50; 1 drivers, strength-aware
+v00000000036dabf0_0 .net "Y", 0 0, L_000000000395b960; 1 drivers
+S_00000000036af100 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 7021, 4 6642 1, S_00000000026fa4e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395bb20 .functor NOT 1, o000000000365e328, C4<0>, C4<0>, C4<0>;
+L_000000000395afc0 .functor NAND 1, o000000000365e3b8, o000000000365e388, o000000000365e358, L_000000000395bb20;
+L_000000000395b960 .functor BUF 1, L_000000000395afc0, C4<0>, C4<0>, C4<0>;
+v00000000036da970_0 .net "A_N", 0 0, o000000000365e328; alias, 0 drivers
+v00000000036db370_0 .net "B", 0 0, o000000000365e358; alias, 0 drivers
+v00000000036da830_0 .net "C", 0 0, o000000000365e388; alias, 0 drivers
+v00000000036db5f0_0 .net "D", 0 0, o000000000365e3b8; alias, 0 drivers
+L_00000000038dd6a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dbc30_0 .net8 "VGND", 0 0, L_00000000038dd6a0; 1 drivers, strength-aware
+L_00000000038dd860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036db550_0 .net8 "VNB", 0 0, L_00000000038dd860; 1 drivers, strength-aware
+L_00000000038dd8d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036db690_0 .net8 "VPB", 0 0, L_00000000038dd8d0; 1 drivers, strength-aware
+L_00000000038dd9b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dc810_0 .net8 "VPWR", 0 0, L_00000000038dd9b0; 1 drivers, strength-aware
+v00000000036dc8b0_0 .net "Y", 0 0, L_000000000395b960; alias, 1 drivers
+v00000000036da6f0_0 .net "nand0_out_Y", 0 0, L_000000000395afc0; 1 drivers
+v00000000036da510_0 .net "not0_out", 0 0, L_000000000395bb20; 1 drivers
+S_00000000026fb0e0 .scope module, "sky130_fd_sc_hd__nand4b_4" "sky130_fd_sc_hd__nand4b_4" 4 6765;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365e7d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dbcd0_0 .net "A_N", 0 0, o000000000365e7d8; 0 drivers
+o000000000365e808 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036db730_0 .net "B", 0 0, o000000000365e808; 0 drivers
+o000000000365e838 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dbe10_0 .net "C", 0 0, o000000000365e838; 0 drivers
+o000000000365e868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dc4f0_0 .net "D", 0 0, o000000000365e868; 0 drivers
+L_00000000038dda90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036de750_0 .net8 "VGND", 0 0, L_00000000038dda90; 1 drivers, strength-aware
+L_00000000038ddb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dd5d0_0 .net8 "VNB", 0 0, L_00000000038ddb00; 1 drivers, strength-aware
+L_00000000038ddda0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dd490_0 .net8 "VPB", 0 0, L_00000000038ddda0; 1 drivers, strength-aware
+L_00000000038deac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036de4d0_0 .net8 "VPWR", 0 0, L_00000000038deac0; 1 drivers, strength-aware
+v00000000036de610_0 .net "Y", 0 0, L_000000000395ba40; 1 drivers
+S_00000000036af580 .scope module, "base" "sky130_fd_sc_hd__nand4b" 4 6785, 4 6642 1, S_00000000026fb0e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395aee0 .functor NOT 1, o000000000365e7d8, C4<0>, C4<0>, C4<0>;
+L_000000000395af50 .functor NAND 1, o000000000365e868, o000000000365e838, o000000000365e808, L_000000000395aee0;
+L_000000000395ba40 .functor BUF 1, L_000000000395af50, C4<0>, C4<0>, C4<0>;
+v00000000036db870_0 .net "A_N", 0 0, o000000000365e7d8; alias, 0 drivers
+v00000000036dac90_0 .net "B", 0 0, o000000000365e808; alias, 0 drivers
+v00000000036dae70_0 .net "C", 0 0, o000000000365e838; alias, 0 drivers
+v00000000036db9b0_0 .net "D", 0 0, o000000000365e868; alias, 0 drivers
+L_00000000038e03b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dc270_0 .net8 "VGND", 0 0, L_00000000038e03b0; 1 drivers, strength-aware
+L_00000000038df460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036daf10_0 .net8 "VNB", 0 0, L_00000000038df460; 1 drivers, strength-aware
+L_00000000038df4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dbff0_0 .net8 "VPB", 0 0, L_00000000038df4d0; 1 drivers, strength-aware
+L_00000000038def90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036db410_0 .net8 "VPWR", 0 0, L_00000000038def90; 1 drivers, strength-aware
+v00000000036db4b0_0 .net "Y", 0 0, L_000000000395ba40; alias, 1 drivers
+v00000000036dc090_0 .net "nand0_out_Y", 0 0, L_000000000395af50; 1 drivers
+v00000000036dc3b0_0 .net "not0_out", 0 0, L_000000000395aee0; 1 drivers
+S_00000000026f9be0 .scope module, "sky130_fd_sc_hd__nand4bb_1" "sky130_fd_sc_hd__nand4bb_1" 4 28507;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365ec88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dd530_0 .net "A_N", 0 0, o000000000365ec88; 0 drivers
+o000000000365ecb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036def70_0 .net "B_N", 0 0, o000000000365ecb8; 0 drivers
+o000000000365ece8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ddcb0_0 .net "C", 0 0, o000000000365ece8; 0 drivers
+o000000000365ed18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036de890_0 .net "D", 0 0, o000000000365ed18; 0 drivers
+L_00000000038dfa80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dc9f0_0 .net8 "VGND", 0 0, L_00000000038dfa80; 1 drivers, strength-aware
+L_00000000038dec80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dd8f0_0 .net8 "VNB", 0 0, L_00000000038dec80; 1 drivers, strength-aware
+L_00000000038decf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dd990_0 .net8 "VPB", 0 0, L_00000000038decf0; 1 drivers, strength-aware
+L_00000000038deb30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036de2f0_0 .net8 "VPWR", 0 0, L_00000000038deb30; 1 drivers, strength-aware
+v00000000036de9d0_0 .net "Y", 0 0, L_000000000395aa80; 1 drivers
+S_00000000036af280 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 28527, 4 28828 1, S_00000000026f9be0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395bab0 .functor NAND 1, o000000000365ed18, o000000000365ece8, C4<1>, C4<1>;
+L_000000000395c220 .functor OR 1, o000000000365ecb8, o000000000365ec88, L_000000000395bab0, C4<0>;
+L_000000000395aa80 .functor BUF 1, L_000000000395c220, C4<0>, C4<0>, C4<0>;
+v00000000036dcef0_0 .net "A_N", 0 0, o000000000365ec88; alias, 0 drivers
+v00000000036de570_0 .net "B_N", 0 0, o000000000365ecb8; alias, 0 drivers
+v00000000036ddf30_0 .net "C", 0 0, o000000000365ece8; alias, 0 drivers
+v00000000036dd0d0_0 .net "D", 0 0, o000000000365ed18; alias, 0 drivers
+L_00000000038dfbd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dd850_0 .net8 "VGND", 0 0, L_00000000038dfbd0; 1 drivers, strength-aware
+L_00000000038deba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036de250_0 .net8 "VNB", 0 0, L_00000000038deba0; 1 drivers, strength-aware
+L_00000000038de970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036de7f0_0 .net8 "VPB", 0 0, L_00000000038de970; 1 drivers, strength-aware
+L_00000000038df000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dda30_0 .net8 "VPWR", 0 0, L_00000000038df000; 1 drivers, strength-aware
+v00000000036dce50_0 .net "Y", 0 0, L_000000000395aa80; alias, 1 drivers
+v00000000036de6b0_0 .net "nand0_out", 0 0, L_000000000395bab0; 1 drivers
+v00000000036de930_0 .net "or0_out_Y", 0 0, L_000000000395c220; 1 drivers
+S_00000000026faae0 .scope module, "sky130_fd_sc_hd__nand4bb_2" "sky130_fd_sc_hd__nand4bb_2" 4 28951;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365f138 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dd3f0_0 .net "A_N", 0 0, o000000000365f138; 0 drivers
+o000000000365f168 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ddad0_0 .net "B_N", 0 0, o000000000365f168; 0 drivers
+o000000000365f198 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dcf90_0 .net "C", 0 0, o000000000365f198; 0 drivers
+o000000000365f1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036de1b0_0 .net "D", 0 0, o000000000365f1c8; 0 drivers
+L_00000000038df070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dd710_0 .net8 "VGND", 0 0, L_00000000038df070; 1 drivers, strength-aware
+L_00000000038de9e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ddfd0_0 .net8 "VNB", 0 0, L_00000000038de9e0; 1 drivers, strength-aware
+L_00000000038dee40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dca90_0 .net8 "VPB", 0 0, L_00000000038dee40; 1 drivers, strength-aware
+L_00000000038dfee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036df010_0 .net8 "VPWR", 0 0, L_00000000038dfee0; 1 drivers, strength-aware
+v00000000036dd030_0 .net "Y", 0 0, L_000000000395c3e0; 1 drivers
+S_00000000036b0780 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 28971, 4 28828 1, S_00000000026faae0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395c300 .functor NAND 1, o000000000365f1c8, o000000000365f198, C4<1>, C4<1>;
+L_000000000395c370 .functor OR 1, o000000000365f168, o000000000365f138, L_000000000395c300, C4<0>;
+L_000000000395c3e0 .functor BUF 1, L_000000000395c370, C4<0>, C4<0>, C4<0>;
+v00000000036dea70_0 .net "A_N", 0 0, o000000000365f138; alias, 0 drivers
+v00000000036deb10_0 .net "B_N", 0 0, o000000000365f168; alias, 0 drivers
+v00000000036ddd50_0 .net "C", 0 0, o000000000365f198; alias, 0 drivers
+v00000000036dd670_0 .net "D", 0 0, o000000000365f1c8; alias, 0 drivers
+L_00000000038def20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dcd10_0 .net8 "VGND", 0 0, L_00000000038def20; 1 drivers, strength-aware
+L_00000000038dea50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036de390_0 .net8 "VNB", 0 0, L_00000000038dea50; 1 drivers, strength-aware
+L_00000000038df770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dd170_0 .net8 "VPB", 0 0, L_00000000038df770; 1 drivers, strength-aware
+L_00000000038dec10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dc950_0 .net8 "VPWR", 0 0, L_00000000038dec10; 1 drivers, strength-aware
+v00000000036dcb30_0 .net "Y", 0 0, L_000000000395c3e0; alias, 1 drivers
+v00000000036dd7b0_0 .net "nand0_out", 0 0, L_000000000395c300; 1 drivers
+v00000000036decf0_0 .net "or0_out_Y", 0 0, L_000000000395c370; 1 drivers
+S_00000000026fb560 .scope module, "sky130_fd_sc_hd__nand4bb_4" "sky130_fd_sc_hd__nand4bb_4" 4 29069;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000365f5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dcdb0_0 .net "A_N", 0 0, o000000000365f5e8; 0 drivers
+o000000000365f618 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ddc10_0 .net "B_N", 0 0, o000000000365f618; 0 drivers
+o000000000365f648 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dde90_0 .net "C", 0 0, o000000000365f648; 0 drivers
+o000000000365f678 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036dec50_0 .net "D", 0 0, o000000000365f678; 0 drivers
+L_00000000038dff50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036deed0_0 .net8 "VGND", 0 0, L_00000000038dff50; 1 drivers, strength-aware
+L_00000000038dfa10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dd2b0_0 .net8 "VNB", 0 0, L_00000000038dfa10; 1 drivers, strength-aware
+L_00000000038e0420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036de110_0 .net8 "VPB", 0 0, L_00000000038e0420; 1 drivers, strength-aware
+L_00000000038dfd90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dd350_0 .net8 "VPWR", 0 0, L_00000000038dfd90; 1 drivers, strength-aware
+v00000000036dff10_0 .net "Y", 0 0, L_000000000395abd0; 1 drivers
+S_00000000036b1500 .scope module, "base" "sky130_fd_sc_hd__nand4bb" 4 29089, 4 28828 1, S_00000000026fb560;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A_N"
+ .port_info 2 /INPUT 1 "B_N"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395c450 .functor NAND 1, o000000000365f678, o000000000365f648, C4<1>, C4<1>;
+L_000000000395aaf0 .functor OR 1, o000000000365f618, o000000000365f5e8, L_000000000395c450, C4<0>;
+L_000000000395abd0 .functor BUF 1, L_000000000395aaf0, C4<0>, C4<0>, C4<0>;
+v00000000036ded90_0 .net "A_N", 0 0, o000000000365f5e8; alias, 0 drivers
+v00000000036ddb70_0 .net "B_N", 0 0, o000000000365f618; alias, 0 drivers
+v00000000036debb0_0 .net "C", 0 0, o000000000365f648; alias, 0 drivers
+v00000000036dd210_0 .net "D", 0 0, o000000000365f678; alias, 0 drivers
+L_00000000038dfaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036de070_0 .net8 "VGND", 0 0, L_00000000038dfaf0; 1 drivers, strength-aware
+L_00000000038df2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dee30_0 .net8 "VNB", 0 0, L_00000000038df2a0; 1 drivers, strength-aware
+L_00000000038dffc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dcbd0_0 .net8 "VPB", 0 0, L_00000000038dffc0; 1 drivers, strength-aware
+L_00000000038dfd20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036df0b0_0 .net8 "VPWR", 0 0, L_00000000038dfd20; 1 drivers, strength-aware
+v00000000036dcc70_0 .net "Y", 0 0, L_000000000395abd0; alias, 1 drivers
+v00000000036de430_0 .net "nand0_out", 0 0, L_000000000395c450; 1 drivers
+v00000000036dddf0_0 .net "or0_out_Y", 0 0, L_000000000395aaf0; 1 drivers
+S_00000000026fbb60 .scope module, "sky130_fd_sc_hd__nor2_1" "sky130_fd_sc_hd__nor2_1" 4 30391;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000365fa98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e1310_0 .net "A", 0 0, o000000000365fa98; 0 drivers
+o000000000365fac8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e1130_0 .net "B", 0 0, o000000000365fac8; 0 drivers
+L_00000000038df380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0190_0 .net8 "VGND", 0 0, L_00000000038df380; 1 drivers, strength-aware
+L_00000000038df0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0eb0_0 .net8 "VNB", 0 0, L_00000000038df0e0; 1 drivers, strength-aware
+L_00000000038dfe70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e09b0_0 .net8 "VPB", 0 0, L_00000000038dfe70; 1 drivers, strength-aware
+L_00000000038df150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e0b90_0 .net8 "VPWR", 0 0, L_00000000038df150; 1 drivers, strength-aware
+v00000000036df1f0_0 .net "Y", 0 0, L_000000000395ae70; 1 drivers
+S_00000000036afb80 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30407, 4 30688 1, S_00000000026fbb60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395ad90 .functor NOR 1, o000000000365fa98, o000000000365fac8, C4<0>, C4<0>;
+L_000000000395ae70 .functor BUF 1, L_000000000395ad90, C4<0>, C4<0>, C4<0>;
+v00000000036e1090_0 .net "A", 0 0, o000000000365fa98; alias, 0 drivers
+v00000000036dffb0_0 .net "B", 0 0, o000000000365fac8; alias, 0 drivers
+L_00000000038ded60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0ff0_0 .net8 "VGND", 0 0, L_00000000038ded60; 1 drivers, strength-aware
+L_00000000038df9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036df5b0_0 .net8 "VNB", 0 0, L_00000000038df9a0; 1 drivers, strength-aware
+L_00000000038dedd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dfbf0_0 .net8 "VPB", 0 0, L_00000000038dedd0; 1 drivers, strength-aware
+L_00000000038df1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e0910_0 .net8 "VPWR", 0 0, L_00000000038df1c0; 1 drivers, strength-aware
+v00000000036dfd30_0 .net "Y", 0 0, L_000000000395ae70; alias, 1 drivers
+v00000000036dfc90_0 .net "nor0_out_Y", 0 0, L_000000000395ad90; 1 drivers
+S_00000000026f80e0 .scope module, "sky130_fd_sc_hd__nor2_4" "sky130_fd_sc_hd__nor2_4" 4 30799;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000365fdf8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036df470_0 .net "A", 0 0, o000000000365fdf8; 0 drivers
+o000000000365fe28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e1450_0 .net "B", 0 0, o000000000365fe28; 0 drivers
+L_00000000038de900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e00f0_0 .net8 "VGND", 0 0, L_00000000038de900; 1 drivers, strength-aware
+L_00000000038dfc40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036df510_0 .net8 "VNB", 0 0, L_00000000038dfc40; 1 drivers, strength-aware
+L_00000000038deeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1630_0 .net8 "VPB", 0 0, L_00000000038deeb0; 1 drivers, strength-aware
+L_00000000038df230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e0370_0 .net8 "VPWR", 0 0, L_00000000038df230; 1 drivers, strength-aware
+v00000000036df330_0 .net "Y", 0 0, L_000000000395cc30; 1 drivers
+S_00000000036b0180 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30815, 4 30688 1, S_00000000026f80e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395d2c0 .functor NOR 1, o000000000365fdf8, o000000000365fe28, C4<0>, C4<0>;
+L_000000000395cc30 .functor BUF 1, L_000000000395d2c0, C4<0>, C4<0>, C4<0>;
+v00000000036dfdd0_0 .net "A", 0 0, o000000000365fdf8; alias, 0 drivers
+v00000000036df8d0_0 .net "B", 0 0, o000000000365fe28; alias, 0 drivers
+L_00000000038dfb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dfb50_0 .net8 "VGND", 0 0, L_00000000038dfb60; 1 drivers, strength-aware
+L_00000000038dfcb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e16d0_0 .net8 "VNB", 0 0, L_00000000038dfcb0; 1 drivers, strength-aware
+L_00000000038df310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036df290_0 .net8 "VPB", 0 0, L_00000000038df310; 1 drivers, strength-aware
+L_00000000038e0030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dfe70_0 .net8 "VPWR", 0 0, L_00000000038e0030; 1 drivers, strength-aware
+v00000000036e0050_0 .net "Y", 0 0, L_000000000395cc30; alias, 1 drivers
+v00000000036e11d0_0 .net "nor0_out_Y", 0 0, L_000000000395d2c0; 1 drivers
+S_00000000026fb260 .scope module, "sky130_fd_sc_hd__nor2_8" "sky130_fd_sc_hd__nor2_8" 4 30905;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003660158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e0f50_0 .net "A", 0 0, o0000000003660158; 0 drivers
+o0000000003660188 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e0410_0 .net "B", 0 0, o0000000003660188; 0 drivers
+L_00000000038df3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036df6f0_0 .net8 "VGND", 0 0, L_00000000038df3f0; 1 drivers, strength-aware
+L_00000000038e01f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0af0_0 .net8 "VNB", 0 0, L_00000000038e01f0; 1 drivers, strength-aware
+L_00000000038df620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036dfab0_0 .net8 "VPB", 0 0, L_00000000038df620; 1 drivers, strength-aware
+L_00000000038df8c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e02d0_0 .net8 "VPWR", 0 0, L_00000000038df8c0; 1 drivers, strength-aware
+v00000000036e13b0_0 .net "Y", 0 0, L_000000000395c6f0; 1 drivers
+S_00000000036b0300 .scope module, "base" "sky130_fd_sc_hd__nor2" 4 30921, 4 30688 1, S_00000000026fb260;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000395c610 .functor NOR 1, o0000000003660158, o0000000003660188, C4<0>, C4<0>;
+L_000000000395c6f0 .functor BUF 1, L_000000000395c610, C4<0>, C4<0>, C4<0>;
+v00000000036df650_0 .net "A", 0 0, o0000000003660158; alias, 0 drivers
+v00000000036df970_0 .net "B", 0 0, o0000000003660188; alias, 0 drivers
+L_00000000038e0180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e05f0_0 .net8 "VGND", 0 0, L_00000000038e0180; 1 drivers, strength-aware
+L_00000000038dfe00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036dfa10_0 .net8 "VNB", 0 0, L_00000000038dfe00; 1 drivers, strength-aware
+L_00000000038e02d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1270_0 .net8 "VPB", 0 0, L_00000000038e02d0; 1 drivers, strength-aware
+L_00000000038df690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e0a50_0 .net8 "VPWR", 0 0, L_00000000038df690; 1 drivers, strength-aware
+v00000000036df830_0 .net "Y", 0 0, L_000000000395c6f0; alias, 1 drivers
+v00000000036e0230_0 .net "nor0_out_Y", 0 0, L_000000000395c610; 1 drivers
+S_00000000026fa660 .scope module, "sky130_fd_sc_hd__nor2b_1" "sky130_fd_sc_hd__nor2b_1" 4 5605;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o00000000036604b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e0870_0 .net "A", 0 0, o00000000036604b8; 0 drivers
+o00000000036604e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e0cd0_0 .net "B_N", 0 0, o00000000036604e8; 0 drivers
+L_00000000038e0340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0d70_0 .net8 "VGND", 0 0, L_00000000038e0340; 1 drivers, strength-aware
+L_00000000038e00a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e14f0_0 .net8 "VNB", 0 0, L_00000000038e00a0; 1 drivers, strength-aware
+L_00000000038df540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1590_0 .net8 "VPB", 0 0, L_00000000038df540; 1 drivers, strength-aware
+L_00000000038df5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1810_0 .net8 "VPWR", 0 0, L_00000000038df5b0; 1 drivers, strength-aware
+v00000000036e18b0_0 .net "Y", 0 0, L_000000000395c7d0; 1 drivers
+S_00000000036af400 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5621, 4 5274 1, S_00000000026fa660;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_000000000395c760 .functor NOT 1, o00000000036604b8, C4<0>, C4<0>, C4<0>;
+L_000000000395ddb0 .functor AND 1, L_000000000395c760, o00000000036604e8, C4<1>, C4<1>;
+L_000000000395c7d0 .functor BUF 1, L_000000000395ddb0, C4<0>, C4<0>, C4<0>;
+v00000000036e04b0_0 .net "A", 0 0, o00000000036604b8; alias, 0 drivers
+v00000000036e0c30_0 .net "B_N", 0 0, o00000000036604e8; alias, 0 drivers
+L_00000000038df700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0e10_0 .net8 "VGND", 0 0, L_00000000038df700; 1 drivers, strength-aware
+L_00000000038e0110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e0550_0 .net8 "VNB", 0 0, L_00000000038e0110; 1 drivers, strength-aware
+L_00000000038e0260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e0690_0 .net8 "VPB", 0 0, L_00000000038e0260; 1 drivers, strength-aware
+L_00000000038e0490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036df790_0 .net8 "VPWR", 0 0, L_00000000038e0490; 1 drivers, strength-aware
+v00000000036e1770_0 .net "Y", 0 0, L_000000000395c7d0; alias, 1 drivers
+v00000000036e0730_0 .net "and0_out_Y", 0 0, L_000000000395ddb0; 1 drivers
+v00000000036e07d0_0 .net "not0_out", 0 0, L_000000000395c760; 1 drivers
+S_00000000026fa7e0 .scope module, "sky130_fd_sc_hd__nor2b_2" "sky130_fd_sc_hd__nor2b_2" 4 5389;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o0000000003660848 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e2030_0 .net "A", 0 0, o0000000003660848; 0 drivers
+o0000000003660878 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e2850_0 .net "B_N", 0 0, o0000000003660878; 0 drivers
+L_00000000038df7e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e2350_0 .net8 "VGND", 0 0, L_00000000038df7e0; 1 drivers, strength-aware
+L_00000000038df850 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e2df0_0 .net8 "VNB", 0 0, L_00000000038df850; 1 drivers, strength-aware
+L_00000000038df930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2fd0_0 .net8 "VPB", 0 0, L_00000000038df930; 1 drivers, strength-aware
+L_00000000038e0ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e3f70_0 .net8 "VPWR", 0 0, L_00000000038e0ea0; 1 drivers, strength-aware
+v00000000036e2cb0_0 .net "Y", 0 0, L_000000000395d950; 1 drivers
+S_00000000036b1380 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5405, 4 5274 1, S_00000000026fa7e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_000000000395c8b0 .functor NOT 1, o0000000003660848, C4<0>, C4<0>, C4<0>;
+L_000000000395c840 .functor AND 1, L_000000000395c8b0, o0000000003660878, C4<1>, C4<1>;
+L_000000000395d950 .functor BUF 1, L_000000000395c840, C4<0>, C4<0>, C4<0>;
+v00000000036df150_0 .net "A", 0 0, o0000000003660848; alias, 0 drivers
+v00000000036df3d0_0 .net "B_N", 0 0, o0000000003660878; alias, 0 drivers
+L_00000000038e1b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3e30_0 .net8 "VGND", 0 0, L_00000000038e1b50; 1 drivers, strength-aware
+L_00000000038e1680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e1d10_0 .net8 "VNB", 0 0, L_00000000038e1680; 1 drivers, strength-aware
+L_00000000038e0880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1db0_0 .net8 "VPB", 0 0, L_00000000038e0880; 1 drivers, strength-aware
+L_00000000038e1a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e20d0_0 .net8 "VPWR", 0 0, L_00000000038e1a70; 1 drivers, strength-aware
+v00000000036e1950_0 .net "Y", 0 0, L_000000000395d950; alias, 1 drivers
+v00000000036e1b30_0 .net "and0_out_Y", 0 0, L_000000000395c840; 1 drivers
+v00000000036e28f0_0 .net "not0_out", 0 0, L_000000000395c8b0; 1 drivers
+S_00000000026f98e0 .scope module, "sky130_fd_sc_hd__nor2b_4" "sky130_fd_sc_hd__nor2b_4" 4 5497;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o0000000003660bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e1bd0_0 .net "A", 0 0, o0000000003660bd8; 0 drivers
+o0000000003660c08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e2f30_0 .net "B_N", 0 0, o0000000003660c08; 0 drivers
+L_00000000038e08f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3070_0 .net8 "VGND", 0 0, L_00000000038e08f0; 1 drivers, strength-aware
+L_00000000038e1760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3110_0 .net8 "VNB", 0 0, L_00000000038e1760; 1 drivers, strength-aware
+L_00000000038e17d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2210_0 .net8 "VPB", 0 0, L_00000000038e17d0; 1 drivers, strength-aware
+L_00000000038e1ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e3c50_0 .net8 "VPWR", 0 0, L_00000000038e1ae0; 1 drivers, strength-aware
+v00000000036e3570_0 .net "Y", 0 0, L_000000000395d8e0; 1 drivers
+S_00000000036ae080 .scope module, "base" "sky130_fd_sc_hd__nor2b" 4 5513, 4 5274 1, S_00000000026f98e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_000000000395cd10 .functor NOT 1, o0000000003660bd8, C4<0>, C4<0>, C4<0>;
+L_000000000395d3a0 .functor AND 1, L_000000000395cd10, o0000000003660c08, C4<1>, C4<1>;
+L_000000000395d8e0 .functor BUF 1, L_000000000395d3a0, C4<0>, C4<0>, C4<0>;
+v00000000036e1e50_0 .net "A", 0 0, o0000000003660bd8; alias, 0 drivers
+v00000000036e3390_0 .net "B_N", 0 0, o0000000003660c08; alias, 0 drivers
+L_00000000038e16f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3b10_0 .net8 "VGND", 0 0, L_00000000038e16f0; 1 drivers, strength-aware
+L_00000000038e10d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e34d0_0 .net8 "VNB", 0 0, L_00000000038e10d0; 1 drivers, strength-aware
+L_00000000038e1df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e3d90_0 .net8 "VPB", 0 0, L_00000000038e1df0; 1 drivers, strength-aware
+L_00000000038e0960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2710_0 .net8 "VPWR", 0 0, L_00000000038e0960; 1 drivers, strength-aware
+v00000000036e27b0_0 .net "Y", 0 0, L_000000000395d8e0; alias, 1 drivers
+v00000000036e2e90_0 .net "and0_out_Y", 0 0, L_000000000395d3a0; 1 drivers
+v00000000036e2170_0 .net "not0_out", 0 0, L_000000000395cd10; 1 drivers
+S_00000000026f9160 .scope module, "sky130_fd_sc_hd__nor3_1" "sky130_fd_sc_hd__nor3_1" 4 16734;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003660f68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e3250_0 .net "A", 0 0, o0000000003660f68; 0 drivers
+o0000000003660f98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e2490_0 .net "B", 0 0, o0000000003660f98; 0 drivers
+o0000000003660fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e22b0_0 .net "C", 0 0, o0000000003660fc8; 0 drivers
+L_00000000038e0ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e36b0_0 .net8 "VGND", 0 0, L_00000000038e0ff0; 1 drivers, strength-aware
+L_00000000038e1920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3930_0 .net8 "VNB", 0 0, L_00000000038e1920; 1 drivers, strength-aware
+L_00000000038e06c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2530_0 .net8 "VPB", 0 0, L_00000000038e06c0; 1 drivers, strength-aware
+L_00000000038e1fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e25d0_0 .net8 "VPWR", 0 0, L_00000000038e1fb0; 1 drivers, strength-aware
+v00000000036e19f0_0 .net "Y", 0 0, L_000000000395d9c0; 1 drivers
+S_00000000036b0480 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16752, 4 16616 1, S_00000000026f9160;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395d4f0 .functor NOR 1, o0000000003660fc8, o0000000003660f68, o0000000003660f98, C4<0>;
+L_000000000395d9c0 .functor BUF 1, L_000000000395d4f0, C4<0>, C4<0>, C4<0>;
+v00000000036e3610_0 .net "A", 0 0, o0000000003660f68; alias, 0 drivers
+v00000000036e2a30_0 .net "B", 0 0, o0000000003660f98; alias, 0 drivers
+v00000000036e2d50_0 .net "C", 0 0, o0000000003660fc8; alias, 0 drivers
+L_00000000038e1d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e23f0_0 .net8 "VGND", 0 0, L_00000000038e1d80; 1 drivers, strength-aware
+L_00000000038e1bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e2990_0 .net8 "VNB", 0 0, L_00000000038e1bc0; 1 drivers, strength-aware
+L_00000000038e1370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e1ef0_0 .net8 "VPB", 0 0, L_00000000038e1370; 1 drivers, strength-aware
+L_00000000038e1220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2ad0_0 .net8 "VPWR", 0 0, L_00000000038e1220; 1 drivers, strength-aware
+v00000000036e1f90_0 .net "Y", 0 0, L_000000000395d9c0; alias, 1 drivers
+v00000000036e31b0_0 .net "nor0_out_Y", 0 0, L_000000000395d4f0; 1 drivers
+S_00000000026fa1e0 .scope module, "sky130_fd_sc_hd__nor3_2" "sky130_fd_sc_hd__nor3_2" 4 16300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003661358 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e37f0_0 .net "A", 0 0, o0000000003661358; 0 drivers
+o0000000003661388 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e3890_0 .net "B", 0 0, o0000000003661388; 0 drivers
+o00000000036613b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e39d0_0 .net "C", 0 0, o00000000036613b8; 0 drivers
+L_00000000038e1840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3a70_0 .net8 "VGND", 0 0, L_00000000038e1840; 1 drivers, strength-aware
+L_00000000038e18b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3bb0_0 .net8 "VNB", 0 0, L_00000000038e18b0; 1 drivers, strength-aware
+L_00000000038e1e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e3ed0_0 .net8 "VPB", 0 0, L_00000000038e1e60; 1 drivers, strength-aware
+L_00000000038e0dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e4010_0 .net8 "VPWR", 0 0, L_00000000038e0dc0; 1 drivers, strength-aware
+v00000000036e40b0_0 .net "Y", 0 0, L_000000000395ced0; 1 drivers
+S_00000000036b0600 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16318, 4 16616 1, S_00000000026fa1e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395c5a0 .functor NOR 1, o00000000036613b8, o0000000003661358, o0000000003661388, C4<0>;
+L_000000000395ced0 .functor BUF 1, L_000000000395c5a0, C4<0>, C4<0>, C4<0>;
+v00000000036e1a90_0 .net "A", 0 0, o0000000003661358; alias, 0 drivers
+v00000000036e2670_0 .net "B", 0 0, o0000000003661388; alias, 0 drivers
+v00000000036e2b70_0 .net "C", 0 0, o00000000036613b8; alias, 0 drivers
+L_00000000038e1610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e1c70_0 .net8 "VGND", 0 0, L_00000000038e1610; 1 drivers, strength-aware
+L_00000000038e1990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e3cf0_0 .net8 "VNB", 0 0, L_00000000038e1990; 1 drivers, strength-aware
+L_00000000038e1a00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e2c10_0 .net8 "VPB", 0 0, L_00000000038e1a00; 1 drivers, strength-aware
+L_00000000038e1ed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e3750_0 .net8 "VPWR", 0 0, L_00000000038e1ed0; 1 drivers, strength-aware
+v00000000036e32f0_0 .net "Y", 0 0, L_000000000395ced0; alias, 1 drivers
+v00000000036e3430_0 .net "nor0_out_Y", 0 0, L_000000000395c5a0; 1 drivers
+S_00000000026f86e0 .scope module, "sky130_fd_sc_hd__nor3_4" "sky130_fd_sc_hd__nor3_4" 4 16186;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o0000000003661748 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e5910_0 .net "A", 0 0, o0000000003661748; 0 drivers
+o0000000003661778 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e5d70_0 .net "B", 0 0, o0000000003661778; 0 drivers
+o00000000036617a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e5230_0 .net "C", 0 0, o00000000036617a8; 0 drivers
+L_00000000038e0730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e52d0_0 .net8 "VGND", 0 0, L_00000000038e0730; 1 drivers, strength-aware
+L_00000000038e0810 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e5730_0 .net8 "VNB", 0 0, L_00000000038e0810; 1 drivers, strength-aware
+L_00000000038e07a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e5e10_0 .net8 "VPB", 0 0, L_00000000038e07a0; 1 drivers, strength-aware
+L_00000000038e1c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e61d0_0 .net8 "VPWR", 0 0, L_00000000038e1c30; 1 drivers, strength-aware
+v00000000036e43d0_0 .net "Y", 0 0, L_000000000395d090; 1 drivers
+S_00000000036ae980 .scope module, "base" "sky130_fd_sc_hd__nor3" 4 16204, 4 16616 1, S_00000000026f86e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000395d330 .functor NOR 1, o00000000036617a8, o0000000003661748, o0000000003661778, C4<0>;
+L_000000000395d090 .functor BUF 1, L_000000000395d330, C4<0>, C4<0>, C4<0>;
+v00000000036e6130_0 .net "A", 0 0, o0000000003661748; alias, 0 drivers
+v00000000036e46f0_0 .net "B", 0 0, o0000000003661778; alias, 0 drivers
+v00000000036e5690_0 .net "C", 0 0, o00000000036617a8; alias, 0 drivers
+L_00000000038e0ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e4290_0 .net8 "VGND", 0 0, L_00000000038e0ab0; 1 drivers, strength-aware
+L_00000000038e1140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e41f0_0 .net8 "VNB", 0 0, L_00000000038e1140; 1 drivers, strength-aware
+L_00000000038e13e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e63b0_0 .net8 "VPB", 0 0, L_00000000038e13e0; 1 drivers, strength-aware
+L_00000000038e09d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e4a10_0 .net8 "VPWR", 0 0, L_00000000038e09d0; 1 drivers, strength-aware
+v00000000036e55f0_0 .net "Y", 0 0, L_000000000395d090; alias, 1 drivers
+v00000000036e4330_0 .net "nor0_out_Y", 0 0, L_000000000395d330; 1 drivers
+S_00000000026f9ee0 .scope module, "sky130_fd_sc_hd__nor3b_1" "sky130_fd_sc_hd__nor3b_1" 4 1442;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+o0000000003661b38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e4150_0 .net "A", 0 0, o0000000003661b38; 0 drivers
+o0000000003661b68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e5410_0 .net "B", 0 0, o0000000003661b68; 0 drivers
+o0000000003661b98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e45b0_0 .net "C_N", 0 0, o0000000003661b98; 0 drivers
+L_00000000038e14c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e4970_0 .net8 "VGND", 0 0, L_00000000038e14c0; 1 drivers, strength-aware
+L_00000000038e1450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e5eb0_0 .net8 "VNB", 0 0, L_00000000038e1450; 1 drivers, strength-aware
+L_00000000038e0a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e4470_0 .net8 "VPB", 0 0, L_00000000038e0a40; 1 drivers, strength-aware
+L_00000000038e1f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e5b90_0 .net8 "VPWR", 0 0, L_00000000038e1f40; 1 drivers, strength-aware
+v00000000036e4790_0 .net "Y", 0 0, L_000000000395da30; 1 drivers
+S_00000000036b0900 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1460, 4 1322 1, S_00000000026f9ee0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_000000000395c920 .functor NOR 1, o0000000003661b38, o0000000003661b68, C4<0>, C4<0>;
+L_000000000395cf40 .functor AND 1, o0000000003661b98, L_000000000395c920, C4<1>, C4<1>;
+L_000000000395da30 .functor BUF 1, L_000000000395cf40, C4<0>, C4<0>, C4<0>;
+v00000000036e5050_0 .net "A", 0 0, o0000000003661b38; alias, 0 drivers
+v00000000036e50f0_0 .net "B", 0 0, o0000000003661b68; alias, 0 drivers
+v00000000036e4510_0 .net "C_N", 0 0, o0000000003661b98; alias, 0 drivers
+L_00000000038e0b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e5190_0 .net8 "VGND", 0 0, L_00000000038e0b20; 1 drivers, strength-aware
+L_00000000038e0c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e4fb0_0 .net8 "VNB", 0 0, L_00000000038e0c70; 1 drivers, strength-aware
+L_00000000038e0b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e5ff0_0 .net8 "VPB", 0 0, L_00000000038e0b90; 1 drivers, strength-aware
+L_00000000038e1060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e5370_0 .net8 "VPWR", 0 0, L_00000000038e1060; 1 drivers, strength-aware
+v00000000036e4650_0 .net "Y", 0 0, L_000000000395da30; alias, 1 drivers
+v00000000036e5a50_0 .net "and0_out_Y", 0 0, L_000000000395cf40; 1 drivers
+v00000000036e6270_0 .net "nor0_out", 0 0, L_000000000395c920; 1 drivers
+S_00000000026fbe60 .scope module, "sky130_fd_sc_hd__nor3b_2" "sky130_fd_sc_hd__nor3b_2" 4 1556;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+o0000000003661f58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e5cd0_0 .net "A", 0 0, o0000000003661f58; 0 drivers
+o0000000003661f88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e6090_0 .net "B", 0 0, o0000000003661f88; 0 drivers
+o0000000003661fb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e4b50_0 .net "C_N", 0 0, o0000000003661fb8; 0 drivers
+L_00000000038e1ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e4bf0_0 .net8 "VGND", 0 0, L_00000000038e1ca0; 1 drivers, strength-aware
+L_00000000038e0f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e6310_0 .net8 "VNB", 0 0, L_00000000038e0f10; 1 drivers, strength-aware
+L_00000000038e1d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e6450_0 .net8 "VPB", 0 0, L_00000000038e1d10; 1 drivers, strength-aware
+L_00000000038e2020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e4c90_0 .net8 "VPWR", 0 0, L_00000000038e2020; 1 drivers, strength-aware
+v00000000036e6590_0 .net "Y", 0 0, L_000000000395dcd0; 1 drivers
+S_00000000036b0c00 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1574, 4 1322 1, S_00000000026fbe60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_000000000395c990 .functor NOR 1, o0000000003661f58, o0000000003661f88, C4<0>, C4<0>;
+L_000000000395ca00 .functor AND 1, o0000000003661fb8, L_000000000395c990, C4<1>, C4<1>;
+L_000000000395dcd0 .functor BUF 1, L_000000000395ca00, C4<0>, C4<0>, C4<0>;
+v00000000036e5af0_0 .net "A", 0 0, o0000000003661f58; alias, 0 drivers
+v00000000036e5f50_0 .net "B", 0 0, o0000000003661f88; alias, 0 drivers
+v00000000036e54b0_0 .net "C_N", 0 0, o0000000003661fb8; alias, 0 drivers
+L_00000000038e2090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e4830_0 .net8 "VGND", 0 0, L_00000000038e2090; 1 drivers, strength-aware
+L_00000000038e0500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e48d0_0 .net8 "VNB", 0 0, L_00000000038e0500; 1 drivers, strength-aware
+L_00000000038e0c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e64f0_0 .net8 "VPB", 0 0, L_00000000038e0c00; 1 drivers, strength-aware
+L_00000000038e0570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e59b0_0 .net8 "VPWR", 0 0, L_00000000038e0570; 1 drivers, strength-aware
+v00000000036e5550_0 .net "Y", 0 0, L_000000000395dcd0; alias, 1 drivers
+v00000000036e5c30_0 .net "and0_out_Y", 0 0, L_000000000395ca00; 1 drivers
+v00000000036e4ab0_0 .net "nor0_out", 0 0, L_000000000395c990; 1 drivers
+S_00000000026f9a60 .scope module, "sky130_fd_sc_hd__nor3b_4" "sky130_fd_sc_hd__nor3b_4" 4 1670;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+o0000000003662378 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e4f10_0 .net "A", 0 0, o0000000003662378; 0 drivers
+o00000000036623a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e7210_0 .net "B", 0 0, o00000000036623a8; 0 drivers
+o00000000036623d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8c50_0 .net "C_N", 0 0, o00000000036623d8; 0 drivers
+L_00000000038e0ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e6a90_0 .net8 "VGND", 0 0, L_00000000038e0ce0; 1 drivers, strength-aware
+L_00000000038e05e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7a30_0 .net8 "VNB", 0 0, L_00000000038e05e0; 1 drivers, strength-aware
+L_00000000038e0650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e7ad0_0 .net8 "VPB", 0 0, L_00000000038e0650; 1 drivers, strength-aware
+L_00000000038e0d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e7f30_0 .net8 "VPWR", 0 0, L_00000000038e0d50; 1 drivers, strength-aware
+v00000000036e8250_0 .net "Y", 0 0, L_000000000395c680; 1 drivers
+S_00000000036b0d80 .scope module, "base" "sky130_fd_sc_hd__nor3b" 4 1688, 4 1322 1, S_00000000026f9a60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_000000000395cca0 .functor NOR 1, o0000000003662378, o00000000036623a8, C4<0>, C4<0>;
+L_000000000395d800 .functor AND 1, o00000000036623d8, L_000000000395cca0, C4<1>, C4<1>;
+L_000000000395c680 .functor BUF 1, L_000000000395d800, C4<0>, C4<0>, C4<0>;
+v00000000036e4d30_0 .net "A", 0 0, o0000000003662378; alias, 0 drivers
+v00000000036e57d0_0 .net "B", 0 0, o00000000036623a8; alias, 0 drivers
+v00000000036e4dd0_0 .net "C_N", 0 0, o00000000036623d8; alias, 0 drivers
+L_00000000038e0e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e5870_0 .net8 "VGND", 0 0, L_00000000038e0e30; 1 drivers, strength-aware
+L_00000000038e0f80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e6630_0 .net8 "VNB", 0 0, L_00000000038e0f80; 1 drivers, strength-aware
+L_00000000038e11b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e66d0_0 .net8 "VPB", 0 0, L_00000000038e11b0; 1 drivers, strength-aware
+L_00000000038e1530 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e6770_0 .net8 "VPWR", 0 0, L_00000000038e1530; 1 drivers, strength-aware
+v00000000036e6810_0 .net "Y", 0 0, L_000000000395c680; alias, 1 drivers
+v00000000036e68b0_0 .net "and0_out_Y", 0 0, L_000000000395d800; 1 drivers
+v00000000036e4e70_0 .net "nor0_out", 0 0, L_000000000395cca0; 1 drivers
+S_00000000026fa960 .scope module, "sky130_fd_sc_hd__nor4_1" "sky130_fd_sc_hd__nor4_1" 4 75984;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o0000000003662798 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e7530_0 .net "A", 0 0, o0000000003662798; 0 drivers
+o00000000036627c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8d90_0 .net "B", 0 0, o00000000036627c8; 0 drivers
+o00000000036627f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8b10_0 .net "C", 0 0, o00000000036627f8; 0 drivers
+o0000000003662828 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8890_0 .net "D", 0 0, o0000000003662828; 0 drivers
+L_00000000038e1290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7cb0_0 .net8 "VGND", 0 0, L_00000000038e1290; 1 drivers, strength-aware
+L_00000000038e1300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e84d0_0 .net8 "VNB", 0 0, L_00000000038e1300; 1 drivers, strength-aware
+L_00000000038e15a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e69f0_0 .net8 "VPB", 0 0, L_00000000038e15a0; 1 drivers, strength-aware
+L_00000000038e2b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e6950_0 .net8 "VPWR", 0 0, L_00000000038e2b80; 1 drivers, strength-aware
+v00000000036e8390_0 .net "Y", 0 0, L_000000000395df70; 1 drivers
+S_00000000036b0f00 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 76004, 4 76309 1, S_00000000026fa960;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395cb50 .functor NOR 1, o0000000003662798, o00000000036627c8, o00000000036627f8, o0000000003662828;
+L_000000000395df70 .functor BUF 1, L_000000000395cb50, C4<0>, C4<0>, C4<0>;
+v00000000036e7990_0 .net "A", 0 0, o0000000003662798; alias, 0 drivers
+v00000000036e6ef0_0 .net "B", 0 0, o00000000036627c8; alias, 0 drivers
+v00000000036e8570_0 .net "C", 0 0, o00000000036627f8; alias, 0 drivers
+v00000000036e7fd0_0 .net "D", 0 0, o0000000003662828; alias, 0 drivers
+L_00000000038e3440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e6d10_0 .net8 "VGND", 0 0, L_00000000038e3440; 1 drivers, strength-aware
+L_00000000038e2170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7850_0 .net8 "VNB", 0 0, L_00000000038e2170; 1 drivers, strength-aware
+L_00000000038e22c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e77b0_0 .net8 "VPB", 0 0, L_00000000038e22c0; 1 drivers, strength-aware
+L_00000000038e3bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e8110_0 .net8 "VPWR", 0 0, L_00000000038e3bb0; 1 drivers, strength-aware
+v00000000036e7490_0 .net "Y", 0 0, L_000000000395df70; alias, 1 drivers
+v00000000036e6e50_0 .net "nor0_out_Y", 0 0, L_000000000395cb50; 1 drivers
+S_00000000026fa060 .scope module, "sky130_fd_sc_hd__nor4_2" "sky130_fd_sc_hd__nor4_2" 4 76432;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o0000000003662c18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e6b30_0 .net "A", 0 0, o0000000003662c18; 0 drivers
+o0000000003662c48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8e30_0 .net "B", 0 0, o0000000003662c48; 0 drivers
+o0000000003662c78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e7d50_0 .net "C", 0 0, o0000000003662c78; 0 drivers
+o0000000003662ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e6db0_0 .net "D", 0 0, o0000000003662ca8; 0 drivers
+L_00000000038e33d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e8610_0 .net8 "VGND", 0 0, L_00000000038e33d0; 1 drivers, strength-aware
+L_00000000038e3600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e8070_0 .net8 "VNB", 0 0, L_00000000038e3600; 1 drivers, strength-aware
+L_00000000038e2480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e8750_0 .net8 "VPB", 0 0, L_00000000038e2480; 1 drivers, strength-aware
+L_00000000038e3050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9010_0 .net8 "VPWR", 0 0, L_00000000038e3050; 1 drivers, strength-aware
+v00000000036e78f0_0 .net "Y", 0 0, L_000000000395cd80; 1 drivers
+S_00000000036b1080 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 76452, 4 76309 1, S_00000000026fa060;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395daa0 .functor NOR 1, o0000000003662c18, o0000000003662c48, o0000000003662c78, o0000000003662ca8;
+L_000000000395cd80 .functor BUF 1, L_000000000395daa0, C4<0>, C4<0>, C4<0>;
+v00000000036e82f0_0 .net "A", 0 0, o0000000003662c18; alias, 0 drivers
+v00000000036e86b0_0 .net "B", 0 0, o0000000003662c48; alias, 0 drivers
+v00000000036e7b70_0 .net "C", 0 0, o0000000003662c78; alias, 0 drivers
+v00000000036e6f90_0 .net "D", 0 0, o0000000003662ca8; alias, 0 drivers
+L_00000000038e28e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7030_0 .net8 "VGND", 0 0, L_00000000038e28e0; 1 drivers, strength-aware
+L_00000000038e2aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e8cf0_0 .net8 "VNB", 0 0, L_00000000038e2aa0; 1 drivers, strength-aware
+L_00000000038e2330 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e81b0_0 .net8 "VPB", 0 0, L_00000000038e2330; 1 drivers, strength-aware
+L_00000000038e3360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e7c10_0 .net8 "VPWR", 0 0, L_00000000038e3360; 1 drivers, strength-aware
+v00000000036e8430_0 .net "Y", 0 0, L_000000000395cd80; alias, 1 drivers
+v00000000036e6c70_0 .net "nor0_out_Y", 0 0, L_000000000395daa0; 1 drivers
+S_00000000026fb3e0 .scope module, "sky130_fd_sc_hd__nor4_4" "sky130_fd_sc_hd__nor4_4" 4 75864;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o0000000003663098 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e8930_0 .net "A", 0 0, o0000000003663098; 0 drivers
+o00000000036630c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e7350_0 .net "B", 0 0, o00000000036630c8; 0 drivers
+o00000000036630f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e89d0_0 .net "C", 0 0, o00000000036630f8; 0 drivers
+o0000000003663128 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e73f0_0 .net "D", 0 0, o0000000003663128; 0 drivers
+L_00000000038e3750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e90b0_0 .net8 "VGND", 0 0, L_00000000038e3750; 1 drivers, strength-aware
+L_00000000038e3c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e8a70_0 .net8 "VNB", 0 0, L_00000000038e3c20; 1 drivers, strength-aware
+L_00000000038e32f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e8bb0_0 .net8 "VPB", 0 0, L_00000000038e32f0; 1 drivers, strength-aware
+L_00000000038e2bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e75d0_0 .net8 "VPWR", 0 0, L_00000000038e2bf0; 1 drivers, strength-aware
+v00000000036e8f70_0 .net "Y", 0 0, L_000000000395db10; 1 drivers
+S_00000000036ae680 .scope module, "base" "sky130_fd_sc_hd__nor4" 4 75884, 4 76309 1, S_00000000026fb3e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_000000000395ca70 .functor NOR 1, o0000000003663098, o00000000036630c8, o00000000036630f8, o0000000003663128;
+L_000000000395db10 .functor BUF 1, L_000000000395ca70, C4<0>, C4<0>, C4<0>;
+v00000000036e7710_0 .net "A", 0 0, o0000000003663098; alias, 0 drivers
+v00000000036e8ed0_0 .net "B", 0 0, o00000000036630c8; alias, 0 drivers
+v00000000036e87f0_0 .net "C", 0 0, o00000000036630f8; alias, 0 drivers
+v00000000036e7df0_0 .net "D", 0 0, o0000000003663128; alias, 0 drivers
+L_00000000038e31a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7e90_0 .net8 "VGND", 0 0, L_00000000038e31a0; 1 drivers, strength-aware
+L_00000000038e3280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e7670_0 .net8 "VNB", 0 0, L_00000000038e3280; 1 drivers, strength-aware
+L_00000000038e2db0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e70d0_0 .net8 "VPB", 0 0, L_00000000038e2db0; 1 drivers, strength-aware
+L_00000000038e2790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e7170_0 .net8 "VPWR", 0 0, L_00000000038e2790; 1 drivers, strength-aware
+v00000000036e6bd0_0 .net "Y", 0 0, L_000000000395db10; alias, 1 drivers
+v00000000036e72b0_0 .net "nor0_out_Y", 0 0, L_000000000395ca70; 1 drivers
+S_00000000026f8fe0 .scope module, "sky130_fd_sc_hd__nor4b_1" "sky130_fd_sc_hd__nor4b_1" 4 92793;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+o0000000003663518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eab90_0 .net "A", 0 0, o0000000003663518; 0 drivers
+o0000000003663548 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e9470_0 .net "B", 0 0, o0000000003663548; 0 drivers
+o0000000003663578 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eb450_0 .net "C", 0 0, o0000000003663578; 0 drivers
+o00000000036635a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e9e70_0 .net "D_N", 0 0, o00000000036635a8; 0 drivers
+L_00000000038e25d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e9290_0 .net8 "VGND", 0 0, L_00000000038e25d0; 1 drivers, strength-aware
+L_00000000038e34b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eb630_0 .net8 "VNB", 0 0, L_00000000038e34b0; 1 drivers, strength-aware
+L_00000000038e3910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9650_0 .net8 "VPB", 0 0, L_00000000038e3910; 1 drivers, strength-aware
+L_00000000038e2f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ea410_0 .net8 "VPWR", 0 0, L_00000000038e2f00; 1 drivers, strength-aware
+v00000000036e9510_0 .net "Y", 0 0, L_000000000395cbc0; 1 drivers
+S_00000000036b1680 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 92813, 4 93114 1, S_00000000026f8fe0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395db80 .functor NOT 1, o00000000036635a8, C4<0>, C4<0>, C4<0>;
+L_000000000395dbf0 .functor NOR 1, o0000000003663518, o0000000003663548, o0000000003663578, L_000000000395db80;
+L_000000000395cbc0 .functor BUF 1, L_000000000395dbf0, C4<0>, C4<0>, C4<0>;
+v00000000036e91f0_0 .net "A", 0 0, o0000000003663518; alias, 0 drivers
+v00000000036e95b0_0 .net "B", 0 0, o0000000003663548; alias, 0 drivers
+v00000000036ea7d0_0 .net "C", 0 0, o0000000003663578; alias, 0 drivers
+v00000000036e9b50_0 .net "D_N", 0 0, o00000000036635a8; alias, 0 drivers
+L_00000000038e24f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e96f0_0 .net8 "VGND", 0 0, L_00000000038e24f0; 1 drivers, strength-aware
+L_00000000038e30c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ea690_0 .net8 "VNB", 0 0, L_00000000038e30c0; 1 drivers, strength-aware
+L_00000000038e2e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9970_0 .net8 "VPB", 0 0, L_00000000038e2e20; 1 drivers, strength-aware
+L_00000000038e23a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ea730_0 .net8 "VPWR", 0 0, L_00000000038e23a0; 1 drivers, strength-aware
+v00000000036eb090_0 .net "Y", 0 0, L_000000000395cbc0; alias, 1 drivers
+v00000000036e93d0_0 .net "nor0_out_Y", 0 0, L_000000000395dbf0; 1 drivers
+v00000000036eaaf0_0 .net "not0_out", 0 0, L_000000000395db80; 1 drivers
+S_00000000026f8260 .scope module, "sky130_fd_sc_hd__nor4b_2" "sky130_fd_sc_hd__nor4b_2" 4 93355;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+o00000000036639c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ea190_0 .net "A", 0 0, o00000000036639c8; 0 drivers
+o00000000036639f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e9330_0 .net "B", 0 0, o00000000036639f8; 0 drivers
+o0000000003663a28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ea050_0 .net "C", 0 0, o0000000003663a28; 0 drivers
+o0000000003663a58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eaeb0_0 .net "D_N", 0 0, o0000000003663a58; 0 drivers
+L_00000000038e2560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ea230_0 .net8 "VGND", 0 0, L_00000000038e2560; 1 drivers, strength-aware
+L_00000000038e3c90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ea2d0_0 .net8 "VNB", 0 0, L_00000000038e3c90; 1 drivers, strength-aware
+L_00000000038e2100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9c90_0 .net8 "VPB", 0 0, L_00000000038e2100; 1 drivers, strength-aware
+L_00000000038e2950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9d30_0 .net8 "VPWR", 0 0, L_00000000038e2950; 1 drivers, strength-aware
+v00000000036eb810_0 .net "Y", 0 0, L_000000000395dc60; 1 drivers
+S_00000000036ae200 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 93375, 4 93114 1, S_00000000026f8260;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395cdf0 .functor NOT 1, o0000000003663a58, C4<0>, C4<0>, C4<0>;
+L_000000000395de20 .functor NOR 1, o00000000036639c8, o00000000036639f8, o0000000003663a28, L_000000000395cdf0;
+L_000000000395dc60 .functor BUF 1, L_000000000395de20, C4<0>, C4<0>, C4<0>;
+v00000000036e9bf0_0 .net "A", 0 0, o00000000036639c8; alias, 0 drivers
+v00000000036ea5f0_0 .net "B", 0 0, o00000000036639f8; alias, 0 drivers
+v00000000036e9790_0 .net "C", 0 0, o0000000003663a28; alias, 0 drivers
+v00000000036ea370_0 .net "D_N", 0 0, o0000000003663a58; alias, 0 drivers
+L_00000000038e37c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e9f10_0 .net8 "VGND", 0 0, L_00000000038e37c0; 1 drivers, strength-aware
+L_00000000038e3210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eb4f0_0 .net8 "VNB", 0 0, L_00000000038e3210; 1 drivers, strength-aware
+L_00000000038e21e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eae10_0 .net8 "VPB", 0 0, L_00000000038e21e0; 1 drivers, strength-aware
+L_00000000038e2a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eb590_0 .net8 "VPWR", 0 0, L_00000000038e2a30; 1 drivers, strength-aware
+v00000000036ea550_0 .net "Y", 0 0, L_000000000395dc60; alias, 1 drivers
+v00000000036ea870_0 .net "nor0_out_Y", 0 0, L_000000000395de20; 1 drivers
+v00000000036e9fb0_0 .net "not0_out", 0 0, L_000000000395cdf0; 1 drivers
+S_00000000026f8560 .scope module, "sky130_fd_sc_hd__nor4b_4" "sky130_fd_sc_hd__nor4b_4" 4 93237;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+o0000000003663e78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036e9ab0_0 .net "A", 0 0, o0000000003663e78; 0 drivers
+o0000000003663ea8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eb770_0 .net "B", 0 0, o0000000003663ea8; 0 drivers
+o0000000003663ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eaa50_0 .net "C", 0 0, o0000000003663ed8; 0 drivers
+o0000000003663f08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ea0f0_0 .net "D_N", 0 0, o0000000003663f08; 0 drivers
+L_00000000038e3520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036e9150_0 .net8 "VGND", 0 0, L_00000000038e3520; 1 drivers, strength-aware
+L_00000000038e2410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ea4b0_0 .net8 "VNB", 0 0, L_00000000038e2410; 1 drivers, strength-aware
+L_00000000038e2e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eac30_0 .net8 "VPB", 0 0, L_00000000038e2e90; 1 drivers, strength-aware
+L_00000000038e2800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ead70_0 .net8 "VPWR", 0 0, L_00000000038e2800; 1 drivers, strength-aware
+v00000000036eaff0_0 .net "Y", 0 0, L_000000000395cae0; 1 drivers
+S_00000000036b1800 .scope module, "base" "sky130_fd_sc_hd__nor4b" 4 93257, 4 93114 1, S_00000000026f8560;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395d870 .functor NOT 1, o0000000003663f08, C4<0>, C4<0>, C4<0>;
+L_000000000395c530 .functor NOR 1, o0000000003663e78, o0000000003663ea8, o0000000003663ed8, L_000000000395d870;
+L_000000000395cae0 .functor BUF 1, L_000000000395c530, C4<0>, C4<0>, C4<0>;
+v00000000036eb8b0_0 .net "A", 0 0, o0000000003663e78; alias, 0 drivers
+v00000000036eaf50_0 .net "B", 0 0, o0000000003663ea8; alias, 0 drivers
+v00000000036ea910_0 .net "C", 0 0, o0000000003663ed8; alias, 0 drivers
+v00000000036e9830_0 .net "D_N", 0 0, o0000000003663f08; alias, 0 drivers
+L_00000000038e3830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eb310_0 .net8 "VGND", 0 0, L_00000000038e3830; 1 drivers, strength-aware
+L_00000000038e26b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eacd0_0 .net8 "VNB", 0 0, L_00000000038e26b0; 1 drivers, strength-aware
+L_00000000038e2f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eb6d0_0 .net8 "VPB", 0 0, L_00000000038e2f70; 1 drivers, strength-aware
+L_00000000038e2b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036e9dd0_0 .net8 "VPWR", 0 0, L_00000000038e2b10; 1 drivers, strength-aware
+v00000000036e98d0_0 .net "Y", 0 0, L_000000000395cae0; alias, 1 drivers
+v00000000036ea9b0_0 .net "nor0_out_Y", 0 0, L_000000000395c530; 1 drivers
+v00000000036e9a10_0 .net "not0_out", 0 0, L_000000000395d870; 1 drivers
+S_00000000026f8860 .scope module, "sky130_fd_sc_hd__nor4bb_1" "sky130_fd_sc_hd__nor4bb_1" 4 26077;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o0000000003664328 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ebf90_0 .net "A", 0 0, o0000000003664328; 0 drivers
+o0000000003664358 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ebef0_0 .net "B", 0 0, o0000000003664358; 0 drivers
+o0000000003664388 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ec530_0 .net "C_N", 0 0, o0000000003664388; 0 drivers
+o00000000036643b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036edf70_0 .net "D_N", 0 0, o00000000036643b8; 0 drivers
+L_00000000038e2250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ebe50_0 .net8 "VGND", 0 0, L_00000000038e2250; 1 drivers, strength-aware
+L_00000000038e2720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ec170_0 .net8 "VNB", 0 0, L_00000000038e2720; 1 drivers, strength-aware
+L_00000000038e2c60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed6b0_0 .net8 "VPB", 0 0, L_00000000038e2c60; 1 drivers, strength-aware
+L_00000000038e2cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed110_0 .net8 "VPWR", 0 0, L_00000000038e2cd0; 1 drivers, strength-aware
+v00000000036ec8f0_0 .net "Y", 0 0, L_000000000395de90; 1 drivers
+S_00000000036b1b00 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 26097, 4 26398 1, S_00000000026f8860;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395ce60 .functor NOR 1, o0000000003664328, o0000000003664358, C4<0>, C4<0>;
+L_000000000395cfb0 .functor AND 1, L_000000000395ce60, o0000000003664388, o00000000036643b8, C4<1>;
+L_000000000395de90 .functor BUF 1, L_000000000395cfb0, C4<0>, C4<0>, C4<0>;
+v00000000036eb130_0 .net "A", 0 0, o0000000003664328; alias, 0 drivers
+v00000000036eb1d0_0 .net "B", 0 0, o0000000003664358; alias, 0 drivers
+v00000000036eb270_0 .net "C_N", 0 0, o0000000003664388; alias, 0 drivers
+v00000000036eb3b0_0 .net "D_N", 0 0, o00000000036643b8; alias, 0 drivers
+L_00000000038e36e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ec850_0 .net8 "VGND", 0 0, L_00000000038e36e0; 1 drivers, strength-aware
+L_00000000038e38a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ebd10_0 .net8 "VNB", 0 0, L_00000000038e38a0; 1 drivers, strength-aware
+L_00000000038e3590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed890_0 .net8 "VPB", 0 0, L_00000000038e3590; 1 drivers, strength-aware
+L_00000000038e2d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ec2b0_0 .net8 "VPWR", 0 0, L_00000000038e2d40; 1 drivers, strength-aware
+v00000000036ed250_0 .net "Y", 0 0, L_000000000395de90; alias, 1 drivers
+v00000000036ec490_0 .net "and0_out_Y", 0 0, L_000000000395cfb0; 1 drivers
+v00000000036ebdb0_0 .net "nor0_out", 0 0, L_000000000395ce60; 1 drivers
+S_00000000026f92e0 .scope module, "sky130_fd_sc_hd__nor4bb_2" "sky130_fd_sc_hd__nor4bb_2" 4 25841;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o00000000036647d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ed7f0_0 .net "A", 0 0, o00000000036647d8; 0 drivers
+o0000000003664808 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ec670_0 .net "B", 0 0, o0000000003664808; 0 drivers
+o0000000003664838 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ec3f0_0 .net "C_N", 0 0, o0000000003664838; 0 drivers
+o0000000003664868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ec710_0 .net "D_N", 0 0, o0000000003664868; 0 drivers
+L_00000000038e3ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eda70_0 .net8 "VGND", 0 0, L_00000000038e3ad0; 1 drivers, strength-aware
+L_00000000038e3980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ebb30_0 .net8 "VNB", 0 0, L_00000000038e3980; 1 drivers, strength-aware
+L_00000000038e2fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed2f0_0 .net8 "VPB", 0 0, L_00000000038e2fe0; 1 drivers, strength-aware
+L_00000000038e3130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036edcf0_0 .net8 "VPWR", 0 0, L_00000000038e3130; 1 drivers, strength-aware
+v00000000036ed430_0 .net "Y", 0 0, L_000000000395d560; 1 drivers
+S_00000000036b1c80 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 25861, 4 26398 1, S_00000000026f92e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395d020 .functor NOR 1, o00000000036647d8, o0000000003664808, C4<0>, C4<0>;
+L_000000000395df00 .functor AND 1, L_000000000395d020, o0000000003664838, o0000000003664868, C4<1>;
+L_000000000395d560 .functor BUF 1, L_000000000395df00, C4<0>, C4<0>, C4<0>;
+v00000000036ec5d0_0 .net "A", 0 0, o00000000036647d8; alias, 0 drivers
+v00000000036ec0d0_0 .net "B", 0 0, o0000000003664808; alias, 0 drivers
+v00000000036ec350_0 .net "C_N", 0 0, o0000000003664838; alias, 0 drivers
+v00000000036eded0_0 .net "D_N", 0 0, o0000000003664868; alias, 0 drivers
+L_00000000038e2870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eb9f0_0 .net8 "VGND", 0 0, L_00000000038e2870; 1 drivers, strength-aware
+L_00000000038e29c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eccb0_0 .net8 "VNB", 0 0, L_00000000038e29c0; 1 drivers, strength-aware
+L_00000000038e39f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ec210_0 .net8 "VPB", 0 0, L_00000000038e39f0; 1 drivers, strength-aware
+L_00000000038e3670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed750_0 .net8 "VPWR", 0 0, L_00000000038e3670; 1 drivers, strength-aware
+v00000000036ed1b0_0 .net "Y", 0 0, L_000000000395d560; alias, 1 drivers
+v00000000036ed390_0 .net "and0_out_Y", 0 0, L_000000000395df00; 1 drivers
+v00000000036eba90_0 .net "nor0_out", 0 0, L_000000000395d020; 1 drivers
+S_00000000026f89e0 .scope module, "sky130_fd_sc_hd__nor4bb_4" "sky130_fd_sc_hd__nor4bb_4" 4 25959;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o0000000003664c88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ecb70_0 .net "A", 0 0, o0000000003664c88; 0 drivers
+o0000000003664cb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eca30_0 .net "B", 0 0, o0000000003664cb8; 0 drivers
+o0000000003664ce8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ecdf0_0 .net "C_N", 0 0, o0000000003664ce8; 0 drivers
+o0000000003664d18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036edd90_0 .net "D_N", 0 0, o0000000003664d18; 0 drivers
+L_00000000038e3a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ecd50_0 .net8 "VGND", 0 0, L_00000000038e3a60; 1 drivers, strength-aware
+L_00000000038e3b40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ece90_0 .net8 "VNB", 0 0, L_00000000038e3b40; 1 drivers, strength-aware
+L_00000000038e2640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ecc10_0 .net8 "VPB", 0 0, L_00000000038e2640; 1 drivers, strength-aware
+L_00000000038e4da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ecf30_0 .net8 "VPWR", 0 0, L_00000000038e4da0; 1 drivers, strength-aware
+v00000000036ecfd0_0 .net "Y", 0 0, L_000000000395d170; 1 drivers
+S_00000000036ae500 .scope module, "base" "sky130_fd_sc_hd__nor4bb" 4 25979, 4 26398 1, S_00000000026f89e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_000000000395d100 .functor NOR 1, o0000000003664c88, o0000000003664cb8, C4<0>, C4<0>;
+L_000000000395d5d0 .functor AND 1, L_000000000395d100, o0000000003664ce8, o0000000003664d18, C4<1>;
+L_000000000395d170 .functor BUF 1, L_000000000395d5d0, C4<0>, C4<0>, C4<0>;
+v00000000036ed4d0_0 .net "A", 0 0, o0000000003664c88; alias, 0 drivers
+v00000000036ed570_0 .net "B", 0 0, o0000000003664cb8; alias, 0 drivers
+v00000000036ec030_0 .net "C_N", 0 0, o0000000003664ce8; alias, 0 drivers
+v00000000036ebbd0_0 .net "D_N", 0 0, o0000000003664d18; alias, 0 drivers
+L_00000000038e5200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036edb10_0 .net8 "VGND", 0 0, L_00000000038e5200; 1 drivers, strength-aware
+L_00000000038e4b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ed9d0_0 .net8 "VNB", 0 0, L_00000000038e4b70; 1 drivers, strength-aware
+L_00000000038e4a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ebc70_0 .net8 "VPB", 0 0, L_00000000038e4a20; 1 drivers, strength-aware
+L_00000000038e4ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ed610_0 .net8 "VPWR", 0 0, L_00000000038e4ef0; 1 drivers, strength-aware
+v00000000036ec7b0_0 .net "Y", 0 0, L_000000000395d170; alias, 1 drivers
+v00000000036ec990_0 .net "and0_out_Y", 0 0, L_000000000395d5d0; 1 drivers
+v00000000036ecad0_0 .net "nor0_out", 0 0, L_000000000395d100; 1 drivers
+S_00000000026f8b60 .scope module, "sky130_fd_sc_hd__o2111a_1" "sky130_fd_sc_hd__o2111a_1" 4 5848;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003665138 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ee5b0_0 .net "A1", 0 0, o0000000003665138; 0 drivers
+o0000000003665168 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef870_0 .net "A2", 0 0, o0000000003665168; 0 drivers
+o0000000003665198 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eeb50_0 .net "B1", 0 0, o0000000003665198; 0 drivers
+o00000000036651c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eefb0_0 .net "C1", 0 0, o00000000036651c8; 0 drivers
+o00000000036651f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef690_0 .net "D1", 0 0, o00000000036651f8; 0 drivers
+L_00000000038e4f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee290_0 .net8 "VGND", 0 0, L_00000000038e4f60; 1 drivers, strength-aware
+L_00000000038e5580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee1f0_0 .net8 "VNB", 0 0, L_00000000038e5580; 1 drivers, strength-aware
+L_00000000038e45c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f04f0_0 .net8 "VPB", 0 0, L_00000000038e45c0; 1 drivers, strength-aware
+L_00000000038e4e10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ee3d0_0 .net8 "VPWR", 0 0, L_00000000038e4e10; 1 drivers, strength-aware
+v00000000036ef5f0_0 .net "X", 0 0, L_000000000395dd40; 1 drivers
+S_00000000036aeb00 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 5870, 4 6188 1, S_00000000026f8b60;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395d1e0 .functor OR 1, o0000000003665168, o0000000003665138, C4<0>, C4<0>;
+L_000000000395d250 .functor AND 1, o0000000003665198, o00000000036651c8, L_000000000395d1e0, o00000000036651f8;
+L_000000000395dd40 .functor BUF 1, L_000000000395d250, C4<0>, C4<0>, C4<0>;
+v00000000036ede30_0 .net "A1", 0 0, o0000000003665138; alias, 0 drivers
+v00000000036ed070_0 .net "A2", 0 0, o0000000003665168; alias, 0 drivers
+v00000000036ed930_0 .net "B1", 0 0, o0000000003665198; alias, 0 drivers
+v00000000036edbb0_0 .net "C1", 0 0, o00000000036651c8; alias, 0 drivers
+v00000000036edc50_0 .net "D1", 0 0, o00000000036651f8; alias, 0 drivers
+L_00000000038e4e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee010_0 .net8 "VGND", 0 0, L_00000000038e4e80; 1 drivers, strength-aware
+L_00000000038e3d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee0b0_0 .net8 "VNB", 0 0, L_00000000038e3d00; 1 drivers, strength-aware
+L_00000000038e4630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eb950_0 .net8 "VPB", 0 0, L_00000000038e4630; 1 drivers, strength-aware
+L_00000000038e4fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ef7d0_0 .net8 "VPWR", 0 0, L_00000000038e4fd0; 1 drivers, strength-aware
+v00000000036efa50_0 .net "X", 0 0, L_000000000395dd40; alias, 1 drivers
+v00000000036eef10_0 .net "and0_out_X", 0 0, L_000000000395d250; 1 drivers
+v00000000036eff50_0 .net "or0_out", 0 0, L_000000000395d1e0; 1 drivers
+S_00000000026fa360 .scope module, "sky130_fd_sc_hd__o2111a_2" "sky130_fd_sc_hd__o2111a_2" 4 5722;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003665678 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eeab0_0 .net "A1", 0 0, o0000000003665678; 0 drivers
+o00000000036656a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef910_0 .net "A2", 0 0, o00000000036656a8; 0 drivers
+o00000000036656d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef2d0_0 .net "B1", 0 0, o00000000036656d8; 0 drivers
+o0000000003665708 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036eebf0_0 .net "C1", 0 0, o0000000003665708; 0 drivers
+o0000000003665738 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036efe10_0 .net "D1", 0 0, o0000000003665738; 0 drivers
+L_00000000038e3fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eed30_0 .net8 "VGND", 0 0, L_00000000038e3fa0; 1 drivers, strength-aware
+L_00000000038e4a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036eedd0_0 .net8 "VNB", 0 0, L_00000000038e4a90; 1 drivers, strength-aware
+L_00000000038e4390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ee790_0 .net8 "VPB", 0 0, L_00000000038e4390; 1 drivers, strength-aware
+L_00000000038e53c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ee150_0 .net8 "VPWR", 0 0, L_00000000038e53c0; 1 drivers, strength-aware
+v00000000036ef0f0_0 .net "X", 0 0, L_000000000395e0c0; 1 drivers
+S_00000000036aec80 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 5744, 4 6188 1, S_00000000026fa360;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395dfe0 .functor OR 1, o00000000036656a8, o0000000003665678, C4<0>, C4<0>;
+L_000000000395e050 .functor AND 1, o00000000036656d8, o0000000003665708, L_000000000395dfe0, o0000000003665738;
+L_000000000395e0c0 .functor BUF 1, L_000000000395e050, C4<0>, C4<0>, C4<0>;
+v00000000036ee330_0 .net "A1", 0 0, o0000000003665678; alias, 0 drivers
+v00000000036ef230_0 .net "A2", 0 0, o00000000036656a8; alias, 0 drivers
+v00000000036eec90_0 .net "B1", 0 0, o00000000036656d8; alias, 0 drivers
+v00000000036efaf0_0 .net "C1", 0 0, o0000000003665708; alias, 0 drivers
+v00000000036efc30_0 .net "D1", 0 0, o0000000003665738; alias, 0 drivers
+L_00000000038e42b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee470_0 .net8 "VGND", 0 0, L_00000000038e42b0; 1 drivers, strength-aware
+L_00000000038e4be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ef4b0_0 .net8 "VNB", 0 0, L_00000000038e4be0; 1 drivers, strength-aware
+L_00000000038e46a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ee6f0_0 .net8 "VPB", 0 0, L_00000000038e46a0; 1 drivers, strength-aware
+L_00000000038e5890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ef050_0 .net8 "VPWR", 0 0, L_00000000038e5890; 1 drivers, strength-aware
+v00000000036f0130_0 .net "X", 0 0, L_000000000395e0c0; alias, 1 drivers
+v00000000036ef730_0 .net "and0_out_X", 0 0, L_000000000395e050; 1 drivers
+v00000000036efd70_0 .net "or0_out", 0 0, L_000000000395dfe0; 1 drivers
+S_00000000026f8ce0 .scope module, "sky130_fd_sc_hd__o2111a_4" "sky130_fd_sc_hd__o2111a_4" 4 6318;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003665bb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef410_0 .net "A1", 0 0, o0000000003665bb8; 0 drivers
+o0000000003665be8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef9b0_0 .net "A2", 0 0, o0000000003665be8; 0 drivers
+o0000000003665c18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f01d0_0 .net "B1", 0 0, o0000000003665c18; 0 drivers
+o0000000003665c48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036ef370_0 .net "C1", 0 0, o0000000003665c48; 0 drivers
+o0000000003665c78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036efcd0_0 .net "D1", 0 0, o0000000003665c78; 0 drivers
+L_00000000038e4320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036ee970_0 .net8 "VGND", 0 0, L_00000000038e4320; 1 drivers, strength-aware
+L_00000000038e4710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f0630_0 .net8 "VNB", 0 0, L_00000000038e4710; 1 drivers, strength-aware
+L_00000000038e4780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036eea10_0 .net8 "VPB", 0 0, L_00000000038e4780; 1 drivers, strength-aware
+L_00000000038e52e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f0310_0 .net8 "VPWR", 0 0, L_00000000038e52e0; 1 drivers, strength-aware
+v00000000036f03b0_0 .net "X", 0 0, L_000000000395d640; 1 drivers
+S_00000000036a4f00 .scope module, "base" "sky130_fd_sc_hd__o2111a" 4 6340, 4 6188 1, S_00000000026f8ce0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395d410 .functor OR 1, o0000000003665be8, o0000000003665bb8, C4<0>, C4<0>;
+L_000000000395d480 .functor AND 1, o0000000003665c18, o0000000003665c48, L_000000000395d410, o0000000003665c78;
+L_000000000395d640 .functor BUF 1, L_000000000395d480, C4<0>, C4<0>, C4<0>;
+v00000000036ee510_0 .net "A1", 0 0, o0000000003665bb8; alias, 0 drivers
+v00000000036ef190_0 .net "A2", 0 0, o0000000003665be8; alias, 0 drivers
+v00000000036ee650_0 .net "B1", 0 0, o0000000003665c18; alias, 0 drivers
+v00000000036efeb0_0 .net "C1", 0 0, o0000000003665c48; alias, 0 drivers
+v00000000036ef550_0 .net "D1", 0 0, o0000000003665c78; alias, 0 drivers
+L_00000000038e54a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036efff0_0 .net8 "VGND", 0 0, L_00000000038e54a0; 1 drivers, strength-aware
+L_00000000038e50b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f0090_0 .net8 "VNB", 0 0, L_00000000038e50b0; 1 drivers, strength-aware
+L_00000000038e47f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036efb90_0 .net8 "VPB", 0 0, L_00000000038e47f0; 1 drivers, strength-aware
+L_00000000038e56d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036ee8d0_0 .net8 "VPWR", 0 0, L_00000000038e56d0; 1 drivers, strength-aware
+v00000000036eee70_0 .net "X", 0 0, L_000000000395d640; alias, 1 drivers
+v00000000036f0270_0 .net "and0_out_X", 0 0, L_000000000395d480; 1 drivers
+v00000000036ee830_0 .net "or0_out", 0 0, L_000000000395d410; 1 drivers
+S_00000000026f9460 .scope module, "sky130_fd_sc_hd__o2111ai_1" "sky130_fd_sc_hd__o2111ai_1" 4 63007;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o00000000036660f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f2b10_0 .net "A1", 0 0, o00000000036660f8; 0 drivers
+o0000000003666128 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1850_0 .net "A2", 0 0, o0000000003666128; 0 drivers
+o0000000003666158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f2cf0_0 .net "B1", 0 0, o0000000003666158; 0 drivers
+o0000000003666188 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1670_0 .net "C1", 0 0, o0000000003666188; 0 drivers
+o00000000036661b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1710_0 .net "D1", 0 0, o00000000036661b8; 0 drivers
+L_00000000038e5430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f12b0_0 .net8 "VGND", 0 0, L_00000000038e5430; 1 drivers, strength-aware
+L_00000000038e4940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f2e30_0 .net8 "VNB", 0 0, L_00000000038e4940; 1 drivers, strength-aware
+L_00000000038e4860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f0e50_0 .net8 "VPB", 0 0, L_00000000038e4860; 1 drivers, strength-aware
+L_00000000038e4400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f1990_0 .net8 "VPWR", 0 0, L_00000000038e4400; 1 drivers, strength-aware
+v00000000036f1490_0 .net "Y", 0 0, L_000000000395d790; 1 drivers
+S_00000000036a2800 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63029, 4 63599 1, S_00000000026f9460;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395d6b0 .functor OR 1, o0000000003666128, o00000000036660f8, C4<0>, C4<0>;
+L_000000000395d720 .functor NAND 1, o0000000003666188, o0000000003666158, o00000000036661b8, L_000000000395d6b0;
+L_000000000395d790 .functor BUF 1, L_000000000395d720, C4<0>, C4<0>, C4<0>;
+v00000000036f0450_0 .net "A1", 0 0, o00000000036660f8; alias, 0 drivers
+v00000000036f0590_0 .net "A2", 0 0, o0000000003666128; alias, 0 drivers
+v00000000036f06d0_0 .net "B1", 0 0, o0000000003666158; alias, 0 drivers
+v00000000036f0770_0 .net "C1", 0 0, o0000000003666188; alias, 0 drivers
+v00000000036f0810_0 .net "D1", 0 0, o00000000036661b8; alias, 0 drivers
+L_00000000038e44e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f08b0_0 .net8 "VGND", 0 0, L_00000000038e44e0; 1 drivers, strength-aware
+L_00000000038e5510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f22f0_0 .net8 "VNB", 0 0, L_00000000038e5510; 1 drivers, strength-aware
+L_00000000038e4c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f27f0_0 .net8 "VPB", 0 0, L_00000000038e4c50; 1 drivers, strength-aware
+L_00000000038e5040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f1210_0 .net8 "VPWR", 0 0, L_00000000038e5040; 1 drivers, strength-aware
+v00000000036f2c50_0 .net "Y", 0 0, L_000000000395d790; alias, 1 drivers
+v00000000036f2bb0_0 .net "nand0_out_Y", 0 0, L_000000000395d720; 1 drivers
+v00000000036f1ad0_0 .net "or0_out", 0 0, L_000000000395d6b0; 1 drivers
+S_00000000026f95e0 .scope module, "sky130_fd_sc_hd__o2111ai_2" "sky130_fd_sc_hd__o2111ai_2" 4 63133;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003666638 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f13f0_0 .net "A1", 0 0, o0000000003666638; 0 drivers
+o0000000003666668 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f0a90_0 .net "A2", 0 0, o0000000003666668; 0 drivers
+o0000000003666698 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f0db0_0 .net "B1", 0 0, o0000000003666698; 0 drivers
+o00000000036666c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1c10_0 .net "C1", 0 0, o00000000036666c8; 0 drivers
+o00000000036666f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1cb0_0 .net "D1", 0 0, o00000000036666f8; 0 drivers
+L_00000000038e4cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f24d0_0 .net8 "VGND", 0 0, L_00000000038e4cc0; 1 drivers, strength-aware
+L_00000000038e4470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f2610_0 .net8 "VNB", 0 0, L_00000000038e4470; 1 drivers, strength-aware
+L_00000000038e5120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f2930_0 .net8 "VPB", 0 0, L_00000000038e5120; 1 drivers, strength-aware
+L_00000000038e5270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f0ef0_0 .net8 "VPWR", 0 0, L_00000000038e5270; 1 drivers, strength-aware
+v00000000036f1fd0_0 .net "Y", 0 0, L_000000000395e6e0; 1 drivers
+S_00000000036a3100 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63155, 4 63599 1, S_00000000026f95e0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395fcc0 .functor OR 1, o0000000003666668, o0000000003666638, C4<0>, C4<0>;
+L_000000000395e7c0 .functor NAND 1, o00000000036666c8, o0000000003666698, o00000000036666f8, L_000000000395fcc0;
+L_000000000395e6e0 .functor BUF 1, L_000000000395e7c0, C4<0>, C4<0>, C4<0>;
+v00000000036f0c70_0 .net "A1", 0 0, o0000000003666638; alias, 0 drivers
+v00000000036f1b70_0 .net "A2", 0 0, o0000000003666668; alias, 0 drivers
+v00000000036f0950_0 .net "B1", 0 0, o0000000003666698; alias, 0 drivers
+v00000000036f2d90_0 .net "C1", 0 0, o00000000036666c8; alias, 0 drivers
+v00000000036f1350_0 .net "D1", 0 0, o00000000036666f8; alias, 0 drivers
+L_00000000038e3d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f17b0_0 .net8 "VGND", 0 0, L_00000000038e3d70; 1 drivers, strength-aware
+L_00000000038e3ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f1df0_0 .net8 "VNB", 0 0, L_00000000038e3ec0; 1 drivers, strength-aware
+L_00000000038e57b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f1170_0 .net8 "VPB", 0 0, L_00000000038e57b0; 1 drivers, strength-aware
+L_00000000038e5190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f1e90_0 .net8 "VPWR", 0 0, L_00000000038e5190; 1 drivers, strength-aware
+v00000000036f2ed0_0 .net "Y", 0 0, L_000000000395e6e0; alias, 1 drivers
+v00000000036f0d10_0 .net "nand0_out_Y", 0 0, L_000000000395e7c0; 1 drivers
+v00000000036f09f0_0 .net "or0_out", 0 0, L_000000000395fcc0; 1 drivers
+S_00000000027d5c20 .scope module, "sky130_fd_sc_hd__o2111ai_4" "sky130_fd_sc_hd__o2111ai_4" 4 63259;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+o0000000003666b78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f1f30_0 .net "A1", 0 0, o0000000003666b78; 0 drivers
+o0000000003666ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f2070_0 .net "A2", 0 0, o0000000003666ba8; 0 drivers
+o0000000003666bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f2110_0 .net "B1", 0 0, o0000000003666bd8; 0 drivers
+o0000000003666c08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f21b0_0 .net "C1", 0 0, o0000000003666c08; 0 drivers
+o0000000003666c38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000036f2250_0 .net "D1", 0 0, o0000000003666c38; 0 drivers
+L_00000000038e5350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f0bd0_0 .net8 "VGND", 0 0, L_00000000038e5350; 1 drivers, strength-aware
+L_00000000038e4080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f2390_0 .net8 "VNB", 0 0, L_00000000038e4080; 1 drivers, strength-aware
+L_00000000038e4d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f2750_0 .net8 "VPB", 0 0, L_00000000038e4d30; 1 drivers, strength-aware
+L_00000000038e4550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f10d0_0 .net8 "VPWR", 0 0, L_00000000038e4550; 1 drivers, strength-aware
+v00000000036f2430_0 .net "Y", 0 0, L_000000000395ead0; 1 drivers
+S_00000000036a4480 .scope module, "base" "sky130_fd_sc_hd__o2111ai" 4 63281, 4 63599 1, S_00000000027d5c20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+ .port_info 5 /INPUT 1 "D1"
+L_000000000395e830 .functor OR 1, o0000000003666ba8, o0000000003666b78, C4<0>, C4<0>;
+L_000000000395f0f0 .functor NAND 1, o0000000003666c08, o0000000003666bd8, o0000000003666c38, L_000000000395e830;
+L_000000000395ead0 .functor BUF 1, L_000000000395f0f0, C4<0>, C4<0>, C4<0>;
+v00000000036f18f0_0 .net "A1", 0 0, o0000000003666b78; alias, 0 drivers
+v00000000036f2890_0 .net "A2", 0 0, o0000000003666ba8; alias, 0 drivers
+v00000000036f1a30_0 .net "B1", 0 0, o0000000003666bd8; alias, 0 drivers
+v00000000036f29d0_0 .net "C1", 0 0, o0000000003666c08; alias, 0 drivers
+v00000000036f1d50_0 .net "D1", 0 0, o0000000003666c38; alias, 0 drivers
+L_00000000038e48d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f1530_0 .net8 "VGND", 0 0, L_00000000038e48d0; 1 drivers, strength-aware
+L_00000000038e3f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000036f26b0_0 .net8 "VNB", 0 0, L_00000000038e3f30; 1 drivers, strength-aware
+L_00000000038e55f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f2a70_0 .net8 "VPB", 0 0, L_00000000038e55f0; 1 drivers, strength-aware
+L_00000000038e5660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000036f15d0_0 .net8 "VPWR", 0 0, L_00000000038e5660; 1 drivers, strength-aware
+v00000000036f1030_0 .net "Y", 0 0, L_000000000395ead0; alias, 1 drivers
+v00000000036f0b30_0 .net "nand0_out_Y", 0 0, L_000000000395f0f0; 1 drivers
+v00000000036f0f90_0 .net "or0_out", 0 0, L_000000000395e830; 1 drivers
+S_00000000027d4ea0 .scope module, "sky130_fd_sc_hd__o211a_1" "sky130_fd_sc_hd__o211a_1" 4 77584;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o00000000036670b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003716270_0 .net "A1", 0 0, o00000000036670b8; 0 drivers
+o00000000036670e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717210_0 .net "A2", 0 0, o00000000036670e8; 0 drivers
+o0000000003667118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003716c70_0 .net "B1", 0 0, o0000000003667118; 0 drivers
+o0000000003667148 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717ad0_0 .net "C1", 0 0, o0000000003667148; 0 drivers
+L_00000000038e5820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003717c10_0 .net8 "VGND", 0 0, L_00000000038e5820; 1 drivers, strength-aware
+L_00000000038e5740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003716310_0 .net8 "VNB", 0 0, L_00000000038e5740; 1 drivers, strength-aware
+L_00000000038e49b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003717490_0 .net8 "VPB", 0 0, L_00000000038e49b0; 1 drivers, strength-aware
+L_00000000038e3de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037166d0_0 .net8 "VPWR", 0 0, L_00000000038e3de0; 1 drivers, strength-aware
+v0000000003716ef0_0 .net "X", 0 0, L_000000000395f780; 1 drivers
+S_00000000036a5080 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77604, 4 77459 1, S_00000000027d4ea0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395f390 .functor OR 1, o00000000036670e8, o00000000036670b8, C4<0>, C4<0>;
+L_000000000395f5c0 .functor AND 1, L_000000000395f390, o0000000003667118, o0000000003667148, C4<1>;
+L_000000000395f780 .functor BUF 1, L_000000000395f5c0, C4<0>, C4<0>, C4<0>;
+v00000000036f2570_0 .net "A1", 0 0, o00000000036670b8; alias, 0 drivers
+v0000000003716770_0 .net "A2", 0 0, o00000000036670e8; alias, 0 drivers
+v0000000003717f30_0 .net "B1", 0 0, o0000000003667118; alias, 0 drivers
+v0000000003716950_0 .net "C1", 0 0, o0000000003667148; alias, 0 drivers
+L_00000000038e3e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003717710_0 .net8 "VGND", 0 0, L_00000000038e3e50; 1 drivers, strength-aware
+L_00000000038e4b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037184d0_0 .net8 "VNB", 0 0, L_00000000038e4b00; 1 drivers, strength-aware
+L_00000000038e4010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037163b0_0 .net8 "VPB", 0 0, L_00000000038e4010; 1 drivers, strength-aware
+L_00000000038e41d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037187f0_0 .net8 "VPWR", 0 0, L_00000000038e41d0; 1 drivers, strength-aware
+v0000000003718750_0 .net "X", 0 0, L_000000000395f780; alias, 1 drivers
+v0000000003717a30_0 .net "and0_out_X", 0 0, L_000000000395f5c0; 1 drivers
+v00000000037175d0_0 .net "or0_out", 0 0, L_000000000395f390; 1 drivers
+S_00000000027d5da0 .scope module, "sky130_fd_sc_hd__o211a_2" "sky130_fd_sc_hd__o211a_2" 4 77704;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003667568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717e90_0 .net "A1", 0 0, o0000000003667568; 0 drivers
+o0000000003667598 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003716130_0 .net "A2", 0 0, o0000000003667598; 0 drivers
+o00000000036675c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717170_0 .net "B1", 0 0, o00000000036675c8; 0 drivers
+o00000000036675f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003718610_0 .net "C1", 0 0, o00000000036675f8; 0 drivers
+L_00000000038e40f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003717030_0 .net8 "VGND", 0 0, L_00000000038e40f0; 1 drivers, strength-aware
+L_00000000038e4160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037172b0_0 .net8 "VNB", 0 0, L_00000000038e4160; 1 drivers, strength-aware
+L_00000000038e4240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003716450_0 .net8 "VPB", 0 0, L_00000000038e4240; 1 drivers, strength-aware
+L_00000000038e5c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003717350_0 .net8 "VPWR", 0 0, L_00000000038e5c80; 1 drivers, strength-aware
+v00000000037168b0_0 .net "X", 0 0, L_000000000395fbe0; 1 drivers
+S_00000000036a4600 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77724, 4 77459 1, S_00000000027d5da0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395fa20 .functor OR 1, o0000000003667598, o0000000003667568, C4<0>, C4<0>;
+L_000000000395f7f0 .functor AND 1, L_000000000395fa20, o00000000036675c8, o00000000036675f8, C4<1>;
+L_000000000395fbe0 .functor BUF 1, L_000000000395f7f0, C4<0>, C4<0>, C4<0>;
+v0000000003718070_0 .net "A1", 0 0, o0000000003667568; alias, 0 drivers
+v0000000003716f90_0 .net "A2", 0 0, o0000000003667598; alias, 0 drivers
+v0000000003717fd0_0 .net "B1", 0 0, o00000000036675c8; alias, 0 drivers
+v0000000003716590_0 .net "C1", 0 0, o00000000036675f8; alias, 0 drivers
+L_00000000038e6150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003716bd0_0 .net8 "VGND", 0 0, L_00000000038e6150; 1 drivers, strength-aware
+L_00000000038e6380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037178f0_0 .net8 "VNB", 0 0, L_00000000038e6380; 1 drivers, strength-aware
+L_00000000038e6c40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003716d10_0 .net8 "VPB", 0 0, L_00000000038e6c40; 1 drivers, strength-aware
+L_00000000038e6a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003716db0_0 .net8 "VPWR", 0 0, L_00000000038e6a80; 1 drivers, strength-aware
+v0000000003716810_0 .net "X", 0 0, L_000000000395fbe0; alias, 1 drivers
+v0000000003716e50_0 .net "and0_out_X", 0 0, L_000000000395f7f0; 1 drivers
+v00000000037170d0_0 .net "or0_out", 0 0, L_000000000395fa20; 1 drivers
+S_00000000027d6520 .scope module, "sky130_fd_sc_hd__o211a_4" "sky130_fd_sc_hd__o211a_4" 4 77824;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003667a18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717cb0_0 .net "A1", 0 0, o0000000003667a18; 0 drivers
+o0000000003667a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717850_0 .net "A2", 0 0, o0000000003667a48; 0 drivers
+o0000000003667a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003716b30_0 .net "B1", 0 0, o0000000003667a78; 0 drivers
+o0000000003667aa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003717d50_0 .net "C1", 0 0, o0000000003667aa8; 0 drivers
+L_00000000038e5cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037169f0_0 .net8 "VGND", 0 0, L_00000000038e5cf0; 1 drivers, strength-aware
+L_00000000038e6e70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003718110_0 .net8 "VNB", 0 0, L_00000000038e6e70; 1 drivers, strength-aware
+L_00000000038e5d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037181b0_0 .net8 "VPB", 0 0, L_00000000038e5d60; 1 drivers, strength-aware
+L_00000000038e6b60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003718250_0 .net8 "VPWR", 0 0, L_00000000038e6b60; 1 drivers, strength-aware
+v0000000003718570_0 .net "X", 0 0, L_000000000395e3d0; 1 drivers
+S_00000000036a2200 .scope module, "base" "sky130_fd_sc_hd__o211a" 4 77844, 4 77459 1, S_00000000027d6520;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395e750 .functor OR 1, o0000000003667a48, o0000000003667a18, C4<0>, C4<0>;
+L_000000000395e910 .functor AND 1, L_000000000395e750, o0000000003667a78, o0000000003667aa8, C4<1>;
+L_000000000395e3d0 .functor BUF 1, L_000000000395e910, C4<0>, C4<0>, C4<0>;
+v00000000037173f0_0 .net "A1", 0 0, o0000000003667a18; alias, 0 drivers
+v0000000003717530_0 .net "A2", 0 0, o0000000003667a48; alias, 0 drivers
+v0000000003717990_0 .net "B1", 0 0, o0000000003667a78; alias, 0 drivers
+v0000000003717df0_0 .net "C1", 0 0, o0000000003667aa8; alias, 0 drivers
+L_00000000038e6bd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003718430_0 .net8 "VGND", 0 0, L_00000000038e6bd0; 1 drivers, strength-aware
+L_00000000038e6ee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003717670_0 .net8 "VNB", 0 0, L_00000000038e6ee0; 1 drivers, strength-aware
+L_00000000038e6af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037161d0_0 .net8 "VPB", 0 0, L_00000000038e6af0; 1 drivers, strength-aware
+L_00000000038e64d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003717b70_0 .net8 "VPWR", 0 0, L_00000000038e64d0; 1 drivers, strength-aware
+v0000000003716a90_0 .net "X", 0 0, L_000000000395e3d0; alias, 1 drivers
+v00000000037177b0_0 .net "and0_out_X", 0 0, L_000000000395e910; 1 drivers
+v00000000037164f0_0 .net "or0_out", 0 0, L_000000000395e750; 1 drivers
+S_00000000027d6b20 .scope module, "sky130_fd_sc_hd__o211ai_1" "sky130_fd_sc_hd__o211ai_1" 4 77944;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003667ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371ac30_0 .net "A1", 0 0, o0000000003667ec8; 0 drivers
+o0000000003667ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003719fb0_0 .net "A2", 0 0, o0000000003667ef8; 0 drivers
+o0000000003667f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003718930_0 .net "B1", 0 0, o0000000003667f28; 0 drivers
+o0000000003667f58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371ad70_0 .net "C1", 0 0, o0000000003667f58; 0 drivers
+L_00000000038e71f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371a410_0 .net8 "VGND", 0 0, L_00000000038e71f0; 1 drivers, strength-aware
+L_00000000038e5dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371a0f0_0 .net8 "VNB", 0 0, L_00000000038e5dd0; 1 drivers, strength-aware
+L_00000000038e63f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719290_0 .net8 "VPB", 0 0, L_00000000038e63f0; 1 drivers, strength-aware
+L_00000000038e6d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719b50_0 .net8 "VPWR", 0 0, L_00000000038e6d20; 1 drivers, strength-aware
+v00000000037189d0_0 .net "Y", 0 0, L_000000000395fb70; 1 drivers
+S_00000000036a5380 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 77964, 4 78275 1, S_00000000027d6b20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395eec0 .functor OR 1, o0000000003667ef8, o0000000003667ec8, C4<0>, C4<0>;
+L_000000000395e8a0 .functor NAND 1, o0000000003667f58, L_000000000395eec0, o0000000003667f28, C4<1>;
+L_000000000395fb70 .functor BUF 1, L_000000000395e8a0, C4<0>, C4<0>, C4<0>;
+v00000000037182f0_0 .net "A1", 0 0, o0000000003667ec8; alias, 0 drivers
+v0000000003716630_0 .net "A2", 0 0, o0000000003667ef8; alias, 0 drivers
+v0000000003718390_0 .net "B1", 0 0, o0000000003667f28; alias, 0 drivers
+v00000000037186b0_0 .net "C1", 0 0, o0000000003667f58; alias, 0 drivers
+L_00000000038e5ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003718890_0 .net8 "VGND", 0 0, L_00000000038e5ac0; 1 drivers, strength-aware
+L_00000000038e73b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371a2d0_0 .net8 "VNB", 0 0, L_00000000038e73b0; 1 drivers, strength-aware
+L_00000000038e7180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037190b0_0 .net8 "VPB", 0 0, L_00000000038e7180; 1 drivers, strength-aware
+L_00000000038e6f50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371a370_0 .net8 "VPWR", 0 0, L_00000000038e6f50; 1 drivers, strength-aware
+v0000000003719970_0 .net "Y", 0 0, L_000000000395fb70; alias, 1 drivers
+v0000000003718e30_0 .net "nand0_out_Y", 0 0, L_000000000395e8a0; 1 drivers
+v0000000003718ed0_0 .net "or0_out", 0 0, L_000000000395eec0; 1 drivers
+S_00000000027d5020 .scope module, "sky130_fd_sc_hd__o211ai_2" "sky130_fd_sc_hd__o211ai_2" 4 78520;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003668378 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003719330_0 .net "A1", 0 0, o0000000003668378; 0 drivers
+o00000000036683a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003718bb0_0 .net "A2", 0 0, o00000000036683a8; 0 drivers
+o00000000036683d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003719a10_0 .net "B1", 0 0, o00000000036683d8; 0 drivers
+o0000000003668408 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371acd0_0 .net "C1", 0 0, o0000000003668408; 0 drivers
+L_00000000038e6770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371aeb0_0 .net8 "VGND", 0 0, L_00000000038e6770; 1 drivers, strength-aware
+L_00000000038e6620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003719790_0 .net8 "VNB", 0 0, L_00000000038e6620; 1 drivers, strength-aware
+L_00000000038e6cb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719830_0 .net8 "VPB", 0 0, L_00000000038e6cb0; 1 drivers, strength-aware
+L_00000000038e6d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371a230_0 .net8 "VPWR", 0 0, L_00000000038e6d90; 1 drivers, strength-aware
+v0000000003719ab0_0 .net "Y", 0 0, L_000000000395e130; 1 drivers
+S_00000000036a5980 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 78540, 4 78275 1, S_00000000027d5020;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395e1a0 .functor OR 1, o00000000036683a8, o0000000003668378, C4<0>, C4<0>;
+L_000000000395fc50 .functor NAND 1, o0000000003668408, L_000000000395e1a0, o00000000036683d8, C4<1>;
+L_000000000395e130 .functor BUF 1, L_000000000395fc50, C4<0>, C4<0>, C4<0>;
+v0000000003719150_0 .net "A1", 0 0, o0000000003668378; alias, 0 drivers
+v0000000003719dd0_0 .net "A2", 0 0, o00000000036683a8; alias, 0 drivers
+v00000000037191f0_0 .net "B1", 0 0, o00000000036683d8; alias, 0 drivers
+v00000000037198d0_0 .net "C1", 0 0, o0000000003668408; alias, 0 drivers
+L_00000000038e7260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371a190_0 .net8 "VGND", 0 0, L_00000000038e7260; 1 drivers, strength-aware
+L_00000000038e61c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371a910_0 .net8 "VNB", 0 0, L_00000000038e61c0; 1 drivers, strength-aware
+L_00000000038e6850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719e70_0 .net8 "VPB", 0 0, L_00000000038e6850; 1 drivers, strength-aware
+L_00000000038e7490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371a4b0_0 .net8 "VPWR", 0 0, L_00000000038e7490; 1 drivers, strength-aware
+v000000000371a9b0_0 .net "Y", 0 0, L_000000000395e130; alias, 1 drivers
+v0000000003719d30_0 .net "nand0_out_Y", 0 0, L_000000000395fc50; 1 drivers
+v000000000371ae10_0 .net "or0_out", 0 0, L_000000000395e1a0; 1 drivers
+S_00000000027d5f20 .scope module, "sky130_fd_sc_hd__o211ai_4" "sky130_fd_sc_hd__o211ai_4" 4 78400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+o0000000003668828 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003718c50_0 .net "A1", 0 0, o0000000003668828; 0 drivers
+o0000000003668858 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003719f10_0 .net "A2", 0 0, o0000000003668858; 0 drivers
+o0000000003668888 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371a050_0 .net "B1", 0 0, o0000000003668888; 0 drivers
+o00000000036688b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371a690_0 .net "C1", 0 0, o00000000036688b8; 0 drivers
+L_00000000038e6e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003719510_0 .net8 "VGND", 0 0, L_00000000038e6e00; 1 drivers, strength-aware
+L_00000000038e72d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371af50_0 .net8 "VNB", 0 0, L_00000000038e72d0; 1 drivers, strength-aware
+L_00000000038e5b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371a870_0 .net8 "VPB", 0 0, L_00000000038e5b30; 1 drivers, strength-aware
+L_00000000038e5c10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371aa50_0 .net8 "VPWR", 0 0, L_00000000038e5c10; 1 drivers, strength-aware
+v0000000003719bf0_0 .net "Y", 0 0, L_000000000395e440; 1 drivers
+S_00000000036a5200 .scope module, "base" "sky130_fd_sc_hd__o211ai" 4 78420, 4 78275 1, S_00000000027d5f20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "C1"
+L_000000000395f6a0 .functor OR 1, o0000000003668858, o0000000003668828, C4<0>, C4<0>;
+L_000000000395ef30 .functor NAND 1, o00000000036688b8, L_000000000395f6a0, o0000000003668888, C4<1>;
+L_000000000395e440 .functor BUF 1, L_000000000395ef30, C4<0>, C4<0>, C4<0>;
+v000000000371a550_0 .net "A1", 0 0, o0000000003668828; alias, 0 drivers
+v0000000003719010_0 .net "A2", 0 0, o0000000003668858; alias, 0 drivers
+v0000000003718cf0_0 .net "B1", 0 0, o0000000003668888; alias, 0 drivers
+v000000000371a5f0_0 .net "C1", 0 0, o00000000036688b8; alias, 0 drivers
+L_00000000038e5ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003719c90_0 .net8 "VGND", 0 0, L_00000000038e5ba0; 1 drivers, strength-aware
+L_00000000038e6fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037193d0_0 .net8 "VNB", 0 0, L_00000000038e6fc0; 1 drivers, strength-aware
+L_00000000038e5eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371a730_0 .net8 "VPB", 0 0, L_00000000038e5eb0; 1 drivers, strength-aware
+L_00000000038e6540 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719470_0 .net8 "VPWR", 0 0, L_00000000038e6540; 1 drivers, strength-aware
+v0000000003718f70_0 .net "Y", 0 0, L_000000000395e440; alias, 1 drivers
+v000000000371a7d0_0 .net "nand0_out_Y", 0 0, L_000000000395ef30; 1 drivers
+v000000000371aff0_0 .net "or0_out", 0 0, L_000000000395f6a0; 1 drivers
+S_00000000027d42a0 .scope module, "sky130_fd_sc_hd__o21a_1" "sky130_fd_sc_hd__o21a_1" 4 65062;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003668cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371cd50_0 .net "A1", 0 0, o0000000003668cd8; 0 drivers
+o0000000003668d08 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371bd10_0 .net "A2", 0 0, o0000000003668d08; 0 drivers
+o0000000003668d38 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371c990_0 .net "B1", 0 0, o0000000003668d38; 0 drivers
+L_00000000038e67e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371b130_0 .net8 "VGND", 0 0, L_00000000038e67e0; 1 drivers, strength-aware
+L_00000000038e5e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371d2f0_0 .net8 "VNB", 0 0, L_00000000038e5e40; 1 drivers, strength-aware
+L_00000000038e68c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371d070_0 .net8 "VPB", 0 0, L_00000000038e68c0; 1 drivers, strength-aware
+L_00000000038e6930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371c490_0 .net8 "VPWR", 0 0, L_00000000038e6930; 1 drivers, strength-aware
+v000000000371b950_0 .net "X", 0 0, L_000000000395e280; 1 drivers
+S_00000000036a6d00 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65080, 4 65384 1, S_00000000027d42a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395e360 .functor OR 1, o0000000003668d08, o0000000003668cd8, C4<0>, C4<0>;
+L_000000000395e210 .functor AND 1, L_000000000395e360, o0000000003668d38, C4<1>, C4<1>;
+L_000000000395e280 .functor BUF 1, L_000000000395e210, C4<0>, C4<0>, C4<0>;
+v000000000371aaf0_0 .net "A1", 0 0, o0000000003668cd8; alias, 0 drivers
+v00000000037196f0_0 .net "A2", 0 0, o0000000003668d08; alias, 0 drivers
+v000000000371ab90_0 .net "B1", 0 0, o0000000003668d38; alias, 0 drivers
+L_00000000038e5f20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371b090_0 .net8 "VGND", 0 0, L_00000000038e5f20; 1 drivers, strength-aware
+L_00000000038e7340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037195b0_0 .net8 "VNB", 0 0, L_00000000038e7340; 1 drivers, strength-aware
+L_00000000038e5f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003719650_0 .net8 "VPB", 0 0, L_00000000038e5f90; 1 drivers, strength-aware
+L_00000000038e6070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003718a70_0 .net8 "VPWR", 0 0, L_00000000038e6070; 1 drivers, strength-aware
+v0000000003718b10_0 .net "X", 0 0, L_000000000395e280; alias, 1 drivers
+v0000000003718d90_0 .net "and0_out_X", 0 0, L_000000000395e210; 1 drivers
+v000000000371cfd0_0 .net "or0_out", 0 0, L_000000000395e360; 1 drivers
+S_00000000027d60a0 .scope module, "sky130_fd_sc_hd__o21a_2" "sky130_fd_sc_hd__o21a_2" 4 65618;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o00000000036690f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371c5d0_0 .net "A1", 0 0, o00000000036690f8; 0 drivers
+o0000000003669128 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371b8b0_0 .net "A2", 0 0, o0000000003669128; 0 drivers
+o0000000003669158 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371c0d0_0 .net "B1", 0 0, o0000000003669158; 0 drivers
+L_00000000038e6000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371bef0_0 .net8 "VGND", 0 0, L_00000000038e6000; 1 drivers, strength-aware
+L_00000000038e6460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371d110_0 .net8 "VNB", 0 0, L_00000000038e6460; 1 drivers, strength-aware
+L_00000000038e7030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371cdf0_0 .net8 "VPB", 0 0, L_00000000038e7030; 1 drivers, strength-aware
+L_00000000038e6310 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371d4d0_0 .net8 "VPWR", 0 0, L_00000000038e6310; 1 drivers, strength-aware
+v000000000371c530_0 .net "X", 0 0, L_000000000395f630; 1 drivers
+S_00000000036a5f80 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65636, 4 65384 1, S_00000000027d60a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395ebb0 .functor OR 1, o0000000003669128, o00000000036690f8, C4<0>, C4<0>;
+L_000000000395f2b0 .functor AND 1, L_000000000395ebb0, o0000000003669158, C4<1>, C4<1>;
+L_000000000395f630 .functor BUF 1, L_000000000395f2b0, C4<0>, C4<0>, C4<0>;
+v000000000371ce90_0 .net "A1", 0 0, o00000000036690f8; alias, 0 drivers
+v000000000371be50_0 .net "A2", 0 0, o0000000003669128; alias, 0 drivers
+v000000000371b450_0 .net "B1", 0 0, o0000000003669158; alias, 0 drivers
+L_00000000038e70a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371ba90_0 .net8 "VGND", 0 0, L_00000000038e70a0; 1 drivers, strength-aware
+L_00000000038e7420 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371c350_0 .net8 "VNB", 0 0, L_00000000038e7420; 1 drivers, strength-aware
+L_00000000038e5900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371b4f0_0 .net8 "VPB", 0 0, L_00000000038e5900; 1 drivers, strength-aware
+L_00000000038e5970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371cb70_0 .net8 "VPWR", 0 0, L_00000000038e5970; 1 drivers, strength-aware
+v000000000371d1b0_0 .net "X", 0 0, L_000000000395f630; alias, 1 drivers
+v000000000371b270_0 .net "and0_out_X", 0 0, L_000000000395f2b0; 1 drivers
+v000000000371d7f0_0 .net "or0_out", 0 0, L_000000000395ebb0; 1 drivers
+S_00000000027d69a0 .scope module, "sky130_fd_sc_hd__o21a_4" "sky130_fd_sc_hd__o21a_4" 4 65504;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003669518 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371c850_0 .net "A1", 0 0, o0000000003669518; 0 drivers
+o0000000003669548 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371ca30_0 .net "A2", 0 0, o0000000003669548; 0 drivers
+o0000000003669578 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371b810_0 .net "B1", 0 0, o0000000003669578; 0 drivers
+L_00000000038e60e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371b590_0 .net8 "VGND", 0 0, L_00000000038e60e0; 1 drivers, strength-aware
+L_00000000038e7110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371b630_0 .net8 "VNB", 0 0, L_00000000038e7110; 1 drivers, strength-aware
+L_00000000038e6230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371c670_0 .net8 "VPB", 0 0, L_00000000038e6230; 1 drivers, strength-aware
+L_00000000038e59e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371c710_0 .net8 "VPWR", 0 0, L_00000000038e59e0; 1 drivers, strength-aware
+v000000000371bdb0_0 .net "X", 0 0, L_000000000395e9f0; 1 drivers
+S_00000000036a2e00 .scope module, "base" "sky130_fd_sc_hd__o21a" 4 65522, 4 65384 1, S_00000000027d69a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395e980 .functor OR 1, o0000000003669548, o0000000003669518, C4<0>, C4<0>;
+L_000000000395f860 .functor AND 1, L_000000000395e980, o0000000003669578, C4<1>, C4<1>;
+L_000000000395e9f0 .functor BUF 1, L_000000000395f860, C4<0>, C4<0>, C4<0>;
+v000000000371c170_0 .net "A1", 0 0, o0000000003669518; alias, 0 drivers
+v000000000371b310_0 .net "A2", 0 0, o0000000003669548; alias, 0 drivers
+v000000000371bf90_0 .net "B1", 0 0, o0000000003669578; alias, 0 drivers
+L_00000000038e5a50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371cf30_0 .net8 "VGND", 0 0, L_00000000038e5a50; 1 drivers, strength-aware
+L_00000000038e62a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371c210_0 .net8 "VNB", 0 0, L_00000000038e62a0; 1 drivers, strength-aware
+L_00000000038e65b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371c2b0_0 .net8 "VPB", 0 0, L_00000000038e65b0; 1 drivers, strength-aware
+L_00000000038e6690 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371bbd0_0 .net8 "VPWR", 0 0, L_00000000038e6690; 1 drivers, strength-aware
+v000000000371bb30_0 .net "X", 0 0, L_000000000395e9f0; alias, 1 drivers
+v000000000371d890_0 .net "and0_out_X", 0 0, L_000000000395f860; 1 drivers
+v000000000371c7b0_0 .net "or0_out", 0 0, L_000000000395e980; 1 drivers
+S_00000000027d3e20 .scope module, "sky130_fd_sc_hd__o21ai_0" "sky130_fd_sc_hd__o21ai_0" 4 89973;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003669938 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371cad0_0 .net "A1", 0 0, o0000000003669938; 0 drivers
+o0000000003669968 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371d390_0 .net "A2", 0 0, o0000000003669968; 0 drivers
+o0000000003669998 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371c3f0_0 .net "B1", 0 0, o0000000003669998; 0 drivers
+L_00000000038e6700 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371ccb0_0 .net8 "VGND", 0 0, L_00000000038e6700; 1 drivers, strength-aware
+L_00000000038e69a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371c030_0 .net8 "VNB", 0 0, L_00000000038e69a0; 1 drivers, strength-aware
+L_00000000038e6a10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371d610_0 .net8 "VPB", 0 0, L_00000000038e6a10; 1 drivers, strength-aware
+L_00000000038e7b20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371d6b0_0 .net8 "VPWR", 0 0, L_00000000038e7b20; 1 drivers, strength-aware
+v000000000371d750_0 .net "Y", 0 0, L_000000000395fa90; 1 drivers
+S_00000000036a4300 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89991, 4 89511 1, S_00000000027d3e20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395f710 .functor OR 1, o0000000003669968, o0000000003669938, C4<0>, C4<0>;
+L_000000000395f8d0 .functor NAND 1, o0000000003669998, L_000000000395f710, C4<1>, C4<1>;
+L_000000000395fa90 .functor BUF 1, L_000000000395f8d0, C4<0>, C4<0>, C4<0>;
+v000000000371b3b0_0 .net "A1", 0 0, o0000000003669938; alias, 0 drivers
+v000000000371d250_0 .net "A2", 0 0, o0000000003669968; alias, 0 drivers
+v000000000371b6d0_0 .net "B1", 0 0, o0000000003669998; alias, 0 drivers
+L_00000000038e8300 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371c8f0_0 .net8 "VGND", 0 0, L_00000000038e8300; 1 drivers, strength-aware
+L_00000000038e7880 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371b770_0 .net8 "VNB", 0 0, L_00000000038e7880; 1 drivers, strength-aware
+L_00000000038e84c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371cc10_0 .net8 "VPB", 0 0, L_00000000038e84c0; 1 drivers, strength-aware
+L_00000000038e8220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371bc70_0 .net8 "VPWR", 0 0, L_00000000038e8220; 1 drivers, strength-aware
+v000000000371d570_0 .net "Y", 0 0, L_000000000395fa90; alias, 1 drivers
+v000000000371d430_0 .net "nand0_out_Y", 0 0, L_000000000395f8d0; 1 drivers
+v000000000371b9f0_0 .net "or0_out", 0 0, L_000000000395f710; 1 drivers
+S_00000000027d66a0 .scope module, "sky130_fd_sc_hd__o21ai_1" "sky130_fd_sc_hd__o21ai_1" 4 89745;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o0000000003669d58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371f690_0 .net "A1", 0 0, o0000000003669d58; 0 drivers
+o0000000003669d88 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371d930_0 .net "A2", 0 0, o0000000003669d88; 0 drivers
+o0000000003669db8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371e970_0 .net "B1", 0 0, o0000000003669db8; 0 drivers
+L_00000000038e7730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371fe10_0 .net8 "VGND", 0 0, L_00000000038e7730; 1 drivers, strength-aware
+L_00000000038e7960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371e5b0_0 .net8 "VNB", 0 0, L_00000000038e7960; 1 drivers, strength-aware
+L_00000000038e9090 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371e470_0 .net8 "VPB", 0 0, L_00000000038e9090; 1 drivers, strength-aware
+L_00000000038e7500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371dc50_0 .net8 "VPWR", 0 0, L_00000000038e7500; 1 drivers, strength-aware
+v000000000371e650_0 .net "Y", 0 0, L_000000000395f940; 1 drivers
+S_00000000036a2980 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89763, 4 89511 1, S_00000000027d66a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395f010 .functor OR 1, o0000000003669d88, o0000000003669d58, C4<0>, C4<0>;
+L_000000000395e4b0 .functor NAND 1, o0000000003669db8, L_000000000395f010, C4<1>, C4<1>;
+L_000000000395f940 .functor BUF 1, L_000000000395e4b0, C4<0>, C4<0>, C4<0>;
+v000000000371b1d0_0 .net "A1", 0 0, o0000000003669d58; alias, 0 drivers
+v000000000371f7d0_0 .net "A2", 0 0, o0000000003669d88; alias, 0 drivers
+v000000000371dd90_0 .net "B1", 0 0, o0000000003669db8; alias, 0 drivers
+L_00000000038e7e30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f230_0 .net8 "VGND", 0 0, L_00000000038e7e30; 1 drivers, strength-aware
+L_00000000038e8920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f0f0_0 .net8 "VNB", 0 0, L_00000000038e8920; 1 drivers, strength-aware
+L_00000000038e85a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371df70_0 .net8 "VPB", 0 0, L_00000000038e85a0; 1 drivers, strength-aware
+L_00000000038e7570 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371f190_0 .net8 "VPWR", 0 0, L_00000000038e7570; 1 drivers, strength-aware
+v000000000371fd70_0 .net "Y", 0 0, L_000000000395f940; alias, 1 drivers
+v000000000371e510_0 .net "nand0_out_Y", 0 0, L_000000000395e4b0; 1 drivers
+v000000000371ff50_0 .net "or0_out", 0 0, L_000000000395f010; 1 drivers
+S_00000000027d45a0 .scope module, "sky130_fd_sc_hd__o21ai_4" "sky130_fd_sc_hd__o21ai_4" 4 89859;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+o000000000366a178 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371ef10_0 .net "A1", 0 0, o000000000366a178; 0 drivers
+o000000000366a1a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371feb0_0 .net "A2", 0 0, o000000000366a1a8; 0 drivers
+o000000000366a1d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371e1f0_0 .net "B1", 0 0, o000000000366a1d8; 0 drivers
+L_00000000038e7ea0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371fff0_0 .net8 "VGND", 0 0, L_00000000038e7ea0; 1 drivers, strength-aware
+L_00000000038e8610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f050_0 .net8 "VNB", 0 0, L_00000000038e8610; 1 drivers, strength-aware
+L_00000000038e77a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371edd0_0 .net8 "VPB", 0 0, L_00000000038e77a0; 1 drivers, strength-aware
+L_00000000038e8290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371e290_0 .net8 "VPWR", 0 0, L_00000000038e8290; 1 drivers, strength-aware
+v000000000371f2d0_0 .net "Y", 0 0, L_000000000395f470; 1 drivers
+S_00000000036a4780 .scope module, "base" "sky130_fd_sc_hd__o21ai" 4 89877, 4 89511 1, S_00000000027d45a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+L_000000000395f400 .functor OR 1, o000000000366a1a8, o000000000366a178, C4<0>, C4<0>;
+L_000000000395f9b0 .functor NAND 1, o000000000366a1d8, L_000000000395f400, C4<1>, C4<1>;
+L_000000000395f470 .functor BUF 1, L_000000000395f9b0, C4<0>, C4<0>, C4<0>;
+v000000000371ded0_0 .net "A1", 0 0, o000000000366a178; alias, 0 drivers
+v000000000371fcd0_0 .net "A2", 0 0, o000000000366a1a8; alias, 0 drivers
+v000000000371f910_0 .net "B1", 0 0, o000000000366a1d8; alias, 0 drivers
+L_00000000038e7b90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f370_0 .net8 "VGND", 0 0, L_00000000038e7b90; 1 drivers, strength-aware
+L_00000000038e8bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371efb0_0 .net8 "VNB", 0 0, L_00000000038e8bc0; 1 drivers, strength-aware
+L_00000000038e7ab0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371d9d0_0 .net8 "VPB", 0 0, L_00000000038e7ab0; 1 drivers, strength-aware
+L_00000000038e8370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371e330_0 .net8 "VPWR", 0 0, L_00000000038e8370; 1 drivers, strength-aware
+v000000000371f730_0 .net "Y", 0 0, L_000000000395f470; alias, 1 drivers
+v000000000371e3d0_0 .net "nand0_out_Y", 0 0, L_000000000395f9b0; 1 drivers
+v000000000371e010_0 .net "or0_out", 0 0, L_000000000395f400; 1 drivers
+S_00000000027d7420 .scope module, "sky130_fd_sc_hd__o21ba_1" "sky130_fd_sc_hd__o21ba_1" 4 31350;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366a598 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371f5f0_0 .net "A1", 0 0, o000000000366a598; 0 drivers
+o000000000366a5c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371e8d0_0 .net "A2", 0 0, o000000000366a5c8; 0 drivers
+o000000000366a5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000371ea10_0 .net "B1_N", 0 0, o000000000366a5f8; 0 drivers
+L_00000000038e7f10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f870_0 .net8 "VGND", 0 0, L_00000000038e7f10; 1 drivers, strength-aware
+L_00000000038e75e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f9b0_0 .net8 "VNB", 0 0, L_00000000038e75e0; 1 drivers, strength-aware
+L_00000000038e7c00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371eab0_0 .net8 "VPB", 0 0, L_00000000038e7c00; 1 drivers, strength-aware
+L_00000000038e7f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371eb50_0 .net8 "VPWR", 0 0, L_00000000038e7f80; 1 drivers, strength-aware
+v000000000371da70_0 .net "X", 0 0, L_000000000395e670; 1 drivers
+S_00000000036a4900 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31368, 4 31229 1, S_00000000027d7420;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395fb00 .functor NOR 1, o000000000366a598, o000000000366a5c8, C4<0>, C4<0>;
+L_000000000395e2f0 .functor NOR 1, o000000000366a5f8, L_000000000395fb00, C4<0>, C4<0>;
+L_000000000395e670 .functor BUF 1, L_000000000395e2f0, C4<0>, C4<0>, C4<0>;
+v000000000371f4b0_0 .net "A1", 0 0, o000000000366a598; alias, 0 drivers
+v000000000371f410_0 .net "A2", 0 0, o000000000366a5c8; alias, 0 drivers
+v000000000371db10_0 .net "B1_N", 0 0, o000000000366a5f8; alias, 0 drivers
+L_00000000038e7ff0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371f550_0 .net8 "VGND", 0 0, L_00000000038e7ff0; 1 drivers, strength-aware
+L_00000000038e8ae0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371e6f0_0 .net8 "VNB", 0 0, L_00000000038e8ae0; 1 drivers, strength-aware
+L_00000000038e8ca0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371de30_0 .net8 "VPB", 0 0, L_00000000038e8ca0; 1 drivers, strength-aware
+L_00000000038e88b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371e0b0_0 .net8 "VPWR", 0 0, L_00000000038e88b0; 1 drivers, strength-aware
+v000000000371e830_0 .net "X", 0 0, L_000000000395e670; alias, 1 drivers
+v000000000371e150_0 .net "nor0_out", 0 0, L_000000000395fb00; 1 drivers
+v000000000371e790_0 .net "nor1_out_X", 0 0, L_000000000395e2f0; 1 drivers
+S_00000000027d6220 .scope module, "sky130_fd_sc_hd__o21ba_2" "sky130_fd_sc_hd__o21ba_2" 4 31465;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366a9b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720090_0 .net "A1", 0 0, o000000000366a9b8; 0 drivers
+o000000000366a9e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720f90_0 .net "A2", 0 0, o000000000366a9e8; 0 drivers
+o000000000366aa18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037213f0_0 .net "B1_N", 0 0, o000000000366aa18; 0 drivers
+L_00000000038e8060 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037218f0_0 .net8 "VGND", 0 0, L_00000000038e8060; 1 drivers, strength-aware
+L_00000000038e8ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720450_0 .net8 "VNB", 0 0, L_00000000038e8ed0; 1 drivers, strength-aware
+L_00000000038e8c30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003722430_0 .net8 "VPB", 0 0, L_00000000038e8c30; 1 drivers, strength-aware
+L_00000000038e8140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003722570_0 .net8 "VPWR", 0 0, L_00000000038e8140; 1 drivers, strength-aware
+v0000000003721ad0_0 .net "X", 0 0, L_000000000395e520; 1 drivers
+S_00000000036a5500 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31483, 4 31229 1, S_00000000027d6220;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395f080 .functor NOR 1, o000000000366a9b8, o000000000366a9e8, C4<0>, C4<0>;
+L_000000000395f160 .functor NOR 1, o000000000366aa18, L_000000000395f080, C4<0>, C4<0>;
+L_000000000395e520 .functor BUF 1, L_000000000395f160, C4<0>, C4<0>, C4<0>;
+v000000000371dbb0_0 .net "A1", 0 0, o000000000366a9b8; alias, 0 drivers
+v000000000371ebf0_0 .net "A2", 0 0, o000000000366a9e8; alias, 0 drivers
+v000000000371dcf0_0 .net "B1_N", 0 0, o000000000366aa18; alias, 0 drivers
+L_00000000038e80d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371fa50_0 .net8 "VGND", 0 0, L_00000000038e80d0; 1 drivers, strength-aware
+L_00000000038e7c70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000371ec90_0 .net8 "VNB", 0 0, L_00000000038e7c70; 1 drivers, strength-aware
+L_00000000038e7ce0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371faf0_0 .net8 "VPB", 0 0, L_00000000038e7ce0; 1 drivers, strength-aware
+L_00000000038e8d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000371fb90_0 .net8 "VPWR", 0 0, L_00000000038e8d10; 1 drivers, strength-aware
+v000000000371fc30_0 .net "X", 0 0, L_000000000395e520; alias, 1 drivers
+v000000000371ed30_0 .net "nor0_out", 0 0, L_000000000395f080; 1 drivers
+v000000000371ee70_0 .net "nor1_out_X", 0 0, L_000000000395f160; 1 drivers
+S_00000000027d4420 .scope module, "sky130_fd_sc_hd__o21ba_4" "sky130_fd_sc_hd__o21ba_4" 4 31580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366add8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037224d0_0 .net "A1", 0 0, o000000000366add8; 0 drivers
+o000000000366ae08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720b30_0 .net "A2", 0 0, o000000000366ae08; 0 drivers
+o000000000366ae38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720bd0_0 .net "B1_N", 0 0, o000000000366ae38; 0 drivers
+L_00000000038e83e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003722070_0 .net8 "VGND", 0 0, L_00000000038e83e0; 1 drivers, strength-aware
+L_00000000038e8760 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720c70_0 .net8 "VNB", 0 0, L_00000000038e8760; 1 drivers, strength-aware
+L_00000000038e8450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037208b0_0 .net8 "VPB", 0 0, L_00000000038e8450; 1 drivers, strength-aware
+L_00000000038e7d50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003720130_0 .net8 "VPWR", 0 0, L_00000000038e7d50; 1 drivers, strength-aware
+v0000000003720310_0 .net "X", 0 0, L_000000000395ea60; 1 drivers
+S_00000000036a4c00 .scope module, "base" "sky130_fd_sc_hd__o21ba" 4 31598, 4 31229 1, S_00000000027d4420;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395f1d0 .functor NOR 1, o000000000366add8, o000000000366ae08, C4<0>, C4<0>;
+L_000000000395e590 .functor NOR 1, o000000000366ae38, L_000000000395f1d0, C4<0>, C4<0>;
+L_000000000395ea60 .functor BUF 1, L_000000000395e590, C4<0>, C4<0>, C4<0>;
+v0000000003721b70_0 .net "A1", 0 0, o000000000366add8; alias, 0 drivers
+v00000000037217b0_0 .net "A2", 0 0, o000000000366ae08; alias, 0 drivers
+v0000000003721990_0 .net "B1_N", 0 0, o000000000366ae38; alias, 0 drivers
+L_00000000038e8680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003721030_0 .net8 "VGND", 0 0, L_00000000038e8680; 1 drivers, strength-aware
+L_00000000038e8a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720950_0 .net8 "VNB", 0 0, L_00000000038e8a00; 1 drivers, strength-aware
+L_00000000038e7650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037215d0_0 .net8 "VPB", 0 0, L_00000000038e7650; 1 drivers, strength-aware
+L_00000000038e76c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003720a90_0 .net8 "VPWR", 0 0, L_00000000038e76c0; 1 drivers, strength-aware
+v00000000037204f0_0 .net "X", 0 0, L_000000000395ea60; alias, 1 drivers
+v00000000037210d0_0 .net "nor0_out", 0 0, L_000000000395f1d0; 1 drivers
+v0000000003720ef0_0 .net "nor1_out_X", 0 0, L_000000000395e590; 1 drivers
+S_00000000027d4720 .scope module, "sky130_fd_sc_hd__o21bai_1" "sky130_fd_sc_hd__o21bai_1" 4 61463;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366b1f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037201d0_0 .net "A1", 0 0, o000000000366b1f8; 0 drivers
+o000000000366b228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003721350_0 .net "A2", 0 0, o000000000366b228; 0 drivers
+o000000000366b258 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003722610_0 .net "B1_N", 0 0, o000000000366b258; 0 drivers
+L_00000000038e8fb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003721490_0 .net8 "VGND", 0 0, L_00000000038e8fb0; 1 drivers, strength-aware
+L_00000000038e87d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720db0_0 .net8 "VNB", 0 0, L_00000000038e87d0; 1 drivers, strength-aware
+L_00000000038e8a70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003721d50_0 .net8 "VPB", 0 0, L_00000000038e8a70; 1 drivers, strength-aware
+L_00000000038e78f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003721c10_0 .net8 "VPWR", 0 0, L_00000000038e78f0; 1 drivers, strength-aware
+v00000000037209f0_0 .net "Y", 0 0, L_000000000395f240; 1 drivers
+S_00000000036a7900 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 61481, 4 61340 1, S_00000000027d4720;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395ec20 .functor NOT 1, o000000000366b258, C4<0>, C4<0>, C4<0>;
+L_000000000395ed70 .functor OR 1, o000000000366b228, o000000000366b1f8, C4<0>, C4<0>;
+L_000000000395eb40 .functor NAND 1, L_000000000395ec20, L_000000000395ed70, C4<1>, C4<1>;
+L_000000000395f240 .functor BUF 1, L_000000000395eb40, C4<0>, C4<0>, C4<0>;
+v0000000003721170_0 .net "A1", 0 0, o000000000366b1f8; alias, 0 drivers
+v0000000003720d10_0 .net "A2", 0 0, o000000000366b228; alias, 0 drivers
+v0000000003721670_0 .net "B1_N", 0 0, o000000000366b258; alias, 0 drivers
+L_00000000038e8530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037212b0_0 .net8 "VGND", 0 0, L_00000000038e8530; 1 drivers, strength-aware
+L_00000000038e7dc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003722750_0 .net8 "VNB", 0 0, L_00000000038e7dc0; 1 drivers, strength-aware
+L_00000000038e81b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037206d0_0 .net8 "VPB", 0 0, L_00000000038e81b0; 1 drivers, strength-aware
+L_00000000038e7810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037203b0_0 .net8 "VPWR", 0 0, L_00000000038e7810; 1 drivers, strength-aware
+v0000000003721a30_0 .net "Y", 0 0, L_000000000395f240; alias, 1 drivers
+v0000000003721210_0 .net "b", 0 0, L_000000000395ec20; 1 drivers
+v0000000003721710_0 .net "nand0_out_Y", 0 0, L_000000000395eb40; 1 drivers
+v0000000003721850_0 .net "or0_out", 0 0, L_000000000395ed70; 1 drivers
+S_00000000027d6820 .scope module, "sky130_fd_sc_hd__o21bai_2" "sky130_fd_sc_hd__o21bai_2" 4 60892;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366b648 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720810_0 .net "A1", 0 0, o000000000366b648; 0 drivers
+o000000000366b678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003720e50_0 .net "A2", 0 0, o000000000366b678; 0 drivers
+o000000000366b6a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003721e90_0 .net "B1_N", 0 0, o000000000366b6a8; 0 drivers
+L_00000000038e8840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003721f30_0 .net8 "VGND", 0 0, L_00000000038e8840; 1 drivers, strength-aware
+L_00000000038e8b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003721fd0_0 .net8 "VNB", 0 0, L_00000000038e8b50; 1 drivers, strength-aware
+L_00000000038e9020 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037221b0_0 .net8 "VPB", 0 0, L_00000000038e9020; 1 drivers, strength-aware
+L_00000000038e86f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003722250_0 .net8 "VPWR", 0 0, L_00000000038e86f0; 1 drivers, strength-aware
+v00000000037222f0_0 .net "Y", 0 0, L_000000000395f550; 1 drivers
+S_00000000036a2c80 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 60910, 4 61340 1, S_00000000027d6820;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395ec90 .functor NOT 1, o000000000366b6a8, C4<0>, C4<0>, C4<0>;
+L_000000000395f4e0 .functor OR 1, o000000000366b678, o000000000366b648, C4<0>, C4<0>;
+L_000000000395e600 .functor NAND 1, L_000000000395ec90, L_000000000395f4e0, C4<1>, C4<1>;
+L_000000000395f550 .functor BUF 1, L_000000000395e600, C4<0>, C4<0>, C4<0>;
+v00000000037226b0_0 .net "A1", 0 0, o000000000366b648; alias, 0 drivers
+v0000000003722110_0 .net "A2", 0 0, o000000000366b678; alias, 0 drivers
+v0000000003721cb0_0 .net "B1_N", 0 0, o000000000366b6a8; alias, 0 drivers
+L_00000000038e8990 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720590_0 .net8 "VGND", 0 0, L_00000000038e8990; 1 drivers, strength-aware
+L_00000000038e8d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003720270_0 .net8 "VNB", 0 0, L_00000000038e8d80; 1 drivers, strength-aware
+L_00000000038e8df0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037227f0_0 .net8 "VPB", 0 0, L_00000000038e8df0; 1 drivers, strength-aware
+L_00000000038e8e60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003721df0_0 .net8 "VPWR", 0 0, L_00000000038e8e60; 1 drivers, strength-aware
+v0000000003720630_0 .net "Y", 0 0, L_000000000395f550; alias, 1 drivers
+v0000000003722890_0 .net "b", 0 0, L_000000000395ec90; 1 drivers
+v0000000003721530_0 .net "nand0_out_Y", 0 0, L_000000000395e600; 1 drivers
+v0000000003720770_0 .net "or0_out", 0 0, L_000000000395f4e0; 1 drivers
+S_00000000027d6ca0 .scope module, "sky130_fd_sc_hd__o21bai_4" "sky130_fd_sc_hd__o21bai_4" 4 61007;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+o000000000366ba98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003723dd0_0 .net "A1", 0 0, o000000000366ba98; 0 drivers
+o000000000366bac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003723b50_0 .net "A2", 0 0, o000000000366bac8; 0 drivers
+o000000000366baf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003723510_0 .net "B1_N", 0 0, o000000000366baf8; 0 drivers
+L_00000000038e8f40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003723fb0_0 .net8 "VGND", 0 0, L_00000000038e8f40; 1 drivers, strength-aware
+L_00000000038e79d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003722930_0 .net8 "VNB", 0 0, L_00000000038e79d0; 1 drivers, strength-aware
+L_00000000038e7a40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037236f0_0 .net8 "VPB", 0 0, L_00000000038e7a40; 1 drivers, strength-aware
+L_00000000038ea910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003724730_0 .net8 "VPWR", 0 0, L_00000000038ea910; 1 drivers, strength-aware
+v0000000003722cf0_0 .net "Y", 0 0, L_000000000395f320; 1 drivers
+S_00000000036a6100 .scope module, "base" "sky130_fd_sc_hd__o21bai" 4 61025, 4 61340 1, S_00000000027d6ca0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1_N"
+L_000000000395ed00 .functor NOT 1, o000000000366baf8, C4<0>, C4<0>, C4<0>;
+L_000000000395ede0 .functor OR 1, o000000000366bac8, o000000000366ba98, C4<0>, C4<0>;
+L_000000000395ee50 .functor NAND 1, L_000000000395ed00, L_000000000395ede0, C4<1>, C4<1>;
+L_000000000395f320 .functor BUF 1, L_000000000395ee50, C4<0>, C4<0>, C4<0>;
+v0000000003722390_0 .net "A1", 0 0, o000000000366ba98; alias, 0 drivers
+v0000000003725090_0 .net "A2", 0 0, o000000000366bac8; alias, 0 drivers
+v0000000003722ed0_0 .net "B1_N", 0 0, o000000000366baf8; alias, 0 drivers
+L_00000000038ea050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003722bb0_0 .net8 "VGND", 0 0, L_00000000038ea050; 1 drivers, strength-aware
+L_00000000038eac90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003723970_0 .net8 "VNB", 0 0, L_00000000038eac90; 1 drivers, strength-aware
+L_00000000038ea520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003722b10_0 .net8 "VPB", 0 0, L_00000000038ea520; 1 drivers, strength-aware
+L_00000000038eaa60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037238d0_0 .net8 "VPWR", 0 0, L_00000000038eaa60; 1 drivers, strength-aware
+v0000000003723a10_0 .net "Y", 0 0, L_000000000395f320; alias, 1 drivers
+v0000000003724690_0 .net "b", 0 0, L_000000000395ed00; 1 drivers
+v0000000003723010_0 .net "nand0_out_Y", 0 0, L_000000000395ee50; 1 drivers
+v0000000003723ab0_0 .net "or0_out", 0 0, L_000000000395ede0; 1 drivers
+S_00000000027d5aa0 .scope module, "sky130_fd_sc_hd__o221a_1" "sky130_fd_sc_hd__o221a_1" 4 74583;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366bee8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037235b0_0 .net "A1", 0 0, o000000000366bee8; 0 drivers
+o000000000366bf18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724230_0 .net "A2", 0 0, o000000000366bf18; 0 drivers
+o000000000366bf48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724910_0 .net "B1", 0 0, o000000000366bf48; 0 drivers
+o000000000366bf78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724550_0 .net "B2", 0 0, o000000000366bf78; 0 drivers
+o000000000366bfa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724050_0 .net "C1", 0 0, o000000000366bfa8; 0 drivers
+L_00000000038e9330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003723790_0 .net8 "VGND", 0 0, L_00000000038e9330; 1 drivers, strength-aware
+L_00000000038e9410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003722d90_0 .net8 "VNB", 0 0, L_00000000038e9410; 1 drivers, strength-aware
+L_00000000038e93a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037230b0_0 .net8 "VPB", 0 0, L_00000000038e93a0; 1 drivers, strength-aware
+L_00000000038ea590 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003723830_0 .net8 "VPWR", 0 0, L_00000000038ea590; 1 drivers, strength-aware
+v0000000003723bf0_0 .net "X", 0 0, L_0000000003960580; 1 drivers
+S_00000000036a5680 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 74605, 4 74929 1, S_00000000027d5aa0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000395efa0 .functor OR 1, o000000000366bf78, o000000000366bf48, C4<0>, C4<0>;
+L_0000000003961000 .functor OR 1, o000000000366bf18, o000000000366bee8, C4<0>, C4<0>;
+L_000000000395ffd0 .functor AND 1, L_000000000395efa0, L_0000000003961000, o000000000366bfa8, C4<1>;
+L_0000000003960580 .functor BUF 1, L_000000000395ffd0, C4<0>, C4<0>, C4<0>;
+v0000000003723330_0 .net "A1", 0 0, o000000000366bee8; alias, 0 drivers
+v0000000003722f70_0 .net "A2", 0 0, o000000000366bf18; alias, 0 drivers
+v0000000003723e70_0 .net "B1", 0 0, o000000000366bf48; alias, 0 drivers
+v0000000003722a70_0 .net "B2", 0 0, o000000000366bf78; alias, 0 drivers
+v00000000037229d0_0 .net "C1", 0 0, o000000000366bfa8; alias, 0 drivers
+L_00000000038e96b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003724b90_0 .net8 "VGND", 0 0, L_00000000038e96b0; 1 drivers, strength-aware
+L_00000000038e9d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037231f0_0 .net8 "VNB", 0 0, L_00000000038e9d40; 1 drivers, strength-aware
+L_00000000038e9f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003723f10_0 .net8 "VPB", 0 0, L_00000000038e9f70; 1 drivers, strength-aware
+L_00000000038e9480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003722c50_0 .net8 "VPWR", 0 0, L_00000000038e9480; 1 drivers, strength-aware
+v0000000003724410_0 .net "X", 0 0, L_0000000003960580; alias, 1 drivers
+v0000000003723470_0 .net "and0_out_X", 0 0, L_000000000395ffd0; 1 drivers
+v0000000003724cd0_0 .net "or0_out", 0 0, L_000000000395efa0; 1 drivers
+v0000000003724c30_0 .net "or1_out", 0 0, L_0000000003961000; 1 drivers
+S_00000000027d3fa0 .scope module, "sky130_fd_sc_hd__o221a_2" "sky130_fd_sc_hd__o221a_2" 4 75187;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366c458 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724190_0 .net "A1", 0 0, o000000000366c458; 0 drivers
+o000000000366c488 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724d70_0 .net "A2", 0 0, o000000000366c488; 0 drivers
+o000000000366c4b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003724a50_0 .net "B1", 0 0, o000000000366c4b8; 0 drivers
+o000000000366c4e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037245f0_0 .net "B2", 0 0, o000000000366c4e8; 0 drivers
+o000000000366c518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037247d0_0 .net "C1", 0 0, o000000000366c518; 0 drivers
+L_00000000038ea0c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003724af0_0 .net8 "VGND", 0 0, L_00000000038ea0c0; 1 drivers, strength-aware
+L_00000000038e9fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003724e10_0 .net8 "VNB", 0 0, L_00000000038e9fe0; 1 drivers, strength-aware
+L_00000000038e94f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003724eb0_0 .net8 "VPB", 0 0, L_00000000038e94f0; 1 drivers, strength-aware
+L_00000000038ea9f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003724f50_0 .net8 "VPWR", 0 0, L_00000000038ea9f0; 1 drivers, strength-aware
+v0000000003724ff0_0 .net "X", 0 0, L_000000000395fda0; 1 drivers
+S_00000000036a5c80 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75209, 4 74929 1, S_00000000027d3fa0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003960190 .functor OR 1, o000000000366c4e8, o000000000366c4b8, C4<0>, C4<0>;
+L_0000000003960270 .functor OR 1, o000000000366c488, o000000000366c458, C4<0>, C4<0>;
+L_0000000003961540 .functor AND 1, L_0000000003960190, L_0000000003960270, o000000000366c518, C4<1>;
+L_000000000395fda0 .functor BUF 1, L_0000000003961540, C4<0>, C4<0>, C4<0>;
+v0000000003722e30_0 .net "A1", 0 0, o000000000366c458; alias, 0 drivers
+v00000000037242d0_0 .net "A2", 0 0, o000000000366c488; alias, 0 drivers
+v00000000037249b0_0 .net "B1", 0 0, o000000000366c4b8; alias, 0 drivers
+v0000000003723650_0 .net "B2", 0 0, o000000000366c4e8; alias, 0 drivers
+v0000000003723150_0 .net "C1", 0 0, o000000000366c518; alias, 0 drivers
+L_00000000038e95d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003723c90_0 .net8 "VGND", 0 0, L_00000000038e95d0; 1 drivers, strength-aware
+L_00000000038e9870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003723d30_0 .net8 "VNB", 0 0, L_00000000038e9870; 1 drivers, strength-aware
+L_00000000038e9640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003724870_0 .net8 "VPB", 0 0, L_00000000038e9640; 1 drivers, strength-aware
+L_00000000038e9bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037240f0_0 .net8 "VPWR", 0 0, L_00000000038e9bf0; 1 drivers, strength-aware
+v00000000037244b0_0 .net "X", 0 0, L_000000000395fda0; alias, 1 drivers
+v0000000003723290_0 .net "and0_out_X", 0 0, L_0000000003961540; 1 drivers
+v0000000003724370_0 .net "or0_out", 0 0, L_0000000003960190; 1 drivers
+v00000000037233d0_0 .net "or1_out", 0 0, L_0000000003960270; 1 drivers
+S_00000000027d48a0 .scope module, "sky130_fd_sc_hd__o221a_4" "sky130_fd_sc_hd__o221a_4" 4 75061;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366c9c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725950_0 .net "A1", 0 0, o000000000366c9c8; 0 drivers
+o000000000366c9f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037253b0_0 .net "A2", 0 0, o000000000366c9f8; 0 drivers
+o000000000366ca28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003726170_0 .net "B1", 0 0, o000000000366ca28; 0 drivers
+o000000000366ca58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037274d0_0 .net "B2", 0 0, o000000000366ca58; 0 drivers
+o000000000366ca88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003727610_0 .net "C1", 0 0, o000000000366ca88; 0 drivers
+L_00000000038ea600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003726030_0 .net8 "VGND", 0 0, L_00000000038ea600; 1 drivers, strength-aware
+L_00000000038e9b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003726210_0 .net8 "VNB", 0 0, L_00000000038e9b10; 1 drivers, strength-aware
+L_00000000038ea360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726a30_0 .net8 "VPB", 0 0, L_00000000038ea360; 1 drivers, strength-aware
+L_00000000038eabb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037262b0_0 .net8 "VPWR", 0 0, L_00000000038eabb0; 1 drivers, strength-aware
+v0000000003725630_0 .net "X", 0 0, L_0000000003960a50; 1 drivers
+S_00000000036a6400 .scope module, "base" "sky130_fd_sc_hd__o221a" 4 75083, 4 74929 1, S_00000000027d48a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_000000000395ff60 .functor OR 1, o000000000366ca58, o000000000366ca28, C4<0>, C4<0>;
+L_0000000003961380 .functor OR 1, o000000000366c9f8, o000000000366c9c8, C4<0>, C4<0>;
+L_0000000003960ba0 .functor AND 1, L_000000000395ff60, L_0000000003961380, o000000000366ca88, C4<1>;
+L_0000000003960a50 .functor BUF 1, L_0000000003960ba0, C4<0>, C4<0>, C4<0>;
+v00000000037268f0_0 .net "A1", 0 0, o000000000366c9c8; alias, 0 drivers
+v0000000003725f90_0 .net "A2", 0 0, o000000000366c9f8; alias, 0 drivers
+v0000000003725b30_0 .net "B1", 0 0, o000000000366ca28; alias, 0 drivers
+v00000000037265d0_0 .net "B2", 0 0, o000000000366ca58; alias, 0 drivers
+v00000000037258b0_0 .net "C1", 0 0, o000000000366ca88; alias, 0 drivers
+L_00000000038e9100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037260d0_0 .net8 "VGND", 0 0, L_00000000038e9100; 1 drivers, strength-aware
+L_00000000038eab40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003726990_0 .net8 "VNB", 0 0, L_00000000038eab40; 1 drivers, strength-aware
+L_00000000038e9560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003725810_0 .net8 "VPB", 0 0, L_00000000038e9560; 1 drivers, strength-aware
+L_00000000038ea3d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003727430_0 .net8 "VPWR", 0 0, L_00000000038ea3d0; 1 drivers, strength-aware
+v0000000003726c10_0 .net "X", 0 0, L_0000000003960a50; alias, 1 drivers
+v00000000037271b0_0 .net "and0_out_X", 0 0, L_0000000003960ba0; 1 drivers
+v0000000003725a90_0 .net "or0_out", 0 0, L_000000000395ff60; 1 drivers
+v0000000003725e50_0 .net "or1_out", 0 0, L_0000000003961380; 1 drivers
+S_00000000027d63a0 .scope module, "sky130_fd_sc_hd__o221ai_1" "sky130_fd_sc_hd__o221ai_1" 4 23010;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366cf38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003726cb0_0 .net "A1", 0 0, o000000000366cf38; 0 drivers
+o000000000366cf68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725ef0_0 .net "A2", 0 0, o000000000366cf68; 0 drivers
+o000000000366cf98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003727570_0 .net "B1", 0 0, o000000000366cf98; 0 drivers
+o000000000366cfc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725270_0 .net "B2", 0 0, o000000000366cfc8; 0 drivers
+o000000000366cff8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003726350_0 .net "C1", 0 0, o000000000366cff8; 0 drivers
+L_00000000038e9720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037263f0_0 .net8 "VGND", 0 0, L_00000000038e9720; 1 drivers, strength-aware
+L_00000000038ea8a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037267b0_0 .net8 "VNB", 0 0, L_00000000038ea8a0; 1 drivers, strength-aware
+L_00000000038ea670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726ad0_0 .net8 "VPB", 0 0, L_00000000038ea670; 1 drivers, strength-aware
+L_00000000038e9790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726d50_0 .net8 "VPWR", 0 0, L_00000000038e9790; 1 drivers, strength-aware
+v0000000003725310_0 .net "Y", 0 0, L_00000000039610e0; 1 drivers
+S_00000000036a2500 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23032, 4 23482 1, S_00000000027d63a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003960c10 .functor OR 1, o000000000366cfc8, o000000000366cf98, C4<0>, C4<0>;
+L_00000000039613f0 .functor OR 1, o000000000366cf68, o000000000366cf38, C4<0>, C4<0>;
+L_0000000003960970 .functor NAND 1, L_00000000039613f0, L_0000000003960c10, o000000000366cff8, C4<1>;
+L_00000000039610e0 .functor BUF 1, L_0000000003960970, C4<0>, C4<0>, C4<0>;
+v00000000037259f0_0 .net "A1", 0 0, o000000000366cf38; alias, 0 drivers
+v00000000037254f0_0 .net "A2", 0 0, o000000000366cf68; alias, 0 drivers
+v0000000003726b70_0 .net "B1", 0 0, o000000000366cf98; alias, 0 drivers
+v00000000037272f0_0 .net "B2", 0 0, o000000000366cfc8; alias, 0 drivers
+v0000000003725bd0_0 .net "C1", 0 0, o000000000366cff8; alias, 0 drivers
+L_00000000038eac20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003725c70_0 .net8 "VGND", 0 0, L_00000000038eac20; 1 drivers, strength-aware
+L_00000000038e92c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003725d10_0 .net8 "VNB", 0 0, L_00000000038e92c0; 1 drivers, strength-aware
+L_00000000038ea980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037256d0_0 .net8 "VPB", 0 0, L_00000000038ea980; 1 drivers, strength-aware
+L_00000000038ea130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726f30_0 .net8 "VPWR", 0 0, L_00000000038ea130; 1 drivers, strength-aware
+v0000000003725db0_0 .net "Y", 0 0, L_00000000039610e0; alias, 1 drivers
+v0000000003726710_0 .net "nand0_out_Y", 0 0, L_0000000003960970; 1 drivers
+v0000000003727070_0 .net "or0_out", 0 0, L_0000000003960c10; 1 drivers
+v0000000003727390_0 .net "or1_out", 0 0, L_00000000039613f0; 1 drivers
+S_00000000027d6e20 .scope module, "sky130_fd_sc_hd__o221ai_2" "sky130_fd_sc_hd__o221ai_2" 4 23614;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366d4a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003727890_0 .net "A1", 0 0, o000000000366d4a8; 0 drivers
+o000000000366d4d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725130_0 .net "A2", 0 0, o000000000366d4d8; 0 drivers
+o000000000366d508 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037251d0_0 .net "B1", 0 0, o000000000366d508; 0 drivers
+o000000000366d538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725450_0 .net "B2", 0 0, o000000000366d538; 0 drivers
+o000000000366d568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003725590_0 .net "C1", 0 0, o000000000366d568; 0 drivers
+L_00000000038ea280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003728b50_0 .net8 "VGND", 0 0, L_00000000038ea280; 1 drivers, strength-aware
+L_00000000038e9800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729730_0 .net8 "VNB", 0 0, L_00000000038e9800; 1 drivers, strength-aware
+L_00000000038e9950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003729550_0 .net8 "VPB", 0 0, L_00000000038e9950; 1 drivers, strength-aware
+L_00000000038e9b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037295f0_0 .net8 "VPWR", 0 0, L_00000000038e9b80; 1 drivers, strength-aware
+v0000000003727ed0_0 .net "Y", 0 0, L_00000000039606d0; 1 drivers
+S_00000000036a6e80 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23636, 4 23482 1, S_00000000027d6e20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003960cf0 .functor OR 1, o000000000366d538, o000000000366d508, C4<0>, C4<0>;
+L_0000000003960dd0 .functor OR 1, o000000000366d4d8, o000000000366d4a8, C4<0>, C4<0>;
+L_000000000395fe10 .functor NAND 1, L_0000000003960dd0, L_0000000003960cf0, o000000000366d568, C4<1>;
+L_00000000039606d0 .functor BUF 1, L_000000000395fe10, C4<0>, C4<0>, C4<0>;
+v0000000003725770_0 .net "A1", 0 0, o000000000366d4a8; alias, 0 drivers
+v0000000003726490_0 .net "A2", 0 0, o000000000366d4d8; alias, 0 drivers
+v0000000003727110_0 .net "B1", 0 0, o000000000366d508; alias, 0 drivers
+v0000000003726530_0 .net "B2", 0 0, o000000000366d538; alias, 0 drivers
+v0000000003726df0_0 .net "C1", 0 0, o000000000366d568; alias, 0 drivers
+L_00000000038ea440 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003726670_0 .net8 "VGND", 0 0, L_00000000038ea440; 1 drivers, strength-aware
+L_00000000038ea2f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003726850_0 .net8 "VNB", 0 0, L_00000000038ea2f0; 1 drivers, strength-aware
+L_00000000038e98e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726e90_0 .net8 "VPB", 0 0, L_00000000038e98e0; 1 drivers, strength-aware
+L_00000000038ea6e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003726fd0_0 .net8 "VPWR", 0 0, L_00000000038ea6e0; 1 drivers, strength-aware
+v0000000003727250_0 .net "Y", 0 0, L_00000000039606d0; alias, 1 drivers
+v00000000037276b0_0 .net "nand0_out_Y", 0 0, L_000000000395fe10; 1 drivers
+v0000000003727750_0 .net "or0_out", 0 0, L_0000000003960cf0; 1 drivers
+v00000000037277f0_0 .net "or1_out", 0 0, L_0000000003960dd0; 1 drivers
+S_00000000027d51a0 .scope module, "sky130_fd_sc_hd__o221ai_4" "sky130_fd_sc_hd__o221ai_4" 4 23136;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+o000000000366da18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003727930_0 .net "A1", 0 0, o000000000366da18; 0 drivers
+o000000000366da48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728970_0 .net "A2", 0 0, o000000000366da48; 0 drivers
+o000000000366da78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003729e10_0 .net "B1", 0 0, o000000000366da78; 0 drivers
+o000000000366daa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728c90_0 .net "B2", 0 0, o000000000366daa8; 0 drivers
+o000000000366dad8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037286f0_0 .net "C1", 0 0, o000000000366dad8; 0 drivers
+L_00000000038e99c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729690_0 .net8 "VGND", 0 0, L_00000000038e99c0; 1 drivers, strength-aware
+L_00000000038ea4b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729370_0 .net8 "VNB", 0 0, L_00000000038ea4b0; 1 drivers, strength-aware
+L_00000000038ea750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037280b0_0 .net8 "VPB", 0 0, L_00000000038ea750; 1 drivers, strength-aware
+L_00000000038ea7c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003729410_0 .net8 "VPWR", 0 0, L_00000000038ea7c0; 1 drivers, strength-aware
+v0000000003729a50_0 .net "Y", 0 0, L_00000000039600b0; 1 drivers
+S_00000000036a6580 .scope module, "base" "sky130_fd_sc_hd__o221ai" 4 23158, 4 23482 1, S_00000000027d51a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003960ac0 .functor OR 1, o000000000366daa8, o000000000366da78, C4<0>, C4<0>;
+L_0000000003961700 .functor OR 1, o000000000366da48, o000000000366da18, C4<0>, C4<0>;
+L_0000000003960040 .functor NAND 1, L_0000000003961700, L_0000000003960ac0, o000000000366dad8, C4<1>;
+L_00000000039600b0 .functor BUF 1, L_0000000003960040, C4<0>, C4<0>, C4<0>;
+v0000000003727cf0_0 .net "A1", 0 0, o000000000366da18; alias, 0 drivers
+v0000000003728830_0 .net "A2", 0 0, o000000000366da48; alias, 0 drivers
+v0000000003729230_0 .net "B1", 0 0, o000000000366da78; alias, 0 drivers
+v0000000003728470_0 .net "B2", 0 0, o000000000366daa8; alias, 0 drivers
+v0000000003727d90_0 .net "C1", 0 0, o000000000366dad8; alias, 0 drivers
+L_00000000038ea830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037292d0_0 .net8 "VGND", 0 0, L_00000000038ea830; 1 drivers, strength-aware
+L_00000000038e9cd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037290f0_0 .net8 "VNB", 0 0, L_00000000038e9cd0; 1 drivers, strength-aware
+L_00000000038eaad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003728510_0 .net8 "VPB", 0 0, L_00000000038eaad0; 1 drivers, strength-aware
+L_00000000038e9a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037285b0_0 .net8 "VPWR", 0 0, L_00000000038e9a30; 1 drivers, strength-aware
+v0000000003729d70_0 .net "Y", 0 0, L_00000000039600b0; alias, 1 drivers
+v0000000003728650_0 .net "nand0_out_Y", 0 0, L_0000000003960040; 1 drivers
+v00000000037288d0_0 .net "or0_out", 0 0, L_0000000003960ac0; 1 drivers
+v0000000003729870_0 .net "or1_out", 0 0, L_0000000003961700; 1 drivers
+S_00000000027d78a0 .scope module, "sky130_fd_sc_hd__o22a_1" "sky130_fd_sc_hd__o22a_1" 4 50886;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366df88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728dd0_0 .net "A1", 0 0, o000000000366df88; 0 drivers
+o000000000366dfb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728150_0 .net "A2", 0 0, o000000000366dfb8; 0 drivers
+o000000000366dfe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728ab0_0 .net "B1", 0 0, o000000000366dfe8; 0 drivers
+o000000000366e018 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728790_0 .net "B2", 0 0, o000000000366e018; 0 drivers
+L_00000000038e9c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729b90_0 .net8 "VGND", 0 0, L_00000000038e9c60; 1 drivers, strength-aware
+L_00000000038e9170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729c30_0 .net8 "VNB", 0 0, L_00000000038e9170; 1 drivers, strength-aware
+L_00000000038e9aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003729cd0_0 .net8 "VPB", 0 0, L_00000000038e9aa0; 1 drivers, strength-aware
+L_00000000038e91e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003728d30_0 .net8 "VPWR", 0 0, L_00000000038e91e0; 1 drivers, strength-aware
+v0000000003728e70_0 .net "X", 0 0, L_0000000003960c80; 1 drivers
+S_00000000036a5b00 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50906, 4 51223 1, S_00000000027d78a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_00000000039611c0 .functor OR 1, o000000000366dfb8, o000000000366df88, C4<0>, C4<0>;
+L_00000000039615b0 .functor OR 1, o000000000366e018, o000000000366dfe8, C4<0>, C4<0>;
+L_0000000003960d60 .functor AND 1, L_00000000039611c0, L_00000000039615b0, C4<1>, C4<1>;
+L_0000000003960c80 .functor BUF 1, L_0000000003960d60, C4<0>, C4<0>, C4<0>;
+v0000000003729190_0 .net "A1", 0 0, o000000000366df88; alias, 0 drivers
+v00000000037297d0_0 .net "A2", 0 0, o000000000366dfb8; alias, 0 drivers
+v0000000003728a10_0 .net "B1", 0 0, o000000000366dfe8; alias, 0 drivers
+v00000000037294b0_0 .net "B2", 0 0, o000000000366e018; alias, 0 drivers
+L_00000000038e9250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003727c50_0 .net8 "VGND", 0 0, L_00000000038e9250; 1 drivers, strength-aware
+L_00000000038e9db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003728290_0 .net8 "VNB", 0 0, L_00000000038e9db0; 1 drivers, strength-aware
+L_00000000038ea1a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003728bf0_0 .net8 "VPB", 0 0, L_00000000038ea1a0; 1 drivers, strength-aware
+L_00000000038e9e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037279d0_0 .net8 "VPWR", 0 0, L_00000000038e9e20; 1 drivers, strength-aware
+v0000000003729af0_0 .net "X", 0 0, L_0000000003960c80; alias, 1 drivers
+v00000000037299b0_0 .net "and0_out_X", 0 0, L_0000000003960d60; 1 drivers
+v0000000003727a70_0 .net "or0_out", 0 0, L_00000000039611c0; 1 drivers
+v0000000003729910_0 .net "or1_out", 0 0, L_00000000039615b0; 1 drivers
+S_00000000027d5320 .scope module, "sky130_fd_sc_hd__o22a_4" "sky130_fd_sc_hd__o22a_4" 4 50646;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366e468 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037281f0_0 .net "A1", 0 0, o000000000366e468; 0 drivers
+o000000000366e498 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003728330_0 .net "A2", 0 0, o000000000366e498; 0 drivers
+o000000000366e4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037283d0_0 .net "B1", 0 0, o000000000366e4c8; 0 drivers
+o000000000366e4f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372ab30_0 .net "B2", 0 0, o000000000366e4f8; 0 drivers
+L_00000000038e9e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372bf30_0 .net8 "VGND", 0 0, L_00000000038e9e90; 1 drivers, strength-aware
+L_00000000038e9f00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372ac70_0 .net8 "VNB", 0 0, L_00000000038e9f00; 1 drivers, strength-aware
+L_00000000038ea210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372a6d0_0 .net8 "VPB", 0 0, L_00000000038ea210; 1 drivers, strength-aware
+L_00000000038eb5c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372bfd0_0 .net8 "VPWR", 0 0, L_00000000038eb5c0; 1 drivers, strength-aware
+v000000000372c7f0_0 .net "X", 0 0, L_0000000003960e40; 1 drivers
+S_00000000036a2680 .scope module, "base" "sky130_fd_sc_hd__o22a" 4 50666, 4 51223 1, S_00000000027d5320;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960430 .functor OR 1, o000000000366e498, o000000000366e468, C4<0>, C4<0>;
+L_0000000003961770 .functor OR 1, o000000000366e4f8, o000000000366e4c8, C4<0>, C4<0>;
+L_0000000003961310 .functor AND 1, L_0000000003960430, L_0000000003961770, C4<1>, C4<1>;
+L_0000000003960e40 .functor BUF 1, L_0000000003961310, C4<0>, C4<0>, C4<0>;
+v0000000003727b10_0 .net "A1", 0 0, o000000000366e468; alias, 0 drivers
+v0000000003728f10_0 .net "A2", 0 0, o000000000366e498; alias, 0 drivers
+v0000000003729eb0_0 .net "B1", 0 0, o000000000366e4c8; alias, 0 drivers
+v0000000003728010_0 .net "B2", 0 0, o000000000366e4f8; alias, 0 drivers
+L_00000000038eb400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003728fb0_0 .net8 "VGND", 0 0, L_00000000038eb400; 1 drivers, strength-aware
+L_00000000038ebda0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003729f50_0 .net8 "VNB", 0 0, L_00000000038ebda0; 1 drivers, strength-aware
+L_00000000038ec200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003729050_0 .net8 "VPB", 0 0, L_00000000038ec200; 1 drivers, strength-aware
+L_00000000038ead70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003729ff0_0 .net8 "VPWR", 0 0, L_00000000038ead70; 1 drivers, strength-aware
+v000000000372a090_0 .net "X", 0 0, L_0000000003960e40; alias, 1 drivers
+v0000000003727bb0_0 .net "and0_out_X", 0 0, L_0000000003961310; 1 drivers
+v0000000003727e30_0 .net "or0_out", 0 0, L_0000000003960430; 1 drivers
+v0000000003727f70_0 .net "or1_out", 0 0, L_0000000003961770; 1 drivers
+S_00000000027d6fa0 .scope module, "sky130_fd_sc_hd__o22ai_1" "sky130_fd_sc_hd__o22ai_1" 4 24201;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366e948 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372af90_0 .net "A1", 0 0, o000000000366e948; 0 drivers
+o000000000366e978 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372abd0_0 .net "A2", 0 0, o000000000366e978; 0 drivers
+o000000000366e9a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372b670_0 .net "B1", 0 0, o000000000366e9a8; 0 drivers
+o000000000366e9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a450_0 .net "B2", 0 0, o000000000366e9d8; 0 drivers
+L_00000000038eaec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372b0d0_0 .net8 "VGND", 0 0, L_00000000038eaec0; 1 drivers, strength-aware
+L_00000000038ec7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372aef0_0 .net8 "VNB", 0 0, L_00000000038ec7b0; 1 drivers, strength-aware
+L_00000000038ebfd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372c1b0_0 .net8 "VPB", 0 0, L_00000000038ebfd0; 1 drivers, strength-aware
+L_00000000038ec270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372b850_0 .net8 "VPWR", 0 0, L_00000000038ec270; 1 drivers, strength-aware
+v000000000372bc10_0 .net "Y", 0 0, L_0000000003960f20; 1 drivers
+S_00000000036a3580 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 24221, 4 24074 1, S_00000000027d6fa0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960eb0 .functor NOR 1, o000000000366e9a8, o000000000366e9d8, C4<0>, C4<0>;
+L_00000000039612a0 .functor NOR 1, o000000000366e948, o000000000366e978, C4<0>, C4<0>;
+L_0000000003960b30 .functor OR 1, L_00000000039612a0, L_0000000003960eb0, C4<0>, C4<0>;
+L_0000000003960f20 .functor BUF 1, L_0000000003960b30, C4<0>, C4<0>, C4<0>;
+v000000000372b710_0 .net "A1", 0 0, o000000000366e948; alias, 0 drivers
+v000000000372b5d0_0 .net "A2", 0 0, o000000000366e978; alias, 0 drivers
+v000000000372c4d0_0 .net "B1", 0 0, o000000000366e9a8; alias, 0 drivers
+v000000000372b030_0 .net "B2", 0 0, o000000000366e9d8; alias, 0 drivers
+L_00000000038eb080 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372a270_0 .net8 "VGND", 0 0, L_00000000038eb080; 1 drivers, strength-aware
+L_00000000038ebc50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372b210_0 .net8 "VNB", 0 0, L_00000000038ebc50; 1 drivers, strength-aware
+L_00000000038eb4e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372b2b0_0 .net8 "VPB", 0 0, L_00000000038eb4e0; 1 drivers, strength-aware
+L_00000000038eb6a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372b7b0_0 .net8 "VPWR", 0 0, L_00000000038eb6a0; 1 drivers, strength-aware
+v000000000372ba30_0 .net "Y", 0 0, L_0000000003960f20; alias, 1 drivers
+v000000000372c110_0 .net "nor0_out", 0 0, L_0000000003960eb0; 1 drivers
+v000000000372a310_0 .net "nor1_out", 0 0, L_00000000039612a0; 1 drivers
+v000000000372bd50_0 .net "or0_out_Y", 0 0, L_0000000003960b30; 1 drivers
+S_00000000027d57a0 .scope module, "sky130_fd_sc_hd__o22ai_2" "sky130_fd_sc_hd__o22ai_2" 4 24321;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366ee28 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372bb70_0 .net "A1", 0 0, o000000000366ee28; 0 drivers
+o000000000366ee58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a8b0_0 .net "A2", 0 0, o000000000366ee58; 0 drivers
+o000000000366ee88 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a4f0_0 .net "B1", 0 0, o000000000366ee88; 0 drivers
+o000000000366eeb8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372bcb0_0 .net "B2", 0 0, o000000000366eeb8; 0 drivers
+L_00000000038eaf30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372b490_0 .net8 "VGND", 0 0, L_00000000038eaf30; 1 drivers, strength-aware
+L_00000000038ebf60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372ae50_0 .net8 "VNB", 0 0, L_00000000038ebf60; 1 drivers, strength-aware
+L_00000000038ec350 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372c070_0 .net8 "VPB", 0 0, L_00000000038ec350; 1 drivers, strength-aware
+L_00000000038ec820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372b3f0_0 .net8 "VPWR", 0 0, L_00000000038ec820; 1 drivers, strength-aware
+v000000000372a770_0 .net "Y", 0 0, L_00000000039607b0; 1 drivers
+S_00000000036a3280 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 24341, 4 24074 1, S_00000000027d57a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960120 .functor NOR 1, o000000000366ee88, o000000000366eeb8, C4<0>, C4<0>;
+L_0000000003960740 .functor NOR 1, o000000000366ee28, o000000000366ee58, C4<0>, C4<0>;
+L_0000000003960f90 .functor OR 1, L_0000000003960740, L_0000000003960120, C4<0>, C4<0>;
+L_00000000039607b0 .functor BUF 1, L_0000000003960f90, C4<0>, C4<0>, C4<0>;
+v000000000372a3b0_0 .net "A1", 0 0, o000000000366ee28; alias, 0 drivers
+v000000000372a130_0 .net "A2", 0 0, o000000000366ee58; alias, 0 drivers
+v000000000372c570_0 .net "B1", 0 0, o000000000366ee88; alias, 0 drivers
+v000000000372b170_0 .net "B2", 0 0, o000000000366eeb8; alias, 0 drivers
+L_00000000038ebef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372be90_0 .net8 "VGND", 0 0, L_00000000038ebef0; 1 drivers, strength-aware
+L_00000000038eb780 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372a810_0 .net8 "VNB", 0 0, L_00000000038eb780; 1 drivers, strength-aware
+L_00000000038ebe10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372b350_0 .net8 "VPB", 0 0, L_00000000038ebe10; 1 drivers, strength-aware
+L_00000000038ebe80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372ad10_0 .net8 "VPWR", 0 0, L_00000000038ebe80; 1 drivers, strength-aware
+v000000000372adb0_0 .net "Y", 0 0, L_00000000039607b0; alias, 1 drivers
+v000000000372b8f0_0 .net "nor0_out", 0 0, L_0000000003960120; 1 drivers
+v000000000372b990_0 .net "nor1_out", 0 0, L_0000000003960740; 1 drivers
+v000000000372bad0_0 .net "or0_out_Y", 0 0, L_0000000003960f90; 1 drivers
+S_00000000027d4a20 .scope module, "sky130_fd_sc_hd__o22ai_4" "sky130_fd_sc_hd__o22ai_4" 4 23737;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366f308 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a1d0_0 .net "A1", 0 0, o000000000366f308; 0 drivers
+o000000000366f338 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a630_0 .net "A2", 0 0, o000000000366f338; 0 drivers
+o000000000366f368 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372a950_0 .net "B1", 0 0, o000000000366f368; 0 drivers
+o000000000366f398 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372aa90_0 .net "B2", 0 0, o000000000366f398; 0 drivers
+L_00000000038eb9b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372df10_0 .net8 "VGND", 0 0, L_00000000038eb9b0; 1 drivers, strength-aware
+L_00000000038eb390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372d0b0_0 .net8 "VNB", 0 0, L_00000000038eb390; 1 drivers, strength-aware
+L_00000000038eb1d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372d830_0 .net8 "VPB", 0 0, L_00000000038eb1d0; 1 drivers, strength-aware
+L_00000000038ec040 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372d790_0 .net8 "VPWR", 0 0, L_00000000038ec040; 1 drivers, strength-aware
+v000000000372e0f0_0 .net "Y", 0 0, L_0000000003960200; 1 drivers
+S_00000000036a2380 .scope module, "base" "sky130_fd_sc_hd__o22ai" 4 23757, 4 24074 1, S_00000000027d4a20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960820 .functor NOR 1, o000000000366f368, o000000000366f398, C4<0>, C4<0>;
+L_0000000003961070 .functor NOR 1, o000000000366f308, o000000000366f338, C4<0>, C4<0>;
+L_00000000039604a0 .functor OR 1, L_0000000003961070, L_0000000003960820, C4<0>, C4<0>;
+L_0000000003960200 .functor BUF 1, L_00000000039604a0, C4<0>, C4<0>, C4<0>;
+v000000000372a9f0_0 .net "A1", 0 0, o000000000366f308; alias, 0 drivers
+v000000000372c750_0 .net "A2", 0 0, o000000000366f338; alias, 0 drivers
+v000000000372bdf0_0 .net "B1", 0 0, o000000000366f368; alias, 0 drivers
+v000000000372b530_0 .net "B2", 0 0, o000000000366f398; alias, 0 drivers
+L_00000000038ec510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372c610_0 .net8 "VGND", 0 0, L_00000000038ec510; 1 drivers, strength-aware
+L_00000000038ebb00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372c250_0 .net8 "VNB", 0 0, L_00000000038ebb00; 1 drivers, strength-aware
+L_00000000038eb0f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372a590_0 .net8 "VPB", 0 0, L_00000000038eb0f0; 1 drivers, strength-aware
+L_00000000038ebcc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372c2f0_0 .net8 "VPWR", 0 0, L_00000000038ebcc0; 1 drivers, strength-aware
+v000000000372c390_0 .net "Y", 0 0, L_0000000003960200; alias, 1 drivers
+v000000000372c430_0 .net "nor0_out", 0 0, L_0000000003960820; 1 drivers
+v000000000372c6b0_0 .net "nor1_out", 0 0, L_0000000003961070; 1 drivers
+v000000000372c890_0 .net "or0_out_Y", 0 0, L_00000000039604a0; 1 drivers
+S_00000000027d5920 .scope module, "sky130_fd_sc_hd__o2bb2a_1" "sky130_fd_sc_hd__o2bb2a_1" 4 85622;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366f7e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372d150_0 .net "A1_N", 0 0, o000000000366f7e8; 0 drivers
+o000000000366f818 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372d330_0 .net "A2_N", 0 0, o000000000366f818; 0 drivers
+o000000000366f848 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372eeb0_0 .net "B1", 0 0, o000000000366f848; 0 drivers
+o000000000366f878 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372ced0_0 .net "B2", 0 0, o000000000366f878; 0 drivers
+L_00000000038eba20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372d5b0_0 .net8 "VGND", 0 0, L_00000000038eba20; 1 drivers, strength-aware
+L_00000000038eafa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372e2d0_0 .net8 "VNB", 0 0, L_00000000038eafa0; 1 drivers, strength-aware
+L_00000000038eb160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372dbf0_0 .net8 "VPB", 0 0, L_00000000038eb160; 1 drivers, strength-aware
+L_00000000038ec890 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372e370_0 .net8 "VPWR", 0 0, L_00000000038ec890; 1 drivers, strength-aware
+v000000000372dfb0_0 .net "X", 0 0, L_0000000003960900; 1 drivers
+S_00000000036a5e00 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85642, 4 86199 1, S_00000000027d5920;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960510 .functor NAND 1, o000000000366f818, o000000000366f7e8, C4<1>, C4<1>;
+L_00000000039617e0 .functor OR 1, o000000000366f878, o000000000366f848, C4<0>, C4<0>;
+L_00000000039602e0 .functor AND 1, L_0000000003960510, L_00000000039617e0, C4<1>, C4<1>;
+L_0000000003960900 .functor BUF 1, L_00000000039602e0, C4<0>, C4<0>, C4<0>;
+v000000000372e190_0 .net "A1_N", 0 0, o000000000366f7e8; alias, 0 drivers
+v000000000372c930_0 .net "A2_N", 0 0, o000000000366f818; alias, 0 drivers
+v000000000372d8d0_0 .net "B1", 0 0, o000000000366f848; alias, 0 drivers
+v000000000372ccf0_0 .net "B2", 0 0, o000000000366f878; alias, 0 drivers
+L_00000000038ead00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372d970_0 .net8 "VGND", 0 0, L_00000000038ead00; 1 drivers, strength-aware
+L_00000000038eb630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372e690_0 .net8 "VNB", 0 0, L_00000000038eb630; 1 drivers, strength-aware
+L_00000000038ec120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372e230_0 .net8 "VPB", 0 0, L_00000000038ec120; 1 drivers, strength-aware
+L_00000000038ec0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372da10_0 .net8 "VPWR", 0 0, L_00000000038ec0b0; 1 drivers, strength-aware
+v000000000372dab0_0 .net "X", 0 0, L_0000000003960900; alias, 1 drivers
+v000000000372ee10_0 .net "and0_out_X", 0 0, L_00000000039602e0; 1 drivers
+v000000000372d510_0 .net "nand0_out", 0 0, L_0000000003960510; 1 drivers
+v000000000372db50_0 .net "or0_out", 0 0, L_00000000039617e0; 1 drivers
+S_00000000027d7120 .scope module, "sky130_fd_sc_hd__o2bb2a_2" "sky130_fd_sc_hd__o2bb2a_2" 4 85742;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o000000000366fcc8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372d010_0 .net "A1_N", 0 0, o000000000366fcc8; 0 drivers
+o000000000366fcf8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372d470_0 .net "A2_N", 0 0, o000000000366fcf8; 0 drivers
+o000000000366fd28 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372d290_0 .net "B1", 0 0, o000000000366fd28; 0 drivers
+o000000000366fd58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372cbb0_0 .net "B2", 0 0, o000000000366fd58; 0 drivers
+L_00000000038eade0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372ed70_0 .net8 "VGND", 0 0, L_00000000038eade0; 1 drivers, strength-aware
+L_00000000038eb710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372de70_0 .net8 "VNB", 0 0, L_00000000038eb710; 1 drivers, strength-aware
+L_00000000038ec190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372e730_0 .net8 "VPB", 0 0, L_00000000038ec190; 1 drivers, strength-aware
+L_00000000038eb010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372e050_0 .net8 "VPWR", 0 0, L_00000000038eb010; 1 drivers, strength-aware
+v000000000372e410_0 .net "X", 0 0, L_0000000003961620; 1 drivers
+S_00000000036a2b00 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85762, 4 86199 1, S_00000000027d7120;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960350 .functor NAND 1, o000000000366fcf8, o000000000366fcc8, C4<1>, C4<1>;
+L_000000000395fe80 .functor OR 1, o000000000366fd58, o000000000366fd28, C4<0>, C4<0>;
+L_000000000395fd30 .functor AND 1, L_0000000003960350, L_000000000395fe80, C4<1>, C4<1>;
+L_0000000003961620 .functor BUF 1, L_000000000395fd30, C4<0>, C4<0>, C4<0>;
+v000000000372cd90_0 .net "A1_N", 0 0, o000000000366fcc8; alias, 0 drivers
+v000000000372c9d0_0 .net "A2_N", 0 0, o000000000366fcf8; alias, 0 drivers
+v000000000372dc90_0 .net "B1", 0 0, o000000000366fd28; alias, 0 drivers
+v000000000372d3d0_0 .net "B2", 0 0, o000000000366fd58; alias, 0 drivers
+L_00000000038eba90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372ddd0_0 .net8 "VGND", 0 0, L_00000000038eba90; 1 drivers, strength-aware
+L_00000000038eb470 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372d1f0_0 .net8 "VNB", 0 0, L_00000000038eb470; 1 drivers, strength-aware
+L_00000000038ec3c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372ea50_0 .net8 "VPB", 0 0, L_00000000038ec3c0; 1 drivers, strength-aware
+L_00000000038eb2b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372dd30_0 .net8 "VPWR", 0 0, L_00000000038eb2b0; 1 drivers, strength-aware
+v000000000372d6f0_0 .net "X", 0 0, L_0000000003961620; alias, 1 drivers
+v000000000372ec30_0 .net "and0_out_X", 0 0, L_000000000395fd30; 1 drivers
+v000000000372e5f0_0 .net "nand0_out", 0 0, L_0000000003960350; 1 drivers
+v000000000372ecd0_0 .net "or0_out", 0 0, L_000000000395fe80; 1 drivers
+S_00000000027d54a0 .scope module, "sky130_fd_sc_hd__o2bb2a_4" "sky130_fd_sc_hd__o2bb2a_4" 4 85862;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o00000000036701a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372cb10_0 .net "A1_N", 0 0, o00000000036701a8; 0 drivers
+o00000000036701d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372ef50_0 .net "A2_N", 0 0, o00000000036701d8; 0 drivers
+o0000000003670208 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372eff0_0 .net "B1", 0 0, o0000000003670208; 0 drivers
+o0000000003670238 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372cc50_0 .net "B2", 0 0, o0000000003670238; 0 drivers
+L_00000000038ebb70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372f090_0 .net8 "VGND", 0 0, L_00000000038ebb70; 1 drivers, strength-aware
+L_00000000038eb7f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372fc70_0 .net8 "VNB", 0 0, L_00000000038eb7f0; 1 drivers, strength-aware
+L_00000000038eae50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037314d0_0 .net8 "VPB", 0 0, L_00000000038eae50; 1 drivers, strength-aware
+L_00000000038eb320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731430_0 .net8 "VPWR", 0 0, L_00000000038eb320; 1 drivers, strength-aware
+v0000000003730d50_0 .net "X", 0 0, L_0000000003961150; 1 drivers
+S_00000000036a2f80 .scope module, "base" "sky130_fd_sc_hd__o2bb2a" 4 85882, 4 86199 1, S_00000000027d54a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_00000000039618c0 .functor NAND 1, o00000000036701d8, o00000000036701a8, C4<1>, C4<1>;
+L_0000000003961690 .functor OR 1, o0000000003670238, o0000000003670208, C4<0>, C4<0>;
+L_00000000039603c0 .functor AND 1, L_00000000039618c0, L_0000000003961690, C4<1>, C4<1>;
+L_0000000003961150 .functor BUF 1, L_00000000039603c0, C4<0>, C4<0>, C4<0>;
+v000000000372d650_0 .net "A1_N", 0 0, o00000000036701a8; alias, 0 drivers
+v000000000372e4b0_0 .net "A2_N", 0 0, o00000000036701d8; alias, 0 drivers
+v000000000372e550_0 .net "B1", 0 0, o0000000003670208; alias, 0 drivers
+v000000000372e7d0_0 .net "B2", 0 0, o0000000003670238; alias, 0 drivers
+L_00000000038eb860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372e870_0 .net8 "VGND", 0 0, L_00000000038eb860; 1 drivers, strength-aware
+L_00000000038eb8d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372ce30_0 .net8 "VNB", 0 0, L_00000000038eb8d0; 1 drivers, strength-aware
+L_00000000038ec2e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372ca70_0 .net8 "VPB", 0 0, L_00000000038ec2e0; 1 drivers, strength-aware
+L_00000000038ec4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372eaf0_0 .net8 "VPWR", 0 0, L_00000000038ec4a0; 1 drivers, strength-aware
+v000000000372e910_0 .net "X", 0 0, L_0000000003961150; alias, 1 drivers
+v000000000372e9b0_0 .net "and0_out_X", 0 0, L_00000000039603c0; 1 drivers
+v000000000372eb90_0 .net "nand0_out", 0 0, L_00000000039618c0; 1 drivers
+v000000000372cf70_0 .net "or0_out", 0 0, L_0000000003961690; 1 drivers
+S_00000000027d72a0 .scope module, "sky130_fd_sc_hd__o2bb2ai_1" "sky130_fd_sc_hd__o2bb2ai_1" 4 101951;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o0000000003670688 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037308f0_0 .net "A1_N", 0 0, o0000000003670688; 0 drivers
+o00000000036706b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372f770_0 .net "A2_N", 0 0, o00000000036706b8; 0 drivers
+o00000000036706e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372f810_0 .net "B1", 0 0, o00000000036706e8; 0 drivers
+o0000000003670718 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372fdb0_0 .net "B2", 0 0, o0000000003670718; 0 drivers
+L_00000000038ec430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037300d0_0 .net8 "VGND", 0 0, L_00000000038ec430; 1 drivers, strength-aware
+L_00000000038eb940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372f4f0_0 .net8 "VNB", 0 0, L_00000000038eb940; 1 drivers, strength-aware
+L_00000000038ec6d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003730170_0 .net8 "VPB", 0 0, L_00000000038ec6d0; 1 drivers, strength-aware
+L_00000000038ec580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003730cb0_0 .net8 "VPWR", 0 0, L_00000000038ec580; 1 drivers, strength-aware
+v000000000372f1d0_0 .net "Y", 0 0, L_0000000003961460; 1 drivers
+S_00000000036a6280 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 101971, 4 102408 1, S_00000000027d72a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_0000000003960660 .functor NAND 1, o00000000036706b8, o0000000003670688, C4<1>, C4<1>;
+L_00000000039605f0 .functor OR 1, o0000000003670718, o00000000036706e8, C4<0>, C4<0>;
+L_0000000003961230 .functor NAND 1, L_0000000003960660, L_00000000039605f0, C4<1>, C4<1>;
+L_0000000003961460 .functor BUF 1, L_0000000003961230, C4<0>, C4<0>, C4<0>;
+v0000000003730210_0 .net "A1_N", 0 0, o0000000003670688; alias, 0 drivers
+v0000000003730490_0 .net "A2_N", 0 0, o00000000036706b8; alias, 0 drivers
+v000000000372fb30_0 .net "B1", 0 0, o00000000036706e8; alias, 0 drivers
+v000000000372f590_0 .net "B2", 0 0, o0000000003670718; alias, 0 drivers
+L_00000000038ebbe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372f6d0_0 .net8 "VGND", 0 0, L_00000000038ebbe0; 1 drivers, strength-aware
+L_00000000038ebd30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003730df0_0 .net8 "VNB", 0 0, L_00000000038ebd30; 1 drivers, strength-aware
+L_00000000038eb550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003730030_0 .net8 "VPB", 0 0, L_00000000038eb550; 1 drivers, strength-aware
+L_00000000038ec5f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372fd10_0 .net8 "VPWR", 0 0, L_00000000038ec5f0; 1 drivers, strength-aware
+v000000000372f8b0_0 .net "Y", 0 0, L_0000000003961460; alias, 1 drivers
+v000000000372fa90_0 .net "nand0_out", 0 0, L_0000000003960660; 1 drivers
+v0000000003730a30_0 .net "nand1_out_Y", 0 0, L_0000000003961230; 1 drivers
+v0000000003730fd0_0 .net "or0_out", 0 0, L_00000000039605f0; 1 drivers
+S_00000000027d4120 .scope module, "sky130_fd_sc_hd__o2bb2ai_2" "sky130_fd_sc_hd__o2bb2ai_2" 4 101831;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o0000000003670b68 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372f310_0 .net "A1_N", 0 0, o0000000003670b68; 0 drivers
+o0000000003670b98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037316b0_0 .net "A2_N", 0 0, o0000000003670b98; 0 drivers
+o0000000003670bc8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003730350_0 .net "B1", 0 0, o0000000003670bc8; 0 drivers
+o0000000003670bf8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000372f630_0 .net "B2", 0 0, o0000000003670bf8; 0 drivers
+L_00000000038ec660 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003730c10_0 .net8 "VGND", 0 0, L_00000000038ec660; 1 drivers, strength-aware
+L_00000000038ec740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037307b0_0 .net8 "VNB", 0 0, L_00000000038ec740; 1 drivers, strength-aware
+L_00000000038eb240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003730e90_0 .net8 "VPB", 0 0, L_00000000038eb240; 1 drivers, strength-aware
+L_00000000038ed850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037317f0_0 .net8 "VPWR", 0 0, L_00000000038ed850; 1 drivers, strength-aware
+v0000000003731750_0 .net "Y", 0 0, L_0000000003961850; 1 drivers
+S_00000000036a6700 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 101851, 4 102408 1, S_00000000027d4120;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_00000000039609e0 .functor NAND 1, o0000000003670b98, o0000000003670b68, C4<1>, C4<1>;
+L_0000000003960890 .functor OR 1, o0000000003670bf8, o0000000003670bc8, C4<0>, C4<0>;
+L_00000000039614d0 .functor NAND 1, L_00000000039609e0, L_0000000003960890, C4<1>, C4<1>;
+L_0000000003961850 .functor BUF 1, L_00000000039614d0, C4<0>, C4<0>, C4<0>;
+v0000000003730f30_0 .net "A1_N", 0 0, o0000000003670b68; alias, 0 drivers
+v000000000372fe50_0 .net "A2_N", 0 0, o0000000003670b98; alias, 0 drivers
+v000000000372f950_0 .net "B1", 0 0, o0000000003670bc8; alias, 0 drivers
+v000000000372fbd0_0 .net "B2", 0 0, o0000000003670bf8; alias, 0 drivers
+L_00000000038ed8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003731250_0 .net8 "VGND", 0 0, L_00000000038ed8c0; 1 drivers, strength-aware
+L_00000000038ed0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372f270_0 .net8 "VNB", 0 0, L_00000000038ed0e0; 1 drivers, strength-aware
+L_00000000038ede70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003730ad0_0 .net8 "VPB", 0 0, L_00000000038ede70; 1 drivers, strength-aware
+L_00000000038ecdd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731570_0 .net8 "VPWR", 0 0, L_00000000038ecdd0; 1 drivers, strength-aware
+v0000000003730990_0 .net "Y", 0 0, L_0000000003961850; alias, 1 drivers
+v0000000003731610_0 .net "nand0_out", 0 0, L_00000000039609e0; 1 drivers
+v0000000003730b70_0 .net "nand1_out_Y", 0 0, L_00000000039614d0; 1 drivers
+v000000000372f450_0 .net "or0_out", 0 0, L_0000000003960890; 1 drivers
+S_00000000027d75a0 .scope module, "sky130_fd_sc_hd__o2bb2ai_4" "sky130_fd_sc_hd__o2bb2ai_4" 4 102071;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+o0000000003671048 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037305d0_0 .net "A1_N", 0 0, o0000000003671048; 0 drivers
+o0000000003671078 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003730670_0 .net "A2_N", 0 0, o0000000003671078; 0 drivers
+o00000000036710a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003730710_0 .net "B1", 0 0, o00000000036710a8; 0 drivers
+o00000000036710d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003730850_0 .net "B2", 0 0, o00000000036710d8; 0 drivers
+L_00000000038ed540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037312f0_0 .net8 "VGND", 0 0, L_00000000038ed540; 1 drivers, strength-aware
+L_00000000038ecc10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003731390_0 .net8 "VNB", 0 0, L_00000000038ecc10; 1 drivers, strength-aware
+L_00000000038ecc80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003734090_0 .net8 "VPB", 0 0, L_00000000038ecc80; 1 drivers, strength-aware
+L_00000000038edee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003733870_0 .net8 "VPWR", 0 0, L_00000000038edee0; 1 drivers, strength-aware
+v00000000037323d0_0 .net "Y", 0 0, L_0000000003962340; 1 drivers
+S_00000000036a3400 .scope module, "base" "sky130_fd_sc_hd__o2bb2ai" 4 102091, 4 102408 1, S_00000000027d75a0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1_N"
+ .port_info 2 /INPUT 1 "A2_N"
+ .port_info 3 /INPUT 1 "B1"
+ .port_info 4 /INPUT 1 "B2"
+L_000000000395fef0 .functor NAND 1, o0000000003671078, o0000000003671048, C4<1>, C4<1>;
+L_0000000003963220 .functor OR 1, o00000000036710d8, o00000000036710a8, C4<0>, C4<0>;
+L_0000000003962490 .functor NAND 1, L_000000000395fef0, L_0000000003963220, C4<1>, C4<1>;
+L_0000000003962340 .functor BUF 1, L_0000000003962490, C4<0>, C4<0>, C4<0>;
+v0000000003731890_0 .net "A1_N", 0 0, o0000000003671048; alias, 0 drivers
+v000000000372f3b0_0 .net "A2_N", 0 0, o0000000003671078; alias, 0 drivers
+v000000000372f130_0 .net "B1", 0 0, o00000000036710a8; alias, 0 drivers
+v00000000037303f0_0 .net "B2", 0 0, o00000000036710d8; alias, 0 drivers
+L_00000000038eccf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000372f9f0_0 .net8 "VGND", 0 0, L_00000000038eccf0; 1 drivers, strength-aware
+L_00000000038edb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003731070_0 .net8 "VNB", 0 0, L_00000000038edb60; 1 drivers, strength-aware
+L_00000000038edbd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037311b0_0 .net8 "VPB", 0 0, L_00000000038edbd0; 1 drivers, strength-aware
+L_00000000038edf50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000372fef0_0 .net8 "VPWR", 0 0, L_00000000038edf50; 1 drivers, strength-aware
+v0000000003731110_0 .net "Y", 0 0, L_0000000003962340; alias, 1 drivers
+v000000000372ff90_0 .net "nand0_out", 0 0, L_000000000395fef0; 1 drivers
+v00000000037302b0_0 .net "nand1_out_Y", 0 0, L_0000000003962490; 1 drivers
+v0000000003730530_0 .net "or0_out", 0 0, L_0000000003963220; 1 drivers
+S_00000000027d7720 .scope module, "sky130_fd_sc_hd__o311a_1" "sky130_fd_sc_hd__o311a_1" 4 48497;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003671528 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732f10_0 .net "A1", 0 0, o0000000003671528; 0 drivers
+o0000000003671558 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037337d0_0 .net "A2", 0 0, o0000000003671558; 0 drivers
+o0000000003671588 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732510_0 .net "A3", 0 0, o0000000003671588; 0 drivers
+o00000000036715b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037328d0_0 .net "B1", 0 0, o00000000036715b8; 0 drivers
+o00000000036715e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732e70_0 .net "C1", 0 0, o00000000036715e8; 0 drivers
+L_00000000038eda80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003731a70_0 .net8 "VGND", 0 0, L_00000000038eda80; 1 drivers, strength-aware
+L_00000000038ed4d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037319d0_0 .net8 "VNB", 0 0, L_00000000038ed4d0; 1 drivers, strength-aware
+L_00000000038ee1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003733cd0_0 .net8 "VPB", 0 0, L_00000000038ee1f0; 1 drivers, strength-aware
+L_00000000038ecd60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731bb0_0 .net8 "VPWR", 0 0, L_00000000038ecd60; 1 drivers, strength-aware
+v0000000003733050_0 .net "X", 0 0, L_00000000039634c0; 1 drivers
+S_00000000036a4a80 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48519, 4 48837 1, S_00000000027d7720;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003962500 .functor OR 1, o0000000003671558, o0000000003671528, o0000000003671588, C4<0>;
+L_0000000003962570 .functor AND 1, L_0000000003962500, o00000000036715b8, o00000000036715e8, C4<1>;
+L_00000000039634c0 .functor BUF 1, L_0000000003962570, C4<0>, C4<0>, C4<0>;
+v0000000003733e10_0 .net "A1", 0 0, o0000000003671528; alias, 0 drivers
+v0000000003732790_0 .net "A2", 0 0, o0000000003671558; alias, 0 drivers
+v0000000003732470_0 .net "A3", 0 0, o0000000003671588; alias, 0 drivers
+v0000000003732830_0 .net "B1", 0 0, o00000000036715b8; alias, 0 drivers
+v0000000003732dd0_0 .net "C1", 0 0, o00000000036715e8; alias, 0 drivers
+L_00000000038ed3f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003732ab0_0 .net8 "VGND", 0 0, L_00000000038ed3f0; 1 drivers, strength-aware
+L_00000000038edd20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003733f50_0 .net8 "VNB", 0 0, L_00000000038edd20; 1 drivers, strength-aware
+L_00000000038ecac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003732c90_0 .net8 "VPB", 0 0, L_00000000038ecac0; 1 drivers, strength-aware
+L_00000000038ee3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003732fb0_0 .net8 "VPWR", 0 0, L_00000000038ee3b0; 1 drivers, strength-aware
+v0000000003733230_0 .net "X", 0 0, L_00000000039634c0; alias, 1 drivers
+v00000000037326f0_0 .net "and0_out_X", 0 0, L_0000000003962570; 1 drivers
+v0000000003733730_0 .net "or0_out", 0 0, L_0000000003962500; 1 drivers
+S_00000000027d4ba0 .scope module, "sky130_fd_sc_hd__o311a_2" "sky130_fd_sc_hd__o311a_2" 4 48371;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003671a68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732290_0 .net "A1", 0 0, o0000000003671a68; 0 drivers
+o0000000003671a98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003733190_0 .net "A2", 0 0, o0000000003671a98; 0 drivers
+o0000000003671ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732b50_0 .net "A3", 0 0, o0000000003671ac8; 0 drivers
+o0000000003671af8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732650_0 .net "B1", 0 0, o0000000003671af8; 0 drivers
+o0000000003671b28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037335f0_0 .net "C1", 0 0, o0000000003671b28; 0 drivers
+L_00000000038ee180 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003732bf0_0 .net8 "VGND", 0 0, L_00000000038ee180; 1 drivers, strength-aware
+L_00000000038edfc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003733370_0 .net8 "VNB", 0 0, L_00000000038edfc0; 1 drivers, strength-aware
+L_00000000038ed770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731f70_0 .net8 "VPB", 0 0, L_00000000038ed770; 1 drivers, strength-aware
+L_00000000038ed620 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731930_0 .net8 "VPWR", 0 0, L_00000000038ed620; 1 drivers, strength-aware
+v00000000037334b0_0 .net "X", 0 0, L_00000000039626c0; 1 drivers
+S_00000000036a7600 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48393, 4 48837 1, S_00000000027d4ba0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003962110 .functor OR 1, o0000000003671a98, o0000000003671a68, o0000000003671ac8, C4<0>;
+L_0000000003962b90 .functor AND 1, L_0000000003962110, o0000000003671af8, o0000000003671b28, C4<1>;
+L_00000000039626c0 .functor BUF 1, L_0000000003962b90, C4<0>, C4<0>, C4<0>;
+v0000000003731b10_0 .net "A1", 0 0, o0000000003671a68; alias, 0 drivers
+v0000000003732a10_0 .net "A2", 0 0, o0000000003671a98; alias, 0 drivers
+v00000000037325b0_0 .net "A3", 0 0, o0000000003671ac8; alias, 0 drivers
+v00000000037332d0_0 .net "B1", 0 0, o0000000003671af8; alias, 0 drivers
+v0000000003733410_0 .net "C1", 0 0, o0000000003671b28; alias, 0 drivers
+L_00000000038edaf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003731c50_0 .net8 "VGND", 0 0, L_00000000038edaf0; 1 drivers, strength-aware
+L_00000000038edc40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003732d30_0 .net8 "VNB", 0 0, L_00000000038edc40; 1 drivers, strength-aware
+L_00000000038ee260 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003731ed0_0 .net8 "VPB", 0 0, L_00000000038ee260; 1 drivers, strength-aware
+L_00000000038ed1c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003732970_0 .net8 "VPWR", 0 0, L_00000000038ed1c0; 1 drivers, strength-aware
+v0000000003733910_0 .net "X", 0 0, L_00000000039626c0; alias, 1 drivers
+v00000000037330f0_0 .net "and0_out_X", 0 0, L_0000000003962b90; 1 drivers
+v0000000003733550_0 .net "or0_out", 0 0, L_0000000003962110; 1 drivers
+S_00000000027d5620 .scope module, "sky130_fd_sc_hd__o311a_4" "sky130_fd_sc_hd__o311a_4" 4 48245;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003671fa8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003731d90_0 .net "A1", 0 0, o0000000003671fa8; 0 drivers
+o0000000003671fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003731e30_0 .net "A2", 0 0, o0000000003671fd8; 0 drivers
+o0000000003672008 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037320b0_0 .net "A3", 0 0, o0000000003672008; 0 drivers
+o0000000003672038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003732150_0 .net "B1", 0 0, o0000000003672038; 0 drivers
+o0000000003672068 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037321f0_0 .net "C1", 0 0, o0000000003672068; 0 drivers
+L_00000000038ed930 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003734a90_0 .net8 "VGND", 0 0, L_00000000038ed930; 1 drivers, strength-aware
+L_00000000038ee490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003735a30_0 .net8 "VNB", 0 0, L_00000000038ee490; 1 drivers, strength-aware
+L_00000000038edd90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735fd0_0 .net8 "VPB", 0 0, L_00000000038edd90; 1 drivers, strength-aware
+L_00000000038ee2d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735210_0 .net8 "VPWR", 0 0, L_00000000038ee2d0; 1 drivers, strength-aware
+v0000000003734bd0_0 .net "X", 0 0, L_0000000003962f10; 1 drivers
+S_00000000036a3700 .scope module, "base" "sky130_fd_sc_hd__o311a" 4 48267, 4 48837 1, S_00000000027d5620;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003962e30 .functor OR 1, o0000000003671fd8, o0000000003671fa8, o0000000003672008, C4<0>;
+L_0000000003962c00 .functor AND 1, L_0000000003962e30, o0000000003672038, o0000000003672068, C4<1>;
+L_0000000003962f10 .functor BUF 1, L_0000000003962c00, C4<0>, C4<0>, C4<0>;
+v0000000003733690_0 .net "A1", 0 0, o0000000003671fa8; alias, 0 drivers
+v0000000003733eb0_0 .net "A2", 0 0, o0000000003671fd8; alias, 0 drivers
+v00000000037339b0_0 .net "A3", 0 0, o0000000003672008; alias, 0 drivers
+v0000000003733a50_0 .net "B1", 0 0, o0000000003672038; alias, 0 drivers
+v0000000003733af0_0 .net "C1", 0 0, o0000000003672068; alias, 0 drivers
+L_00000000038ecb30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003732010_0 .net8 "VGND", 0 0, L_00000000038ecb30; 1 drivers, strength-aware
+L_00000000038ece40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003733b90_0 .net8 "VNB", 0 0, L_00000000038ece40; 1 drivers, strength-aware
+L_00000000038ecba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003732330_0 .net8 "VPB", 0 0, L_00000000038ecba0; 1 drivers, strength-aware
+L_00000000038ede00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003733c30_0 .net8 "VPWR", 0 0, L_00000000038ede00; 1 drivers, strength-aware
+v0000000003731cf0_0 .net "X", 0 0, L_0000000003962f10; alias, 1 drivers
+v0000000003733d70_0 .net "and0_out_X", 0 0, L_0000000003962c00; 1 drivers
+v0000000003733ff0_0 .net "or0_out", 0 0, L_0000000003962e30; 1 drivers
+S_00000000027d4d20 .scope module, "sky130_fd_sc_hd__o311ai_0" "sky130_fd_sc_hd__o311ai_0" 4 93948;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o00000000036724e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003734630_0 .net "A1", 0 0, o00000000036724e8; 0 drivers
+o0000000003672518 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003735c10_0 .net "A2", 0 0, o0000000003672518; 0 drivers
+o0000000003672548 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003734f90_0 .net "A3", 0 0, o0000000003672548; 0 drivers
+o0000000003672578 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037353f0_0 .net "B1", 0 0, o0000000003672578; 0 drivers
+o00000000036725a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003735cb0_0 .net "C1", 0 0, o00000000036725a8; 0 drivers
+L_00000000038eceb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003734450_0 .net8 "VGND", 0 0, L_00000000038eceb0; 1 drivers, strength-aware
+L_00000000038ed5b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003734270_0 .net8 "VNB", 0 0, L_00000000038ed5b0; 1 drivers, strength-aware
+L_00000000038ed7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037352b0_0 .net8 "VPB", 0 0, L_00000000038ed7e0; 1 drivers, strength-aware
+L_00000000038ecf20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003734e50_0 .net8 "VPWR", 0 0, L_00000000038ecf20; 1 drivers, strength-aware
+v0000000003734590_0 .net "Y", 0 0, L_0000000003961cb0; 1 drivers
+S_00000000036a3880 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 93970, 4 93818 1, S_00000000027d4d20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003963450 .functor OR 1, o0000000003672518, o00000000036724e8, o0000000003672548, C4<0>;
+L_0000000003963370 .functor NAND 1, o00000000036725a8, L_0000000003963450, o0000000003672578, C4<1>;
+L_0000000003961cb0 .functor BUF 1, L_0000000003963370, C4<0>, C4<0>, C4<0>;
+v00000000037350d0_0 .net "A1", 0 0, o00000000036724e8; alias, 0 drivers
+v00000000037344f0_0 .net "A2", 0 0, o0000000003672518; alias, 0 drivers
+v0000000003734950_0 .net "A3", 0 0, o0000000003672548; alias, 0 drivers
+v00000000037341d0_0 .net "B1", 0 0, o0000000003672578; alias, 0 drivers
+v0000000003734130_0 .net "C1", 0 0, o00000000036725a8; alias, 0 drivers
+L_00000000038ed9a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003735170_0 .net8 "VGND", 0 0, L_00000000038ed9a0; 1 drivers, strength-aware
+L_00000000038eda10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003735ad0_0 .net8 "VNB", 0 0, L_00000000038eda10; 1 drivers, strength-aware
+L_00000000038ecf90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735e90_0 .net8 "VPB", 0 0, L_00000000038ecf90; 1 drivers, strength-aware
+L_00000000038ee340 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735490_0 .net8 "VPWR", 0 0, L_00000000038ee340; 1 drivers, strength-aware
+v0000000003735f30_0 .net "Y", 0 0, L_0000000003961cb0; alias, 1 drivers
+v0000000003735d50_0 .net "nand0_out_Y", 0 0, L_0000000003963370; 1 drivers
+v0000000003735b70_0 .net "or0_out", 0 0, L_0000000003963450; 1 drivers
+S_00000000027d7a20 .scope module, "sky130_fd_sc_hd__o311ai_1" "sky130_fd_sc_hd__o311ai_1" 4 94074;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003672a28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003734770_0 .net "A1", 0 0, o0000000003672a28; 0 drivers
+o0000000003672a58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037343b0_0 .net "A2", 0 0, o0000000003672a58; 0 drivers
+o0000000003672a88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037348b0_0 .net "A3", 0 0, o0000000003672a88; 0 drivers
+o0000000003672ab8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037364d0_0 .net "B1", 0 0, o0000000003672ab8; 0 drivers
+o0000000003672ae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003735030_0 .net "C1", 0 0, o0000000003672ae8; 0 drivers
+L_00000000038ed000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003736070_0 .net8 "VGND", 0 0, L_00000000038ed000; 1 drivers, strength-aware
+L_00000000038ed070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003735710_0 .net8 "VNB", 0 0, L_00000000038ed070; 1 drivers, strength-aware
+L_00000000038ed150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037357b0_0 .net8 "VPB", 0 0, L_00000000038ed150; 1 drivers, strength-aware
+L_00000000038ed460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735850_0 .net8 "VPWR", 0 0, L_00000000038ed460; 1 drivers, strength-aware
+v0000000003734b30_0 .net "Y", 0 0, L_0000000003962ea0; 1 drivers
+S_00000000036a7180 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 94096, 4 93818 1, S_00000000027d7a20;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003962c70 .functor OR 1, o0000000003672a58, o0000000003672a28, o0000000003672a88, C4<0>;
+L_00000000039622d0 .functor NAND 1, o0000000003672ae8, L_0000000003962c70, o0000000003672ab8, C4<1>;
+L_0000000003962ea0 .functor BUF 1, L_00000000039622d0, C4<0>, C4<0>, C4<0>;
+v0000000003734310_0 .net "A1", 0 0, o0000000003672a28; alias, 0 drivers
+v00000000037367f0_0 .net "A2", 0 0, o0000000003672a58; alias, 0 drivers
+v0000000003736750_0 .net "A3", 0 0, o0000000003672a88; alias, 0 drivers
+v0000000003735350_0 .net "B1", 0 0, o0000000003672ab8; alias, 0 drivers
+v00000000037355d0_0 .net "C1", 0 0, o0000000003672ae8; alias, 0 drivers
+L_00000000038ee030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037346d0_0 .net8 "VGND", 0 0, L_00000000038ee030; 1 drivers, strength-aware
+L_00000000038ed310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003735530_0 .net8 "VNB", 0 0, L_00000000038ed310; 1 drivers, strength-aware
+L_00000000038edcb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003735990_0 .net8 "VPB", 0 0, L_00000000038edcb0; 1 drivers, strength-aware
+L_00000000038ee420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003734810_0 .net8 "VPWR", 0 0, L_00000000038ee420; 1 drivers, strength-aware
+v0000000003735670_0 .net "Y", 0 0, L_0000000003962ea0; alias, 1 drivers
+v0000000003735df0_0 .net "nand0_out_Y", 0 0, L_00000000039622d0; 1 drivers
+v00000000037361b0_0 .net "or0_out", 0 0, L_0000000003962c70; 1 drivers
+S_00000000027d7ba0 .scope module, "sky130_fd_sc_hd__o311ai_2" "sky130_fd_sc_hd__o311ai_2" 4 94200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o0000000003672f68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003736890_0 .net "A1", 0 0, o0000000003672f68; 0 drivers
+o0000000003672f98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003736610_0 .net "A2", 0 0, o0000000003672f98; 0 drivers
+o0000000003672fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037366b0_0 .net "A3", 0 0, o0000000003672fc8; 0 drivers
+o0000000003672ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037371f0_0 .net "B1", 0 0, o0000000003672ff8; 0 drivers
+o0000000003673028 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037380f0_0 .net "C1", 0 0, o0000000003673028; 0 drivers
+L_00000000038ec900 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003738550_0 .net8 "VGND", 0 0, L_00000000038ec900; 1 drivers, strength-aware
+L_00000000038ec970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003738730_0 .net8 "VNB", 0 0, L_00000000038ec970; 1 drivers, strength-aware
+L_00000000038ed230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003737a10_0 .net8 "VPB", 0 0, L_00000000038ed230; 1 drivers, strength-aware
+L_00000000038ee0a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003737ab0_0 .net8 "VPWR", 0 0, L_00000000038ee0a0; 1 drivers, strength-aware
+v00000000037384b0_0 .net "Y", 0 0, L_00000000039623b0; 1 drivers
+S_00000000036a3d00 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 94222, 4 93818 1, S_00000000027d7ba0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_0000000003962f80 .functor OR 1, o0000000003672f98, o0000000003672f68, o0000000003672fc8, C4<0>;
+L_0000000003962ce0 .functor NAND 1, o0000000003673028, L_0000000003962f80, o0000000003672ff8, C4<1>;
+L_00000000039623b0 .functor BUF 1, L_0000000003962ce0, C4<0>, C4<0>, C4<0>;
+v00000000037349f0_0 .net "A1", 0 0, o0000000003672f68; alias, 0 drivers
+v0000000003734ef0_0 .net "A2", 0 0, o0000000003672f98; alias, 0 drivers
+v00000000037358f0_0 .net "A3", 0 0, o0000000003672fc8; alias, 0 drivers
+v0000000003734c70_0 .net "B1", 0 0, o0000000003672ff8; alias, 0 drivers
+v0000000003734d10_0 .net "C1", 0 0, o0000000003673028; alias, 0 drivers
+L_00000000038ed2a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003736110_0 .net8 "VGND", 0 0, L_00000000038ed2a0; 1 drivers, strength-aware
+L_00000000038ee110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003734db0_0 .net8 "VNB", 0 0, L_00000000038ee110; 1 drivers, strength-aware
+L_00000000038ec9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003736250_0 .net8 "VPB", 0 0, L_00000000038ec9e0; 1 drivers, strength-aware
+L_00000000038ed380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037362f0_0 .net8 "VPWR", 0 0, L_00000000038ed380; 1 drivers, strength-aware
+v0000000003736390_0 .net "Y", 0 0, L_00000000039623b0; alias, 1 drivers
+v0000000003736430_0 .net "nand0_out_Y", 0 0, L_0000000003962ce0; 1 drivers
+v0000000003736570_0 .net "or0_out", 0 0, L_0000000003962f80; 1 drivers
+S_000000000272f8c0 .scope module, "sky130_fd_sc_hd__o311ai_4" "sky130_fd_sc_hd__o311ai_4" 4 93478;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+o00000000036734a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037376f0_0 .net "A1", 0 0, o00000000036734a8; 0 drivers
+o00000000036734d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738c30_0 .net "A2", 0 0, o00000000036734d8; 0 drivers
+o0000000003673508 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738410_0 .net "A3", 0 0, o0000000003673508; 0 drivers
+o0000000003673538 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003737d30_0 .net "B1", 0 0, o0000000003673538; 0 drivers
+o0000000003673568 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003737e70_0 .net "C1", 0 0, o0000000003673568; 0 drivers
+L_00000000038eca50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003739090_0 .net8 "VGND", 0 0, L_00000000038eca50; 1 drivers, strength-aware
+L_00000000038ed690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003738870_0 .net8 "VNB", 0 0, L_00000000038ed690; 1 drivers, strength-aware
+L_00000000038ed700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037373d0_0 .net8 "VPB", 0 0, L_00000000038ed700; 1 drivers, strength-aware
+L_00000000038ef370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003736bb0_0 .net8 "VPWR", 0 0, L_00000000038ef370; 1 drivers, strength-aware
+v0000000003736930_0 .net "Y", 0 0, L_0000000003963290; 1 drivers
+S_00000000036a6880 .scope module, "base" "sky130_fd_sc_hd__o311ai" 4 93500, 4 93818 1, S_000000000272f8c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "C1"
+L_00000000039625e0 .functor OR 1, o00000000036734d8, o00000000036734a8, o0000000003673508, C4<0>;
+L_0000000003962030 .functor NAND 1, o0000000003673568, L_00000000039625e0, o0000000003673538, C4<1>;
+L_0000000003963290 .functor BUF 1, L_0000000003962030, C4<0>, C4<0>, C4<0>;
+v0000000003737650_0 .net "A1", 0 0, o00000000036734a8; alias, 0 drivers
+v0000000003736c50_0 .net "A2", 0 0, o00000000036734d8; alias, 0 drivers
+v0000000003737290_0 .net "A3", 0 0, o0000000003673508; alias, 0 drivers
+v0000000003737bf0_0 .net "B1", 0 0, o0000000003673538; alias, 0 drivers
+v0000000003736cf0_0 .net "C1", 0 0, o0000000003673568; alias, 0 drivers
+L_00000000038ef680 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037385f0_0 .net8 "VGND", 0 0, L_00000000038ef680; 1 drivers, strength-aware
+L_00000000038ef1b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003737fb0_0 .net8 "VNB", 0 0, L_00000000038ef1b0; 1 drivers, strength-aware
+L_00000000038eeb90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738190_0 .net8 "VPB", 0 0, L_00000000038eeb90; 1 drivers, strength-aware
+L_00000000038ee9d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738ff0_0 .net8 "VPWR", 0 0, L_00000000038ee9d0; 1 drivers, strength-aware
+v0000000003738f50_0 .net "Y", 0 0, L_0000000003963290; alias, 1 drivers
+v0000000003737330_0 .net "nand0_out_Y", 0 0, L_0000000003962030; 1 drivers
+v0000000003737dd0_0 .net "or0_out", 0 0, L_00000000039625e0; 1 drivers
+S_0000000002730c40 .scope module, "sky130_fd_sc_hd__o31a_1" "sky130_fd_sc_hd__o31a_1" 4 76792;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o00000000036739e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003737510_0 .net "A1", 0 0, o00000000036739e8; 0 drivers
+o0000000003673a18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037375b0_0 .net "A2", 0 0, o0000000003673a18; 0 drivers
+o0000000003673a48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003736f70_0 .net "A3", 0 0, o0000000003673a48; 0 drivers
+o0000000003673a78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738370_0 .net "B1", 0 0, o0000000003673a78; 0 drivers
+L_00000000038ef840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003737150_0 .net8 "VGND", 0 0, L_00000000038ef840; 1 drivers, strength-aware
+L_00000000038efd10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003736a70_0 .net8 "VNB", 0 0, L_00000000038efd10; 1 drivers, strength-aware
+L_00000000038ef300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738cd0_0 .net8 "VPB", 0 0, L_00000000038ef300; 1 drivers, strength-aware
+L_00000000038ee880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003736d90_0 .net8 "VPWR", 0 0, L_00000000038ee880; 1 drivers, strength-aware
+v0000000003736e30_0 .net "X", 0 0, L_0000000003962ff0; 1 drivers
+S_00000000036a7a80 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76812, 4 77123 1, S_0000000002730c40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_0000000003962650 .functor OR 1, o0000000003673a18, o00000000036739e8, o0000000003673a48, C4<0>;
+L_0000000003962d50 .functor AND 1, L_0000000003962650, o0000000003673a78, C4<1>, C4<1>;
+L_0000000003962ff0 .functor BUF 1, L_0000000003962d50, C4<0>, C4<0>, C4<0>;
+v0000000003737830_0 .net "A1", 0 0, o00000000036739e8; alias, 0 drivers
+v0000000003737470_0 .net "A2", 0 0, o0000000003673a18; alias, 0 drivers
+v0000000003737f10_0 .net "A3", 0 0, o0000000003673a48; alias, 0 drivers
+v0000000003737b50_0 .net "B1", 0 0, o0000000003673a78; alias, 0 drivers
+L_00000000038ef4c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037369d0_0 .net8 "VGND", 0 0, L_00000000038ef4c0; 1 drivers, strength-aware
+L_00000000038ef220 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003736ed0_0 .net8 "VNB", 0 0, L_00000000038ef220; 1 drivers, strength-aware
+L_00000000038ee730 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003736b10_0 .net8 "VPB", 0 0, L_00000000038ee730; 1 drivers, strength-aware
+L_00000000038ee960 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738230_0 .net8 "VPWR", 0 0, L_00000000038ee960; 1 drivers, strength-aware
+v0000000003737790_0 .net "X", 0 0, L_0000000003962ff0; alias, 1 drivers
+v0000000003738050_0 .net "and0_out_X", 0 0, L_0000000003962d50; 1 drivers
+v00000000037382d0_0 .net "or0_out", 0 0, L_0000000003962650; 1 drivers
+S_000000000272fa40 .scope module, "sky130_fd_sc_hd__o31a_2" "sky130_fd_sc_hd__o31a_2" 4 76672;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003673e98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003737970_0 .net "A1", 0 0, o0000000003673e98; 0 drivers
+o0000000003673ec8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738d70_0 .net "A2", 0 0, o0000000003673ec8; 0 drivers
+o0000000003673ef8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738e10_0 .net "A3", 0 0, o0000000003673ef8; 0 drivers
+o0000000003673f28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003738eb0_0 .net "B1", 0 0, o0000000003673f28; 0 drivers
+L_00000000038f0090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003739590_0 .net8 "VGND", 0 0, L_00000000038f0090; 1 drivers, strength-aware
+L_00000000038ee500 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373aa30_0 .net8 "VNB", 0 0, L_00000000038ee500; 1 drivers, strength-aware
+L_00000000038eee30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373a8f0_0 .net8 "VPB", 0 0, L_00000000038eee30; 1 drivers, strength-aware
+L_00000000038ef920 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739d10_0 .net8 "VPWR", 0 0, L_00000000038ef920; 1 drivers, strength-aware
+v0000000003739c70_0 .net "X", 0 0, L_0000000003963060; 1 drivers
+S_00000000036a3a00 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76692, 4 77123 1, S_000000000272fa40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_00000000039620a0 .functor OR 1, o0000000003673ec8, o0000000003673e98, o0000000003673ef8, C4<0>;
+L_0000000003962180 .functor AND 1, L_00000000039620a0, o0000000003673f28, C4<1>, C4<1>;
+L_0000000003963060 .functor BUF 1, L_0000000003962180, C4<0>, C4<0>, C4<0>;
+v0000000003738690_0 .net "A1", 0 0, o0000000003673e98; alias, 0 drivers
+v0000000003737c90_0 .net "A2", 0 0, o0000000003673ec8; alias, 0 drivers
+v00000000037387d0_0 .net "A3", 0 0, o0000000003673ef8; alias, 0 drivers
+v0000000003738910_0 .net "B1", 0 0, o0000000003673f28; alias, 0 drivers
+L_00000000038ef5a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037389b0_0 .net8 "VGND", 0 0, L_00000000038ef5a0; 1 drivers, strength-aware
+L_00000000038ee570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003738a50_0 .net8 "VNB", 0 0, L_00000000038ee570; 1 drivers, strength-aware
+L_00000000038eeea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738af0_0 .net8 "VPB", 0 0, L_00000000038eeea0; 1 drivers, strength-aware
+L_00000000038ef610 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003738b90_0 .net8 "VPWR", 0 0, L_00000000038ef610; 1 drivers, strength-aware
+v00000000037378d0_0 .net "X", 0 0, L_0000000003963060; alias, 1 drivers
+v0000000003737010_0 .net "and0_out_X", 0 0, L_0000000003962180; 1 drivers
+v00000000037370b0_0 .net "or0_out", 0 0, L_00000000039620a0; 1 drivers
+S_0000000002733040 .scope module, "sky130_fd_sc_hd__o31a_4" "sky130_fd_sc_hd__o31a_4" 4 76552;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003674348 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003739db0_0 .net "A1", 0 0, o0000000003674348; 0 drivers
+o0000000003674378 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373adf0_0 .net "A2", 0 0, o0000000003674378; 0 drivers
+o00000000036743a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373b430_0 .net "A3", 0 0, o00000000036743a8; 0 drivers
+o00000000036743d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003739810_0 .net "B1", 0 0, o00000000036743d8; 0 drivers
+L_00000000038ee7a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373b4d0_0 .net8 "VGND", 0 0, L_00000000038ee7a0; 1 drivers, strength-aware
+L_00000000038ef290 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373b070_0 .net8 "VNB", 0 0, L_00000000038ef290; 1 drivers, strength-aware
+L_00000000038eec00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373b1b0_0 .net8 "VPB", 0 0, L_00000000038eec00; 1 drivers, strength-aware
+L_00000000038efbc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739a90_0 .net8 "VPWR", 0 0, L_00000000038efbc0; 1 drivers, strength-aware
+v0000000003739e50_0 .net "X", 0 0, L_0000000003963300; 1 drivers
+S_00000000036a6b80 .scope module, "base" "sky130_fd_sc_hd__o31a" 4 76572, 4 77123 1, S_0000000002733040;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_0000000003961e70 .functor OR 1, o0000000003674378, o0000000003674348, o00000000036743a8, C4<0>;
+L_0000000003962880 .functor AND 1, L_0000000003961e70, o00000000036743d8, C4<1>, C4<1>;
+L_0000000003963300 .functor BUF 1, L_0000000003962880, C4<0>, C4<0>, C4<0>;
+v000000000373acb0_0 .net "A1", 0 0, o0000000003674348; alias, 0 drivers
+v000000000373a990_0 .net "A2", 0 0, o0000000003674378; alias, 0 drivers
+v000000000373ab70_0 .net "A3", 0 0, o00000000036743a8; alias, 0 drivers
+v000000000373aad0_0 .net "B1", 0 0, o00000000036743d8; alias, 0 drivers
+L_00000000038eeab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373ae90_0 .net8 "VGND", 0 0, L_00000000038eeab0; 1 drivers, strength-aware
+L_00000000038ef3e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373a350_0 .net8 "VNB", 0 0, L_00000000038ef3e0; 1 drivers, strength-aware
+L_00000000038eef10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373af30_0 .net8 "VPB", 0 0, L_00000000038eef10; 1 drivers, strength-aware
+L_00000000038ee5e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373ad50_0 .net8 "VPWR", 0 0, L_00000000038ee5e0; 1 drivers, strength-aware
+v000000000373ac10_0 .net "X", 0 0, L_0000000003963300; alias, 1 drivers
+v000000000373afd0_0 .net "and0_out_X", 0 0, L_0000000003962880; 1 drivers
+v0000000003739b30_0 .net "or0_out", 0 0, L_0000000003961e70; 1 drivers
+S_0000000002730ac0 .scope module, "sky130_fd_sc_hd__o31ai_1" "sky130_fd_sc_hd__o31ai_1" 4 67077;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o00000000036747f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373b110_0 .net "A1", 0 0, o00000000036747f8; 0 drivers
+o0000000003674828 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373a7b0_0 .net "A2", 0 0, o0000000003674828; 0 drivers
+o0000000003674858 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037391d0_0 .net "A3", 0 0, o0000000003674858; 0 drivers
+o0000000003674888 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373a710_0 .net "B1", 0 0, o0000000003674888; 0 drivers
+L_00000000038eeb20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373a0d0_0 .net8 "VGND", 0 0, L_00000000038eeb20; 1 drivers, strength-aware
+L_00000000038eef80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373a210_0 .net8 "VNB", 0 0, L_00000000038eef80; 1 drivers, strength-aware
+L_00000000038eeff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739770_0 .net8 "VPB", 0 0, L_00000000038eeff0; 1 drivers, strength-aware
+L_00000000038efae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373a3f0_0 .net8 "VPWR", 0 0, L_00000000038efae0; 1 drivers, strength-aware
+v000000000373a670_0 .net "Y", 0 0, L_0000000003961b60; 1 drivers
+S_00000000036a3b80 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67097, 4 66952 1, S_0000000002730ac0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_0000000003962dc0 .functor OR 1, o0000000003674828, o00000000036747f8, o0000000003674858, C4<0>;
+L_00000000039621f0 .functor NAND 1, o0000000003674888, L_0000000003962dc0, C4<1>, C4<1>;
+L_0000000003961b60 .functor BUF 1, L_00000000039621f0, C4<0>, C4<0>, C4<0>;
+v000000000373b570_0 .net "A1", 0 0, o00000000036747f8; alias, 0 drivers
+v000000000373a170_0 .net "A2", 0 0, o0000000003674828; alias, 0 drivers
+v000000000373b610_0 .net "A3", 0 0, o0000000003674858; alias, 0 drivers
+v0000000003739f90_0 .net "B1", 0 0, o0000000003674888; alias, 0 drivers
+L_00000000038efca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373a030_0 .net8 "VGND", 0 0, L_00000000038efca0; 1 drivers, strength-aware
+L_00000000038ef8b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003739bd0_0 .net8 "VNB", 0 0, L_00000000038ef8b0; 1 drivers, strength-aware
+L_00000000038ef060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373b7f0_0 .net8 "VPB", 0 0, L_00000000038ef060; 1 drivers, strength-aware
+L_00000000038efed0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739630_0 .net8 "VPWR", 0 0, L_00000000038efed0; 1 drivers, strength-aware
+v000000000373a2b0_0 .net "Y", 0 0, L_0000000003961b60; alias, 1 drivers
+v0000000003739ef0_0 .net "nand0_out_Y", 0 0, L_00000000039621f0; 1 drivers
+v00000000037396d0_0 .net "or0_out", 0 0, L_0000000003962dc0; 1 drivers
+S_0000000002732ec0 .scope module, "sky130_fd_sc_hd__o31ai_2" "sky130_fd_sc_hd__o31ai_2" 4 67197;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003674ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373b890_0 .net "A1", 0 0, o0000000003674ca8; 0 drivers
+o0000000003674cd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037398b0_0 .net "A2", 0 0, o0000000003674cd8; 0 drivers
+o0000000003674d08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003739130_0 .net "A3", 0 0, o0000000003674d08; 0 drivers
+o0000000003674d38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003739310_0 .net "B1", 0 0, o0000000003674d38; 0 drivers
+L_00000000038efc30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037394f0_0 .net8 "VGND", 0 0, L_00000000038efc30; 1 drivers, strength-aware
+L_00000000038ef140 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037393b0_0 .net8 "VNB", 0 0, L_00000000038ef140; 1 drivers, strength-aware
+L_00000000038ef0d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739450_0 .net8 "VPB", 0 0, L_00000000038ef0d0; 1 drivers, strength-aware
+L_00000000038eec70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003739950_0 .net8 "VPWR", 0 0, L_00000000038eec70; 1 drivers, strength-aware
+v000000000373c470_0 .net "Y", 0 0, L_00000000039633e0; 1 drivers
+S_00000000036a3e80 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67217, 4 66952 1, S_0000000002732ec0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_0000000003961930 .functor OR 1, o0000000003674cd8, o0000000003674ca8, o0000000003674d08, C4<0>;
+L_0000000003962420 .functor NAND 1, o0000000003674d38, L_0000000003961930, C4<1>, C4<1>;
+L_00000000039633e0 .functor BUF 1, L_0000000003962420, C4<0>, C4<0>, C4<0>;
+v0000000003739270_0 .net "A1", 0 0, o0000000003674ca8; alias, 0 drivers
+v000000000373b250_0 .net "A2", 0 0, o0000000003674cd8; alias, 0 drivers
+v00000000037399f0_0 .net "A3", 0 0, o0000000003674d08; alias, 0 drivers
+v000000000373b6b0_0 .net "B1", 0 0, o0000000003674d38; alias, 0 drivers
+L_00000000038eece0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373b2f0_0 .net8 "VGND", 0 0, L_00000000038eece0; 1 drivers, strength-aware
+L_00000000038efd80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373a490_0 .net8 "VNB", 0 0, L_00000000038efd80; 1 drivers, strength-aware
+L_00000000038ef450 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373a530_0 .net8 "VPB", 0 0, L_00000000038ef450; 1 drivers, strength-aware
+L_00000000038ef760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373a5d0_0 .net8 "VPWR", 0 0, L_00000000038ef760; 1 drivers, strength-aware
+v000000000373b390_0 .net "Y", 0 0, L_00000000039633e0; alias, 1 drivers
+v000000000373b750_0 .net "nand0_out_Y", 0 0, L_0000000003962420; 1 drivers
+v000000000373a850_0 .net "or0_out", 0 0, L_0000000003961930; 1 drivers
+S_000000000272fec0 .scope module, "sky130_fd_sc_hd__o31ai_4" "sky130_fd_sc_hd__o31ai_4" 4 67317;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+o0000000003675158 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373c0b0_0 .net "A1", 0 0, o0000000003675158; 0 drivers
+o0000000003675188 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373c330_0 .net "A2", 0 0, o0000000003675188; 0 drivers
+o00000000036751b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373deb0_0 .net "A3", 0 0, o00000000036751b8; 0 drivers
+o00000000036751e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373bed0_0 .net "B1", 0 0, o00000000036751e8; 0 drivers
+L_00000000038ef530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373c5b0_0 .net8 "VGND", 0 0, L_00000000038ef530; 1 drivers, strength-aware
+L_00000000038eed50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373d190_0 .net8 "VNB", 0 0, L_00000000038eed50; 1 drivers, strength-aware
+L_00000000038ef6f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373cbf0_0 .net8 "VPB", 0 0, L_00000000038ef6f0; 1 drivers, strength-aware
+L_00000000038efa00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373d370_0 .net8 "VPWR", 0 0, L_00000000038efa00; 1 drivers, strength-aware
+v000000000373cfb0_0 .net "Y", 0 0, L_00000000039631b0; 1 drivers
+S_00000000036a4000 .scope module, "base" "sky130_fd_sc_hd__o31ai" 4 67337, 4 66952 1, S_000000000272fec0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+L_00000000039630d0 .functor OR 1, o0000000003675188, o0000000003675158, o00000000036751b8, C4<0>;
+L_0000000003963140 .functor NAND 1, o00000000036751e8, L_00000000039630d0, C4<1>, C4<1>;
+L_00000000039631b0 .functor BUF 1, L_0000000003963140, C4<0>, C4<0>, C4<0>;
+v000000000373dd70_0 .net "A1", 0 0, o0000000003675158; alias, 0 drivers
+v000000000373daf0_0 .net "A2", 0 0, o0000000003675188; alias, 0 drivers
+v000000000373d870_0 .net "A3", 0 0, o00000000036751b8; alias, 0 drivers
+v000000000373c970_0 .net "B1", 0 0, o00000000036751e8; alias, 0 drivers
+L_00000000038ee650 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373d4b0_0 .net8 "VGND", 0 0, L_00000000038ee650; 1 drivers, strength-aware
+L_00000000038ee6c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373d0f0_0 .net8 "VNB", 0 0, L_00000000038ee6c0; 1 drivers, strength-aware
+L_00000000038effb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373c830_0 .net8 "VPB", 0 0, L_00000000038effb0; 1 drivers, strength-aware
+L_00000000038ef7d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373ca10_0 .net8 "VPWR", 0 0, L_00000000038ef7d0; 1 drivers, strength-aware
+v000000000373d2d0_0 .net "Y", 0 0, L_00000000039631b0; alias, 1 drivers
+v000000000373c510_0 .net "nand0_out_Y", 0 0, L_0000000003963140; 1 drivers
+v000000000373cb50_0 .net "or0_out", 0 0, L_00000000039630d0; 1 drivers
+S_000000000272f2c0 .scope module, "sky130_fd_sc_hd__o32a_1" "sky130_fd_sc_hd__o32a_1" 4 45369;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003675608 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373dff0_0 .net "A1", 0 0, o0000000003675608; 0 drivers
+o0000000003675638 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373e090_0 .net "A2", 0 0, o0000000003675638; 0 drivers
+o0000000003675668 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373cab0_0 .net "A3", 0 0, o0000000003675668; 0 drivers
+o0000000003675698 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373c290_0 .net "B1", 0 0, o0000000003675698; 0 drivers
+o00000000036756c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373be30_0 .net "B2", 0 0, o00000000036756c8; 0 drivers
+L_00000000038efa70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373cd30_0 .net8 "VGND", 0 0, L_00000000038efa70; 1 drivers, strength-aware
+L_00000000038ee8f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373c6f0_0 .net8 "VNB", 0 0, L_00000000038ee8f0; 1 drivers, strength-aware
+L_00000000038ef990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373d910_0 .net8 "VPB", 0 0, L_00000000038ef990; 1 drivers, strength-aware
+L_00000000038ee810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373ce70_0 .net8 "VPWR", 0 0, L_00000000038ee810; 1 drivers, strength-aware
+v000000000373dcd0_0 .net "X", 0 0, L_0000000003961bd0; 1 drivers
+S_00000000036a4180 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45391, 4 45841 1, S_000000000272f2c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_00000000039619a0 .functor OR 1, o0000000003675638, o0000000003675608, o0000000003675668, C4<0>;
+L_0000000003961a10 .functor OR 1, o00000000036756c8, o0000000003675698, C4<0>, C4<0>;
+L_0000000003961d20 .functor AND 1, L_00000000039619a0, L_0000000003961a10, C4<1>, C4<1>;
+L_0000000003961bd0 .functor BUF 1, L_0000000003961d20, C4<0>, C4<0>, C4<0>;
+v000000000373bd90_0 .net "A1", 0 0, o0000000003675608; alias, 0 drivers
+v000000000373b9d0_0 .net "A2", 0 0, o0000000003675638; alias, 0 drivers
+v000000000373d410_0 .net "A3", 0 0, o0000000003675668; alias, 0 drivers
+v000000000373d050_0 .net "B1", 0 0, o0000000003675698; alias, 0 drivers
+v000000000373d230_0 .net "B2", 0 0, o00000000036756c8; alias, 0 drivers
+L_00000000038efb50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373bc50_0 .net8 "VGND", 0 0, L_00000000038efb50; 1 drivers, strength-aware
+L_00000000038eea40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373df50_0 .net8 "VNB", 0 0, L_00000000038eea40; 1 drivers, strength-aware
+L_00000000038efdf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373c3d0_0 .net8 "VPB", 0 0, L_00000000038efdf0; 1 drivers, strength-aware
+L_00000000038efe60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373cdd0_0 .net8 "VPWR", 0 0, L_00000000038efe60; 1 drivers, strength-aware
+v000000000373c150_0 .net "X", 0 0, L_0000000003961bd0; alias, 1 drivers
+v000000000373da50_0 .net "and0_out_X", 0 0, L_0000000003961d20; 1 drivers
+v000000000373cc90_0 .net "or0_out", 0 0, L_00000000039619a0; 1 drivers
+v000000000373bcf0_0 .net "or1_out", 0 0, L_0000000003961a10; 1 drivers
+S_000000000272fd40 .scope module, "sky130_fd_sc_hd__o32a_4" "sky130_fd_sc_hd__o32a_4" 4 45495;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003675b78 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373d7d0_0 .net "A1", 0 0, o0000000003675b78; 0 drivers
+o0000000003675ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373d9b0_0 .net "A2", 0 0, o0000000003675ba8; 0 drivers
+o0000000003675bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373bb10_0 .net "A3", 0 0, o0000000003675bd8; 0 drivers
+o0000000003675c08 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373db90_0 .net "B1", 0 0, o0000000003675c08; 0 drivers
+o0000000003675c38 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373c650_0 .net "B2", 0 0, o0000000003675c38; 0 drivers
+L_00000000038f0020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373dc30_0 .net8 "VGND", 0 0, L_00000000038f0020; 1 drivers, strength-aware
+L_00000000038eff40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373c010_0 .net8 "VNB", 0 0, L_00000000038eff40; 1 drivers, strength-aware
+L_00000000038eedc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373ef90_0 .net8 "VPB", 0 0, L_00000000038eedc0; 1 drivers, strength-aware
+L_00000000038f11a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373f670_0 .net8 "VPWR", 0 0, L_00000000038f11a0; 1 drivers, strength-aware
+v000000000373e270_0 .net "X", 0 0, L_0000000003961af0; 1 drivers
+S_00000000036a7000 .scope module, "base" "sky130_fd_sc_hd__o32a" 4 45517, 4 45841 1, S_000000000272fd40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_0000000003962810 .functor OR 1, o0000000003675ba8, o0000000003675b78, o0000000003675bd8, C4<0>;
+L_0000000003961a80 .functor OR 1, o0000000003675c38, o0000000003675c08, C4<0>, C4<0>;
+L_0000000003962260 .functor AND 1, L_0000000003962810, L_0000000003961a80, C4<1>, C4<1>;
+L_0000000003961af0 .functor BUF 1, L_0000000003962260, C4<0>, C4<0>, C4<0>;
+v000000000373c1f0_0 .net "A1", 0 0, o0000000003675b78; alias, 0 drivers
+v000000000373bbb0_0 .net "A2", 0 0, o0000000003675ba8; alias, 0 drivers
+v000000000373c8d0_0 .net "A3", 0 0, o0000000003675bd8; alias, 0 drivers
+v000000000373de10_0 .net "B1", 0 0, o0000000003675c08; alias, 0 drivers
+v000000000373b930_0 .net "B2", 0 0, o0000000003675c38; alias, 0 drivers
+L_00000000038f09c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373c790_0 .net8 "VGND", 0 0, L_00000000038f09c0; 1 drivers, strength-aware
+L_00000000038f1050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373cf10_0 .net8 "VNB", 0 0, L_00000000038f1050; 1 drivers, strength-aware
+L_00000000038f1c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373d550_0 .net8 "VPB", 0 0, L_00000000038f1c90; 1 drivers, strength-aware
+L_00000000038f1520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373d5f0_0 .net8 "VPWR", 0 0, L_00000000038f1520; 1 drivers, strength-aware
+v000000000373bf70_0 .net "X", 0 0, L_0000000003961af0; alias, 1 drivers
+v000000000373d690_0 .net "and0_out_X", 0 0, L_0000000003962260; 1 drivers
+v000000000373ba70_0 .net "or0_out", 0 0, L_0000000003962810; 1 drivers
+v000000000373d730_0 .net "or1_out", 0 0, L_0000000003961a80; 1 drivers
+S_0000000002730640 .scope module, "sky130_fd_sc_hd__o32ai_1" "sky130_fd_sc_hd__o32ai_1" 4 25048;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o00000000036760e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f030_0 .net "A1", 0 0, o00000000036760e8; 0 drivers
+o0000000003676118 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373e4f0_0 .net "A2", 0 0, o0000000003676118; 0 drivers
+o0000000003676148 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f0d0_0 .net "A3", 0 0, o0000000003676148; 0 drivers
+o0000000003676178 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373fad0_0 .net "B1", 0 0, o0000000003676178; 0 drivers
+o00000000036761a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373ffd0_0 .net "B2", 0 0, o00000000036761a8; 0 drivers
+L_00000000038f1a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373e590_0 .net8 "VGND", 0 0, L_00000000038f1a60; 1 drivers, strength-aware
+L_00000000038f0330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373ebd0_0 .net8 "VNB", 0 0, L_00000000038f0330; 1 drivers, strength-aware
+L_00000000038f0410 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373fd50_0 .net8 "VPB", 0 0, L_00000000038f0410; 1 drivers, strength-aware
+L_00000000038f03a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740110_0 .net8 "VPWR", 0 0, L_00000000038f03a0; 1 drivers, strength-aware
+v000000000373ec70_0 .net "Y", 0 0, L_0000000003962730; 1 drivers
+S_00000000036a5800 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 25070, 4 24916 1, S_0000000002730640;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_0000000003961c40 .functor NOR 1, o0000000003676148, o00000000036760e8, o0000000003676118, C4<0>;
+L_00000000039627a0 .functor NOR 1, o0000000003676178, o00000000036761a8, C4<0>, C4<0>;
+L_0000000003961d90 .functor OR 1, L_00000000039627a0, L_0000000003961c40, C4<0>, C4<0>;
+L_0000000003962730 .functor BUF 1, L_0000000003961d90, C4<0>, C4<0>, C4<0>;
+v000000000373fc10_0 .net "A1", 0 0, o00000000036760e8; alias, 0 drivers
+v000000000373e9f0_0 .net "A2", 0 0, o0000000003676118; alias, 0 drivers
+v0000000003740430_0 .net "A3", 0 0, o0000000003676148; alias, 0 drivers
+v000000000373e310_0 .net "B1", 0 0, o0000000003676178; alias, 0 drivers
+v000000000373f210_0 .net "B2", 0 0, o00000000036761a8; alias, 0 drivers
+L_00000000038f1590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373f2b0_0 .net8 "VGND", 0 0, L_00000000038f1590; 1 drivers, strength-aware
+L_00000000038f06b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373f710_0 .net8 "VNB", 0 0, L_00000000038f06b0; 1 drivers, strength-aware
+L_00000000038f0d40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373fa30_0 .net8 "VPB", 0 0, L_00000000038f0d40; 1 drivers, strength-aware
+L_00000000038f0f70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373fcb0_0 .net8 "VPWR", 0 0, L_00000000038f0f70; 1 drivers, strength-aware
+v000000000373e3b0_0 .net "Y", 0 0, L_0000000003962730; alias, 1 drivers
+v000000000373f490_0 .net "nor0_out", 0 0, L_0000000003961c40; 1 drivers
+v000000000373e6d0_0 .net "nor1_out", 0 0, L_00000000039627a0; 1 drivers
+v000000000373eef0_0 .net "or0_out_Y", 0 0, L_0000000003961d90; 1 drivers
+S_00000000027319c0 .scope module, "sky130_fd_sc_hd__o32ai_2" "sky130_fd_sc_hd__o32ai_2" 4 24570;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003676658 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f3f0_0 .net "A1", 0 0, o0000000003676658; 0 drivers
+o0000000003676688 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f990_0 .net "A2", 0 0, o0000000003676688; 0 drivers
+o00000000036766b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037404d0_0 .net "A3", 0 0, o00000000036766b8; 0 drivers
+o00000000036766e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f530_0 .net "B1", 0 0, o00000000036766e8; 0 drivers
+o0000000003676718 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373ee50_0 .net "B2", 0 0, o0000000003676718; 0 drivers
+L_00000000038f0480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373e450_0 .net8 "VGND", 0 0, L_00000000038f0480; 1 drivers, strength-aware
+L_00000000038f10c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003740610_0 .net8 "VNB", 0 0, L_00000000038f10c0; 1 drivers, strength-aware
+L_00000000038f0fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373e770_0 .net8 "VPB", 0 0, L_00000000038f0fe0; 1 drivers, strength-aware
+L_00000000038f04f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000373f5d0_0 .net8 "VPWR", 0 0, L_00000000038f04f0; 1 drivers, strength-aware
+v0000000003740570_0 .net "Y", 0 0, L_0000000003961ee0; 1 drivers
+S_00000000036a7300 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 24592, 4 24916 1, S_00000000027319c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_00000000039628f0 .functor NOR 1, o00000000036766b8, o0000000003676658, o0000000003676688, C4<0>;
+L_0000000003961e00 .functor NOR 1, o00000000036766e8, o0000000003676718, C4<0>, C4<0>;
+L_0000000003962a40 .functor OR 1, L_0000000003961e00, L_00000000039628f0, C4<0>, C4<0>;
+L_0000000003961ee0 .functor BUF 1, L_0000000003962a40, C4<0>, C4<0>, C4<0>;
+v000000000373fdf0_0 .net "A1", 0 0, o0000000003676658; alias, 0 drivers
+v000000000373f8f0_0 .net "A2", 0 0, o0000000003676688; alias, 0 drivers
+v000000000373fb70_0 .net "A3", 0 0, o00000000036766b8; alias, 0 drivers
+v000000000373fe90_0 .net "B1", 0 0, o00000000036766e8; alias, 0 drivers
+v000000000373ff30_0 .net "B2", 0 0, o0000000003676718; alias, 0 drivers
+L_00000000038f19f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373f350_0 .net8 "VGND", 0 0, L_00000000038f19f0; 1 drivers, strength-aware
+L_00000000038f05d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003740070_0 .net8 "VNB", 0 0, L_00000000038f05d0; 1 drivers, strength-aware
+L_00000000038f0870 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037401b0_0 .net8 "VPB", 0 0, L_00000000038f0870; 1 drivers, strength-aware
+L_00000000038f0640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740250_0 .net8 "VPWR", 0 0, L_00000000038f0640; 1 drivers, strength-aware
+v00000000037402f0_0 .net "Y", 0 0, L_0000000003961ee0; alias, 1 drivers
+v000000000373eb30_0 .net "nor0_out", 0 0, L_00000000039628f0; 1 drivers
+v0000000003740390_0 .net "nor1_out", 0 0, L_0000000003961e00; 1 drivers
+v000000000373e630_0 .net "or0_out_Y", 0 0, L_0000000003962a40; 1 drivers
+S_00000000027307c0 .scope module, "sky130_fd_sc_hd__o32ai_4" "sky130_fd_sc_hd__o32ai_4" 4 24444;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+o0000000003676bc8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373ea90_0 .net "A1", 0 0, o0000000003676bc8; 0 drivers
+o0000000003676bf8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000373f850_0 .net "A2", 0 0, o0000000003676bf8; 0 drivers
+o0000000003676c28 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003741970_0 .net "A3", 0 0, o0000000003676c28; 0 drivers
+o0000000003676c58 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003742e10_0 .net "B1", 0 0, o0000000003676c58; 0 drivers
+o0000000003676c88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003741510_0 .net "B2", 0 0, o0000000003676c88; 0 drivers
+L_00000000038f0bf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003741470_0 .net8 "VGND", 0 0, L_00000000038f0bf0; 1 drivers, strength-aware
+L_00000000038f1600 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003740c50_0 .net8 "VNB", 0 0, L_00000000038f1600; 1 drivers, strength-aware
+L_00000000038f0b10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037415b0_0 .net8 "VPB", 0 0, L_00000000038f0b10; 1 drivers, strength-aware
+L_00000000038f1360 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740f70_0 .net8 "VPWR", 0 0, L_00000000038f1360; 1 drivers, strength-aware
+v00000000037422d0_0 .net "Y", 0 0, L_00000000039629d0; 1 drivers
+S_00000000036a4d80 .scope module, "base" "sky130_fd_sc_hd__o32ai" 4 24466, 4 24916 1, S_00000000027307c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "B1"
+ .port_info 5 /INPUT 1 "B2"
+L_0000000003961f50 .functor NOR 1, o0000000003676c28, o0000000003676bc8, o0000000003676bf8, C4<0>;
+L_0000000003961fc0 .functor NOR 1, o0000000003676c58, o0000000003676c88, C4<0>, C4<0>;
+L_0000000003962960 .functor OR 1, L_0000000003961fc0, L_0000000003961f50, C4<0>, C4<0>;
+L_00000000039629d0 .functor BUF 1, L_0000000003962960, C4<0>, C4<0>, C4<0>;
+v000000000373f170_0 .net "A1", 0 0, o0000000003676bc8; alias, 0 drivers
+v000000000373e810_0 .net "A2", 0 0, o0000000003676bf8; alias, 0 drivers
+v000000000373f7b0_0 .net "A3", 0 0, o0000000003676c28; alias, 0 drivers
+v00000000037406b0_0 .net "B1", 0 0, o0000000003676c58; alias, 0 drivers
+v0000000003740750_0 .net "B2", 0 0, o0000000003676c88; alias, 0 drivers
+L_00000000038f1bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373e8b0_0 .net8 "VGND", 0 0, L_00000000038f1bb0; 1 drivers, strength-aware
+L_00000000038f0100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000373ed10_0 .net8 "VNB", 0 0, L_00000000038f0100; 1 drivers, strength-aware
+L_00000000038f1b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037407f0_0 .net8 "VPB", 0 0, L_00000000038f1b40; 1 drivers, strength-aware
+L_00000000038f0560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740890_0 .net8 "VPWR", 0 0, L_00000000038f0560; 1 drivers, strength-aware
+v000000000373edb0_0 .net "Y", 0 0, L_00000000039629d0; alias, 1 drivers
+v000000000373e950_0 .net "nor0_out", 0 0, L_0000000003961f50; 1 drivers
+v000000000373e130_0 .net "nor1_out", 0 0, L_0000000003961fc0; 1 drivers
+v000000000373e1d0_0 .net "or0_out_Y", 0 0, L_0000000003962960; 1 drivers
+S_00000000027313c0 .scope module, "sky130_fd_sc_hd__o41a_1" "sky130_fd_sc_hd__o41a_1" 4 71368;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003677138 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003741330_0 .net "A1", 0 0, o0000000003677138; 0 drivers
+o0000000003677168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003741dd0_0 .net "A2", 0 0, o0000000003677168; 0 drivers
+o0000000003677198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003740e30_0 .net "A3", 0 0, o0000000003677198; 0 drivers
+o00000000036771c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003741b50_0 .net "A4", 0 0, o00000000036771c8; 0 drivers
+o00000000036771f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037416f0_0 .net "B1", 0 0, o00000000036771f8; 0 drivers
+L_00000000038f13d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003742c30_0 .net8 "VGND", 0 0, L_00000000038f13d0; 1 drivers, strength-aware
+L_00000000038f0720 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003742690_0 .net8 "VNB", 0 0, L_00000000038f0720; 1 drivers, strength-aware
+L_00000000038f18a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003742cd0_0 .net8 "VPB", 0 0, L_00000000038f18a0; 1 drivers, strength-aware
+L_00000000038f1670 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003741d30_0 .net8 "VPWR", 0 0, L_00000000038f1670; 1 drivers, strength-aware
+v0000000003741790_0 .net "X", 0 0, L_00000000039641e0; 1 drivers
+S_00000000036a6a00 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71390, 4 71708 1, S_00000000027313c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_0000000003962ab0 .functor OR 1, o00000000036771c8, o0000000003677198, o0000000003677168, o0000000003677138;
+L_0000000003962b20 .functor AND 1, L_0000000003962ab0, o00000000036771f8, C4<1>, C4<1>;
+L_00000000039641e0 .functor BUF 1, L_0000000003962b20, C4<0>, C4<0>, C4<0>;
+v0000000003741bf0_0 .net "A1", 0 0, o0000000003677138; alias, 0 drivers
+v00000000037420f0_0 .net "A2", 0 0, o0000000003677168; alias, 0 drivers
+v00000000037425f0_0 .net "A3", 0 0, o0000000003677198; alias, 0 drivers
+v0000000003741a10_0 .net "A4", 0 0, o00000000036771c8; alias, 0 drivers
+v0000000003741650_0 .net "B1", 0 0, o00000000036771f8; alias, 0 drivers
+L_00000000038f0790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003740cf0_0 .net8 "VGND", 0 0, L_00000000038f0790; 1 drivers, strength-aware
+L_00000000038f1c20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003742eb0_0 .net8 "VNB", 0 0, L_00000000038f1c20; 1 drivers, strength-aware
+L_00000000038f02c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740d90_0 .net8 "VPB", 0 0, L_00000000038f02c0; 1 drivers, strength-aware
+L_00000000038f1910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003741c90_0 .net8 "VPWR", 0 0, L_00000000038f1910; 1 drivers, strength-aware
+v0000000003742af0_0 .net "X", 0 0, L_00000000039641e0; alias, 1 drivers
+v0000000003742550_0 .net "and0_out_X", 0 0, L_0000000003962b20; 1 drivers
+v0000000003741fb0_0 .net "or0_out", 0 0, L_0000000003962ab0; 1 drivers
+S_000000000272fbc0 .scope module, "sky130_fd_sc_hd__o41a_2" "sky130_fd_sc_hd__o41a_2" 4 71838;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003677678 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003742050_0 .net "A1", 0 0, o0000000003677678; 0 drivers
+o00000000036776a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037409d0_0 .net "A2", 0 0, o00000000036776a8; 0 drivers
+o00000000036776d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003742190_0 .net "A3", 0 0, o00000000036776d8; 0 drivers
+o0000000003677708 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003742730_0 .net "A4", 0 0, o0000000003677708; 0 drivers
+o0000000003677738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003742230_0 .net "B1", 0 0, o0000000003677738; 0 drivers
+L_00000000038f1130 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037410b0_0 .net8 "VGND", 0 0, L_00000000038f1130; 1 drivers, strength-aware
+L_00000000038f1280 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037427d0_0 .net8 "VNB", 0 0, L_00000000038f1280; 1 drivers, strength-aware
+L_00000000038f0800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003743090_0 .net8 "VPB", 0 0, L_00000000038f0800; 1 drivers, strength-aware
+L_00000000038f0950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740a70_0 .net8 "VPWR", 0 0, L_00000000038f0950; 1 drivers, strength-aware
+v0000000003742870_0 .net "X", 0 0, L_0000000003963ca0; 1 drivers
+S_00000000036a7480 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71860, 4 71708 1, S_000000000272fbc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_0000000003964db0 .functor OR 1, o0000000003677708, o00000000036776d8, o00000000036776a8, o0000000003677678;
+L_0000000003964100 .functor AND 1, L_0000000003964db0, o0000000003677738, C4<1>, C4<1>;
+L_0000000003963ca0 .functor BUF 1, L_0000000003964100, C4<0>, C4<0>, C4<0>;
+v0000000003742d70_0 .net "A1", 0 0, o0000000003677678; alias, 0 drivers
+v0000000003741ab0_0 .net "A2", 0 0, o00000000036776a8; alias, 0 drivers
+v0000000003742f50_0 .net "A3", 0 0, o00000000036776d8; alias, 0 drivers
+v0000000003741830_0 .net "A4", 0 0, o0000000003677708; alias, 0 drivers
+v00000000037418d0_0 .net "B1", 0 0, o0000000003677738; alias, 0 drivers
+L_00000000038f0b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037413d0_0 .net8 "VGND", 0 0, L_00000000038f0b80; 1 drivers, strength-aware
+L_00000000038f1210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003742ff0_0 .net8 "VNB", 0 0, L_00000000038f1210; 1 drivers, strength-aware
+L_00000000038f08e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003740ed0_0 .net8 "VPB", 0 0, L_00000000038f08e0; 1 drivers, strength-aware
+L_00000000038f0a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003741e70_0 .net8 "VPWR", 0 0, L_00000000038f0a30; 1 drivers, strength-aware
+v0000000003741f10_0 .net "X", 0 0, L_0000000003963ca0; alias, 1 drivers
+v0000000003741010_0 .net "and0_out_X", 0 0, L_0000000003964100; 1 drivers
+v0000000003740b10_0 .net "or0_out", 0 0, L_0000000003964db0; 1 drivers
+S_0000000002731540 .scope module, "sky130_fd_sc_hd__o41a_4" "sky130_fd_sc_hd__o41a_4" 4 71964;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003677bb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003745070_0 .net "A1", 0 0, o0000000003677bb8; 0 drivers
+o0000000003677be8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744170_0 .net "A2", 0 0, o0000000003677be8; 0 drivers
+o0000000003677c18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744e90_0 .net "A3", 0 0, o0000000003677c18; 0 drivers
+o0000000003677c48 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003743130_0 .net "A4", 0 0, o0000000003677c48; 0 drivers
+o0000000003677c78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744b70_0 .net "B1", 0 0, o0000000003677c78; 0 drivers
+L_00000000038f16e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744ad0_0 .net8 "VGND", 0 0, L_00000000038f16e0; 1 drivers, strength-aware
+L_00000000038f0aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744f30_0 .net8 "VNB", 0 0, L_00000000038f0aa0; 1 drivers, strength-aware
+L_00000000038f1440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003744490_0 .net8 "VPB", 0 0, L_00000000038f1440; 1 drivers, strength-aware
+L_00000000038f14b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003743c70_0 .net8 "VPWR", 0 0, L_00000000038f14b0; 1 drivers, strength-aware
+v0000000003744d50_0 .net "X", 0 0, L_0000000003964950; 1 drivers
+S_00000000036a7780 .scope module, "base" "sky130_fd_sc_hd__o41a" 4 71986, 4 71708 1, S_0000000002731540;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_00000000039635a0 .functor OR 1, o0000000003677c48, o0000000003677c18, o0000000003677be8, o0000000003677bb8;
+L_0000000003963a70 .functor AND 1, L_00000000039635a0, o0000000003677c78, C4<1>, C4<1>;
+L_0000000003964950 .functor BUF 1, L_0000000003963a70, C4<0>, C4<0>, C4<0>;
+v00000000037411f0_0 .net "A1", 0 0, o0000000003677bb8; alias, 0 drivers
+v0000000003740930_0 .net "A2", 0 0, o0000000003677be8; alias, 0 drivers
+v0000000003740bb0_0 .net "A3", 0 0, o0000000003677c18; alias, 0 drivers
+v0000000003742370_0 .net "A4", 0 0, o0000000003677c48; alias, 0 drivers
+v0000000003742410_0 .net "B1", 0 0, o0000000003677c78; alias, 0 drivers
+L_00000000038f1750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037424b0_0 .net8 "VGND", 0 0, L_00000000038f1750; 1 drivers, strength-aware
+L_00000000038f12f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003742910_0 .net8 "VNB", 0 0, L_00000000038f12f0; 1 drivers, strength-aware
+L_00000000038f0cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037429b0_0 .net8 "VPB", 0 0, L_00000000038f0cd0; 1 drivers, strength-aware
+L_00000000038f1ad0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003742a50_0 .net8 "VPWR", 0 0, L_00000000038f1ad0; 1 drivers, strength-aware
+v0000000003742b90_0 .net "X", 0 0, L_0000000003964950; alias, 1 drivers
+v0000000003741150_0 .net "and0_out_X", 0 0, L_0000000003963a70; 1 drivers
+v0000000003741290_0 .net "or0_out", 0 0, L_00000000039635a0; 1 drivers
+S_0000000002731fc0 .scope module, "sky130_fd_sc_hd__o41ai_1" "sky130_fd_sc_hd__o41ai_1" 4 34012;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o00000000036780f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037457f0_0 .net "A1", 0 0, o00000000036780f8; 0 drivers
+o0000000003678128 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003745750_0 .net "A2", 0 0, o0000000003678128; 0 drivers
+o0000000003678158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037442b0_0 .net "A3", 0 0, o0000000003678158; 0 drivers
+o0000000003678188 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003743a90_0 .net "A4", 0 0, o0000000003678188; 0 drivers
+o00000000036781b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037434f0_0 .net "B1", 0 0, o00000000036781b8; 0 drivers
+L_00000000038f0c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744350_0 .net8 "VGND", 0 0, L_00000000038f0c60; 1 drivers, strength-aware
+L_00000000038f0db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743ef0_0 .net8 "VNB", 0 0, L_00000000038f0db0; 1 drivers, strength-aware
+L_00000000038f17c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003745110_0 .net8 "VPB", 0 0, L_00000000038f17c0; 1 drivers, strength-aware
+L_00000000038f0e20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037445d0_0 .net8 "VPWR", 0 0, L_00000000038f0e20; 1 drivers, strength-aware
+v00000000037454d0_0 .net "Y", 0 0, L_0000000003963840; 1 drivers
+S_00000000036a7c00 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 34034, 4 33756 1, S_0000000002731fc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_00000000039644f0 .functor OR 1, o0000000003678188, o0000000003678158, o0000000003678128, o00000000036780f8;
+L_0000000003964720 .functor NAND 1, o00000000036781b8, L_00000000039644f0, C4<1>, C4<1>;
+L_0000000003963840 .functor BUF 1, L_0000000003964720, C4<0>, C4<0>, C4<0>;
+v0000000003743d10_0 .net "A1", 0 0, o00000000036780f8; alias, 0 drivers
+v0000000003744990_0 .net "A2", 0 0, o0000000003678128; alias, 0 drivers
+v0000000003745430_0 .net "A3", 0 0, o0000000003678158; alias, 0 drivers
+v00000000037447b0_0 .net "A4", 0 0, o0000000003678188; alias, 0 drivers
+v0000000003744df0_0 .net "B1", 0 0, o00000000036781b8; alias, 0 drivers
+L_00000000038f0170 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744210_0 .net8 "VGND", 0 0, L_00000000038f0170; 1 drivers, strength-aware
+L_00000000038f1980 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743e50_0 .net8 "VNB", 0 0, L_00000000038f1980; 1 drivers, strength-aware
+L_00000000038f1830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037431d0_0 .net8 "VPB", 0 0, L_00000000038f1830; 1 drivers, strength-aware
+L_00000000038f01e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037448f0_0 .net8 "VPWR", 0 0, L_00000000038f01e0; 1 drivers, strength-aware
+v0000000003743590_0 .net "Y", 0 0, L_0000000003963840; alias, 1 drivers
+v00000000037443f0_0 .net "nand0_out_Y", 0 0, L_0000000003964720; 1 drivers
+v0000000003743450_0 .net "or0_out", 0 0, L_00000000039644f0; 1 drivers
+S_000000000272f440 .scope module, "sky130_fd_sc_hd__o41ai_2" "sky130_fd_sc_hd__o41ai_2" 4 33886;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003678638 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744710_0 .net "A1", 0 0, o0000000003678638; 0 drivers
+o0000000003678668 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744850_0 .net "A2", 0 0, o0000000003678668; 0 drivers
+o0000000003678698 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037436d0_0 .net "A3", 0 0, o0000000003678698; 0 drivers
+o00000000036786c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744c10_0 .net "A4", 0 0, o00000000036786c8; 0 drivers
+o00000000036786f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003744cb0_0 .net "B1", 0 0, o00000000036786f8; 0 drivers
+L_00000000038f0e90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744fd0_0 .net8 "VGND", 0 0, L_00000000038f0e90; 1 drivers, strength-aware
+L_00000000038f0250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743b30_0 .net8 "VNB", 0 0, L_00000000038f0250; 1 drivers, strength-aware
+L_00000000038f0f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003743770_0 .net8 "VPB", 0 0, L_00000000038f0f00; 1 drivers, strength-aware
+L_00000000038f3580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037451b0_0 .net8 "VPWR", 0 0, L_00000000038f3580; 1 drivers, strength-aware
+v0000000003743270_0 .net "Y", 0 0, L_0000000003964560; 1 drivers
+S_00000000036a7d80 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 33908, 4 33756 1, S_000000000272f440;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_0000000003963ae0 .functor OR 1, o00000000036786c8, o0000000003678698, o0000000003678668, o0000000003678638;
+L_0000000003963ed0 .functor NAND 1, o00000000036786f8, L_0000000003963ae0, C4<1>, C4<1>;
+L_0000000003964560 .functor BUF 1, L_0000000003963ed0, C4<0>, C4<0>, C4<0>;
+v00000000037438b0_0 .net "A1", 0 0, o0000000003678638; alias, 0 drivers
+v00000000037433b0_0 .net "A2", 0 0, o0000000003678668; alias, 0 drivers
+v00000000037440d0_0 .net "A3", 0 0, o0000000003678698; alias, 0 drivers
+v0000000003745570_0 .net "A4", 0 0, o00000000036786c8; alias, 0 drivers
+v0000000003745610_0 .net "B1", 0 0, o00000000036786f8; alias, 0 drivers
+L_00000000038f37b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743f90_0 .net8 "VGND", 0 0, L_00000000038f37b0; 1 drivers, strength-aware
+L_00000000038f2ef0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003744030_0 .net8 "VNB", 0 0, L_00000000038f2ef0; 1 drivers, strength-aware
+L_00000000038f2780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003744a30_0 .net8 "VPB", 0 0, L_00000000038f2780; 1 drivers, strength-aware
+L_00000000038f2da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003744530_0 .net8 "VPWR", 0 0, L_00000000038f2da0; 1 drivers, strength-aware
+v0000000003743630_0 .net "Y", 0 0, L_0000000003964560; alias, 1 drivers
+v0000000003744670_0 .net "nand0_out_Y", 0 0, L_0000000003963ed0; 1 drivers
+v0000000003745890_0 .net "or0_out", 0 0, L_0000000003963ae0; 1 drivers
+S_0000000002731b40 .scope module, "sky130_fd_sc_hd__o41ai_4" "sky130_fd_sc_hd__o41ai_4" 4 34138;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+o0000000003678b78 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003746dd0_0 .net "A1", 0 0, o0000000003678b78; 0 drivers
+o0000000003678ba8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003745ed0_0 .net "A2", 0 0, o0000000003678ba8; 0 drivers
+o0000000003678bd8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003746510_0 .net "A3", 0 0, o0000000003678bd8; 0 drivers
+o0000000003678c08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003747870_0 .net "A4", 0 0, o0000000003678c08; 0 drivers
+o0000000003678c38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003746290_0 .net "B1", 0 0, o0000000003678c38; 0 drivers
+L_00000000038f2e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037470f0_0 .net8 "VGND", 0 0, L_00000000038f2e80; 1 drivers, strength-aware
+L_00000000038f29b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003746470_0 .net8 "VNB", 0 0, L_00000000038f29b0; 1 drivers, strength-aware
+L_00000000038f2390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003745d90_0 .net8 "VPB", 0 0, L_00000000038f2390; 1 drivers, strength-aware
+L_00000000038f21d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037461f0_0 .net8 "VPWR", 0 0, L_00000000038f21d0; 1 drivers, strength-aware
+v0000000003747c30_0 .net "Y", 0 0, L_0000000003963fb0; 1 drivers
+S_00000000036a7f00 .scope module, "base" "sky130_fd_sc_hd__o41ai" 4 34160, 4 33756 1, S_0000000002731b40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A1"
+ .port_info 2 /INPUT 1 "A2"
+ .port_info 3 /INPUT 1 "A3"
+ .port_info 4 /INPUT 1 "A4"
+ .port_info 5 /INPUT 1 "B1"
+L_0000000003963f40 .functor OR 1, o0000000003678c08, o0000000003678bd8, o0000000003678ba8, o0000000003678b78;
+L_00000000039645d0 .functor NAND 1, o0000000003678c38, L_0000000003963f40, C4<1>, C4<1>;
+L_0000000003963fb0 .functor BUF 1, L_00000000039645d0, C4<0>, C4<0>, C4<0>;
+v0000000003745250_0 .net "A1", 0 0, o0000000003678b78; alias, 0 drivers
+v00000000037452f0_0 .net "A2", 0 0, o0000000003678ba8; alias, 0 drivers
+v00000000037456b0_0 .net "A3", 0 0, o0000000003678bd8; alias, 0 drivers
+v0000000003745390_0 .net "A4", 0 0, o0000000003678c08; alias, 0 drivers
+v0000000003743310_0 .net "B1", 0 0, o0000000003678c38; alias, 0 drivers
+L_00000000038f3040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743810_0 .net8 "VGND", 0 0, L_00000000038f3040; 1 drivers, strength-aware
+L_00000000038f3510 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003743950_0 .net8 "VNB", 0 0, L_00000000038f3510; 1 drivers, strength-aware
+L_00000000038f2b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037439f0_0 .net8 "VPB", 0 0, L_00000000038f2b00; 1 drivers, strength-aware
+L_00000000038f2080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003743bd0_0 .net8 "VPWR", 0 0, L_00000000038f2080; 1 drivers, strength-aware
+v0000000003743db0_0 .net "Y", 0 0, L_0000000003963fb0; alias, 1 drivers
+v0000000003745b10_0 .net "nand0_out_Y", 0 0, L_00000000039645d0; 1 drivers
+v0000000003746c90_0 .net "or0_out", 0 0, L_0000000003963f40; 1 drivers
+S_0000000002730040 .scope module, "sky130_fd_sc_hd__or2_0" "sky130_fd_sc_hd__or2_0" 4 32925;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o00000000036790b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037468d0_0 .net "A", 0 0, o00000000036790b8; 0 drivers
+o00000000036790e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003747230_0 .net "B", 0 0, o00000000036790e8; 0 drivers
+L_00000000038f2cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037465b0_0 .net8 "VGND", 0 0, L_00000000038f2cc0; 1 drivers, strength-aware
+L_00000000038f2a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003745f70_0 .net8 "VNB", 0 0, L_00000000038f2a20; 1 drivers, strength-aware
+L_00000000038f1f30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037472d0_0 .net8 "VPB", 0 0, L_00000000038f1f30; 1 drivers, strength-aware
+L_00000000038f2160 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003747910_0 .net8 "VPWR", 0 0, L_00000000038f2160; 1 drivers, strength-aware
+v0000000003746010_0 .net "X", 0 0, L_0000000003964f00; 1 drivers
+S_00000000036a2080 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32941, 4 32814 1, S_0000000002730040;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_00000000039642c0 .functor OR 1, o00000000036790e8, o00000000036790b8, C4<0>, C4<0>;
+L_0000000003964f00 .functor BUF 1, L_00000000039642c0, C4<0>, C4<0>, C4<0>;
+v0000000003747410_0 .net "A", 0 0, o00000000036790b8; alias, 0 drivers
+v0000000003745bb0_0 .net "B", 0 0, o00000000036790e8; alias, 0 drivers
+L_00000000038f3890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003746f10_0 .net8 "VGND", 0 0, L_00000000038f3890; 1 drivers, strength-aware
+L_00000000038f1d00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037466f0_0 .net8 "VNB", 0 0, L_00000000038f1d00; 1 drivers, strength-aware
+L_00000000038f2630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003745e30_0 .net8 "VPB", 0 0, L_00000000038f2630; 1 drivers, strength-aware
+L_00000000038f3120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003746e70_0 .net8 "VPWR", 0 0, L_00000000038f3120; 1 drivers, strength-aware
+v0000000003747550_0 .net "X", 0 0, L_0000000003964f00; alias, 1 drivers
+v0000000003746830_0 .net "or0_out_X", 0 0, L_00000000039642c0; 1 drivers
+S_0000000002732a40 .scope module, "sky130_fd_sc_hd__or2_1" "sky130_fd_sc_hd__or2_1" 4 32411;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003679418 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037460b0_0 .net "A", 0 0, o0000000003679418; 0 drivers
+o0000000003679448 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037475f0_0 .net "B", 0 0, o0000000003679448; 0 drivers
+L_00000000038f2e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003745930_0 .net8 "VGND", 0 0, L_00000000038f2e10; 1 drivers, strength-aware
+L_00000000038f1d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003746150_0 .net8 "VNB", 0 0, L_00000000038f1d70; 1 drivers, strength-aware
+L_00000000038f26a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003746330_0 .net8 "VPB", 0 0, L_00000000038f26a0; 1 drivers, strength-aware
+L_00000000038f2f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003746790_0 .net8 "VPWR", 0 0, L_00000000038f2f60; 1 drivers, strength-aware
+v00000000037479b0_0 .net "X", 0 0, L_0000000003964fe0; 1 drivers
+S_000000000376e570 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32427, 4 32814 1, S_0000000002732a40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003963bc0 .functor OR 1, o0000000003679448, o0000000003679418, C4<0>, C4<0>;
+L_0000000003964fe0 .functor BUF 1, L_0000000003963bc0, C4<0>, C4<0>, C4<0>;
+v0000000003746d30_0 .net "A", 0 0, o0000000003679418; alias, 0 drivers
+v00000000037474b0_0 .net "B", 0 0, o0000000003679448; alias, 0 drivers
+L_00000000038f1fa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003747190_0 .net8 "VGND", 0 0, L_00000000038f1fa0; 1 drivers, strength-aware
+L_00000000038f2a90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003747370_0 .net8 "VNB", 0 0, L_00000000038f2a90; 1 drivers, strength-aware
+L_00000000038f2400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037459d0_0 .net8 "VPB", 0 0, L_00000000038f2400; 1 drivers, strength-aware
+L_00000000038f33c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003747690_0 .net8 "VPWR", 0 0, L_00000000038f33c0; 1 drivers, strength-aware
+v0000000003746fb0_0 .net "X", 0 0, L_0000000003964fe0; alias, 1 drivers
+v0000000003746650_0 .net "or0_out_X", 0 0, L_0000000003963bc0; 1 drivers
+S_0000000002731840 .scope module, "sky130_fd_sc_hd__or2_4" "sky130_fd_sc_hd__or2_4" 4 32517;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o0000000003679778 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003747f50_0 .net "A", 0 0, o0000000003679778; 0 drivers
+o00000000036797a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003746ab0_0 .net "B", 0 0, o00000000036797a8; 0 drivers
+L_00000000038f22b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037463d0_0 .net8 "VGND", 0 0, L_00000000038f22b0; 1 drivers, strength-aware
+L_00000000038f2b70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003747af0_0 .net8 "VNB", 0 0, L_00000000038f2b70; 1 drivers, strength-aware
+L_00000000038f2710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003746bf0_0 .net8 "VPB", 0 0, L_00000000038f2710; 1 drivers, strength-aware
+L_00000000038f1de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003746970_0 .net8 "VPWR", 0 0, L_00000000038f1de0; 1 drivers, strength-aware
+v0000000003747cd0_0 .net "X", 0 0, L_0000000003963d10; 1 drivers
+S_000000000376a7f0 .scope module, "base" "sky130_fd_sc_hd__or2" 4 32533, 4 32814 1, S_0000000002731840;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_0000000003963b50 .functor OR 1, o00000000036797a8, o0000000003679778, C4<0>, C4<0>;
+L_0000000003963d10 .functor BUF 1, L_0000000003963b50, C4<0>, C4<0>, C4<0>;
+v0000000003747d70_0 .net "A", 0 0, o0000000003679778; alias, 0 drivers
+v0000000003745a70_0 .net "B", 0 0, o00000000036797a8; alias, 0 drivers
+L_00000000038f2320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003747e10_0 .net8 "VGND", 0 0, L_00000000038f2320; 1 drivers, strength-aware
+L_00000000038f27f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003746b50_0 .net8 "VNB", 0 0, L_00000000038f27f0; 1 drivers, strength-aware
+L_00000000038f2860 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003745c50_0 .net8 "VPB", 0 0, L_00000000038f2860; 1 drivers, strength-aware
+L_00000000038f32e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003747730_0 .net8 "VPWR", 0 0, L_00000000038f32e0; 1 drivers, strength-aware
+v0000000003747a50_0 .net "X", 0 0, L_0000000003963d10; alias, 1 drivers
+v0000000003745cf0_0 .net "or0_out_X", 0 0, L_0000000003963b50; 1 drivers
+S_00000000027301c0 .scope module, "sky130_fd_sc_hd__or2b_1" "sky130_fd_sc_hd__or2b_1" 4 56612;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o0000000003679ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003749030_0 .net "A", 0 0, o0000000003679ad8; 0 drivers
+o0000000003679b08 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003748630_0 .net "B_N", 0 0, o0000000003679b08; 0 drivers
+L_00000000038f34a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749990_0 .net8 "VGND", 0 0, L_00000000038f34a0; 1 drivers, strength-aware
+L_00000000038f30b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749490_0 .net8 "VNB", 0 0, L_00000000038f30b0; 1 drivers, strength-aware
+L_00000000038f28d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037497b0_0 .net8 "VPB", 0 0, L_00000000038f28d0; 1 drivers, strength-aware
+L_00000000038f36d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003749a30_0 .net8 "VPWR", 0 0, L_00000000038f36d0; 1 drivers, strength-aware
+v0000000003748ef0_0 .net "X", 0 0, L_0000000003963d80; 1 drivers
+S_000000000376d070 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56628, 4 56915 1, S_00000000027301c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_0000000003964790 .functor NOT 1, o0000000003679b08, C4<0>, C4<0>, C4<0>;
+L_0000000003964800 .functor OR 1, L_0000000003964790, o0000000003679ad8, C4<0>, C4<0>;
+L_0000000003963d80 .functor BUF 1, L_0000000003964800, C4<0>, C4<0>, C4<0>;
+v0000000003748090_0 .net "A", 0 0, o0000000003679ad8; alias, 0 drivers
+v0000000003746a10_0 .net "B_N", 0 0, o0000000003679b08; alias, 0 drivers
+L_00000000038f3430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003747050_0 .net8 "VGND", 0 0, L_00000000038f3430; 1 drivers, strength-aware
+L_00000000038f2940 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037477d0_0 .net8 "VNB", 0 0, L_00000000038f2940; 1 drivers, strength-aware
+L_00000000038f2be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003747b90_0 .net8 "VPB", 0 0, L_00000000038f2be0; 1 drivers, strength-aware
+L_00000000038f2470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003747eb0_0 .net8 "VPWR", 0 0, L_00000000038f2470; 1 drivers, strength-aware
+v0000000003747ff0_0 .net "X", 0 0, L_0000000003963d80; alias, 1 drivers
+v000000000374a610_0 .net "not0_out", 0 0, L_0000000003964790; 1 drivers
+v0000000003748810_0 .net "or0_out_X", 0 0, L_0000000003964800; 1 drivers
+S_0000000002730340 .scope module, "sky130_fd_sc_hd__or2b_2" "sky130_fd_sc_hd__or2b_2" 4 56400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o0000000003679e68 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003749ad0_0 .net "A", 0 0, o0000000003679e68; 0 drivers
+o0000000003679e98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037490d0_0 .net "B_N", 0 0, o0000000003679e98; 0 drivers
+L_00000000038f24e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374a570_0 .net8 "VGND", 0 0, L_00000000038f24e0; 1 drivers, strength-aware
+L_00000000038f35f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749170_0 .net8 "VNB", 0 0, L_00000000038f35f0; 1 drivers, strength-aware
+L_00000000038f2c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003749210_0 .net8 "VPB", 0 0, L_00000000038f2c50; 1 drivers, strength-aware
+L_00000000038f2fd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003748bd0_0 .net8 "VPWR", 0 0, L_00000000038f2fd0; 1 drivers, strength-aware
+v0000000003748b30_0 .net "X", 0 0, L_0000000003964e20; 1 drivers
+S_000000000376a970 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56416, 4 56915 1, S_0000000002730340;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_0000000003963990 .functor NOT 1, o0000000003679e98, C4<0>, C4<0>, C4<0>;
+L_0000000003964a30 .functor OR 1, L_0000000003963990, o0000000003679e68, C4<0>, C4<0>;
+L_0000000003964e20 .functor BUF 1, L_0000000003964a30, C4<0>, C4<0>, C4<0>;
+v0000000003749710_0 .net "A", 0 0, o0000000003679e68; alias, 0 drivers
+v0000000003749f30_0 .net "B_N", 0 0, o0000000003679e98; alias, 0 drivers
+L_00000000038f2d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003748c70_0 .net8 "VGND", 0 0, L_00000000038f2d30; 1 drivers, strength-aware
+L_00000000038f2550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003748f90_0 .net8 "VNB", 0 0, L_00000000038f2550; 1 drivers, strength-aware
+L_00000000038f3190 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003749670_0 .net8 "VPB", 0 0, L_00000000038f3190; 1 drivers, strength-aware
+L_00000000038f3200 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003748270_0 .net8 "VPWR", 0 0, L_00000000038f3200; 1 drivers, strength-aware
+v00000000037481d0_0 .net "X", 0 0, L_0000000003964e20; alias, 1 drivers
+v000000000374a4d0_0 .net "not0_out", 0 0, L_0000000003963990; 1 drivers
+v00000000037483b0_0 .net "or0_out_X", 0 0, L_0000000003964a30; 1 drivers
+S_0000000002731cc0 .scope module, "sky130_fd_sc_hd__or2b_4" "sky130_fd_sc_hd__or2b_4" 4 56506;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+o000000000367a1f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374a070_0 .net "A", 0 0, o000000000367a1f8; 0 drivers
+o000000000367a228 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003748950_0 .net "B_N", 0 0, o000000000367a228; 0 drivers
+L_00000000038f1e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003748450_0 .net8 "VGND", 0 0, L_00000000038f1e50; 1 drivers, strength-aware
+L_00000000038f1ec0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374a390_0 .net8 "VNB", 0 0, L_00000000038f1ec0; 1 drivers, strength-aware
+L_00000000038f3820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037489f0_0 .net8 "VPB", 0 0, L_00000000038f3820; 1 drivers, strength-aware
+L_00000000038f3270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374a750_0 .net8 "VPWR", 0 0, L_00000000038f3270; 1 drivers, strength-aware
+v0000000003749b70_0 .net "X", 0 0, L_0000000003964aa0; 1 drivers
+S_000000000376ca70 .scope module, "base" "sky130_fd_sc_hd__or2b" 4 56522, 4 56915 1, S_0000000002731cc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B_N"
+L_00000000039643a0 .functor NOT 1, o000000000367a228, C4<0>, C4<0>, C4<0>;
+L_0000000003964640 .functor OR 1, L_00000000039643a0, o000000000367a1f8, C4<0>, C4<0>;
+L_0000000003964aa0 .functor BUF 1, L_0000000003964640, C4<0>, C4<0>, C4<0>;
+v00000000037486d0_0 .net "A", 0 0, o000000000367a1f8; alias, 0 drivers
+v0000000003748130_0 .net "B_N", 0 0, o000000000367a228; alias, 0 drivers
+L_00000000038f3350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037492b0_0 .net8 "VGND", 0 0, L_00000000038f3350; 1 drivers, strength-aware
+L_00000000038f20f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749850_0 .net8 "VNB", 0 0, L_00000000038f20f0; 1 drivers, strength-aware
+L_00000000038f3660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037498f0_0 .net8 "VPB", 0 0, L_00000000038f3660; 1 drivers, strength-aware
+L_00000000038f2010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003748310_0 .net8 "VPWR", 0 0, L_00000000038f2010; 1 drivers, strength-aware
+v000000000374a2f0_0 .net "X", 0 0, L_0000000003964aa0; alias, 1 drivers
+v0000000003748d10_0 .net "not0_out", 0 0, L_00000000039643a0; 1 drivers
+v0000000003749fd0_0 .net "or0_out_X", 0 0, L_0000000003964640; 1 drivers
+S_0000000002732140 .scope module, "sky130_fd_sc_hd__or3_1" "sky130_fd_sc_hd__or3_1" 4 49789;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000367a588 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037488b0_0 .net "A", 0 0, o000000000367a588; 0 drivers
+o000000000367a5b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003748e50_0 .net "B", 0 0, o000000000367a5b8; 0 drivers
+o000000000367a5e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374a110_0 .net "C", 0 0, o000000000367a5e8; 0 drivers
+L_00000000038f3740 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037495d0_0 .net8 "VGND", 0 0, L_00000000038f3740; 1 drivers, strength-aware
+L_00000000038f2240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749d50_0 .net8 "VNB", 0 0, L_00000000038f2240; 1 drivers, strength-aware
+L_00000000038f25c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003749df0_0 .net8 "VPB", 0 0, L_00000000038f25c0; 1 drivers, strength-aware
+L_00000000038f3e40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003748a90_0 .net8 "VPWR", 0 0, L_00000000038f3e40; 1 drivers, strength-aware
+v0000000003749e90_0 .net "X", 0 0, L_0000000003964250; 1 drivers
+S_000000000376f5f0 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49807, 4 49673 1, S_0000000002732140;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_0000000003964020 .functor OR 1, o000000000367a5b8, o000000000367a588, o000000000367a5e8, C4<0>;
+L_0000000003964250 .functor BUF 1, L_0000000003964020, C4<0>, C4<0>, C4<0>;
+v00000000037484f0_0 .net "A", 0 0, o000000000367a588; alias, 0 drivers
+v0000000003749350_0 .net "B", 0 0, o000000000367a5b8; alias, 0 drivers
+v0000000003748db0_0 .net "C", 0 0, o000000000367a5e8; alias, 0 drivers
+L_00000000038f3c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749c10_0 .net8 "VGND", 0 0, L_00000000038f3c10; 1 drivers, strength-aware
+L_00000000038f3970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003749cb0_0 .net8 "VNB", 0 0, L_00000000038f3970; 1 drivers, strength-aware
+L_00000000038f3f90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003748590_0 .net8 "VPB", 0 0, L_00000000038f3f90; 1 drivers, strength-aware
+L_00000000038f3ac0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003749530_0 .net8 "VPWR", 0 0, L_00000000038f3ac0; 1 drivers, strength-aware
+v0000000003748770_0 .net "X", 0 0, L_0000000003964250; alias, 1 drivers
+v00000000037493f0_0 .net "or0_out_X", 0 0, L_0000000003964020; 1 drivers
+S_00000000027310c0 .scope module, "sky130_fd_sc_hd__or3_4" "sky130_fd_sc_hd__or3_4" 4 49367;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000367a978 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374c2d0_0 .net "A", 0 0, o000000000367a978; 0 drivers
+o000000000367a9a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374c690_0 .net "B", 0 0, o000000000367a9a8; 0 drivers
+o000000000367a9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374b010_0 .net "C", 0 0, o000000000367a9d8; 0 drivers
+L_00000000038f3dd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374b5b0_0 .net8 "VGND", 0 0, L_00000000038f3dd0; 1 drivers, strength-aware
+L_00000000038f39e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374c730_0 .net8 "VNB", 0 0, L_00000000038f39e0; 1 drivers, strength-aware
+L_00000000038f3a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374ccd0_0 .net8 "VPB", 0 0, L_00000000038f3a50; 1 drivers, strength-aware
+L_00000000038f3f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374c190_0 .net8 "VPWR", 0 0, L_00000000038f3f20; 1 drivers, strength-aware
+v000000000374bbf0_0 .net "X", 0 0, L_0000000003963610; 1 drivers
+S_000000000376b3f0 .scope module, "base" "sky130_fd_sc_hd__or3" 4 49385, 4 49673 1, S_00000000027310c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_00000000039638b0 .functor OR 1, o000000000367a9a8, o000000000367a978, o000000000367a9d8, C4<0>;
+L_0000000003963610 .functor BUF 1, L_00000000039638b0, C4<0>, C4<0>, C4<0>;
+v000000000374a1b0_0 .net "A", 0 0, o000000000367a978; alias, 0 drivers
+v000000000374a250_0 .net "B", 0 0, o000000000367a9a8; alias, 0 drivers
+v000000000374a430_0 .net "C", 0 0, o000000000367a9d8; alias, 0 drivers
+L_00000000038f3c80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374a6b0_0 .net8 "VGND", 0 0, L_00000000038f3c80; 1 drivers, strength-aware
+L_00000000038f3b30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374a7f0_0 .net8 "VNB", 0 0, L_00000000038f3b30; 1 drivers, strength-aware
+L_00000000038f3ba0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374a890_0 .net8 "VPB", 0 0, L_00000000038f3ba0; 1 drivers, strength-aware
+L_00000000038f3900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374a9d0_0 .net8 "VPWR", 0 0, L_00000000038f3900; 1 drivers, strength-aware
+v000000000374ce10_0 .net "X", 0 0, L_0000000003963610; alias, 1 drivers
+v000000000374b510_0 .net "or0_out_X", 0 0, L_00000000039638b0; 1 drivers
+S_000000000272f5c0 .scope module, "sky130_fd_sc_hd__or3b_1" "sky130_fd_sc_hd__or3b_1" 4 36996;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+o000000000367ad68 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374acf0_0 .net "A", 0 0, o000000000367ad68; 0 drivers
+o000000000367ad98 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374bb50_0 .net "B", 0 0, o000000000367ad98; 0 drivers
+o000000000367adc8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374b0b0_0 .net "C_N", 0 0, o000000000367adc8; 0 drivers
+L_00000000038f3eb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374bdd0_0 .net8 "VGND", 0 0, L_00000000038f3eb0; 1 drivers, strength-aware
+L_00000000038f3cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374c410_0 .net8 "VNB", 0 0, L_00000000038f3cf0; 1 drivers, strength-aware
+L_00000000038f3d60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374bd30_0 .net8 "VPB", 0 0, L_00000000038f3d60; 1 drivers, strength-aware
+L_00000000038d53d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374be70_0 .net8 "VPWR", 0 0, L_00000000038d53d0; 1 drivers, strength-aware
+v000000000374b290_0 .net "X", 0 0, L_00000000039646b0; 1 drivers
+S_000000000376a070 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 37014, 4 36878 1, S_000000000272f5c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_0000000003964870 .functor NOT 1, o000000000367adc8, C4<0>, C4<0>, C4<0>;
+L_00000000039648e0 .functor OR 1, o000000000367ad98, o000000000367ad68, L_0000000003964870, C4<0>;
+L_00000000039646b0 .functor BUF 1, L_00000000039648e0, C4<0>, C4<0>, C4<0>;
+v000000000374c370_0 .net "A", 0 0, o000000000367ad68; alias, 0 drivers
+v000000000374c0f0_0 .net "B", 0 0, o000000000367ad98; alias, 0 drivers
+v000000000374ad90_0 .net "C_N", 0 0, o000000000367adc8; alias, 0 drivers
+L_00000000038d48e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374aa70_0 .net8 "VGND", 0 0, L_00000000038d48e0; 1 drivers, strength-aware
+L_00000000038d4d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374caf0_0 .net8 "VNB", 0 0, L_00000000038d4d40; 1 drivers, strength-aware
+L_00000000038d4640 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374c9b0_0 .net8 "VPB", 0 0, L_00000000038d4640; 1 drivers, strength-aware
+L_00000000038d44f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374ab10_0 .net8 "VPWR", 0 0, L_00000000038d44f0; 1 drivers, strength-aware
+v000000000374c230_0 .net "X", 0 0, L_00000000039646b0; alias, 1 drivers
+v000000000374ac50_0 .net "not0_out", 0 0, L_0000000003964870; 1 drivers
+v000000000374b150_0 .net "or0_out_X", 0 0, L_00000000039648e0; 1 drivers
+S_00000000027304c0 .scope module, "sky130_fd_sc_hd__or3b_4" "sky130_fd_sc_hd__or3b_4" 4 36454;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+o000000000367b188 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374ba10_0 .net "A", 0 0, o000000000367b188; 0 drivers
+o000000000367b1b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374c550_0 .net "B", 0 0, o000000000367b1b8; 0 drivers
+o000000000367b1e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374c5f0_0 .net "C_N", 0 0, o000000000367b1e8; 0 drivers
+L_00000000038d50c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374ae30_0 .net8 "VGND", 0 0, L_00000000038d50c0; 1 drivers, strength-aware
+L_00000000038d4b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374bc90_0 .net8 "VNB", 0 0, L_00000000038d4b10; 1 drivers, strength-aware
+L_00000000038d5830 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374b330_0 .net8 "VPB", 0 0, L_00000000038d5830; 1 drivers, strength-aware
+L_00000000038d5c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374b970_0 .net8 "VPWR", 0 0, L_00000000038d5c90; 1 drivers, strength-aware
+v000000000374c910_0 .net "X", 0 0, L_0000000003963a00; 1 drivers
+S_000000000376a670 .scope module, "base" "sky130_fd_sc_hd__or3b" 4 36472, 4 36878 1, S_00000000027304c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+L_00000000039649c0 .functor NOT 1, o000000000367b1e8, C4<0>, C4<0>, C4<0>;
+L_0000000003963680 .functor OR 1, o000000000367b1b8, o000000000367b188, L_00000000039649c0, C4<0>;
+L_0000000003963a00 .functor BUF 1, L_0000000003963680, C4<0>, C4<0>, C4<0>;
+v000000000374abb0_0 .net "A", 0 0, o000000000367b188; alias, 0 drivers
+v000000000374bf10_0 .net "B", 0 0, o000000000367b1b8; alias, 0 drivers
+v000000000374cd70_0 .net "C_N", 0 0, o000000000367b1e8; alias, 0 drivers
+L_00000000038d4870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374b1f0_0 .net8 "VGND", 0 0, L_00000000038d4870; 1 drivers, strength-aware
+L_00000000038d4c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374bfb0_0 .net8 "VNB", 0 0, L_00000000038d4c60; 1 drivers, strength-aware
+L_00000000038d4e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374c050_0 .net8 "VPB", 0 0, L_00000000038d4e90; 1 drivers, strength-aware
+L_00000000038d59f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374c4b0_0 .net8 "VPWR", 0 0, L_00000000038d59f0; 1 drivers, strength-aware
+v000000000374b470_0 .net "X", 0 0, L_0000000003963a00; alias, 1 drivers
+v000000000374ceb0_0 .net "not0_out", 0 0, L_00000000039649c0; 1 drivers
+v000000000374b830_0 .net "or0_out_X", 0 0, L_0000000003963680; 1 drivers
+S_0000000002731240 .scope module, "sky130_fd_sc_hd__or4_1" "sky130_fd_sc_hd__or4_1" 4 87540;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000367b5a8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374cc30_0 .net "A", 0 0, o000000000367b5a8; 0 drivers
+o000000000367b5d8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374cf50_0 .net "B", 0 0, o000000000367b5d8; 0 drivers
+o000000000367b608 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374cff0_0 .net "C", 0 0, o000000000367b608; 0 drivers
+o000000000367b638 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374d090_0 .net "D", 0 0, o000000000367b638; 0 drivers
+L_00000000038d45d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374a930_0 .net8 "VGND", 0 0, L_00000000038d45d0; 1 drivers, strength-aware
+L_00000000038d4410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374af70_0 .net8 "VNB", 0 0, L_00000000038d4410; 1 drivers, strength-aware
+L_00000000038d4cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374bab0_0 .net8 "VPB", 0 0, L_00000000038d4cd0; 1 drivers, strength-aware
+L_00000000038d51a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374ed50_0 .net8 "VPWR", 0 0, L_00000000038d51a0; 1 drivers, strength-aware
+v000000000374ead0_0 .net "X", 0 0, L_0000000003964b10; 1 drivers
+S_000000000376d4f0 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87560, 4 87301 1, S_0000000002731240;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_0000000003963c30 .functor OR 1, o000000000367b638, o000000000367b608, o000000000367b5d8, o000000000367b5a8;
+L_0000000003964b10 .functor BUF 1, L_0000000003963c30, C4<0>, C4<0>, C4<0>;
+v000000000374b8d0_0 .net "A", 0 0, o000000000367b5a8; alias, 0 drivers
+v000000000374c7d0_0 .net "B", 0 0, o000000000367b5d8; alias, 0 drivers
+v000000000374b650_0 .net "C", 0 0, o000000000367b608; alias, 0 drivers
+v000000000374aed0_0 .net "D", 0 0, o000000000367b638; alias, 0 drivers
+L_00000000038d5590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374c870_0 .net8 "VGND", 0 0, L_00000000038d5590; 1 drivers, strength-aware
+L_00000000038d4950 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374ca50_0 .net8 "VNB", 0 0, L_00000000038d4950; 1 drivers, strength-aware
+L_00000000038d4f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374b3d0_0 .net8 "VPB", 0 0, L_00000000038d4f00; 1 drivers, strength-aware
+L_00000000038d5130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374b6f0_0 .net8 "VPWR", 0 0, L_00000000038d5130; 1 drivers, strength-aware
+v000000000374b790_0 .net "X", 0 0, L_0000000003964b10; alias, 1 drivers
+v000000000374cb90_0 .net "or0_out_X", 0 0, L_0000000003963c30; 1 drivers
+S_00000000027322c0 .scope module, "sky130_fd_sc_hd__or4_4" "sky130_fd_sc_hd__or4_4" 4 86986;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+o000000000367ba28 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374e7b0_0 .net "A", 0 0, o000000000367ba28; 0 drivers
+o000000000367ba58 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374e8f0_0 .net "B", 0 0, o000000000367ba58; 0 drivers
+o000000000367ba88 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374df90_0 .net "C", 0 0, o000000000367ba88; 0 drivers
+o000000000367bab8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374db30_0 .net "D", 0 0, o000000000367bab8; 0 drivers
+L_00000000038d4f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374e5d0_0 .net8 "VGND", 0 0, L_00000000038d4f70; 1 drivers, strength-aware
+L_00000000038d49c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374d8b0_0 .net8 "VNB", 0 0, L_00000000038d49c0; 1 drivers, strength-aware
+L_00000000038d4a30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374f250_0 .net8 "VPB", 0 0, L_00000000038d4a30; 1 drivers, strength-aware
+L_00000000038d5440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374e3f0_0 .net8 "VPWR", 0 0, L_00000000038d5440; 1 drivers, strength-aware
+v000000000374def0_0 .net "X", 0 0, L_00000000039650c0; 1 drivers
+S_000000000376bcf0 .scope module, "base" "sky130_fd_sc_hd__or4" 4 87006, 4 87301 1, S_00000000027322c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D"
+L_0000000003964330 .functor OR 1, o000000000367bab8, o000000000367ba88, o000000000367ba58, o000000000367ba28;
+L_00000000039650c0 .functor BUF 1, L_0000000003964330, C4<0>, C4<0>, C4<0>;
+v000000000374f4d0_0 .net "A", 0 0, o000000000367ba28; alias, 0 drivers
+v000000000374f110_0 .net "B", 0 0, o000000000367ba58; alias, 0 drivers
+v000000000374eb70_0 .net "C", 0 0, o000000000367ba88; alias, 0 drivers
+v000000000374d450_0 .net "D", 0 0, o000000000367bab8; alias, 0 drivers
+L_00000000038d5a60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374d130_0 .net8 "VGND", 0 0, L_00000000038d5a60; 1 drivers, strength-aware
+L_00000000038d5ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374f570_0 .net8 "VNB", 0 0, L_00000000038d5ad0; 1 drivers, strength-aware
+L_00000000038d5c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374ec10_0 .net8 "VPB", 0 0, L_00000000038d5c20; 1 drivers, strength-aware
+L_00000000038d5050 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374d4f0_0 .net8 "VPWR", 0 0, L_00000000038d5050; 1 drivers, strength-aware
+v000000000374f610_0 .net "X", 0 0, L_00000000039650c0; alias, 1 drivers
+v000000000374e350_0 .net "or0_out_X", 0 0, L_0000000003964330; 1 drivers
+S_0000000002730940 .scope module, "sky130_fd_sc_hd__or4b_1" "sky130_fd_sc_hd__or4b_1" 4 18133;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+o000000000367bea8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374e990_0 .net "A", 0 0, o000000000367bea8; 0 drivers
+o000000000367bed8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374e490_0 .net "B", 0 0, o000000000367bed8; 0 drivers
+o000000000367bf08 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374d590_0 .net "C", 0 0, o000000000367bf08; 0 drivers
+o000000000367bf38 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374f7f0_0 .net "D_N", 0 0, o000000000367bf38; 0 drivers
+L_00000000038d4aa0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374d950_0 .net8 "VGND", 0 0, L_00000000038d4aa0; 1 drivers, strength-aware
+L_00000000038d5670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374d630_0 .net8 "VNB", 0 0, L_00000000038d5670; 1 drivers, strength-aware
+L_00000000038d46b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374d770_0 .net8 "VPB", 0 0, L_00000000038d46b0; 1 drivers, strength-aware
+L_00000000038d4800 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374d270_0 .net8 "VPWR", 0 0, L_00000000038d4800; 1 drivers, strength-aware
+v000000000374f2f0_0 .net "X", 0 0, L_0000000003963e60; 1 drivers
+S_000000000376d1f0 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 18153, 4 17892 1, S_0000000002730940;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_0000000003963df0 .functor NOT 1, o000000000367bf38, C4<0>, C4<0>, C4<0>;
+L_0000000003963530 .functor OR 1, L_0000000003963df0, o000000000367bf08, o000000000367bed8, o000000000367bea8;
+L_0000000003963e60 .functor BUF 1, L_0000000003963530, C4<0>, C4<0>, C4<0>;
+v000000000374f890_0 .net "A", 0 0, o000000000367bea8; alias, 0 drivers
+v000000000374d6d0_0 .net "B", 0 0, o000000000367bed8; alias, 0 drivers
+v000000000374d3b0_0 .net "C", 0 0, o000000000367bf08; alias, 0 drivers
+v000000000374d1d0_0 .net "D_N", 0 0, o000000000367bf38; alias, 0 drivers
+L_00000000038d4e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374d310_0 .net8 "VGND", 0 0, L_00000000038d4e20; 1 drivers, strength-aware
+L_00000000038d4db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374e030_0 .net8 "VNB", 0 0, L_00000000038d4db0; 1 drivers, strength-aware
+L_00000000038d4720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374f6b0_0 .net8 "VPB", 0 0, L_00000000038d4720; 1 drivers, strength-aware
+L_00000000038d4170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374f750_0 .net8 "VPWR", 0 0, L_00000000038d4170; 1 drivers, strength-aware
+v000000000374d810_0 .net "X", 0 0, L_0000000003963e60; alias, 1 drivers
+v000000000374e0d0_0 .net "not0_out", 0 0, L_0000000003963df0; 1 drivers
+v000000000374ea30_0 .net "or0_out_X", 0 0, L_0000000003963530; 1 drivers
+S_000000000272f740 .scope module, "sky130_fd_sc_hd__or4b_4" "sky130_fd_sc_hd__or4b_4" 4 17571;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+o000000000367c358 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374ee90_0 .net "A", 0 0, o000000000367c358; 0 drivers
+o000000000367c388 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374f1b0_0 .net "B", 0 0, o000000000367c388; 0 drivers
+o000000000367c3b8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374ef30_0 .net "C", 0 0, o000000000367c3b8; 0 drivers
+o000000000367c3e8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374f390_0 .net "D_N", 0 0, o000000000367c3e8; 0 drivers
+L_00000000038d4b80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374ddb0_0 .net8 "VGND", 0 0, L_00000000038d4b80; 1 drivers, strength-aware
+L_00000000038d4790 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374de50_0 .net8 "VNB", 0 0, L_00000000038d4790; 1 drivers, strength-aware
+L_00000000038d5bb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374e210_0 .net8 "VPB", 0 0, L_00000000038d5bb0; 1 drivers, strength-aware
+L_00000000038d4bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374e2b0_0 .net8 "VPWR", 0 0, L_00000000038d4bf0; 1 drivers, strength-aware
+v000000000374e710_0 .net "X", 0 0, L_00000000039636f0; 1 drivers
+S_000000000376adf0 .scope module, "base" "sky130_fd_sc_hd__or4b" 4 17591, 4 17892 1, S_000000000272f740;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+ .port_info 4 /INPUT 1 "D_N"
+L_0000000003964480 .functor NOT 1, o000000000367c3e8, C4<0>, C4<0>, C4<0>;
+L_0000000003963760 .functor OR 1, L_0000000003964480, o000000000367c3b8, o000000000367c388, o000000000367c358;
+L_00000000039636f0 .functor BUF 1, L_0000000003963760, C4<0>, C4<0>, C4<0>;
+v000000000374d9f0_0 .net "A", 0 0, o000000000367c358; alias, 0 drivers
+v000000000374da90_0 .net "B", 0 0, o000000000367c388; alias, 0 drivers
+v000000000374e530_0 .net "C", 0 0, o000000000367c3b8; alias, 0 drivers
+v000000000374dbd0_0 .net "D_N", 0 0, o000000000367c3e8; alias, 0 drivers
+L_00000000038d4fe0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374ecb0_0 .net8 "VGND", 0 0, L_00000000038d4fe0; 1 drivers, strength-aware
+L_00000000038d5210 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374e850_0 .net8 "VNB", 0 0, L_00000000038d5210; 1 drivers, strength-aware
+L_00000000038d5280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374edf0_0 .net8 "VPB", 0 0, L_00000000038d5280; 1 drivers, strength-aware
+L_00000000038d52f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374dc70_0 .net8 "VPWR", 0 0, L_00000000038d52f0; 1 drivers, strength-aware
+v000000000374e170_0 .net "X", 0 0, L_00000000039636f0; alias, 1 drivers
+v000000000374dd10_0 .net "not0_out", 0 0, L_0000000003964480; 1 drivers
+v000000000374e670_0 .net "or0_out_X", 0 0, L_0000000003963760; 1 drivers
+S_0000000002732440 .scope module, "sky130_fd_sc_hd__or4bb_1" "sky130_fd_sc_hd__or4bb_1" 4 15625;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o000000000367c808 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750c90_0 .net "A", 0 0, o000000000367c808; 0 drivers
+o000000000367c838 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750330_0 .net "B", 0 0, o000000000367c838; 0 drivers
+o000000000367c868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037503d0_0 .net "C_N", 0 0, o000000000367c868; 0 drivers
+o000000000367c898 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000374ff70_0 .net "D_N", 0 0, o000000000367c898; 0 drivers
+L_00000000038d5360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003750790_0 .net8 "VGND", 0 0, L_00000000038d5360; 1 drivers, strength-aware
+L_00000000038d54b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374f930_0 .net8 "VNB", 0 0, L_00000000038d54b0; 1 drivers, strength-aware
+L_00000000038d5520 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374fa70_0 .net8 "VPB", 0 0, L_00000000038d5520; 1 drivers, strength-aware
+L_00000000038d5600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374f9d0_0 .net8 "VPWR", 0 0, L_00000000038d5600; 1 drivers, strength-aware
+v0000000003751cd0_0 .net "X", 0 0, L_0000000003964bf0; 1 drivers
+S_000000000376c2f0 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 15645, 4 15946 1, S_0000000002732440;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_0000000003963920 .functor NAND 1, o000000000367c898, o000000000367c868, C4<1>, C4<1>;
+L_0000000003964f70 .functor OR 1, o000000000367c838, o000000000367c808, L_0000000003963920, C4<0>;
+L_0000000003964bf0 .functor BUF 1, L_0000000003964f70, C4<0>, C4<0>, C4<0>;
+v000000000374efd0_0 .net "A", 0 0, o000000000367c808; alias, 0 drivers
+v000000000374f070_0 .net "B", 0 0, o000000000367c838; alias, 0 drivers
+v000000000374f430_0 .net "C_N", 0 0, o000000000367c868; alias, 0 drivers
+v0000000003751ff0_0 .net "D_N", 0 0, o000000000367c898; alias, 0 drivers
+L_00000000038d56e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374fe30_0 .net8 "VGND", 0 0, L_00000000038d56e0; 1 drivers, strength-aware
+L_00000000038d4100 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003751190_0 .net8 "VNB", 0 0, L_00000000038d4100; 1 drivers, strength-aware
+L_00000000038d5750 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003750510_0 .net8 "VPB", 0 0, L_00000000038d5750; 1 drivers, strength-aware
+L_00000000038d5b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374fed0_0 .net8 "VPWR", 0 0, L_00000000038d5b40; 1 drivers, strength-aware
+v000000000374fb10_0 .net "X", 0 0, L_0000000003964bf0; alias, 1 drivers
+v0000000003752090_0 .net "nand0_out", 0 0, L_0000000003963920; 1 drivers
+v0000000003750010_0 .net "or0_out_X", 0 0, L_0000000003964f70; 1 drivers
+S_0000000002732d40 .scope module, "sky130_fd_sc_hd__or4bb_2" "sky130_fd_sc_hd__or4bb_2" 4 16069;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o000000000367ccb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750150_0 .net "A", 0 0, o000000000367ccb8; 0 drivers
+o000000000367cce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750650_0 .net "B", 0 0, o000000000367cce8; 0 drivers
+o000000000367cd18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003751870_0 .net "C_N", 0 0, o000000000367cd18; 0 drivers
+o000000000367cd48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037508d0_0 .net "D_N", 0 0, o000000000367cd48; 0 drivers
+L_00000000038d4330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037510f0_0 .net8 "VGND", 0 0, L_00000000038d4330; 1 drivers, strength-aware
+L_00000000038d4480 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003750ab0_0 .net8 "VNB", 0 0, L_00000000038d4480; 1 drivers, strength-aware
+L_00000000038d43a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037501f0_0 .net8 "VPB", 0 0, L_00000000038d43a0; 1 drivers, strength-aware
+L_00000000038d57c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037512d0_0 .net8 "VPWR", 0 0, L_00000000038d57c0; 1 drivers, strength-aware
+v0000000003751370_0 .net "X", 0 0, L_0000000003964c60; 1 drivers
+S_000000000376dc70 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 16089, 4 15946 1, S_0000000002732d40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_00000000039637d0 .functor NAND 1, o000000000367cd48, o000000000367cd18, C4<1>, C4<1>;
+L_0000000003964b80 .functor OR 1, o000000000367cce8, o000000000367ccb8, L_00000000039637d0, C4<0>;
+L_0000000003964c60 .functor BUF 1, L_0000000003964b80, C4<0>, C4<0>, C4<0>;
+v0000000003751d70_0 .net "A", 0 0, o000000000367ccb8; alias, 0 drivers
+v0000000003750830_0 .net "B", 0 0, o000000000367cce8; alias, 0 drivers
+v0000000003751730_0 .net "C_N", 0 0, o000000000367cd18; alias, 0 drivers
+v00000000037505b0_0 .net "D_N", 0 0, o000000000367cd48; alias, 0 drivers
+L_00000000038d58a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003750470_0 .net8 "VGND", 0 0, L_00000000038d58a0; 1 drivers, strength-aware
+L_00000000038d5910 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003751230_0 .net8 "VNB", 0 0, L_00000000038d5910; 1 drivers, strength-aware
+L_00000000038d5980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003751410_0 .net8 "VPB", 0 0, L_00000000038d5980; 1 drivers, strength-aware
+L_00000000038d4560 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003750a10_0 .net8 "VPWR", 0 0, L_00000000038d4560; 1 drivers, strength-aware
+v0000000003751550_0 .net "X", 0 0, L_0000000003964c60; alias, 1 drivers
+v00000000037500b0_0 .net "nand0_out", 0 0, L_00000000039637d0; 1 drivers
+v00000000037506f0_0 .net "or0_out_X", 0 0, L_0000000003964b80; 1 drivers
+S_00000000027325c0 .scope module, "sky130_fd_sc_hd__or4bb_4" "sky130_fd_sc_hd__or4bb_4" 4 15507;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+o000000000367d168 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750f10_0 .net "A", 0 0, o000000000367d168; 0 drivers
+o000000000367d198 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003750fb0_0 .net "B", 0 0, o000000000367d198; 0 drivers
+o000000000367d1c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003751050_0 .net "C_N", 0 0, o000000000367d1c8; 0 drivers
+o000000000367d1f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037514b0_0 .net "D_N", 0 0, o000000000367d1f8; 0 drivers
+L_00000000038d41e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037515f0_0 .net8 "VGND", 0 0, L_00000000038d41e0; 1 drivers, strength-aware
+L_00000000038d4250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000374fc50_0 .net8 "VNB", 0 0, L_00000000038d4250; 1 drivers, strength-aware
+L_00000000038d42c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000374fd90_0 .net8 "VPB", 0 0, L_00000000038d42c0; 1 drivers, strength-aware
+L_0000000003912f60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003751690_0 .net8 "VPWR", 0 0, L_0000000003912f60; 1 drivers, strength-aware
+v0000000003751910_0 .net "X", 0 0, L_0000000003964cd0; 1 drivers
+S_000000000376c170 .scope module, "base" "sky130_fd_sc_hd__or4bb" 4 15527, 4 15946 1, S_00000000027325c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C_N"
+ .port_info 4 /INPUT 1 "D_N"
+L_0000000003964090 .functor NAND 1, o000000000367d1f8, o000000000367d1c8, C4<1>, C4<1>;
+L_0000000003964170 .functor OR 1, o000000000367d198, o000000000367d168, L_0000000003964090, C4<0>;
+L_0000000003964cd0 .functor BUF 1, L_0000000003964170, C4<0>, C4<0>, C4<0>;
+v000000000374fcf0_0 .net "A", 0 0, o000000000367d168; alias, 0 drivers
+v0000000003750290_0 .net "B", 0 0, o000000000367d198; alias, 0 drivers
+v000000000374fbb0_0 .net "C_N", 0 0, o000000000367d1c8; alias, 0 drivers
+v0000000003750970_0 .net "D_N", 0 0, o000000000367d1f8; alias, 0 drivers
+L_00000000039135f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003750b50_0 .net8 "VGND", 0 0, L_00000000039135f0; 1 drivers, strength-aware
+L_00000000039134a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003751e10_0 .net8 "VNB", 0 0, L_00000000039134a0; 1 drivers, strength-aware
+L_00000000039130b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003750bf0_0 .net8 "VPB", 0 0, L_00000000039130b0; 1 drivers, strength-aware
+L_0000000003912710 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003750d30_0 .net8 "VPWR", 0 0, L_0000000003912710; 1 drivers, strength-aware
+v00000000037517d0_0 .net "X", 0 0, L_0000000003964cd0; alias, 1 drivers
+v0000000003750dd0_0 .net "nand0_out", 0 0, L_0000000003964090; 1 drivers
+v0000000003750e70_0 .net "or0_out_X", 0 0, L_0000000003964170; 1 drivers
+S_00000000027316c0 .scope module, "sky130_fd_sc_hd__probe_p_8" "sky130_fd_sc_hd__probe_p_8" 4 53853;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000367d618 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037538f0_0 .net "A", 0 0, o000000000367d618; 0 drivers
+L_00000000039136d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003752810_0 .net8 "VGND", 0 0, L_00000000039136d0; 1 drivers, strength-aware
+L_00000000039133c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003753df0_0 .net8 "VNB", 0 0, L_00000000039133c0; 1 drivers, strength-aware
+L_0000000003912940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003754070_0 .net8 "VPB", 0 0, L_0000000003912940; 1 drivers, strength-aware
+L_0000000003912780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003753490_0 .net8 "VPWR", 0 0, L_0000000003912780; 1 drivers, strength-aware
+v0000000003753cb0_0 .net "X", 0 0, L_0000000003964d40; 1 drivers
+S_000000000376c470 .scope module, "base" "sky130_fd_sc_hd__probe_p" 4 53867, 4 53747 1, S_00000000027316c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003964410 .functor BUF 1, o000000000367d618, C4<0>, C4<0>, C4<0>;
+L_0000000003964d40 .functor BUF 1, L_0000000003964410, C4<0>, C4<0>, C4<0>;
+v00000000037519b0_0 .net "A", 0 0, o000000000367d618; alias, 0 drivers
+L_00000000039122b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003751a50_0 .net8 "VGND", 0 0, L_00000000039122b0; 1 drivers, strength-aware
+L_00000000039124e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003751af0_0 .net8 "VNB", 0 0, L_00000000039124e0; 1 drivers, strength-aware
+L_0000000003913510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003751b90_0 .net8 "VPB", 0 0, L_0000000003913510; 1 drivers, strength-aware
+L_0000000003912be0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003751c30_0 .net8 "VPWR", 0 0, L_0000000003912be0; 1 drivers, strength-aware
+v0000000003751eb0_0 .net "X", 0 0, L_0000000003964d40; alias, 1 drivers
+v0000000003751f50_0 .net "buf0_out_X", 0 0, L_0000000003964410; 1 drivers
+S_0000000002732740 .scope module, "sky130_fd_sc_hd__probec_p_8" "sky130_fd_sc_hd__probec_p_8" 4 66336;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+o000000000367d8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003752950_0 .net "A", 0 0, o000000000367d8e8; 0 drivers
+L_0000000003912fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003752f90_0 .net8 "VGND", 0 0, L_0000000003912fd0; 1 drivers, strength-aware
+L_0000000003912c50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037533f0_0 .net8 "VNB", 0 0, L_0000000003912c50; 1 drivers, strength-aware
+L_0000000003912400 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003753990_0 .net8 "VPB", 0 0, L_0000000003912400; 1 drivers, strength-aware
+L_0000000003912da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037524f0_0 .net8 "VPWR", 0 0, L_0000000003912da0; 1 drivers, strength-aware
+v0000000003754430_0 .net "X", 0 0, L_0000000003965050; 1 drivers
+S_000000000376c5f0 .scope module, "base" "sky130_fd_sc_hd__probec_p" 4 66350, 4 66624 1, S_0000000002732740;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+L_0000000003964e90 .functor BUF 1, o000000000367d8e8, C4<0>, C4<0>, C4<0>;
+L_0000000003965050 .functor BUF 1, L_0000000003964e90, C4<0>, C4<0>, C4<0>;
+v0000000003754610_0 .net "A", 0 0, o000000000367d8e8; alias, 0 drivers
+L_0000000003913200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003753a30_0 .net8 "VGND", 0 0, L_0000000003913200; 1 drivers, strength-aware
+L_0000000003911d70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003752450_0 .net8 "VNB", 0 0, L_0000000003911d70; 1 drivers, strength-aware
+L_0000000003911ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003753ad0_0 .net8 "VPB", 0 0, L_0000000003911ec0; 1 drivers, strength-aware
+L_00000000039137b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037528b0_0 .net8 "VPWR", 0 0, L_00000000039137b0; 1 drivers, strength-aware
+v0000000003753fd0_0 .net "X", 0 0, L_0000000003965050; alias, 1 drivers
+v0000000003752130_0 .net "buf0_out_X", 0 0, L_0000000003964e90; 1 drivers
+S_0000000002730dc0 .scope module, "sky130_fd_sc_hd__sdfbbn_1" "sky130_fd_sc_hd__sdfbbn_1" 4 70811;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK_N"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000367dbe8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003752770_0 .net "CLK_N", 0 0, o000000000367dbe8; 0 drivers
+o000000000367dc48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037547f0_0 .net "D", 0 0, o000000000367dc48; 0 drivers
+v0000000003754890_0 .net "Q", 0 0, L_0000000003966400; 1 drivers
+v0000000003752270_0 .net "Q_N", 0 0, L_00000000039657c0; 1 drivers
+o000000000367dd38 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003754f70_0 .net "RESET_B", 0 0, o000000000367dd38; 0 drivers
+o000000000367dd98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003756550_0 .net "SCD", 0 0, o000000000367dd98; 0 drivers
+o000000000367ddf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003755290_0 .net "SCE", 0 0, o000000000367ddf8; 0 drivers
+o000000000367de88 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003754bb0_0 .net "SET_B", 0 0, o000000000367de88; 0 drivers
+L_0000000003913040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003754930_0 .net8 "VGND", 0 0, L_0000000003913040; 1 drivers, strength-aware
+L_0000000003913270 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003756690_0 .net8 "VNB", 0 0, L_0000000003913270; 1 drivers, strength-aware
+L_0000000003912080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003756050_0 .net8 "VPB", 0 0, L_0000000003912080; 1 drivers, strength-aware
+L_0000000003912b00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003755830_0 .net8 "VPWR", 0 0, L_0000000003912b00; 1 drivers, strength-aware
+S_000000000376a1f0 .scope module, "base" "sky130_fd_sc_hd__sdfbbn" 4 70837, 4 71206 1, S_0000000002730dc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK_N"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000367dd68 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966240 .functor NOT 1, o000000000367dd68, C4<0>, C4<0>, C4<0>;
+o000000000367deb8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039651a0 .functor NOT 1, o000000000367deb8, C4<0>, C4<0>, C4<0>;
+o000000000367dc18 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966390 .functor NOT 1, o000000000367dc18, C4<0>, C4<0>, C4<0>;
+o000000000367dc78 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000367ddc8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000367de28 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966320 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000367dc78, o000000000367ddc8, o000000000367de28;
+L_0000000003913120 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003911f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039662b0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_00000000039651a0, L_0000000003966240, L_0000000003966390, L_0000000003966320, v00000000037532b0_0, L_0000000003913120, L_0000000003911f30;
+L_0000000003965830 .functor AND 1, L_000000000380fe40, L_000000000380ff80, C4<1>, C4<1>;
+L_0000000003965440 .functor AND 1, L_000000000380fe40, L_0000000003810de0, C4<1>, C4<1>;
+L_0000000003965910 .functor AND 1, L_0000000003965830, L_0000000003965440, C4<1>, C4<1>;
+L_0000000003965210 .functor AND 1, L_00000000038103e0, L_0000000003965910, C4<1>, C4<1>;
+L_0000000003965c20 .functor AND 1, L_000000000380f940, L_0000000003965910, C4<1>, C4<1>;
+L_0000000003966550 .functor AND 1, L_0000000003810c00, L_0000000003965910, C4<1>, C4<1>;
+L_0000000003966400 .functor BUF 1, L_00000000039662b0, C4<0>, C4<0>, C4<0>;
+L_00000000039657c0 .functor NOT 1, L_00000000039662b0, C4<0>, C4<0>, C4<0>;
+v0000000003752590_0 .net "CLK", 0 0, L_0000000003966390; 1 drivers
+v00000000037521d0_0 .net "CLK_N", 0 0, o000000000367dbe8; alias, 0 drivers
+v0000000003753b70_0 .net "CLK_N_delayed", 0 0, o000000000367dc18; 0 drivers
+v00000000037537b0_0 .net "D", 0 0, o000000000367dc48; alias, 0 drivers
+v0000000003753c10_0 .net "D_delayed", 0 0, o000000000367dc78; 0 drivers
+v0000000003752630_0 .net "Q", 0 0, L_0000000003966400; alias, 1 drivers
+v0000000003754750_0 .net "Q_N", 0 0, L_00000000039657c0; alias, 1 drivers
+v0000000003752b30_0 .net "RESET", 0 0, L_0000000003966240; 1 drivers
+v00000000037535d0_0 .net "RESET_B", 0 0, o000000000367dd38; alias, 0 drivers
+v00000000037529f0_0 .net "RESET_B_delayed", 0 0, o000000000367dd68; 0 drivers
+v0000000003754250_0 .net "SCD", 0 0, o000000000367dd98; alias, 0 drivers
+v0000000003753350_0 .net "SCD_delayed", 0 0, o000000000367ddc8; 0 drivers
+v0000000003752ef0_0 .net "SCE", 0 0, o000000000367ddf8; alias, 0 drivers
+v0000000003754110_0 .net "SCE_delayed", 0 0, o000000000367de28; 0 drivers
+v0000000003753670_0 .net "SET", 0 0, L_00000000039651a0; 1 drivers
+v0000000003753d50_0 .net "SET_B", 0 0, o000000000367de88; alias, 0 drivers
+v00000000037541b0_0 .net "SET_B_delayed", 0 0, o000000000367deb8; 0 drivers
+v0000000003753530_0 .net8 "VGND", 0 0, L_0000000003911f30; 1 drivers, strength-aware
+L_00000000039126a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003752a90_0 .net8 "VNB", 0 0, L_00000000039126a0; 1 drivers, strength-aware
+L_0000000003911fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003752bd0_0 .net8 "VPB", 0 0, L_0000000003911fa0; 1 drivers, strength-aware
+v00000000037526d0_0 .net8 "VPWR", 0 0, L_0000000003913120; 1 drivers, strength-aware
+v0000000003752c70_0 .net *"_s10", 0 0, L_000000000380ff80; 1 drivers
+L_0000000003971a90 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003752d10_0 .net/2u *"_s14", 0 0, L_0000000003971a90; 1 drivers
+v00000000037523b0_0 .net *"_s16", 0 0, L_0000000003810de0; 1 drivers
+L_0000000003971ad8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037544d0_0 .net/2u *"_s22", 0 0, L_0000000003971ad8; 1 drivers
+v0000000003753e90_0 .net *"_s24", 0 0, L_00000000038103e0; 1 drivers
+L_0000000003971b20 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003753f30_0 .net/2u *"_s28", 0 0, L_0000000003971b20; 1 drivers
+v0000000003752db0_0 .net *"_s30", 0 0, L_000000000380f940; 1 drivers
+v0000000003752e50_0 .net *"_s34", 0 0, L_0000000003810c00; 1 drivers
+L_0000000003971a00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037542f0_0 .net/2u *"_s4", 0 0, L_0000000003971a00; 1 drivers
+L_0000000003971a48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003754390_0 .net/2u *"_s8", 0 0, L_0000000003971a48; 1 drivers
+v0000000003752310_0 .net "awake", 0 0, L_000000000380fe40; 1 drivers
+v0000000003753710_0 .net "buf_Q", 0 0, L_00000000039662b0; 1 drivers
+v0000000003753030_0 .net "cond0", 0 0, L_0000000003965830; 1 drivers
+v0000000003753170_0 .net "cond1", 0 0, L_0000000003965440; 1 drivers
+v0000000003754570_0 .net "cond_D", 0 0, L_0000000003965210; 1 drivers
+v0000000003753850_0 .net "cond_SCD", 0 0, L_0000000003965c20; 1 drivers
+v00000000037546b0_0 .net "cond_SCE", 0 0, L_0000000003966550; 1 drivers
+v00000000037530d0_0 .net "condb", 0 0, L_0000000003965910; 1 drivers
+v0000000003753210_0 .net "mux_out", 0 0, L_0000000003966320; 1 drivers
+v00000000037532b0_0 .var "notifier", 0 0;
+L_000000000380fe40 .cmp/eeq 1, L_0000000003913120, L_0000000003971a00;
+L_000000000380ff80 .cmp/eeq 1, o000000000367dd68, L_0000000003971a48;
+L_0000000003810de0 .cmp/eeq 1, o000000000367deb8, L_0000000003971a90;
+L_00000000038103e0 .cmp/eeq 1, o000000000367de28, L_0000000003971ad8;
+L_000000000380f940 .cmp/eeq 1, o000000000367de28, L_0000000003971b20;
+L_0000000003810c00 .cmp/nee 1, o000000000367dc78, o000000000367ddc8;
+S_00000000027328c0 .scope module, "sky130_fd_sc_hd__sdfbbn_2" "sky130_fd_sc_hd__sdfbbn_2" 4 70674;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK_N"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000378c738 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003756910_0 .net "CLK_N", 0 0, o000000000378c738; 0 drivers
+o000000000378c798 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003756eb0_0 .net "D", 0 0, o000000000378c798; 0 drivers
+v0000000003755790_0 .net "Q", 0 0, L_00000000039664e0; 1 drivers
+v0000000003756f50_0 .net "Q_N", 0 0, L_0000000003965280; 1 drivers
+o000000000378c888 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037569b0_0 .net "RESET_B", 0 0, o000000000378c888; 0 drivers
+o000000000378c8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003756a50_0 .net "SCD", 0 0, o000000000378c8e8; 0 drivers
+o000000000378c948 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003755c90_0 .net "SCE", 0 0, o000000000378c948; 0 drivers
+o000000000378c9d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003756af0_0 .net "SET_B", 0 0, o000000000378c9d8; 0 drivers
+L_0000000003913350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003756b90_0 .net8 "VGND", 0 0, L_0000000003913350; 1 drivers, strength-aware
+L_0000000003913820 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003756c30_0 .net8 "VNB", 0 0, L_0000000003913820; 1 drivers, strength-aware
+L_0000000003912ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003754a70_0 .net8 "VPB", 0 0, L_0000000003912ef0; 1 drivers, strength-aware
+L_00000000039127f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003754b10_0 .net8 "VPWR", 0 0, L_00000000039127f0; 1 drivers, strength-aware
+S_000000000376cd70 .scope module, "base" "sky130_fd_sc_hd__sdfbbn" 4 70700, 4 71206 1, S_00000000027328c0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK_N"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000378c8b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966cc0 .functor NOT 1, o000000000378c8b8, C4<0>, C4<0>, C4<0>;
+o000000000378ca08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039665c0 .functor NOT 1, o000000000378ca08, C4<0>, C4<0>, C4<0>;
+o000000000378c768 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039667f0 .functor NOT 1, o000000000378c768, C4<0>, C4<0>, C4<0>;
+o000000000378c7c8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378c918 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378c978 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039658a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378c7c8, o000000000378c918, o000000000378c978;
+L_0000000003912390 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003912e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003965ad0 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_00000000039665c0, L_0000000003966cc0, L_00000000039667f0, L_00000000039658a0, v00000000037556f0_0, L_0000000003912390, L_0000000003912e10;
+L_0000000003966630 .functor AND 1, L_0000000003811100, L_0000000003811ce0, C4<1>, C4<1>;
+L_0000000003966a20 .functor AND 1, L_0000000003811100, L_0000000003811920, C4<1>, C4<1>;
+L_0000000003965b40 .functor AND 1, L_0000000003966630, L_0000000003966a20, C4<1>, C4<1>;
+L_0000000003965130 .functor AND 1, L_0000000003810a20, L_0000000003965b40, C4<1>, C4<1>;
+L_0000000003965ec0 .functor AND 1, L_0000000003810520, L_0000000003965b40, C4<1>, C4<1>;
+L_0000000003965fa0 .functor AND 1, L_000000000380fee0, L_0000000003965b40, C4<1>, C4<1>;
+L_00000000039664e0 .functor BUF 1, L_0000000003965ad0, C4<0>, C4<0>, C4<0>;
+L_0000000003965280 .functor NOT 1, L_0000000003965ad0, C4<0>, C4<0>, C4<0>;
+v0000000003755010_0 .net "CLK", 0 0, L_00000000039667f0; 1 drivers
+v0000000003756230_0 .net "CLK_N", 0 0, o000000000378c738; alias, 0 drivers
+v00000000037549d0_0 .net "CLK_N_delayed", 0 0, o000000000378c768; 0 drivers
+v0000000003755330_0 .net "D", 0 0, o000000000378c798; alias, 0 drivers
+v0000000003755b50_0 .net "D_delayed", 0 0, o000000000378c7c8; 0 drivers
+v00000000037553d0_0 .net "Q", 0 0, L_00000000039664e0; alias, 1 drivers
+v0000000003754d90_0 .net "Q_N", 0 0, L_0000000003965280; alias, 1 drivers
+v0000000003755970_0 .net "RESET", 0 0, L_0000000003966cc0; 1 drivers
+v0000000003756190_0 .net "RESET_B", 0 0, o000000000378c888; alias, 0 drivers
+v0000000003755dd0_0 .net "RESET_B_delayed", 0 0, o000000000378c8b8; 0 drivers
+v00000000037565f0_0 .net "SCD", 0 0, o000000000378c8e8; alias, 0 drivers
+v0000000003756cd0_0 .net "SCD_delayed", 0 0, o000000000378c918; 0 drivers
+v0000000003755e70_0 .net "SCE", 0 0, o000000000378c948; alias, 0 drivers
+v0000000003755f10_0 .net "SCE_delayed", 0 0, o000000000378c978; 0 drivers
+v0000000003755470_0 .net "SET", 0 0, L_00000000039665c0; 1 drivers
+v0000000003755150_0 .net "SET_B", 0 0, o000000000378c9d8; alias, 0 drivers
+v00000000037550b0_0 .net "SET_B_delayed", 0 0, o000000000378ca08; 0 drivers
+v0000000003754cf0_0 .net8 "VGND", 0 0, L_0000000003912e10; 1 drivers, strength-aware
+L_0000000003912e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003755a10_0 .net8 "VNB", 0 0, L_0000000003912e80; 1 drivers, strength-aware
+L_00000000039129b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003754e30_0 .net8 "VPB", 0 0, L_00000000039129b0; 1 drivers, strength-aware
+v0000000003756d70_0 .net8 "VPWR", 0 0, L_0000000003912390; 1 drivers, strength-aware
+v00000000037558d0_0 .net *"_s10", 0 0, L_0000000003811ce0; 1 drivers
+L_0000000003971bf8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003756e10_0 .net/2u *"_s14", 0 0, L_0000000003971bf8; 1 drivers
+v0000000003755ab0_0 .net *"_s16", 0 0, L_0000000003811920; 1 drivers
+L_0000000003971c40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003755bf0_0 .net/2u *"_s22", 0 0, L_0000000003971c40; 1 drivers
+v0000000003755510_0 .net *"_s24", 0 0, L_0000000003810a20; 1 drivers
+L_0000000003971c88 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037555b0_0 .net/2u *"_s28", 0 0, L_0000000003971c88; 1 drivers
+v0000000003755fb0_0 .net *"_s30", 0 0, L_0000000003810520; 1 drivers
+v00000000037560f0_0 .net *"_s34", 0 0, L_000000000380fee0; 1 drivers
+L_0000000003971b68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037562d0_0 .net/2u *"_s4", 0 0, L_0000000003971b68; 1 drivers
+L_0000000003971bb0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003755d30_0 .net/2u *"_s8", 0 0, L_0000000003971bb0; 1 drivers
+v0000000003754c50_0 .net "awake", 0 0, L_0000000003811100; 1 drivers
+v0000000003756370_0 .net "buf_Q", 0 0, L_0000000003965ad0; 1 drivers
+v00000000037551f0_0 .net "cond0", 0 0, L_0000000003966630; 1 drivers
+v0000000003756410_0 .net "cond1", 0 0, L_0000000003966a20; 1 drivers
+v00000000037564b0_0 .net "cond_D", 0 0, L_0000000003965130; 1 drivers
+v0000000003756730_0 .net "cond_SCD", 0 0, L_0000000003965ec0; 1 drivers
+v00000000037567d0_0 .net "cond_SCE", 0 0, L_0000000003965fa0; 1 drivers
+v0000000003756870_0 .net "condb", 0 0, L_0000000003965b40; 1 drivers
+v0000000003755650_0 .net "mux_out", 0 0, L_00000000039658a0; 1 drivers
+v00000000037556f0_0 .var "notifier", 0 0;
+L_0000000003811100 .cmp/eeq 1, L_0000000003912390, L_0000000003971b68;
+L_0000000003811ce0 .cmp/eeq 1, o000000000378c8b8, L_0000000003971bb0;
+L_0000000003811920 .cmp/eeq 1, o000000000378ca08, L_0000000003971bf8;
+L_0000000003810a20 .cmp/eeq 1, o000000000378c978, L_0000000003971c40;
+L_0000000003810520 .cmp/eeq 1, o000000000378c978, L_0000000003971c88;
+L_000000000380fee0 .cmp/nee 1, o000000000378c7c8, o000000000378c918;
+S_0000000002730f40 .scope module, "sky130_fd_sc_hd__sdfbbp_1" "sky130_fd_sc_hd__sdfbbp_1" 4 75318;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000378d278 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037d9ca0_0 .net "CLK", 0 0, o000000000378d278; 0 drivers
+o000000000378d2d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dab00_0 .net "D", 0 0, o000000000378d2d8; 0 drivers
+v00000000037da9c0_0 .net "Q", 0 0, L_0000000003966710; 1 drivers
+v00000000037daa60_0 .net "Q_N", 0 0, L_0000000003965d70; 1 drivers
+o000000000378d3c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037db000_0 .net "RESET_B", 0 0, o000000000378d3c8; 0 drivers
+o000000000378d428 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037d9d40_0 .net "SCD", 0 0, o000000000378d428; 0 drivers
+o000000000378d488 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dace0_0 .net "SCE", 0 0, o000000000378d488; 0 drivers
+o000000000378d518 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037d95c0_0 .net "SET_B", 0 0, o000000000378d518; 0 drivers
+L_00000000039121d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037d8f80_0 .net8 "VGND", 0 0, L_00000000039121d0; 1 drivers, strength-aware
+L_0000000003913190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dad80_0 .net8 "VNB", 0 0, L_0000000003913190; 1 drivers, strength-aware
+L_0000000003913580 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dae20_0 .net8 "VPB", 0 0, L_0000000003913580; 1 drivers, strength-aware
+L_0000000003912b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037d9660_0 .net8 "VPWR", 0 0, L_0000000003912b70; 1 drivers, strength-aware
+S_000000000376d670 .scope module, "base" "sky130_fd_sc_hd__sdfbbp" 4 75344, 4 75707 1, S_0000000002730f40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "CLK"
+ .port_info 6 /INPUT 1 "SET_B"
+ .port_info 7 /INPUT 1 "RESET_B"
+o000000000378d3f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039666a0 .functor NOT 1, o000000000378d3f8, C4<0>, C4<0>, C4<0>;
+o000000000378d548 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003965670 .functor NOT 1, o000000000378d548, C4<0>, C4<0>, C4<0>;
+o000000000378d308 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378d458 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378d4b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003965bb0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378d308, o000000000378d458, o000000000378d4b8;
+o000000000378d2a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003912010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039120f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003965c90 .udp UDP_sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N, L_0000000003965670, L_00000000039666a0, o000000000378d2a8, L_0000000003965bb0, v00000000037d9ac0_0, L_0000000003912010, L_00000000039120f0;
+L_0000000003966470 .functor AND 1, L_000000000380fb20, L_00000000038105c0, C4<1>, C4<1>;
+L_0000000003965980 .functor AND 1, L_000000000380fb20, L_0000000003811380, C4<1>, C4<1>;
+L_00000000039659f0 .functor AND 1, L_0000000003966470, L_0000000003965980, C4<1>, C4<1>;
+L_0000000003966a90 .functor AND 1, L_0000000003810160, L_00000000039659f0, C4<1>, C4<1>;
+L_0000000003966b70 .functor AND 1, L_0000000003811c40, L_00000000039659f0, C4<1>, C4<1>;
+L_0000000003965d00 .functor AND 1, L_00000000038117e0, L_00000000039659f0, C4<1>, C4<1>;
+L_0000000003966710 .functor BUF 1, L_0000000003965c90, C4<0>, C4<0>, C4<0>;
+L_0000000003965d70 .functor NOT 1, L_0000000003965c90, C4<0>, C4<0>, C4<0>;
+v0000000003754ed0_0 .net "CLK", 0 0, o000000000378d278; alias, 0 drivers
+v00000000037da380_0 .net "CLK_delayed", 0 0, o000000000378d2a8; 0 drivers
+v00000000037d9840_0 .net "D", 0 0, o000000000378d2d8; alias, 0 drivers
+v00000000037d8d00_0 .net "D_delayed", 0 0, o000000000378d308; 0 drivers
+v00000000037da880_0 .net "Q", 0 0, L_0000000003966710; alias, 1 drivers
+v00000000037d97a0_0 .net "Q_N", 0 0, L_0000000003965d70; alias, 1 drivers
+v00000000037da100_0 .net "RESET", 0 0, L_00000000039666a0; 1 drivers
+v00000000037d9480_0 .net "RESET_B", 0 0, o000000000378d3c8; alias, 0 drivers
+v00000000037d8da0_0 .net "RESET_B_delayed", 0 0, o000000000378d3f8; 0 drivers
+v00000000037da240_0 .net "SCD", 0 0, o000000000378d428; alias, 0 drivers
+v00000000037da1a0_0 .net "SCD_delayed", 0 0, o000000000378d458; 0 drivers
+v00000000037d9520_0 .net "SCE", 0 0, o000000000378d488; alias, 0 drivers
+v00000000037da2e0_0 .net "SCE_delayed", 0 0, o000000000378d4b8; 0 drivers
+v00000000037d98e0_0 .net "SET", 0 0, L_0000000003965670; 1 drivers
+v00000000037d8bc0_0 .net "SET_B", 0 0, o000000000378d518; alias, 0 drivers
+v00000000037da600_0 .net "SET_B_delayed", 0 0, o000000000378d548; 0 drivers
+v00000000037d9340_0 .net8 "VGND", 0 0, L_00000000039120f0; 1 drivers, strength-aware
+L_0000000003912cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037daba0_0 .net8 "VNB", 0 0, L_0000000003912cc0; 1 drivers, strength-aware
+L_0000000003912a20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037d9b60_0 .net8 "VPB", 0 0, L_0000000003912a20; 1 drivers, strength-aware
+v00000000037da6a0_0 .net8 "VPWR", 0 0, L_0000000003912010; 1 drivers, strength-aware
+v00000000037da420_0 .net *"_s10", 0 0, L_00000000038105c0; 1 drivers
+L_0000000003971d60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037d9980_0 .net/2u *"_s14", 0 0, L_0000000003971d60; 1 drivers
+v00000000037d89e0_0 .net *"_s16", 0 0, L_0000000003811380; 1 drivers
+L_0000000003971da8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037d8c60_0 .net/2u *"_s22", 0 0, L_0000000003971da8; 1 drivers
+v00000000037d9c00_0 .net *"_s24", 0 0, L_0000000003810160; 1 drivers
+L_0000000003971df0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037daf60_0 .net/2u *"_s28", 0 0, L_0000000003971df0; 1 drivers
+v00000000037da560_0 .net *"_s30", 0 0, L_0000000003811c40; 1 drivers
+v00000000037da4c0_0 .net *"_s34", 0 0, L_00000000038117e0; 1 drivers
+L_0000000003971cd0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037d90c0_0 .net/2u *"_s4", 0 0, L_0000000003971cd0; 1 drivers
+L_0000000003971d18 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037da7e0_0 .net/2u *"_s8", 0 0, L_0000000003971d18; 1 drivers
+v00000000037d93e0_0 .net "awake", 0 0, L_000000000380fb20; 1 drivers
+v00000000037d8ee0_0 .net "buf_Q", 0 0, L_0000000003965c90; 1 drivers
+v00000000037d9020_0 .net "cond0", 0 0, L_0000000003966470; 1 drivers
+v00000000037d9a20_0 .net "cond1", 0 0, L_0000000003965980; 1 drivers
+v00000000037da920_0 .net "cond_D", 0 0, L_0000000003966a90; 1 drivers
+v00000000037dac40_0 .net "cond_SCD", 0 0, L_0000000003966b70; 1 drivers
+v00000000037da740_0 .net "cond_SCE", 0 0, L_0000000003965d00; 1 drivers
+v00000000037d8e40_0 .net "condb", 0 0, L_00000000039659f0; 1 drivers
+v00000000037d8940_0 .net "mux_out", 0 0, L_0000000003965bb0; 1 drivers
+v00000000037d9ac0_0 .var "notifier", 0 0;
+L_000000000380fb20 .cmp/eeq 1, L_0000000003912010, L_0000000003971cd0;
+L_00000000038105c0 .cmp/eeq 1, o000000000378d3f8, L_0000000003971d18;
+L_0000000003811380 .cmp/eeq 1, o000000000378d548, L_0000000003971d60;
+L_0000000003810160 .cmp/eeq 1, o000000000378d4b8, L_0000000003971da8;
+L_0000000003811c40 .cmp/eeq 1, o000000000378d4b8, L_0000000003971df0;
+L_00000000038117e0 .cmp/nee 1, o000000000378d308, o000000000378d458;
+S_0000000002731e40 .scope module, "sky130_fd_sc_hd__sdfrbp_1" "sky130_fd_sc_hd__sdfrbp_1" 4 22881;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "RESET_B"
+o000000000378ddb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dd4e0_0 .net "CLK", 0 0, o000000000378ddb8; 0 drivers
+o000000000378de18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dbb40_0 .net "D", 0 0, o000000000378de18; 0 drivers
+v00000000037dbbe0_0 .net "Q", 0 0, L_0000000003965de0; 1 drivers
+v00000000037dd080_0 .net "Q_N", 0 0, L_0000000003965e50; 1 drivers
+o000000000378df08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dbc80_0 .net "RESET_B", 0 0, o000000000378df08; 0 drivers
+o000000000378df68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037db8c0_0 .net "SCD", 0 0, o000000000378df68; 0 drivers
+o000000000378dfc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037db280_0 .net "SCE", 0 0, o000000000378dfc8; 0 drivers
+L_0000000003912160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037db320_0 .net8 "VGND", 0 0, L_0000000003912160; 1 drivers, strength-aware
+L_0000000003913890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dc0e0_0 .net8 "VNB", 0 0, L_0000000003913890; 1 drivers, strength-aware
+L_0000000003911d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dd580_0 .net8 "VPB", 0 0, L_0000000003911d00; 1 drivers, strength-aware
+L_0000000003912630 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dd6c0_0 .net8 "VPWR", 0 0, L_0000000003912630; 1 drivers, strength-aware
+S_000000000376c8f0 .scope module, "base" "sky130_fd_sc_hd__sdfrbp" 4 22905, 4 22726 1, S_0000000002731e40;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "RESET_B"
+o000000000378df38 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039656e0 .functor NOT 1, o000000000378df38, C4<0>, C4<0>, C4<0>;
+o000000000378de48 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378df98 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378dff8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039654b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378de48, o000000000378df98, o000000000378dff8;
+o000000000378dde8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003913660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039132e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003965750 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_00000000039654b0, o000000000378dde8, L_00000000039656e0, v00000000037dcd60_0, L_0000000003913660, L_00000000039132e0;
+L_0000000003965520 .functor AND 1, L_0000000003810200, L_0000000003811880, C4<1>, C4<1>;
+L_00000000039652f0 .functor AND 1, L_000000000380fda0, L_0000000003965520, C4<1>, C4<1>;
+L_0000000003965f30 .functor AND 1, L_0000000003810b60, L_0000000003965520, C4<1>, C4<1>;
+L_0000000003965360 .functor AND 1, L_0000000003810ac0, L_0000000003965520, C4<1>, C4<1>;
+L_00000000039653d0 .functor AND 1, L_0000000003811d80, L_0000000003811880, C4<1>, C4<1>;
+L_0000000003965de0 .functor BUF 1, L_0000000003965750, C4<0>, C4<0>, C4<0>;
+L_0000000003965e50 .functor NOT 1, L_0000000003965750, C4<0>, C4<0>, C4<0>;
+v00000000037db0a0_0 .net "CLK", 0 0, o000000000378ddb8; alias, 0 drivers
+v00000000037daec0_0 .net "CLK_delayed", 0 0, o000000000378dde8; 0 drivers
+v00000000037d8a80_0 .net "D", 0 0, o000000000378de18; alias, 0 drivers
+v00000000037d9fc0_0 .net "D_delayed", 0 0, o000000000378de48; 0 drivers
+v00000000037d9160_0 .net "Q", 0 0, L_0000000003965de0; alias, 1 drivers
+v00000000037d8b20_0 .net "Q_N", 0 0, L_0000000003965e50; alias, 1 drivers
+v00000000037d9de0_0 .net "RESET", 0 0, L_00000000039656e0; 1 drivers
+v00000000037d9200_0 .net "RESET_B", 0 0, o000000000378df08; alias, 0 drivers
+v00000000037d92a0_0 .net "RESET_B_delayed", 0 0, o000000000378df38; 0 drivers
+v00000000037d9700_0 .net "SCD", 0 0, o000000000378df68; alias, 0 drivers
+v00000000037d9e80_0 .net "SCD_delayed", 0 0, o000000000378df98; 0 drivers
+v00000000037d9f20_0 .net "SCE", 0 0, o000000000378dfc8; alias, 0 drivers
+v00000000037da060_0 .net "SCE_delayed", 0 0, o000000000378dff8; 0 drivers
+v00000000037dcf40_0 .net8 "VGND", 0 0, L_00000000039132e0; 1 drivers, strength-aware
+L_0000000003912240 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dbd20_0 .net8 "VNB", 0 0, L_0000000003912240; 1 drivers, strength-aware
+L_0000000003911de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dbfa0_0 .net8 "VPB", 0 0, L_0000000003911de0; 1 drivers, strength-aware
+v00000000037dd120_0 .net8 "VPWR", 0 0, L_0000000003913660; 1 drivers, strength-aware
+v00000000037dcb80_0 .net *"_s10", 0 0, L_0000000003810200; 1 drivers
+L_0000000003971ec8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037dc7c0_0 .net/2u *"_s14", 0 0, L_0000000003971ec8; 1 drivers
+v00000000037db140_0 .net *"_s16", 0 0, L_000000000380fda0; 1 drivers
+L_0000000003971f10 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dc220_0 .net/2u *"_s20", 0 0, L_0000000003971f10; 1 drivers
+v00000000037dcae0_0 .net *"_s22", 0 0, L_0000000003810b60; 1 drivers
+v00000000037db460_0 .net *"_s26", 0 0, L_0000000003810ac0; 1 drivers
+L_0000000003971f58 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dd620_0 .net/2u *"_s30", 0 0, L_0000000003971f58; 1 drivers
+v00000000037dc360_0 .net *"_s32", 0 0, L_0000000003811d80; 1 drivers
+L_0000000003971e38 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037db1e0_0 .net/2u *"_s4", 0 0, L_0000000003971e38; 1 drivers
+L_0000000003971e80 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dcc20_0 .net/2u *"_s8", 0 0, L_0000000003971e80; 1 drivers
+v00000000037dc860_0 .net "awake", 0 0, L_0000000003811880; 1 drivers
+v00000000037dc9a0_0 .net "buf_Q", 0 0, L_0000000003965750; 1 drivers
+v00000000037dd800_0 .net "cond0", 0 0, L_0000000003965520; 1 drivers
+v00000000037dc040_0 .net "cond1", 0 0, L_00000000039652f0; 1 drivers
+v00000000037db960_0 .net "cond2", 0 0, L_0000000003965f30; 1 drivers
+v00000000037dc2c0_0 .net "cond3", 0 0, L_0000000003965360; 1 drivers
+v00000000037dbaa0_0 .net "cond4", 0 0, L_00000000039653d0; 1 drivers
+v00000000037db500_0 .net "mux_out", 0 0, L_00000000039654b0; 1 drivers
+v00000000037dcd60_0 .var "notifier", 0 0;
+L_0000000003811880 .cmp/eeq 1, L_0000000003913660, L_0000000003971e38;
+L_0000000003810200 .cmp/eeq 1, o000000000378df38, L_0000000003971e80;
+L_000000000380fda0 .cmp/eeq 1, o000000000378dff8, L_0000000003971ec8;
+L_0000000003810b60 .cmp/eeq 1, o000000000378dff8, L_0000000003971f10;
+L_0000000003810ac0 .cmp/nee 1, o000000000378de48, o000000000378df98;
+L_0000000003811d80 .cmp/eeq 1, o000000000378df08, L_0000000003971f58;
+S_0000000002732bc0 .scope module, "sky130_fd_sc_hd__sdfrbp_2" "sky130_fd_sc_hd__sdfrbp_2" 4 22355;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "RESET_B"
+o000000000378e7d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037de840_0 .net "CLK", 0 0, o000000000378e7d8; 0 drivers
+o000000000378e838 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dfce0_0 .net "D", 0 0, o000000000378e838; 0 drivers
+v00000000037de2a0_0 .net "Q", 0 0, L_0000000003966860; 1 drivers
+v00000000037de340_0 .net "Q_N", 0 0, L_0000000003966940; 1 drivers
+o000000000378e928 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037de020_0 .net "RESET_B", 0 0, o000000000378e928; 0 drivers
+o000000000378e988 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037de3e0_0 .net "SCD", 0 0, o000000000378e988; 0 drivers
+o000000000378e9e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ddbc0_0 .net "SCE", 0 0, o000000000378e9e8; 0 drivers
+L_0000000003913430 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037de980_0 .net8 "VGND", 0 0, L_0000000003913430; 1 drivers, strength-aware
+L_0000000003912d30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ddc60_0 .net8 "VNB", 0 0, L_0000000003912d30; 1 drivers, strength-aware
+L_0000000003912a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037de8e0_0 .net8 "VPB", 0 0, L_0000000003912a90; 1 drivers, strength-aware
+L_0000000003913740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dea20_0 .net8 "VPWR", 0 0, L_0000000003913740; 1 drivers, strength-aware
+S_000000000376fd70 .scope module, "base" "sky130_fd_sc_hd__sdfrbp" 4 22379, 4 22726 1, S_0000000002732bc0;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "RESET_B"
+o000000000378e958 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003965590 .functor NOT 1, o000000000378e958, C4<0>, C4<0>, C4<0>;
+o000000000378e868 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378e9b8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378ea18 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966b00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378e868, o000000000378e9b8, o000000000378ea18;
+o000000000378e808 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003912470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003911e50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003965a60 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000003966b00, o000000000378e808, L_0000000003965590, v00000000037de660_0, L_0000000003912470, L_0000000003911e50;
+L_0000000003966010 .functor AND 1, L_0000000003810660, L_0000000003811600, C4<1>, C4<1>;
+L_0000000003966080 .functor AND 1, L_00000000038102a0, L_0000000003966010, C4<1>, C4<1>;
+L_0000000003966780 .functor AND 1, L_0000000003811f60, L_0000000003966010, C4<1>, C4<1>;
+L_00000000039660f0 .functor AND 1, L_0000000003810340, L_0000000003966010, C4<1>, C4<1>;
+L_0000000003966160 .functor AND 1, L_000000000380fbc0, L_0000000003811600, C4<1>, C4<1>;
+L_0000000003966860 .functor BUF 1, L_0000000003965a60, C4<0>, C4<0>, C4<0>;
+L_0000000003966940 .functor NOT 1, L_0000000003965a60, C4<0>, C4<0>, C4<0>;
+v00000000037dca40_0 .net "CLK", 0 0, o000000000378e7d8; alias, 0 drivers
+v00000000037dc4a0_0 .net "CLK_delayed", 0 0, o000000000378e808; 0 drivers
+v00000000037db3c0_0 .net "D", 0 0, o000000000378e838; alias, 0 drivers
+v00000000037dd8a0_0 .net "D_delayed", 0 0, o000000000378e868; 0 drivers
+v00000000037db820_0 .net "Q", 0 0, L_0000000003966860; alias, 1 drivers
+v00000000037db5a0_0 .net "Q_N", 0 0, L_0000000003966940; alias, 1 drivers
+v00000000037db640_0 .net "RESET", 0 0, L_0000000003965590; 1 drivers
+v00000000037db6e0_0 .net "RESET_B", 0 0, o000000000378e928; alias, 0 drivers
+v00000000037dd300_0 .net "RESET_B_delayed", 0 0, o000000000378e958; 0 drivers
+v00000000037dbdc0_0 .net "SCD", 0 0, o000000000378e988; alias, 0 drivers
+v00000000037dbe60_0 .net "SCD_delayed", 0 0, o000000000378e9b8; 0 drivers
+v00000000037dbf00_0 .net "SCE", 0 0, o000000000378e9e8; alias, 0 drivers
+v00000000037db780_0 .net "SCE_delayed", 0 0, o000000000378ea18; 0 drivers
+v00000000037dcfe0_0 .net8 "VGND", 0 0, L_0000000003911e50; 1 drivers, strength-aware
+L_0000000003912320 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dba00_0 .net8 "VNB", 0 0, L_0000000003912320; 1 drivers, strength-aware
+L_00000000039125c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dc180_0 .net8 "VPB", 0 0, L_00000000039125c0; 1 drivers, strength-aware
+v00000000037dd1c0_0 .net8 "VPWR", 0 0, L_0000000003912470; 1 drivers, strength-aware
+v00000000037dc400_0 .net *"_s10", 0 0, L_0000000003810660; 1 drivers
+L_0000000003972030 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037dc540_0 .net/2u *"_s14", 0 0, L_0000000003972030; 1 drivers
+v00000000037dc5e0_0 .net *"_s16", 0 0, L_00000000038102a0; 1 drivers
+L_0000000003972078 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dccc0_0 .net/2u *"_s20", 0 0, L_0000000003972078; 1 drivers
+v00000000037dc680_0 .net *"_s22", 0 0, L_0000000003811f60; 1 drivers
+v00000000037dd260_0 .net *"_s26", 0 0, L_0000000003810340; 1 drivers
+L_00000000039720c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dd3a0_0 .net/2u *"_s30", 0 0, L_00000000039720c0; 1 drivers
+v00000000037dd440_0 .net *"_s32", 0 0, L_000000000380fbc0; 1 drivers
+L_0000000003971fa0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dc720_0 .net/2u *"_s4", 0 0, L_0000000003971fa0; 1 drivers
+L_0000000003971fe8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037dc900_0 .net/2u *"_s8", 0 0, L_0000000003971fe8; 1 drivers
+v00000000037dce00_0 .net "awake", 0 0, L_0000000003811600; 1 drivers
+v00000000037dcea0_0 .net "buf_Q", 0 0, L_0000000003965a60; 1 drivers
+v00000000037dd760_0 .net "cond0", 0 0, L_0000000003966010; 1 drivers
+v00000000037ddb20_0 .net "cond1", 0 0, L_0000000003966080; 1 drivers
+v00000000037deca0_0 .net "cond2", 0 0, L_0000000003966780; 1 drivers
+v00000000037ddee0_0 .net "cond3", 0 0, L_00000000039660f0; 1 drivers
+v00000000037dd9e0_0 .net "cond4", 0 0, L_0000000003966160; 1 drivers
+v00000000037df920_0 .net "mux_out", 0 0, L_0000000003966b00; 1 drivers
+v00000000037de660_0 .var "notifier", 0 0;
+L_0000000003811600 .cmp/eeq 1, L_0000000003912470, L_0000000003971fa0;
+L_0000000003810660 .cmp/eeq 1, o000000000378e958, L_0000000003971fe8;
+L_00000000038102a0 .cmp/eeq 1, o000000000378ea18, L_0000000003972030;
+L_0000000003811f60 .cmp/eeq 1, o000000000378ea18, L_0000000003972078;
+L_0000000003810340 .cmp/nee 1, o000000000378e868, o000000000378e9b8;
+L_000000000380fbc0 .cmp/eeq 1, o000000000378e928, L_00000000039720c0;
+S_00000000026c4380 .scope module, "sky130_fd_sc_hd__sdfrtn_1" "sky130_fd_sc_hd__sdfrtn_1" 4 44917;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o000000000378f1f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037df2e0_0 .net "CLK_N", 0 0, o000000000378f1f8; 0 drivers
+o000000000378f258 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037df6a0_0 .net "D", 0 0, o000000000378f258; 0 drivers
+v00000000037df7e0_0 .net "Q", 0 0, L_0000000003967b30; 1 drivers
+o000000000378f318 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037df880_0 .net "RESET_B", 0 0, o000000000378f318; 0 drivers
+o000000000378f378 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dfa60_0 .net "SCD", 0 0, o000000000378f378; 0 drivers
+o000000000378f3d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037dfc40_0 .net "SCE", 0 0, o000000000378f3d8; 0 drivers
+L_0000000003912550 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dfd80_0 .net8 "VGND", 0 0, L_0000000003912550; 1 drivers, strength-aware
+L_0000000003912860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037dfe20_0 .net8 "VNB", 0 0, L_0000000003912860; 1 drivers, strength-aware
+L_00000000039128d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e0000_0 .net8 "VPB", 0 0, L_00000000039128d0; 1 drivers, strength-aware
+L_0000000003913b30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e00a0_0 .net8 "VPWR", 0 0, L_0000000003913b30; 1 drivers, strength-aware
+S_000000000376ddf0 .scope module, "base" "sky130_fd_sc_hd__sdfrtn" 4 44939, 4 44766 1, S_00000000026c4380;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK_N"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o000000000378f348 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039661d0 .functor NOT 1, o000000000378f348, C4<0>, C4<0>, C4<0>;
+o000000000378f228 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003965600 .functor NOT 1, o000000000378f228, C4<0>, C4<0>, C4<0>;
+o000000000378f288 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378f3a8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378f408 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039668d0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378f288, o000000000378f3a8, o000000000378f408;
+L_0000000003913eb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003913c10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039669b0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_00000000039668d0, L_0000000003965600, L_00000000039661d0, v00000000037df100_0, L_0000000003913eb0, L_0000000003913c10;
+L_0000000003966be0 .functor AND 1, L_0000000003810840, L_00000000038108e0, C4<1>, C4<1>;
+L_0000000003966c50 .functor AND 1, L_0000000003811ec0, L_0000000003966be0, C4<1>, C4<1>;
+L_0000000003968700 .functor AND 1, L_0000000003810e80, L_0000000003966be0, C4<1>, C4<1>;
+L_0000000003967970 .functor AND 1, L_0000000003811420, L_0000000003966be0, C4<1>, C4<1>;
+L_0000000003967cf0 .functor AND 1, L_0000000003810840, L_0000000003810980, C4<1>, C4<1>;
+L_0000000003967b30 .functor BUF 1, L_00000000039669b0, C4<0>, C4<0>, C4<0>;
+v00000000037dde40_0 .net "CLK_N", 0 0, o000000000378f1f8; alias, 0 drivers
+v00000000037df1a0_0 .net "CLK_N_delayed", 0 0, o000000000378f228; 0 drivers
+v00000000037ded40_0 .net "D", 0 0, o000000000378f258; alias, 0 drivers
+v00000000037ddd00_0 .net "D_delayed", 0 0, o000000000378f288; 0 drivers
+v00000000037df240_0 .net "Q", 0 0, L_0000000003967b30; alias, 1 drivers
+v00000000037de0c0_0 .net "RESET", 0 0, L_00000000039661d0; 1 drivers
+v00000000037dee80_0 .net "RESET_B", 0 0, o000000000378f318; alias, 0 drivers
+v00000000037defc0_0 .net "RESET_B_delayed", 0 0, o000000000378f348; 0 drivers
+v00000000037df380_0 .net "SCD", 0 0, o000000000378f378; alias, 0 drivers
+v00000000037dfb00_0 .net "SCD_delayed", 0 0, o000000000378f3a8; 0 drivers
+v00000000037de480_0 .net "SCE", 0 0, o000000000378f3d8; alias, 0 drivers
+v00000000037df740_0 .net "SCE_delayed", 0 0, o000000000378f408; 0 drivers
+v00000000037de520_0 .net8 "VGND", 0 0, L_0000000003913c10; 1 drivers, strength-aware
+L_0000000003913ba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ddf80_0 .net8 "VNB", 0 0, L_0000000003913ba0; 1 drivers, strength-aware
+L_0000000003914d20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037dda80_0 .net8 "VPB", 0 0, L_0000000003914d20; 1 drivers, strength-aware
+v00000000037dfec0_0 .net8 "VPWR", 0 0, L_0000000003913eb0; 1 drivers, strength-aware
+v00000000037de160_0 .net *"_s10", 0 0, L_00000000038108e0; 1 drivers
+L_0000000003972198 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037ddda0_0 .net/2u *"_s14", 0 0, L_0000000003972198; 1 drivers
+v00000000037dfba0_0 .net *"_s16", 0 0, L_0000000003811ec0; 1 drivers
+L_00000000039721e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037de200_0 .net/2u *"_s20", 0 0, L_00000000039721e0; 1 drivers
+v00000000037dff60_0 .net *"_s22", 0 0, L_0000000003810e80; 1 drivers
+v00000000037def20_0 .net *"_s26", 0 0, L_0000000003811420; 1 drivers
+L_0000000003972228 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037df420_0 .net/2u *"_s30", 0 0, L_0000000003972228; 1 drivers
+v00000000037de5c0_0 .net *"_s32", 0 0, L_0000000003810980; 1 drivers
+L_0000000003972108 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037de700_0 .net/2u *"_s4", 0 0, L_0000000003972108; 1 drivers
+L_0000000003972150 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037de7a0_0 .net/2u *"_s8", 0 0, L_0000000003972150; 1 drivers
+v00000000037deac0_0 .net "awake", 0 0, L_0000000003810840; 1 drivers
+v00000000037deb60_0 .net "buf_Q", 0 0, L_00000000039669b0; 1 drivers
+v00000000037dec00_0 .net "cond0", 0 0, L_0000000003966be0; 1 drivers
+v00000000037df4c0_0 .net "cond1", 0 0, L_0000000003966c50; 1 drivers
+v00000000037df600_0 .net "cond2", 0 0, L_0000000003968700; 1 drivers
+v00000000037df9c0_0 .net "cond3", 0 0, L_0000000003967970; 1 drivers
+v00000000037dede0_0 .net "cond4", 0 0, L_0000000003967cf0; 1 drivers
+v00000000037df060_0 .net "intclk", 0 0, L_0000000003965600; 1 drivers
+v00000000037df560_0 .net "mux_out", 0 0, L_00000000039668d0; 1 drivers
+v00000000037df100_0 .var "notifier", 0 0;
+L_0000000003810840 .cmp/eeq 1, L_0000000003913eb0, L_0000000003972108;
+L_00000000038108e0 .cmp/eeq 1, o000000000378f348, L_0000000003972150;
+L_0000000003811ec0 .cmp/eeq 1, o000000000378f408, L_0000000003972198;
+L_0000000003810e80 .cmp/eeq 1, o000000000378f408, L_00000000039721e0;
+L_0000000003811420 .cmp/nee 1, o000000000378f288, o000000000378f3a8;
+L_0000000003810980 .cmp/eeq 1, o000000000378f318, L_0000000003972228;
+S_00000000026c3d80 .scope module, "sky130_fd_sc_hd__sdfrtp_1" "sky130_fd_sc_hd__sdfrtp_1" 4 88789;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o000000000378fbb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e0320_0 .net "CLK", 0 0, o000000000378fbb8; 0 drivers
+o000000000378fc18 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e2120_0 .net "D", 0 0, o000000000378fc18; 0 drivers
+v00000000037e1d60_0 .net "Q", 0 0, L_0000000003966e80; 1 drivers
+o000000000378fcd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e1720_0 .net "RESET_B", 0 0, o000000000378fcd8; 0 drivers
+o000000000378fd38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e0a00_0 .net "SCD", 0 0, o000000000378fd38; 0 drivers
+o000000000378fd98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e1040_0 .net "SCE", 0 0, o000000000378fd98; 0 drivers
+L_0000000003914540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e0fa0_0 .net8 "VGND", 0 0, L_0000000003914540; 1 drivers, strength-aware
+L_0000000003914770 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e1c20_0 .net8 "VNB", 0 0, L_0000000003914770; 1 drivers, strength-aware
+L_0000000003913c80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e0c80_0 .net8 "VPB", 0 0, L_0000000003913c80; 1 drivers, strength-aware
+L_00000000039148c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e0aa0_0 .net8 "VPWR", 0 0, L_00000000039148c0; 1 drivers, strength-aware
+S_000000000376aaf0 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88811, 4 88390 1, S_00000000026c3d80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o000000000378fd08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039680e0 .functor NOT 1, o000000000378fd08, C4<0>, C4<0>, C4<0>;
+o000000000378fc48 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378fd68 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000378fdc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966da0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o000000000378fc48, o000000000378fd68, o000000000378fdc8;
+o000000000378fbe8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003914930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039147e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039676d0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000003966da0, o000000000378fbe8, L_00000000039680e0, v00000000037e0f00_0, L_0000000003914930, L_00000000039147e0;
+L_0000000003967900 .functor AND 1, L_0000000003810fc0, L_0000000003812000, C4<1>, C4<1>;
+L_0000000003967510 .functor AND 1, L_0000000003811060, L_0000000003967900, C4<1>, C4<1>;
+L_0000000003966e10 .functor AND 1, L_00000000038111a0, L_0000000003967900, C4<1>, C4<1>;
+L_0000000003967190 .functor AND 1, L_0000000003811240, L_0000000003967900, C4<1>, C4<1>;
+L_0000000003968540 .functor AND 1, L_00000000038112e0, L_0000000003812000, C4<1>, C4<1>;
+L_0000000003966e80 .functor BUF 1, L_00000000039676d0, C4<0>, C4<0>, C4<0>;
+v00000000037dd940_0 .net "CLK", 0 0, o000000000378fbb8; alias, 0 drivers
+v00000000037e0140_0 .net "CLK_delayed", 0 0, o000000000378fbe8; 0 drivers
+v00000000037e1180_0 .net "D", 0 0, o000000000378fc18; alias, 0 drivers
+v00000000037e0460_0 .net "D_delayed", 0 0, o000000000378fc48; 0 drivers
+v00000000037e15e0_0 .net "Q", 0 0, L_0000000003966e80; alias, 1 drivers
+v00000000037e2760_0 .net "RESET", 0 0, L_00000000039680e0; 1 drivers
+v00000000037e0500_0 .net "RESET_B", 0 0, o000000000378fcd8; alias, 0 drivers
+v00000000037e0d20_0 .net "RESET_B_delayed", 0 0, o000000000378fd08; 0 drivers
+v00000000037e0780_0 .net "SCD", 0 0, o000000000378fd38; alias, 0 drivers
+v00000000037e1ae0_0 .net "SCD_delayed", 0 0, o000000000378fd68; 0 drivers
+v00000000037e0820_0 .net "SCE", 0 0, o000000000378fd98; alias, 0 drivers
+v00000000037e0be0_0 .net "SCE_delayed", 0 0, o000000000378fdc8; 0 drivers
+v00000000037e06e0_0 .net8 "VGND", 0 0, L_00000000039147e0; 1 drivers, strength-aware
+L_0000000003913cf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e08c0_0 .net8 "VNB", 0 0, L_0000000003913cf0; 1 drivers, strength-aware
+L_00000000039151f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e24e0_0 .net8 "VPB", 0 0, L_00000000039151f0; 1 drivers, strength-aware
+v00000000037e19a0_0 .net8 "VPWR", 0 0, L_0000000003914930; 1 drivers, strength-aware
+v00000000037e1400_0 .net *"_s10", 0 0, L_0000000003810fc0; 1 drivers
+L_0000000003972300 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e1900_0 .net/2u *"_s14", 0 0, L_0000000003972300; 1 drivers
+v00000000037e1e00_0 .net *"_s16", 0 0, L_0000000003811060; 1 drivers
+L_0000000003972348 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e2440_0 .net/2u *"_s20", 0 0, L_0000000003972348; 1 drivers
+v00000000037e0e60_0 .net *"_s22", 0 0, L_00000000038111a0; 1 drivers
+v00000000037e01e0_0 .net *"_s26", 0 0, L_0000000003811240; 1 drivers
+L_0000000003972390 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e1a40_0 .net/2u *"_s30", 0 0, L_0000000003972390; 1 drivers
+v00000000037e05a0_0 .net *"_s32", 0 0, L_00000000038112e0; 1 drivers
+L_0000000003972270 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e14a0_0 .net/2u *"_s4", 0 0, L_0000000003972270; 1 drivers
+L_00000000039722b8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e2300_0 .net/2u *"_s8", 0 0, L_00000000039722b8; 1 drivers
+v00000000037e21c0_0 .net "awake", 0 0, L_0000000003812000; 1 drivers
+v00000000037e0280_0 .net "buf_Q", 0 0, L_00000000039676d0; 1 drivers
+v00000000037e1b80_0 .net "cond0", 0 0, L_0000000003967900; 1 drivers
+v00000000037e0640_0 .net "cond1", 0 0, L_0000000003967510; 1 drivers
+v00000000037e2800_0 .net "cond2", 0 0, L_0000000003966e10; 1 drivers
+v00000000037e0b40_0 .net "cond3", 0 0, L_0000000003967190; 1 drivers
+v00000000037e1680_0 .net "cond4", 0 0, L_0000000003968540; 1 drivers
+v00000000037e0960_0 .net "mux_out", 0 0, L_0000000003966da0; 1 drivers
+v00000000037e0f00_0 .var "notifier", 0 0;
+L_0000000003812000 .cmp/eeq 1, L_0000000003914930, L_0000000003972270;
+L_0000000003810fc0 .cmp/eeq 1, o000000000378fd08, L_00000000039722b8;
+L_0000000003811060 .cmp/eeq 1, o000000000378fdc8, L_0000000003972300;
+L_00000000038111a0 .cmp/eeq 1, o000000000378fdc8, L_0000000003972348;
+L_0000000003811240 .cmp/nee 1, o000000000378fc48, o000000000378fd68;
+L_00000000038112e0 .cmp/eeq 1, o000000000378fcd8, L_0000000003972390;
+S_00000000026c4500 .scope module, "sky130_fd_sc_hd__sdfrtp_2" "sky130_fd_sc_hd__sdfrtp_2" 4 88539;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003790548 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e3700_0 .net "CLK", 0 0, o0000000003790548; 0 drivers
+o00000000037905a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e4100_0 .net "D", 0 0, o00000000037905a8; 0 drivers
+v00000000037e4240_0 .net "Q", 0 0, L_0000000003967430; 1 drivers
+o0000000003790668 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e46a0_0 .net "RESET_B", 0 0, o0000000003790668; 0 drivers
+o00000000037906c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e4ce0_0 .net "SCD", 0 0, o00000000037906c8; 0 drivers
+o0000000003790728 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e3340_0 .net "SCE", 0 0, o0000000003790728; 0 drivers
+L_0000000003914000 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e37a0_0 .net8 "VGND", 0 0, L_0000000003914000; 1 drivers, strength-aware
+L_0000000003913e40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e50a0_0 .net8 "VNB", 0 0, L_0000000003913e40; 1 drivers, strength-aware
+L_00000000039143f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e4880_0 .net8 "VPB", 0 0, L_00000000039143f0; 1 drivers, strength-aware
+L_0000000003914d90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e33e0_0 .net8 "VPWR", 0 0, L_0000000003914d90; 1 drivers, strength-aware
+S_000000000376b570 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88561, 4 88390 1, S_00000000026c4500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003790698 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003968770 .functor NOT 1, o0000000003790698, C4<0>, C4<0>, C4<0>;
+o00000000037905d8 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037906f8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003790758 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039682a0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000037905d8, o00000000037906f8, o0000000003790758;
+o0000000003790578 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003915490 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003914310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003968000 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_00000000039682a0, o0000000003790578, L_0000000003968770, v00000000037e4f60_0, L_0000000003915490, L_0000000003914310;
+L_00000000039687e0 .functor AND 1, L_00000000038114c0, L_00000000038116a0, C4<1>, C4<1>;
+L_0000000003968150 .functor AND 1, L_0000000003811560, L_00000000039687e0, C4<1>, C4<1>;
+L_0000000003967ba0 .functor AND 1, L_0000000003811740, L_00000000039687e0, C4<1>, C4<1>;
+L_0000000003967d60 .functor AND 1, L_00000000038119c0, L_00000000039687e0, C4<1>, C4<1>;
+L_0000000003966ef0 .functor AND 1, L_0000000003811a60, L_00000000038116a0, C4<1>, C4<1>;
+L_0000000003967430 .functor BUF 1, L_0000000003968000, C4<0>, C4<0>, C4<0>;
+v00000000037e1ea0_0 .net "CLK", 0 0, o0000000003790548; alias, 0 drivers
+v00000000037e1220_0 .net "CLK_delayed", 0 0, o0000000003790578; 0 drivers
+v00000000037e03c0_0 .net "D", 0 0, o00000000037905a8; alias, 0 drivers
+v00000000037e1f40_0 .net "D_delayed", 0 0, o00000000037905d8; 0 drivers
+v00000000037e1cc0_0 .net "Q", 0 0, L_0000000003967430; alias, 1 drivers
+v00000000037e1fe0_0 .net "RESET", 0 0, L_0000000003968770; 1 drivers
+v00000000037e0dc0_0 .net "RESET_B", 0 0, o0000000003790668; alias, 0 drivers
+v00000000037e10e0_0 .net "RESET_B_delayed", 0 0, o0000000003790698; 0 drivers
+v00000000037e17c0_0 .net "SCD", 0 0, o00000000037906c8; alias, 0 drivers
+v00000000037e28a0_0 .net "SCD_delayed", 0 0, o00000000037906f8; 0 drivers
+v00000000037e12c0_0 .net "SCE", 0 0, o0000000003790728; alias, 0 drivers
+v00000000037e1360_0 .net "SCE_delayed", 0 0, o0000000003790758; 0 drivers
+v00000000037e1540_0 .net8 "VGND", 0 0, L_0000000003914310; 1 drivers, strength-aware
+L_0000000003914b60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e2080_0 .net8 "VNB", 0 0, L_0000000003914b60; 1 drivers, strength-aware
+L_00000000039153b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e2260_0 .net8 "VPB", 0 0, L_00000000039153b0; 1 drivers, strength-aware
+v00000000037e1860_0 .net8 "VPWR", 0 0, L_0000000003915490; 1 drivers, strength-aware
+v00000000037e23a0_0 .net *"_s10", 0 0, L_00000000038114c0; 1 drivers
+L_0000000003972468 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e2580_0 .net/2u *"_s14", 0 0, L_0000000003972468; 1 drivers
+v00000000037e2620_0 .net *"_s16", 0 0, L_0000000003811560; 1 drivers
+L_00000000039724b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e26c0_0 .net/2u *"_s20", 0 0, L_00000000039724b0; 1 drivers
+v00000000037e4380_0 .net *"_s22", 0 0, L_0000000003811740; 1 drivers
+v00000000037e3fc0_0 .net *"_s26", 0 0, L_00000000038119c0; 1 drivers
+L_00000000039724f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e4600_0 .net/2u *"_s30", 0 0, L_00000000039724f8; 1 drivers
+v00000000037e3a20_0 .net *"_s32", 0 0, L_0000000003811a60; 1 drivers
+L_00000000039723d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e3660_0 .net/2u *"_s4", 0 0, L_00000000039723d8; 1 drivers
+L_0000000003972420 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e2c60_0 .net/2u *"_s8", 0 0, L_0000000003972420; 1 drivers
+v00000000037e32a0_0 .net "awake", 0 0, L_00000000038116a0; 1 drivers
+v00000000037e3b60_0 .net "buf_Q", 0 0, L_0000000003968000; 1 drivers
+v00000000037e29e0_0 .net "cond0", 0 0, L_00000000039687e0; 1 drivers
+v00000000037e4b00_0 .net "cond1", 0 0, L_0000000003968150; 1 drivers
+v00000000037e4560_0 .net "cond2", 0 0, L_0000000003967ba0; 1 drivers
+v00000000037e4060_0 .net "cond3", 0 0, L_0000000003967d60; 1 drivers
+v00000000037e41a0_0 .net "cond4", 0 0, L_0000000003966ef0; 1 drivers
+v00000000037e2d00_0 .net "mux_out", 0 0, L_00000000039682a0; 1 drivers
+v00000000037e4f60_0 .var "notifier", 0 0;
+L_00000000038116a0 .cmp/eeq 1, L_0000000003915490, L_00000000039723d8;
+L_00000000038114c0 .cmp/eeq 1, o0000000003790698, L_0000000003972420;
+L_0000000003811560 .cmp/eeq 1, o0000000003790758, L_0000000003972468;
+L_0000000003811740 .cmp/eeq 1, o0000000003790758, L_00000000039724b0;
+L_00000000038119c0 .cmp/nee 1, o00000000037905d8, o00000000037906f8;
+L_0000000003811a60 .cmp/eeq 1, o0000000003790668, L_00000000039724f8;
+S_00000000026c5880 .scope module, "sky130_fd_sc_hd__sdfrtp_4" "sky130_fd_sc_hd__sdfrtp_4" 4 88664;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003790ed8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e4e20_0 .net "CLK", 0 0, o0000000003790ed8; 0 drivers
+o0000000003790f38 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e3d40_0 .net "D", 0 0, o0000000003790f38; 0 drivers
+v00000000037e3de0_0 .net "Q", 0 0, L_00000000039677b0; 1 drivers
+o0000000003790ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e4ec0_0 .net "RESET_B", 0 0, o0000000003790ff8; 0 drivers
+o0000000003791058 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e5280_0 .net "SCD", 0 0, o0000000003791058; 0 drivers
+o00000000037910b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e6c20_0 .net "SCE", 0 0, o00000000037910b8; 0 drivers
+L_0000000003915340 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e5c80_0 .net8 "VGND", 0 0, L_0000000003915340; 1 drivers, strength-aware
+L_0000000003913d60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e6f40_0 .net8 "VNB", 0 0, L_0000000003913d60; 1 drivers, strength-aware
+L_0000000003914bd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e6fe0_0 .net8 "VPB", 0 0, L_0000000003914bd0; 1 drivers, strength-aware
+L_0000000003913dd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e7120_0 .net8 "VPWR", 0 0, L_0000000003913dd0; 1 drivers, strength-aware
+S_000000000376c770 .scope module, "base" "sky130_fd_sc_hd__sdfrtp" 4 88686, 4 88390 1, S_00000000026c5880;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "RESET_B"
+o0000000003791028 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039681c0 .functor NOT 1, o0000000003791028, C4<0>, C4<0>, C4<0>;
+o0000000003790f68 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003791088 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037910e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967890 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003790f68, o0000000003791088, o00000000037910e8;
+o0000000003790f08 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003915420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039150a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039683f0 .udp UDP_sky130_fd_sc_hd__udp_dff$PR_pp$PG$N, L_0000000003967890, o0000000003790f08, L_00000000039681c0, v00000000037e4d80_0, L_0000000003915420, L_00000000039150a0;
+L_0000000003968070 .functor AND 1, L_0000000003811ba0, L_0000000003811b00, C4<1>, C4<1>;
+L_00000000039674a0 .functor AND 1, L_0000000003813b80, L_0000000003968070, C4<1>, C4<1>;
+L_0000000003968230 .functor AND 1, L_0000000003813900, L_0000000003968070, C4<1>, C4<1>;
+L_0000000003968850 .functor AND 1, L_0000000003814080, L_0000000003968070, C4<1>, C4<1>;
+L_0000000003968310 .functor AND 1, L_00000000038146c0, L_0000000003811b00, C4<1>, C4<1>;
+L_00000000039677b0 .functor BUF 1, L_00000000039683f0, C4<0>, C4<0>, C4<0>;
+v00000000037e3980_0 .net "CLK", 0 0, o0000000003790ed8; alias, 0 drivers
+v00000000037e3ac0_0 .net "CLK_delayed", 0 0, o0000000003790f08; 0 drivers
+v00000000037e42e0_0 .net "D", 0 0, o0000000003790f38; alias, 0 drivers
+v00000000037e5000_0 .net "D_delayed", 0 0, o0000000003790f68; 0 drivers
+v00000000037e2e40_0 .net "Q", 0 0, L_00000000039677b0; alias, 1 drivers
+v00000000037e4420_0 .net "RESET", 0 0, L_00000000039681c0; 1 drivers
+v00000000037e3520_0 .net "RESET_B", 0 0, o0000000003790ff8; alias, 0 drivers
+v00000000037e2ee0_0 .net "RESET_B_delayed", 0 0, o0000000003791028; 0 drivers
+v00000000037e2b20_0 .net "SCD", 0 0, o0000000003791058; alias, 0 drivers
+v00000000037e2940_0 .net "SCD_delayed", 0 0, o0000000003791088; 0 drivers
+v00000000037e3020_0 .net "SCE", 0 0, o00000000037910b8; alias, 0 drivers
+v00000000037e3e80_0 .net "SCE_delayed", 0 0, o00000000037910e8; 0 drivers
+v00000000037e44c0_0 .net8 "VGND", 0 0, L_00000000039150a0; 1 drivers, strength-aware
+L_0000000003914e00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e4740_0 .net8 "VNB", 0 0, L_0000000003914e00; 1 drivers, strength-aware
+L_0000000003913f20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e3ca0_0 .net8 "VPB", 0 0, L_0000000003913f20; 1 drivers, strength-aware
+v00000000037e3f20_0 .net8 "VPWR", 0 0, L_0000000003915420; 1 drivers, strength-aware
+v00000000037e35c0_0 .net *"_s10", 0 0, L_0000000003811ba0; 1 drivers
+L_00000000039725d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e3480_0 .net/2u *"_s14", 0 0, L_00000000039725d0; 1 drivers
+v00000000037e47e0_0 .net *"_s16", 0 0, L_0000000003813b80; 1 drivers
+L_0000000003972618 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e4920_0 .net/2u *"_s20", 0 0, L_0000000003972618; 1 drivers
+v00000000037e30c0_0 .net *"_s22", 0 0, L_0000000003813900; 1 drivers
+v00000000037e2bc0_0 .net *"_s26", 0 0, L_0000000003814080; 1 drivers
+L_0000000003972660 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e49c0_0 .net/2u *"_s30", 0 0, L_0000000003972660; 1 drivers
+v00000000037e2da0_0 .net *"_s32", 0 0, L_00000000038146c0; 1 drivers
+L_0000000003972540 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e2a80_0 .net/2u *"_s4", 0 0, L_0000000003972540; 1 drivers
+L_0000000003972588 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e2f80_0 .net/2u *"_s8", 0 0, L_0000000003972588; 1 drivers
+v00000000037e4a60_0 .net "awake", 0 0, L_0000000003811b00; 1 drivers
+v00000000037e3840_0 .net "buf_Q", 0 0, L_00000000039683f0; 1 drivers
+v00000000037e4ba0_0 .net "cond0", 0 0, L_0000000003968070; 1 drivers
+v00000000037e4c40_0 .net "cond1", 0 0, L_00000000039674a0; 1 drivers
+v00000000037e3160_0 .net "cond2", 0 0, L_0000000003968230; 1 drivers
+v00000000037e3200_0 .net "cond3", 0 0, L_0000000003968850; 1 drivers
+v00000000037e3c00_0 .net "cond4", 0 0, L_0000000003968310; 1 drivers
+v00000000037e38e0_0 .net "mux_out", 0 0, L_0000000003967890; 1 drivers
+v00000000037e4d80_0 .var "notifier", 0 0;
+L_0000000003811b00 .cmp/eeq 1, L_0000000003915420, L_0000000003972540;
+L_0000000003811ba0 .cmp/eeq 1, o0000000003791028, L_0000000003972588;
+L_0000000003813b80 .cmp/eeq 1, o00000000037910e8, L_00000000039725d0;
+L_0000000003813900 .cmp/eeq 1, o00000000037910e8, L_0000000003972618;
+L_0000000003814080 .cmp/nee 1, o0000000003790f68, o0000000003791088;
+L_00000000038146c0 .cmp/eeq 1, o0000000003790ff8, L_0000000003972660;
+S_00000000026c4c80 .scope module, "sky130_fd_sc_hd__sdfsbp_1" "sky130_fd_sc_hd__sdfsbp_1" 4 79454;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "SET_B"
+o0000000003791868 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e6b80_0 .net "CLK", 0 0, o0000000003791868; 0 drivers
+o00000000037918c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e5960_0 .net "D", 0 0, o00000000037918c8; 0 drivers
+v00000000037e7440_0 .net "Q", 0 0, L_0000000003968620; 1 drivers
+v00000000037e6360_0 .net "Q_N", 0 0, L_0000000003966d30; 1 drivers
+o0000000003791988 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e5a00_0 .net "SCD", 0 0, o0000000003791988; 0 drivers
+o00000000037919e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e7620_0 .net "SCE", 0 0, o00000000037919e8; 0 drivers
+o0000000003791a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e5b40_0 .net "SET_B", 0 0, o0000000003791a78; 0 drivers
+L_0000000003913ac0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e64a0_0 .net8 "VGND", 0 0, L_0000000003913ac0; 1 drivers, strength-aware
+L_0000000003915110 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e6540_0 .net8 "VNB", 0 0, L_0000000003915110; 1 drivers, strength-aware
+L_0000000003914850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e6e00_0 .net8 "VPB", 0 0, L_0000000003914850; 1 drivers, strength-aware
+L_0000000003914a80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e6860_0 .net8 "VPWR", 0 0, L_0000000003914a80; 1 drivers, strength-aware
+S_000000000376df70 .scope module, "base" "sky130_fd_sc_hd__sdfsbp" 4 79478, 4 79299 1, S_00000000026c4c80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "SET_B"
+o0000000003791aa8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003966f60 .functor NOT 1, o0000000003791aa8, C4<0>, C4<0>, C4<0>;
+o00000000037918f8 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037919b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003791a18 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003968380 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000037918f8, o00000000037919b8, o0000000003791a18;
+o0000000003791898 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039149a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003913f90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003967f90 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000003968380, o0000000003791898, L_0000000003966f60, v00000000037e58c0_0, L_00000000039149a0, L_0000000003913f90;
+L_0000000003968460 .functor AND 1, L_0000000003813040, L_0000000003813c20, C4<1>, C4<1>;
+L_0000000003967740 .functor AND 1, L_0000000003813360, L_0000000003968460, C4<1>, C4<1>;
+L_00000000039685b0 .functor AND 1, L_0000000003813cc0, L_0000000003968460, C4<1>, C4<1>;
+L_0000000003967ac0 .functor AND 1, L_0000000003813d60, L_0000000003968460, C4<1>, C4<1>;
+L_00000000039684d0 .functor AND 1, L_0000000003813e00, L_0000000003813c20, C4<1>, C4<1>;
+L_0000000003968620 .functor BUF 1, L_0000000003967f90, C4<0>, C4<0>, C4<0>;
+L_0000000003966d30 .functor NOT 1, L_0000000003967f90, C4<0>, C4<0>, C4<0>;
+v00000000037e5320_0 .net "CLK", 0 0, o0000000003791868; alias, 0 drivers
+v00000000037e6720_0 .net "CLK_delayed", 0 0, o0000000003791898; 0 drivers
+v00000000037e5f00_0 .net "D", 0 0, o00000000037918c8; alias, 0 drivers
+v00000000037e71c0_0 .net "D_delayed", 0 0, o00000000037918f8; 0 drivers
+v00000000037e5e60_0 .net "Q", 0 0, L_0000000003968620; alias, 1 drivers
+v00000000037e56e0_0 .net "Q_N", 0 0, L_0000000003966d30; alias, 1 drivers
+v00000000037e67c0_0 .net "SCD", 0 0, o0000000003791988; alias, 0 drivers
+v00000000037e5500_0 .net "SCD_delayed", 0 0, o00000000037919b8; 0 drivers
+v00000000037e7080_0 .net "SCE", 0 0, o00000000037919e8; alias, 0 drivers
+v00000000037e5fa0_0 .net "SCE_delayed", 0 0, o0000000003791a18; 0 drivers
+v00000000037e6900_0 .net "SET", 0 0, L_0000000003966f60; 1 drivers
+v00000000037e5d20_0 .net "SET_B", 0 0, o0000000003791a78; alias, 0 drivers
+v00000000037e55a0_0 .net "SET_B_delayed", 0 0, o0000000003791aa8; 0 drivers
+v00000000037e5be0_0 .net8 "VGND", 0 0, L_0000000003913f90; 1 drivers, strength-aware
+L_0000000003914150 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e6d60_0 .net8 "VNB", 0 0, L_0000000003914150; 1 drivers, strength-aware
+L_0000000003914380 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e7260_0 .net8 "VPB", 0 0, L_0000000003914380; 1 drivers, strength-aware
+v00000000037e5aa0_0 .net8 "VPWR", 0 0, L_00000000039149a0; 1 drivers, strength-aware
+v00000000037e60e0_0 .net *"_s10", 0 0, L_0000000003813040; 1 drivers
+L_0000000003972738 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e53c0_0 .net/2u *"_s14", 0 0, L_0000000003972738; 1 drivers
+v00000000037e6cc0_0 .net *"_s16", 0 0, L_0000000003813360; 1 drivers
+L_0000000003972780 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e6220_0 .net/2u *"_s20", 0 0, L_0000000003972780; 1 drivers
+v00000000037e5140_0 .net *"_s22", 0 0, L_0000000003813cc0; 1 drivers
+v00000000037e7760_0 .net *"_s26", 0 0, L_0000000003813d60; 1 drivers
+L_00000000039727c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e51e0_0 .net/2u *"_s30", 0 0, L_00000000039727c8; 1 drivers
+v00000000037e6040_0 .net *"_s32", 0 0, L_0000000003813e00; 1 drivers
+L_00000000039726a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e6180_0 .net/2u *"_s4", 0 0, L_00000000039726a8; 1 drivers
+L_00000000039726f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e5460_0 .net/2u *"_s8", 0 0, L_00000000039726f0; 1 drivers
+v00000000037e6400_0 .net "awake", 0 0, L_0000000003813c20; 1 drivers
+v00000000037e7800_0 .net "buf_Q", 0 0, L_0000000003967f90; 1 drivers
+v00000000037e5640_0 .net "cond0", 0 0, L_0000000003968460; 1 drivers
+v00000000037e5dc0_0 .net "cond1", 0 0, L_0000000003967740; 1 drivers
+v00000000037e5780_0 .net "cond2", 0 0, L_00000000039685b0; 1 drivers
+v00000000037e6ea0_0 .net "cond3", 0 0, L_0000000003967ac0; 1 drivers
+v00000000037e5820_0 .net "cond4", 0 0, L_00000000039684d0; 1 drivers
+v00000000037e62c0_0 .net "mux_out", 0 0, L_0000000003968380; 1 drivers
+v00000000037e58c0_0 .var "notifier", 0 0;
+L_0000000003813c20 .cmp/eeq 1, L_00000000039149a0, L_00000000039726a8;
+L_0000000003813040 .cmp/eeq 1, o0000000003791aa8, L_00000000039726f0;
+L_0000000003813360 .cmp/eeq 1, o0000000003791a18, L_0000000003972738;
+L_0000000003813cc0 .cmp/eeq 1, o0000000003791a18, L_0000000003972780;
+L_0000000003813d60 .cmp/nee 1, o00000000037918f8, o00000000037919b8;
+L_0000000003813e00 .cmp/eeq 1, o0000000003791a78, L_00000000039727c8;
+S_00000000026c5700 .scope module, "sky130_fd_sc_hd__sdfsbp_2" "sky130_fd_sc_hd__sdfsbp_2" 4 79585;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "SET_B"
+o0000000003792288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e9240_0 .net "CLK", 0 0, o0000000003792288; 0 drivers
+o00000000037922e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e9f60_0 .net "D", 0 0, o00000000037922e8; 0 drivers
+v00000000037e7ee0_0 .net "Q", 0 0, L_0000000003967f20; 1 drivers
+v00000000037e79e0_0 .net "Q_N", 0 0, L_0000000003967120; 1 drivers
+o00000000037923a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ea0a0_0 .net "SCD", 0 0, o00000000037923a8; 0 drivers
+o0000000003792408 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e9740_0 .net "SCE", 0 0, o0000000003792408; 0 drivers
+o0000000003792498 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037e7d00_0 .net "SET_B", 0 0, o0000000003792498; 0 drivers
+L_0000000003914070 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e7da0_0 .net8 "VGND", 0 0, L_0000000003914070; 1 drivers, strength-aware
+L_00000000039140e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e7b20_0 .net8 "VNB", 0 0, L_00000000039140e0; 1 drivers, strength-aware
+L_0000000003914e70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e92e0_0 .net8 "VPB", 0 0, L_0000000003914e70; 1 drivers, strength-aware
+L_00000000039141c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e8660_0 .net8 "VPWR", 0 0, L_00000000039141c0; 1 drivers, strength-aware
+S_000000000376cbf0 .scope module, "base" "sky130_fd_sc_hd__sdfsbp" 4 79609, 4 79299 1, S_00000000026c5700;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+ .port_info 6 /INPUT 1 "SET_B"
+o00000000037924c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967660 .functor NOT 1, o00000000037924c8, C4<0>, C4<0>, C4<0>;
+o0000000003792318 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037923d8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003792438 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967c80 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003792318, o00000000037923d8, o0000000003792438;
+o00000000037922b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003914af0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003914c40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003968690 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000003967c80, o00000000037922b8, L_0000000003967660, v00000000037e7a80_0, L_0000000003914af0, L_0000000003914c40;
+L_00000000039670b0 .functor AND 1, L_00000000038132c0, L_0000000003812fa0, C4<1>, C4<1>;
+L_00000000039688c0 .functor AND 1, L_0000000003812c80, L_00000000039670b0, C4<1>, C4<1>;
+L_0000000003967dd0 .functor AND 1, L_0000000003813ea0, L_00000000039670b0, C4<1>, C4<1>;
+L_0000000003966fd0 .functor AND 1, L_0000000003813400, L_00000000039670b0, C4<1>, C4<1>;
+L_0000000003967eb0 .functor AND 1, L_00000000038144e0, L_0000000003812fa0, C4<1>, C4<1>;
+L_0000000003967f20 .functor BUF 1, L_0000000003968690, C4<0>, C4<0>, C4<0>;
+L_0000000003967120 .functor NOT 1, L_0000000003968690, C4<0>, C4<0>, C4<0>;
+v00000000037e65e0_0 .net "CLK", 0 0, o0000000003792288; alias, 0 drivers
+v00000000037e6680_0 .net "CLK_delayed", 0 0, o00000000037922b8; 0 drivers
+v00000000037e6a40_0 .net "D", 0 0, o00000000037922e8; alias, 0 drivers
+v00000000037e69a0_0 .net "D_delayed", 0 0, o0000000003792318; 0 drivers
+v00000000037e7300_0 .net "Q", 0 0, L_0000000003967f20; alias, 1 drivers
+v00000000037e6ae0_0 .net "Q_N", 0 0, L_0000000003967120; alias, 1 drivers
+v00000000037e73a0_0 .net "SCD", 0 0, o00000000037923a8; alias, 0 drivers
+v00000000037e74e0_0 .net "SCD_delayed", 0 0, o00000000037923d8; 0 drivers
+v00000000037e7580_0 .net "SCE", 0 0, o0000000003792408; alias, 0 drivers
+v00000000037e76c0_0 .net "SCE_delayed", 0 0, o0000000003792438; 0 drivers
+v00000000037e78a0_0 .net "SET", 0 0, L_0000000003967660; 1 drivers
+v00000000037e8980_0 .net "SET_B", 0 0, o0000000003792498; alias, 0 drivers
+v00000000037e7bc0_0 .net "SET_B_delayed", 0 0, o00000000037924c8; 0 drivers
+v00000000037e9ce0_0 .net8 "VGND", 0 0, L_0000000003914c40; 1 drivers, strength-aware
+L_0000000003914cb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e87a0_0 .net8 "VNB", 0 0, L_0000000003914cb0; 1 drivers, strength-aware
+L_0000000003914ee0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e9d80_0 .net8 "VPB", 0 0, L_0000000003914ee0; 1 drivers, strength-aware
+v00000000037e9e20_0 .net8 "VPWR", 0 0, L_0000000003914af0; 1 drivers, strength-aware
+v00000000037e8840_0 .net *"_s10", 0 0, L_00000000038132c0; 1 drivers
+L_00000000039728a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e88e0_0 .net/2u *"_s14", 0 0, L_00000000039728a0; 1 drivers
+v00000000037e8340_0 .net *"_s16", 0 0, L_0000000003812c80; 1 drivers
+L_00000000039728e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ea000_0 .net/2u *"_s20", 0 0, L_00000000039728e8; 1 drivers
+v00000000037e8fc0_0 .net *"_s22", 0 0, L_0000000003813ea0; 1 drivers
+v00000000037e91a0_0 .net *"_s26", 0 0, L_0000000003813400; 1 drivers
+L_0000000003972930 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e8520_0 .net/2u *"_s30", 0 0, L_0000000003972930; 1 drivers
+v00000000037e9060_0 .net *"_s32", 0 0, L_00000000038144e0; 1 drivers
+L_0000000003972810 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e7940_0 .net/2u *"_s4", 0 0, L_0000000003972810; 1 drivers
+L_0000000003972858 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e8700_0 .net/2u *"_s8", 0 0, L_0000000003972858; 1 drivers
+v00000000037e8e80_0 .net "awake", 0 0, L_0000000003812fa0; 1 drivers
+v00000000037e9100_0 .net "buf_Q", 0 0, L_0000000003968690; 1 drivers
+v00000000037e9380_0 .net "cond0", 0 0, L_00000000039670b0; 1 drivers
+v00000000037e8ca0_0 .net "cond1", 0 0, L_00000000039688c0; 1 drivers
+v00000000037e8f20_0 .net "cond2", 0 0, L_0000000003967dd0; 1 drivers
+v00000000037e85c0_0 .net "cond3", 0 0, L_0000000003966fd0; 1 drivers
+v00000000037e83e0_0 .net "cond4", 0 0, L_0000000003967eb0; 1 drivers
+v00000000037e7f80_0 .net "mux_out", 0 0, L_0000000003967c80; 1 drivers
+v00000000037e7a80_0 .var "notifier", 0 0;
+L_0000000003812fa0 .cmp/eeq 1, L_0000000003914af0, L_0000000003972810;
+L_00000000038132c0 .cmp/eeq 1, o00000000037924c8, L_0000000003972858;
+L_0000000003812c80 .cmp/eeq 1, o0000000003792438, L_00000000039728a0;
+L_0000000003813ea0 .cmp/eeq 1, o0000000003792438, L_00000000039728e8;
+L_0000000003813400 .cmp/nee 1, o0000000003792318, o00000000037923d8;
+L_00000000038144e0 .cmp/eeq 1, o0000000003792498, L_0000000003972930;
+S_00000000026c3f00 .scope module, "sky130_fd_sc_hd__sdfstp_1" "sky130_fd_sc_hd__sdfstp_1" 4 46768;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o0000000003792ca8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ea140_0 .net "CLK", 0 0, o0000000003792ca8; 0 drivers
+o0000000003792d08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037eb180_0 .net "D", 0 0, o0000000003792d08; 0 drivers
+v00000000037ea460_0 .net "Q", 0 0, L_0000000003967a50; 1 drivers
+o0000000003792d98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037eb400_0 .net "SCD", 0 0, o0000000003792d98; 0 drivers
+o0000000003792df8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ec760_0 .net "SCE", 0 0, o0000000003792df8; 0 drivers
+o0000000003792e88 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ebd60_0 .net "SET_B", 0 0, o0000000003792e88; 0 drivers
+L_00000000039144d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ebae0_0 .net8 "VGND", 0 0, L_00000000039144d0; 1 drivers, strength-aware
+L_0000000003915260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ea8c0_0 .net8 "VNB", 0 0, L_0000000003915260; 1 drivers, strength-aware
+L_0000000003914230 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037ebb80_0 .net8 "VPB", 0 0, L_0000000003914230; 1 drivers, strength-aware
+L_0000000003914460 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037ea1e0_0 .net8 "VPWR", 0 0, L_0000000003914460; 1 drivers, strength-aware
+S_000000000376e870 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 46790, 4 47127 1, S_00000000026c3f00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o0000000003792eb8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967040 .functor NOT 1, o0000000003792eb8, C4<0>, C4<0>, C4<0>;
+o0000000003792d38 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003792dc8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003792e28 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967580 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003792d38, o0000000003792dc8, o0000000003792e28;
+o0000000003792cd8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039142a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003914a10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003967200 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000003967580, o0000000003792cd8, L_0000000003967040, v00000000037eb220_0, L_00000000039142a0, L_0000000003914a10;
+L_00000000039672e0 .functor AND 1, L_0000000003813f40, L_0000000003814120, C4<1>, C4<1>;
+L_0000000003967350 .functor AND 1, L_0000000003813fe0, L_00000000039672e0, C4<1>, C4<1>;
+L_00000000039673c0 .functor AND 1, L_0000000003812f00, L_00000000039672e0, C4<1>, C4<1>;
+L_00000000039675f0 .functor AND 1, L_0000000003813220, L_00000000039672e0, C4<1>, C4<1>;
+L_00000000039679e0 .functor AND 1, L_00000000038134a0, L_0000000003814120, C4<1>, C4<1>;
+L_0000000003967a50 .functor BUF 1, L_0000000003967200, C4<0>, C4<0>, C4<0>;
+v00000000037e9880_0 .net "CLK", 0 0, o0000000003792ca8; alias, 0 drivers
+v00000000037e7c60_0 .net "CLK_delayed", 0 0, o0000000003792cd8; 0 drivers
+v00000000037e8de0_0 .net "D", 0 0, o0000000003792d08; alias, 0 drivers
+v00000000037e9420_0 .net "D_delayed", 0 0, o0000000003792d38; 0 drivers
+v00000000037e94c0_0 .net "Q", 0 0, L_0000000003967a50; alias, 1 drivers
+v00000000037e8200_0 .net "SCD", 0 0, o0000000003792d98; alias, 0 drivers
+v00000000037e7e40_0 .net "SCD_delayed", 0 0, o0000000003792dc8; 0 drivers
+v00000000037e8a20_0 .net "SCE", 0 0, o0000000003792df8; alias, 0 drivers
+v00000000037e9920_0 .net "SCE_delayed", 0 0, o0000000003792e28; 0 drivers
+v00000000037e8ac0_0 .net "SET", 0 0, L_0000000003967040; 1 drivers
+v00000000037e8b60_0 .net "SET_B", 0 0, o0000000003792e88; alias, 0 drivers
+v00000000037e9560_0 .net "SET_B_delayed", 0 0, o0000000003792eb8; 0 drivers
+v00000000037e9600_0 .net8 "VGND", 0 0, L_0000000003914a10; 1 drivers, strength-aware
+L_0000000003914f50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037e96a0_0 .net8 "VNB", 0 0, L_0000000003914f50; 1 drivers, strength-aware
+L_00000000039145b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037e8c00_0 .net8 "VPB", 0 0, L_00000000039145b0; 1 drivers, strength-aware
+v00000000037e97e0_0 .net8 "VPWR", 0 0, L_00000000039142a0; 1 drivers, strength-aware
+v00000000037e99c0_0 .net *"_s10", 0 0, L_0000000003813f40; 1 drivers
+L_0000000003972a08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037e8d40_0 .net/2u *"_s14", 0 0, L_0000000003972a08; 1 drivers
+v00000000037e9a60_0 .net *"_s16", 0 0, L_0000000003813fe0; 1 drivers
+L_0000000003972a50 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e9b00_0 .net/2u *"_s20", 0 0, L_0000000003972a50; 1 drivers
+v00000000037e8020_0 .net *"_s22", 0 0, L_0000000003812f00; 1 drivers
+v00000000037e9ba0_0 .net *"_s26", 0 0, L_0000000003813220; 1 drivers
+L_0000000003972a98 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e80c0_0 .net/2u *"_s30", 0 0, L_0000000003972a98; 1 drivers
+v00000000037e82a0_0 .net *"_s32", 0 0, L_00000000038134a0; 1 drivers
+L_0000000003972978 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e9c40_0 .net/2u *"_s4", 0 0, L_0000000003972978; 1 drivers
+L_00000000039729c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037e8480_0 .net/2u *"_s8", 0 0, L_00000000039729c0; 1 drivers
+v00000000037e8160_0 .net "awake", 0 0, L_0000000003814120; 1 drivers
+v00000000037e9ec0_0 .net "buf_Q", 0 0, L_0000000003967200; 1 drivers
+v00000000037eb900_0 .net "cond0", 0 0, L_00000000039672e0; 1 drivers
+v00000000037ead20_0 .net "cond1", 0 0, L_0000000003967350; 1 drivers
+v00000000037eb9a0_0 .net "cond2", 0 0, L_00000000039673c0; 1 drivers
+v00000000037eb0e0_0 .net "cond3", 0 0, L_00000000039675f0; 1 drivers
+v00000000037ea3c0_0 .net "cond4", 0 0, L_00000000039679e0; 1 drivers
+v00000000037ebcc0_0 .net "mux_out", 0 0, L_0000000003967580; 1 drivers
+v00000000037eb220_0 .var "notifier", 0 0;
+L_0000000003814120 .cmp/eeq 1, L_00000000039142a0, L_0000000003972978;
+L_0000000003813f40 .cmp/eeq 1, o0000000003792eb8, L_00000000039729c0;
+L_0000000003813fe0 .cmp/eeq 1, o0000000003792e28, L_0000000003972a08;
+L_0000000003812f00 .cmp/eeq 1, o0000000003792e28, L_0000000003972a50;
+L_0000000003813220 .cmp/nee 1, o0000000003792d38, o0000000003792dc8;
+L_00000000038134a0 .cmp/eeq 1, o0000000003792e88, L_0000000003972a98;
+S_00000000026c4800 .scope module, "sky130_fd_sc_hd__sdfstp_2" "sky130_fd_sc_hd__sdfstp_2" 4 47401;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o0000000003793638 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037eaa00_0 .net "CLK", 0 0, o0000000003793638; 0 drivers
+o0000000003793698 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ea780_0 .net "D", 0 0, o0000000003793698; 0 drivers
+v00000000037ec3a0_0 .net "Q", 0 0, L_000000000396a0d0; 1 drivers
+o0000000003793728 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ec4e0_0 .net "SCD", 0 0, o0000000003793728; 0 drivers
+o0000000003793788 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ec620_0 .net "SCE", 0 0, o0000000003793788; 0 drivers
+o0000000003793818 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037eafa0_0 .net "SET_B", 0 0, o0000000003793818; 0 drivers
+L_0000000003914620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037eb040_0 .net8 "VGND", 0 0, L_0000000003914620; 1 drivers, strength-aware
+L_0000000003914fc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ec440_0 .net8 "VNB", 0 0, L_0000000003914fc0; 1 drivers, strength-aware
+L_0000000003915180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037ec580_0 .net8 "VPB", 0 0, L_0000000003915180; 1 drivers, strength-aware
+L_0000000003914700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037eae60_0 .net8 "VPWR", 0 0, L_0000000003914700; 1 drivers, strength-aware
+S_000000000376daf0 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 47423, 4 47127 1, S_00000000026c4800;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o0000000003793848 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003967820 .functor NOT 1, o0000000003793848, C4<0>, C4<0>, C4<0>;
+o00000000037936c8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003793758 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037937b8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003968b60 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000037936c8, o0000000003793758, o00000000037937b8;
+o0000000003793668 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003913900 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003914690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003969420 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_0000000003968b60, o0000000003793668, L_0000000003967820, v00000000037eb860_0, L_0000000003913900, L_0000000003914690;
+L_0000000003968fc0 .functor AND 1, L_0000000003813ae0, L_0000000003812140, C4<1>, C4<1>;
+L_0000000003969c00 .functor AND 1, L_0000000003814620, L_0000000003968fc0, C4<1>, C4<1>;
+L_0000000003969030 .functor AND 1, L_0000000003812b40, L_0000000003968fc0, C4<1>, C4<1>;
+L_00000000039697a0 .functor AND 1, L_00000000038126e0, L_0000000003968fc0, C4<1>, C4<1>;
+L_00000000039698f0 .functor AND 1, L_0000000003812500, L_0000000003812140, C4<1>, C4<1>;
+L_000000000396a0d0 .functor BUF 1, L_0000000003969420, C4<0>, C4<0>, C4<0>;
+v00000000037eba40_0 .net "CLK", 0 0, o0000000003793638; alias, 0 drivers
+v00000000037ebe00_0 .net "CLK_delayed", 0 0, o0000000003793668; 0 drivers
+v00000000037eb2c0_0 .net "D", 0 0, o0000000003793698; alias, 0 drivers
+v00000000037ebc20_0 .net "D_delayed", 0 0, o00000000037936c8; 0 drivers
+v00000000037ea500_0 .net "Q", 0 0, L_000000000396a0d0; alias, 1 drivers
+v00000000037eaaa0_0 .net "SCD", 0 0, o0000000003793728; alias, 0 drivers
+v00000000037eb360_0 .net "SCD_delayed", 0 0, o0000000003793758; 0 drivers
+v00000000037ea280_0 .net "SCE", 0 0, o0000000003793788; alias, 0 drivers
+v00000000037ec300_0 .net "SCE_delayed", 0 0, o00000000037937b8; 0 drivers
+v00000000037ec1c0_0 .net "SET", 0 0, L_0000000003967820; 1 drivers
+v00000000037ea320_0 .net "SET_B", 0 0, o0000000003793818; alias, 0 drivers
+v00000000037ebea0_0 .net "SET_B_delayed", 0 0, o0000000003793848; 0 drivers
+v00000000037ea5a0_0 .net8 "VGND", 0 0, L_0000000003914690; 1 drivers, strength-aware
+L_0000000003915030 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ec800_0 .net8 "VNB", 0 0, L_0000000003915030; 1 drivers, strength-aware
+L_00000000039152d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037eab40_0 .net8 "VPB", 0 0, L_00000000039152d0; 1 drivers, strength-aware
+v00000000037eb5e0_0 .net8 "VPWR", 0 0, L_0000000003913900; 1 drivers, strength-aware
+v00000000037eabe0_0 .net *"_s10", 0 0, L_0000000003813ae0; 1 drivers
+L_0000000003972b70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037eaf00_0 .net/2u *"_s14", 0 0, L_0000000003972b70; 1 drivers
+v00000000037eb7c0_0 .net *"_s16", 0 0, L_0000000003814620; 1 drivers
+L_0000000003972bb8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ebf40_0 .net/2u *"_s20", 0 0, L_0000000003972bb8; 1 drivers
+v00000000037eb680_0 .net *"_s22", 0 0, L_0000000003812b40; 1 drivers
+v00000000037ebfe0_0 .net *"_s26", 0 0, L_00000000038126e0; 1 drivers
+L_0000000003972c00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ec260_0 .net/2u *"_s30", 0 0, L_0000000003972c00; 1 drivers
+v00000000037eb540_0 .net *"_s32", 0 0, L_0000000003812500; 1 drivers
+L_0000000003972ae0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037eac80_0 .net/2u *"_s4", 0 0, L_0000000003972ae0; 1 drivers
+L_0000000003972b28 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ec080_0 .net/2u *"_s8", 0 0, L_0000000003972b28; 1 drivers
+v00000000037eadc0_0 .net "awake", 0 0, L_0000000003812140; 1 drivers
+v00000000037ea960_0 .net "buf_Q", 0 0, L_0000000003969420; 1 drivers
+v00000000037ea640_0 .net "cond0", 0 0, L_0000000003968fc0; 1 drivers
+v00000000037ea6e0_0 .net "cond1", 0 0, L_0000000003969c00; 1 drivers
+v00000000037eb4a0_0 .net "cond2", 0 0, L_0000000003969030; 1 drivers
+v00000000037eb720_0 .net "cond3", 0 0, L_00000000039697a0; 1 drivers
+v00000000037ec120_0 .net "cond4", 0 0, L_00000000039698f0; 1 drivers
+v00000000037ea820_0 .net "mux_out", 0 0, L_0000000003968b60; 1 drivers
+v00000000037eb860_0 .var "notifier", 0 0;
+L_0000000003812140 .cmp/eeq 1, L_0000000003913900, L_0000000003972ae0;
+L_0000000003813ae0 .cmp/eeq 1, o0000000003793848, L_0000000003972b28;
+L_0000000003814620 .cmp/eeq 1, o00000000037937b8, L_0000000003972b70;
+L_0000000003812b40 .cmp/eeq 1, o00000000037937b8, L_0000000003972bb8;
+L_00000000038126e0 .cmp/nee 1, o00000000037936c8, o0000000003793758;
+L_0000000003812500 .cmp/eeq 1, o0000000003793818, L_0000000003972c00;
+S_00000000026c4080 .scope module, "sky130_fd_sc_hd__sdfstp_4" "sky130_fd_sc_hd__sdfstp_4" 4 47276;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o0000000003793fc8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ecda0_0 .net "CLK", 0 0, o0000000003793fc8; 0 drivers
+o0000000003794028 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ee2e0_0 .net "D", 0 0, o0000000003794028; 0 drivers
+v00000000037ee9c0_0 .net "Q", 0 0, L_00000000039690a0; 1 drivers
+o00000000037940b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ee1a0_0 .net "SCD", 0 0, o00000000037940b8; 0 drivers
+o0000000003794118 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ed8e0_0 .net "SCE", 0 0, o0000000003794118; 0 drivers
+o00000000037941a8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ed7a0_0 .net "SET_B", 0 0, o00000000037941a8; 0 drivers
+L_0000000003913970 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ee6a0_0 .net8 "VGND", 0 0, L_0000000003913970; 1 drivers, strength-aware
+L_00000000039139e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037edc00_0 .net8 "VNB", 0 0, L_00000000039139e0; 1 drivers, strength-aware
+L_0000000003913a50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037eec40_0 .net8 "VPB", 0 0, L_0000000003913a50; 1 drivers, strength-aware
+L_0000000003915e30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037eef60_0 .net8 "VPWR", 0 0, L_0000000003915e30; 1 drivers, strength-aware
+S_000000000376a4f0 .scope module, "base" "sky130_fd_sc_hd__sdfstp" 4 47298, 4 47127 1, S_00000000026c4080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+ .port_info 5 /INPUT 1 "SET_B"
+o00000000037941d8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396a290 .functor NOT 1, o00000000037941d8, C4<0>, C4<0>, C4<0>;
+o0000000003794058 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037940e8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003794148 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396a140 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003794058, o00000000037940e8, o0000000003794148;
+o0000000003793ff8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003915ea0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003916920 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_00000000039689a0 .udp UDP_sky130_fd_sc_hd__udp_dff$PS_pp$PG$N, L_000000000396a140, o0000000003793ff8, L_000000000396a290, v00000000037ee7e0_0, L_0000000003915ea0, L_0000000003916920;
+L_0000000003968c40 .functor AND 1, L_0000000003812be0, L_00000000038141c0, C4<1>, C4<1>;
+L_0000000003968cb0 .functor AND 1, L_0000000003812960, L_0000000003968c40, C4<1>, C4<1>;
+L_000000000396a3e0 .functor AND 1, L_0000000003812a00, L_0000000003968c40, C4<1>, C4<1>;
+L_0000000003969ab0 .functor AND 1, L_0000000003813a40, L_0000000003968c40, C4<1>, C4<1>;
+L_0000000003968d90 .functor AND 1, L_0000000003812640, L_00000000038141c0, C4<1>, C4<1>;
+L_00000000039690a0 .functor BUF 1, L_00000000039689a0, C4<0>, C4<0>, C4<0>;
+v00000000037ec6c0_0 .net "CLK", 0 0, o0000000003793fc8; alias, 0 drivers
+v00000000037ec8a0_0 .net "CLK_delayed", 0 0, o0000000003793ff8; 0 drivers
+v00000000037ee380_0 .net "D", 0 0, o0000000003794028; alias, 0 drivers
+v00000000037eeb00_0 .net "D_delayed", 0 0, o0000000003794058; 0 drivers
+v00000000037ed340_0 .net "Q", 0 0, L_00000000039690a0; alias, 1 drivers
+v00000000037ed3e0_0 .net "SCD", 0 0, o00000000037940b8; alias, 0 drivers
+v00000000037ed480_0 .net "SCD_delayed", 0 0, o00000000037940e8; 0 drivers
+v00000000037ee100_0 .net "SCE", 0 0, o0000000003794118; alias, 0 drivers
+v00000000037ee420_0 .net "SCE_delayed", 0 0, o0000000003794148; 0 drivers
+v00000000037ed0c0_0 .net "SET", 0 0, L_000000000396a290; 1 drivers
+v00000000037ecbc0_0 .net "SET_B", 0 0, o00000000037941a8; alias, 0 drivers
+v00000000037ee880_0 .net "SET_B_delayed", 0 0, o00000000037941d8; 0 drivers
+v00000000037eeba0_0 .net8 "VGND", 0 0, L_0000000003916920; 1 drivers, strength-aware
+L_00000000039165a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ed200_0 .net8 "VNB", 0 0, L_00000000039165a0; 1 drivers, strength-aware
+L_0000000003915500 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037edde0_0 .net8 "VPB", 0 0, L_0000000003915500; 1 drivers, strength-aware
+v00000000037eca80_0 .net8 "VPWR", 0 0, L_0000000003915ea0; 1 drivers, strength-aware
+v00000000037ee240_0 .net *"_s10", 0 0, L_0000000003812be0; 1 drivers
+L_0000000003972cd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037ed520_0 .net/2u *"_s14", 0 0, L_0000000003972cd8; 1 drivers
+v00000000037ecc60_0 .net *"_s16", 0 0, L_0000000003812960; 1 drivers
+L_0000000003972d20 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ed5c0_0 .net/2u *"_s20", 0 0, L_0000000003972d20; 1 drivers
+v00000000037ed020_0 .net *"_s22", 0 0, L_0000000003812a00; 1 drivers
+v00000000037eda20_0 .net *"_s26", 0 0, L_0000000003813a40; 1 drivers
+L_0000000003972d68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037edac0_0 .net/2u *"_s30", 0 0, L_0000000003972d68; 1 drivers
+v00000000037ee4c0_0 .net *"_s32", 0 0, L_0000000003812640; 1 drivers
+L_0000000003972c48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ee600_0 .net/2u *"_s4", 0 0, L_0000000003972c48; 1 drivers
+L_0000000003972c90 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037edb60_0 .net/2u *"_s8", 0 0, L_0000000003972c90; 1 drivers
+v00000000037edca0_0 .net "awake", 0 0, L_00000000038141c0; 1 drivers
+v00000000037ecee0_0 .net "buf_Q", 0 0, L_00000000039689a0; 1 drivers
+v00000000037ed700_0 .net "cond0", 0 0, L_0000000003968c40; 1 drivers
+v00000000037ece40_0 .net "cond1", 0 0, L_0000000003968cb0; 1 drivers
+v00000000037ee920_0 .net "cond2", 0 0, L_000000000396a3e0; 1 drivers
+v00000000037ee560_0 .net "cond3", 0 0, L_0000000003969ab0; 1 drivers
+v00000000037ecb20_0 .net "cond4", 0 0, L_0000000003968d90; 1 drivers
+v00000000037ed840_0 .net "mux_out", 0 0, L_000000000396a140; 1 drivers
+v00000000037ee7e0_0 .var "notifier", 0 0;
+L_00000000038141c0 .cmp/eeq 1, L_0000000003915ea0, L_0000000003972c48;
+L_0000000003812be0 .cmp/eeq 1, o00000000037941d8, L_0000000003972c90;
+L_0000000003812960 .cmp/eeq 1, o0000000003794148, L_0000000003972cd8;
+L_0000000003812a00 .cmp/eeq 1, o0000000003794148, L_0000000003972d20;
+L_0000000003813a40 .cmp/nee 1, o0000000003794058, o00000000037940e8;
+L_0000000003812640 .cmp/eeq 1, o00000000037941a8, L_0000000003972d68;
+S_00000000026c5a00 .scope module, "sky130_fd_sc_hd__sdfxbp_1" "sky130_fd_sc_hd__sdfxbp_1" 4 65736;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o0000000003794958 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f0860_0 .net "CLK", 0 0, o0000000003794958; 0 drivers
+o00000000037949b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f0900_0 .net "D", 0 0, o00000000037949b8; 0 drivers
+v00000000037f0e00_0 .net "Q", 0 0, L_00000000039699d0; 1 drivers
+v00000000037f11c0_0 .net "Q_N", 0 0, L_0000000003969650; 1 drivers
+o0000000003794a78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037efaa0_0 .net "SCD", 0 0, o0000000003794a78; 0 drivers
+o0000000003794ad8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037efb40_0 .net "SCE", 0 0, o0000000003794ad8; 0 drivers
+L_0000000003916610 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ef820_0 .net8 "VGND", 0 0, L_0000000003916610; 1 drivers, strength-aware
+L_00000000039157a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ef6e0_0 .net8 "VNB", 0 0, L_00000000039157a0; 1 drivers, strength-aware
+L_0000000003916290 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037efbe0_0 .net8 "VPB", 0 0, L_0000000003916290; 1 drivers, strength-aware
+L_0000000003915b90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f0a40_0 .net8 "VPWR", 0 0, L_0000000003915b90; 1 drivers, strength-aware
+S_000000000376d7f0 .scope module, "base" "sky130_fd_sc_hd__sdfxbp" 4 65758, 4 66082 1, S_00000000026c5a00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o00000000037949e8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003794aa8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003794b08 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039695e0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000037949e8, o0000000003794aa8, o0000000003794b08;
+o0000000003794988 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003915f10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003916bc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003968d20 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_00000000039695e0, o0000000003794988, v00000000037f02c0_0, L_0000000003915f10, L_0000000003916bc0;
+L_000000000396a060 .functor AND 1, L_0000000003812aa0, L_00000000038143a0, C4<1>, C4<1>;
+L_0000000003969d50 .functor AND 1, L_0000000003812e60, L_00000000038143a0, C4<1>, C4<1>;
+L_0000000003969500 .functor AND 1, L_00000000038137c0, L_00000000038143a0, C4<1>, C4<1>;
+L_00000000039699d0 .functor BUF 1, L_0000000003968d20, C4<0>, C4<0>, C4<0>;
+L_0000000003969650 .functor NOT 1, L_0000000003968d20, C4<0>, C4<0>, C4<0>;
+v00000000037ee740_0 .net "CLK", 0 0, o0000000003794958; alias, 0 drivers
+v00000000037ecd00_0 .net "CLK_delayed", 0 0, o0000000003794988; 0 drivers
+v00000000037eea60_0 .net "D", 0 0, o00000000037949b8; alias, 0 drivers
+v00000000037eece0_0 .net "D_delayed", 0 0, o00000000037949e8; 0 drivers
+v00000000037eed80_0 .net "Q", 0 0, L_00000000039699d0; alias, 1 drivers
+v00000000037ed660_0 .net "Q_N", 0 0, L_0000000003969650; alias, 1 drivers
+v00000000037ecf80_0 .net "SCD", 0 0, o0000000003794a78; alias, 0 drivers
+v00000000037ed160_0 .net "SCD_delayed", 0 0, o0000000003794aa8; 0 drivers
+v00000000037eee20_0 .net "SCE", 0 0, o0000000003794ad8; alias, 0 drivers
+v00000000037eeec0_0 .net "SCE_delayed", 0 0, o0000000003794b08; 0 drivers
+v00000000037ef000_0 .net8 "VGND", 0 0, L_0000000003916bc0; 1 drivers, strength-aware
+L_0000000003915ab0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ef0a0_0 .net8 "VNB", 0 0, L_0000000003915ab0; 1 drivers, strength-aware
+L_0000000003916370 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037ed2a0_0 .net8 "VPB", 0 0, L_0000000003916370; 1 drivers, strength-aware
+v00000000037ec940_0 .net8 "VPWR", 0 0, L_0000000003915f10; 1 drivers, strength-aware
+v00000000037edd40_0 .net *"_s10", 0 0, L_0000000003812aa0; 1 drivers
+L_0000000003972e40 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ed980_0 .net/2u *"_s14", 0 0, L_0000000003972e40; 1 drivers
+v00000000037ede80_0 .net *"_s16", 0 0, L_0000000003812e60; 1 drivers
+v00000000037edf20_0 .net *"_s20", 0 0, L_00000000038137c0; 1 drivers
+L_0000000003972db0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037edfc0_0 .net/2u *"_s4", 0 0, L_0000000003972db0; 1 drivers
+L_0000000003972df8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037ee060_0 .net/2u *"_s8", 0 0, L_0000000003972df8; 1 drivers
+v00000000037ec9e0_0 .net "awake", 0 0, L_00000000038143a0; 1 drivers
+v00000000037f07c0_0 .net "buf_Q", 0 0, L_0000000003968d20; 1 drivers
+v00000000037f09a0_0 .net "cond1", 0 0, L_000000000396a060; 1 drivers
+v00000000037f1800_0 .net "cond2", 0 0, L_0000000003969d50; 1 drivers
+v00000000037effa0_0 .net "cond3", 0 0, L_0000000003969500; 1 drivers
+v00000000037ef960_0 .net "mux_out", 0 0, L_00000000039695e0; 1 drivers
+v00000000037f02c0_0 .var "notifier", 0 0;
+L_00000000038143a0 .cmp/eeq 1, L_0000000003915f10, L_0000000003972db0;
+L_0000000003812aa0 .cmp/eeq 1, o0000000003794b08, L_0000000003972df8;
+L_0000000003812e60 .cmp/eeq 1, o0000000003794b08, L_0000000003972e40;
+L_00000000038137c0 .cmp/nee 1, o00000000037949e8, o0000000003794aa8;
+S_00000000026c4980 .scope module, "sky130_fd_sc_hd__sdfxbp_2" "sky130_fd_sc_hd__sdfxbp_2" 4 66224;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o0000000003795168 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f0cc0_0 .net "CLK", 0 0, o0000000003795168; 0 drivers
+o00000000037951c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f0d60_0 .net "D", 0 0, o00000000037951c8; 0 drivers
+v00000000037efe60_0 .net "Q", 0 0, L_0000000003969dc0; 1 drivers
+v00000000037ef500_0 .net "Q_N", 0 0, L_000000000396a1b0; 1 drivers
+o0000000003795288 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ef5a0_0 .net "SCD", 0 0, o0000000003795288; 0 drivers
+o00000000037952e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f04a0_0 .net "SCE", 0 0, o00000000037952e8; 0 drivers
+L_0000000003917090 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f0fe0_0 .net8 "VGND", 0 0, L_0000000003917090; 1 drivers, strength-aware
+L_0000000003915b20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f0400_0 .net8 "VNB", 0 0, L_0000000003915b20; 1 drivers, strength-aware
+L_0000000003915f80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f1080_0 .net8 "VPB", 0 0, L_0000000003915f80; 1 drivers, strength-aware
+L_0000000003916760 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f1120_0 .net8 "VPWR", 0 0, L_0000000003916760; 1 drivers, strength-aware
+S_000000000376e0f0 .scope module, "base" "sky130_fd_sc_hd__sdfxbp" 4 66246, 4 66082 1, S_00000000026c4980;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o00000000037951f8 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037952b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003795318 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396a300 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o00000000037951f8, o00000000037952b8, o0000000003795318;
+o0000000003795198 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003915ff0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003916df0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003969ff0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396a300, o0000000003795198, v00000000037f0720_0, L_0000000003915ff0, L_0000000003916df0;
+L_0000000003969730 .functor AND 1, L_0000000003813860, L_00000000038128c0, C4<1>, C4<1>;
+L_0000000003969960 .functor AND 1, L_0000000003812820, L_00000000038128c0, C4<1>, C4<1>;
+L_0000000003969f80 .functor AND 1, L_0000000003814300, L_00000000038128c0, C4<1>, C4<1>;
+L_0000000003969dc0 .functor BUF 1, L_0000000003969ff0, C4<0>, C4<0>, C4<0>;
+L_000000000396a1b0 .functor NOT 1, L_0000000003969ff0, C4<0>, C4<0>, C4<0>;
+v00000000037f0ae0_0 .net "CLK", 0 0, o0000000003795168; alias, 0 drivers
+v00000000037ef460_0 .net "CLK_delayed", 0 0, o0000000003795198; 0 drivers
+v00000000037efa00_0 .net "D", 0 0, o00000000037951c8; alias, 0 drivers
+v00000000037f05e0_0 .net "D_delayed", 0 0, o00000000037951f8; 0 drivers
+v00000000037efc80_0 .net "Q", 0 0, L_0000000003969dc0; alias, 1 drivers
+v00000000037eff00_0 .net "Q_N", 0 0, L_000000000396a1b0; alias, 1 drivers
+v00000000037ef780_0 .net "SCD", 0 0, o0000000003795288; alias, 0 drivers
+v00000000037f18a0_0 .net "SCD_delayed", 0 0, o00000000037952b8; 0 drivers
+v00000000037f0b80_0 .net "SCE", 0 0, o00000000037952e8; alias, 0 drivers
+v00000000037f0ea0_0 .net "SCE_delayed", 0 0, o0000000003795318; 0 drivers
+v00000000037f14e0_0 .net8 "VGND", 0 0, L_0000000003916df0; 1 drivers, strength-aware
+L_0000000003916ca0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f0540_0 .net8 "VNB", 0 0, L_0000000003916ca0; 1 drivers, strength-aware
+L_00000000039168b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f0680_0 .net8 "VPB", 0 0, L_00000000039168b0; 1 drivers, strength-aware
+v00000000037efd20_0 .net8 "VPWR", 0 0, L_0000000003915ff0; 1 drivers, strength-aware
+v00000000037ef8c0_0 .net *"_s10", 0 0, L_0000000003813860; 1 drivers
+L_0000000003972f18 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037efdc0_0 .net/2u *"_s14", 0 0, L_0000000003972f18; 1 drivers
+v00000000037ef3c0_0 .net *"_s16", 0 0, L_0000000003812820; 1 drivers
+v00000000037ef140_0 .net *"_s20", 0 0, L_0000000003814300; 1 drivers
+L_0000000003972e88 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ef320_0 .net/2u *"_s4", 0 0, L_0000000003972e88; 1 drivers
+L_0000000003972ed0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f0040_0 .net/2u *"_s8", 0 0, L_0000000003972ed0; 1 drivers
+v00000000037f0f40_0 .net "awake", 0 0, L_00000000038128c0; 1 drivers
+v00000000037f0180_0 .net "buf_Q", 0 0, L_0000000003969ff0; 1 drivers
+v00000000037f00e0_0 .net "cond1", 0 0, L_0000000003969730; 1 drivers
+v00000000037f0220_0 .net "cond2", 0 0, L_0000000003969960; 1 drivers
+v00000000037f0c20_0 .net "cond3", 0 0, L_0000000003969f80; 1 drivers
+v00000000037f0360_0 .net "mux_out", 0 0, L_000000000396a300; 1 drivers
+v00000000037f0720_0 .var "notifier", 0 0;
+L_00000000038128c0 .cmp/eeq 1, L_0000000003915ff0, L_0000000003972e88;
+L_0000000003813860 .cmp/eeq 1, o0000000003795318, L_0000000003972ed0;
+L_0000000003812820 .cmp/eeq 1, o0000000003795318, L_0000000003972f18;
+L_0000000003814300 .cmp/nee 1, o00000000037951f8, o00000000037952b8;
+S_00000000026c3c00 .scope module, "sky130_fd_sc_hd__sdfxtp_1" "sky130_fd_sc_hd__sdfxtp_1" 4 20753;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o0000000003795978 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f22a0_0 .net "CLK", 0 0, o0000000003795978; 0 drivers
+o00000000037959d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f28e0_0 .net "D", 0 0, o00000000037959d8; 0 drivers
+v00000000037f2980_0 .net "Q", 0 0, L_0000000003969e30; 1 drivers
+o0000000003795a68 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f2340_0 .net "SCD", 0 0, o0000000003795a68; 0 drivers
+o0000000003795ac8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f1bc0_0 .net "SCE", 0 0, o0000000003795ac8; 0 drivers
+L_0000000003916ed0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f2b60_0 .net8 "VGND", 0 0, L_0000000003916ed0; 1 drivers, strength-aware
+L_0000000003916c30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f36a0_0 .net8 "VNB", 0 0, L_0000000003916c30; 1 drivers, strength-aware
+L_0000000003916140 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f31a0_0 .net8 "VPB", 0 0, L_0000000003916140; 1 drivers, strength-aware
+L_0000000003916060 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f2ac0_0 .net8 "VPWR", 0 0, L_0000000003916060; 1 drivers, strength-aware
+S_000000000376a370 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20773, 4 20381 1, S_00000000026c3c00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o0000000003795a08 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003795a98 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003795af8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969570 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003795a08, o0000000003795a98, o0000000003795af8;
+o00000000037959a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039163e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003915c00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396a4c0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000003969570, o00000000037959a8, v00000000037f1da0_0, L_00000000039163e0, L_0000000003915c00;
+L_000000000396a220 .functor AND 1, L_00000000038139a0, L_0000000003814260, C4<1>, C4<1>;
+L_0000000003969c70 .functor AND 1, L_0000000003813540, L_0000000003814260, C4<1>, C4<1>;
+L_00000000039696c0 .functor AND 1, L_0000000003812d20, L_0000000003814260, C4<1>, C4<1>;
+L_0000000003969e30 .functor BUF 1, L_000000000396a4c0, C4<0>, C4<0>, C4<0>;
+v00000000037f1260_0 .net "CLK", 0 0, o0000000003795978; alias, 0 drivers
+v00000000037f1760_0 .net "CLK_delayed", 0 0, o00000000037959a8; 0 drivers
+v00000000037f1300_0 .net "D", 0 0, o00000000037959d8; alias, 0 drivers
+v00000000037f13a0_0 .net "D_delayed", 0 0, o0000000003795a08; 0 drivers
+v00000000037f1440_0 .net "Q", 0 0, L_0000000003969e30; alias, 1 drivers
+v00000000037f1580_0 .net "SCD", 0 0, o0000000003795a68; alias, 0 drivers
+v00000000037f1620_0 .net "SCD_delayed", 0 0, o0000000003795a98; 0 drivers
+v00000000037f16c0_0 .net "SCE", 0 0, o0000000003795ac8; alias, 0 drivers
+v00000000037ef1e0_0 .net "SCE_delayed", 0 0, o0000000003795af8; 0 drivers
+v00000000037ef280_0 .net8 "VGND", 0 0, L_0000000003915c00; 1 drivers, strength-aware
+L_0000000003915ce0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ef640_0 .net8 "VNB", 0 0, L_0000000003915ce0; 1 drivers, strength-aware
+L_0000000003916d10 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f3420_0 .net8 "VPB", 0 0, L_0000000003916d10; 1 drivers, strength-aware
+v00000000037f2a20_0 .net8 "VPWR", 0 0, L_00000000039163e0; 1 drivers, strength-aware
+v00000000037f3560_0 .net *"_s10", 0 0, L_00000000038139a0; 1 drivers
+L_0000000003972ff0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f2f20_0 .net/2u *"_s14", 0 0, L_0000000003972ff0; 1 drivers
+v00000000037f2700_0 .net *"_s16", 0 0, L_0000000003813540; 1 drivers
+v00000000037f1e40_0 .net *"_s20", 0 0, L_0000000003812d20; 1 drivers
+L_0000000003972f60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f2660_0 .net/2u *"_s4", 0 0, L_0000000003972f60; 1 drivers
+L_0000000003972fa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f3600_0 .net/2u *"_s8", 0 0, L_0000000003972fa8; 1 drivers
+v00000000037f32e0_0 .net "awake", 0 0, L_0000000003814260; 1 drivers
+v00000000037f3f60_0 .net "buf_Q", 0 0, L_000000000396a4c0; 1 drivers
+v00000000037f2840_0 .net "cond1", 0 0, L_000000000396a220; 1 drivers
+v00000000037f27a0_0 .net "cond2", 0 0, L_0000000003969c70; 1 drivers
+v00000000037f3100_0 .net "cond3", 0 0, L_00000000039696c0; 1 drivers
+v00000000037f2480_0 .net "mux_out", 0 0, L_0000000003969570; 1 drivers
+v00000000037f1da0_0 .var "notifier", 0 0;
+L_0000000003814260 .cmp/eeq 1, L_00000000039163e0, L_0000000003972f60;
+L_00000000038139a0 .cmp/eeq 1, o0000000003795af8, L_0000000003972fa8;
+L_0000000003813540 .cmp/eeq 1, o0000000003795af8, L_0000000003972ff0;
+L_0000000003812d20 .cmp/nee 1, o0000000003795a08, o0000000003795a98;
+S_00000000026c4b00 .scope module, "sky130_fd_sc_hd__sdfxtp_2" "sky130_fd_sc_hd__sdfxtp_2" 4 20517;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o00000000037960f8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f2e80_0 .net "CLK", 0 0, o00000000037960f8; 0 drivers
+o0000000003796158 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f3b00_0 .net "D", 0 0, o0000000003796158; 0 drivers
+v00000000037f3ba0_0 .net "Q", 0 0, L_000000000396a450; 1 drivers
+o00000000037961e8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f3e20_0 .net "SCD", 0 0, o00000000037961e8; 0 drivers
+o0000000003796248 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f1d00_0 .net "SCE", 0 0, o0000000003796248; 0 drivers
+L_00000000039167d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f3ec0_0 .net8 "VGND", 0 0, L_00000000039167d0; 1 drivers, strength-aware
+L_0000000003916450 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f1940_0 .net8 "VNB", 0 0, L_0000000003916450; 1 drivers, strength-aware
+L_0000000003915c70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f19e0_0 .net8 "VPB", 0 0, L_0000000003915c70; 1 drivers, strength-aware
+L_0000000003916680 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f1a80_0 .net8 "VPWR", 0 0, L_0000000003916680; 1 drivers, strength-aware
+S_000000000376e270 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20537, 4 20381 1, S_00000000026c4b00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o0000000003796188 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003796218 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003796278 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969f10 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003796188, o0000000003796218, o0000000003796278;
+o0000000003796128 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003916fb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003916a00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003968a10 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000003969f10, o0000000003796128, v00000000037f3a60_0, L_0000000003916fb0, L_0000000003916a00;
+L_0000000003968af0 .functor AND 1, L_00000000038130e0, L_0000000003814440, C4<1>, C4<1>;
+L_0000000003969ea0 .functor AND 1, L_0000000003812780, L_0000000003814440, C4<1>, C4<1>;
+L_000000000396a370 .functor AND 1, L_0000000003814580, L_0000000003814440, C4<1>, C4<1>;
+L_000000000396a450 .functor BUF 1, L_0000000003968a10, C4<0>, C4<0>, C4<0>;
+v00000000037f2520_0 .net "CLK", 0 0, o00000000037960f8; alias, 0 drivers
+v00000000037f20c0_0 .net "CLK_delayed", 0 0, o0000000003796128; 0 drivers
+v00000000037f37e0_0 .net "D", 0 0, o0000000003796158; alias, 0 drivers
+v00000000037f23e0_0 .net "D_delayed", 0 0, o0000000003796188; 0 drivers
+v00000000037f1ee0_0 .net "Q", 0 0, L_000000000396a450; alias, 1 drivers
+v00000000037f25c0_0 .net "SCD", 0 0, o00000000037961e8; alias, 0 drivers
+v00000000037f2c00_0 .net "SCD_delayed", 0 0, o0000000003796218; 0 drivers
+v00000000037f3920_0 .net "SCE", 0 0, o0000000003796248; alias, 0 drivers
+v00000000037f3c40_0 .net "SCE_delayed", 0 0, o0000000003796278; 0 drivers
+v00000000037f2fc0_0 .net8 "VGND", 0 0, L_0000000003916a00; 1 drivers, strength-aware
+L_0000000003915570 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f3740_0 .net8 "VNB", 0 0, L_0000000003915570; 1 drivers, strength-aware
+L_00000000039156c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f3ce0_0 .net8 "VPB", 0 0, L_00000000039156c0; 1 drivers, strength-aware
+v00000000037f3d80_0 .net8 "VPWR", 0 0, L_0000000003916fb0; 1 drivers, strength-aware
+v00000000037f3380_0 .net *"_s10", 0 0, L_00000000038130e0; 1 drivers
+L_00000000039730c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f39c0_0 .net/2u *"_s14", 0 0, L_00000000039730c8; 1 drivers
+v00000000037f3240_0 .net *"_s16", 0 0, L_0000000003812780; 1 drivers
+v00000000037f4000_0 .net *"_s20", 0 0, L_0000000003814580; 1 drivers
+L_0000000003973038 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f40a0_0 .net/2u *"_s4", 0 0, L_0000000003973038; 1 drivers
+L_0000000003973080 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f2ca0_0 .net/2u *"_s8", 0 0, L_0000000003973080; 1 drivers
+v00000000037f2d40_0 .net "awake", 0 0, L_0000000003814440; 1 drivers
+v00000000037f1c60_0 .net "buf_Q", 0 0, L_0000000003968a10; 1 drivers
+v00000000037f3880_0 .net "cond1", 0 0, L_0000000003968af0; 1 drivers
+v00000000037f3060_0 .net "cond2", 0 0, L_0000000003969ea0; 1 drivers
+v00000000037f34c0_0 .net "cond3", 0 0, L_000000000396a370; 1 drivers
+v00000000037f2de0_0 .net "mux_out", 0 0, L_0000000003969f10; 1 drivers
+v00000000037f3a60_0 .var "notifier", 0 0;
+L_0000000003814440 .cmp/eeq 1, L_0000000003916fb0, L_0000000003973038;
+L_00000000038130e0 .cmp/eeq 1, o0000000003796278, L_0000000003973080;
+L_0000000003812780 .cmp/eeq 1, o0000000003796278, L_00000000039730c8;
+L_0000000003814580 .cmp/nee 1, o0000000003796188, o0000000003796218;
+S_00000000026c4200 .scope module, "sky130_fd_sc_hd__sdfxtp_4" "sky130_fd_sc_hd__sdfxtp_4" 4 20635;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o0000000003796878 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f5a40_0 .net "CLK", 0 0, o0000000003796878; 0 drivers
+o00000000037968d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f61c0_0 .net "D", 0 0, o00000000037968d8; 0 drivers
+v00000000037f5d60_0 .net "Q", 0 0, L_0000000003968e00; 1 drivers
+o0000000003796968 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f46e0_0 .net "SCD", 0 0, o0000000003796968; 0 drivers
+o00000000037969c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f4f00_0 .net "SCE", 0 0, o00000000037969c8; 0 drivers
+L_0000000003916840 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f6260_0 .net8 "VGND", 0 0, L_0000000003916840; 1 drivers, strength-aware
+L_0000000003916a70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f4e60_0 .net8 "VNB", 0 0, L_0000000003916a70; 1 drivers, strength-aware
+L_0000000003915880 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f6760_0 .net8 "VPB", 0 0, L_0000000003915880; 1 drivers, strength-aware
+L_0000000003916300 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f4960_0 .net8 "VPWR", 0 0, L_0000000003916300; 1 drivers, strength-aware
+S_000000000376fef0 .scope module, "base" "sky130_fd_sc_hd__sdfxtp" 4 20655, 4 20381 1, S_00000000026c4200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "SCD"
+ .port_info 4 /INPUT 1 "SCE"
+o0000000003796908 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003796998 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037969f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969a40 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, o0000000003796908, o0000000003796998, o00000000037969f8;
+o00000000037968a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003916990 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003915730 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003968a80 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_0000000003969a40, o00000000037968a8, v00000000037f4820_0, L_0000000003916990, L_0000000003915730;
+L_0000000003968bd0 .functor AND 1, L_00000000038135e0, L_0000000003814760, C4<1>, C4<1>;
+L_0000000003969110 .functor AND 1, L_0000000003813680, L_0000000003814760, C4<1>, C4<1>;
+L_0000000003969180 .functor AND 1, L_0000000003814800, L_0000000003814760, C4<1>, C4<1>;
+L_0000000003968e00 .functor BUF 1, L_0000000003968a80, C4<0>, C4<0>, C4<0>;
+v00000000037f1b20_0 .net "CLK", 0 0, o0000000003796878; alias, 0 drivers
+v00000000037f1f80_0 .net "CLK_delayed", 0 0, o00000000037968a8; 0 drivers
+v00000000037f2020_0 .net "D", 0 0, o00000000037968d8; alias, 0 drivers
+v00000000037f2160_0 .net "D_delayed", 0 0, o0000000003796908; 0 drivers
+v00000000037f2200_0 .net "Q", 0 0, L_0000000003968e00; alias, 1 drivers
+v00000000037f4500_0 .net "SCD", 0 0, o0000000003796968; alias, 0 drivers
+v00000000037f45a0_0 .net "SCD_delayed", 0 0, o0000000003796998; 0 drivers
+v00000000037f41e0_0 .net "SCE", 0 0, o00000000037969c8; alias, 0 drivers
+v00000000037f6300_0 .net "SCE_delayed", 0 0, o00000000037969f8; 0 drivers
+v00000000037f4d20_0 .net8 "VGND", 0 0, L_0000000003915730; 1 drivers, strength-aware
+L_00000000039160d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f4b40_0 .net8 "VNB", 0 0, L_00000000039160d0; 1 drivers, strength-aware
+L_0000000003915810 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f4c80_0 .net8 "VPB", 0 0, L_0000000003915810; 1 drivers, strength-aware
+v00000000037f5900_0 .net8 "VPWR", 0 0, L_0000000003916990; 1 drivers, strength-aware
+v00000000037f5c20_0 .net *"_s10", 0 0, L_00000000038135e0; 1 drivers
+L_00000000039731a0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f5f40_0 .net/2u *"_s14", 0 0, L_00000000039731a0; 1 drivers
+v00000000037f43c0_0 .net *"_s16", 0 0, L_0000000003813680; 1 drivers
+v00000000037f6080_0 .net *"_s20", 0 0, L_0000000003814800; 1 drivers
+L_0000000003973110 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f4460_0 .net/2u *"_s4", 0 0, L_0000000003973110; 1 drivers
+L_0000000003973158 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f55e0_0 .net/2u *"_s8", 0 0, L_0000000003973158; 1 drivers
+v00000000037f5720_0 .net "awake", 0 0, L_0000000003814760; 1 drivers
+v00000000037f5cc0_0 .net "buf_Q", 0 0, L_0000000003968a80; 1 drivers
+v00000000037f4dc0_0 .net "cond1", 0 0, L_0000000003968bd0; 1 drivers
+v00000000037f5fe0_0 .net "cond2", 0 0, L_0000000003969110; 1 drivers
+v00000000037f6120_0 .net "cond3", 0 0, L_0000000003969180; 1 drivers
+v00000000037f4640_0 .net "mux_out", 0 0, L_0000000003969a40; 1 drivers
+v00000000037f4820_0 .var "notifier", 0 0;
+L_0000000003814760 .cmp/eeq 1, L_0000000003916990, L_0000000003973110;
+L_00000000038135e0 .cmp/eeq 1, o00000000037969f8, L_0000000003973158;
+L_0000000003813680 .cmp/eeq 1, o00000000037969f8, L_00000000039731a0;
+L_0000000003814800 .cmp/nee 1, o0000000003796908, o0000000003796998;
+S_00000000026c4e00 .scope module, "sky130_fd_sc_hd__sdlclkp_1" "sky130_fd_sc_hd__sdlclkp_1" 4 14230;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+o0000000003796ff8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f6580_0 .net "CLK", 0 0, o0000000003796ff8; 0 drivers
+o0000000003797058 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f57c0_0 .net "GATE", 0 0, o0000000003797058; 0 drivers
+v00000000037f52c0_0 .net "GCLK", 0 0, L_00000000039692d0; 1 drivers
+o0000000003797118 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f6620_0 .net "SCE", 0 0, o0000000003797118; 0 drivers
+L_0000000003916b50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f66c0_0 .net8 "VGND", 0 0, L_0000000003916b50; 1 drivers, strength-aware
+L_0000000003917020 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f5360_0 .net8 "VNB", 0 0, L_0000000003917020; 1 drivers, strength-aware
+L_00000000039166f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f5400_0 .net8 "VPB", 0 0, L_00000000039166f0; 1 drivers, strength-aware
+L_00000000039161b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f54a0_0 .net8 "VPWR", 0 0, L_00000000039161b0; 1 drivers, strength-aware
+S_000000000376e3f0 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14248, 4 14676 1, S_00000000026c4e00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+L_00000000039691f0 .functor NOT 1, L_0000000003969260, C4<0>, C4<0>, C4<0>;
+o0000000003797028 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003968ee0 .functor NOT 1, o0000000003797028, C4<0>, C4<0>, C4<0>;
+o00000000037970b8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003797178 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969b20 .functor NOR 1, o00000000037970b8, o0000000003797178, C4<0>, C4<0>;
+L_00000000039159d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039158f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003969260 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_0000000003969b20, L_0000000003968ee0, v00000000037f5180_0, L_00000000039159d0, L_00000000039158f0;
+L_00000000039692d0 .functor AND 1, L_00000000039691f0, o0000000003797028, C4<1>, C4<1>;
+L_0000000003969340 .functor AND 1, L_00000000038148a0, L_00000000038121e0, C4<1>, C4<1>;
+L_0000000003969b90 .functor AND 1, L_00000000038148a0, L_0000000003813180, C4<1>, C4<1>;
+v00000000037f4780_0 .net "CLK", 0 0, o0000000003796ff8; alias, 0 drivers
+v00000000037f5ae0_0 .net "CLK_delayed", 0 0, o0000000003797028; 0 drivers
+v00000000037f63a0_0 .net "GATE", 0 0, o0000000003797058; alias, 0 drivers
+v00000000037f59a0_0 .net "GATE_awake", 0 0, L_0000000003969b90; 1 drivers
+v00000000037f50e0_0 .net "GATE_delayed", 0 0, o00000000037970b8; 0 drivers
+v00000000037f4fa0_0 .net "GCLK", 0 0, L_00000000039692d0; alias, 1 drivers
+v00000000037f5e00_0 .net "SCE", 0 0, o0000000003797118; alias, 0 drivers
+v00000000037f5220_0 .net "SCE_awake", 0 0, L_0000000003969340; 1 drivers
+v00000000037f6440_0 .net "SCE_delayed", 0 0, o0000000003797178; 0 drivers
+v00000000037f6800_0 .net "SCE_gate_delayed", 0 0, L_0000000003969b20; 1 drivers
+v00000000037f4280_0 .net8 "VGND", 0 0, L_00000000039158f0; 1 drivers, strength-aware
+L_0000000003915960 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f4140_0 .net8 "VNB", 0 0, L_0000000003915960; 1 drivers, strength-aware
+L_0000000003916ae0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f5b80_0 .net8 "VPB", 0 0, L_0000000003916ae0; 1 drivers, strength-aware
+v00000000037f4320_0 .net8 "VPWR", 0 0, L_00000000039159d0; 1 drivers, strength-aware
+v00000000037f48c0_0 .net *"_s10", 0 0, L_00000000038121e0; 1 drivers
+L_0000000003973278 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f5680_0 .net/2u *"_s14", 0 0, L_0000000003973278; 1 drivers
+v00000000037f68a0_0 .net *"_s16", 0 0, L_0000000003813180; 1 drivers
+L_00000000039731e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f5ea0_0 .net/2u *"_s4", 0 0, L_00000000039731e8; 1 drivers
+L_0000000003973230 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f4a00_0 .net/2u *"_s8", 0 0, L_0000000003973230; 1 drivers
+v00000000037f64e0_0 .net "awake", 0 0, L_00000000038148a0; 1 drivers
+v00000000037f4aa0_0 .net "clkn", 0 0, L_0000000003968ee0; 1 drivers
+v00000000037f4be0_0 .net "m0", 0 0, L_0000000003969260; 1 drivers
+v00000000037f5040_0 .net "m0n", 0 0, L_00000000039691f0; 1 drivers
+v00000000037f5180_0 .var "notifier", 0 0;
+L_00000000038148a0 .cmp/eeq 1, L_00000000039159d0, L_00000000039731e8;
+L_00000000038121e0 .cmp/eeq 1, o00000000037970b8, L_0000000003973230;
+L_0000000003813180 .cmp/eeq 1, o0000000003797178, L_0000000003973278;
+S_00000000026c4f80 .scope module, "sky130_fd_sc_hd__sdlclkp_2" "sky130_fd_sc_hd__sdlclkp_2" 4 14808;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+o00000000037976b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f7520_0 .net "CLK", 0 0, o00000000037976b8; 0 drivers
+o0000000003797718 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f6c60_0 .net "GATE", 0 0, o0000000003797718; 0 drivers
+v00000000037f6e40_0 .net "GCLK", 0 0, L_0000000003969ce0; 1 drivers
+o00000000037977d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f7840_0 .net "SCE", 0 0, o00000000037977d8; 0 drivers
+L_00000000039155e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f75c0_0 .net8 "VGND", 0 0, L_00000000039155e0; 1 drivers, strength-aware
+L_0000000003915d50 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f7f20_0 .net8 "VNB", 0 0, L_0000000003915d50; 1 drivers, strength-aware
+L_0000000003915dc0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f8240_0 .net8 "VPB", 0 0, L_0000000003915dc0; 1 drivers, strength-aware
+L_0000000003915650 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f8420_0 .net8 "VPWR", 0 0, L_0000000003915650; 1 drivers, strength-aware
+S_000000000376e6f0 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14826, 4 14676 1, S_00000000026c4f80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+L_00000000039693b0 .functor NOT 1, L_0000000003969880, C4<0>, C4<0>, C4<0>;
+o00000000037976e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969490 .functor NOT 1, o00000000037976e8, C4<0>, C4<0>, C4<0>;
+o0000000003797778 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003797838 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003969810 .functor NOR 1, o0000000003797778, o0000000003797838, C4<0>, C4<0>;
+L_00000000039164c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003915a40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_0000000003969880 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_0000000003969810, L_0000000003969490, v00000000037f7de0_0, L_00000000039164c0, L_0000000003915a40;
+L_0000000003969ce0 .functor AND 1, L_00000000039693b0, o00000000037976e8, C4<1>, C4<1>;
+L_000000000396aae0 .functor AND 1, L_00000000038125a0, L_0000000003812280, C4<1>, C4<1>;
+L_000000000396b410 .functor AND 1, L_00000000038125a0, L_0000000003812dc0, C4<1>, C4<1>;
+v00000000037f5540_0 .net "CLK", 0 0, o00000000037976b8; alias, 0 drivers
+v00000000037f5860_0 .net "CLK_delayed", 0 0, o00000000037976e8; 0 drivers
+v00000000037f9000_0 .net "GATE", 0 0, o0000000003797718; alias, 0 drivers
+v00000000037f7fc0_0 .net "GATE_awake", 0 0, L_000000000396b410; 1 drivers
+v00000000037f81a0_0 .net "GATE_delayed", 0 0, o0000000003797778; 0 drivers
+v00000000037f7ca0_0 .net "GCLK", 0 0, L_0000000003969ce0; alias, 1 drivers
+v00000000037f8060_0 .net "SCE", 0 0, o00000000037977d8; alias, 0 drivers
+v00000000037f6940_0 .net "SCE_awake", 0 0, L_000000000396aae0; 1 drivers
+v00000000037f90a0_0 .net "SCE_delayed", 0 0, o0000000003797838; 0 drivers
+v00000000037f8740_0 .net "SCE_gate_delayed", 0 0, L_0000000003969810; 1 drivers
+v00000000037f6d00_0 .net8 "VGND", 0 0, L_0000000003915a40; 1 drivers, strength-aware
+L_0000000003916d80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f6da0_0 .net8 "VNB", 0 0, L_0000000003916d80; 1 drivers, strength-aware
+L_0000000003916220 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f69e0_0 .net8 "VPB", 0 0, L_0000000003916220; 1 drivers, strength-aware
+v00000000037f8b00_0 .net8 "VPWR", 0 0, L_00000000039164c0; 1 drivers, strength-aware
+v00000000037f7340_0 .net *"_s10", 0 0, L_0000000003812280; 1 drivers
+L_0000000003973350 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f87e0_0 .net/2u *"_s14", 0 0, L_0000000003973350; 1 drivers
+v00000000037f7480_0 .net *"_s16", 0 0, L_0000000003812dc0; 1 drivers
+L_00000000039732c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f6a80_0 .net/2u *"_s4", 0 0, L_00000000039732c0; 1 drivers
+L_0000000003973308 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f8880_0 .net/2u *"_s8", 0 0, L_0000000003973308; 1 drivers
+v00000000037f6bc0_0 .net "awake", 0 0, L_00000000038125a0; 1 drivers
+v00000000037f8920_0 .net "clkn", 0 0, L_0000000003969490; 1 drivers
+v00000000037f8ba0_0 .net "m0", 0 0, L_0000000003969880; 1 drivers
+v00000000037f7200_0 .net "m0n", 0 0, L_00000000039693b0; 1 drivers
+v00000000037f7de0_0 .var "notifier", 0 0;
+L_00000000038125a0 .cmp/eeq 1, L_00000000039164c0, L_00000000039732c0;
+L_0000000003812280 .cmp/eeq 1, o0000000003797778, L_0000000003973308;
+L_0000000003812dc0 .cmp/eeq 1, o0000000003797838, L_0000000003973350;
+S_00000000026c4680 .scope module, "sky130_fd_sc_hd__sdlclkp_4" "sky130_fd_sc_hd__sdlclkp_4" 4 14342;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+o0000000003797d78 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f7ac0_0 .net "CLK", 0 0, o0000000003797d78; 0 drivers
+o0000000003797dd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f73e0_0 .net "GATE", 0 0, o0000000003797dd8; 0 drivers
+v00000000037f8ce0_0 .net "GCLK", 0 0, L_000000000396a680; 1 drivers
+o0000000003797e98 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037f7b60_0 .net "SCE", 0 0, o0000000003797e98; 0 drivers
+L_0000000003916530 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f7c00_0 .net8 "VGND", 0 0, L_0000000003916530; 1 drivers, strength-aware
+L_0000000003916e60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f7d40_0 .net8 "VNB", 0 0, L_0000000003916e60; 1 drivers, strength-aware
+L_0000000003916f40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f8d80_0 .net8 "VPB", 0 0, L_0000000003916f40; 1 drivers, strength-aware
+L_00000000039183d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f8e20_0 .net8 "VPWR", 0 0, L_00000000039183d0; 1 drivers, strength-aware
+S_000000000376af70 .scope module, "base" "sky130_fd_sc_hd__sdlclkp" 4 14360, 4 14676 1, S_00000000026c4680;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "GCLK"
+ .port_info 1 /INPUT 1 "SCE"
+ .port_info 2 /INPUT 1 "GATE"
+ .port_info 3 /INPUT 1 "CLK"
+L_000000000396a5a0 .functor NOT 1, L_000000000396b8e0, C4<0>, C4<0>, C4<0>;
+o0000000003797da8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396ad10 .functor NOT 1, o0000000003797da8, C4<0>, C4<0>, C4<0>;
+o0000000003797e38 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003797ef8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396b3a0 .functor NOR 1, o0000000003797e38, o0000000003797ef8, C4<0>, C4<0>;
+L_0000000003917aa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_00000000039184b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396b8e0 .udp UDP_sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N, L_000000000396b3a0, L_000000000396ad10, v00000000037f7e80_0, L_0000000003917aa0, L_00000000039184b0;
+L_000000000396a680 .functor AND 1, L_000000000396a5a0, o0000000003797da8, C4<1>, C4<1>;
+L_000000000396aa70 .functor AND 1, L_0000000003812320, L_00000000038123c0, C4<1>, C4<1>;
+L_000000000396af40 .functor AND 1, L_0000000003812320, L_0000000003812460, C4<1>, C4<1>;
+v00000000037f89c0_0 .net "CLK", 0 0, o0000000003797d78; alias, 0 drivers
+v00000000037f8380_0 .net "CLK_delayed", 0 0, o0000000003797da8; 0 drivers
+v00000000037f7160_0 .net "GATE", 0 0, o0000000003797dd8; alias, 0 drivers
+v00000000037f78e0_0 .net "GATE_awake", 0 0, L_000000000396af40; 1 drivers
+v00000000037f8a60_0 .net "GATE_delayed", 0 0, o0000000003797e38; 0 drivers
+v00000000037f77a0_0 .net "GCLK", 0 0, L_000000000396a680; alias, 1 drivers
+v00000000037f8100_0 .net "SCE", 0 0, o0000000003797e98; alias, 0 drivers
+v00000000037f7660_0 .net "SCE_awake", 0 0, L_000000000396aa70; 1 drivers
+v00000000037f6ee0_0 .net "SCE_delayed", 0 0, o0000000003797ef8; 0 drivers
+v00000000037f82e0_0 .net "SCE_gate_delayed", 0 0, L_000000000396b3a0; 1 drivers
+v00000000037f84c0_0 .net8 "VGND", 0 0, L_00000000039184b0; 1 drivers, strength-aware
+L_0000000003918590 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f7700_0 .net8 "VNB", 0 0, L_0000000003918590; 1 drivers, strength-aware
+L_0000000003918210 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f8560_0 .net8 "VPB", 0 0, L_0000000003918210; 1 drivers, strength-aware
+v00000000037f7980_0 .net8 "VPWR", 0 0, L_0000000003917aa0; 1 drivers, strength-aware
+v00000000037f6f80_0 .net *"_s10", 0 0, L_00000000038123c0; 1 drivers
+L_0000000003973428 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f8600_0 .net/2u *"_s14", 0 0, L_0000000003973428; 1 drivers
+v00000000037f7a20_0 .net *"_s16", 0 0, L_0000000003812460; 1 drivers
+L_0000000003973398 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f6b20_0 .net/2u *"_s4", 0 0, L_0000000003973398; 1 drivers
+L_00000000039733e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f86a0_0 .net/2u *"_s8", 0 0, L_00000000039733e0; 1 drivers
+v00000000037f7020_0 .net "awake", 0 0, L_0000000003812320; 1 drivers
+v00000000037f8c40_0 .net "clkn", 0 0, L_000000000396ad10; 1 drivers
+v00000000037f70c0_0 .net "m0", 0 0, L_000000000396b8e0; 1 drivers
+v00000000037f72a0_0 .net "m0n", 0 0, L_000000000396a5a0; 1 drivers
+v00000000037f7e80_0 .var "notifier", 0 0;
+L_0000000003812320 .cmp/eeq 1, L_0000000003917aa0, L_0000000003973398;
+L_00000000038123c0 .cmp/eeq 1, o0000000003797e38, L_00000000039733e0;
+L_0000000003812460 .cmp/eeq 1, o0000000003797ef8, L_0000000003973428;
+S_00000000026c5100 .scope module, "sky130_fd_sc_hd__sedfxbp_1" "sky130_fd_sc_hd__sedfxbp_1" 4 99731;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+ .port_info 5 /INPUT 1 "SCD"
+ .port_info 6 /INPUT 1 "SCE"
+o0000000003798438 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fa220_0 .net "CLK", 0 0, o0000000003798438; 0 drivers
+o0000000003798498 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fab80_0 .net "D", 0 0, o0000000003798498; 0 drivers
+o00000000037984c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fa900_0 .net "DE", 0 0, o00000000037984c8; 0 drivers
+v00000000037f95a0_0 .net "Q", 0 0, L_000000000396b790; 1 drivers
+v00000000037fa4a0_0 .net "Q_N", 0 0, L_000000000396bb80; 1 drivers
+o00000000037985b8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fb300_0 .net "SCD", 0 0, o00000000037985b8; 0 drivers
+o0000000003798618 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037faea0_0 .net "SCE", 0 0, o0000000003798618; 0 drivers
+L_0000000003918750 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037facc0_0 .net8 "VGND", 0 0, L_0000000003918750; 1 drivers, strength-aware
+L_0000000003918520 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037faf40_0 .net8 "VNB", 0 0, L_0000000003918520; 1 drivers, strength-aware
+L_0000000003917b80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f9640_0 .net8 "VPB", 0 0, L_0000000003917b80; 1 drivers, strength-aware
+L_0000000003917790 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037f91e0_0 .net8 "VPWR", 0 0, L_0000000003917790; 1 drivers, strength-aware
+S_000000000376e9f0 .scope module, "base" "sky130_fd_sc_hd__sedfxbp" 4 99755, 4 100229 1, S_00000000026c5100;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+ .port_info 5 /INPUT 1 "SCD"
+ .port_info 6 /INPUT 1 "SCE"
+o00000000037985e8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003798648 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396b170 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396c0c0, o00000000037985e8, o0000000003798648;
+o0000000003798528 .functor BUFZ 1, C4<z>; HiZ drive
+o00000000037984f8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396c0c0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396ad80, o0000000003798528, o00000000037984f8;
+o0000000003798468 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039181a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003918670 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396ad80 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396b170, o0000000003798468, v00000000037fb120_0, L_00000000039181a0, L_0000000003918670;
+L_000000000396b1e0 .functor AND 1, L_0000000003813720, L_0000000003815340, C4<1>, C4<1>;
+L_000000000396be20 .functor AND 1, L_000000000396b1e0, L_0000000003815020, C4<1>, C4<1>;
+L_000000000396bf70 .functor AND 1, L_0000000003813720, L_0000000003816b00, C4<1>, C4<1>;
+L_000000000396afb0 .functor AND 1, L_0000000003813720, L_0000000003815480, C4<1>, C4<1>;
+L_000000000396b100 .functor AND 1, L_000000000396afb0, L_00000000038164c0, C4<1>, C4<1>;
+L_000000000396b790 .functor BUF 1, L_000000000396ad80, C4<0>, C4<0>, C4<0>;
+L_000000000396bb80 .functor NOT 1, L_000000000396ad80, C4<0>, C4<0>, C4<0>;
+v00000000037f8ec0_0 .net "CLK", 0 0, o0000000003798438; alias, 0 drivers
+v00000000037f8f60_0 .net "CLK_delayed", 0 0, o0000000003798468; 0 drivers
+v00000000037f9aa0_0 .net "D", 0 0, o0000000003798498; alias, 0 drivers
+v00000000037fa400_0 .net "DE", 0 0, o00000000037984c8; alias, 0 drivers
+v00000000037f9460_0 .net "DE_delayed", 0 0, o00000000037984f8; 0 drivers
+v00000000037fad60_0 .net "D_delayed", 0 0, o0000000003798528; 0 drivers
+v00000000037fa7c0_0 .net "Q", 0 0, L_000000000396b790; alias, 1 drivers
+v00000000037fa9a0_0 .net "Q_N", 0 0, L_000000000396bb80; alias, 1 drivers
+v00000000037fb800_0 .net "SCD", 0 0, o00000000037985b8; alias, 0 drivers
+v00000000037fb760_0 .net "SCD_delayed", 0 0, o00000000037985e8; 0 drivers
+v00000000037f9b40_0 .net "SCE", 0 0, o0000000003798618; alias, 0 drivers
+v00000000037fa5e0_0 .net "SCE_delayed", 0 0, o0000000003798648; 0 drivers
+v00000000037f9be0_0 .net8 "VGND", 0 0, L_0000000003918670; 1 drivers, strength-aware
+L_0000000003917870 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037f9500_0 .net8 "VNB", 0 0, L_0000000003917870; 1 drivers, strength-aware
+L_0000000003917170 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fae00_0 .net8 "VPB", 0 0, L_0000000003917170; 1 drivers, strength-aware
+v00000000037fa860_0 .net8 "VPWR", 0 0, L_00000000039181a0; 1 drivers, strength-aware
+v00000000037faa40_0 .net *"_s10", 0 0, L_0000000003815340; 1 drivers
+v00000000037fa680_0 .net *"_s12", 0 0, L_000000000396b1e0; 1 drivers
+L_0000000003973500 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fac20_0 .net/2u *"_s14", 0 0, L_0000000003973500; 1 drivers
+v00000000037fa540_0 .net *"_s16", 0 0, L_0000000003815020; 1 drivers
+L_0000000003973548 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fa720_0 .net/2u *"_s20", 0 0, L_0000000003973548; 1 drivers
+v00000000037fb8a0_0 .net *"_s22", 0 0, L_0000000003816b00; 1 drivers
+L_0000000003973590 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fb080_0 .net/2u *"_s26", 0 0, L_0000000003973590; 1 drivers
+v00000000037f9c80_0 .net *"_s28", 0 0, L_0000000003815480; 1 drivers
+v00000000037f98c0_0 .net *"_s30", 0 0, L_000000000396afb0; 1 drivers
+v00000000037f9140_0 .net *"_s32", 0 0, L_00000000038164c0; 1 drivers
+L_0000000003973470 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f9320_0 .net/2u *"_s4", 0 0, L_0000000003973470; 1 drivers
+L_00000000039734b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037f9fa0_0 .net/2u *"_s8", 0 0, L_00000000039734b8; 1 drivers
+v00000000037f9960_0 .net "awake", 0 0, L_0000000003813720; 1 drivers
+v00000000037faae0_0 .net "buf_Q", 0 0, L_000000000396ad80; 1 drivers
+v00000000037f9820_0 .net "cond1", 0 0, L_000000000396be20; 1 drivers
+v00000000037f9d20_0 .net "cond2", 0 0, L_000000000396bf70; 1 drivers
+v00000000037f96e0_0 .net "cond3", 0 0, L_000000000396b100; 1 drivers
+v00000000037f9dc0_0 .net "de_d", 0 0, L_000000000396c0c0; 1 drivers
+v00000000037fa040_0 .net "mux_out", 0 0, L_000000000396b170; 1 drivers
+v00000000037fb120_0 .var "notifier", 0 0;
+L_0000000003813720 .cmp/eeq 1, L_00000000039181a0, L_0000000003973470;
+L_0000000003815340 .cmp/eeq 1, o0000000003798648, L_00000000039734b8;
+L_0000000003815020 .cmp/eeq 1, o00000000037984f8, L_0000000003973500;
+L_0000000003816b00 .cmp/eeq 1, o0000000003798648, L_0000000003973548;
+L_0000000003815480 .cmp/eeq 1, o00000000037984f8, L_0000000003973590;
+L_00000000038164c0 .cmp/nee 1, o0000000003798528, o00000000037985e8;
+S_00000000026c5280 .scope module, "sky130_fd_sc_hd__sedfxbp_2" "sky130_fd_sc_hd__sedfxbp_2" 4 99862;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+ .port_info 5 /INPUT 1 "SCD"
+ .port_info 6 /INPUT 1 "SCE"
+o0000000003798e58 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fcf20_0 .net "CLK", 0 0, o0000000003798e58; 0 drivers
+o0000000003798eb8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fcde0_0 .net "D", 0 0, o0000000003798eb8; 0 drivers
+o0000000003798ee8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fd920_0 .net "DE", 0 0, o0000000003798ee8; 0 drivers
+v00000000037fc5c0_0 .net "Q", 0 0, L_000000000396bdb0; 1 drivers
+v00000000037fd9c0_0 .net "Q_N", 0 0, L_000000000396b720; 1 drivers
+o0000000003798fd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fca20_0 .net "SCD", 0 0, o0000000003798fd8; 0 drivers
+o0000000003799038 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fcac0_0 .net "SCE", 0 0, o0000000003799038; 0 drivers
+L_00000000039172c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fd060_0 .net8 "VGND", 0 0, L_00000000039172c0; 1 drivers, strength-aware
+L_0000000003917800 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fd240_0 .net8 "VNB", 0 0, L_0000000003917800; 1 drivers, strength-aware
+L_0000000003917100 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fda60_0 .net8 "VPB", 0 0, L_0000000003917100; 1 drivers, strength-aware
+L_0000000003918440 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fbb20_0 .net8 "VPWR", 0 0, L_0000000003918440; 1 drivers, strength-aware
+S_000000000376eb70 .scope module, "base" "sky130_fd_sc_hd__sedfxbp" 4 99886, 4 100229 1, S_00000000026c5280;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /OUTPUT 1 "Q_N"
+ .port_info 2 /INPUT 1 "CLK"
+ .port_info 3 /INPUT 1 "D"
+ .port_info 4 /INPUT 1 "DE"
+ .port_info 5 /INPUT 1 "SCD"
+ .port_info 6 /INPUT 1 "SCE"
+o0000000003799008 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003799068 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396b950 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396b020, o0000000003799008, o0000000003799068;
+o0000000003798f48 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003798f18 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396b020 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396b250, o0000000003798f48, o0000000003798f18;
+o0000000003798e88 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003918600 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003917410 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396b250 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396b950, o0000000003798e88, v00000000037fb9e0_0, L_0000000003918600, L_0000000003917410;
+L_000000000396a6f0 .functor AND 1, L_0000000003815660, L_0000000003814da0, C4<1>, C4<1>;
+L_000000000396baa0 .functor AND 1, L_000000000396a6f0, L_0000000003815ac0, C4<1>, C4<1>;
+L_000000000396b9c0 .functor AND 1, L_0000000003815660, L_0000000003816f60, C4<1>, C4<1>;
+L_000000000396a530 .functor AND 1, L_0000000003815660, L_0000000003814940, C4<1>, C4<1>;
+L_000000000396a610 .functor AND 1, L_000000000396a530, L_0000000003816ba0, C4<1>, C4<1>;
+L_000000000396bdb0 .functor BUF 1, L_000000000396b250, C4<0>, C4<0>, C4<0>;
+L_000000000396b720 .functor NOT 1, L_000000000396b250, C4<0>, C4<0>, C4<0>;
+v00000000037fafe0_0 .net "CLK", 0 0, o0000000003798e58; alias, 0 drivers
+v00000000037fb1c0_0 .net "CLK_delayed", 0 0, o0000000003798e88; 0 drivers
+v00000000037fb260_0 .net "D", 0 0, o0000000003798eb8; alias, 0 drivers
+v00000000037fb3a0_0 .net "DE", 0 0, o0000000003798ee8; alias, 0 drivers
+v00000000037f9e60_0 .net "DE_delayed", 0 0, o0000000003798f18; 0 drivers
+v00000000037fb440_0 .net "D_delayed", 0 0, o0000000003798f48; 0 drivers
+v00000000037f9f00_0 .net "Q", 0 0, L_000000000396bdb0; alias, 1 drivers
+v00000000037f93c0_0 .net "Q_N", 0 0, L_000000000396b720; alias, 1 drivers
+v00000000037fa180_0 .net "SCD", 0 0, o0000000003798fd8; alias, 0 drivers
+v00000000037f9780_0 .net "SCD_delayed", 0 0, o0000000003799008; 0 drivers
+v00000000037fa0e0_0 .net "SCE", 0 0, o0000000003799038; alias, 0 drivers
+v00000000037fa2c0_0 .net "SCE_delayed", 0 0, o0000000003799068; 0 drivers
+v00000000037fb4e0_0 .net8 "VGND", 0 0, L_0000000003917410; 1 drivers, strength-aware
+L_0000000003917330 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fa360_0 .net8 "VNB", 0 0, L_0000000003917330; 1 drivers, strength-aware
+L_0000000003918280 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fb580_0 .net8 "VPB", 0 0, L_0000000003918280; 1 drivers, strength-aware
+v00000000037fb620_0 .net8 "VPWR", 0 0, L_0000000003918600; 1 drivers, strength-aware
+v00000000037fb6c0_0 .net *"_s10", 0 0, L_0000000003814da0; 1 drivers
+v00000000037f9280_0 .net *"_s12", 0 0, L_000000000396a6f0; 1 drivers
+L_0000000003973668 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037f9a00_0 .net/2u *"_s14", 0 0, L_0000000003973668; 1 drivers
+v00000000037fd1a0_0 .net *"_s16", 0 0, L_0000000003815ac0; 1 drivers
+L_00000000039736b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fc520_0 .net/2u *"_s20", 0 0, L_00000000039736b0; 1 drivers
+v00000000037fcfc0_0 .net *"_s22", 0 0, L_0000000003816f60; 1 drivers
+L_00000000039736f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fb940_0 .net/2u *"_s26", 0 0, L_00000000039736f8; 1 drivers
+v00000000037fc700_0 .net *"_s28", 0 0, L_0000000003814940; 1 drivers
+v00000000037fd740_0 .net *"_s30", 0 0, L_000000000396a530; 1 drivers
+v00000000037fbd00_0 .net *"_s32", 0 0, L_0000000003816ba0; 1 drivers
+L_00000000039735d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fbda0_0 .net/2u *"_s4", 0 0, L_00000000039735d8; 1 drivers
+L_0000000003973620 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037fcca0_0 .net/2u *"_s8", 0 0, L_0000000003973620; 1 drivers
+v00000000037fc340_0 .net "awake", 0 0, L_0000000003815660; 1 drivers
+v00000000037fd7e0_0 .net "buf_Q", 0 0, L_000000000396b250; 1 drivers
+v00000000037fc3e0_0 .net "cond1", 0 0, L_000000000396baa0; 1 drivers
+v00000000037fbf80_0 .net "cond2", 0 0, L_000000000396b9c0; 1 drivers
+v00000000037fba80_0 .net "cond3", 0 0, L_000000000396a610; 1 drivers
+v00000000037fd880_0 .net "de_d", 0 0, L_000000000396b020; 1 drivers
+v00000000037fdd80_0 .net "mux_out", 0 0, L_000000000396b950; 1 drivers
+v00000000037fb9e0_0 .var "notifier", 0 0;
+L_0000000003815660 .cmp/eeq 1, L_0000000003918600, L_00000000039735d8;
+L_0000000003814da0 .cmp/eeq 1, o0000000003799068, L_0000000003973620;
+L_0000000003815ac0 .cmp/eeq 1, o0000000003798f18, L_0000000003973668;
+L_0000000003816f60 .cmp/eeq 1, o0000000003799068, L_00000000039736b0;
+L_0000000003814940 .cmp/eeq 1, o0000000003798f18, L_00000000039736f8;
+L_0000000003816ba0 .cmp/nee 1, o0000000003798f48, o0000000003799008;
+S_00000000026c5400 .scope module, "sky130_fd_sc_hd__sedfxtp_1" "sky130_fd_sc_hd__sedfxtp_1" 4 82068;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o0000000003799878 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fe0a0_0 .net "CLK", 0 0, o0000000003799878; 0 drivers
+o00000000037998d8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ff720_0 .net "D", 0 0, o00000000037998d8; 0 drivers
+o0000000003799908 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fff40_0 .net "DE", 0 0, o0000000003799908; 0 drivers
+v00000000037fec80_0 .net "Q", 0 0, L_000000000396c050; 1 drivers
+o00000000037999c8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ff900_0 .net "SCD", 0 0, o00000000037999c8; 0 drivers
+o0000000003799a28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038006c0_0 .net "SCE", 0 0, o0000000003799a28; 0 drivers
+L_0000000003917640 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fe8c0_0 .net8 "VGND", 0 0, L_0000000003917640; 1 drivers, strength-aware
+L_0000000003918830 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fe3c0_0 .net8 "VNB", 0 0, L_0000000003918830; 1 drivers, strength-aware
+L_00000000039171e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003800080_0 .net8 "VPB", 0 0, L_00000000039171e0; 1 drivers, strength-aware
+L_0000000003917bf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fe460_0 .net8 "VPWR", 0 0, L_0000000003917bf0; 1 drivers, strength-aware
+S_000000000376ecf0 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82090, 4 82673 1, S_00000000026c5400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o00000000037999f8 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003799a58 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396abc0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396bf00, o00000000037999f8, o0000000003799a58;
+o0000000003799968 .functor BUFZ 1, C4<z>; HiZ drive
+o0000000003799938 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396bf00 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396bcd0, o0000000003799968, o0000000003799938;
+o00000000037998a8 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039182f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003918050 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396bcd0 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396abc0, o00000000037998a8, v00000000037fe000_0, L_00000000039182f0, L_0000000003918050;
+L_000000000396b2c0 .functor AND 1, L_0000000003816c40, L_00000000038157a0, C4<1>, C4<1>;
+L_000000000396adf0 .functor AND 1, L_000000000396b2c0, L_00000000038149e0, C4<1>, C4<1>;
+L_000000000396a7d0 .functor AND 1, L_0000000003816c40, L_0000000003816380, C4<1>, C4<1>;
+L_000000000396a760 .functor AND 1, L_0000000003816c40, L_0000000003815520, C4<1>, C4<1>;
+L_000000000396a840 .functor AND 1, L_000000000396a760, L_0000000003816ec0, C4<1>, C4<1>;
+L_000000000396c050 .functor BUF 1, L_000000000396bcd0, C4<0>, C4<0>, C4<0>;
+v00000000037fc160_0 .net "CLK", 0 0, o0000000003799878; alias, 0 drivers
+v00000000037fc840_0 .net "CLK_delayed", 0 0, o00000000037998a8; 0 drivers
+v00000000037fc8e0_0 .net "D", 0 0, o00000000037998d8; alias, 0 drivers
+v00000000037fd2e0_0 .net "DE", 0 0, o0000000003799908; alias, 0 drivers
+v00000000037fdb00_0 .net "DE_delayed", 0 0, o0000000003799938; 0 drivers
+v00000000037fbe40_0 .net "D_delayed", 0 0, o0000000003799968; 0 drivers
+v00000000037fc480_0 .net "Q", 0 0, L_000000000396c050; alias, 1 drivers
+v00000000037fd560_0 .net "SCD", 0 0, o00000000037999c8; alias, 0 drivers
+v00000000037fdba0_0 .net "SCD_delayed", 0 0, o00000000037999f8; 0 drivers
+v00000000037fd100_0 .net "SCE", 0 0, o0000000003799a28; alias, 0 drivers
+v00000000037fc980_0 .net "SCE_delayed", 0 0, o0000000003799a58; 0 drivers
+v00000000037fbbc0_0 .net8 "VGND", 0 0, L_0000000003918050; 1 drivers, strength-aware
+L_00000000039180c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037fd600_0 .net8 "VNB", 0 0, L_00000000039180c0; 1 drivers, strength-aware
+L_0000000003918980 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fc660_0 .net8 "VPB", 0 0, L_0000000003918980; 1 drivers, strength-aware
+v00000000037fbc60_0 .net8 "VPWR", 0 0, L_00000000039182f0; 1 drivers, strength-aware
+v00000000037fbee0_0 .net *"_s10", 0 0, L_00000000038157a0; 1 drivers
+v00000000037fdf60_0 .net *"_s12", 0 0, L_000000000396b2c0; 1 drivers
+L_00000000039737d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fd380_0 .net/2u *"_s14", 0 0, L_00000000039737d0; 1 drivers
+v00000000037fd420_0 .net *"_s16", 0 0, L_00000000038149e0; 1 drivers
+L_0000000003973818 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fc020_0 .net/2u *"_s20", 0 0, L_0000000003973818; 1 drivers
+v00000000037fc0c0_0 .net *"_s22", 0 0, L_0000000003816380; 1 drivers
+L_0000000003973860 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fcc00_0 .net/2u *"_s26", 0 0, L_0000000003973860; 1 drivers
+v00000000037fcd40_0 .net *"_s28", 0 0, L_0000000003815520; 1 drivers
+v00000000037fd6a0_0 .net *"_s30", 0 0, L_000000000396a760; 1 drivers
+v00000000037fd4c0_0 .net *"_s32", 0 0, L_0000000003816ec0; 1 drivers
+L_0000000003973740 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fc7a0_0 .net/2u *"_s4", 0 0, L_0000000003973740; 1 drivers
+L_0000000003973788 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000037fcb60_0 .net/2u *"_s8", 0 0, L_0000000003973788; 1 drivers
+v00000000037fce80_0 .net "awake", 0 0, L_0000000003816c40; 1 drivers
+v00000000037fdc40_0 .net "buf_Q", 0 0, L_000000000396bcd0; 1 drivers
+v00000000037fdce0_0 .net "cond1", 0 0, L_000000000396adf0; 1 drivers
+v00000000037fde20_0 .net "cond2", 0 0, L_000000000396a7d0; 1 drivers
+v00000000037fdec0_0 .net "cond3", 0 0, L_000000000396a840; 1 drivers
+v00000000037fc200_0 .net "de_d", 0 0, L_000000000396bf00; 1 drivers
+v00000000037fc2a0_0 .net "mux_out", 0 0, L_000000000396abc0; 1 drivers
+v00000000037fe000_0 .var "notifier", 0 0;
+L_0000000003816c40 .cmp/eeq 1, L_00000000039182f0, L_0000000003973740;
+L_00000000038157a0 .cmp/eeq 1, o0000000003799a58, L_0000000003973788;
+L_00000000038149e0 .cmp/eeq 1, o0000000003799938, L_00000000039737d0;
+L_0000000003816380 .cmp/eeq 1, o0000000003799a58, L_0000000003973818;
+L_0000000003815520 .cmp/eeq 1, o0000000003799938, L_0000000003973860;
+L_0000000003816ec0 .cmp/nee 1, o0000000003799968, o00000000037999f8;
+S_00000000026c5580 .scope module, "sky130_fd_sc_hd__sedfxtp_2" "sky130_fd_sc_hd__sedfxtp_2" 4 82318;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o000000000379a208 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037ffae0_0 .net "CLK", 0 0, o000000000379a208; 0 drivers
+o000000000379a268 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003800580_0 .net "D", 0 0, o000000000379a268; 0 drivers
+o000000000379a298 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000037fe820_0 .net "DE", 0 0, o000000000379a298; 0 drivers
+v00000000037fee60_0 .net "Q", 0 0, L_000000000396b4f0; 1 drivers
+o000000000379a358 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003800620_0 .net "SCD", 0 0, o000000000379a358; 0 drivers
+o000000000379a3b8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003800800_0 .net "SCE", 0 0, o000000000379a3b8; 0 drivers
+L_0000000003918ad0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ffa40_0 .net8 "VGND", 0 0, L_0000000003918ad0; 1 drivers, strength-aware
+L_0000000003917e20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ff400_0 .net8 "VNB", 0 0, L_0000000003917e20; 1 drivers, strength-aware
+L_0000000003918b40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038008a0_0 .net8 "VPB", 0 0, L_0000000003918b40; 1 drivers, strength-aware
+L_00000000039186e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037fe780_0 .net8 "VPWR", 0 0, L_00000000039186e0; 1 drivers, strength-aware
+S_000000000376d370 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82340, 4 82673 1, S_00000000026c5580;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o000000000379a388 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000379a3e8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396a8b0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396a920, o000000000379a388, o000000000379a3e8;
+o000000000379a2f8 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000379a2c8 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396a920 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396b330, o000000000379a2f8, o000000000379a2c8;
+o000000000379a238 .functor BUFZ 1, C4<z>; HiZ drive
+L_00000000039187c0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003917c60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396b330 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396a8b0, o000000000379a238, v00000000037fe6e0_0, L_00000000039187c0, L_0000000003917c60;
+L_000000000396bbf0 .functor AND 1, L_0000000003815b60, L_00000000038167e0, C4<1>, C4<1>;
+L_000000000396b090 .functor AND 1, L_000000000396bbf0, L_0000000003816560, C4<1>, C4<1>;
+L_000000000396bfe0 .functor AND 1, L_0000000003815b60, L_0000000003815c00, C4<1>, C4<1>;
+L_000000000396a990 .functor AND 1, L_0000000003815b60, L_0000000003815840, C4<1>, C4<1>;
+L_000000000396b480 .functor AND 1, L_000000000396a990, L_0000000003814d00, C4<1>, C4<1>;
+L_000000000396b4f0 .functor BUF 1, L_000000000396b330, C4<0>, C4<0>, C4<0>;
+v00000000037fffe0_0 .net "CLK", 0 0, o000000000379a208; alias, 0 drivers
+v0000000003800120_0 .net "CLK_delayed", 0 0, o000000000379a238; 0 drivers
+v00000000037ff220_0 .net "D", 0 0, o000000000379a268; alias, 0 drivers
+v00000000037fed20_0 .net "DE", 0 0, o000000000379a298; alias, 0 drivers
+v00000000037ffcc0_0 .net "DE_delayed", 0 0, o000000000379a2c8; 0 drivers
+v00000000037ffc20_0 .net "D_delayed", 0 0, o000000000379a2f8; 0 drivers
+v00000000037ff2c0_0 .net "Q", 0 0, L_000000000396b4f0; alias, 1 drivers
+v00000000037ffd60_0 .net "SCD", 0 0, o000000000379a358; alias, 0 drivers
+v00000000037ff7c0_0 .net "SCD_delayed", 0 0, o000000000379a388; 0 drivers
+v00000000037fef00_0 .net "SCE", 0 0, o000000000379a3b8; alias, 0 drivers
+v00000000037fe640_0 .net "SCE_delayed", 0 0, o000000000379a3e8; 0 drivers
+v00000000038001c0_0 .net8 "VGND", 0 0, L_0000000003917c60; 1 drivers, strength-aware
+L_00000000039178e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000037ffb80_0 .net8 "VNB", 0 0, L_00000000039178e0; 1 drivers, strength-aware
+L_0000000003917950 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000037ffe00_0 .net8 "VPB", 0 0, L_0000000003917950; 1 drivers, strength-aware
+v00000000037ffea0_0 .net8 "VPWR", 0 0, L_00000000039187c0; 1 drivers, strength-aware
+v00000000037ff040_0 .net *"_s10", 0 0, L_00000000038167e0; 1 drivers
+v0000000003800260_0 .net *"_s12", 0 0, L_000000000396bbf0; 1 drivers
+L_0000000003973938 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fefa0_0 .net/2u *"_s14", 0 0, L_0000000003973938; 1 drivers
+v0000000003800300_0 .net *"_s16", 0 0, L_0000000003816560; 1 drivers
+L_0000000003973980 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037ff360_0 .net/2u *"_s20", 0 0, L_0000000003973980; 1 drivers
+v00000000037febe0_0 .net *"_s22", 0 0, L_0000000003815c00; 1 drivers
+L_00000000039739c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000038003a0_0 .net/2u *"_s26", 0 0, L_00000000039739c8; 1 drivers
+v00000000037fedc0_0 .net *"_s28", 0 0, L_0000000003815840; 1 drivers
+v00000000037ff9a0_0 .net *"_s30", 0 0, L_000000000396a990; 1 drivers
+v00000000037ff0e0_0 .net *"_s32", 0 0, L_0000000003814d00; 1 drivers
+L_00000000039738a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000037fe500_0 .net/2u *"_s4", 0 0, L_00000000039738a8; 1 drivers
+L_00000000039738f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003800440_0 .net/2u *"_s8", 0 0, L_00000000039738f0; 1 drivers
+v00000000037fe5a0_0 .net "awake", 0 0, L_0000000003815b60; 1 drivers
+v00000000037fe140_0 .net "buf_Q", 0 0, L_000000000396b330; 1 drivers
+v0000000003800760_0 .net "cond1", 0 0, L_000000000396b090; 1 drivers
+v00000000037fe1e0_0 .net "cond2", 0 0, L_000000000396bfe0; 1 drivers
+v00000000037fe280_0 .net "cond3", 0 0, L_000000000396b480; 1 drivers
+v00000000038004e0_0 .net "de_d", 0 0, L_000000000396a920; 1 drivers
+v00000000037ff860_0 .net "mux_out", 0 0, L_000000000396a8b0; 1 drivers
+v00000000037fe6e0_0 .var "notifier", 0 0;
+L_0000000003815b60 .cmp/eeq 1, L_00000000039187c0, L_00000000039738a8;
+L_00000000038167e0 .cmp/eeq 1, o000000000379a3e8, L_00000000039738f0;
+L_0000000003816560 .cmp/eeq 1, o000000000379a2c8, L_0000000003973938;
+L_0000000003815c00 .cmp/eeq 1, o000000000379a3e8, L_0000000003973980;
+L_0000000003815840 .cmp/eeq 1, o000000000379a2c8, L_00000000039739c8;
+L_0000000003814d00 .cmp/nee 1, o000000000379a2f8, o000000000379a388;
+S_00000000026be080 .scope module, "sky130_fd_sc_hd__sedfxtp_4" "sky130_fd_sc_hd__sedfxtp_4" 4 82193;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o000000000379ab98 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003802740_0 .net "CLK", 0 0, o000000000379ab98; 0 drivers
+o000000000379abf8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003800f80_0 .net "D", 0 0, o000000000379abf8; 0 drivers
+o000000000379ac28 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038022e0_0 .net "DE", 0 0, o000000000379ac28; 0 drivers
+v0000000003800d00_0 .net "Q", 0 0, L_000000000396b640; 1 drivers
+o000000000379ace8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003801520_0 .net "SCD", 0 0, o000000000379ace8; 0 drivers
+o000000000379ad48 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038010c0_0 .net "SCE", 0 0, o000000000379ad48; 0 drivers
+L_0000000003918360 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802d80_0 .net8 "VGND", 0 0, L_0000000003918360; 1 drivers, strength-aware
+L_00000000039189f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038021a0_0 .net8 "VNB", 0 0, L_00000000039189f0; 1 drivers, strength-aware
+L_0000000003917f00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801c00_0 .net8 "VPB", 0 0, L_0000000003917f00; 1 drivers, strength-aware
+L_0000000003918a60 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802100_0 .net8 "VPWR", 0 0, L_0000000003918a60; 1 drivers, strength-aware
+S_000000000376ac70 .scope module, "base" "sky130_fd_sc_hd__sedfxtp" 4 82215, 4 82673 1, S_00000000026be080;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Q"
+ .port_info 1 /INPUT 1 "CLK"
+ .port_info 2 /INPUT 1 "D"
+ .port_info 3 /INPUT 1 "DE"
+ .port_info 4 /INPUT 1 "SCD"
+ .port_info 5 /INPUT 1 "SCE"
+o000000000379ad18 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000379ad78 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396ae60 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396aca0, o000000000379ad18, o000000000379ad78;
+o000000000379ac88 .functor BUFZ 1, C4<z>; HiZ drive
+o000000000379ac58 .functor BUFZ 1, C4<z>; HiZ drive
+L_000000000396aca0 .udp UDP_sky130_fd_sc_hd__udp_mux_2to1, L_000000000396aa00, o000000000379ac88, o000000000379ac58;
+o000000000379abc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000000003917cd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+L_0000000003917250 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+L_000000000396aa00 .udp UDP_sky130_fd_sc_hd__udp_dff$P_pp$PG$N, L_000000000396ae60, o000000000379abc8, v0000000003802060_0, L_0000000003917cd0, L_0000000003917250;
+L_000000000396ab50 .functor AND 1, L_0000000003816ce0, L_0000000003814a80, C4<1>, C4<1>;
+L_000000000396ac30 .functor AND 1, L_000000000396ab50, L_0000000003814e40, C4<1>, C4<1>;
+L_000000000396aed0 .functor AND 1, L_0000000003816ce0, L_0000000003816740, C4<1>, C4<1>;
+L_000000000396b560 .functor AND 1, L_0000000003816ce0, L_00000000038155c0, C4<1>, C4<1>;
+L_000000000396b5d0 .functor AND 1, L_000000000396b560, L_0000000003816060, C4<1>, C4<1>;
+L_000000000396b640 .functor BUF 1, L_000000000396aa00, C4<0>, C4<0>, C4<0>;
+v00000000037ff4a0_0 .net "CLK", 0 0, o000000000379ab98; alias, 0 drivers
+v00000000037fe960_0 .net "CLK_delayed", 0 0, o000000000379abc8; 0 drivers
+v00000000037fe320_0 .net "D", 0 0, o000000000379abf8; alias, 0 drivers
+v00000000037fea00_0 .net "DE", 0 0, o000000000379ac28; alias, 0 drivers
+v00000000037feaa0_0 .net "DE_delayed", 0 0, o000000000379ac58; 0 drivers
+v00000000037ff180_0 .net "D_delayed", 0 0, o000000000379ac88; 0 drivers
+v00000000037feb40_0 .net "Q", 0 0, L_000000000396b640; alias, 1 drivers
+v00000000037ff540_0 .net "SCD", 0 0, o000000000379ace8; alias, 0 drivers
+v00000000037ff5e0_0 .net "SCD_delayed", 0 0, o000000000379ad18; 0 drivers
+v00000000037ff680_0 .net "SCE", 0 0, o000000000379ad48; alias, 0 drivers
+v0000000003802560_0 .net "SCE_delayed", 0 0, o000000000379ad78; 0 drivers
+v0000000003801fc0_0 .net8 "VGND", 0 0, L_0000000003917250; 1 drivers, strength-aware
+L_0000000003917b10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802240_0 .net8 "VNB", 0 0, L_0000000003917b10; 1 drivers, strength-aware
+L_00000000039188a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801de0_0 .net8 "VPB", 0 0, L_00000000039188a0; 1 drivers, strength-aware
+v0000000003802600_0 .net8 "VPWR", 0 0, L_0000000003917cd0; 1 drivers, strength-aware
+v0000000003802ce0_0 .net *"_s10", 0 0, L_0000000003814a80; 1 drivers
+v0000000003801d40_0 .net *"_s12", 0 0, L_000000000396ab50; 1 drivers
+L_0000000003973aa0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003801660_0 .net/2u *"_s14", 0 0, L_0000000003973aa0; 1 drivers
+v0000000003801020_0 .net *"_s16", 0 0, L_0000000003814e40; 1 drivers
+L_0000000003973ae8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003800ee0_0 .net/2u *"_s20", 0 0, L_0000000003973ae8; 1 drivers
+v0000000003800bc0_0 .net *"_s22", 0 0, L_0000000003816740; 1 drivers
+L_0000000003973b30 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0000000003801980_0 .net/2u *"_s26", 0 0, L_0000000003973b30; 1 drivers
+v0000000003800b20_0 .net *"_s28", 0 0, L_00000000038155c0; 1 drivers
+v00000000038018e0_0 .net *"_s30", 0 0, L_000000000396b560; 1 drivers
+v0000000003801a20_0 .net *"_s32", 0 0, L_0000000003816060; 1 drivers
+L_0000000003973a10 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v00000000038026a0_0 .net/2u *"_s4", 0 0, L_0000000003973a10; 1 drivers
+L_0000000003973a58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000000003801700_0 .net/2u *"_s8", 0 0, L_0000000003973a58; 1 drivers
+v0000000003801340_0 .net "awake", 0 0, L_0000000003816ce0; 1 drivers
+v0000000003800c60_0 .net "buf_Q", 0 0, L_000000000396aa00; 1 drivers
+v0000000003800940_0 .net "cond1", 0 0, L_000000000396ac30; 1 drivers
+v0000000003802f60_0 .net "cond2", 0 0, L_000000000396aed0; 1 drivers
+v00000000038009e0_0 .net "cond3", 0 0, L_000000000396b5d0; 1 drivers
+v0000000003800a80_0 .net "de_d", 0 0, L_000000000396aca0; 1 drivers
+v0000000003801ac0_0 .net "mux_out", 0 0, L_000000000396ae60; 1 drivers
+v0000000003802060_0 .var "notifier", 0 0;
+L_0000000003816ce0 .cmp/eeq 1, L_0000000003917cd0, L_0000000003973a10;
+L_0000000003814a80 .cmp/eeq 1, o000000000379ad78, L_0000000003973a58;
+L_0000000003814e40 .cmp/eeq 1, o000000000379ac58, L_0000000003973aa0;
+L_0000000003816740 .cmp/eeq 1, o000000000379ad78, L_0000000003973ae8;
+L_00000000038155c0 .cmp/eeq 1, o000000000379ac58, L_0000000003973b30;
+L_0000000003816060 .cmp/nee 1, o000000000379ac88, o000000000379ad18;
+S_00000000026c1c80 .scope module, "sky130_fd_sc_hd__tap_1" "sky130_fd_sc_hd__tap_1" 4 90393;
+ .timescale -9 -12;
+L_0000000003917d40 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038029c0_0 .net8 "VGND", 0 0, L_0000000003917d40; 1 drivers, strength-aware
+L_00000000039179c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038024c0_0 .net8 "VNB", 0 0, L_00000000039179c0; 1 drivers, strength-aware
+L_0000000003918910 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801160_0 .net8 "VPB", 0 0, L_0000000003918910; 1 drivers, strength-aware
+L_0000000003917480 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801200_0 .net8 "VPWR", 0 0, L_0000000003917480; 1 drivers, strength-aware
+S_000000000376ee70 .scope module, "base" "sky130_fd_sc_hd__tap" 4 90400, 4 90307 1, S_00000000026c1c80;
+ .timescale -9 -12;
+L_0000000003917db0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802380_0 .net8 "VGND", 0 0, L_0000000003917db0; 1 drivers, strength-aware
+L_0000000003918bb0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003800da0_0 .net8 "VNB", 0 0, L_0000000003918bb0; 1 drivers, strength-aware
+L_0000000003918c20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003800e40_0 .net8 "VPB", 0 0, L_0000000003918c20; 1 drivers, strength-aware
+L_0000000003917e90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802420_0 .net8 "VPWR", 0 0, L_0000000003917e90; 1 drivers, strength-aware
+S_00000000026bfa00 .scope module, "sky130_fd_sc_hd__tap_2" "sky130_fd_sc_hd__tap_2" 4 90073;
+ .timescale -9 -12;
+L_0000000003917a30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003801e80_0 .net8 "VGND", 0 0, L_0000000003917a30; 1 drivers, strength-aware
+L_00000000039175d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802e20_0 .net8 "VNB", 0 0, L_00000000039175d0; 1 drivers, strength-aware
+L_0000000003918c90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038013e0_0 .net8 "VPB", 0 0, L_0000000003918c90; 1 drivers, strength-aware
+L_00000000039173a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801480_0 .net8 "VPWR", 0 0, L_00000000039173a0; 1 drivers, strength-aware
+S_000000000376cef0 .scope module, "base" "sky130_fd_sc_hd__tap" 4 90080, 4 90307 1, S_00000000026bfa00;
+ .timescale -9 -12;
+L_0000000003917f70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038012a0_0 .net8 "VGND", 0 0, L_0000000003917f70; 1 drivers, strength-aware
+L_00000000039174f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038017a0_0 .net8 "VNB", 0 0, L_00000000039174f0; 1 drivers, strength-aware
+L_0000000003918130 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038027e0_0 .net8 "VPB", 0 0, L_0000000003918130; 1 drivers, strength-aware
+L_0000000003917fe0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802880_0 .net8 "VPWR", 0 0, L_0000000003917fe0; 1 drivers, strength-aware
+S_00000000026c3180 .scope module, "sky130_fd_sc_hd__tapvgnd2_1" "sky130_fd_sc_hd__tapvgnd2_1" 4 41561;
+ .timescale -9 -12;
+L_0000000003917560 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003801f20_0 .net8 "VGND", 0 0, L_0000000003917560; 1 drivers, strength-aware
+L_00000000039176b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802ec0_0 .net8 "VNB", 0 0, L_00000000039176b0; 1 drivers, strength-aware
+L_0000000003917720 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802920_0 .net8 "VPB", 0 0, L_0000000003917720; 1 drivers, strength-aware
+L_0000000003918d00 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802a60_0 .net8 "VPWR", 0 0, L_0000000003918d00; 1 drivers, strength-aware
+S_000000000376b0f0 .scope module, "base" "sky130_fd_sc_hd__tapvgnd2" 4 41568, 4 41474 1, S_00000000026c3180;
+ .timescale -9 -12;
+L_0000000003919630 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038015c0_0 .net8 "VGND", 0 0, L_0000000003919630; 1 drivers, strength-aware
+L_000000000391a120 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003801840_0 .net8 "VNB", 0 0, L_000000000391a120; 1 drivers, strength-aware
+L_0000000003919da0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801b60_0 .net8 "VPB", 0 0, L_0000000003919da0; 1 drivers, strength-aware
+L_0000000003918d70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003801ca0_0 .net8 "VPWR", 0 0, L_0000000003918d70; 1 drivers, strength-aware
+S_00000000026c0780 .scope module, "sky130_fd_sc_hd__tapvgnd_1" "sky130_fd_sc_hd__tapvgnd_1" 4 45024;
+ .timescale -9 -12;
+L_00000000039196a0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038030a0_0 .net8 "VGND", 0 0, L_00000000039196a0; 1 drivers, strength-aware
+L_0000000003919e10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803f00_0 .net8 "VNB", 0 0, L_0000000003919e10; 1 drivers, strength-aware
+L_0000000003918fa0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804680_0 .net8 "VPB", 0 0, L_0000000003918fa0; 1 drivers, strength-aware
+L_0000000003919a90 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803500_0 .net8 "VPWR", 0 0, L_0000000003919a90; 1 drivers, strength-aware
+S_000000000376b870 .scope module, "base" "sky130_fd_sc_hd__tapvgnd" 4 45031, 4 45263 1, S_00000000026c0780;
+ .timescale -9 -12;
+L_0000000003919390 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802b00_0 .net8 "VGND", 0 0, L_0000000003919390; 1 drivers, strength-aware
+L_000000000391a3c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003802ba0_0 .net8 "VNB", 0 0, L_000000000391a3c0; 1 drivers, strength-aware
+L_00000000039192b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003802c40_0 .net8 "VPB", 0 0, L_00000000039192b0; 1 drivers, strength-aware
+L_0000000003919b70 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803000_0 .net8 "VPWR", 0 0, L_0000000003919b70; 1 drivers, strength-aware
+S_00000000026c0900 .scope module, "sky130_fd_sc_hd__tapvpwrvgnd_1" "sky130_fd_sc_hd__tapvpwrvgnd_1" 4 55677;
+ .timescale -9 -12;
+L_0000000003919710 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038056c0_0 .net8 "VGND", 0 0, L_0000000003919710; 1 drivers, strength-aware
+L_000000000391a890 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003805580_0 .net8 "VNB", 0 0, L_000000000391a890; 1 drivers, strength-aware
+L_0000000003919320 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805080_0 .net8 "VPB", 0 0, L_0000000003919320; 1 drivers, strength-aware
+L_0000000003919780 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038033c0_0 .net8 "VPWR", 0 0, L_0000000003919780; 1 drivers, strength-aware
+S_000000000376b270 .scope module, "base" "sky130_fd_sc_hd__tapvpwrvgnd" 4 55684, 4 55911 1, S_00000000026c0900;
+ .timescale -9 -12;
+L_0000000003919f60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804720_0 .net8 "VGND", 0 0, L_0000000003919f60; 1 drivers, strength-aware
+L_000000000391a5f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804f40_0 .net8 "VNB", 0 0, L_000000000391a5f0; 1 drivers, strength-aware
+L_000000000391a4a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803c80_0 .net8 "VPB", 0 0, L_000000000391a4a0; 1 drivers, strength-aware
+L_000000000391a0b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803280_0 .net8 "VPWR", 0 0, L_000000000391a0b0; 1 drivers, strength-aware
+S_00000000026bdd80 .scope module, "sky130_fd_sc_hd__xnor2_1" "sky130_fd_sc_hd__xnor2_1" 4 99084;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379bca8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003803320_0 .net "A", 0 0, o000000000379bca8; 0 drivers
+o000000000379bcd8 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038047c0_0 .net "B", 0 0, o000000000379bcd8; 0 drivers
+L_00000000039197f0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803fa0_0 .net8 "VGND", 0 0, L_00000000039197f0; 1 drivers, strength-aware
+L_000000000391a6d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003805120_0 .net8 "VNB", 0 0, L_000000000391a6d0; 1 drivers, strength-aware
+L_000000000391a430 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804040_0 .net8 "VPB", 0 0, L_000000000391a430; 1 drivers, strength-aware
+L_0000000003919940 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804e00_0 .net8 "VPWR", 0 0, L_0000000003919940; 1 drivers, strength-aware
+v0000000003804c20_0 .net "Y", 0 0, L_000000000396b870; 1 drivers
+S_000000000376b6f0 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99100, 4 99391 1, S_00000000026bdd80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396b800 .functor XNOR 1, o000000000379bca8, o000000000379bcd8, C4<0>, C4<0>;
+L_000000000396b870 .functor BUF 1, L_000000000396b800, C4<0>, C4<0>, C4<0>;
+v0000000003804a40_0 .net "A", 0 0, o000000000379bca8; alias, 0 drivers
+v0000000003803d20_0 .net "B", 0 0, o000000000379bcd8; alias, 0 drivers
+L_0000000003919860 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803460_0 .net8 "VGND", 0 0, L_0000000003919860; 1 drivers, strength-aware
+L_0000000003919400 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803640_0 .net8 "VNB", 0 0, L_0000000003919400; 1 drivers, strength-aware
+L_00000000039194e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803820_0 .net8 "VPB", 0 0, L_00000000039194e0; 1 drivers, strength-aware
+L_000000000391a510 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003803dc0_0 .net8 "VPWR", 0 0, L_000000000391a510; 1 drivers, strength-aware
+v0000000003803e60_0 .net "Y", 0 0, L_000000000396b870; alias, 1 drivers
+v0000000003804cc0_0 .net "xnor0_out_Y", 0 0, L_000000000396b800; 1 drivers
+S_00000000026c1b00 .scope module, "sky130_fd_sc_hd__xnor2_2" "sky130_fd_sc_hd__xnor2_2" 4 99612;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379c008 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003803be0_0 .net "A", 0 0, o000000000379c008; 0 drivers
+o000000000379c038 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003804220_0 .net "B", 0 0, o000000000379c038; 0 drivers
+L_0000000003919be0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803780_0 .net8 "VGND", 0 0, L_0000000003919be0; 1 drivers, strength-aware
+L_0000000003919fd0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038049a0_0 .net8 "VNB", 0 0, L_0000000003919fd0; 1 drivers, strength-aware
+L_0000000003919c50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038042c0_0 .net8 "VPB", 0 0, L_0000000003919c50; 1 drivers, strength-aware
+L_0000000003919470 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804860_0 .net8 "VPWR", 0 0, L_0000000003919470; 1 drivers, strength-aware
+v0000000003803140_0 .net "Y", 0 0, L_000000000396bb10; 1 drivers
+S_000000000376b9f0 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99628, 4 99391 1, S_00000000026c1b00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396ba30 .functor XNOR 1, o000000000379c008, o000000000379c038, C4<0>, C4<0>;
+L_000000000396bb10 .functor BUF 1, L_000000000396ba30, C4<0>, C4<0>, C4<0>;
+v00000000038040e0_0 .net "A", 0 0, o000000000379c008; alias, 0 drivers
+v00000000038036e0_0 .net "B", 0 0, o000000000379c038; alias, 0 drivers
+L_0000000003919e80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804d60_0 .net8 "VGND", 0 0, L_0000000003919e80; 1 drivers, strength-aware
+L_000000000391a200 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804180_0 .net8 "VNB", 0 0, L_000000000391a200; 1 drivers, strength-aware
+L_0000000003918de0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804900_0 .net8 "VPB", 0 0, L_0000000003918de0; 1 drivers, strength-aware
+L_0000000003918ec0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038038c0_0 .net8 "VPWR", 0 0, L_0000000003918ec0; 1 drivers, strength-aware
+v00000000038054e0_0 .net "Y", 0 0, L_000000000396bb10; alias, 1 drivers
+v0000000003805620_0 .net "xnor0_out_Y", 0 0, L_000000000396ba30; 1 drivers
+S_00000000026c1200 .scope module, "sky130_fd_sc_hd__xnor2_4" "sky130_fd_sc_hd__xnor2_4" 4 99504;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379c368 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003803a00_0 .net "A", 0 0, o000000000379c368; 0 drivers
+o000000000379c398 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003805800_0 .net "B", 0 0, o000000000379c398; 0 drivers
+L_000000000391a7b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804ea0_0 .net8 "VGND", 0 0, L_000000000391a7b0; 1 drivers, strength-aware
+L_000000000391a040 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804400_0 .net8 "VNB", 0 0, L_000000000391a040; 1 drivers, strength-aware
+L_000000000391a270 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038051c0_0 .net8 "VPB", 0 0, L_000000000391a270; 1 drivers, strength-aware
+L_0000000003919080 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038044a0_0 .net8 "VPWR", 0 0, L_0000000003919080; 1 drivers, strength-aware
+v0000000003805260_0 .net "Y", 0 0, L_000000000396d1d0; 1 drivers
+S_000000000376d970 .scope module, "base" "sky130_fd_sc_hd__xnor2" 4 99520, 4 99391 1, S_00000000026c1200;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "Y"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396bc60 .functor XNOR 1, o000000000379c368, o000000000379c398, C4<0>, C4<0>;
+L_000000000396d1d0 .functor BUF 1, L_000000000396bc60, C4<0>, C4<0>, C4<0>;
+v00000000038031e0_0 .net "A", 0 0, o000000000379c368; alias, 0 drivers
+v0000000003804ae0_0 .net "B", 0 0, o000000000379c398; alias, 0 drivers
+L_0000000003919b00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804fe0_0 .net8 "VGND", 0 0, L_0000000003919b00; 1 drivers, strength-aware
+L_0000000003918f30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804360_0 .net8 "VNB", 0 0, L_0000000003918f30; 1 drivers, strength-aware
+L_00000000039198d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003804b80_0 .net8 "VPB", 0 0, L_00000000039198d0; 1 drivers, strength-aware
+L_0000000003919010 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805760_0 .net8 "VPWR", 0 0, L_0000000003919010; 1 drivers, strength-aware
+v0000000003803960_0 .net "Y", 0 0, L_000000000396d1d0; alias, 1 drivers
+v00000000038035a0_0 .net "xnor0_out_Y", 0 0, L_000000000396bc60; 1 drivers
+S_00000000026c1500 .scope module, "sky130_fd_sc_hd__xnor3_1" "sky130_fd_sc_hd__xnor3_1" 4 57031;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379c6c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807100_0 .net "A", 0 0, o000000000379c6c8; 0 drivers
+o000000000379c6f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003806a20_0 .net "B", 0 0, o000000000379c6f8; 0 drivers
+o000000000379c728 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038063e0_0 .net "C", 0 0, o000000000379c728; 0 drivers
+L_000000000391a190 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038071a0_0 .net8 "VGND", 0 0, L_000000000391a190; 1 drivers, strength-aware
+L_000000000391a350 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806520_0 .net8 "VNB", 0 0, L_000000000391a350; 1 drivers, strength-aware
+L_000000000391a820 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806160_0 .net8 "VPB", 0 0, L_000000000391a820; 1 drivers, strength-aware
+L_0000000003919ef0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806020_0 .net8 "VPWR", 0 0, L_0000000003919ef0; 1 drivers, strength-aware
+v0000000003806700_0 .net "X", 0 0, L_000000000396c7c0; 1 drivers
+S_000000000376bb70 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57049, 4 57561 1, S_00000000026c1500;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396ce50 .functor XNOR 1, o000000000379c6c8, o000000000379c6f8, o000000000379c728, C4<0>;
+L_000000000396c7c0 .functor BUF 1, L_000000000396ce50, C4<0>, C4<0>, C4<0>;
+v0000000003805300_0 .net "A", 0 0, o000000000379c6c8; alias, 0 drivers
+v0000000003803aa0_0 .net "B", 0 0, o000000000379c6f8; alias, 0 drivers
+v00000000038053a0_0 .net "C", 0 0, o000000000379c728; alias, 0 drivers
+L_0000000003919a20 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003804540_0 .net8 "VGND", 0 0, L_0000000003919a20; 1 drivers, strength-aware
+L_00000000039199b0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003803b40_0 .net8 "VNB", 0 0, L_00000000039199b0; 1 drivers, strength-aware
+L_0000000003919550 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038045e0_0 .net8 "VPB", 0 0, L_0000000003919550; 1 drivers, strength-aware
+L_0000000003918e50 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038058a0_0 .net8 "VPWR", 0 0, L_0000000003918e50; 1 drivers, strength-aware
+v0000000003805440_0 .net "X", 0 0, L_000000000396c7c0; alias, 1 drivers
+v00000000038072e0_0 .net "xnor0_out_X", 0 0, L_000000000396ce50; 1 drivers
+S_00000000026bfe80 .scope module, "sky130_fd_sc_hd__xnor3_2" "sky130_fd_sc_hd__xnor3_2" 4 57255;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379cab8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807740_0 .net "A", 0 0, o000000000379cab8; 0 drivers
+o000000000379cae8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807ce0_0 .net "B", 0 0, o000000000379cae8; 0 drivers
+o000000000379cb18 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807920_0 .net "C", 0 0, o000000000379cb18; 0 drivers
+L_0000000003919cc0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038074c0_0 .net8 "VGND", 0 0, L_0000000003919cc0; 1 drivers, strength-aware
+L_00000000039195c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003807060_0 .net8 "VNB", 0 0, L_00000000039195c0; 1 drivers, strength-aware
+L_00000000039190f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805940_0 .net8 "VPB", 0 0, L_00000000039190f0; 1 drivers, strength-aware
+L_0000000003919d30 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806ac0_0 .net8 "VPWR", 0 0, L_0000000003919d30; 1 drivers, strength-aware
+v0000000003806660_0 .net "X", 0 0, L_000000000396cfa0; 1 drivers
+S_000000000376be70 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57273, 4 57561 1, S_00000000026bfe80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396cc20 .functor XNOR 1, o000000000379cab8, o000000000379cae8, o000000000379cb18, C4<0>;
+L_000000000396cfa0 .functor BUF 1, L_000000000396cc20, C4<0>, C4<0>, C4<0>;
+v0000000003807240_0 .net "A", 0 0, o000000000379cab8; alias, 0 drivers
+v0000000003807380_0 .net "B", 0 0, o000000000379cae8; alias, 0 drivers
+v0000000003806fc0_0 .net "C", 0 0, o000000000379cb18; alias, 0 drivers
+L_000000000391a2e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806de0_0 .net8 "VGND", 0 0, L_000000000391a2e0; 1 drivers, strength-aware
+L_000000000391a580 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003807420_0 .net8 "VNB", 0 0, L_000000000391a580; 1 drivers, strength-aware
+L_000000000391a660 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805c60_0 .net8 "VPB", 0 0, L_000000000391a660; 1 drivers, strength-aware
+L_000000000391a740 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038065c0_0 .net8 "VPWR", 0 0, L_000000000391a740; 1 drivers, strength-aware
+v0000000003805f80_0 .net "X", 0 0, L_000000000396cfa0; alias, 1 drivers
+v00000000038076a0_0 .net "xnor0_out_X", 0 0, L_000000000396cc20; 1 drivers
+S_00000000026bf400 .scope module, "sky130_fd_sc_hd__xnor3_4" "sky130_fd_sc_hd__xnor3_4" 4 57143;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379cea8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003806f20_0 .net "A", 0 0, o000000000379cea8; 0 drivers
+o000000000379ced8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807d80_0 .net "B", 0 0, o000000000379ced8; 0 drivers
+o000000000379cf08 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038062a0_0 .net "C", 0 0, o000000000379cf08; 0 drivers
+L_0000000003919160 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806340_0 .net8 "VGND", 0 0, L_0000000003919160; 1 drivers, strength-aware
+L_00000000039191d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806200_0 .net8 "VNB", 0 0, L_00000000039191d0; 1 drivers, strength-aware
+L_0000000003919240 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806480_0 .net8 "VPB", 0 0, L_0000000003919240; 1 drivers, strength-aware
+L_000000000391b5b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805bc0_0 .net8 "VPWR", 0 0, L_000000000391b5b0; 1 drivers, strength-aware
+v0000000003806980_0 .net "X", 0 0, L_000000000396cf30; 1 drivers
+S_000000000376bff0 .scope module, "base" "sky130_fd_sc_hd__xnor3" 4 57161, 4 57561 1, S_00000000026bf400;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396d4e0 .functor XNOR 1, o000000000379cea8, o000000000379ced8, o000000000379cf08, C4<0>;
+L_000000000396cf30 .functor BUF 1, L_000000000396d4e0, C4<0>, C4<0>, C4<0>;
+v0000000003807b00_0 .net "A", 0 0, o000000000379cea8; alias, 0 drivers
+v00000000038079c0_0 .net "B", 0 0, o000000000379ced8; alias, 0 drivers
+v0000000003807560_0 .net "C", 0 0, o000000000379cf08; alias, 0 drivers
+L_000000000391b690 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003805d00_0 .net8 "VGND", 0 0, L_000000000391b690; 1 drivers, strength-aware
+L_000000000391ac10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003807f60_0 .net8 "VNB", 0 0, L_000000000391ac10; 1 drivers, strength-aware
+L_000000000391c3b0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806b60_0 .net8 "VPB", 0 0, L_000000000391c3b0; 1 drivers, strength-aware
+L_000000000391b150 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806e80_0 .net8 "VPWR", 0 0, L_000000000391b150; 1 drivers, strength-aware
+v00000000038060c0_0 .net "X", 0 0, L_000000000396cf30; alias, 1 drivers
+v00000000038067a0_0 .net "xnor0_out_X", 0 0, L_000000000396d4e0; 1 drivers
+S_00000000026c0d80 .scope module, "sky130_fd_sc_hd__xor2_1" "sky130_fd_sc_hd__xor2_1" 4 39544;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379d298 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003806ca0_0 .net "A", 0 0, o000000000379d298; 0 drivers
+o000000000379d2c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003807c40_0 .net "B", 0 0, o000000000379d2c8; 0 drivers
+L_000000000391bd90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806d40_0 .net8 "VGND", 0 0, L_000000000391bd90; 1 drivers, strength-aware
+L_000000000391ab30 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038059e0_0 .net8 "VNB", 0 0, L_000000000391ab30; 1 drivers, strength-aware
+L_000000000391ae40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808000_0 .net8 "VPB", 0 0, L_000000000391ae40; 1 drivers, strength-aware
+L_000000000391c180 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003807e20_0 .net8 "VPWR", 0 0, L_000000000391c180; 1 drivers, strength-aware
+v0000000003807ec0_0 .net "X", 0 0, L_000000000396d0f0; 1 drivers
+S_000000000376eff0 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39560, 4 39851 1, S_00000000026c0d80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396d550 .functor XOR 1, o000000000379d2c8, o000000000379d298, C4<0>, C4<0>;
+L_000000000396d0f0 .functor BUF 1, L_000000000396d550, C4<0>, C4<0>, C4<0>;
+v0000000003807600_0 .net "A", 0 0, o000000000379d298; alias, 0 drivers
+v00000000038077e0_0 .net "B", 0 0, o000000000379d2c8; alias, 0 drivers
+L_000000000391b620 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003806840_0 .net8 "VGND", 0 0, L_000000000391b620; 1 drivers, strength-aware
+L_000000000391aba0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003807880_0 .net8 "VNB", 0 0, L_000000000391aba0; 1 drivers, strength-aware
+L_000000000391b4d0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003806c00_0 .net8 "VPB", 0 0, L_000000000391b4d0; 1 drivers, strength-aware
+L_000000000391a970 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038068e0_0 .net8 "VPWR", 0 0, L_000000000391a970; 1 drivers, strength-aware
+v0000000003807a60_0 .net "X", 0 0, L_000000000396d0f0; alias, 1 drivers
+v0000000003807ba0_0 .net "xor0_out_X", 0 0, L_000000000396d550; 1 drivers
+S_00000000026be380 .scope module, "sky130_fd_sc_hd__xor2_2" "sky130_fd_sc_hd__xor2_2" 4 39964;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379d5f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809b80_0 .net "A", 0 0, o000000000379d5f8; 0 drivers
+o000000000379d628 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003808460_0 .net "B", 0 0, o000000000379d628; 0 drivers
+L_000000000391af90 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380a440_0 .net8 "VGND", 0 0, L_000000000391af90; 1 drivers, strength-aware
+L_000000000391c490 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808e60_0 .net8 "VNB", 0 0, L_000000000391c490; 1 drivers, strength-aware
+L_000000000391b770 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038081e0_0 .net8 "VPB", 0 0, L_000000000391b770; 1 drivers, strength-aware
+L_000000000391bbd0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380a620_0 .net8 "VPWR", 0 0, L_000000000391bbd0; 1 drivers, strength-aware
+v00000000038085a0_0 .net "X", 0 0, L_000000000396cec0; 1 drivers
+S_000000000376f170 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39980, 4 39851 1, S_00000000026be380;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396d8d0 .functor XOR 1, o000000000379d628, o000000000379d5f8, C4<0>, C4<0>;
+L_000000000396cec0 .functor BUF 1, L_000000000396d8d0, C4<0>, C4<0>, C4<0>;
+v00000000038080a0_0 .net "A", 0 0, o000000000379d5f8; alias, 0 drivers
+v0000000003805a80_0 .net "B", 0 0, o000000000379d628; alias, 0 drivers
+L_000000000391b0e0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003805b20_0 .net8 "VGND", 0 0, L_000000000391b0e0; 1 drivers, strength-aware
+L_000000000391b540 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003805da0_0 .net8 "VNB", 0 0, L_000000000391b540; 1 drivers, strength-aware
+L_000000000391aeb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805e40_0 .net8 "VPB", 0 0, L_000000000391aeb0; 1 drivers, strength-aware
+L_000000000391acf0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003805ee0_0 .net8 "VPWR", 0 0, L_000000000391acf0; 1 drivers, strength-aware
+v0000000003808820_0 .net "X", 0 0, L_000000000396cec0; alias, 1 drivers
+v000000000380a4e0_0 .net "xor0_out_X", 0 0, L_000000000396d8d0; 1 drivers
+S_00000000026c0a80 .scope module, "sky130_fd_sc_hd__xor2_4" "sky130_fd_sc_hd__xor2_4" 4 39436;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+o000000000379d958 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809c20_0 .net "A", 0 0, o000000000379d958; 0 drivers
+o000000000379d988 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809540_0 .net "B", 0 0, o000000000379d988; 0 drivers
+L_000000000391b8c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808fa0_0 .net8 "VGND", 0 0, L_000000000391b8c0; 1 drivers, strength-aware
+L_000000000391b310 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038088c0_0 .net8 "VNB", 0 0, L_000000000391b310; 1 drivers, strength-aware
+L_000000000391c030 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808780_0 .net8 "VPB", 0 0, L_000000000391c030; 1 drivers, strength-aware
+L_000000000391a9e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v00000000038083c0_0 .net8 "VPWR", 0 0, L_000000000391a9e0; 1 drivers, strength-aware
+v0000000003809180_0 .net "X", 0 0, L_000000000396c830; 1 drivers
+S_000000000376f2f0 .scope module, "base" "sky130_fd_sc_hd__xor2" 4 39452, 4 39851 1, S_00000000026c0a80;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+L_000000000396d5c0 .functor XOR 1, o000000000379d988, o000000000379d958, C4<0>, C4<0>;
+L_000000000396c830 .functor BUF 1, L_000000000396d5c0, C4<0>, C4<0>, C4<0>;
+v00000000038099a0_0 .net "A", 0 0, o000000000379d958; alias, 0 drivers
+v0000000003808500_0 .net "B", 0 0, o000000000379d988; alias, 0 drivers
+L_000000000391be00 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808960_0 .net8 "VGND", 0 0, L_000000000391be00; 1 drivers, strength-aware
+L_000000000391b460 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v00000000038095e0_0 .net8 "VNB", 0 0, L_000000000391b460; 1 drivers, strength-aware
+L_000000000391b700 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808aa0_0 .net8 "VPB", 0 0, L_000000000391b700; 1 drivers, strength-aware
+L_000000000391c1f0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808f00_0 .net8 "VPWR", 0 0, L_000000000391c1f0; 1 drivers, strength-aware
+v00000000038086e0_0 .net "X", 0 0, L_000000000396c830; alias, 1 drivers
+v000000000380a8a0_0 .net "xor0_out_X", 0 0, L_000000000396d5c0; 1 drivers
+S_00000000026c3300 .scope module, "sky130_fd_sc_hd__xor3_1" "sky130_fd_sc_hd__xor3_1" 4 86643;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379dcb8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003808b40_0 .net "A", 0 0, o000000000379dcb8; 0 drivers
+o000000000379dce8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809cc0_0 .net "B", 0 0, o000000000379dce8; 0 drivers
+o000000000379dd18 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000380a300_0 .net "C", 0 0, o000000000379dd18; 0 drivers
+L_000000000391add0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808dc0_0 .net8 "VGND", 0 0, L_000000000391add0; 1 drivers, strength-aware
+L_000000000391ac80 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808be0_0 .net8 "VNB", 0 0, L_000000000391ac80; 1 drivers, strength-aware
+L_000000000391b7e0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808c80_0 .net8 "VPB", 0 0, L_000000000391b7e0; 1 drivers, strength-aware
+L_000000000391b9a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808280_0 .net8 "VPWR", 0 0, L_000000000391b9a0; 1 drivers, strength-aware
+v000000000380a6c0_0 .net "X", 0 0, L_000000000396c520; 1 drivers
+S_000000000376f470 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86661, 4 86525 1, S_00000000026c3300;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396cd00 .functor XOR 1, o000000000379dcb8, o000000000379dce8, o000000000379dd18, C4<0>;
+L_000000000396c520 .functor BUF 1, L_000000000396cd00, C4<0>, C4<0>, C4<0>;
+v0000000003809220_0 .net "A", 0 0, o000000000379dcb8; alias, 0 drivers
+v00000000038092c0_0 .net "B", 0 0, o000000000379dce8; alias, 0 drivers
+v0000000003809a40_0 .net "C", 0 0, o000000000379dd18; alias, 0 drivers
+L_000000000391be70 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380a800_0 .net8 "VGND", 0 0, L_000000000391be70; 1 drivers, strength-aware
+L_000000000391b1c0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003808640_0 .net8 "VNB", 0 0, L_000000000391b1c0; 1 drivers, strength-aware
+L_000000000391b850 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003809ae0_0 .net8 "VPB", 0 0, L_000000000391b850; 1 drivers, strength-aware
+L_000000000391b930 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808d20_0 .net8 "VPWR", 0 0, L_000000000391b930; 1 drivers, strength-aware
+v0000000003808a00_0 .net "X", 0 0, L_000000000396c520; alias, 1 drivers
+v0000000003808320_0 .net "xor0_out_X", 0 0, L_000000000396cd00; 1 drivers
+S_00000000026bfd00 .scope module, "sky130_fd_sc_hd__xor3_2" "sky130_fd_sc_hd__xor3_2" 4 86757;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379e0a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809400_0 .net "A", 0 0, o000000000379e0a8; 0 drivers
+o000000000379e0d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0000000003809860_0 .net "B", 0 0, o000000000379e0d8; 0 drivers
+o000000000379e108 .functor BUFZ 1, C4<z>; HiZ drive
+v00000000038094a0_0 .net "C", 0 0, o000000000379e108; 0 drivers
+L_000000000391ba10 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380a1c0_0 .net8 "VGND", 0 0, L_000000000391ba10; 1 drivers, strength-aware
+L_000000000391b230 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003809900_0 .net8 "VNB", 0 0, L_000000000391b230; 1 drivers, strength-aware
+L_000000000391b2a0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003809d60_0 .net8 "VPB", 0 0, L_000000000391b2a0; 1 drivers, strength-aware
+L_000000000391bc40 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003808140_0 .net8 "VPWR", 0 0, L_000000000391bc40; 1 drivers, strength-aware
+v0000000003809e00_0 .net "X", 0 0, L_000000000396c3d0; 1 drivers
+S_000000000376f770 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86775, 4 86525 1, S_00000000026bfd00;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396c910 .functor XOR 1, o000000000379e0a8, o000000000379e0d8, o000000000379e108, C4<0>;
+L_000000000396c3d0 .functor BUF 1, L_000000000396c910, C4<0>, C4<0>, C4<0>;
+v0000000003809680_0 .net "A", 0 0, o000000000379e0a8; alias, 0 drivers
+v0000000003809720_0 .net "B", 0 0, o000000000379e0d8; alias, 0 drivers
+v00000000038097c0_0 .net "C", 0 0, o000000000379e108; alias, 0 drivers
+L_000000000391c260 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003809f40_0 .net8 "VGND", 0 0, L_000000000391c260; 1 drivers, strength-aware
+L_000000000391c2d0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v0000000003809fe0_0 .net8 "VNB", 0 0, L_000000000391c2d0; 1 drivers, strength-aware
+L_000000000391c420 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380a120_0 .net8 "VPB", 0 0, L_000000000391c420; 1 drivers, strength-aware
+L_000000000391ba80 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v0000000003809040_0 .net8 "VPWR", 0 0, L_000000000391ba80; 1 drivers, strength-aware
+v00000000038090e0_0 .net "X", 0 0, L_000000000396c3d0; alias, 1 drivers
+v0000000003809360_0 .net "xor0_out_X", 0 0, L_000000000396c910; 1 drivers
+S_00000000026c1380 .scope module, "sky130_fd_sc_hd__xor3_4" "sky130_fd_sc_hd__xor3_4" 4 86871;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+o000000000379e498 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000380c420_0 .net "A", 0 0, o000000000379e498; 0 drivers
+o000000000379e4c8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000380b200_0 .net "B", 0 0, o000000000379e4c8; 0 drivers
+o000000000379e4f8 .functor BUFZ 1, C4<z>; HiZ drive
+v000000000380c7e0_0 .net "C", 0 0, o000000000379e4f8; 0 drivers
+L_000000000391b380 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380c920_0 .net8 "VGND", 0 0, L_000000000391b380; 1 drivers, strength-aware
+L_000000000391bee0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380b840_0 .net8 "VNB", 0 0, L_000000000391bee0; 1 drivers, strength-aware
+L_000000000391af20 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380ba20_0 .net8 "VPB", 0 0, L_000000000391af20; 1 drivers, strength-aware
+L_000000000391b000 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380bf20_0 .net8 "VPWR", 0 0, L_000000000391b000; 1 drivers, strength-aware
+v000000000380c240_0 .net "X", 0 0, L_000000000396c130; 1 drivers
+S_000000000376f8f0 .scope module, "base" "sky130_fd_sc_hd__xor3" 4 86889, 4 86525 1, S_00000000026c1380;
+ .timescale -9 -12;
+ .port_info 0 /OUTPUT 1 "X"
+ .port_info 1 /INPUT 1 "A"
+ .port_info 2 /INPUT 1 "B"
+ .port_info 3 /INPUT 1 "C"
+L_000000000396d010 .functor XOR 1, o000000000379e498, o000000000379e4c8, o000000000379e4f8, C4<0>;
+L_000000000396c130 .functor BUF 1, L_000000000396d010, C4<0>, C4<0>, C4<0>;
+v0000000003809ea0_0 .net "A", 0 0, o000000000379e498; alias, 0 drivers
+v000000000380a080_0 .net "B", 0 0, o000000000379e4c8; alias, 0 drivers
+v000000000380a260_0 .net "C", 0 0, o000000000379e4f8; alias, 0 drivers
+L_000000000391bb60 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380a3a0_0 .net8 "VGND", 0 0, L_000000000391bb60; 1 drivers, strength-aware
+L_000000000391baf0 .functor BUFT 1, C8<770>, C4<0>, C4<0>, C4<0>;
+v000000000380a760_0 .net8 "VNB", 0 0, L_000000000391baf0; 1 drivers, strength-aware
+L_000000000391b070 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380a580_0 .net8 "VPB", 0 0, L_000000000391b070; 1 drivers, strength-aware
+L_000000000391bcb0 .functor BUFT 1, C8<771>, C4<0>, C4<0>, C4<0>;
+v000000000380a9e0_0 .net8 "VPWR", 0 0, L_000000000391bcb0; 1 drivers, strength-aware
+v000000000380cce0_0 .net "X", 0 0, L_000000000396c130; alias, 1 drivers
+v000000000380abc0_0 .net "xor0_out_X", 0 0, L_000000000396d010; 1 drivers
+ .scope S_000000000269ec20;
+T_0 ;
+ %pushi/vec4 1024, 0, 19;
+ %store/vec4 v00000000035308f0_0, 0, 19;
+ %delay 1316134912, 2328;
+ %pushi/vec4 65536, 0, 19;
+ %store/vec4 v00000000035308f0_0, 0, 19;
+ %delay 1316134912, 2328;
+ %pushi/vec4 123456, 0, 19;
+ %store/vec4 v00000000035308f0_0, 0, 19;
+ %delay 276447232, 23283;
+ %vpi_call 2 18 "$finish" {0 0 0};
+ %end;
+ .thread T_0;
+ .scope S_000000000269ec20;
+T_1 ;
+ %vpi_call 2 23 "$dumpfile", "fxd2float.vcd" {0 0 0};
+ %vpi_call 2 24 "$dumpvars", 32'sb00000000000000000000000000000000, S_000000000269ec20 {0 0 0};
+ %end;
+ .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+ "N/A";
+ "<interactive>";
+ "gls.v";
+ "fxd2flot.synthesis.v";
+ "sky130_fd_sc_hd.v";
diff --git a/Simulations/post_synthesis/fxd2float.vcd b/Simulations/post_synthesis/fxd2float.vcd
new file mode 100644
index 0000000..0da2b3a
--- /dev/null
+++ b/Simulations/post_synthesis/fxd2float.vcd
@@ -0,0 +1,6982 @@
+$date
+ Thu Oct 28 16:31:13 2021
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1ps
+$end
+$scope module gls $end
+$var wire 1 ! zro $end
+$var wire 32 " b [31:0] $end
+$var reg 19 # a [18:0] $end
+$scope module u1 $end
+$var wire 1 $ _003_ $end
+$var wire 19 % a [18:0] $end
+$var wire 1 ! zro $end
+$var wire 32 & b [31:0] $end
+$var wire 1 ' _187_ $end
+$var wire 1 ( _186_ $end
+$var wire 1 ) _185_ $end
+$var wire 1 * _184_ $end
+$var wire 1 + _183_ $end
+$var wire 1 , _182_ $end
+$var wire 1 - _181_ $end
+$var wire 1 . _180_ $end
+$var wire 1 / _179_ $end
+$var wire 1 0 _178_ $end
+$var wire 1 1 _177_ $end
+$var wire 1 2 _176_ $end
+$var wire 1 3 _175_ $end
+$var wire 1 4 _174_ $end
+$var wire 1 5 _173_ $end
+$var wire 1 6 _172_ $end
+$var wire 1 7 _171_ $end
+$var wire 1 8 _170_ $end
+$var wire 1 9 _169_ $end
+$var wire 1 : _168_ $end
+$var wire 1 ; _167_ $end
+$var wire 1 < _166_ $end
+$var wire 1 = _165_ $end
+$var wire 1 > _164_ $end
+$var wire 1 ? _163_ $end
+$var wire 1 @ _162_ $end
+$var wire 1 A _161_ $end
+$var wire 1 B _160_ $end
+$var wire 1 C _159_ $end
+$var wire 1 D _158_ $end
+$var wire 1 E _157_ $end
+$var wire 1 F _156_ $end
+$var wire 1 G _155_ $end
+$var wire 1 H _154_ $end
+$var wire 1 I _153_ $end
+$var wire 1 J _152_ $end
+$var wire 1 K _151_ $end
+$var wire 1 L _150_ $end
+$var wire 1 M _149_ $end
+$var wire 1 N _148_ $end
+$var wire 1 O _147_ $end
+$var wire 1 P _146_ $end
+$var wire 1 Q _145_ $end
+$var wire 1 R _144_ $end
+$var wire 1 S _143_ $end
+$var wire 1 T _142_ $end
+$var wire 1 U _141_ $end
+$var wire 1 V _140_ $end
+$var wire 1 W _139_ $end
+$var wire 1 X _138_ $end
+$var wire 1 Y _137_ $end
+$var wire 1 Z _136_ $end
+$var wire 1 [ _135_ $end
+$var wire 1 \ _134_ $end
+$var wire 1 ] _133_ $end
+$var wire 1 ^ _132_ $end
+$var wire 1 _ _131_ $end
+$var wire 1 ` _130_ $end
+$var wire 1 a _129_ $end
+$var wire 1 b _128_ $end
+$var wire 1 c _127_ $end
+$var wire 1 d _126_ $end
+$var wire 1 e _125_ $end
+$var wire 1 f _124_ $end
+$var wire 1 g _123_ $end
+$var wire 1 h _122_ $end
+$var wire 1 i _121_ $end
+$var wire 1 j _120_ $end
+$var wire 1 k _119_ $end
+$var wire 1 l _118_ $end
+$var wire 1 m _117_ $end
+$var wire 1 n _116_ $end
+$var wire 1 o _115_ $end
+$var wire 1 p _114_ $end
+$var wire 1 q _113_ $end
+$var wire 1 r _112_ $end
+$var wire 1 s _111_ $end
+$var wire 1 t _110_ $end
+$var wire 1 u _109_ $end
+$var wire 1 v _108_ $end
+$var wire 1 w _107_ $end
+$var wire 1 x _106_ $end
+$var wire 1 y _105_ $end
+$var wire 1 z _104_ $end
+$var wire 1 { _103_ $end
+$var wire 1 | _102_ $end
+$var wire 1 } _101_ $end
+$var wire 1 ~ _100_ $end
+$var wire 1 !" _099_ $end
+$var wire 1 "" _098_ $end
+$var wire 1 #" _097_ $end
+$var wire 1 $" _096_ $end
+$var wire 1 %" _095_ $end
+$var wire 1 &" _094_ $end
+$var wire 1 '" _093_ $end
+$var wire 1 (" _092_ $end
+$var wire 1 )" _091_ $end
+$var wire 1 *" _090_ $end
+$var wire 1 +" _089_ $end
+$var wire 1 ," _088_ $end
+$var wire 1 -" _087_ $end
+$var wire 1 ." _086_ $end
+$var wire 1 /" _085_ $end
+$var wire 1 0" _084_ $end
+$var wire 1 1" _083_ $end
+$var wire 1 2" _082_ $end
+$var wire 1 3" _081_ $end
+$var wire 1 4" _080_ $end
+$var wire 1 5" _079_ $end
+$var wire 1 6" _078_ $end
+$var wire 1 7" _077_ $end
+$var wire 1 8" _076_ $end
+$var wire 1 9" _075_ $end
+$var wire 1 :" _074_ $end
+$var wire 1 ;" _073_ $end
+$var wire 1 <" _072_ $end
+$var wire 1 =" _071_ $end
+$var wire 1 >" _070_ $end
+$var wire 1 ?" _069_ $end
+$var wire 1 @" _068_ $end
+$var wire 1 A" _067_ $end
+$var wire 1 B" _066_ $end
+$var wire 1 C" _065_ $end
+$var wire 1 D" _064_ $end
+$var wire 1 E" _063_ $end
+$var wire 1 F" _062_ $end
+$var wire 1 G" _061_ $end
+$var wire 1 H" _060_ $end
+$var wire 1 I" _059_ $end
+$var wire 1 J" _058_ $end
+$var wire 1 K" _057_ $end
+$var wire 1 L" _056_ $end
+$var wire 1 M" _055_ $end
+$var wire 1 N" _054_ $end
+$var wire 1 O" _053_ $end
+$var wire 1 P" _052_ $end
+$var wire 1 Q" _051_ $end
+$var wire 1 R" _050_ $end
+$var wire 1 S" _049_ $end
+$var wire 1 T" _048_ $end
+$var wire 1 U" _047_ $end
+$var wire 1 V" _046_ $end
+$var wire 1 W" _045_ $end
+$var wire 1 X" _044_ $end
+$var wire 1 Y" _043_ $end
+$var wire 1 Z" _042_ $end
+$var wire 1 [" _041_ $end
+$var wire 1 \" _040_ $end
+$var wire 1 ]" _039_ $end
+$var wire 1 ^" _038_ $end
+$var wire 1 _" _037_ $end
+$var wire 1 `" _036_ $end
+$var wire 1 a" _035_ $end
+$var wire 1 b" _034_ $end
+$var wire 1 c" _033_ $end
+$var wire 1 d" _032_ $end
+$var wire 1 e" _031_ $end
+$var wire 1 f" _030_ $end
+$var wire 1 g" _029_ $end
+$var wire 1 h" _028_ $end
+$var wire 1 i" _027_ $end
+$var wire 1 j" _026_ $end
+$var wire 1 k" _025_ $end
+$var wire 1 l" _024_ $end
+$var wire 1 m" _023_ $end
+$var wire 1 n" _022_ $end
+$var wire 1 o" _021_ $end
+$var wire 1 p" _020_ $end
+$var wire 1 q" _019_ $end
+$var wire 1 r" _018_ $end
+$var wire 1 s" _017_ $end
+$var wire 1 t" _016_ $end
+$var wire 1 u" _015_ $end
+$var wire 1 v" _014_ $end
+$var wire 1 w" _013_ $end
+$var wire 1 x" _012_ $end
+$var wire 1 y" _011_ $end
+$var wire 1 z" _010_ $end
+$var wire 1 {" _009_ $end
+$var wire 1 |" _008_ $end
+$var wire 1 }" _007_ $end
+$var wire 1 ~" _006_ $end
+$var wire 1 !# _005_ $end
+$var wire 1 "# _004_ $end
+$var wire 1 ## _002_ $end
+$var wire 1 $# _001_ $end
+$var wire 1 %# _000_ $end
+$scope module _188_ $end
+$var wire 1 &# A $end
+$var wire 1 '# B $end
+$var wire 1 (# VGND $end
+$var wire 1 )# VNB $end
+$var wire 1 *# VPB $end
+$var wire 1 +# VPWR $end
+$var wire 1 n X $end
+$scope module base $end
+$var wire 1 &# A $end
+$var wire 1 '# B $end
+$var wire 1 ,# VGND $end
+$var wire 1 -# VNB $end
+$var wire 1 .# VPB $end
+$var wire 1 /# VPWR $end
+$var wire 1 n X $end
+$var wire 1 0# or0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _189_ $end
+$var wire 1 1# A $end
+$var wire 1 2# VGND $end
+$var wire 1 3# VNB $end
+$var wire 1 4# VPB $end
+$var wire 1 5# VPWR $end
+$var wire 1 N" Y $end
+$scope module base $end
+$var wire 1 1# A $end
+$var wire 1 6# VGND $end
+$var wire 1 7# VNB $end
+$var wire 1 8# VPB $end
+$var wire 1 9# VPWR $end
+$var wire 1 N" Y $end
+$var wire 1 :# not0_out_Y $end
+$upscope $end
+$upscope $end
+$scope module _190_ $end
+$var wire 1 ;# A $end
+$var wire 1 <# VGND $end
+$var wire 1 =# VNB $end
+$var wire 1 ># VPB $end
+$var wire 1 ?# VPWR $end
+$var wire 1 v Y $end
+$scope module base $end
+$var wire 1 ;# A $end
+$var wire 1 @# VGND $end
+$var wire 1 A# VNB $end
+$var wire 1 B# VPB $end
+$var wire 1 C# VPWR $end
+$var wire 1 v Y $end
+$var wire 1 D# not0_out_Y $end
+$upscope $end
+$upscope $end
+$scope module _191_ $end
+$var wire 1 E# A $end
+$var wire 1 F# B $end
+$var wire 1 G# VGND $end
+$var wire 1 H# VNB $end
+$var wire 1 I# VPB $end
+$var wire 1 J# VPWR $end
+$var wire 1 #" Y $end
+$scope module base $end
+$var wire 1 E# A $end
+$var wire 1 F# B $end
+$var wire 1 K# VGND $end
+$var wire 1 L# VNB $end
+$var wire 1 M# VPB $end
+$var wire 1 N# VPWR $end
+$var wire 1 #" Y $end
+$var wire 1 O# nor0_out_Y $end
+$upscope $end
+$upscope $end
+$scope module _192_ $end
+$var wire 1 N" A $end
+$var wire 1 v B $end
+$var wire 1 #" C $end
+$var wire 1 P# VGND $end
+$var wire 1 Q# VNB $end
+$var wire 1 R# VPB $end
+$var wire 1 S# VPWR $end
+$var wire 1 "" X $end
+$scope module base $end
+$var wire 1 N" A $end
+$var wire 1 v B $end
+$var wire 1 #" C $end
+$var wire 1 T# VGND $end
+$var wire 1 U# VNB $end
+$var wire 1 V# VPB $end
+$var wire 1 W# VPWR $end
+$var wire 1 "" X $end
+$var wire 1 X# and0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _193_ $end
+$var wire 1 Y# A $end
+$var wire 1 Z# B $end
+$var wire 1 n C $end
+$var wire 1 "" D_N $end
+$var wire 1 [# VGND $end
+$var wire 1 \# VNB $end
+$var wire 1 ]# VPB $end
+$var wire 1 ^# VPWR $end
+$var wire 1 m X $end
+$scope module base $end
+$var wire 1 Y# A $end
+$var wire 1 Z# B $end
+$var wire 1 n C $end
+$var wire 1 "" D_N $end
+$var wire 1 _# VGND $end
+$var wire 1 `# VNB $end
+$var wire 1 a# VPB $end
+$var wire 1 b# VPWR $end
+$var wire 1 m X $end
+$var wire 1 c# not0_out $end
+$var wire 1 d# or0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _194_ $end
+$var wire 1 e# A $end
+$var wire 1 f# B $end
+$var wire 1 g# VGND $end
+$var wire 1 h# VNB $end
+$var wire 1 i# VPB $end
+$var wire 1 j# VPWR $end
+$var wire 1 l X $end
+$scope module base $end
+$var wire 1 e# A $end
+$var wire 1 f# B $end
+$var wire 1 k# VGND $end
+$var wire 1 l# VNB $end
+$var wire 1 m# VPB $end
+$var wire 1 n# VPWR $end
+$var wire 1 l X $end
+$var wire 1 o# or0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _195_ $end
+$var wire 1 m A $end
+$var wire 1 l B $end
+$var wire 1 p# VGND $end
+$var wire 1 q# VNB $end
+$var wire 1 r# VPB $end
+$var wire 1 s# VPWR $end
+$var wire 1 k X $end
+$scope module base $end
+$var wire 1 m A $end
+$var wire 1 l B $end
+$var wire 1 t# VGND $end
+$var wire 1 u# VNB $end
+$var wire 1 v# VPB $end
+$var wire 1 w# VPWR $end
+$var wire 1 k X $end
+$var wire 1 x# or0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _196_ $end
+$var wire 1 k A $end
+$var wire 1 y# VGND $end
+$var wire 1 z# VNB $end
+$var wire 1 {# VPB $end
+$var wire 1 |# VPWR $end
+$var wire 1 m" X $end
+$scope module base $end
+$var wire 1 k A $end
+$var wire 1 }# VGND $end
+$var wire 1 ~# VNB $end
+$var wire 1 !$ VPB $end
+$var wire 1 "$ VPWR $end
+$var wire 1 m" X $end
+$var wire 1 #$ buf0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _197_ $end
+$var wire 1 m" A $end
+$var wire 1 $$ VGND $end
+$var wire 1 %$ VNB $end
+$var wire 1 &$ VPB $end
+$var wire 1 '$ VPWR $end
+$var wire 1 j Y $end
+$scope module base $end
+$var wire 1 m" A $end
+$var wire 1 ($ VGND $end
+$var wire 1 )$ VNB $end
+$var wire 1 *$ VPB $end
+$var wire 1 +$ VPWR $end
+$var wire 1 j Y $end
+$var wire 1 ,$ not0_out_Y $end
+$upscope $end
+$upscope $end
+$scope module _198_ $end
+$var wire 1 j A $end
+$var wire 1 -$ VGND $end
+$var wire 1 .$ VNB $end
+$var wire 1 /$ VPB $end
+$var wire 1 0$ VPWR $end
+$var wire 1 i X $end
+$scope module base $end
+$var wire 1 j A $end
+$var wire 1 1$ VGND $end
+$var wire 1 2$ VNB $end
+$var wire 1 3$ VPB $end
+$var wire 1 4$ VPWR $end
+$var wire 1 i X $end
+$var wire 1 5$ buf0_out_X $end
+$upscope $end
+$upscope $end
+$scope module _199_ $end
+$var wire 1 i B $end
+$var wire 1 6$ VGND $end
+$var wire 1 7$ VNB $end
+$var wire 1 8$ VPB $end
+$var wire 1 9$ VPWR $end
+$var wire 1 :$ Y $end
+$var wire 1 V" A $end
+$scope module base $end
+$var wire 1 i B $end
+$var wire 1 ;$ VGND $end
+$var wire 1 <$ VNB $end
+$var wire 1 =$ VPB $end
+$var wire 1 >$ VPWR $end
+$var wire 1 :$ Y $end
+$var wire 1 ?$ nor0_out_Y $end
+$var wire 1 V" A $end
+$upscope $end
+$upscope $end
+$scope module _200_ $end
+$var wire 1 i B $end
+$var wire 1 @$ VGND $end
+$var wire 1 A$ VNB $end
+$var wire 1 B$ VPB $end
+$var wire 1 C$ VPWR $end
+$var wire 1 D$ Y $end
+$var wire 1 T" A $end
+$scope module base $end
+$var wire 1 i B $end
+$var wire 1 E$ VGND $end
+$var wire 1 F$ VNB $end
+$var wire 1 G$ VPB $end
+$var wire 1 H$ VPWR $end
+$var wire 1 D$ Y $end
+$var wire 1 I$ nor0_out_Y $end
+$var wire 1 T" A $end
+$upscope $end
+$upscope $end
+$scope module _201_ $end
+$var wire 1 J$ A $end
+$var wire 1 K$ VGND $end
+$var wire 1 L$ VNB $end
+$var wire 1 M$ VPB $end
+$var wire 1 N$ VPWR $end
+$var wire 1 S" Y $end
+$scope module base $end
+$var wire 1 J$ A $end
+$var wire 1 O$ VGND $end
+$var wire 1 P$ VNB $end
+$var wire 1 Q$ VPB $end
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diff --git a/Simulations/post_synthesis/fxd2flot.synthesis.v b/Simulations/post_synthesis/fxd2flot.synthesis.v
new file mode 100644
index 0000000..9b4344a
--- /dev/null
+++ b/Simulations/post_synthesis/fxd2flot.synthesis.v
@@ -0,0 +1,1341 @@
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+
+module fxd2flot(a, b, zro);
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ input [18:0] a;
+ output [31:0] b;
+ output zro;
+ sky130_fd_sc_hd__or2_2 _188_ (
+ .A(a[10]),
+ .B(a[11]),
+ .X(_116_)
+ );
+ sky130_fd_sc_hd__inv_2 _189_ (
+ .A(a[12]),
+ .Y(_054_)
+ );
+ sky130_fd_sc_hd__inv_2 _190_ (
+ .A(a[13]),
+ .Y(_108_)
+ );
+ sky130_fd_sc_hd__nor2_2 _191_ (
+ .A(a[14]),
+ .B(a[15]),
+ .Y(_097_)
+ );
+ sky130_fd_sc_hd__and3_2 _192_ (
+ .A(_054_),
+ .B(_108_),
+ .C(_097_),
+ .X(_098_)
+ );
+ sky130_fd_sc_hd__or4b_2 _193_ (
+ .A(a[9]),
+ .B(a[8]),
+ .C(_116_),
+ .D_N(_098_),
+ .X(_117_)
+ );
+ sky130_fd_sc_hd__or2_2 _194_ (
+ .A(a[16]),
+ .B(a[17]),
+ .X(_118_)
+ );
+ sky130_fd_sc_hd__or2_2 _195_ (
+ .A(_117_),
+ .B(_118_),
+ .X(_119_)
+ );
+ sky130_fd_sc_hd__buf_1 _196_ (
+ .A(_119_),
+ .X(_023_)
+ );
+ sky130_fd_sc_hd__inv_2 _197_ (
+ .A(_023_),
+ .Y(_120_)
+ );
+ sky130_fd_sc_hd__buf_1 _198_ (
+ .A(_120_),
+ .X(_121_)
+ );
+ sky130_fd_sc_hd__nor2_2 _199_ (
+ .A(_046_),
+ .B(_121_),
+ .Y(b[8])
+ );
+ sky130_fd_sc_hd__nor2_2 _200_ (
+ .A(_048_),
+ .B(_121_),
+ .Y(b[9])
+ );
+ sky130_fd_sc_hd__inv_2 _201_ (
+ .A(a[10]),
+ .Y(_049_)
+ );
+ sky130_fd_sc_hd__nor2_2 _202_ (
+ .A(_051_),
+ .B(_121_),
+ .Y(b[10])
+ );
+ sky130_fd_sc_hd__nor2_2 _203_ (
+ .A(_053_),
+ .B(_121_),
+ .Y(b[11])
+ );
+ sky130_fd_sc_hd__nor2_2 _204_ (
+ .A(_057_),
+ .B(_121_),
+ .Y(b[12])
+ );
+ sky130_fd_sc_hd__nor2_2 _205_ (
+ .A(_060_),
+ .B(_120_),
+ .Y(b[13])
+ );
+ sky130_fd_sc_hd__inv_2 _206_ (
+ .A(a[14]),
+ .Y(_061_)
+ );
+ sky130_fd_sc_hd__nor2_2 _207_ (
+ .A(_065_),
+ .B(_120_),
+ .Y(b[14])
+ );
+ sky130_fd_sc_hd__nor2_2 _208_ (
+ .A(_067_),
+ .B(_120_),
+ .Y(b[15])
+ );
+ sky130_fd_sc_hd__inv_2 _209_ (
+ .A(_045_),
+ .Y(_068_)
+ );
+ sky130_fd_sc_hd__inv_2 _210_ (
+ .A(_055_),
+ .Y(_069_)
+ );
+ sky130_fd_sc_hd__inv_2 _211_ (
+ .A(_062_),
+ .Y(_070_)
+ );
+ sky130_fd_sc_hd__inv_2 _212_ (
+ .A(a[16]),
+ .Y(_071_)
+ );
+ sky130_fd_sc_hd__inv_2 _213_ (
+ .A(_072_),
+ .Y(_073_)
+ );
+ sky130_fd_sc_hd__inv_2 _214_ (
+ .A(_047_),
+ .Y(_074_)
+ );
+ sky130_fd_sc_hd__inv_2 _215_ (
+ .A(_058_),
+ .Y(_075_)
+ );
+ sky130_fd_sc_hd__buf_1 _216_ (
+ .A(_118_),
+ .X(_086_)
+ );
+ sky130_fd_sc_hd__inv_2 _217_ (
+ .A(_086_),
+ .Y(_122_)
+ );
+ sky130_fd_sc_hd__buf_1 _218_ (
+ .A(_122_),
+ .X(_076_)
+ );
+ sky130_fd_sc_hd__inv_2 _219_ (
+ .A(_077_),
+ .Y(_078_)
+ );
+ sky130_fd_sc_hd__inv_2 _220_ (
+ .A(_050_),
+ .Y(_079_)
+ );
+ sky130_fd_sc_hd__inv_2 _221_ (
+ .A(_063_),
+ .Y(_080_)
+ );
+ sky130_fd_sc_hd__inv_2 _222_ (
+ .A(a[17]),
+ .Y(_100_)
+ );
+ sky130_fd_sc_hd__inv_2 _223_ (
+ .A(_110_),
+ .Y(_123_)
+ );
+ sky130_fd_sc_hd__or2_2 _224_ (
+ .A(_100_),
+ .B(_123_),
+ .X(_081_)
+ );
+ sky130_fd_sc_hd__inv_2 _225_ (
+ .A(_082_),
+ .Y(_083_)
+ );
+ sky130_fd_sc_hd__inv_2 _226_ (
+ .A(_052_),
+ .Y(_084_)
+ );
+ sky130_fd_sc_hd__inv_2 _227_ (
+ .A(_066_),
+ .Y(_085_)
+ );
+ sky130_fd_sc_hd__inv_2 _228_ (
+ .A(_056_),
+ .Y(_087_)
+ );
+ sky130_fd_sc_hd__or2_2 _229_ (
+ .A(_113_),
+ .B(_086_),
+ .X(_124_)
+ );
+ sky130_fd_sc_hd__buf_1 _230_ (
+ .A(_124_),
+ .X(_114_)
+ );
+ sky130_fd_sc_hd__inv_2 _231_ (
+ .A(_114_),
+ .Y(_001_)
+ );
+ sky130_fd_sc_hd__inv_2 _232_ (
+ .A(_081_),
+ .Y(_088_)
+ );
+ sky130_fd_sc_hd__inv_2 _233_ (
+ .A(_059_),
+ .Y(_089_)
+ );
+ sky130_fd_sc_hd__or2_2 _234_ (
+ .A(_103_),
+ .B(_086_),
+ .X(_125_)
+ );
+ sky130_fd_sc_hd__inv_2 _235_ (
+ .A(_125_),
+ .Y(_112_)
+ );
+ sky130_fd_sc_hd__nor2_2 _236_ (
+ .A(_077_),
+ .B(_112_),
+ .Y(_090_)
+ );
+ sky130_fd_sc_hd__inv_2 _237_ (
+ .A(_064_),
+ .Y(_091_)
+ );
+ sky130_fd_sc_hd__nor2_2 _238_ (
+ .A(_082_),
+ .B(_112_),
+ .Y(_092_)
+ );
+ sky130_fd_sc_hd__or2_2 _239_ (
+ .A(a[3]),
+ .B(a[2]),
+ .X(_126_)
+ );
+ sky130_fd_sc_hd__inv_2 _240_ (
+ .A(_126_),
+ .Y(_093_)
+ );
+ sky130_fd_sc_hd__nor2_2 _241_ (
+ .A(a[7]),
+ .B(a[6]),
+ .Y(_094_)
+ );
+ sky130_fd_sc_hd__inv_2 _242_ (
+ .A(a[5]),
+ .Y(_104_)
+ );
+ sky130_fd_sc_hd__inv_2 _243_ (
+ .A(a[4]),
+ .Y(_035_)
+ );
+ sky130_fd_sc_hd__and3_2 _244_ (
+ .A(_104_),
+ .B(_035_),
+ .C(_094_),
+ .X(_095_)
+ );
+ sky130_fd_sc_hd__inv_2 _245_ (
+ .A(_116_),
+ .Y(_096_)
+ );
+ sky130_fd_sc_hd__inv_2 _246_ (
+ .A(_117_),
+ .Y(_099_)
+ );
+ sky130_fd_sc_hd__or4_2 _247_ (
+ .A(a[1]),
+ .B(a[0]),
+ .C(_118_),
+ .D(_126_),
+ .X(_127_)
+ );
+ sky130_fd_sc_hd__or3b_2 _248_ (
+ .A(_117_),
+ .B(_127_),
+ .C_N(_095_),
+ .X(_128_)
+ );
+ sky130_fd_sc_hd__buf_1 _249_ (
+ .A(_128_),
+ .X(zro)
+ );
+ sky130_fd_sc_hd__inv_2 _250_ (
+ .A(zro),
+ .Y(_015_)
+ );
+ sky130_fd_sc_hd__inv_2 _251_ (
+ .A(a[1]),
+ .Y(_101_)
+ );
+ sky130_fd_sc_hd__inv_2 _252_ (
+ .A(a[3]),
+ .Y(_102_)
+ );
+ sky130_fd_sc_hd__inv_2 _253_ (
+ .A(a[7]),
+ .Y(_105_)
+ );
+ sky130_fd_sc_hd__inv_2 _254_ (
+ .A(a[9]),
+ .Y(_106_)
+ );
+ sky130_fd_sc_hd__inv_2 _255_ (
+ .A(a[11]),
+ .Y(_107_)
+ );
+ sky130_fd_sc_hd__inv_2 _256_ (
+ .A(a[15]),
+ .Y(_109_)
+ );
+ sky130_fd_sc_hd__inv_2 _257_ (
+ .A(a[8]),
+ .Y(_044_)
+ );
+ sky130_fd_sc_hd__or2_2 _258_ (
+ .A(_099_),
+ .B(_086_),
+ .X(_129_)
+ );
+ sky130_fd_sc_hd__inv_2 _259_ (
+ .A(_129_),
+ .Y(_130_)
+ );
+ sky130_fd_sc_hd__buf_1 _260_ (
+ .A(_130_),
+ .X(_111_)
+ );
+ sky130_fd_sc_hd__or2_2 _261_ (
+ .A(_123_),
+ .B(_015_),
+ .X(_131_)
+ );
+ sky130_fd_sc_hd__inv_2 _262_ (
+ .A(_131_),
+ .Y(b[23])
+ );
+ sky130_fd_sc_hd__nor2_2 _263_ (
+ .A(_001_),
+ .B(_131_),
+ .Y(_115_)
+ );
+ sky130_fd_sc_hd__buf_1 _264_ (
+ .A(_002_),
+ .X(_132_)
+ );
+ sky130_fd_sc_hd__nor2_2 _265_ (
+ .A(_132_),
+ .B(_131_),
+ .Y(_133_)
+ );
+ sky130_fd_sc_hd__a21o_2 _266_ (
+ .A1(_132_),
+ .A2(_131_),
+ .B1(_133_),
+ .X(_004_)
+ );
+ sky130_fd_sc_hd__inv_2 _267_ (
+ .A(_000_),
+ .Y(_134_)
+ );
+ sky130_fd_sc_hd__or3_2 _268_ (
+ .A(_000_),
+ .B(_002_),
+ .C(_131_),
+ .X(_135_)
+ );
+ sky130_fd_sc_hd__o21ai_2 _269_ (
+ .A1(_134_),
+ .A2(_133_),
+ .B1(_135_),
+ .Y(_005_)
+ );
+ sky130_fd_sc_hd__inv_2 _270_ (
+ .A(_132_),
+ .Y(_136_)
+ );
+ sky130_fd_sc_hd__o22a_2 _271_ (
+ .A1(_000_),
+ .A2(_132_),
+ .B1(_134_),
+ .B2(_136_),
+ .X(_006_)
+ );
+ sky130_fd_sc_hd__inv_2 _272_ (
+ .A(_135_),
+ .Y(_137_)
+ );
+ sky130_fd_sc_hd__a22o_2 _273_ (
+ .A1(_129_),
+ .A2(_137_),
+ .B1(_130_),
+ .B2(_135_),
+ .X(_007_)
+ );
+ sky130_fd_sc_hd__or3_2 _274_ (
+ .A(_000_),
+ .B(_132_),
+ .C(b[23]),
+ .X(_138_)
+ );
+ sky130_fd_sc_hd__nor2_2 _275_ (
+ .A(_130_),
+ .B(_138_),
+ .Y(_139_)
+ );
+ sky130_fd_sc_hd__a21oi_2 _276_ (
+ .A1(_007_),
+ .A2(_138_),
+ .B1(_139_),
+ .Y(_008_)
+ );
+ sky130_fd_sc_hd__or2_2 _277_ (
+ .A(_023_),
+ .B(_135_),
+ .X(_140_)
+ );
+ sky130_fd_sc_hd__o21ai_2 _278_ (
+ .A1(_122_),
+ .A2(_137_),
+ .B1(_140_),
+ .Y(_009_)
+ );
+ sky130_fd_sc_hd__inv_2 _279_ (
+ .A(_009_),
+ .Y(_141_)
+ );
+ sky130_fd_sc_hd__or3_2 _280_ (
+ .A(_000_),
+ .B(_002_),
+ .C(_023_),
+ .X(_142_)
+ );
+ sky130_fd_sc_hd__buf_1 _281_ (
+ .A(_142_),
+ .X(_012_)
+ );
+ sky130_fd_sc_hd__o22a_2 _282_ (
+ .A1(_139_),
+ .A2(_141_),
+ .B1(b[23]),
+ .B2(_012_),
+ .X(_010_)
+ );
+ sky130_fd_sc_hd__inv_2 _283_ (
+ .A(_140_),
+ .Y(_011_)
+ );
+ sky130_fd_sc_hd__buf_1 _284_ (
+ .A(_011_),
+ .X(_013_)
+ );
+ sky130_fd_sc_hd__buf_1 _285_ (
+ .A(_012_),
+ .X(_014_)
+ );
+ sky130_fd_sc_hd__nor2_2 _286_ (
+ .A(_015_),
+ .B(_011_),
+ .Y(_016_)
+ );
+ sky130_fd_sc_hd__inv_2 _287_ (
+ .A(_012_),
+ .Y(_143_)
+ );
+ sky130_fd_sc_hd__o32a_2 _288_ (
+ .A1(b[23]),
+ .A2(_012_),
+ .A3(zro),
+ .B1(_015_),
+ .B2(_143_),
+ .X(_017_)
+ );
+ sky130_fd_sc_hd__inv_2 _289_ (
+ .A(a[0]),
+ .Y(_018_)
+ );
+ sky130_fd_sc_hd__or2_2 _290_ (
+ .A(_110_),
+ .B(_018_),
+ .X(_019_)
+ );
+ sky130_fd_sc_hd__or2_2 _291_ (
+ .A(_114_),
+ .B(_019_),
+ .X(_020_)
+ );
+ sky130_fd_sc_hd__or2_2 _292_ (
+ .A(_103_),
+ .B(_020_),
+ .X(_144_)
+ );
+ sky130_fd_sc_hd__buf_1 _293_ (
+ .A(_144_),
+ .X(_021_)
+ );
+ sky130_fd_sc_hd__nor2_2 _294_ (
+ .A(_111_),
+ .B(_021_),
+ .Y(_022_)
+ );
+ sky130_fd_sc_hd__or2_2 _295_ (
+ .A(_024_),
+ .B(_114_),
+ .X(_025_)
+ );
+ sky130_fd_sc_hd__or2_2 _296_ (
+ .A(_103_),
+ .B(_025_),
+ .X(_145_)
+ );
+ sky130_fd_sc_hd__buf_1 _297_ (
+ .A(_145_),
+ .X(_026_)
+ );
+ sky130_fd_sc_hd__nor2_2 _298_ (
+ .A(_130_),
+ .B(_026_),
+ .Y(_027_)
+ );
+ sky130_fd_sc_hd__inv_2 _299_ (
+ .A(a[2]),
+ .Y(_028_)
+ );
+ sky130_fd_sc_hd__or2_2 _300_ (
+ .A(_029_),
+ .B(_125_),
+ .X(_146_)
+ );
+ sky130_fd_sc_hd__buf_1 _301_ (
+ .A(_146_),
+ .X(_030_)
+ );
+ sky130_fd_sc_hd__nor2_2 _302_ (
+ .A(_117_),
+ .B(_030_),
+ .Y(_031_)
+ );
+ sky130_fd_sc_hd__or2_2 _303_ (
+ .A(_032_),
+ .B(_125_),
+ .X(_147_)
+ );
+ sky130_fd_sc_hd__buf_1 _304_ (
+ .A(_147_),
+ .X(_033_)
+ );
+ sky130_fd_sc_hd__nor2_2 _305_ (
+ .A(_117_),
+ .B(_033_),
+ .Y(_034_)
+ );
+ sky130_fd_sc_hd__nor2_2 _306_ (
+ .A(_036_),
+ .B(_111_),
+ .Y(_037_)
+ );
+ sky130_fd_sc_hd__nor2_2 _307_ (
+ .A(_036_),
+ .B(_076_),
+ .Y(b[4])
+ );
+ sky130_fd_sc_hd__nor2_2 _308_ (
+ .A(_038_),
+ .B(_111_),
+ .Y(_039_)
+ );
+ sky130_fd_sc_hd__nor2_2 _309_ (
+ .A(_038_),
+ .B(_076_),
+ .Y(b[5])
+ );
+ sky130_fd_sc_hd__inv_2 _310_ (
+ .A(a[6]),
+ .Y(_040_)
+ );
+ sky130_fd_sc_hd__nor2_2 _311_ (
+ .A(_041_),
+ .B(_111_),
+ .Y(_042_)
+ );
+ sky130_fd_sc_hd__nor2_2 _312_ (
+ .A(_041_),
+ .B(_076_),
+ .Y(b[6])
+ );
+ sky130_fd_sc_hd__nor2_2 _313_ (
+ .A(_043_),
+ .B(_076_),
+ .Y(b[7])
+ );
+ sky130_fd_sc_hd__conb_1 _314_ (
+ .HI(_003_)
+ );
+ sky130_fd_sc_hd__conb_1 _315_ (
+ .LO(b[3])
+ );
+ sky130_fd_sc_hd__conb_1 _316_ (
+ .LO(b[2])
+ );
+ sky130_fd_sc_hd__conb_1 _317_ (
+ .LO(b[1])
+ );
+ sky130_fd_sc_hd__conb_1 _318_ (
+ .LO(b[0])
+ );
+ sky130_fd_sc_hd__buf_2 _319_ (
+ .A(a[18]),
+ .X(b[31])
+ );
+ sky130_fd_sc_hd__mux2_1 _320_ (
+ .A0(_069_),
+ .A1(_170_),
+ .S(_112_),
+ .X(_171_)
+ );
+ sky130_fd_sc_hd__mux2_1 _321_ (
+ .A0(_171_),
+ .A1(_068_),
+ .S(_111_),
+ .X(_172_)
+ );
+ sky130_fd_sc_hd__mux2_1 _322_ (
+ .A0(_022_),
+ .A1(_172_),
+ .S(_023_),
+ .X(b[16])
+ );
+ sky130_fd_sc_hd__mux2_1 _323_ (
+ .A0(_075_),
+ .A1(_078_),
+ .S(_112_),
+ .X(_173_)
+ );
+ sky130_fd_sc_hd__mux2_1 _324_ (
+ .A0(_173_),
+ .A1(_074_),
+ .S(_111_),
+ .X(_174_)
+ );
+ sky130_fd_sc_hd__mux2_1 _325_ (
+ .A0(_027_),
+ .A1(_174_),
+ .S(_023_),
+ .X(b[17])
+ );
+ sky130_fd_sc_hd__mux2_1 _326_ (
+ .A0(_080_),
+ .A1(_083_),
+ .S(_112_),
+ .X(_175_)
+ );
+ sky130_fd_sc_hd__mux2_1 _327_ (
+ .A0(_175_),
+ .A1(_079_),
+ .S(_111_),
+ .X(_176_)
+ );
+ sky130_fd_sc_hd__mux2_1 _328_ (
+ .A0(_031_),
+ .A1(_176_),
+ .S(_023_),
+ .X(b[18])
+ );
+ sky130_fd_sc_hd__mux2_1 _329_ (
+ .A0(_085_),
+ .A1(_086_),
+ .S(_112_),
+ .X(_177_)
+ );
+ sky130_fd_sc_hd__mux2_1 _330_ (
+ .A0(_177_),
+ .A1(_084_),
+ .S(_111_),
+ .X(_178_)
+ );
+ sky130_fd_sc_hd__mux2_1 _331_ (
+ .A0(_034_),
+ .A1(_178_),
+ .S(_023_),
+ .X(b[19])
+ );
+ sky130_fd_sc_hd__mux2_1 _332_ (
+ .A0(_170_),
+ .A1(_088_),
+ .S(_112_),
+ .X(_179_)
+ );
+ sky130_fd_sc_hd__mux2_1 _333_ (
+ .A0(_179_),
+ .A1(_087_),
+ .S(_111_),
+ .X(_180_)
+ );
+ sky130_fd_sc_hd__mux2_1 _334_ (
+ .A0(_037_),
+ .A1(_180_),
+ .S(_023_),
+ .X(b[20])
+ );
+ sky130_fd_sc_hd__mux2_1 _335_ (
+ .A0(_090_),
+ .A1(_089_),
+ .S(_111_),
+ .X(_181_)
+ );
+ sky130_fd_sc_hd__mux2_1 _336_ (
+ .A0(_039_),
+ .A1(_181_),
+ .S(_023_),
+ .X(b[21])
+ );
+ sky130_fd_sc_hd__mux2_1 _337_ (
+ .A0(_092_),
+ .A1(_091_),
+ .S(_111_),
+ .X(_182_)
+ );
+ sky130_fd_sc_hd__mux2_1 _338_ (
+ .A0(_042_),
+ .A1(_182_),
+ .S(_023_),
+ .X(b[22])
+ );
+ sky130_fd_sc_hd__mux2_1 _339_ (
+ .A0(_002_),
+ .A1(_004_),
+ .S(_003_),
+ .X(b[24])
+ );
+ sky130_fd_sc_hd__mux2_1 _340_ (
+ .A0(_006_),
+ .A1(_005_),
+ .S(_003_),
+ .X(b[25])
+ );
+ sky130_fd_sc_hd__mux2_1 _341_ (
+ .A0(_008_),
+ .A1(_007_),
+ .S(_003_),
+ .X(b[26])
+ );
+ sky130_fd_sc_hd__mux2_1 _342_ (
+ .A0(_010_),
+ .A1(_009_),
+ .S(_003_),
+ .X(b[27])
+ );
+ sky130_fd_sc_hd__mux2_1 _343_ (
+ .A0(_012_),
+ .A1(_011_),
+ .S(_003_),
+ .X(b[28])
+ );
+ sky130_fd_sc_hd__mux2_1 _344_ (
+ .A0(_014_),
+ .A1(_013_),
+ .S(_003_),
+ .X(b[29])
+ );
+ sky130_fd_sc_hd__mux2_1 _345_ (
+ .A0(_017_),
+ .A1(_016_),
+ .S(_003_),
+ .X(b[30])
+ );
+ sky130_fd_sc_hd__mux2_1 _346_ (
+ .A0(_109_),
+ .A1(_108_),
+ .S(_097_),
+ .X(_186_)
+ );
+ sky130_fd_sc_hd__mux2_1 _347_ (
+ .A0(_107_),
+ .A1(_106_),
+ .S(_096_),
+ .X(_185_)
+ );
+ sky130_fd_sc_hd__mux2_1 _348_ (
+ .A0(_105_),
+ .A1(_104_),
+ .S(_094_),
+ .X(_184_)
+ );
+ sky130_fd_sc_hd__mux2_1 _349_ (
+ .A0(_102_),
+ .A1(_101_),
+ .S(_093_),
+ .X(_183_)
+ );
+ sky130_fd_sc_hd__mux2_1 _350_ (
+ .A0(_187_),
+ .A1(_100_),
+ .S(_086_),
+ .X(_110_)
+ );
+ sky130_fd_sc_hd__mux2_1 _351_ (
+ .A0(_101_),
+ .A1(_018_),
+ .S(_110_),
+ .X(_024_)
+ );
+ sky130_fd_sc_hd__mux2_1 _352_ (
+ .A0(_154_),
+ .A1(_150_),
+ .S(_114_),
+ .X(_155_)
+ );
+ sky130_fd_sc_hd__mux2_1 _353_ (
+ .A0(_054_),
+ .A1(_107_),
+ .S(_110_),
+ .X(_166_)
+ );
+ sky130_fd_sc_hd__mux2_1 _354_ (
+ .A0(_166_),
+ .A1(_162_),
+ .S(_114_),
+ .X(_055_)
+ );
+ sky130_fd_sc_hd__mux2_1 _355_ (
+ .A0(_098_),
+ .A1(_095_),
+ .S(_099_),
+ .X(_103_)
+ );
+ sky130_fd_sc_hd__mux2_1 _356_ (
+ .A0(_045_),
+ .A1(_021_),
+ .S(_111_),
+ .X(_046_)
+ );
+ sky130_fd_sc_hd__mux2_1 _357_ (
+ .A0(_047_),
+ .A1(_026_),
+ .S(_111_),
+ .X(_048_)
+ );
+ sky130_fd_sc_hd__mux2_1 _358_ (
+ .A0(_160_),
+ .A1(_156_),
+ .S(_114_),
+ .X(_161_)
+ );
+ sky130_fd_sc_hd__mux2_1 _359_ (
+ .A0(_158_),
+ .A1(_154_),
+ .S(_114_),
+ .X(_159_)
+ );
+ sky130_fd_sc_hd__mux2_1 _360_ (
+ .A0(_001_),
+ .A1(b[23]),
+ .S(_015_),
+ .X(_002_)
+ );
+ sky130_fd_sc_hd__mux2_1 _361_ (
+ .A0(_151_),
+ .A1(_159_),
+ .S(_112_),
+ .X(_045_)
+ );
+ sky130_fd_sc_hd__mux2_1 _362_ (
+ .A0(_112_),
+ .A1(_115_),
+ .S(_015_),
+ .X(_000_)
+ );
+ sky130_fd_sc_hd__mux2_1 _363_ (
+ .A0(_162_),
+ .A1(_158_),
+ .S(_114_),
+ .X(_163_)
+ );
+ sky130_fd_sc_hd__mux2_1 _364_ (
+ .A0(_150_),
+ .A1(_148_),
+ .S(_114_),
+ .X(_151_)
+ );
+ sky130_fd_sc_hd__mux2_1 _365_ (
+ .A0(_020_),
+ .A1(_151_),
+ .S(_112_),
+ .X(_036_)
+ );
+ sky130_fd_sc_hd__mux2_1 _366_ (
+ .A0(_035_),
+ .A1(_102_),
+ .S(_110_),
+ .X(_150_)
+ );
+ sky130_fd_sc_hd__mux2_1 _367_ (
+ .A0(_148_),
+ .A1(_019_),
+ .S(_114_),
+ .X(_029_)
+ );
+ sky130_fd_sc_hd__mux2_1 _368_ (
+ .A0(_028_),
+ .A1(_101_),
+ .S(_110_),
+ .X(_148_)
+ );
+ sky130_fd_sc_hd__mux2_1 _369_ (
+ .A0(_102_),
+ .A1(_028_),
+ .S(_110_),
+ .X(_149_)
+ );
+ sky130_fd_sc_hd__mux2_1 _370_ (
+ .A0(_155_),
+ .A1(_163_),
+ .S(_112_),
+ .X(_050_)
+ );
+ sky130_fd_sc_hd__mux2_1 _371_ (
+ .A0(_050_),
+ .A1(_030_),
+ .S(_111_),
+ .X(_051_)
+ );
+ sky130_fd_sc_hd__mux2_1 _372_ (
+ .A0(_107_),
+ .A1(_049_),
+ .S(_110_),
+ .X(_164_)
+ );
+ sky130_fd_sc_hd__mux2_1 _373_ (
+ .A0(_164_),
+ .A1(_160_),
+ .S(_114_),
+ .X(_165_)
+ );
+ sky130_fd_sc_hd__mux2_1 _374_ (
+ .A0(_157_),
+ .A1(_165_),
+ .S(_112_),
+ .X(_052_)
+ );
+ sky130_fd_sc_hd__mux2_1 _375_ (
+ .A0(_052_),
+ .A1(_033_),
+ .S(_111_),
+ .X(_053_)
+ );
+ sky130_fd_sc_hd__mux2_1 _376_ (
+ .A0(_040_),
+ .A1(_104_),
+ .S(_110_),
+ .X(_154_)
+ );
+ sky130_fd_sc_hd__mux2_1 _377_ (
+ .A0(_149_),
+ .A1(_024_),
+ .S(_114_),
+ .X(_032_)
+ );
+ sky130_fd_sc_hd__mux2_1 _378_ (
+ .A0(_049_),
+ .A1(_106_),
+ .S(_110_),
+ .X(_162_)
+ );
+ sky130_fd_sc_hd__mux2_1 _379_ (
+ .A0(_032_),
+ .A1(_157_),
+ .S(_112_),
+ .X(_043_)
+ );
+ sky130_fd_sc_hd__mux2_1 _380_ (
+ .A0(_156_),
+ .A1(_152_),
+ .S(_114_),
+ .X(_157_)
+ );
+ sky130_fd_sc_hd__mux2_1 _381_ (
+ .A0(_105_),
+ .A1(_040_),
+ .S(_110_),
+ .X(_156_)
+ );
+ sky130_fd_sc_hd__mux2_1 _382_ (
+ .A0(_044_),
+ .A1(_105_),
+ .S(_110_),
+ .X(_158_)
+ );
+ sky130_fd_sc_hd__mux2_1 _383_ (
+ .A0(_106_),
+ .A1(_044_),
+ .S(_110_),
+ .X(_160_)
+ );
+ sky130_fd_sc_hd__mux2_1 _384_ (
+ .A0(_153_),
+ .A1(_161_),
+ .S(_112_),
+ .X(_047_)
+ );
+ sky130_fd_sc_hd__mux2_1 _385_ (
+ .A0(_029_),
+ .A1(_155_),
+ .S(_112_),
+ .X(_041_)
+ );
+ sky130_fd_sc_hd__mux2_1 _386_ (
+ .A0(_152_),
+ .A1(_149_),
+ .S(_114_),
+ .X(_153_)
+ );
+ sky130_fd_sc_hd__mux2_1 _387_ (
+ .A0(_056_),
+ .A1(_036_),
+ .S(_111_),
+ .X(_057_)
+ );
+ sky130_fd_sc_hd__mux2_1 _388_ (
+ .A0(_159_),
+ .A1(_055_),
+ .S(_112_),
+ .X(_056_)
+ );
+ sky130_fd_sc_hd__mux2_1 _389_ (
+ .A0(_025_),
+ .A1(_153_),
+ .S(_112_),
+ .X(_038_)
+ );
+ sky130_fd_sc_hd__mux2_1 _390_ (
+ .A0(_168_),
+ .A1(_167_),
+ .S(_114_),
+ .X(_066_)
+ );
+ sky130_fd_sc_hd__mux2_1 _391_ (
+ .A0(_108_),
+ .A1(_054_),
+ .S(_110_),
+ .X(_167_)
+ );
+ sky130_fd_sc_hd__mux2_1 _392_ (
+ .A0(_104_),
+ .A1(_035_),
+ .S(_110_),
+ .X(_152_)
+ );
+ sky130_fd_sc_hd__mux2_1 _393_ (
+ .A0(_071_),
+ .A1(_109_),
+ .S(_110_),
+ .X(_072_)
+ );
+ sky130_fd_sc_hd__mux2_1 _394_ (
+ .A0(_073_),
+ .A1(_070_),
+ .S(_114_),
+ .X(_170_)
+ );
+ sky130_fd_sc_hd__mux2_1 _395_ (
+ .A0(_061_),
+ .A1(_108_),
+ .S(_110_),
+ .X(_062_)
+ );
+ sky130_fd_sc_hd__mux2_1 _396_ (
+ .A0(_064_),
+ .A1(_041_),
+ .S(_111_),
+ .X(_065_)
+ );
+ sky130_fd_sc_hd__mux2_1 _397_ (
+ .A0(_059_),
+ .A1(_038_),
+ .S(_111_),
+ .X(_060_)
+ );
+ sky130_fd_sc_hd__mux2_1 _398_ (
+ .A0(_081_),
+ .A1(_072_),
+ .S(_114_),
+ .X(_082_)
+ );
+ sky130_fd_sc_hd__mux2_1 _399_ (
+ .A0(_163_),
+ .A1(_063_),
+ .S(_112_),
+ .X(_064_)
+ );
+ sky130_fd_sc_hd__mux2_1 _400_ (
+ .A0(_076_),
+ .A1(_168_),
+ .S(_114_),
+ .X(_077_)
+ );
+ sky130_fd_sc_hd__mux2_1 _401_ (
+ .A0(_161_),
+ .A1(_058_),
+ .S(_112_),
+ .X(_059_)
+ );
+ sky130_fd_sc_hd__mux2_1 _402_ (
+ .A0(_062_),
+ .A1(_166_),
+ .S(_114_),
+ .X(_063_)
+ );
+ sky130_fd_sc_hd__mux2_1 _403_ (
+ .A0(_109_),
+ .A1(_061_),
+ .S(_110_),
+ .X(_168_)
+ );
+ sky130_fd_sc_hd__mux2_1 _404_ (
+ .A0(_165_),
+ .A1(_066_),
+ .S(_112_),
+ .X(_169_)
+ );
+ sky130_fd_sc_hd__mux2_1 _405_ (
+ .A0(_169_),
+ .A1(_043_),
+ .S(_111_),
+ .X(_067_)
+ );
+ sky130_fd_sc_hd__mux2_1 _406_ (
+ .A0(_167_),
+ .A1(_164_),
+ .S(_114_),
+ .X(_058_)
+ );
+ sky130_fd_sc_hd__mux4_1 _407_ (
+ .A0(_186_),
+ .A1(_185_),
+ .A2(_184_),
+ .A3(_183_),
+ .S0(_103_),
+ .S1(_099_),
+ .X(_187_)
+ );
+ sky130_fd_sc_hd__mux4_1 _408_ (
+ .A0(_097_),
+ .A1(_096_),
+ .A2(_094_),
+ .A3(_093_),
+ .S0(_103_),
+ .S1(_099_),
+ .X(_113_)
+ );
+endmodule
diff --git a/Simulations/post_synthesis/gls.v b/Simulations/post_synthesis/gls.v
new file mode 100644
index 0000000..85a26bb
--- /dev/null
+++ b/Simulations/post_synthesis/gls.v
@@ -0,0 +1,27 @@
+module gls;
+parameter in = 19; // input resolution
+parameter man = 23; // Mantisa resolution in bits without hidden bit
+parameter exp = 8; // Exponent Resolution
+reg [in-1:0] a;
+
+wire [exp+man:0] b;
+wire zro;
+
+fxd2flot u1 (a, b, zro);
+
+initial
+begin
+a=19'd 1024;
+# 10 a= 19'd 65536;
+# 10 a=19'd 123456;
+
+#100 $finish;
+end
+
+initial
+begin
+ $dumpfile("fxd2float.vcd");
+ $dumpvars(0, gls);
+ //$monitor("time = %2d, in1 = %d, in2 = %d, out = %d", $time, in1, in2, out);
+end
+endmodule
\ No newline at end of file
diff --git a/Simulations/post_synthesis/gls_sim.PNG b/Simulations/post_synthesis/gls_sim.PNG
new file mode 100644
index 0000000..1f431be
--- /dev/null
+++ b/Simulations/post_synthesis/gls_sim.PNG
Binary files differ
diff --git a/Simulations/post_synthesis/primitives.v b/Simulations/post_synthesis/primitives.v
new file mode 100644
index 0000000..03689fe
--- /dev/null
+++ b/Simulations/post_synthesis/primitives.v
@@ -0,0 +1,1680 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+`define SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+
+/**
+ * udp_mux_2to1_N: Two to one multiplexer with inverting output
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_2to1_N (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ table
+ // A0 A1 S : Y
+ 0 ? 0 : 1 ;
+ 1 ? 0 : 0 ;
+ ? 0 1 : 1 ;
+ ? 1 1 : 0 ;
+ 0 0 ? : 1 ;
+ 1 1 ? : 0 ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_MUX_2TO1_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ * high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PS_pp$PG$N (
+ Q ,
+ D ,
+ CLK ,
+ SET ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input CLK ;
+ input SET ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D CLK SET NOTIFIER VPWR VGND : Qt : Qt+1
+ * b 0 ? 1 0 : ? : - ; // data event, hold unless CP==x
+ ? (?0) 0 ? 1 0 : ? : - ; // CP => 0, hold
+ ? b (?0) ? 1 0 : ? : - ; // S => 0, hold unless CP==x
+ ? ? 1 ? 1 0 : ? : 1 ; // async set
+ 0 r 0 ? 1 0 : ? : 0 ; // clock data on CP
+ 1 r ? ? 1 0 : ? : 1 ; // clock data on CP
+ 0 (x1) 0 ? 1 0 : 0 : 0 ; // possible CP, hold when D==Q==0
+ 1 (x1) ? ? 1 0 : 1 : 1 ; // possible CP, hold when D==Q==1
+ 0 x 0 ? 1 0 : 0 : 0 ; // unkown CP, hold when D==Q==0
+ 1 x ? ? 1 0 : 1 : 1 ; // unkown CP, hold when D==Q==1
+ ? b (?x) ? 1 0 : 1 : 1 ; // S=>x, hold when Q==1 unless CP==x
+ ? (?0) x ? 1 0 : 1 : 1 ;
+ // ['IfDef(functional)', ''] ? ? ? * 1 0 : ? : - ; // Q => - on any change on notifier
+ // ['Else', ''] ? ? ? * 1 0 : ? : x ; // Q => X on any change on notifier
+ // ['EndIfDef(functional)', ''] ? ? ? ? * ? : ? : x ; // Q => X on any change on vpwr
+ ? ? ? ? ? * : ? : x ; // Q => X on any change on vgnd
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_P_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ * (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$P (
+ Q ,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input D ;
+ input GATE;
+
+ reg Q;
+
+ table
+ // D GATE : Qt : Qt+1
+ ? 0 : ? : - ; // hold
+ 0 1 : ? : 0 ; // pass 0
+ 1 1 : ? : 1 ; // pass 1
+ 0 x : 0 : 0 ; // reduce pessimism
+ 1 x : 1 : 1 ; // reduce pessimism
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_P_V
+`define SKY130_FD_SC_HD__UDP_DFF_P_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$P (
+ Q ,
+ D ,
+ CLK
+);
+
+ output Q ;
+ input D ;
+ input CLK;
+
+ reg Q;
+
+ table
+ // D CLK : Qt : Qt+1
+ 1 (01) : ? : 1 ; // clocked data
+ 0 (01) : ? : 0 ;
+ 1 (x1) : 1 : 1 ; // reducing pessimism
+ 0 (x1) : 0 : 0 ;
+ 1 (0x) : 1 : 1 ;
+ 0 (0x) : 0 : 0 ;
+ ? (1x) : ? : - ; // no change on falling edge
+ ? (?0) : ? : - ;
+ * ? : ? : - ; // ignore edges on data
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+
+/**
+ * udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
+ * (Q output UDP) with both active high reset and
+ * set (set dominate). Includes VPWR and VGND
+ * power pins and notifier pin.
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N (
+ Q ,
+ SET ,
+ RESET ,
+ CLK_N ,
+ D ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input SET ;
+ input RESET ;
+ input CLK_N ;
+ input D ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // SET RESET CLK_N D NOTIFIER VPWR VGND : Qt : Qt+1
+ 0 1 b ? ? 1 0 : ? : 0 ; // Asserting reset
+ 0 * ? ? ? 1 0 : 0 : 0 ; // Changing reset
+ 1 ? b ? ? 1 0 : ? : 1 ; // Asserting set (dominates reset)
+ * 0 ? ? ? 1 0 : 1 : 1 ; // Changing set
+ 1 ? n ? ? 1 0 : 1 : 1 ;
+ ? 1 n ? ? 1 0 : 0 : 0 ;
+ x ? n ? ? 1 0 : 1 : 1 ;
+ ? x n ? ? 1 0 : 0 : 0 ;
+ 0 ? (01) 0 ? 1 0 : ? : 0 ; // rising clock
+ ? 0 (01) 1 ? 1 0 : ? : 1 ; // rising clock
+ 0 ? p 0 ? 1 0 : 0 : 0 ; // potential rising clock
+ ? 0 p 1 ? 1 0 : 1 : 1 ; // potential rising clock
+ 0 ? x 0 ? 1 0 : 1 : x ;
+ ? 0 x 1 ? 1 0 : 0 : x ;
+ 0 0 n ? ? 1 0 : ? : - ; // Clock falling register output does not change
+ 0 0 ? * ? 1 0 : ? : - ; // Changing Data
+ // ['IfDef(functional)', ''] ? ? ? ? * 1 0 : ? : - ; // go to - on notify
+ // ['Else', ''] ? ? ? ? * 1 0 : ? : X ; // go to X on notify
+ // ['EndIfDef(functional)', ''] ? ? ? ? ? * 0 : ? : X ; // any change on vpwr
+ ? ? ? ? ? ? * : ? : X ; // any change on vgnd
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_V
+`define SKY130_FD_SC_HD__UDP_DFF_PS_V
+
+/**
+ * udp_dff$PS: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PS (
+ Q ,
+ D ,
+ CLK,
+ SET
+);
+
+ output Q ;
+ input D ;
+ input CLK;
+ input SET;
+
+ reg Q;
+
+ table
+ // D CLK SET : Qt : Qt+1
+ * b 0 : ? : - ; // data event, hold unless CP==x
+ ? (?0) 0 : ? : - ; // CP => 0, hold
+ ? b (?0) : ? : - ; // S => 0, hold unless CP==x
+ ? ? 1 : ? : 1 ; // async set
+ 0 r 0 : ? : 0 ; // clock data on CP
+ 1 r ? : ? : 1 ; // clock data on CP
+ 0 (x1) 0 : 0 : 0 ; // possible CP, hold when D==Q==0
+ 1 (x1) ? : 1 : 1 ; // possible CP, hold when D==Q==1
+ 0 x 0 : 0 : 0 ; // unkown CP, hold when D==Q==0
+ 1 x ? : 1 : 1 ; // unkown CP, hold when D==Q==1
+ ? b (?x) : 1 : 1 ; // S=>x, hold when Q==1 unless CP==x
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_PS_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+
+/**
+ * udp_dlatch$lP: D-latch, gated standard drive / active high
+ * (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$lP (
+ Q ,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input D ;
+ input GATE;
+
+ reg Q;
+
+ table
+ // D GATE : Qt : Qt+1
+ ? 0 : ? : - ; // hold
+ 0 1 : ? : 0 ; // pass 0
+ 1 1 : ? : 1 ; // pass 1
+ 0 x : 0 : 0 ; // reduce pessimism
+ 1 x : 1 : 1 ; // reduce pessimism
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+
+/**
+
+ * UDP_OUT :=x when VPWR!=1
+ * UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$P (
+ UDP_OUT,
+ UDP_IN ,
+ VPWR
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VPWR ;
+
+ table
+ // UDP_IN VPWR : UDP_OUT
+ 0 1 : 0 ;
+ 1 1 : 1 ;
+ ? 0 : x ;
+ ? x : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+
+/**
+
+ * UDP_OUT :=x when VPWR!=1 or VGND!=0
+ * UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$PG (
+ UDP_OUT,
+ UDP_IN ,
+ VPWR ,
+ VGND
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VPWR ;
+ input VGND ;
+
+ table
+ // UDP_IN VPWR VGND : out
+ 0 1 0 : 0 ;
+ 1 1 0 : 1 ;
+ x 1 0 : x ;
+ ? 0 0 : x ;
+ ? 1 1 : x ;
+ ? x 0 : x ;
+ ? 1 x : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ * high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PR_pp$PG$N (
+ Q ,
+ D ,
+ CLK ,
+ RESET ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input CLK ;
+ input RESET ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D CLK RESET NOTIFIER VPWR VGND : Qt : Qt+1
+ * b 0 ? 1 0 : ? : - ; // data event, hold unless CP==x
+ ? (?0) 0 ? 1 0 : ? : - ; // CP => 0, hold
+ ? b (?0) ? 1 0 : ? : - ; // R => 0, hold unless CP==x
+ ? ? 1 ? 1 0 : ? : 0 ; // async reset
+ 0 r ? ? 1 0 : ? : 0 ; // clock data on CP
+ 1 r 0 ? 1 0 : ? : 1 ; // clock data on CP
+ 0 (x1) ? ? 1 0 : 0 : 0 ; // possible CP, hold when D==Q==0
+ 1 (x1) 0 ? 1 0 : 1 : 1 ; // possible CP, hold when D==Q==1
+ 0 x ? ? 1 0 : 0 : 0 ; // unkown CP, hold when D==Q==0
+ 1 x 0 ? 1 0 : 1 : 1 ; // unkown CP, hold when D==Q==1
+ ? b (?x) ? 1 0 : 0 : 0 ; // R=>x, hold when Q==0 unless CP==x
+ ? (?0) x ? 1 0 : 0 : 0 ;
+ // ['IfDef(functional)', ''] ? ? ? * 1 0 : ? : - ; // Q => - on any change on notifier
+ // ['Else', ''] ? ? ? * 1 0 : ? : x ; // Q => X on any change on notifier
+ // ['EndIfDef(functional)', ''] ? ? ? ? * ? : ? : x ; // Q => X on any change on vpwr
+ ? ? ? ? ? * : ? : x ; // Q => X on any change on vgnd
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+
+/**
+
+ * UDP_OUT :=x when VPWR!=1 or VGND!=0
+ * UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$PG (
+ UDP_OUT,
+ UDP_IN ,
+ VPWR ,
+ VGND
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VPWR ;
+ input VGND ;
+
+ table
+ // UDP_IN VPWR VGND : out
+ 0 1 0 : 0 ;
+ 1 1 0 : 1 ;
+ x 1 0 : x ;
+ ? 0 0 : x ;
+ ? 1 1 : x ;
+ ? x 0 : x ;
+ ? 1 x : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+
+/**
+
+ * UDP_OUT :=x when VPWR!=1 or VGND!=0
+ * UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
+ UDP_OUT,
+ UDP_IN ,
+ VPWR ,
+ VGND ,
+ SLEEP
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VPWR ;
+ input VGND ;
+ input SLEEP ;
+
+ table
+ // UDP_IN VPWR VGND SLEEP : out
+ 0 1 0 ? : 0 ;
+ 1 1 0 0 : 1 ;
+ x 1 0 0 : x ;
+ ? 0 0 0 : x ;
+ ? 1 1 0 : x ;
+ ? x 0 0 : x ;
+ ? 1 x 0 : x ;
+ ? ? 0 1 : 0 ;
+ ? ? 1 1 : x ;
+ ? ? x 1 : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+`define SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_2to1 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ table
+ // A0 A1 S : X
+ 0 0 ? : 0 ;
+ 1 1 ? : 1 ;
+ 0 ? 0 : 0 ;
+ 1 ? 0 : 1 ;
+ ? 0 1 : 0 ;
+ ? 1 1 : 1 ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_MUX_2TO1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ * (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N (
+ Q ,
+ D ,
+ GATE ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input GATE ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D GATE NOTIFIER VPWR VGND : Qtn : Qtn+1
+ * 0 ? 1 0 : ? : - ;
+ ? (?0) ? 1 0 : ? : - ;
+ ? (1x) ? 1 0 : ? : - ;
+ 0 (0x) ? 1 0 : 0 : 0 ;
+ 1 (0x) ? 1 0 : 1 : 1 ;
+ 0 (x1) ? 1 0 : ? : 0 ;
+ 1 (x1) ? 1 0 : ? : 1 ;
+ (?0) 1 ? 1 0 : ? : 0 ;
+ (?1) 1 ? 1 0 : ? : 1 ;
+ 0 (01) ? 1 0 : ? : 0 ;
+ 1 (01) ? 1 0 : ? : 1 ;
+ (?1) x ? 1 0 : 1 : 1 ; // Reducing pessimism.
+ (?0) x ? 1 0 : 0 : 0 ;
+ // ['IfDef(functional)', ''] ? ? * 1 0 : ? : - ;
+ // ['Else', ''] ? ? * 1 0 : ? : x ;
+ // ['EndIfDef(functional)', ''] 0 1 ? (?1) 0 : ? : 0 ;
+ 1 1 ? (?1) 0 : ? : 1 ;
+ 0 1 ? 1 (?0) : ? : 0 ;
+ 1 1 ? 1 (?0) : ? : 1 ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_V
+`define SKY130_FD_SC_HD__UDP_DFF_NSR_V
+
+/**
+ * udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
+ * with both active high reset and set (set dominate).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$NSR (
+ Q ,
+ SET ,
+ RESET,
+ CLK_N,
+ D
+);
+
+ output Q ;
+ input SET ;
+ input RESET;
+ input CLK_N;
+ input D ;
+
+ reg Q;
+
+ table
+ // SET RESET CLK_N D : Qt : Qt+1
+ 0 1 ? ? : ? : 0 ; // Asserting reset
+ 0 * ? ? : 0 : 0 ; // Changing reset
+ 1 ? ? ? : ? : 1 ; // Asserting set (dominates reset)
+ * 0 ? ? : 1 : 1 ; // Changing set
+ 0 ? (01) 0 : ? : 0 ; // rising clock
+ ? 0 (01) 1 : ? : 1 ; // rising clock
+ 0 ? p 0 : 0 : 0 ; // potential rising clock
+ ? 0 p 1 : 1 : 1 ; // potential rising clock
+ 0 0 n ? : ? : - ; // Clock falling register output does not change
+ 0 0 ? * : ? : - ; // Changing Data
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+
+/**
+ * udp_dlatch$lP_pp$PG$N: D-latch, gated standard drive / active high
+ * (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N (
+ Q ,
+ D ,
+ GATE ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input GATE ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D GATE NOTIFIER VPWR VGND : Qtn : Qtn+1
+ * 0 ? 1 0 : ? : - ;
+ ? (?0) ? 1 0 : ? : - ;
+ ? (1x) ? 1 0 : ? : - ;
+ 0 (0x) ? 1 0 : 0 : 0 ;
+ 1 (0x) ? 1 0 : 1 : 1 ;
+ 0 (x1) ? 1 0 : ? : 0 ;
+ 1 (x1) ? 1 0 : ? : 1 ;
+ (?0) 1 ? 1 0 : ? : 0 ;
+ (?1) 1 ? 1 0 : ? : 1 ;
+ 0 (01) ? 1 0 : ? : 0 ;
+ 1 (01) ? 1 0 : ? : 1 ;
+ (?1) x ? 1 0 : 1 : 1 ; // Reducing pessimism.
+ (?0) x ? 1 0 : 0 : 0 ;
+ // ['IfDef(functional)', ''] ? ? * 1 0 : ? : - ;
+ // ['Else', ''] ? ? * 1 0 : ? : x ;
+ // ['EndIfDef(functional)', ''] ? ? ? * ? : ? : x ; // any change on vpwr
+ ? ? ? ? * : ? : x ; // any change on vgnd
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+
+/**
+
+ * UDP_OUT :=x when VGND!=0
+ * UDP_OUT :=UDP_IN when VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood$l_pp$G (
+ UDP_OUT,
+ UDP_IN ,
+ VGND
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VGND ;
+
+ table
+ // UDP_IN VGND : out
+ 0 0 : 0 ;
+ 1 0 : 1 ;
+ x 0 : x ;
+ ? 1 : x ;
+ ? x : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ * (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$P_pp$PG$N (
+ Q ,
+ D ,
+ CLK ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input CLK ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D CLK NOTIFIER VPWR VGND : Qt : Qt+1
+ 1 (01) ? 1 0 : ? : 1 ; // clocked data
+ 0 (01) ? 1 0 : ? : 0 ;
+ 1 (x1) ? 1 0 : 1 : 1 ; // reducing pessimism
+ 0 (x1) ? 1 0 : 0 : 0 ;
+ 1 (0x) ? 1 0 : 1 : 1 ;
+ 0 (0x) ? 1 0 : 0 : 0 ;
+ 0 x ? 1 0 : 0 : 0 ; // Hold when CLK=X and D=Q
+ 1 x ? 1 0 : 1 : 1 ; // Hold when CLK=X and D=Q
+ ? (?0) ? 1 0 : ? : - ;
+ * b ? 1 0 : ? : - ; // ignore edges on data
+ // ['IfDef(functional)', ''] ? ? * 1 0 : ? : - ;
+ // ['Else', ''] ? ? * 1 0 : ? : x ;
+ // ['EndIfDef(functional)', ''] ? ? ? * ? : ? : x ; // any change on vpwr
+ ? ? ? ? * : ? : x ; // any change on vgnd
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+`define SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_mux_4to2 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ table
+ // A0 A1 A2 A3 S0 S1 : X
+ 0 ? ? ? 0 0 : 0 ;
+ 1 ? ? ? 0 0 : 1 ;
+ ? 0 ? ? 1 0 : 0 ;
+ ? 1 ? ? 1 0 : 1 ;
+ ? ? 0 ? 0 1 : 0 ;
+ ? ? 1 ? 0 1 : 1 ;
+ ? ? ? 0 1 1 : 0 ;
+ ? ? ? 1 1 1 : 1 ;
+ 0 0 0 0 ? ? : 0 ;
+ 1 1 1 1 ? ? : 1 ;
+ 0 0 ? ? ? 0 : 0 ;
+ 1 1 ? ? ? 0 : 1 ;
+ ? ? 0 0 ? 1 : 0 ;
+ ? ? 1 1 ? 1 : 1 ;
+ 0 ? 0 ? 0 ? : 0 ;
+ 1 ? 1 ? 0 ? : 1 ;
+ ? 0 ? 0 1 ? : 0 ;
+ ? 1 ? 1 1 ? : 1 ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_MUX_4TO2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+
+/**
+
+ * UDP_OUT :=x when VPWR!=1
+ * UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_pwrgood_pp$G (
+ UDP_OUT,
+ UDP_IN ,
+ VGND
+);
+
+ output UDP_OUT;
+ input UDP_IN ;
+ input VGND ;
+
+ table
+ // UDP_IN VPWR : UDP_OUT
+ 0 0 : 0 ;
+ 1 0 : 1 ;
+ ? 1 : x ;
+ ? x : x ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_V
+`define SKY130_FD_SC_HD__UDP_DFF_PR_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dff$PR (
+ Q ,
+ D ,
+ CLK ,
+ RESET
+);
+
+ output Q ;
+ input D ;
+ input CLK ;
+ input RESET;
+
+ reg Q;
+
+ table
+ // D CLK RESET : Qt : Qt+1
+ * b 0 : ? : - ; // data event, hold unless CP==x
+ ? (?0) 0 : ? : - ; // CP => 0, hold
+ ? b (?0) : ? : - ; // R => 0, hold unless CP==x
+ ? ? 1 : ? : 0 ; // async reset
+ 0 r ? : ? : 0 ; // clock data on CP
+ 1 r 0 : ? : 1 ; // clock data on CP
+ 0 (x1) ? : 0 : 0 ; // possible CP, hold when D==Q==0
+ 1 (x1) 0 : 1 : 1 ; // possible CP, hold when D==Q==1
+ 0 x ? : 0 : 0 ; // unkown CP, hold when D==Q==0
+ 1 x 0 : 1 : 1 ; // unkown CP, hold when D==Q==1
+ ? b (?x) : 0 : 0 ; // R=>x, hold when Q==0 unless CP==x
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DFF_PR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+
+/**
+ * udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
+ * high (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N (
+ Q ,
+ D ,
+ GATE ,
+ RESET ,
+ NOTIFIER,
+ VPWR ,
+ VGND
+);
+
+ output Q ;
+ input D ;
+ input GATE ;
+ input RESET ;
+ input NOTIFIER;
+ input VPWR ;
+ input VGND ;
+
+ reg Q;
+
+ table
+ // D GATE RESET NOTIFIER VPWR VGND : Qt : Qt+1
+ * 0 0 ? 1 0 : ? : - ;
+ ? ? 1 ? 1 0 : ? : 0 ; // asynchro clear
+ ? (?0) 0 ? 1 0 : ? : - ; // Changed R=? to R=0 ; jek 08/14/06/
+ ? (1x) 0 ? 1 0 : ? : - ; // Changed R=? to R=0 ; jek 08/14/06
+ 0 (0x) 0 ? 1 0 : 0 : 0 ;
+ 1 (0x) 0 ? 1 0 : 1 : 1 ;
+ 0 (x1) 0 ? 1 0 : ? : 0 ;
+ 1 (x1) 0 ? 1 0 : ? : 1 ;
+ (?0) 1 0 ? 1 0 : ? : 0 ;
+ (?1) 1 0 ? 1 0 : ? : 1 ;
+ 0 (01) 0 ? 1 0 : ? : 0 ;
+ 1 (01) 0 ? 1 0 : ? : 1 ;
+ ? 0 (?x) ? 1 0 : 0 : 0 ; // Reducing pessimism.//AB
+ * 0 x ? 1 0 : 0 : 0 ; // Reducing pessimism//AB
+ 0 (?1) x ? 1 0 : ? : 0 ; // Reducing pessimism.
+ (?0) 1 x ? 1 0 : ? : 0 ; // Reducing pessimism.
+ 0 1 (?x) ? 1 0 : ? : 0 ; // Reducing pessimism.//AB
+ ? 0 (?0) ? 1 0 : ? : - ; // ignore edge on clear
+ 0 1 (?0) ? 1 0 : ? : 0 ; // pessimism .
+ 1 1 (?0) ? 1 0 : ? : 1 ;
+ (?1) x 0 ? 1 0 : 1 : 1 ; // Reducing pessimism.
+ (?0) x 0 ? 1 0 : 0 : 0 ; // Reducing pessimism.
+ // ['IfDef(functional)', ''] ? ? ? * 1 0 : ? : - ;
+ // ['Else', ''] ? ? ? * 1 0 : ? : x ;
+ // ['EndIfDef(functional)', ''] 0 1 0 ? (?1) 0 : ? : 0 ;
+ 1 1 0 ? (?1) 0 : ? : 1 ;
+ 0 1 0 ? 1 (?0) : ? : 0 ;
+ 1 1 0 ? 1 (?0) : ? : 1 ;
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+`define SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ * (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`else
+primitive sky130_fd_sc_hd__udp_dlatch$PR (
+ Q ,
+ D ,
+ GATE ,
+ RESET
+);
+
+ output Q ;
+ input D ;
+ input GATE ;
+ input RESET;
+
+ reg Q;
+
+ table
+ // D GATE RESET : Qt : Qt+1
+ ? 0 0 : ? : - ; // hold
+ 0 1 0 : ? : 0 ; // pass 0
+ 1 1 0 : ? : 1 ; // pass 1
+ ? ? 1 : ? : 0 ; // async reset
+ 0 1 ? : ? : 0 ; // reduce pessimism
+ 0 x 0 : 0 : 0 ; // reduce pessimism
+ 1 x 0 : 1 : 1 ; // reduce pessimism
+ ? 0 x : 0 : 0 ; // reduce pessimism
+ 0 x x : 0 : 0 ; // reduce pessimism
+ endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_V
+
+
+//--------EOF---------
+
diff --git a/Simulations/post_synthesis/sky130_fd_sc_hd.v b/Simulations/post_synthesis/sky130_fd_sc_hd.v
new file mode 100644
index 0000000..2398035
--- /dev/null
+++ b/Simulations/post_synthesis/sky130_fd_sc_hd.v
@@ -0,0 +1,102454 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_6 (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_decapkapwr base (
+ .VPWR(VPWR),
+ .KAPWR(KAPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_6 ();
+ // Voltage supply signals
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_12 (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_decapkapwr base (
+ .VPWR(VPWR),
+ .KAPWR(KAPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_12 ();
+ // Voltage supply signals
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 3 units
+ * (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_3 (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_decapkapwr base (
+ .VPWR(VPWR),
+ .KAPWR(KAPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_3 ();
+ // Voltage supply signals
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_4 (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_decapkapwr base (
+ .VPWR(VPWR),
+ .KAPWR(KAPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_4 ();
+ // Voltage supply signals
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr ();
+
+ // Module supplies
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+
+/**
+ * lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
+ * rail.
+ *
+ * Verilog wrapper for lpflow_decapkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_8 (
+ VPWR ,
+ KAPWR,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input VPWR ;
+ input KAPWR;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_decapkapwr base (
+ .VPWR(VPWR),
+ .KAPWR(KAPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_decapkapwr_8 ();
+ // Voltage supply signals
+ supply1 VPWR ;
+ supply1 KAPWR;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_decapkapwr base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DIODE_2_V
+`define SKY130_FD_SC_HD__DIODE_2_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog wrapper for diode with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__diode_2 (
+ DIODE,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input DIODE;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__diode base (
+ .DIODE(DIODE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__diode_2 (
+ DIODE
+);
+
+ input DIODE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__diode base (
+ .DIODE(DIODE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DIODE_V
+`define SKY130_FD_SC_HD__DIODE_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+ DIODE,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input DIODE;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+ DIODE,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input DIODE;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+ DIODE
+);
+
+ // Module ports
+ input DIODE;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__diode (
+ DIODE
+);
+
+ // Module ports
+ input DIODE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DIODE_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_V
+`define SKY130_FD_SC_HD__NOR3B_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y , C_N, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y , C_N, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+ Y ,
+ A ,
+ B ,
+ C_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y, C_N, nor0_out );
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3b (
+ Y ,
+ A ,
+ B ,
+ C_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y, C_N, nor0_out );
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_1_V
+`define SKY130_FD_SC_HD__NOR3B_1_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_1 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_1 (
+ Y ,
+ A ,
+ B ,
+ C_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_2_V
+`define SKY130_FD_SC_HD__NOR3B_2_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_2 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_2 (
+ Y ,
+ A ,
+ B ,
+ C_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3B_4_V
+`define SKY130_FD_SC_HD__NOR3B_4_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ * Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_4 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3b_4 (
+ Y ,
+ A ,
+ B ,
+ C_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_4_V
+`define SKY130_FD_SC_HD__A211O_4_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_1_V
+`define SKY130_FD_SC_HD__A211O_1_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_2_V
+`define SKY130_FD_SC_HD__A211O_2_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211o_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211O_V
+`define SKY130_FD_SC_HD__A211O_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , and0_out, C1, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , and0_out, C1, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, and0_out, C1, B1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211o (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, and0_out, C1, B1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_2_V
+`define SKY130_FD_SC_HD__A221OI_2_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_1_V
+`define SKY130_FD_SC_HD__A221OI_1_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_4_V
+`define SKY130_FD_SC_HD__A221OI_4_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221oi_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221OI_V
+`define SKY130_FD_SC_HD__A221OI_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_V
+`define SKY130_FD_SC_HD__FILL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fill ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_4_V
+`define SKY130_FD_SC_HD__FILL_4_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_4 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fill base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_4 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_8_V
+`define SKY130_FD_SC_HD__FILL_8_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_8 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fill base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_8 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_2_V
+`define SKY130_FD_SC_HD__FILL_2_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_2 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fill base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_2 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FILL_1_V
+`define SKY130_FD_SC_HD__FILL_1_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_1 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fill base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fill_1 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FILL_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_V
+`define SKY130_FD_SC_HD__NAND3_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , B, A, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , B, A, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, B, A, C );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, B, A, C );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_2_V
+`define SKY130_FD_SC_HD__NAND3_2_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_2 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_1_V
+`define SKY130_FD_SC_HD__NAND3_1_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_1 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3_4_V
+`define SKY130_FD_SC_HD__NAND3_4_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3_4 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_4_V
+`define SKY130_FD_SC_HD__DLCLKP_4_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_4 (
+ GCLK,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_4 (
+ GCLK,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_2_V
+`define SKY130_FD_SC_HD__DLCLKP_2_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_2 (
+ GCLK,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_2 (
+ GCLK,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_1_V
+`define SKY130_FD_SC_HD__DLCLKP_1_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_1 (
+ GCLK,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp_1 (
+ GCLK,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlclkp base (
+ .GCLK(GCLK),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_V
+`define SKY130_FD_SC_HD__DLCLKP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+ GCLK,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output GCLK;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire clkn;
+
+ // Name Output Other arguments
+ not not0 (clkn , CLK );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
+ and and0 (GCLK , m0, CLK );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+ GCLK,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output GCLK;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire clkn ;
+ wire CLK_delayed ;
+ wire GATE_delayed;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ not not0 (clkn , CLK_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
+ and and0 (GCLK , m0, CLK_delayed );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+ GCLK,
+ GATE,
+ CLK
+);
+
+ // Module ports
+ output GCLK;
+ input GATE;
+ input CLK ;
+
+ // Local signals
+ wire m0 ;
+ wire clkn;
+
+ // Name Output Other arguments
+ not not0 (clkn , CLK );
+ sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
+ and and0 (GCLK , m0, CLK );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlclkp (
+ GCLK,
+ GATE,
+ CLK
+);
+
+ // Module ports
+ output GCLK;
+ input GATE;
+ input CLK ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire clkn ;
+ wire CLK_delayed ;
+ wire GATE_delayed;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ not not0 (clkn , CLK_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
+ and and0 (GCLK , m0, CLK_delayed );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLCLKP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_V
+`define SKY130_FD_SC_HD__NOR2B_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+ Y ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A );
+ and and0 (and0_out_Y , not0_out, B_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+ Y ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A );
+ and and0 (and0_out_Y , not0_out, B_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+ Y ,
+ A ,
+ B_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B_N;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A );
+ and and0 (and0_out_Y, not0_out, B_N );
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2b (
+ Y ,
+ A ,
+ B_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A );
+ and and0 (and0_out_Y, not0_out, B_N );
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_2_V
+`define SKY130_FD_SC_HD__NOR2B_2_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_2 (
+ Y ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_2 (
+ Y ,
+ A ,
+ B_N
+);
+
+ output Y ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_4_V
+`define SKY130_FD_SC_HD__NOR2B_4_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_4 (
+ Y ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_4 (
+ Y ,
+ A ,
+ B_N
+);
+
+ output Y ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2B_1_V
+`define SKY130_FD_SC_HD__NOR2B_1_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_1 (
+ Y ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2b_1 (
+ Y ,
+ A ,
+ B_N
+);
+
+ output Y ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2b base (
+ .Y(Y),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_2_V
+`define SKY130_FD_SC_HD__O2111A_2_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_1_V
+`define SKY130_FD_SC_HD__O2111A_1_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_V
+`define SKY130_FD_SC_HD__O2111A_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , B1, C1, or0_out, D1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , B1, C1, or0_out, D1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, B1, C1, or0_out, D1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111a (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, B1, C1, or0_out, D1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111A_4_V
+`define SKY130_FD_SC_HD__O2111A_4_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111a_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_V
+`define SKY130_FD_SC_HD__NAND4B_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y , D, C, B, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y , D, C, B, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y, D, C, B, not0_out);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4b (
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y, D, C, B, not0_out);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_4_V
+`define SKY130_FD_SC_HD__NAND4B_4_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_4 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_4 (
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_1_V
+`define SKY130_FD_SC_HD__NAND4B_1_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_1 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_1 (
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4B_2_V
+`define SKY130_FD_SC_HD__NAND4B_2_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_2 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4b_2 (
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
+ buf buf1 (X , pwrgood0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
+ buf buf1 (X , pwrgood0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+
+/**
+ * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
+ *
+ * Verilog wrapper for lpflow_clkbufkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
+ X ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkbufkapwr base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_4_V
+`define SKY130_FD_SC_HD__NAND2_4_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_4 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_4 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_8_V
+`define SKY130_FD_SC_HD__NAND2_8_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_8 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_8 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_1_V
+`define SKY130_FD_SC_HD__NAND2_1_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_1 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_1 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_V
+`define SKY130_FD_SC_HD__NAND2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, B, A );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, B, A );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2_2_V
+`define SKY130_FD_SC_HD__NAND2_2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2_2 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_V
+`define SKY130_FD_SC_HD__MUX4_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+ X ,
+ A0 ,
+ A1 ,
+ A2 ,
+ A3 ,
+ S0 ,
+ S1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A0 ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input S0 ;
+ input S1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_4to20_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+ X ,
+ A0 ,
+ A1 ,
+ A2 ,
+ A3 ,
+ S0 ,
+ S1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A0 ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input S0 ;
+ input S1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_4to20_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ // Module ports
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ // Local signals
+ wire mux_4to20_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+ buf buf0 (X , mux_4to20_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux4 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ // Module ports
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire mux_4to20_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+ buf buf0 (X , mux_4to20_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_1_V
+`define SKY130_FD_SC_HD__MUX4_1_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_1 (
+ X ,
+ A0 ,
+ A1 ,
+ A2 ,
+ A3 ,
+ S0 ,
+ S1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input S0 ;
+ input S1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_1 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_4_V
+`define SKY130_FD_SC_HD__MUX4_4_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_4 (
+ X ,
+ A0 ,
+ A1 ,
+ A2 ,
+ A3 ,
+ S0 ,
+ S1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input S0 ;
+ input S1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_4 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX4_2_V
+`define SKY130_FD_SC_HD__MUX4_2_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_2 (
+ X ,
+ A0 ,
+ A1 ,
+ A2 ,
+ A3 ,
+ S0 ,
+ S1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input S0 ;
+ input S1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux4_2 (
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux4 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S0),
+ .S1(S1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ * horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s4s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlymetal6s4s base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s4s_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlymetal6s4s base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_4_V
+`define SKY130_FD_SC_HD__AND3_4_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_4 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_1_V
+`define SKY130_FD_SC_HD__AND3_1_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_1 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_2_V
+`define SKY130_FD_SC_HD__AND3_2_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3_2 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3_V
+`define SKY130_FD_SC_HD__AND3_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , C, A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , C, A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, C, A, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, C, A, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_1_V
+`define SKY130_FD_SC_HD__HA_1_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_1 (
+ COUT,
+ SUM ,
+ A ,
+ B
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_4_V
+`define SKY130_FD_SC_HD__HA_4_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_4 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_4 (
+ COUT,
+ SUM ,
+ A ,
+ B
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_V
+`define SKY130_FD_SC_HD__HA_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_COUT ;
+ wire pwrgood_pp0_out_COUT;
+ wire xor0_out_SUM ;
+ wire pwrgood_pp1_out_SUM ;
+
+ // Name Output Other arguments
+ and and0 (and0_out_COUT , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
+ buf buf0 (COUT , pwrgood_pp0_out_COUT );
+ xor xor0 (xor0_out_SUM , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
+ buf buf1 (SUM , pwrgood_pp1_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_COUT ;
+ wire pwrgood_pp0_out_COUT;
+ wire xor0_out_SUM ;
+ wire pwrgood_pp1_out_SUM ;
+
+ // Name Output Other arguments
+ and and0 (and0_out_COUT , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
+ buf buf0 (COUT , pwrgood_pp0_out_COUT );
+ xor xor0 (xor0_out_SUM , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
+ buf buf1 (SUM , pwrgood_pp1_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+ COUT,
+ SUM ,
+ A ,
+ B
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+
+ // Local signals
+ wire and0_out_COUT;
+ wire xor0_out_SUM ;
+
+ // Name Output Other arguments
+ and and0 (and0_out_COUT, A, B );
+ buf buf0 (COUT , and0_out_COUT );
+ xor xor0 (xor0_out_SUM , B, A );
+ buf buf1 (SUM , xor0_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ha (
+ COUT,
+ SUM ,
+ A ,
+ B
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out_COUT;
+ wire xor0_out_SUM ;
+
+ // Name Output Other arguments
+ and and0 (and0_out_COUT, A, B );
+ buf buf0 (COUT , and0_out_COUT );
+ xor xor0 (xor0_out_SUM , B, A );
+ buf buf1 (SUM , xor0_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__HA_2_V
+`define SKY130_FD_SC_HD__HA_2_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_2 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ha_2 (
+ COUT,
+ SUM ,
+ A ,
+ B
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ha base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__HA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCON_V
+`define SKY130_FD_SC_HD__FAHCON_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_coutn ;
+ wire pwrgood_pp1_out_coutn;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ nor nor0 (a_b , A, B );
+ nor nor1 (a_ci , A, CI );
+ nor nor2 (b_ci , B, CI );
+ or or0 (or0_out_coutn , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+ buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_coutn ;
+ wire pwrgood_pp1_out_coutn;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ nor nor0 (a_b , A, B );
+ nor nor1 (a_ci , A, CI );
+ nor nor2 (b_ci , B, CI );
+ or or0 (or0_out_coutn , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+ buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ // Module ports
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_coutn;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ buf buf0 (SUM , xor0_out_SUM );
+ nor nor0 (a_b , A, B );
+ nor nor1 (a_ci , A, CI );
+ nor nor2 (b_ci , B, CI );
+ or or0 (or0_out_coutn, a_b, a_ci, b_ci);
+ buf buf1 (COUT_N , or0_out_coutn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcon (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ // Module ports
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_coutn;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ buf buf0 (SUM , xor0_out_SUM );
+ nor nor0 (a_b , A, B );
+ nor nor1 (a_ci , A, CI );
+ nor nor2 (b_ci , B, CI );
+ or or0 (or0_out_coutn, a_b, a_ci, b_ci);
+ buf buf1 (COUT_N , or0_out_coutn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCON_1_V
+`define SKY130_FD_SC_HD__FAHCON_1_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog wrapper for fahcon with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcon_1 (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fahcon base (
+ .COUT_N(COUT_N),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CI(CI),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcon_1 (
+ COUT_N,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ output COUT_N;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fahcon base (
+ .COUT_N(COUT_N),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CI(CI)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCON_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_2_V
+`define SKY130_FD_SC_HD__A21BOI_2_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_4_V
+`define SKY130_FD_SC_HD__A21BOI_4_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_V
+`define SKY130_FD_SC_HD__A21BOI_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire b ;
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , b, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire b ;
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , b, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Local signals
+ wire b ;
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, b, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21boi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire b ;
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, b, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_0_V
+`define SKY130_FD_SC_HD__A21BOI_0_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_0 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_0 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BOI_1_V
+`define SKY130_FD_SC_HD__A21BOI_1_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ * 2nd input inverted.
+ *
+ * Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21boi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21boi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BOI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_1_V
+`define SKY130_FD_SC_HD__DLRTN_1_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_1 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_1 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_V
+`define SKY130_FD_SC_HD__DLRTN_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate;
+ wire buf_Q ;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intgate, GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_N_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intgate, GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate;
+ wire buf_Q ;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intgate, GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_N_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intgate, GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_4_V
+`define SKY130_FD_SC_HD__DLRTN_4_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_4 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_4 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTN_2_V
+`define SKY130_FD_SC_HD__DLRTN_2_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog wrapper for dlrtn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_2 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtn_2 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtn base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_4_V
+`define SKY130_FD_SC_HD__A211OI_4_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_1_V
+`define SKY130_FD_SC_HD__A211OI_1_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_2_V
+`define SKY130_FD_SC_HD__A211OI_2_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a211oi_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a211oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A211OI_V
+`define SKY130_FD_SC_HD__A211OI_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, B1, C1);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a211oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, B1, C1);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A211OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAH_1_V
+`define SKY130_FD_SC_HD__FAH_1_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog wrapper for fah with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fah_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fah base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CI(CI),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fah_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fah base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CI(CI)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAH_V
+`define SKY130_FD_SC_HD__FAH_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT ;
+ wire pwrgood_pp1_out_COUT;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, CI );
+ and and2 (b_ci , B, CI );
+ or or0 (or0_out_COUT , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+ buf buf1 (COUT , pwrgood_pp1_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT ;
+ wire pwrgood_pp1_out_COUT;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM , A, B, CI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, CI );
+ and and2 (b_ci , B, CI );
+ or or0 (or0_out_COUT , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+ buf buf1 (COUT , pwrgood_pp1_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Local signals
+ wire xor0_out_SUM;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM, A, B, CI );
+ buf buf0 (SUM , xor0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, CI );
+ and and2 (b_ci , B, CI );
+ or or0 (or0_out_COUT, a_b, a_ci, b_ci);
+ buf buf1 (COUT , or0_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fah (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CI
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CI ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xor0_out_SUM;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_SUM, A, B, CI );
+ buf buf0 (SUM , xor0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, CI );
+ and and2 (b_ci , B, CI );
+ or or0 (or0_out_COUT, a_b, a_ci, b_ci);
+ buf buf1 (COUT , or0_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAH_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_1_V
+`define SKY130_FD_SC_HD__SDLCLKP_1_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_1 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_1 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_4_V
+`define SKY130_FD_SC_HD__SDLCLKP_4_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_4 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_4 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_V
+`define SKY130_FD_SC_HD__SDLCLKP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire m0n ;
+ wire clkn ;
+ wire SCE_GATE;
+
+ // Name Output Other arguments
+ not not0 (m0n , m0 );
+ not not1 (clkn , CLK );
+ nor nor0 (SCE_GATE, GATE, SCE );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
+ and and0 (GCLK , m0n, CLK );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire m0n ;
+ wire clkn ;
+ wire CLK_delayed ;
+ wire SCE_delayed ;
+ wire GATE_delayed ;
+ wire SCE_gate_delayed;
+ reg notifier ;
+ wire awake ;
+ wire SCE_awake ;
+ wire GATE_awake ;
+
+ // Name Output Other arguments
+ not not0 (m0n , m0 );
+ not not1 (clkn , CLK_delayed );
+ nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+ and and0 (GCLK , m0n, CLK_delayed );
+ assign awake = ( VPWR === 1'b1 );
+ assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
+ assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK
+);
+
+ // Module ports
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+
+ // Local signals
+ wire m0 ;
+ wire m0n ;
+ wire clkn ;
+ wire SCE_GATE;
+
+ // Name Output Other arguments
+ not not0 (m0n , m0 );
+ not not1 (clkn , CLK );
+ nor nor0 (SCE_GATE, GATE, SCE );
+ sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
+ and and0 (GCLK , m0n, CLK );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK
+);
+
+ // Module ports
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire m0 ;
+ wire m0n ;
+ wire clkn ;
+ wire CLK_delayed ;
+ wire SCE_delayed ;
+ wire GATE_delayed ;
+ wire SCE_gate_delayed;
+ reg notifier ;
+ wire awake ;
+ wire SCE_awake ;
+ wire GATE_awake ;
+
+ // Name Output Other arguments
+ not not0 (m0n , m0 );
+ not not1 (clkn , CLK_delayed );
+ nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+ and and0 (GCLK , m0n, CLK_delayed );
+ assign awake = ( VPWR === 1'b1 );
+ assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
+ assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDLCLKP_2_V
+`define SKY130_FD_SC_HD__SDLCLKP_2_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_2 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdlclkp_2 (
+ GCLK,
+ SCE ,
+ GATE,
+ CLK
+);
+
+ output GCLK;
+ input SCE ;
+ input GATE;
+ input CLK ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdlclkp base (
+ .GCLK(GCLK),
+ .SCE(SCE),
+ .GATE(GATE),
+ .CLK(CLK)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDLCLKP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_V
+`define SKY130_FD_SC_HD__DFRBP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+ wire RESET;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q;
+ wire RESET;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_1_V
+`define SKY130_FD_SC_HD__DFRBP_1_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRBP_2_V
+`define SKY130_FD_SC_HD__DFRBP_2_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_4_V
+`define SKY130_FD_SC_HD__OR4BB_4_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_4 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_4 (
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_1_V
+`define SKY130_FD_SC_HD__OR4BB_1_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_1 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_1 (
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_V
+`define SKY130_FD_SC_HD__OR4BB_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , D_N, C_N );
+ or or0 (or0_out_X , B, A, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , D_N, C_N );
+ or or0 (or0_out_X , B, A, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Local signals
+ wire nand0_out;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out, D_N, C_N );
+ or or0 (or0_out_X, B, A, nand0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4bb (
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out, D_N, C_N );
+ or or0 (or0_out_X, B, A, nand0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4BB_2_V
+`define SKY130_FD_SC_HD__OR4BB_2_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_2 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4bb_2 (
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4bb base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_4_V
+`define SKY130_FD_SC_HD__NOR3_4_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_4 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_2_V
+`define SKY130_FD_SC_HD__NOR3_2_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_2 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_V
+`define SKY130_FD_SC_HD__NOR3_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , C, A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , C, A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, C, A, B );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor3 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, C, A, B );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR3_1_V
+`define SKY130_FD_SC_HD__NOR3_1_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ * Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor3_1 (
+ Y,
+ A,
+ B,
+ C
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor3 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_V
+`define SKY130_FD_SC_HD__A41O_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41o (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_4_V
+`define SKY130_FD_SC_HD__A41O_4_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_2_V
+`define SKY130_FD_SC_HD__A41O_2_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41O_1_V
+`define SKY130_FD_SC_HD__A41O_1_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41o_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_4_V
+`define SKY130_FD_SC_HD__OR4B_4_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_V
+`define SKY130_FD_SC_HD__OR4B_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ or or0 (or0_out_X , not0_out, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ or or0 (or0_out_X , not0_out, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ or or0 (or0_out_X, not0_out, C, B, A);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4b (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ or or0 (or0_out_X, not0_out, C, B, A);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_2_V
+`define SKY130_FD_SC_HD__OR4B_2_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4B_1_V
+`define SKY130_FD_SC_HD__OR4B_1_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4b_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_2_V
+`define SKY130_FD_SC_HD__CLKINV_2_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_2 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_2 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_V
+`define SKY130_FD_SC_HD__CLKINV_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_4_V
+`define SKY130_FD_SC_HD__CLKINV_4_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_4 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_4 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_8_V
+`define SKY130_FD_SC_HD__CLKINV_8_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_8 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_8 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_1_V
+`define SKY130_FD_SC_HD__CLKINV_1_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_1 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_1 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINV_16_V
+`define SKY130_FD_SC_HD__CLKINV_16_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_16 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinv_16 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_V
+`define SKY130_FD_SC_HD__EDFXBP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXBP_1_V
+`define SKY130_FD_SC_HD__EDFXBP_1_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for edfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__edfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxbp_1 (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__edfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_2_V
+`define SKY130_FD_SC_HD__MUX2I_2_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_2 (
+ Y ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_2 (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_4_V
+`define SKY130_FD_SC_HD__MUX2I_4_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_4 (
+ Y ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_4 (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_V
+`define SKY130_FD_SC_HD__MUX2I_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+ Y ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_2to1_n0_out_Y;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+ Y ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_2to1_n0_out_Y;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ // Module ports
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Local signals
+ wire mux_2to1_n0_out_Y;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
+ buf buf0 (Y , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2i (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ // Module ports
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire mux_2to1_n0_out_Y;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
+ buf buf0 (Y , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2I_1_V
+`define SKY130_FD_SC_HD__MUX2I_1_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_1 (
+ Y ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2i_1 (
+ Y ,
+ A0,
+ A1,
+ S
+);
+
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2i base (
+ .Y(Y),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2I_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_V
+`define SKY130_FD_SC_HD__SDFXTP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp (
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_2_V
+`define SKY130_FD_SC_HD__SDFXTP_2_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_2 (
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_4_V
+`define SKY130_FD_SC_HD__SDFXTP_4_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_4 (
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXTP_1_V
+`define SKY130_FD_SC_HD__SDFXTP_1_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxtp_1 (
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CONB_1_V
+`define SKY130_FD_SC_HD__CONB_1_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog wrapper for conb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__conb_1 (
+ HI ,
+ LO ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output HI ;
+ output LO ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__conb base (
+ .HI(HI),
+ .LO(LO),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__conb_1 (
+ HI,
+ LO
+);
+
+ output HI;
+ output LO;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__conb base (
+ .HI(HI),
+ .LO(LO)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CONB_V
+`define SKY130_FD_SC_HD__CONB_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+ HI ,
+ LO ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output HI ;
+ output LO ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pullup0_out_HI ;
+ wire pulldown0_out_LO;
+
+ // Name Output Other arguments
+ pullup pullup0 (pullup0_out_HI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
+ pulldown pulldown0 (pulldown0_out_LO);
+ sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+ HI ,
+ LO ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output HI ;
+ output LO ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pullup0_out_HI ;
+ wire pulldown0_out_LO;
+
+ // Name Output Other arguments
+ pullup pullup0 (pullup0_out_HI );
+ sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
+ pulldown pulldown0 (pulldown0_out_LO);
+ sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+ HI,
+ LO
+);
+
+ // Module ports
+ output HI;
+ output LO;
+
+ // Name Output
+ pullup pullup0 (HI );
+ pulldown pulldown0 (LO );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__conb (
+ HI,
+ LO
+);
+
+ // Module ports
+ output HI;
+ output LO;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output
+ pullup pullup0 (HI );
+ pulldown pulldown0 (LO );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CONB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_V
+`define SKY130_FD_SC_HD__DFSBP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+ wire SET ;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( SET_B_delayed === 1'b1 );
+ assign cond1 = ( SET_B === 1'b1 );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Local signals
+ wire buf_Q;
+ wire SET ;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( SET_B_delayed === 1'b1 );
+ assign cond1 = ( SET_B === 1'b1 );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_1_V
+`define SKY130_FD_SC_HD__DFSBP_1_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSBP_2_V
+`define SKY130_FD_SC_HD__DFSBP_2_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfsbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s18 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s18 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s18 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s18 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s18 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s18 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s18 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_2_V
+`define SKY130_FD_SC_HD__SDFRBP_2_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sdfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_V
+`define SKY130_FD_SC_HD__SDFRBP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRBP_1_V
+`define SKY130_FD_SC_HD__SDFRBP_1_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sdfrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_1_V
+`define SKY130_FD_SC_HD__O221AI_1_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_4_V
+`define SKY130_FD_SC_HD__O221AI_4_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_V
+`define SKY130_FD_SC_HD__O221AI_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221AI_2_V
+`define SKY130_FD_SC_HD__O221AI_2_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221ai_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_4_V
+`define SKY130_FD_SC_HD__O22AI_4_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_V
+`define SKY130_FD_SC_HD__O22AI_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , B1, B2 );
+ nor nor1 (nor1_out , A1, A2 );
+ or or0 (or0_out_Y , nor1_out, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , B1, B2 );
+ nor nor1 (nor1_out , A1, A2 );
+ or or0 (or0_out_Y , nor1_out, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , B1, B2 );
+ nor nor1 (nor1_out , A1, A2 );
+ or or0 (or0_out_Y, nor1_out, nor0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , B1, B2 );
+ nor nor1 (nor1_out , A1, A2 );
+ or or0 (or0_out_Y, nor1_out, nor0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_1_V
+`define SKY130_FD_SC_HD__O22AI_1_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22AI_2_V
+`define SKY130_FD_SC_HD__O22AI_2_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22ai_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_4_V
+`define SKY130_FD_SC_HD__O32AI_4_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_2_V
+`define SKY130_FD_SC_HD__O32AI_2_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_V
+`define SKY130_FD_SC_HD__O32AI_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A3, A1, A2 );
+ nor nor1 (nor1_out , B1, B2 );
+ or or0 (or0_out_Y , nor1_out, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A3, A1, A2 );
+ nor nor1 (nor1_out , B1, B2 );
+ or or0 (or0_out_Y , nor1_out, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A3, A1, A2 );
+ nor nor1 (nor1_out , B1, B2 );
+ or or0 (or0_out_Y, nor1_out, nor0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A3, A1, A2 );
+ nor nor1 (nor1_out , B1, B2 );
+ or or0 (or0_out_Y, nor1_out, nor0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32AI_1_V
+`define SKY130_FD_SC_HD__O32AI_1_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32ai_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_2_V
+`define SKY130_FD_SC_HD__NAND4_2_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_2 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_V
+`define SKY130_FD_SC_HD__NAND4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , D, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y , D, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, D, C, B, A );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out_Y, D, C, B, A );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_1_V
+`define SKY130_FD_SC_HD__NAND4_1_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_1 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4_4_V
+`define SKY130_FD_SC_HD__NAND4_4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4_4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_2_V
+`define SKY130_FD_SC_HD__NOR4BB_2_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_2 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_2 (
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_4_V
+`define SKY130_FD_SC_HD__NOR4BB_4_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_4 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_4 (
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_1_V
+`define SKY130_FD_SC_HD__NOR4BB_1_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_1 (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb_1 (
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4bb base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_V
+`define SKY130_FD_SC_HD__NOR4BB_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y , nor0_out, C_N, D_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+ Y ,
+ A ,
+ B ,
+ C_N ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y , nor0_out, C_N, D_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y, nor0_out, C_N, D_N);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4bb (
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A, B );
+ and and0 (and0_out_Y, nor0_out, C_N, D_N);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_V
+`define SKY130_FD_SC_HD__DLXTN_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+ Q ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+ Q ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q ;
+ wire GATE_N_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+ Q ,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE_N;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn (
+ Q ,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q ;
+ wire GATE_N_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_2_V
+`define SKY130_FD_SC_HD__DLXTN_2_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_2 (
+ Q ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_2 (
+ Q ,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_1_V
+`define SKY130_FD_SC_HD__DLXTN_1_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_1 (
+ Q ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_1 (
+ Q ,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTN_4_V
+`define SKY130_FD_SC_HD__DLXTN_4_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_4 (
+ Q ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtn_4 (
+ Q ,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ input D ;
+ input GATE_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxtn base (
+ .Q(Q),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_2_V
+`define SKY130_FD_SC_HD__DFSTP_2_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_4_V
+`define SKY130_FD_SC_HD__DFSTP_4_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_V
+`define SKY130_FD_SC_HD__DFSTP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+ Q ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+ wire SET ;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+ Q ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( SET_B_delayed === 1'b1 );
+ assign cond1 = ( SET_B === 1'b1 );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+ Q ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Local signals
+ wire buf_Q;
+ wire SET ;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfstp (
+ Q ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( SET_B_delayed === 1'b1 );
+ assign cond1 = ( SET_B === 1'b1 );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFSTP_1_V
+`define SKY130_FD_SC_HD__DFSTP_1_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfstp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFSTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_1_V
+`define SKY130_FD_SC_HD__DFRTP_1_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_V
+`define SKY130_FD_SC_HD__DFRTP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+ wire RESET;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q;
+ wire RESET;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_2_V
+`define SKY130_FD_SC_HD__DFRTP_2_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTP_4_V
+`define SKY130_FD_SC_HD__DFRTP_4_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_1_V
+`define SKY130_FD_SC_HD__NAND4BB_1_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_1 (
+ Y ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_1 (
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_V
+`define SKY130_FD_SC_HD__NAND4BB_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+ Y ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , D, C );
+ or or0 (or0_out_Y , B_N, A_N, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+ Y ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , D, C );
+ or or0 (or0_out_Y , B_N, A_N, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Local signals
+ wire nand0_out;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out, D, C );
+ or or0 (or0_out_Y, B_N, A_N, nand0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb (
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out, D, C );
+ or or0 (or0_out_Y, B_N, A_N, nand0_out);
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_2_V
+`define SKY130_FD_SC_HD__NAND4BB_2_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_2 (
+ Y ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_2 (
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND4BB_4_V
+`define SKY130_FD_SC_HD__NAND4BB_4_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_4 (
+ Y ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand4bb_4 (
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand4bb base (
+ .Y(Y),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ * containing inverter, 2-input NOR, 2-input NAND,
+ * and constant cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ * containing inverter, 2-input NOR, 2-input NAND,
+ * and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+ LO ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output LO ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire nor2left ;
+ wire invleft ;
+ wire nor2right;
+ wire invright ;
+ wire nd2left ;
+ wire nd2right ;
+ wire tielo ;
+ wire net7 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
+ sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ buf buf0 (LO , tielo );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ * containing inverter, 2-input NOR, 2-input NAND,
+ * and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+ LO ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output LO ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire nor2left ;
+ wire invleft ;
+ wire nor2right;
+ wire invright ;
+ wire nd2left ;
+ wire nd2right ;
+ wire tielo ;
+ wire net7 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
+ sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
+ buf buf0 (LO , tielo );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ * containing inverter, 2-input NOR, 2-input NAND,
+ * and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+ LO
+);
+
+ // Module ports
+ output LO;
+
+ // Local signals
+ wire nor2left ;
+ wire invleft ;
+ wire nor2right;
+ wire invright ;
+ wire nd2left ;
+ wire nd2right ;
+ wire tielo ;
+ wire net7 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) );
+ sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) );
+ sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) );
+ sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right));
+ sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) );
+ sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) );
+ sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) );
+ buf buf0 (LO , tielo );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+
+/**
+ * macro_sparecell: Macro cell for metal-mask-only revisioning,
+ * containing inverter, 2-input NOR, 2-input NAND,
+ * and constant cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import sub cells.
+
+`celldefine
+module sky130_fd_sc_hd__macro_sparecell (
+ LO
+);
+
+ // Module ports
+ output LO;
+
+ // Local signals
+ wire nor2left ;
+ wire invleft ;
+ wire nor2right;
+ wire invright ;
+ wire nd2left ;
+ wire nd2right ;
+ wire tielo ;
+ wire net7 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) );
+ sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) );
+ sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) );
+ sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right));
+ sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) );
+ sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) );
+ sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) );
+ buf buf0 (LO , tielo );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_1_V
+`define SKY130_FD_SC_HD__MUX2_1_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_1 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_1 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_V
+`define SKY130_FD_SC_HD__MUX2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_2to10_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire mux_2to10_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ // Module ports
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Local signals
+ wire mux_2to10_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
+ buf buf0 (X , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__mux2 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ // Module ports
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire mux_2to10_out_X;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
+ buf buf0 (X , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_2_V
+`define SKY130_FD_SC_HD__MUX2_2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_2 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_2 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_8_V
+`define SKY130_FD_SC_HD__MUX2_8_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_8 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_8 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MUX2_4_V
+`define SKY130_FD_SC_HD__MUX2_4_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_4 (
+ X ,
+ A0 ,
+ A1 ,
+ S ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A0 ;
+ input A1 ;
+ input S ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__mux2_4 (
+ X ,
+ A0,
+ A1,
+ S
+);
+
+ output X ;
+ input A0;
+ input A1;
+ input S ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__mux2 base (
+ .X(X),
+ .A0(A0),
+ .A1(A1),
+ .S(S)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MUX2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_2_V
+`define SKY130_FD_SC_HD__NOR2_2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_2 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_1_V
+`define SKY130_FD_SC_HD__NOR2_1_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_1 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_1 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_V
+`define SKY130_FD_SC_HD__NOR2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, A, B );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, A, B );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_4_V
+`define SKY130_FD_SC_HD__NOR2_4_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_4 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_4 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR2_8_V
+`define SKY130_FD_SC_HD__NOR2_8_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_8 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor2_8 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR2_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_V
+`define SKY130_FD_SC_HD__O21BA_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A1, A2 );
+ nor nor1 (nor1_out_X , B1_N, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A1, A2 );
+ nor nor1 (nor1_out_X , B1_N, nor0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A1, A2 );
+ nor nor1 (nor1_out_X, B1_N, nor0_out );
+ buf buf0 (X , nor1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ba (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire nor1_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A1, A2 );
+ nor nor1 (nor1_out_X, B1_N, nor0_out );
+ buf buf0 (X , nor1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_1_V
+`define SKY130_FD_SC_HD__O21BA_1_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_2_V
+`define SKY130_FD_SC_HD__O21BA_2_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BA_4_V
+`define SKY130_FD_SC_HD__O21BA_4_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ * 2nd input inverted.
+ *
+ * X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ba_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ba base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_1_V
+`define SKY130_FD_SC_HD__A41OI_1_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_4_V
+`define SKY130_FD_SC_HD__A41OI_4_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_2_V
+`define SKY130_FD_SC_HD__A41OI_2_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a41oi_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a41oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A41OI_V
+`define SKY130_FD_SC_HD__A41OI_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a41oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2, A3, A4 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A41OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_1_V
+`define SKY130_FD_SC_HD__OR2_1_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_1 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_1 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_4_V
+`define SKY130_FD_SC_HD__OR2_4_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_4 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_4 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_V
+`define SKY130_FD_SC_HD__OR2_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, B, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, B, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_0_V
+`define SKY130_FD_SC_HD__OR2_0_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_0 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_0 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2_2_V
+`define SKY130_FD_SC_HD__OR2_2_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2_2 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlygate4sd2 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd2_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlygate4sd2 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_V
+`define SKY130_FD_SC_HD__O41AI_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_2_V
+`define SKY130_FD_SC_HD__O41AI_2_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_1_V
+`define SKY130_FD_SC_HD__O41AI_1_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41AI_4_V
+`define SKY130_FD_SC_HD__O41AI_4_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41ai_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_2_V
+`define SKY130_FD_SC_HD__AND2B_2_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_2 (
+ X ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_2 (
+ X ,
+ A_N,
+ B
+);
+
+ output X ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_4_V
+`define SKY130_FD_SC_HD__AND2B_4_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_4 (
+ X ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_4 (
+ X ,
+ A_N,
+ B
+);
+
+ output X ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_V
+`define SKY130_FD_SC_HD__AND2B_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+ X ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , not0_out, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+ X ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , not0_out, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+ X ,
+ A_N,
+ B
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, not0_out, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2b (
+ X ,
+ A_N,
+ B
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, not0_out, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2B_1_V
+`define SKY130_FD_SC_HD__AND2B_1_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_1 (
+ X ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2b_1 (
+ X ,
+ A_N,
+ B
+);
+
+ output X ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_2_V
+`define SKY130_FD_SC_HD__A311O_2_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_1_V
+`define SKY130_FD_SC_HD__A311O_1_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_4_V
+`define SKY130_FD_SC_HD__A311O_4_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311o_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311O_V
+`define SKY130_FD_SC_HD__A311O_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X , and0_out, C1, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X , and0_out, C1, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X, and0_out, C1, B1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X, and0_out, C1, B1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_V
+`define SKY130_FD_SC_HD__A2111OI_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_0_V
+`define SKY130_FD_SC_HD__A2111OI_0_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_0 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_0 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_1_V
+`define SKY130_FD_SC_HD__A2111OI_1_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_4_V
+`define SKY130_FD_SC_HD__A2111OI_4_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111OI_2_V
+`define SKY130_FD_SC_HD__A2111OI_2_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ * Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111oi_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_4_V
+`define SKY130_FD_SC_HD__OR3B_4_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_4 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_4 (
+ X ,
+ A ,
+ B ,
+ C_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_2_V
+`define SKY130_FD_SC_HD__OR3B_2_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_2 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_2 (
+ X ,
+ A ,
+ B ,
+ C_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_V
+`define SKY130_FD_SC_HD__OR3B_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , C_N );
+ or or0 (or0_out_X , B, A, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , C_N );
+ or or0 (or0_out_X , B, A, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+ X ,
+ A ,
+ B ,
+ C_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , C_N );
+ or or0 (or0_out_X, B, A, not0_out );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3b (
+ X ,
+ A ,
+ B ,
+ C_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , C_N );
+ or or0 (or0_out_X, B, A, not0_out );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3B_1_V
+`define SKY130_FD_SC_HD__OR3B_1_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_1 (
+ X ,
+ A ,
+ B ,
+ C_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3b_1 (
+ X ,
+ A ,
+ B ,
+ C_N
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3b base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C_N(C_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_8_V
+`define SKY130_FD_SC_HD__BUFINV_8_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_8 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__bufinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_8 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__bufinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_16_V
+`define SKY130_FD_SC_HD__BUFINV_16_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_16 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__bufinv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufinv_16 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__bufinv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFINV_V
+`define SKY130_FD_SC_HD__BUFINV_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufinv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFINV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
+ X ,
+ A ,
+ VPWRIN,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input VPWRIN;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A),
+ .VPWRIN(VPWRIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire VPWRIN;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+ X ,
+ A ,
+ VPWRIN,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWRIN;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+ X ,
+ A ,
+ VPWRIN,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWRIN;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
+ X ,
+ A ,
+ VPWRIN,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input VPWRIN;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A),
+ .VPWRIN(VPWRIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire VPWRIN;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+
+/**
+ * lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer,
+ * vpb/vnb taps, double-row-height
+ * cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
+ * size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
+ X ,
+ A ,
+ VPWRIN,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input VPWRIN;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A),
+ .VPWRIN(VPWRIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire VPWRIN;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s25 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s25 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s25 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+
+/**
+ * clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s25 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s25 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s25_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s25 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_V
+`define SKY130_FD_SC_HD__A2111O_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , C1, B1, and0_out, D1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , C1, B1, and0_out, D1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, C1, B1, and0_out, D1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, C1, B1, and0_out, D1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_2_V
+`define SKY130_FD_SC_HD__A2111O_2_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_1_V
+`define SKY130_FD_SC_HD__A2111O_1_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_4_V
+`define SKY130_FD_SC_HD__A2111O_4_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ * X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2111o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2111O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_4_V
+`define SKY130_FD_SC_HD__XOR2_4_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_4 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_4 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_1_V
+`define SKY130_FD_SC_HD__XOR2_1_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_1 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_1 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_V
+`define SKY130_FD_SC_HD__XOR2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X , B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Local signals
+ wire xor0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X, B, A );
+ buf buf0 (X , xor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xor0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X, B, A );
+ buf buf0 (X , xor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR2_2_V
+`define SKY130_FD_SC_HD__XOR2_2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ * X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor2_2 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_2_V
+`define SKY130_FD_SC_HD__AND3B_2_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_2 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_2 (
+ X ,
+ A_N,
+ B ,
+ C
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_V
+`define SKY130_FD_SC_HD__AND3B_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , C, not0_out, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , C, not0_out, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+ X ,
+ A_N,
+ B ,
+ C
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, C, not0_out, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and3b (
+ X ,
+ A_N,
+ B ,
+ C
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, C, not0_out, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_4_V
+`define SKY130_FD_SC_HD__AND3B_4_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_4 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_4 (
+ X ,
+ A_N,
+ B ,
+ C
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND3B_1_V
+`define SKY130_FD_SC_HD__AND3B_1_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_1 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and3b_1 (
+ X ,
+ A_N,
+ B ,
+ C
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and3b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A),
+ .LOWLVPWR(LOWLVPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire LOWLVPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A),
+ .LOWLVPWR(LOWLVPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire LOWLVPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+
+/**
+ * lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
+ * isolated well on input buffer, vpb/vnb
+ * taps, double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
+ * size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB
+);
+
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A),
+ .LOWLVPWR(LOWLVPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire LOWLVPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_V
+`define SKY130_FD_SC_HD__TAPVGND2_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ * 2 rows down.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ * rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ * rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ * rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ * rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2 ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND2_1_V
+`define SKY130_FD_SC_HD__TAPVGND2_1_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ * 2 rows down.
+ *
+ * Verilog wrapper for tapvgnd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2_1 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__tapvgnd2 base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd2_1 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__tapvgnd2 base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_1_V
+`define SKY130_FD_SC_HD__A31O_1_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_V
+`define SKY130_FD_SC_HD__A31O_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_2_V
+`define SKY130_FD_SC_HD__A31O_2_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31O_4_V
+`define SKY130_FD_SC_HD__A31O_4_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31o_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_V
+`define SKY130_FD_SC_HD__AND4BB_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+ X ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A_N, B_N );
+ and and0 (and0_out_X , nor0_out, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+ X ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A_N, B_N );
+ and and0 (and0_out_X , nor0_out, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A_N, B_N );
+ and and0 (and0_out_X, nor0_out, C, D );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4bb (
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out , A_N, B_N );
+ and and0 (and0_out_X, nor0_out, C, D );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_4_V
+`define SKY130_FD_SC_HD__AND4BB_4_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_4 (
+ X ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_4 (
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_1_V
+`define SKY130_FD_SC_HD__AND4BB_1_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_1 (
+ X ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_1 (
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4BB_2_V
+`define SKY130_FD_SC_HD__AND4BB_2_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_2 (
+ X ,
+ A_N ,
+ B_N ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B_N ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4bb_2 (
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4bb base (
+ .X(X),
+ .A_N(A_N),
+ .B_N(B_N),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4BB_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_2_V
+`define SKY130_FD_SC_HD__DFXBP_2_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_2 (
+ Q ,
+ Q_N,
+ CLK,
+ D
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_1_V
+`define SKY130_FD_SC_HD__DFXBP_1_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp_1 (
+ Q ,
+ Q_N,
+ CLK,
+ D
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXBP_V
+`define SKY130_FD_SC_HD__DFXBP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire CLK_delayed;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire CLK_delayed;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBP_1_V
+`define SKY130_FD_SC_HD__DLXBP_1_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBP_V
+`define SKY130_FD_SC_HD__DLXBP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+ Q ,
+ Q_N ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+ Q ,
+ Q_N ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire GATE_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+ Q ,
+ Q_N ,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbp (
+ Q ,
+ Q_N ,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire GATE_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBP_1_V
+`define SKY130_FD_SC_HD__DFBBP_1_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dfbbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfbbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK(CLK),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfbbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK(CLK),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBP_V
+`define SKY130_FD_SC_HD__DFBBP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET;
+ wire SET ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ wire CLK_delayed ;
+ wire RESET_B_delayed;
+ wire SET_B_delayed ;
+ reg notifier ;
+ wire D_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Local signals
+ wire RESET;
+ wire SET ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ wire CLK_delayed ;
+ wire RESET_B_delayed;
+ wire SET_B_delayed ;
+ reg notifier ;
+ wire D_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_V
+`define SKY130_FD_SC_HD__SDFRTN_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intclk , CLK_N );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_N_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intclk , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intclk , CLK_N );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_N_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intclk , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTN_1_V
+`define SKY130_FD_SC_HD__SDFRTN_1_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn_1 (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrtn base (
+ .Q(Q),
+ .CLK_N(CLK_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtn_1 (
+ Q ,
+ CLK_N ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrtn base (
+ .Q(Q),
+ .CLK_N(CLK_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_1_V
+`define SKY130_FD_SC_HD__TAPVGND_1_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ * 1 row down.
+ *
+ * Verilog wrapper for tapvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd_1 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__tapvgnd base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd_1 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__tapvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_V
+`define SKY130_FD_SC_HD__TAPVGND_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ * 1 row down.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ * row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ * row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ * row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ * row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvgnd ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVGND_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_1_V
+`define SKY130_FD_SC_HD__O32A_1_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_4_V
+`define SKY130_FD_SC_HD__O32A_4_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_V
+`define SKY130_FD_SC_HD__O32A_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X , or0_out, or1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X , or0_out, or1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X, or0_out, or1_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o32a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X, or0_out, or1_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O32A_2_V
+`define SKY130_FD_SC_HD__O32A_2_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o32a_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o32a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O32A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_2_V
+`define SKY130_FD_SC_HD__A21O_2_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_2 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_V
+`define SKY130_FD_SC_HD__A21O_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X , and0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21o (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ or or0 (or0_out_X, and0_out, B1 );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_1_V
+`define SKY130_FD_SC_HD__A21O_1_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_1 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21O_4_V
+`define SKY130_FD_SC_HD__A21O_4_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ * X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21o_4 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_1_V
+`define SKY130_FD_SC_HD__SDFSTP_1_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_V
+`define SKY130_FD_SC_HD__SDFSTP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_4_V
+`define SKY130_FD_SC_HD__SDFSTP_4_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfstp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSTP_2_V
+`define SKY130_FD_SC_HD__SDFSTP_2_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfstp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfstp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfstp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_8_V
+`define SKY130_FD_SC_HD__EBUFN_8_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_8 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_8 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_4_V
+`define SKY130_FD_SC_HD__EBUFN_4_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_4 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_4 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_2_V
+`define SKY130_FD_SC_HD__EBUFN_2_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_2 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_2 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_V
+`define SKY130_FD_SC_HD__EBUFN_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_teb;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
+ bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_teb;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
+ bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+ Z ,
+ A ,
+ TE_B
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Name Output Other arguments
+ bufif0 bufif00 (Z , A, TE_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__ebufn (
+ Z ,
+ A ,
+ TE_B
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ bufif0 bufif00 (Z , A, TE_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EBUFN_1_V
+`define SKY130_FD_SC_HD__EBUFN_1_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_1 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__ebufn_1 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__ebufn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EBUFN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_4_V
+`define SKY130_FD_SC_HD__O311A_4_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_2_V
+`define SKY130_FD_SC_HD__O311A_2_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_1_V
+`define SKY130_FD_SC_HD__O311A_1_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311a_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311A_V
+`define SKY130_FD_SC_HD__O311A_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X , or0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X , or0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X, or0_out, B1, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X, or0_out, B1, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, A, SLEEP );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, A, SLEEP );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+ X ,
+ A ,
+ SLEEP
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Name Output Other arguments
+ or or0 (X , A, SLEEP );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p (
+ X ,
+ A ,
+ SLEEP
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ or or0 (X , A, SLEEP );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+
+/**
+ * lpflow_inputiso1p: Input isolation, noninverted sleep.
+ *
+ * X = (A & !SLEEP)
+ *
+ * Verilog wrapper for lpflow_inputiso1p with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_inputiso1p base (
+ .X(X),
+ .A(A),
+ .SLEEP(SLEEP),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
+ X ,
+ A ,
+ SLEEP
+);
+
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_inputiso1p base (
+ .X(X),
+ .A(A),
+ .SLEEP(SLEEP)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_4_V
+`define SKY130_FD_SC_HD__OR3_4_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_4 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_V
+`define SKY130_FD_SC_HD__OR3_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , B, A, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , B, A, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, B, A, C );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, B, A, C );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_1_V
+`define SKY130_FD_SC_HD__OR3_1_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_1 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR3_2_V
+`define SKY130_FD_SC_HD__OR3_2_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or3_2 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_2_V
+`define SKY130_FD_SC_HD__NAND2B_2_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_2 (
+ Y ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_2 (
+ Y ,
+ A_N,
+ B
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_4_V
+`define SKY130_FD_SC_HD__NAND2B_4_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_4 (
+ Y ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_4 (
+ Y ,
+ A_N,
+ B
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_1_V
+`define SKY130_FD_SC_HD__NAND2B_1_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_1 (
+ Y ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand2b_1 (
+ Y ,
+ A_N,
+ B
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand2b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND2B_V
+`define SKY130_FD_SC_HD__NAND2B_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+ Y ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B );
+ or or0 (or0_out_Y , not0_out, A_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+ Y ,
+ A_N ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B );
+ or or0 (or0_out_Y , not0_out, A_N );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+ Y ,
+ A_N,
+ B
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B );
+ or or0 (or0_out_Y, not0_out, A_N );
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand2b (
+ Y ,
+ A_N,
+ B
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B );
+ or or0 (or0_out_Y, not0_out, A_N );
+ buf buf0 (Y , or0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_4_V
+`define SKY130_FD_SC_HD__O22A_4_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_2_V
+`define SKY130_FD_SC_HD__O22A_2_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_1_V
+`define SKY130_FD_SC_HD__O22A_1_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o22a_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o22a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O22A_V
+`define SKY130_FD_SC_HD__O22A_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X , or0_out, or1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X , or0_out, or1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X, or0_out, or1_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o22a (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ or or1 (or1_out , B2, B1 );
+ and and0 (and0_out_X, or0_out, or1_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O22A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_V
+`define SKY130_FD_SC_HD__A21OI_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21oi (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A1, A2 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_1_V
+`define SKY130_FD_SC_HD__A21OI_1_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_4_V
+`define SKY130_FD_SC_HD__A21OI_4_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_4 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21OI_2_V
+`define SKY130_FD_SC_HD__A21OI_2_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21oi_2 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_2_V
+`define SKY130_FD_SC_HD__AND2_2_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_2 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_4_V
+`define SKY130_FD_SC_HD__AND2_4_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_4 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_4 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_V
+`define SKY130_FD_SC_HD__AND2_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and2 (
+ X,
+ A,
+ B
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, B );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_0_V
+`define SKY130_FD_SC_HD__AND2_0_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_0 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_0 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND2_1_V
+`define SKY130_FD_SC_HD__AND2_1_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_1 (
+ X ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and2_1 (
+ X,
+ A,
+ B
+);
+
+ output X;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and2 base (
+ .X(X),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_0_V
+`define SKY130_FD_SC_HD__EINVN_0_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_0 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_0 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_4_V
+`define SKY130_FD_SC_HD__EINVN_4_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_4 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_4 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_1_V
+`define SKY130_FD_SC_HD__EINVN_1_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_1 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_1 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_V
+`define SKY130_FD_SC_HD__EINVN_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_teb;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
+ notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_teb;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
+ notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+ Z ,
+ A ,
+ TE_B
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Name Output Other arguments
+ notif0 notif00 (Z , A, TE_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvn (
+ Z ,
+ A ,
+ TE_B
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ notif0 notif00 (Z , A, TE_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_2_V
+`define SKY130_FD_SC_HD__EINVN_2_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_2 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_2 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVN_8_V
+`define SKY130_FD_SC_HD__EINVN_8_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_8 (
+ Z ,
+ A ,
+ TE_B,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvn_8 (
+ Z ,
+ A ,
+ TE_B
+);
+
+ output Z ;
+ input A ;
+ input TE_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvn base (
+ .Z(Z),
+ .A(A),
+ .TE_B(TE_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVN_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_V
+`define SKY130_FD_SC_HD__PROBE_P_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probe_p (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBE_P_8_V
+`define SKY130_FD_SC_HD__PROBE_P_8_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog wrapper for probe_p with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probe_p_8 (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+ sky130_fd_sc_hd__probe_p base (
+ .X(X),
+ .A(A),
+ .VGND(VGND),
+ .VNB(VNB),
+ .VPB(VPB),
+ .VPWR(VPWR)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probe_p_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply0 VGND;
+ supply0 VNB ;
+ supply1 VPB ;
+ supply1 VPWR;
+
+ sky130_fd_sc_hd__probe_p base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBE_P_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_1_V
+`define SKY130_FD_SC_HD__INV_1_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_1 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_1 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_2_V
+`define SKY130_FD_SC_HD__INV_2_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_2 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_2 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_6_V
+`define SKY130_FD_SC_HD__INV_6_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_6 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_6 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_16_V
+`define SKY130_FD_SC_HD__INV_16_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_16 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_16 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_4_V
+`define SKY130_FD_SC_HD__INV_4_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_4 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_4 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_8_V
+`define SKY130_FD_SC_HD__INV_8_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_8 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_8 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_12_V
+`define SKY130_FD_SC_HD__INV_12_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_12 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__inv_12 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__inv base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__INV_V
+`define SKY130_FD_SC_HD__INV_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__inv (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__INV_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_2_V
+`define SKY130_FD_SC_HD__FA_2_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_2 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_2 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_4_V
+`define SKY130_FD_SC_HD__FA_4_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_4 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_4 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_1_V
+`define SKY130_FD_SC_HD__FA_1_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fa_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fa base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FA_V
+`define SKY130_FD_SC_HD__FA_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire and2_out ;
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or1_out_COUT ;
+ wire pwrgood_pp0_out_COUT;
+ wire or2_out_SUM ;
+ wire pwrgood_pp1_out_SUM ;
+
+ // Name Output Other arguments
+ or or0 (or0_out , CIN, B );
+ and and0 (and0_out , or0_out, A );
+ and and1 (and1_out , B, CIN );
+ or or1 (or1_out_COUT , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+ buf buf0 (COUT , pwrgood_pp0_out_COUT );
+ and and2 (and2_out , CIN, A, B );
+ nor nor0 (nor0_out , A, or0_out );
+ nor nor1 (nor1_out , nor0_out, COUT );
+ or or2 (or2_out_SUM , nor1_out, and2_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+ buf buf1 (SUM , pwrgood_pp1_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire and2_out ;
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or1_out_COUT ;
+ wire pwrgood_pp0_out_COUT;
+ wire or2_out_SUM ;
+ wire pwrgood_pp1_out_SUM ;
+
+ // Name Output Other arguments
+ or or0 (or0_out , CIN, B );
+ and and0 (and0_out , or0_out, A );
+ and and1 (and1_out , B, CIN );
+ or or1 (or1_out_COUT , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+ buf buf0 (COUT , pwrgood_pp0_out_COUT );
+ and and2 (and2_out , CIN, A, B );
+ nor nor0 (nor0_out , A, or0_out );
+ nor nor1 (nor1_out , nor0_out, COUT );
+ or or2 (or2_out_SUM , nor1_out, and2_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+ buf buf1 (SUM , pwrgood_pp1_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire and2_out ;
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or1_out_COUT;
+ wire or2_out_SUM ;
+
+ // Name Output Other arguments
+ or or0 (or0_out , CIN, B );
+ and and0 (and0_out , or0_out, A );
+ and and1 (and1_out , B, CIN );
+ or or1 (or1_out_COUT, and1_out, and0_out);
+ buf buf0 (COUT , or1_out_COUT );
+ and and2 (and2_out , CIN, A, B );
+ nor nor0 (nor0_out , A, or0_out );
+ nor nor1 (nor1_out , nor0_out, COUT );
+ or or2 (or2_out_SUM , nor1_out, and2_out);
+ buf buf1 (SUM , or2_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fa (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire and2_out ;
+ wire nor0_out ;
+ wire nor1_out ;
+ wire or1_out_COUT;
+ wire or2_out_SUM ;
+
+ // Name Output Other arguments
+ or or0 (or0_out , CIN, B );
+ and and0 (and0_out , or0_out, A );
+ and and1 (and1_out , B, CIN );
+ or or1 (or1_out_COUT, and1_out, and0_out);
+ buf buf0 (COUT , or1_out_COUT );
+ and and2 (and2_out , CIN, A, B );
+ nor nor0 (nor0_out , A, or0_out );
+ nor nor1 (nor1_out , nor0_out, COUT );
+ or or2 (or2_out_SUM , nor1_out, and2_out);
+ buf buf1 (SUM , or2_out_SUM );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FA_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog wrapper for tapvpwrvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd_1 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__tapvpwrvgnd base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__tapvpwrvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tapvpwrvgnd ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAPVPWRVGND_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlygate4sd3 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd3_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlygate4sd3 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_2_V
+`define SKY130_FD_SC_HD__OR2B_2_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_2 (
+ X ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_2 (
+ X ,
+ A ,
+ B_N
+);
+
+ output X ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_4_V
+`define SKY130_FD_SC_HD__OR2B_4_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_4 (
+ X ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_4 (
+ X ,
+ A ,
+ B_N
+);
+
+ output X ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_1_V
+`define SKY130_FD_SC_HD__OR2B_1_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_1 (
+ X ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or2b_1 (
+ X ,
+ A ,
+ B_N
+);
+
+ output X ;
+ input A ;
+ input B_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or2b base (
+ .X(X),
+ .A(A),
+ .B_N(B_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR2B_V
+`define SKY130_FD_SC_HD__OR2B_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+ X ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B_N );
+ or or0 (or0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+ X ,
+ A ,
+ B_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B_N );
+ or or0 (or0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+ X ,
+ A ,
+ B_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B_N;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B_N );
+ or or0 (or0_out_X, not0_out, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or2b (
+ X ,
+ A ,
+ B_N
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , B_N );
+ or or0 (or0_out_X, not0_out, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR2B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_1_V
+`define SKY130_FD_SC_HD__XNOR3_1_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_1 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_4_V
+`define SKY130_FD_SC_HD__XNOR3_4_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_4 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_2_V
+`define SKY130_FD_SC_HD__XNOR3_2_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor3_2 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR3_V
+`define SKY130_FD_SC_HD__XNOR3_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xnor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_X , A, B, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xnor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_X , A, B, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire xnor0_out_X;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_X, A, B, C );
+ buf buf0 (X , xnor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xnor0_out_X;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_X, A, B, C );
+ buf buf0 (X , xnor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_4_V
+`define SKY130_FD_SC_HD__DFXTP_4_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_4 (
+ Q ,
+ CLK,
+ D
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_2_V
+`define SKY130_FD_SC_HD__DFXTP_2_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_2 (
+ Q ,
+ CLK,
+ D
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_V
+`define SKY130_FD_SC_HD__DFXTP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+ Q ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+ Q ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire CLK_delayed;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+ Q ,
+ CLK,
+ D
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp (
+ Q ,
+ CLK,
+ D
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire CLK_delayed;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFXTP_1_V
+`define SKY130_FD_SC_HD__DFXTP_1_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfxtp_1 (
+ Q ,
+ CLK,
+ D
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_2_V
+`define SKY130_FD_SC_HD__DLRTP_2_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog wrapper for dlrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_2 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_2 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_4_V
+`define SKY130_FD_SC_HD__DLRTP_4_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog wrapper for dlrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_4 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_4 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_V
+`define SKY130_FD_SC_HD__DLRTP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+ Q ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+ Q ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+ Q ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Local signals
+ wire RESET;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp (
+ Q ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRTP_1_V
+`define SKY130_FD_SC_HD__DLRTP_1_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ * single output.
+ *
+ * Verilog wrapper for dlrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_1 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrtp_1 (
+ Q ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrtp base (
+ .Q(Q),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_V
+`define SKY130_FD_SC_HD__FAHCIN_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire ci ;
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT ;
+ wire pwrgood_pp1_out_COUT;
+
+ // Name Output Other arguments
+ not not0 (ci , CIN );
+ xor xor0 (xor0_out_SUM , A, B, ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, ci );
+ and and2 (b_ci , B, ci );
+ or or0 (or0_out_COUT , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+ buf buf1 (COUT , pwrgood_pp1_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire ci ;
+ wire xor0_out_SUM ;
+ wire pwrgood_pp0_out_SUM ;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT ;
+ wire pwrgood_pp1_out_COUT;
+
+ // Name Output Other arguments
+ not not0 (ci , CIN );
+ xor xor0 (xor0_out_SUM , A, B, ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+ buf buf0 (SUM , pwrgood_pp0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, ci );
+ and and2 (b_ci , B, ci );
+ or or0 (or0_out_COUT , a_b, a_ci, b_ci );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+ buf buf1 (COUT , pwrgood_pp1_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Local signals
+ wire ci ;
+ wire xor0_out_SUM;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT;
+
+ // Name Output Other arguments
+ not not0 (ci , CIN );
+ xor xor0 (xor0_out_SUM, A, B, ci );
+ buf buf0 (SUM , xor0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, ci );
+ and and2 (b_ci , B, ci );
+ or or0 (or0_out_COUT, a_b, a_ci, b_ci);
+ buf buf1 (COUT , or0_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__fahcin (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ // Module ports
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire ci ;
+ wire xor0_out_SUM;
+ wire a_b ;
+ wire a_ci ;
+ wire b_ci ;
+ wire or0_out_COUT;
+
+ // Name Output Other arguments
+ not not0 (ci , CIN );
+ xor xor0 (xor0_out_SUM, A, B, ci );
+ buf buf0 (SUM , xor0_out_SUM );
+ and and0 (a_b , A, B );
+ and and1 (a_ci , A, ci );
+ and and2 (b_ci , B, ci );
+ or or0 (or0_out_COUT, a_b, a_ci, b_ci);
+ buf buf1 (COUT , or0_out_COUT );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__FAHCIN_1_V
+`define SKY130_FD_SC_HD__FAHCIN_1_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog wrapper for fahcin with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcin_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__fahcin base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__fahcin_1 (
+ COUT,
+ SUM ,
+ A ,
+ B ,
+ CIN
+);
+
+ output COUT;
+ output SUM ;
+ input A ;
+ input B ;
+ input CIN ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__fahcin base (
+ .COUT(COUT),
+ .SUM(SUM),
+ .A(A),
+ .B(B),
+ .CIN(CIN)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__FAHCIN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_2_V
+`define SKY130_FD_SC_HD__DLRBP_2_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dlrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_2 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_2 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_1_V
+`define SKY130_FD_SC_HD__DLRBP_1_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dlrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_1 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp_1 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBP_V
+`define SKY130_FD_SC_HD__DLRBP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Local signals
+ wire RESET;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbp (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
+ buf buf0 (Y , pwrgood0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
+ buf buf0 (Y , pwrgood0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Module supplies
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+
+/**
+ * lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
+ *
+ * Verilog wrapper for lpflow_clkinvkapwr with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
+ Y ,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_clkinvkapwr base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_2_V
+`define SKY130_FD_SC_HD__O21BAI_2_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_4_V
+`define SKY130_FD_SC_HD__O21BAI_4_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_V
+`define SKY130_FD_SC_HD__O21BAI_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire b ;
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , b, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire b ;
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , b, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Local signals
+ wire b ;
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, b, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21bai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire b ;
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (b , B1_N );
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, b, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21BAI_1_V
+`define SKY130_FD_SC_HD__O21BAI_1_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ * inverted.
+ *
+ * Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21bai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21bai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21BAI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_2_V
+`define SKY130_FD_SC_HD__A2BB2OI_2_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_2 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_2 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_1_V
+`define SKY130_FD_SC_HD__A2BB2OI_1_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_1 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_1 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_4_V
+`define SKY130_FD_SC_HD__A2BB2OI_4_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_4 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi_4 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2oi base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_V
+`define SKY130_FD_SC_HD__A2BB2OI_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire nor1_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ nor nor1 (nor1_out_Y , nor0_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire nor1_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ nor nor1 (nor1_out_Y , nor0_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire nor1_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ nor nor1 (nor1_out_Y, nor0_out, and0_out);
+ buf buf0 (Y , nor1_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input NOR.
+ *
+ * Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2oi (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire nor1_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ nor nor1 (nor1_out_Y, nor0_out, and0_out);
+ buf buf0 (Y , nor1_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_2_V
+`define SKY130_FD_SC_HD__A2BB2O_2_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_2 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_2 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_V
+`define SKY130_FD_SC_HD__A2BB2O_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ or or0 (or0_out_X , nor0_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ or or0 (or0_out_X , nor0_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ or or0 (or0_out_X, nor0_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ nor nor0 (nor0_out , A1_N, A2_N );
+ or or0 (or0_out_X, nor0_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_1_V
+`define SKY130_FD_SC_HD__A2BB2O_1_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_1 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_1 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2BB2O_4_V
+`define SKY130_FD_SC_HD__A2BB2O_4_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ * 2-input AND into 2nd input of 2-input OR.
+ *
+ * X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_4 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2bb2o_4 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a2bb2o base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A2BB2O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_1_V
+`define SKY130_FD_SC_HD__O2111AI_1_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_2_V
+`define SKY130_FD_SC_HD__O2111AI_2_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_4_V
+`define SKY130_FD_SC_HD__O2111AI_4_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2111ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .D1(D1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2111AI_V
+`define SKY130_FD_SC_HD__O2111AI_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ D1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input D1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2111ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1,
+ D1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+ input D1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2111AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_4_V
+`define SKY130_FD_SC_HD__A22OI_4_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_V
+`define SKY130_FD_SC_HD__A22OI_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_1_V
+`define SKY130_FD_SC_HD__A22OI_1_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22OI_2_V
+`define SKY130_FD_SC_HD__A22OI_2_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22oi_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_1_V
+`define SKY130_FD_SC_HD__DFBBN_1_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_V
+`define SKY130_FD_SC_HD__DFBBN_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ not not2 (CLK , CLK_N );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ wire CLK_N_delayed ;
+ wire RESET_B_delayed;
+ wire SET_B_delayed ;
+ reg notifier ;
+ wire D_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ not not2 (CLK , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Local signals
+ wire RESET;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ not not2 (CLK , CLK_N );
+ sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ wire CLK_N_delayed ;
+ wire RESET_B_delayed;
+ wire SET_B_delayed ;
+ reg notifier ;
+ wire D_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ not not2 (CLK , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFBBN_2_V
+`define SKY130_FD_SC_HD__DFBBN_2_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfbbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFBBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_1_V
+`define SKY130_FD_SC_HD__O21A_1_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_1 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_V
+`define SKY130_FD_SC_HD__O21A_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21a (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_4_V
+`define SKY130_FD_SC_HD__O21A_4_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_4 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21A_2_V
+`define SKY130_FD_SC_HD__O21A_2_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ * X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21a_2 (
+ X ,
+ A1,
+ A2,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_1_V
+`define SKY130_FD_SC_HD__SDFXBP_1_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_1 (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_V
+`define SKY130_FD_SC_HD__SDFXBP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFXBP_2_V
+`define SKY130_FD_SC_HD__SDFXBP_2_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfxbp_2 (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_8_V
+`define SKY130_FD_SC_HD__PROBEC_P_8_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog wrapper for probec_p with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probec_p_8 (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+ sky130_fd_sc_hd__probec_p base (
+ .X(X),
+ .A(A),
+ .VGND(VGND),
+ .VNB(VNB),
+ .VPB(VPB),
+ .VPWR(VPWR)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__probec_p_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply0 VGND;
+ supply0 VNB ;
+ supply1 VPB ;
+ supply1 VPWR;
+
+ sky130_fd_sc_hd__probec_p base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_V
+`define SKY130_FD_SC_HD__PROBEC_P_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+ X ,
+ A ,
+ VGND,
+ VNB ,
+ VPB ,
+ VPWR
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VGND;
+ input VNB ;
+ input VPB ;
+ input VPWR;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__probec_p (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__PROBEC_P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_V
+`define SKY130_FD_SC_HD__O31AI_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_1_V
+`define SKY130_FD_SC_HD__O31AI_1_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_2_V
+`define SKY130_FD_SC_HD__O31AI_2_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31AI_4_V
+`define SKY130_FD_SC_HD__O31AI_4_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31ai_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_V
+`define SKY130_FD_SC_HD__DLXBN_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (GATE , GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q ;
+ wire GATE_N_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+ wire 1 ;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1 );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q;
+
+ // Delay Name Output Other arguments
+ not not0 (GATE , GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire GATE ;
+ wire buf_Q ;
+ wire GATE_N_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+ //kunal wire 1 ;
+
+ // Name Output Other arguments
+ not not0 (GATE , GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1 );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_1_V
+`define SKY130_FD_SC_HD__DLXBN_1_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXBN_2_V
+`define SKY130_FD_SC_HD__DLXBN_2_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input GATE_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A222OI_V
+`define SKY130_FD_SC_HD__A222OI_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ C2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input C2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire nand2_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ nand nand2 (nand2_out , C2, C1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ C2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input C2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire nand2_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ nand nand2 (nand2_out , C2, C1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1,
+ C2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+ input C2;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire nand2_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ nand nand2 (nand2_out , C2, C1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a222oi (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1,
+ C2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+ input C2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire nand2_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out , B2, B1 );
+ nand nand2 (nand2_out , C2, C1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A222OI_1_V
+`define SKY130_FD_SC_HD__A222OI_1_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog wrapper for a222oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a222oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ C2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input C2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a222oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .C2(C2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a222oi_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1,
+ C2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+ input C2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a222oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .C2(C2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A222OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_2_V
+`define SKY130_FD_SC_HD__DLRBN_2_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dlrbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_2 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_2 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_V
+`define SKY130_FD_SC_HD__DLRBN_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate;
+ wire buf_Q ;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intgate, GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_N_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intgate, GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate;
+ wire buf_Q ;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intgate, GATE_N );
+ sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire intgate ;
+ reg notifier ;
+ wire D_delayed ;
+ wire GATE_N_delayed ;
+ wire RESET_delayed ;
+ wire RESET_B_delayed;
+ wire buf_Q ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intgate, GATE_N_delayed );
+ sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLRBN_1_V
+`define SKY130_FD_SC_HD__DLRBN_1_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dlrbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_1 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlrbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlrbn_1 (
+ Q ,
+ Q_N ,
+ RESET_B,
+ D ,
+ GATE_N
+);
+
+ output Q ;
+ output Q_N ;
+ input RESET_B;
+ input D ;
+ input GATE_N ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlrbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .RESET_B(RESET_B),
+ .D(D),
+ .GATE_N(GATE_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLRBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_4_V
+`define SKY130_FD_SC_HD__NAND3B_4_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_4 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_4 (
+ Y ,
+ A_N,
+ B ,
+ C
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_1_V
+`define SKY130_FD_SC_HD__NAND3B_1_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_1 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_1 (
+ Y ,
+ A_N,
+ B ,
+ C
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_V
+`define SKY130_FD_SC_HD__NAND3B_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y , B, not0_out, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y , B, not0_out, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+ Y ,
+ A_N,
+ B ,
+ C
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y, B, not0_out, C );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nand3b (
+ Y ,
+ A_N,
+ B ,
+ C
+);
+
+ // Module ports
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ nand nand0 (nand0_out_Y, B, not0_out, C );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NAND3B_2_V
+`define SKY130_FD_SC_HD__NAND3B_2_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_2 (
+ Y ,
+ A_N ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A_N ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nand3b_2 (
+ Y ,
+ A_N,
+ B ,
+ C
+);
+
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nand3b base (
+ .Y(Y),
+ .A_N(A_N),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NAND3B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire sleepn ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (sleepn , SLEEP );
+ and and0 (and0_out_X, A, sleepn );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire sleepn ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (sleepn , SLEEP );
+ and and0 (and0_out_X, A, sleepn );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+ X ,
+ A ,
+ SLEEP
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Local signals
+ wire sleepn;
+
+ // Name Output Other arguments
+ not not0 (sleepn, SLEEP );
+ and and0 (X , A, sleepn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p (
+ X ,
+ A ,
+ SLEEP
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire sleepn;
+
+ // Name Output Other arguments
+ not not0 (sleepn, SLEEP );
+ and and0 (X , A, sleepn );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+
+/**
+ * lpflow_inputiso0p: Input isolator with non-inverted enable.
+ *
+ * X = (A & !SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso0p with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
+ X ,
+ A ,
+ SLEEP,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input SLEEP;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_inputiso0p base (
+ .X(X),
+ .A(A),
+ .SLEEP(SLEEP),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
+ X ,
+ A ,
+ SLEEP
+);
+
+ output X ;
+ input A ;
+ input SLEEP;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_inputiso0p base (
+ .X(X),
+ .A(A),
+ .SLEEP(SLEEP)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_8_V
+`define SKY130_FD_SC_HD__BUFBUF_8_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_8 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__bufbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__bufbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_V
+`define SKY130_FD_SC_HD__BUFBUF_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUFBUF_16_V
+`define SKY130_FD_SC_HD__BUFBUF_16_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_16 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__bufbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__bufbuf_16 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__bufbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUFBUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_2_V
+`define SKY130_FD_SC_HD__SDFBBN_2_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_2 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_1_V
+`define SKY130_FD_SC_HD__SDFBBN_1_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn_1 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfbbn base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK_N(CLK_N),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_V
+`define SKY130_FD_SC_HD__SDFBBN_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ not not2 (CLK , CLK_N );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire CLK_N_delayed ;
+ wire SET_B_delayed ;
+ wire RESET_B_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+ wire cond_D ;
+ wire cond_SCD ;
+ wire cond_SCE ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ not not2 (CLK , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+ assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+ assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ not not2 (CLK , CLK_N );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbn (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK_N ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK_N ;
+ input SET_B ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire CLK ;
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire CLK_N_delayed ;
+ wire SET_B_delayed ;
+ wire RESET_B_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+ wire cond_D ;
+ wire cond_SCD ;
+ wire cond_SCE ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ not not2 (CLK , CLK_N_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+ assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+ assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+ buf buf0 (Q , buf_Q );
+ not not3 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_1_V
+`define SKY130_FD_SC_HD__O41A_1_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_V
+`define SKY130_FD_SC_HD__O41A_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o41a (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A4, A3, A2, A1 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_2_V
+`define SKY130_FD_SC_HD__O41A_2_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O41A_4_V
+`define SKY130_FD_SC_HD__O41A_4_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ A4 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input A4 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o41a_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ A4,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o41a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .A4(A4),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O41A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_4_V
+`define SKY130_FD_SC_HD__A31OI_4_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_1_V
+`define SKY130_FD_SC_HD__A31OI_1_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_V
+`define SKY130_FD_SC_HD__A31OI_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y , B1, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a31oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y, B1, and0_out );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A31OI_2_V
+`define SKY130_FD_SC_HD__A31OI_2_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a31oi_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a31oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A31OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ * horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s6s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlymetal6s6s base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s6s_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlymetal6s6s base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_1_V
+`define SKY130_FD_SC_HD__AND4B_1_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_1 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_1 (
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_V
+`define SKY130_FD_SC_HD__AND4B_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , not0_out, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X , not0_out, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, not0_out, B, C, D);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4b (
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ // Module ports
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , A_N );
+ and and0 (and0_out_X, not0_out, B, C, D);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_2_V
+`define SKY130_FD_SC_HD__AND4B_2_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_2 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_2 (
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4B_4_V
+`define SKY130_FD_SC_HD__AND4B_4_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_4 (
+ X ,
+ A_N ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A_N ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4b_4 (
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
+);
+
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4b base (
+ .X(X),
+ .A_N(A_N),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood0_out_A;
+ wire buf0_out_X ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
+ buf buf0 (buf0_out_X , pwrgood0_out_A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ buf buf0 (X , A );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+
+/**
+ * lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
+ * well on input buffer, no taps,
+ * double-row-height cell.
+ *
+ * Verilog wrapper for lpflow_lsbuf_lh_isowell with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
+ X ,
+ A ,
+ LOWLVPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input LOWLVPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
+ .X(X),
+ .A(A),
+ .LOWLVPWR(LOWLVPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ wire LOWLVPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+
+/**
+ * lpflow_bleeder: Current bleeder (weak pulldown to ground).
+ *
+ * Verilog wrapper for lpflow_bleeder with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder_1 (
+ SHORT,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input SHORT;
+ inout VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_bleeder base (
+ .SHORT(SHORT),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder_1 (
+ SHORT
+);
+
+ input SHORT;
+
+ // Voltage supply signals
+ wire VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_bleeder base (
+ .SHORT(SHORT)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+
+/**
+ * lpflow_bleeder: Current bleeder (weak pulldown to ground).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+ SHORT,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input SHORT;
+ inout VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+ SHORT,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input SHORT;
+ inout VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ wire gnd;
+
+ pulldown(gnd);
+ bufif1 (VPWR, gnd, SHORT);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+ SHORT
+);
+
+ input SHORT;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_bleeder (
+ SHORT
+);
+
+ input SHORT;
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_1_V
+`define SKY130_FD_SC_HD__O221A_1_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_V
+`define SKY130_FD_SC_HD__O221A_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, or1_out, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, or1_out, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, or1_out, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o221a (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire or1_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B2, B1 );
+ or or1 (or1_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, or1_out, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_4_V
+`define SKY130_FD_SC_HD__O221A_4_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O221A_2_V
+`define SKY130_FD_SC_HD__O221A_2_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ * X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o221a_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o221a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O221A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_1_V
+`define SKY130_FD_SC_HD__SDFBBP_1_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfbbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK(CLK),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp_1 (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfbbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .CLK(CLK),
+ .SET_B(SET_B),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_V
+`define SKY130_FD_SC_HD__SDFBBP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire CLK_delayed ;
+ wire SET_B_delayed ;
+ wire RESET_B_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+ wire cond_D ;
+ wire cond_SCD ;
+ wire cond_SCE ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+ assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+ assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ * clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfbbp (
+ Q ,
+ Q_N ,
+ D ,
+ SCD ,
+ SCE ,
+ CLK ,
+ SET_B ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input CLK ;
+ input SET_B ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire RESET ;
+ wire SET ;
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire CLK_delayed ;
+ wire SET_B_delayed ;
+ wire RESET_B_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire condb ;
+ wire cond_D ;
+ wire cond_SCD ;
+ wire cond_SCE ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
+ assign condb = ( cond0 & cond1 );
+ assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
+ assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
+ assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+ buf buf0 (Q , buf_Q );
+ not not2 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFBBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_4_V
+`define SKY130_FD_SC_HD__NOR4_4_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_1_V
+`define SKY130_FD_SC_HD__NOR4_1_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_1 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_V
+`define SKY130_FD_SC_HD__NOR4_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , A, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y , A, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, A, B, C, D );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ nor nor0 (nor0_out_Y, A, B, C, D );
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4_2_V
+`define SKY130_FD_SC_HD__NOR4_2_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ * Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4_2 (
+ Y,
+ A,
+ B,
+ C,
+ D
+);
+
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_4_V
+`define SKY130_FD_SC_HD__O31A_4_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_2_V
+`define SKY130_FD_SC_HD__O31A_2_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_1_V
+`define SKY130_FD_SC_HD__O31A_1_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o31a_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o31a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O31A_V
+`define SKY130_FD_SC_HD__O31A_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X , or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ * X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o31a (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ and and0 (and0_out_X, or0_out, B1 );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O31A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_V
+`define SKY130_FD_SC_HD__O211A_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X , or0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, B1, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211a (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ and and0 (and0_out_X, or0_out, B1, C1);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_1_V
+`define SKY130_FD_SC_HD__O211A_1_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_2_V
+`define SKY130_FD_SC_HD__O211A_2_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211A_4_V
+`define SKY130_FD_SC_HD__O211A_4_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ * X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211a_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211a base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_1_V
+`define SKY130_FD_SC_HD__O211AI_1_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_1 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_V
+`define SKY130_FD_SC_HD__O211AI_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , C1, or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , C1, or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, C1, or0_out, B1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o211ai (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, C1, or0_out, B1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_4_V
+`define SKY130_FD_SC_HD__O211AI_4_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_4 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O211AI_2_V
+`define SKY130_FD_SC_HD__O211AI_2_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ * Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o211ai_2 (
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o211ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O211AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+ Q ,
+ D ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D, SLEEP_B, 1'b0, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+ Q ,
+ D ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire SLEEP_B_delayed;
+ wire D_delayed ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+ Q ,
+ D ,
+ SLEEP_B
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input SLEEP_B;
+
+ // Local signals
+ wire buf_Q;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch (
+ Q ,
+ D ,
+ SLEEP_B
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input SLEEP_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire SLEEP_B_delayed;
+ wire D_delayed ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+
+/**
+ * lpflow_inputisolatch: Latching input isolator with inverted enable.
+ *
+ * Verilog wrapper for lpflow_inputisolatch with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
+ Q ,
+ D ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input D ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_inputisolatch base (
+ .Q(Q),
+ .D(D),
+ .SLEEP_B(SLEEP_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
+ Q ,
+ D ,
+ SLEEP_B
+);
+
+ output Q ;
+ input D ;
+ input SLEEP_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_inputisolatch base (
+ .Q(Q),
+ .D(D),
+ .SLEEP_B(SLEEP_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_V
+`define SKY130_FD_SC_HD__SDFSBP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (SET , SET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire SET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire SET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (SET , SET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( SET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+ not not1 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_1_V
+`define SKY130_FD_SC_HD__SDFSBP_1_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFSBP_2_V
+`define SKY130_FD_SC_HD__SDFSBP_2_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfsbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ SET_B
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input SET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfsbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .SET_B(SET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFSBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
+ buf buf0 (X , pwrgood0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
+ buf buf0 (X , pwrgood0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+ X ,
+ SLEEP,
+ A
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X, not0_out, A );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc (
+ X ,
+ SLEEP,
+ A
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X, not0_out, A );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+
+/**
+ * lpflow_isobufsrc: Input isolation, noninverted sleep.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrc with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
+ X ,
+ SLEEP,
+ A ,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrc base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_12_V
+`define SKY130_FD_SC_HD__BUF_12_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_12 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_12 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_16_V
+`define SKY130_FD_SC_HD__BUF_16_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_16 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_16 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_V
+`define SKY130_FD_SC_HD__BUF_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__buf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_4_V
+`define SKY130_FD_SC_HD__BUF_4_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_4 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_1_V
+`define SKY130_FD_SC_HD__BUF_1_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_6_V
+`define SKY130_FD_SC_HD__BUF_6_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_6 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_6 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_2_V
+`define SKY130_FD_SC_HD__BUF_2_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__BUF_8_V
+`define SKY130_FD_SC_HD__BUF_8_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_8 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__buf_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__buf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__BUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s15 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s15 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s15 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s15 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s15 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s15 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s15 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_1_V
+`define SKY130_FD_SC_HD__SEDFXTP_1_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_1 (
+ Q ,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_4_V
+`define SKY130_FD_SC_HD__SEDFXTP_4_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_4 (
+ Q ,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_2_V
+`define SKY130_FD_SC_HD__SEDFXTP_2_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp_2 (
+ Q ,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sedfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_V
+`define SKY130_FD_SC_HD__SEDFXTP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+ wire de_d ;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire de_d ;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+ assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+ assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+ Q ,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+ wire de_d ;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxtp (
+ Q ,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire de_d ;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+ assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+ assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_V
+`define SKY130_FD_SC_HD__DECAP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__decap ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_3_V
+`define SKY130_FD_SC_HD__DECAP_3_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 3 units (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_3 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__decap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_3 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_4_V
+`define SKY130_FD_SC_HD__DECAP_4_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_4 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__decap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_4 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_6_V
+`define SKY130_FD_SC_HD__DECAP_6_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_6 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__decap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_6 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_6_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_12_V
+`define SKY130_FD_SC_HD__DECAP_12_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 12 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_12 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__decap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_12 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_12_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DECAP_8_V
+`define SKY130_FD_SC_HD__DECAP_8_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_8 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__decap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__decap_8 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DECAP_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_2_V
+`define SKY130_FD_SC_HD__AND4_2_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_2 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_1_V
+`define SKY130_FD_SC_HD__AND4_1_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_1 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_V
+`define SKY130_FD_SC_HD__AND4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , A, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X , A, B, C, D );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, B, C, D );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__and4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, B, C, D );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__AND4_4_V
+`define SKY130_FD_SC_HD__AND4_4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__and4_4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__and4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__AND4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s2s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlymetal6s2s base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlymetal6s2s base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ * horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlymetal6s2s (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_V
+`define SKY130_FD_SC_HD__MAJ3_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire or1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B, A );
+ and and0 (and0_out , or0_out, C );
+ and and1 (and1_out , A, B );
+ or or1 (or1_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire or1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B, A );
+ and and0 (and0_out , or0_out, C );
+ and and1 (and1_out , A, B );
+ or or1 (or1_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire or1_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B, A );
+ and and0 (and0_out , or0_out, C );
+ and and1 (and1_out , A, B );
+ or or1 (or1_out_X, and1_out, and0_out);
+ buf buf0 (X , or1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__maj3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire and0_out ;
+ wire and1_out ;
+ wire or1_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out , B, A );
+ and and0 (and0_out , or0_out, C );
+ and and1 (and1_out , A, B );
+ or or1 (or1_out_X, and1_out, and0_out);
+ buf buf0 (X , or1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_4_V
+`define SKY130_FD_SC_HD__MAJ3_4_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_4 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_1_V
+`define SKY130_FD_SC_HD__MAJ3_1_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_1 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__MAJ3_2_V
+`define SKY130_FD_SC_HD__MAJ3_2_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__maj3_2 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__maj3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__MAJ3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso0n with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_inputiso0n base (
+ .X(X),
+ .A(A),
+ .SLEEP_B(SLEEP_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_inputiso0n base (
+ .X(X),
+ .A(A),
+ .SLEEP_B(SLEEP_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, SLEEP_B );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out_X, A, SLEEP_B );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Name Output Other arguments
+ and and0 (X , A, SLEEP_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso0n: Input isolator with inverted enable.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso0n (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ and and0 (X , A, SLEEP_B );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_1_V
+`define SKY130_FD_SC_HD__O2BB2A_1_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_1 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_1 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_2_V
+`define SKY130_FD_SC_HD__O2BB2A_2_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_2 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_2 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_4_V
+`define SKY130_FD_SC_HD__O2BB2A_4_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_4 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a_4 (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2a base (
+ .X(X),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_V
+`define SKY130_FD_SC_HD__O2BB2A_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ and and0 (and0_out_X , nand0_out, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire and0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ and and0 (and0_out_X , nand0_out, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ and and0 (and0_out_X, nand0_out, or0_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ * X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2a (
+ X ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ and and0 (and0_out_X, nand0_out, or0_out);
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2A_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_V
+`define SKY130_FD_SC_HD__XOR3_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X , A, B, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xor0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X , A, B, C );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Local signals
+ wire xor0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X, A, B, C );
+ buf buf0 (X , xor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xor3 (
+ X,
+ A,
+ B,
+ C
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xor0_out_X;
+
+ // Name Output Other arguments
+ xor xor0 (xor0_out_X, A, B, C );
+ buf buf0 (X , xor0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_1_V
+`define SKY130_FD_SC_HD__XOR3_1_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_1 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_2_V
+`define SKY130_FD_SC_HD__XOR3_2_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_2 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XOR3_4_V
+`define SKY130_FD_SC_HD__XOR3_4_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ * X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xor3_4 (
+ X,
+ A,
+ B,
+ C
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xor3 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XOR3_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_4_V
+`define SKY130_FD_SC_HD__OR4_4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_V
+`define SKY130_FD_SC_HD__OR4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , D, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X , D, C, B, A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, D, C, B, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__or4 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ // Module ports
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ or or0 (or0_out_X, D, C, B, A );
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_2_V
+`define SKY130_FD_SC_HD__OR4_2_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_2 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_2 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__OR4_1_V
+`define SKY130_FD_SC_HD__OR4_1_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_1 (
+ X ,
+ A ,
+ B ,
+ C ,
+ D ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__or4_1 (
+ X,
+ A,
+ B,
+ C,
+ D
+);
+
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__or4 base (
+ .X(X),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D(D)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__OR4_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_V
+`define SKY130_FD_SC_HD__CLKINVLP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp (
+ Y,
+ A
+);
+
+ // Module ports
+ output Y;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out_Y, A );
+ buf buf0 (Y , not0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_2_V
+`define SKY130_FD_SC_HD__CLKINVLP_2_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog wrapper for clkinvlp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_2 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinvlp base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_2 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinvlp base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKINVLP_4_V
+`define SKY130_FD_SC_HD__CLKINVLP_4_V
+
+/**
+ * clkinvlp: Lower power Clock tree inverter.
+ *
+ * Verilog wrapper for clkinvlp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_4 (
+ Y ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkinvlp base (
+ .Y(Y),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkinvlp_4 (
+ Y,
+ A
+);
+
+ output Y;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkinvlp base (
+ .Y(Y),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKINVLP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_V
+`define SKY130_FD_SC_HD__SDFRTP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire mux_out ;
+ reg notifier ;
+ wire D_delayed ;
+ wire SCD_delayed ;
+ wire SCE_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+ wire cond4 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
+ assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
+ assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
+ assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+ assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_2_V
+`define SKY130_FD_SC_HD__SDFRTP_2_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_2 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_4_V
+`define SKY130_FD_SC_HD__SDFRTP_4_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_4 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SDFRTP_1_V
+`define SKY130_FD_SC_HD__SDFRTP_1_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sdfrtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ SCD ,
+ SCE ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input SCD ;
+ input SCE ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sdfrtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SCD),
+ .SCE(SCE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SDFRTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd1 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlygate4sd1 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlygate4sd1 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__dlygate4sd1 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLYGATE4SD1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_V
+`define SKY130_FD_SC_HD__O21AI_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y , B1, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o21ai (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1 );
+ nand nand0 (nand0_out_Y, B1, or0_out );
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_2_V
+`define SKY130_FD_SC_HD__O21AI_2_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_2 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_1_V
+`define SKY130_FD_SC_HD__O21AI_1_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_1 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_4_V
+`define SKY130_FD_SC_HD__O21AI_4_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_4 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O21AI_0_V
+`define SKY130_FD_SC_HD__O21AI_0_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ * Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_0 (
+ Y ,
+ A1 ,
+ A2 ,
+ B1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o21ai_0 (
+ Y ,
+ A1,
+ A2,
+ B1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o21ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O21AI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_2_V
+`define SKY130_FD_SC_HD__TAP_2_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog wrapper for tap with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_2 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__tap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_2 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__tap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_V
+`define SKY130_FD_SC_HD__TAP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap ();
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__tap ();
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+ // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__TAP_1_V
+`define SKY130_FD_SC_HD__TAP_1_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog wrapper for tap with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_1 (
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__tap base (
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__tap_1 ();
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__tap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__TAP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s50 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s50 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s50 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog wrapper for clkdlybuf4s50 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkdlybuf4s50 base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkdlybuf4s50 base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+
+/**
+ * clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
+ * gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkdlybuf4s50 (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_1_V
+`define SKY130_FD_SC_HD__A21BO_1_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_2_V
+`define SKY130_FD_SC_HD__A21BO_2_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_V
+`define SKY130_FD_SC_HD__A21BO_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out_X , B1_N, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out_X , B1_N, nand0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out_X, B1_N, nand0_out);
+ buf buf0 (X , nand1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a21bo (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out_X;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1 );
+ nand nand1 (nand1_out_X, B1_N, nand0_out);
+ buf buf0 (X , nand1_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A21BO_4_V
+`define SKY130_FD_SC_HD__A21BO_4_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ * 2nd input inverted.
+ *
+ * X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a21bo_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1_N
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a21bo base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1_N(B1_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A21BO_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_V
+`define SKY130_FD_SC_HD__A22O_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X, and1_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a22o (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X, and1_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_2_V
+`define SKY130_FD_SC_HD__A22O_2_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_1_V
+`define SKY130_FD_SC_HD__A22O_1_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A22O_4_V
+`define SKY130_FD_SC_HD__A22O_4_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a22o_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a22o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A22O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTP_1_V
+`define SKY130_FD_SC_HD__DLXTP_1_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp_1 (
+ Q ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dlxtp base (
+ .Q(Q),
+ .D(D),
+ .GATE(GATE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp_1 (
+ Q ,
+ D ,
+ GATE
+);
+
+ output Q ;
+ input D ;
+ input GATE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dlxtp base (
+ .Q(Q),
+ .D(D),
+ .GATE(GATE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DLXTP_V
+`define SKY130_FD_SC_HD__DLXTP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+ Q ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+ Q ,
+ D ,
+ GATE,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire GATE_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+ Q ,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE;
+
+ // Local signals
+ wire buf_Q;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dlxtp (
+ Q ,
+ D ,
+ GATE
+);
+
+ // Module ports
+ output Q ;
+ input D ;
+ input GATE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire GATE_delayed;
+ wire D_delayed ;
+ reg notifier ;
+ wire awake ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ assign awake = ( VPWR === 1'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DLXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_1_V
+`define SKY130_FD_SC_HD__NOR4B_1_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_1 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_V
+`define SKY130_FD_SC_HD__NOR4B_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ nor nor0 (nor0_out_Y , A, B, C, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ nor nor0 (nor0_out_Y , A, B, C, not0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Local signals
+ wire not0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ nor nor0 (nor0_out_Y, A, B, C, not0_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__nor4b (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ not not0 (not0_out , D_N );
+ nor nor0 (nor0_out_Y, A, B, C, not0_out);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_4_V
+`define SKY130_FD_SC_HD__NOR4B_4_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_4 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__NOR4B_2_V
+`define SKY130_FD_SC_HD__NOR4B_2_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__nor4b_2 (
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__nor4b base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .C(C),
+ .D_N(D_N)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__NOR4B_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_4_V
+`define SKY130_FD_SC_HD__O311AI_4_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_V
+`define SKY130_FD_SC_HD__O311AI_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y , C1, or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y , C1, or0_out, B1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y, C1, or0_out, B1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o311ai (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire or0_out ;
+ wire nand0_out_Y;
+
+ // Name Output Other arguments
+ or or0 (or0_out , A2, A1, A3 );
+ nand nand0 (nand0_out_Y, C1, or0_out, B1);
+ buf buf0 (Y , nand0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_0_V
+`define SKY130_FD_SC_HD__O311AI_0_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 0 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_0 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_0 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_0_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_1_V
+`define SKY130_FD_SC_HD__O311AI_1_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O311AI_2_V
+`define SKY130_FD_SC_HD__O311AI_2_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ * Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o311ai_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o311ai base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O311AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTN_1_V
+`define SKY130_FD_SC_HD__DFRTN_1_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for dfrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn_1 (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__dfrtn base (
+ .Q(Q),
+ .CLK_N(CLK_N),
+ .D(D),
+ .RESET_B(RESET_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn_1 (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B
+);
+
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__dfrtn base (
+ .Q(Q),
+ .CLK_N(CLK_N),
+ .D(D),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__DFRTN_V
+`define SKY130_FD_SC_HD__DFRTN_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intclk, CLK_N );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_N_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intclk, CLK_N_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk;
+
+ // Delay Name Output Other arguments
+ not not0 (RESET , RESET_B );
+ not not1 (intclk, CLK_N );
+ sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__dfrtn (
+ Q ,
+ CLK_N ,
+ D ,
+ RESET_B
+);
+
+ // Module ports
+ output Q ;
+ input CLK_N ;
+ input D ;
+ input RESET_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire RESET ;
+ wire intclk ;
+ reg notifier ;
+ wire D_delayed ;
+ wire RESET_B_delayed;
+ wire CLK_N_delayed ;
+ wire awake ;
+ wire cond0 ;
+ wire cond1 ;
+
+ // Name Output Other arguments
+ not not0 (RESET , RESET_B_delayed );
+ not not1 (intclk, CLK_N_delayed );
+ sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
+ assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__DFRTN_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_16_V
+`define SKY130_FD_SC_HD__CLKBUF_16_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_16 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_16 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_1_V
+`define SKY130_FD_SC_HD__CLKBUF_1_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_1 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_1 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_4_V
+`define SKY130_FD_SC_HD__CLKBUF_4_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_4 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_4 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_V
+`define SKY130_FD_SC_HD__CLKBUF_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X , A );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+ buf buf1 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf (
+ X,
+ A
+);
+
+ // Module ports
+ output X;
+ input A;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf0_out_X;
+
+ // Name Output Other arguments
+ buf buf0 (buf0_out_X, A );
+ buf buf1 (X , buf0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_2_V
+`define SKY130_FD_SC_HD__CLKBUF_2_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_2 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_2 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__CLKBUF_8_V
+`define SKY130_FD_SC_HD__CLKBUF_8_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_8 (
+ X ,
+ A ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__clkbuf_8 (
+ X,
+ A
+);
+
+ output X;
+ input A;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__clkbuf base (
+ .X(X),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__CLKBUF_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog wrapper for lpflow_isobufsrckapwr with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
+ X ,
+ SLEEP,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A),
+ .KAPWR(KAPWR),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
+ X ,
+ SLEEP,
+ A
+);
+
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Voltage supply signals
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
+ .X(X),
+ .SLEEP(SLEEP),
+ .A(A)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+ X ,
+ SLEEP,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood0_out_X ;
+ wire pwrgood1_out_x2;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
+ buf buf0 (X , pwrgood1_out_x2 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+ X ,
+ SLEEP,
+ A ,
+ KAPWR,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+ input KAPWR;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X ;
+ wire pwrgood0_out_X ;
+ wire pwrgood1_out_x2;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X , not0_out, A );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
+ buf buf0 (X , pwrgood1_out_x2 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+ X ,
+ SLEEP,
+ A
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X, not0_out, A );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+
+/**
+ * lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
+ * keep-alive power rail.
+ *
+ * X = (!A | SLEEP)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
+ X ,
+ SLEEP,
+ A
+);
+
+ // Module ports
+ output X ;
+ input SLEEP;
+ input A ;
+
+ // Module supplies
+ supply1 KAPWR;
+ supply1 VPWR ;
+ supply0 VGND ;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire not0_out ;
+ wire and0_out_X;
+
+ // Name Output Other arguments
+ not not0 (not0_out , SLEEP );
+ and and0 (and0_out_X, not0_out, A );
+ buf buf0 (X , and0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_V
+`define SKY130_FD_SC_HD__EDFXTP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+ Q ,
+ CLK,
+ D ,
+ DE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp (
+ Q ,
+ CLK,
+ D ,
+ DE
+);
+
+ // Module ports
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire awake ;
+ wire cond0 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
+ buf buf0 (Q , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EDFXTP_1_V
+`define SKY130_FD_SC_HD__EDFXTP_1_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ * single output.
+ *
+ * Verilog wrapper for edfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp_1 (
+ Q ,
+ CLK ,
+ D ,
+ DE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__edfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__edfxtp_1 (
+ Q ,
+ CLK,
+ D ,
+ DE
+);
+
+ output Q ;
+ input CLK;
+ input D ;
+ input DE ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__edfxtp base (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EDFXTP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_2_V
+`define SKY130_FD_SC_HD__A32O_2_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_2 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_1_V
+`define SKY130_FD_SC_HD__A32O_1_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_1 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_4_V
+`define SKY130_FD_SC_HD__A32O_4_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32o_4 (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32O_V
+`define SKY130_FD_SC_HD__A32O_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ and and1 (and1_out , B1, B2 );
+ or or0 (or0_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+ X ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ and and1 (and1_out , B1, B2 );
+ or or0 (or0_out_X , and1_out, and0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ and and1 (and1_out , B1, B2 );
+ or or0 (or0_out_X, and1_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input OR.
+ *
+ * X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32o (
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ and and1 (and1_out , B1, B2 );
+ or or0 (or0_out_X, and1_out, and0_out);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog wrapper for lpflow_inputiso1n with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__lpflow_inputiso1n base (
+ .X(X),
+ .A(A),
+ .SLEEP_B(SLEEP_B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__lpflow_inputiso1n base (
+ .X(X),
+ .A(A),
+ .SLEEP_B(SLEEP_B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire SLEEP ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (SLEEP , SLEEP_B );
+ or or0 (or0_out_X, A, SLEEP );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+ X ,
+ A ,
+ SLEEP_B,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire SLEEP ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ not not0 (SLEEP , SLEEP_B );
+ or or0 (or0_out_X, A, SLEEP );
+ sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Local signals
+ wire SLEEP;
+
+ // Name Output Other arguments
+ not not0 (SLEEP , SLEEP_B );
+ or or0 (X , A, SLEEP );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+
+/**
+ * lpflow_inputiso1n: Input isolation, inverted sleep.
+ *
+ * X = (A & SLEEP_B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__lpflow_inputiso1n (
+ X ,
+ A ,
+ SLEEP_B
+);
+
+ // Module ports
+ output X ;
+ input A ;
+ input SLEEP_B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire SLEEP;
+
+ // Name Output Other arguments
+ not not0 (SLEEP , SLEEP_B );
+ or or0 (X , A, SLEEP );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_V
+`define SKY130_FD_SC_HD__A221O_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X , and1_out, and0_out, C1);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X ;
+ wire pwrgood_pp0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X , and1_out, and0_out, C1);
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
+ buf buf0 (X , pwrgood_pp0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X, and1_out, and0_out, C1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a221o (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ // Module ports
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire and1_out ;
+ wire or0_out_X;
+
+ // Name Output Other arguments
+ and and0 (and0_out , B1, B2 );
+ and and1 (and1_out , A1, A2 );
+ or or0 (or0_out_X, and1_out, and0_out, C1);
+ buf buf0 (X , or0_out_X );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_4_V
+`define SKY130_FD_SC_HD__A221O_4_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_4 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_4 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_1_V
+`define SKY130_FD_SC_HD__A221O_1_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_1 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_1 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A221O_2_V
+`define SKY130_FD_SC_HD__A221O_2_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ * X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_2 (
+ X ,
+ A1 ,
+ A2 ,
+ B1 ,
+ B2 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output X ;
+ input A1 ;
+ input A2 ;
+ input B1 ;
+ input B2 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a221o_2 (
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
+);
+
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a221o base (
+ .X(X),
+ .A1(A1),
+ .A2(A2),
+ .B1(B1),
+ .B2(B2),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A221O_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_V
+`define SKY130_FD_SC_HD__A311OI_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y , and0_out, B1, C1 );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, B1, C1);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a311oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire and0_out ;
+ wire nor0_out_Y;
+
+ // Name Output Other arguments
+ and and0 (and0_out , A3, A1, A2 );
+ nor nor0 (nor0_out_Y, and0_out, B1, C1);
+ buf buf0 (Y , nor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_2_V
+`define SKY130_FD_SC_HD__A311OI_2_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_4_V
+`define SKY130_FD_SC_HD__A311OI_4_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A311OI_1_V
+`define SKY130_FD_SC_HD__A311OI_1_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ C1 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input C1 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a311oi_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ C1
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input C1;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a311oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .C1(C1)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A311OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_1_V
+`define SKY130_FD_SC_HD__XNOR2_1_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_1 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_1 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_V
+`define SKY130_FD_SC_HD__XNOR2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xnor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_Y , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire xnor0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_Y , A, B );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Local signals
+ wire xnor0_out_Y;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_Y, A, B );
+ buf buf0 (Y , xnor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__xnor2 (
+ Y,
+ A,
+ B
+);
+
+ // Module ports
+ output Y;
+ input A;
+ input B;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire xnor0_out_Y;
+
+ // Name Output Other arguments
+ xnor xnor0 (xnor0_out_Y, A, B );
+ buf buf0 (Y , xnor0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_4_V
+`define SKY130_FD_SC_HD__XNOR2_4_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_4 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_4 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__XNOR2_2_V
+`define SKY130_FD_SC_HD__XNOR2_2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ * Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_2 (
+ Y ,
+ A ,
+ B ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A ;
+ input B ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__xnor2_2 (
+ Y,
+ A,
+ B
+);
+
+ output Y;
+ input A;
+ input B;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__xnor2 base (
+ .Y(Y),
+ .A(A),
+ .B(B)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__XNOR2_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_1_V
+`define SKY130_FD_SC_HD__SEDFXBP_1_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_1 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sedfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_1 (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sedfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_2_V
+`define SKY130_FD_SC_HD__SEDFXBP_2_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_2 (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__sedfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp_2 (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__sedfxbp base (
+ .Q(Q),
+ .Q_N(Q_N),
+ .CLK(CLK),
+ .D(D),
+ .DE(DE),
+ .SCD(SCD),
+ .SCE(SCE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_V
+`define SKY130_FD_SC_HD__SEDFXBP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+ wire de_d ;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+ Q ,
+ Q_N ,
+ CLK ,
+ D ,
+ DE ,
+ SCD ,
+ SCE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Q ;
+ output Q_N ;
+ input CLK ;
+ input D ;
+ input DE ;
+ input SCD ;
+ input SCE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire de_d ;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+ assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+ assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Local signals
+ wire buf_Q ;
+ wire mux_out;
+ wire de_d ;
+
+ // Delay Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
+ sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ * complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__sedfxbp (
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
+);
+
+ // Module ports
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire buf_Q ;
+ reg notifier ;
+ wire D_delayed ;
+ wire DE_delayed ;
+ wire SCD_delayed;
+ wire SCE_delayed;
+ wire CLK_delayed;
+ wire mux_out ;
+ wire de_d ;
+ wire awake ;
+ wire cond1 ;
+ wire cond2 ;
+ wire cond3 ;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
+ sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
+ sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
+ assign awake = ( VPWR === 1'b1 );
+ assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
+ assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
+ assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
+ buf buf0 (Q , buf_Q );
+ not not0 (Q_N , buf_Q );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__SEDFXBP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_4_V
+`define SKY130_FD_SC_HD__EINVP_4_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_4 (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_4 (
+ Z ,
+ A ,
+ TE
+);
+
+ output Z ;
+ input A ;
+ input TE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_1_V
+`define SKY130_FD_SC_HD__EINVP_1_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_1 (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_1 (
+ Z ,
+ A ,
+ TE
+);
+
+ output Z ;
+ input A ;
+ input TE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_2_V
+`define SKY130_FD_SC_HD__EINVP_2_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_2 (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_2 (
+ Z ,
+ A ,
+ TE
+);
+
+ output Z ;
+ input A ;
+ input TE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_8_V
+`define SKY130_FD_SC_HD__EINVP_8_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_8 (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__einvp_8 (
+ Z ,
+ A ,
+ TE
+);
+
+ output Z ;
+ input A ;
+ input TE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__einvp base (
+ .Z(Z),
+ .A(A),
+ .TE(TE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_8_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__EINVP_V
+`define SKY130_FD_SC_HD__EINVP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_TE;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
+ notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+ Z ,
+ A ,
+ TE ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire pwrgood_pp0_out_A ;
+ wire pwrgood_pp1_out_TE;
+
+ // Name Output Other arguments
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
+ notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+ Z ,
+ A ,
+ TE
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE;
+
+ // Name Output Other arguments
+ notif1 notif10 (Z , A, TE );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__einvp (
+ Z ,
+ A ,
+ TE
+);
+
+ // Module ports
+ output Z ;
+ input A ;
+ input TE;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Name Output Other arguments
+ notif1 notif10 (Z , A, TE );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__EINVP_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_4_V
+`define SKY130_FD_SC_HD__A32OI_4_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_4 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_4 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_2_V
+`define SKY130_FD_SC_HD__A32OI_2_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_2 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_2 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_V
+`define SKY130_FD_SC_HD__A32OI_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1, A3 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1, A3 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y , nand0_out, nand1_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1, A3 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a32oi (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire nand1_out ;
+ wire and0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2, A1, A3 );
+ nand nand1 (nand1_out , B2, B1 );
+ and and0 (and0_out_Y, nand0_out, nand1_out);
+ buf buf0 (Y , and0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A32OI_1_V
+`define SKY130_FD_SC_HD__A32OI_1_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ * 2nd input of 2-input NOR.
+ *
+ * Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_1 (
+ Y ,
+ A1 ,
+ A2 ,
+ A3 ,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1 ;
+ input A2 ;
+ input A3 ;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a32oi_1 (
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
+);
+
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__a32oi base (
+ .Y(Y),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__A32OI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_2_V
+`define SKY130_FD_SC_HD__O2BB2AI_2_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_2 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_2 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_2_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_1_V
+`define SKY130_FD_SC_HD__O2BB2AI_1_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_1 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_1 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_1_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_4_V
+`define SKY130_FD_SC_HD__O2BB2AI_4_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_4 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai_4 (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__o2bb2ai base (
+ .Y(Y),
+ .A1_N(A1_N),
+ .A2_N(A2_N),
+ .B1(B1),
+ .B2(B2)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_4_V
+
+
+//--------EOF---------
+
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_V
+`define SKY130_FD_SC_HD__O2BB2AI_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire nand1_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ nand nand1 (nand1_out_Y , nand0_out, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2 ,
+ VPWR,
+ VGND,
+ VPB ,
+ VNB
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+ input VPWR;
+ input VGND;
+ input VPB ;
+ input VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire nand1_out_Y ;
+ wire pwrgood_pp0_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ nand nand1 (nand1_out_Y , nand0_out, or0_out );
+ sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+ buf buf0 (Y , pwrgood_pp0_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
+`endif // FUNCTIONAL
+
+`else // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire nand1_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ nand nand1 (nand1_out_Y, nand0_out, or0_out);
+ buf buf0 (Y , nand1_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
+`else // FUNCTIONAL
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ * Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__o2bb2ai (
+ Y ,
+ A1_N,
+ A2_N,
+ B1 ,
+ B2
+);
+
+ // Module ports
+ output Y ;
+ input A1_N;
+ input A2_N;
+ input B1 ;
+ input B2 ;
+
+ // Module supplies
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ // Local signals
+ wire nand0_out ;
+ wire or0_out ;
+ wire nand1_out_Y;
+
+ // Name Output Other arguments
+ nand nand0 (nand0_out , A2_N, A1_N );
+ or or0 (or0_out , B2, B1 );
+ nand nand1 (nand1_out_Y, nand0_out, or0_out);
+ buf buf0 (Y , nand1_out_Y );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_FD_SC_HD__O2BB2AI_V
+
+
+//--------EOF---------
+
diff --git a/Simulations/pre_synthesis/a.out b/Simulations/pre_synthesis/a.out
new file mode 100644
index 0000000..a3dddca
--- /dev/null
+++ b/Simulations/pre_synthesis/a.out
@@ -0,0 +1,402 @@
+#! c:/iverilog-x64/bin/vvp
+:ivl_version "10.1 (stable)" "(v10_1_1)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_00000000028325b0 .scope module, "fxd2float_tb" "fxd2float_tb" 2 1;
+ .timescale 0 0;
+P_00000000027f2ed0 .param/l "exp" 0 2 4, +C4<00000000000000000000000000001000>;
+P_00000000027f2f08 .param/l "in" 0 2 2, +C4<00000000000000000000000000010011>;
+P_00000000027f2f40 .param/l "man" 0 2 3, +C4<00000000000000000000000000010111>;
+v00000000028c9140_0 .var "a", 18 0;
+v00000000028c91e0_0 .net "b", 31 0, L_0000000002939ec0; 1 drivers
+v00000000028ca360_0 .net "zro", 0 0, L_00000000028d0730; 1 drivers
+S_0000000002832730 .scope module, "u1" "fxd2flot" 2 10, 3 37 0, S_00000000028325b0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 19 "a"
+ .port_info 1 /OUTPUT 32 "b"
+ .port_info 2 /OUTPUT 1 "zro"
+P_00000000028328b0 .param/l "exp" 0 3 41, +C4<00000000000000000000000000001000>;
+P_00000000028328e8 .param/l "in" 0 3 39, +C4<00000000000000000000000000010011>;
+P_0000000002832920 .param/l "man" 0 3 40, +C4<00000000000000000000000000010111>;
+L_00000000028e00d0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v00000000028c9a00_0 .net/2u *"_s0", 5 0, L_00000000028e00d0; 1 drivers
+L_00000000028e0118 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
+v00000000028ca180_0 .net/2u *"_s10", 2 0, L_00000000028e0118; 1 drivers
+v00000000028c9780_0 .net *"_s12", 7 0, L_00000000028d0910; 1 drivers
+L_00000000028e0160 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v00000000028c9f00_0 .net/2u *"_s14", 7 0, L_00000000028e0160; 1 drivers
+v00000000028ca5e0_0 .net *"_s22", 7 0, L_0000000002938520; 1 drivers
+v00000000028c9c80_0 .net *"_s3", 17 0, L_00000000028d1bd0; 1 drivers
+L_00000000028e03e8 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>;
+v00000000028ca540_0 .net/2u *"_s30", 5 0, L_00000000028e03e8; 1 drivers
+v00000000028c9d20_0 .net *"_s33", 17 0, L_0000000002939420; 1 drivers
+v00000000028c9aa0_0 .net *"_s34", 23 0, L_0000000002939e20; 1 drivers
+L_00000000028e0430 .functor BUFT 1, C4<10111>, C4<0>, C4<0>, C4<0>;
+v00000000028c9500_0 .net/2u *"_s36", 4 0, L_00000000028e0430; 1 drivers
+v00000000028ca7c0_0 .net *"_s38", 4 0, L_00000000029388e0; 1 drivers
+v00000000028c95a0_0 .net *"_s40", 23 0, L_00000000029387a0; 1 drivers
+v00000000028cae00_0 .net *"_s43", 22 0, L_0000000002939380; 1 drivers
+v00000000028ca0e0_0 .net *"_s9", 0 0, L_00000000028d0870; 1 drivers
+v00000000028c9820_0 .net "a", 18 0, v00000000028c9140_0; 1 drivers
+v00000000028c9fa0_0 .net "b", 31 0, L_0000000002939ec0; alias, 1 drivers
+v00000000028ca860_0 .net "o", 4 0, L_00000000028d1130; 1 drivers
+v00000000028c9dc0_0 .net "o1", 7 0, L_00000000028d09b0; 1 drivers
+v00000000028ca2c0_0 .net "x", 0 0, L_0000000002938840; 1 drivers
+v00000000028c9640_0 .net "zro", 0 0, L_00000000028d0730; alias, 1 drivers
+L_00000000028d1bd0 .part v00000000028c9140_0, 0, 18;
+L_00000000028d0c30 .concat [ 18 6 0 0], L_00000000028d1bd0, L_00000000028e00d0;
+L_00000000028d0870 .part v00000000028c9140_0, 18, 1;
+L_00000000028d0910 .concat [ 5 3 0 0], L_00000000028d1130, L_00000000028e0118;
+L_00000000028d09b0 .functor MUXZ 8, L_00000000028e0160, L_00000000028d0910, L_00000000028d0730, C4<>;
+L_0000000002938840 .part L_0000000002938480, 8, 1;
+L_0000000002938520 .part L_0000000002938480, 0, 8;
+L_0000000002939ec0 .concat8 [ 23 8 1 0], L_0000000002939380, L_0000000002938520, L_00000000028d0870;
+L_0000000002939420 .part v00000000028c9140_0, 0, 18;
+L_0000000002939e20 .concat [ 18 6 0 0], L_0000000002939420, L_00000000028e03e8;
+L_00000000029388e0 .arith/sub 5, L_00000000028e0430, L_00000000028d1130;
+L_00000000029387a0 .shift/l 24, L_0000000002939e20, L_00000000029388e0;
+L_0000000002939380 .part L_00000000029387a0, 0, 23;
+S_0000000002829680 .scope module, "t" "pe24" 3 51, 3 181 0, S_0000000002832730;
+ .timescale 0 0;
+ .port_info 0 /INPUT 24 "a"
+ .port_info 1 /OUTPUT 5 "b"
+ .port_info 2 /OUTPUT 1 "az"
+v00000000028c7450_0 .net *"_s46", 0 0, L_00000000028d1770; 1 drivers
+v00000000028c7630_0 .net *"_s51", 1 0, L_00000000028d1950; 1 drivers
+v00000000028c8850_0 .net *"_s53", 0 0, L_00000000028d14f0; 1 drivers
+v00000000028c8cb0_0 .net *"_s63", 0 0, L_00000000028cffb0; 1 drivers
+v00000000028c8df0_0 .net *"_s65", 1 0, L_00000000028d16d0; 1 drivers
+v00000000028c88f0_0 .net *"_s67", 1 0, L_00000000028d04b0; 1 drivers
+v00000000028c8a30_0 .net *"_s68", 1 0, L_00000000028d00f0; 1 drivers
+L_00000000028e0088 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000028c80d0_0 .net/2u *"_s73", 0 0, L_00000000028e0088; 1 drivers
+v00000000028c7bd0_0 .net *"_s76", 0 0, L_00000000028d0190; 1 drivers
+v00000000028c8210_0 .net *"_s77", 1 0, L_00000000028d19f0; 1 drivers
+v00000000028c7c70_0 .net *"_s82", 0 0, L_00000000028d0550; 1 drivers
+v00000000028c85d0_0 .net *"_s87", 0 0, L_00000000028d1b30; 1 drivers
+v00000000028c8b70_0 .net *"_s89", 3 0, L_00000000028d05f0; 1 drivers
+v00000000028c8c10_0 .net *"_s91", 3 0, L_00000000028d0230; 1 drivers
+v00000000028c8e90_0 .net *"_s92", 3 0, L_00000000028d1a90; 1 drivers
+v00000000028c73b0_0 .net *"_s95", 0 0, L_00000000028d1270; 1 drivers
+v00000000028c7310_0 .net *"_s97", 0 0, L_00000000028d1d10; 1 drivers
+v00000000028c82b0_0 .net *"_s99", 0 0, L_00000000028d0690; 1 drivers
+v00000000028c7d10_0 .net "a", 23 0, L_00000000028d0c30; 1 drivers
+v00000000028c7590_0 .net "az", 0 0, L_00000000028d0730; alias, 1 drivers
+v00000000028c76d0_0 .net "b", 4 0, L_00000000028d1130; alias, 1 drivers
+v00000000028c8350_0 .net "o", 17 0, L_00000000028cd090; 1 drivers
+v00000000028c7770_0 .net "o1", 4 0, L_00000000028d0e10; 1 drivers
+v00000000028c8670_0 .net "o2", 7 0, L_00000000028d02d0; 1 drivers
+L_00000000028cd590 .part L_00000000028d0c30, 0, 4;
+L_00000000028ce710 .part L_00000000028d0c30, 4, 4;
+L_00000000028ce990 .part L_00000000028d0c30, 8, 4;
+L_00000000028ce8f0 .part L_00000000028d0c30, 12, 4;
+L_00000000028cd270 .part L_00000000028d0c30, 16, 4;
+L_00000000028cd310 .part L_00000000028d0c30, 20, 4;
+LS_00000000028cd090_0_0 .concat8 [ 2 2 2 2], L_00000000028caae0, L_00000000028cd9f0, L_00000000028ce490, L_00000000028cd770;
+LS_00000000028cd090_0_4 .concat8 [ 2 2 1 1], L_00000000028cd8b0, L_00000000028cdf90, L_00000000028c98c0, L_00000000028ce0d0;
+LS_00000000028cd090_0_8 .concat8 [ 1 1 1 1], L_00000000028cd950, L_00000000028cd6d0, L_00000000028cd810, L_00000000028ce530;
+L_00000000028cd090 .concat8 [ 8 6 4 0], LS_00000000028cd090_0_0, LS_00000000028cd090_0_4, LS_00000000028cd090_0_8;
+L_00000000028d0f50 .part L_00000000028cd090, 12, 4;
+L_00000000028d1770 .part L_00000000028cd090, 17, 1;
+L_00000000028d0e10 .concat8 [ 2 1 1 1], L_00000000028d0ff0, L_00000000028d1770, L_00000000028ce2b0, L_00000000028d14f0;
+L_00000000028d1950 .part L_00000000028cd090, 16, 2;
+L_00000000028d14f0 .reduce/or L_00000000028d1950;
+L_00000000028cff10 .part L_00000000028d0e10, 0, 2;
+L_00000000028d11d0 .part L_00000000028cd090, 0, 8;
+L_00000000028cffb0 .part L_00000000028d0e10, 2, 1;
+L_00000000028d16d0 .part L_00000000028cd090, 10, 2;
+L_00000000028d04b0 .part L_00000000028cd090, 8, 2;
+L_00000000028d00f0 .functor MUXZ 2, L_00000000028d04b0, L_00000000028d16d0, L_00000000028cffb0, C4<>;
+L_00000000028d02d0 .concat8 [ 4 2 2 0], L_00000000028d0370, L_00000000028d00f0, L_00000000028d19f0;
+L_00000000028d0190 .part L_00000000028d0e10, 2, 1;
+L_00000000028d19f0 .concat [ 1 1 0 0], L_00000000028d0190, L_00000000028e0088;
+L_00000000028d0550 .part L_00000000028d0e10, 4, 1;
+L_00000000028d1130 .concat8 [ 4 1 0 0], L_00000000028d1a90, L_00000000028d0550;
+L_00000000028d1b30 .part L_00000000028d0e10, 4, 1;
+L_00000000028d05f0 .part L_00000000028d02d0, 4, 4;
+L_00000000028d0230 .part L_00000000028d02d0, 0, 4;
+L_00000000028d1a90 .functor MUXZ 4, L_00000000028d0230, L_00000000028d05f0, L_00000000028d1b30, C4<>;
+L_00000000028d1270 .part L_00000000028d0e10, 4, 1;
+L_00000000028d1d10 .part L_00000000028d0e10, 4, 1;
+L_00000000028d0690 .part L_00000000028d0e10, 3, 1;
+L_00000000028d0730 .functor MUXZ 1, L_00000000028d0690, L_00000000028d1d10, L_00000000028d1270, C4<>;
+S_0000000002829800 .scope module, "t0" "pe4" 3 191, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v0000000002860b80_0 .net *"_s12", 0 0, L_00000000028cab80; 1 drivers
+v0000000002861300_0 .net *"_s14", 0 0, L_00000000028cac20; 1 drivers
+v0000000002860c20_0 .net *"_s16", 0 0, L_00000000028cacc0; 1 drivers
+v0000000002861ee0_0 .net *"_s17", 0 0, L_00000000028caf40; 1 drivers
+v00000000028620c0_0 .net *"_s5", 1 0, L_00000000028ca9a0; 1 drivers
+v0000000002860900_0 .net *"_s7", 0 0, L_00000000028c90a0; 1 drivers
+v0000000002860d60_0 .net "a", 3 0, L_00000000028cd590; 1 drivers
+v00000000028618a0_0 .net "b", 1 0, L_00000000028caae0; 1 drivers
+v0000000002860e00_0 .net "o", 0 0, L_00000000028c98c0; 1 drivers
+L_00000000028c98c0 .reduce/or L_00000000028cd590;
+L_00000000028ca9a0 .part L_00000000028cd590, 2, 2;
+L_00000000028c90a0 .reduce/or L_00000000028ca9a0;
+L_00000000028caae0 .concat8 [ 1 1 0 0], L_00000000028caf40, L_00000000028c90a0;
+L_00000000028cab80 .part L_00000000028caae0, 1, 1;
+L_00000000028cac20 .part L_00000000028cd590, 3, 1;
+L_00000000028cacc0 .part L_00000000028cd590, 1, 1;
+L_00000000028caf40 .functor MUXZ 1, L_00000000028cacc0, L_00000000028cac20, L_00000000028cab80, C4<>;
+S_0000000002834310 .scope module, "t1" "pe4" 3 192, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028611c0_0 .net *"_s12", 0 0, L_00000000028cdbd0; 1 drivers
+v0000000002861260_0 .net *"_s14", 0 0, L_00000000028cd3b0; 1 drivers
+v00000000028c58a0_0 .net *"_s16", 0 0, L_00000000028cdc70; 1 drivers
+v00000000028c6d40_0 .net *"_s17", 0 0, L_00000000028cd450; 1 drivers
+v00000000028c5e40_0 .net *"_s5", 1 0, L_00000000028cd130; 1 drivers
+v00000000028c5ee0_0 .net *"_s7", 0 0, L_00000000028cd4f0; 1 drivers
+v00000000028c6e80_0 .net "a", 3 0, L_00000000028ce710; 1 drivers
+v00000000028c6020_0 .net "b", 1 0, L_00000000028cd9f0; 1 drivers
+v00000000028c6660_0 .net "o", 0 0, L_00000000028ce0d0; 1 drivers
+L_00000000028ce0d0 .reduce/or L_00000000028ce710;
+L_00000000028cd130 .part L_00000000028ce710, 2, 2;
+L_00000000028cd4f0 .reduce/or L_00000000028cd130;
+L_00000000028cd9f0 .concat8 [ 1 1 0 0], L_00000000028cd450, L_00000000028cd4f0;
+L_00000000028cdbd0 .part L_00000000028cd9f0, 1, 1;
+L_00000000028cd3b0 .part L_00000000028ce710, 3, 1;
+L_00000000028cdc70 .part L_00000000028ce710, 1, 1;
+L_00000000028cd450 .functor MUXZ 1, L_00000000028cdc70, L_00000000028cd3b0, L_00000000028cdbd0, C4<>;
+S_0000000002834490 .scope module, "t2" "pe4" 3 193, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028c5a80_0 .net *"_s12", 0 0, L_00000000028cdb30; 1 drivers
+v00000000028c68e0_0 .net *"_s14", 0 0, L_00000000028cd630; 1 drivers
+v00000000028c6f20_0 .net *"_s16", 0 0, L_00000000028ce170; 1 drivers
+v00000000028c5b20_0 .net *"_s17", 0 0, L_00000000028cdd10; 1 drivers
+v00000000028c5300_0 .net *"_s5", 1 0, L_00000000028cd1d0; 1 drivers
+v00000000028c60c0_0 .net *"_s7", 0 0, L_00000000028ce670; 1 drivers
+v00000000028c5080_0 .net "a", 3 0, L_00000000028ce990; 1 drivers
+v00000000028c6de0_0 .net "b", 1 0, L_00000000028ce490; 1 drivers
+v00000000028c5120_0 .net "o", 0 0, L_00000000028cd950; 1 drivers
+L_00000000028cd950 .reduce/or L_00000000028ce990;
+L_00000000028cd1d0 .part L_00000000028ce990, 2, 2;
+L_00000000028ce670 .reduce/or L_00000000028cd1d0;
+L_00000000028ce490 .concat8 [ 1 1 0 0], L_00000000028cdd10, L_00000000028ce670;
+L_00000000028cdb30 .part L_00000000028ce490, 1, 1;
+L_00000000028cd630 .part L_00000000028ce990, 3, 1;
+L_00000000028ce170 .part L_00000000028ce990, 1, 1;
+L_00000000028cdd10 .functor MUXZ 1, L_00000000028ce170, L_00000000028cd630, L_00000000028cdb30, C4<>;
+S_0000000002837fd0 .scope module, "t3" "pe4" 3 194, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028c6160_0 .net *"_s12", 0 0, L_00000000028ce350; 1 drivers
+v00000000028c51c0_0 .net *"_s14", 0 0, L_00000000028cddb0; 1 drivers
+v00000000028c5bc0_0 .net *"_s16", 0 0, L_00000000028ce7b0; 1 drivers
+v00000000028c5440_0 .net *"_s17", 0 0, L_00000000028ccaf0; 1 drivers
+v00000000028c5d00_0 .net *"_s5", 1 0, L_00000000028ccc30; 1 drivers
+v00000000028c6b60_0 .net *"_s7", 0 0, L_00000000028ce030; 1 drivers
+v00000000028c53a0_0 .net "a", 3 0, L_00000000028ce8f0; 1 drivers
+v00000000028c5260_0 .net "b", 1 0, L_00000000028cd770; 1 drivers
+v00000000028c6980_0 .net "o", 0 0, L_00000000028cd6d0; 1 drivers
+L_00000000028cd6d0 .reduce/or L_00000000028ce8f0;
+L_00000000028ccc30 .part L_00000000028ce8f0, 2, 2;
+L_00000000028ce030 .reduce/or L_00000000028ccc30;
+L_00000000028cd770 .concat8 [ 1 1 0 0], L_00000000028ccaf0, L_00000000028ce030;
+L_00000000028ce350 .part L_00000000028cd770, 1, 1;
+L_00000000028cddb0 .part L_00000000028ce8f0, 3, 1;
+L_00000000028ce7b0 .part L_00000000028ce8f0, 1, 1;
+L_00000000028ccaf0 .functor MUXZ 1, L_00000000028ce7b0, L_00000000028cddb0, L_00000000028ce350, C4<>;
+S_0000000002838150 .scope module, "t4" "pe4" 3 195, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028c54e0_0 .net *"_s12", 0 0, L_00000000028ce5d0; 1 drivers
+v00000000028c5da0_0 .net *"_s14", 0 0, L_00000000028cde50; 1 drivers
+v00000000028c5f80_0 .net *"_s16", 0 0, L_00000000028ccd70; 1 drivers
+v00000000028c6200_0 .net *"_s17", 0 0, L_00000000028cda90; 1 drivers
+v00000000028c5580_0 .net *"_s5", 1 0, L_00000000028cccd0; 1 drivers
+v00000000028c6ac0_0 .net *"_s7", 0 0, L_00000000028ce850; 1 drivers
+v00000000028c6700_0 .net "a", 3 0, L_00000000028cd270; 1 drivers
+v00000000028c5800_0 .net "b", 1 0, L_00000000028cd8b0; 1 drivers
+v00000000028c5c60_0 .net "o", 0 0, L_00000000028cd810; 1 drivers
+L_00000000028cd810 .reduce/or L_00000000028cd270;
+L_00000000028cccd0 .part L_00000000028cd270, 2, 2;
+L_00000000028ce850 .reduce/or L_00000000028cccd0;
+L_00000000028cd8b0 .concat8 [ 1 1 0 0], L_00000000028cda90, L_00000000028ce850;
+L_00000000028ce5d0 .part L_00000000028cd8b0, 1, 1;
+L_00000000028cde50 .part L_00000000028cd270, 3, 1;
+L_00000000028ccd70 .part L_00000000028cd270, 1, 1;
+L_00000000028cda90 .functor MUXZ 1, L_00000000028ccd70, L_00000000028cde50, L_00000000028ce5d0, C4<>;
+S_00000000028250b0 .scope module, "t5" "pe4" 3 196, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028c5620_0 .net *"_s12", 0 0, L_00000000028ccb90; 1 drivers
+v00000000028c5940_0 .net *"_s14", 0 0, L_00000000028ce210; 1 drivers
+v00000000028c62a0_0 .net *"_s16", 0 0, L_00000000028cceb0; 1 drivers
+v00000000028c67a0_0 .net *"_s17", 0 0, L_00000000028ccf50; 1 drivers
+v00000000028c59e0_0 .net *"_s5", 1 0, L_00000000028cce10; 1 drivers
+v00000000028c6840_0 .net *"_s7", 0 0, L_00000000028cdef0; 1 drivers
+v00000000028c56c0_0 .net "a", 3 0, L_00000000028cd310; 1 drivers
+v00000000028c5760_0 .net "b", 1 0, L_00000000028cdf90; 1 drivers
+v00000000028c6340_0 .net "o", 0 0, L_00000000028ce530; 1 drivers
+L_00000000028ce530 .reduce/or L_00000000028cd310;
+L_00000000028cce10 .part L_00000000028cd310, 2, 2;
+L_00000000028cdef0 .reduce/or L_00000000028cce10;
+L_00000000028cdf90 .concat8 [ 1 1 0 0], L_00000000028ccf50, L_00000000028cdef0;
+L_00000000028ccb90 .part L_00000000028cdf90, 1, 1;
+L_00000000028ce210 .part L_00000000028cd310, 3, 1;
+L_00000000028cceb0 .part L_00000000028cd310, 1, 1;
+L_00000000028ccf50 .functor MUXZ 1, L_00000000028cceb0, L_00000000028ce210, L_00000000028ccb90, C4<>;
+S_0000000002825230 .scope module, "t6" "pe4" 3 199, 3 212 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 4 "a"
+ .port_info 1 /OUTPUT 2 "b"
+ .port_info 2 /OUTPUT 1 "o"
+v00000000028c6c00_0 .net *"_s12", 0 0, L_00000000028d1310; 1 drivers
+v00000000028c63e0_0 .net *"_s14", 0 0, L_00000000028d13b0; 1 drivers
+v00000000028c6480_0 .net *"_s16", 0 0, L_00000000028d0050; 1 drivers
+v00000000028c6520_0 .net *"_s17", 0 0, L_00000000028d1450; 1 drivers
+v00000000028c65c0_0 .net *"_s5", 1 0, L_00000000028ce3f0; 1 drivers
+v00000000028c6a20_0 .net *"_s7", 0 0, L_00000000028ccff0; 1 drivers
+v00000000028c6ca0_0 .net "a", 3 0, L_00000000028d0f50; 1 drivers
+v00000000028c8990_0 .net "b", 1 0, L_00000000028d0ff0; 1 drivers
+v00000000028c8530_0 .net "o", 0 0, L_00000000028ce2b0; 1 drivers
+L_00000000028ce2b0 .reduce/or L_00000000028d0f50;
+L_00000000028ce3f0 .part L_00000000028d0f50, 2, 2;
+L_00000000028ccff0 .reduce/or L_00000000028ce3f0;
+L_00000000028d0ff0 .concat8 [ 1 1 0 0], L_00000000028d1450, L_00000000028ccff0;
+L_00000000028d1310 .part L_00000000028d0ff0, 1, 1;
+L_00000000028d13b0 .part L_00000000028d0f50, 3, 1;
+L_00000000028d0050 .part L_00000000028d0f50, 1, 1;
+L_00000000028d1450 .functor MUXZ 1, L_00000000028d0050, L_00000000028d13b0, L_00000000028d1310, C4<>;
+S_00000000027f2720 .scope module, "t7" "mux4x1" 3 203, 3 225 0, S_0000000002829680;
+ .timescale 0 0;
+ .port_info 0 /INPUT 2 "sel"
+ .port_info 1 /INPUT 8 "a"
+ .port_info 2 /OUTPUT 4 "y"
+P_000000000285c320 .param/l "n" 0 3 226, +C4<00000000000000000000000000000010>;
+v00000000028c8ad0_0 .net *"_s1", 0 0, L_00000000028d1c70; 1 drivers
+v00000000028c7ef0_0 .net *"_s11", 0 0, L_00000000028d0eb0; 1 drivers
+v00000000028c8f30_0 .net *"_s13", 1 0, L_00000000028d1630; 1 drivers
+v00000000028c7130_0 .net *"_s15", 1 0, L_00000000028d07d0; 1 drivers
+v00000000028c7090_0 .net *"_s16", 1 0, L_00000000028d0410; 1 drivers
+v00000000028c71d0_0 .net *"_s3", 0 0, L_00000000028d1810; 1 drivers
+v00000000028c7270_0 .net *"_s5", 1 0, L_00000000028d1090; 1 drivers
+v00000000028c74f0_0 .net *"_s7", 1 0, L_00000000028d1590; 1 drivers
+v00000000028c8d50_0 .net *"_s8", 1 0, L_00000000028d1db0; 1 drivers
+v00000000028c8710_0 .net "a", 7 0, L_00000000028d11d0; 1 drivers
+v00000000028c7810_0 .net "sel", 1 0, L_00000000028cff10; 1 drivers
+v00000000028c8170_0 .net "y", 3 0, L_00000000028d0370; 1 drivers
+v00000000028c87b0_0 .net "y1", 1 0, L_00000000028d18b0; 1 drivers
+L_00000000028d1c70 .part L_00000000028cff10, 1, 1;
+L_00000000028d1810 .part L_00000000028cff10, 0, 1;
+L_00000000028d1090 .part L_00000000028d11d0, 6, 2;
+L_00000000028d1590 .part L_00000000028d11d0, 4, 2;
+L_00000000028d1db0 .functor MUXZ 2, L_00000000028d1590, L_00000000028d1090, L_00000000028d1810, C4<>;
+L_00000000028d0eb0 .part L_00000000028cff10, 0, 1;
+L_00000000028d1630 .part L_00000000028d11d0, 2, 2;
+L_00000000028d07d0 .part L_00000000028d11d0, 0, 2;
+L_00000000028d0410 .functor MUXZ 2, L_00000000028d07d0, L_00000000028d1630, L_00000000028d0eb0, C4<>;
+L_00000000028d18b0 .functor MUXZ 2, L_00000000028d0410, L_00000000028d1db0, L_00000000028d1c70, C4<>;
+L_00000000028d0370 .concat [ 2 2 0 0], L_00000000028d18b0, L_00000000028cff10;
+S_00000000027f29b0 .scope module, "t0" "adder" 3 55, 3 62 0, S_0000000002832730;
+ .timescale 0 0;
+ .port_info 0 /INPUT 8 "p"
+ .port_info 1 /INPUT 8 "q"
+ .port_info 2 /INPUT 1 "mode"
+ .port_info 3 /OUTPUT 9 "sum"
+P_000000000285bfa0 .param/l "num" 0 3 64, +C4<00000000000000000000000000001000>;
+L_0000000002864650 .functor BUFT 9, L_0000000002939060, C4<000000000>, C4<000000000>, C4<000000000>;
+v00000000028c7db0_0 .net *"_s1", 0 0, L_00000000028d0cd0; 1 drivers
+v00000000028c78b0_0 .net *"_s11", 8 0, L_00000000028d0af0; 1 drivers
+L_00000000028e0478 .functor BUFT 1, C4<001111111>, C4<0>, C4<0>, C4<0>;
+v00000000028c83f0_0 .net *"_s14", 8 0, L_00000000028e0478; 1 drivers
+v00000000028c7950_0 .net *"_s19", 0 0, L_0000000002939240; 1 drivers
+L_00000000028e01a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v00000000028c8490_0 .net/2u *"_s2", 1 0, L_00000000028e01a8; 1 drivers
+L_00000000028e0238 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v00000000028c79f0_0 .net/2u *"_s20", 1 0, L_00000000028e0238; 1 drivers
+v00000000028c7a90_0 .net *"_s23", 6 0, L_0000000002939b00; 1 drivers
+v00000000028c7b30_0 .net *"_s24", 8 0, L_0000000002939c40; 1 drivers
+L_00000000028e0280 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>;
+v00000000028c7e50_0 .net *"_s26", 8 0, L_00000000028e0280; 1 drivers
+v00000000028c7f90_0 .net *"_s29", 8 0, L_00000000029382a0; 1 drivers
+L_00000000028e02c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000028c8030_0 .net/2u *"_s30", 0 0, L_00000000028e02c8; 1 drivers
+v00000000028ca220_0 .net *"_s32", 8 0, L_0000000002939f60; 1 drivers
+v00000000028cad60_0 .net *"_s36", 8 0, L_00000000029383e0; 1 drivers
+v00000000028c9e60_0 .net *"_s38", 8 0, L_0000000002939060; 1 drivers
+L_00000000028e0310 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>;
+v00000000028caa40_0 .net *"_s42", 8 0, L_00000000028e0310; 1 drivers
+v00000000028caea0_0 .net *"_s47", 0 0, L_0000000002938ca0; 1 drivers
+v00000000028ca040_0 .net *"_s49", 0 0, L_00000000029397e0; 1 drivers
+v00000000028ca680_0 .net *"_s5", 6 0, L_00000000028d0d70; 1 drivers
+v00000000028c9960_0 .net *"_s51", 7 0, L_00000000029391a0; 1 drivers
+v00000000028c96e0_0 .net *"_s52", 8 0, L_0000000002938c00; 1 drivers
+v00000000028ca720_0 .net *"_s6", 8 0, L_00000000028d0a50; 1 drivers
+L_00000000028e01f0 .functor BUFT 1, C4<000000000>, C4<0>, C4<0>, C4<0>;
+v00000000028c9280_0 .net *"_s8", 8 0, L_00000000028e01f0; 1 drivers
+L_00000000028e03a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v00000000028ca900_0 .net "mode", 0 0, L_00000000028e03a0; 1 drivers
+L_00000000028e0358 .functor BUFT 1, C4<01111111>, C4<0>, C4<0>, C4<0>;
+v00000000028c9be0_0 .net "p", 7 0, L_00000000028e0358; 1 drivers
+v00000000028ca400_0 .net "q", 7 0, L_00000000028d09b0; alias, 1 drivers
+v00000000028c9b40_0 .net "sum", 8 0, L_0000000002938480; 1 drivers
+v00000000028c9320_0 .net "temp", 8 0, L_0000000002864650; 1 drivers
+v00000000028c93c0_0 .net "temp1", 8 0, L_0000000002938340; 1 drivers
+v00000000028ca4a0_0 .net "temp2", 8 0, L_00000000028d0b90; 1 drivers
+v00000000028c9460_0 .net "temp3", 8 0, L_00000000029392e0; 1 drivers
+L_00000000028d0cd0 .part L_00000000028e0358, 7, 1;
+L_00000000028d0d70 .part L_00000000028e0358, 0, 7;
+L_00000000028d0a50 .concat [ 7 2 0 0], L_00000000028d0d70, L_00000000028e01a8;
+L_00000000028d0af0 .arith/sub 9, L_00000000028e01f0, L_00000000028d0a50;
+L_00000000028d0b90 .functor MUXZ 9, L_00000000028e0478, L_00000000028d0af0, L_00000000028d0cd0, C4<>;
+L_0000000002939240 .part L_00000000028d09b0, 7, 1;
+L_0000000002939b00 .part L_00000000028d09b0, 0, 7;
+L_0000000002939c40 .concat [ 7 2 0 0], L_0000000002939b00, L_00000000028e0238;
+L_00000000029382a0 .arith/sub 9, L_00000000028e0280, L_0000000002939c40;
+L_0000000002939f60 .concat [ 8 1 0 0], L_00000000028d09b0, L_00000000028e02c8;
+L_00000000029392e0 .functor MUXZ 9, L_0000000002939f60, L_00000000029382a0, L_0000000002939240, C4<>;
+L_00000000029383e0 .arith/sub 9, L_00000000028d0b90, L_00000000029392e0;
+L_0000000002939060 .arith/sum 9, L_00000000028d0b90, L_00000000029392e0;
+L_0000000002938340 .arith/sub 9, L_00000000028e0310, L_0000000002864650;
+L_0000000002938ca0 .part L_0000000002864650, 8, 1;
+L_00000000029397e0 .part L_0000000002864650, 8, 1;
+L_00000000029391a0 .part L_0000000002938340, 0, 8;
+L_0000000002938c00 .concat [ 8 1 0 0], L_00000000029391a0, L_00000000029397e0;
+L_0000000002938480 .functor MUXZ 9, L_0000000002864650, L_0000000002938c00, L_0000000002938ca0, C4<>;
+ .scope S_00000000028325b0;
+T_0 ;
+ %pushi/vec4 1024, 0, 19;
+ %store/vec4 v00000000028c9140_0, 0, 19;
+ %delay 10, 0;
+ %pushi/vec4 65536, 0, 19;
+ %store/vec4 v00000000028c9140_0, 0, 19;
+ %delay 10, 0;
+ %pushi/vec4 123456, 0, 19;
+ %store/vec4 v00000000028c9140_0, 0, 19;
+ %delay 100, 0;
+ %vpi_call 2 18 "$finish" {0 0 0};
+ %end;
+ .thread T_0;
+ .scope S_00000000028325b0;
+T_1 ;
+ %vpi_call 2 23 "$dumpfile", "fxd2float.vcd" {0 0 0};
+ %vpi_call 2 24 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000000028325b0 {0 0 0};
+ %end;
+ .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+ "N/A";
+ "<interactive>";
+ "fxd2float_tb.v";
+ "fx2float.v";
diff --git a/Simulations/pre_synthesis/fx2float.v b/Simulations/pre_synthesis/fx2float.v
new file mode 100644
index 0000000..c6191ca
--- /dev/null
+++ b/Simulations/pre_synthesis/fx2float.v
@@ -0,0 +1,237 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Company : SMDP-C2SD //
+// Create Date : 10 AUG 2021 //
+// Design Name : Feature Extraction Engine //
+// Target Devices : ASIC (SCL-180nm) : ZedBoard (FPGA-ZC702) //
+// Tool versions : Cadence Genus : Vivado //
+// //
+// Design Engineer : DHAYALAKUMAR M & SKANDHA DEEPSITA S //
+// Project Co-Ordinator : Dr NOOR MAHAMMAD SK //
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*
+ Exponent Mantissa Object
+ 0 0 Zero
+ 0 Nonzero Denormalized number*
+ 1-254 Anything +/- FP number
+ 255 0 + / - infinity
+ 255 Nonzero NaN
+
+
+
+ Type Sign Actual Exp Exp (biased) Exponent field Fraction field Value
+ Zero 0 −126 0 0000 0000 000 0000 0000 0000 0000 0000 0.0
+ Negative zero 1 −126 0 0000 0000 000 0000 0000 0000 0000 0000 −0.0
+ One 0 0 127 0111 1111 000 0000 0000 0000 0000 0000 1.0
+ Minus One 1 0 127 0111 1111 000 0000 0000 0000 0000 0000 −1.0
+ Smallest denormalized number * −126 0 0000 0000 000 0000 0000 0000 0000 0001 ±2−23 × 2−126 = ±2−149 ≈ ±1.4×10−45
+ "Middle" denormalized number * −126 0 0000 0000 100 0000 0000 0000 0000 0000 ±2−1 × 2−126 = ±2−127 ≈ ±5.88×10−39
+ Largest denormalized number * −126 0 0000 0000 111 1111 1111 1111 1111 1111 ±(1−2−23) × 2−126 ≈ ±1.18×10−38
+ Smallest normalized number * −126 1 0000 0001 000 0000 0000 0000 0000 0000 ±2−126 ≈ ±1.18×10−38
+ Largest normalized number * 127 254 1111 1110 111 1111 1111 1111 1111 1111 ±(2−2−23) × 2127 ≈ ±3.4×1038
+ Positive infinity 0 128 255 1111 1111 000 0000 0000 0000 0000 0000 +∞
+ Negative infinity 1 128 255 1111 1111 000 0000 0000 0000 0000 0000 −∞
+ Not a number * 128 255 1111 1111 non zero NaN
+*/
+
+module fxd2flot(a, b, zro);
+
+parameter in = 19; // input resolution
+parameter man = 23; // Mantisa resolution in bits without hidden bit
+parameter exp = 8; // Exponent Resolution
+
+input [in-1:0] a; // 1 18 (sign Magnitude)
+output [exp+man:0] b; // Floating Point 1 8 23;
+output zro;
+
+wire [4:0] o;
+wire [7:0] o1;
+wire x;
+
+pe24 t({{(man-in+2){1'b0}}, a[in-2:0]}, o, zro);
+
+assign b[exp+man] = a[in-1];
+assign o1 = zro ? {3'b0, o} : 8'd255;
+adder #(exp) t0(8'd127, o1, 1'b0, {x, b[man+exp-1:man]});
+assign b[man-1:0] = {{(man-in+2){1'b0}}, a[in-2:0]}<<(5'd23-o);
+
+endmodule
+
+`define DSPoperator
+
+module adder(p, q, mode, sum);
+
+parameter num = 25;
+
+output [num:0] sum;
+input [num-1:0] p,q;
+input mode;
+
+wire [num:0] temp, temp1;
+
+`ifdef DSPoperator
+wire [num:0] temp2, temp3;
+ assign temp2[num:0] = p[num-1] ? -{2'b0, p[num-2:0]}:{1'b0,p};
+ assign temp3[num:0] = q[num-1] ? -{2'b0, q[num-2:0]}:{1'b0,q};
+ assign temp[num:0] = mode ? temp2-temp3 : temp2+temp3;
+`else
+ wire [2*num+1:0] x [0:$clog2(num+1)];
+ wire [num:0] a1, b1, a, b;
+
+ assign a1 = {(num+1){p[num-1]}}^{2'b0, p[num-2:0]};
+ assign b1 = {(num+1){mode^q[num-1]}}^{2'b0, q[num-2:0]};
+ assign a[0] = a1[0];
+ assign b[0] = b1[0];
+ assign b[1] = p[num-1]&(q[num-1]^mode);
+ assign a[num] = a1[num]^b1[num];
+
+ assign x[0][1:0]={2{p[num-1]^q[num-1]^mode}}; // Input carry
+
+ genvar i, j;
+ generate
+ begin:ha_fa //halfadder
+ for(i=1; i<num; i=i+1) begin
+ halfadd t0({a1[i],b1[i]}, a[i], b[i+1]);
+ end
+ end
+
+ begin: kgp_gen // kgp generation
+ for (i=0; i<num; i=i+1) begin
+ kgp t(a[i], b[i], x[0][2*i+3:2*i+2]);
+ end
+ end
+ begin:recursiveStg //recursive
+ for (i=0; i<$clog2(num+1); i=i+1)
+ begin
+ assign x[i+1][(2**(i+1))-1:0]=x[i][(2**(i+1))-1:0];
+ for(j=(2**(i+1)); j<2*num+1; j=j+2)
+ begin
+ recursive_stage1 s(x[i][j+1-(2**(i+1)):j-(2**(i+1))],x[i][j+1:j],x[i+1][j+1:j]);
+ end
+ end
+ end
+ begin:addition // SUM Calculation
+ for(i=0; i<num+1; i=i+1) begin
+ assign temp[i] = a[i]^b[i]^x[$clog2(num)][2*i];
+ end
+ end
+ endgenerate
+`endif
+ assign temp1 = -temp;
+ assign sum = temp[num] ? ({temp[num], temp1[num-1:0]}) : (temp);
+
+endmodule
+
+`ifdef DSPoperator
+
+`else
+
+ module kgp(a,b,y);
+
+ input a,b; output [1:0] y;
+
+ assign y[0]=a | b;
+ assign y[1]=a & b;
+
+ endmodule
+
+
+
+ module recursive_stage1(a,b,y);
+
+ input [1:0] a,b; output [1:0] y;
+
+ wire [1:0] y;
+ wire b0;
+ not n1(b0,b[1]);
+ wire f,g0,g1;
+ and a1(f,b[0],b[1]);
+ and a2(g0,b0,b[0],a[0]);
+ and a3(g1,b0,b[0],a[1]);
+
+ or o1(y[0],f,g0);
+ or o2(y[1],f,g1);
+
+ endmodule
+
+ module halfadd(x, sum, carry);
+
+output sum,carry;
+input [1:0] x;
+
+ assign sum = x[1] ^ x[0];
+ assign carry = x[1] & x[0];
+
+endmodule
+
+
+
+module fulladd(x, sum, carry);
+
+output sum,carry;
+input [2:0] x;
+
+wire w;
+ assign w = x[2] ^ x[1];
+ assign sum = w ^ x[0];
+ assign carry = (x[2] & x[1])|(w & x[0]);
+endmodule
+`endif
+
+module pe24(a,b,az);
+
+input [23:0] a;
+output [4:0] b;
+output az;
+
+wire [17:0] o;
+wire [4:0] o1;
+wire [7:0] o2;
+
+ pe4 t0(a[3:0],o[1:0],o[12]);
+ pe4 t1(a[7:4],o[3:2],o[13]);
+ pe4 t2(a[11:8],o[5:4],o[14]);
+ pe4 t3(a[15:12],o[7:6],o[15]);
+ pe4 t4(a[19:16],o[9:8],o[16]);
+ pe4 t5(a[23:20],o[11:10],o[17]);
+
+
+ pe4 t6(o[15:12], o1[1:0], o1[3]);
+ assign o1[2] = o[17];
+ assign o1[4] = |o[17:16];
+
+ mux4x1 t7(o1[1:0], o[7:0], o2[3:0]);
+ assign o2[5:4] = o1[2] ? o[11:10]:o[9:8];
+ assign o2[7:6] = {1'b0, o1[2]};
+ assign b[4] = o1[4];
+ assign b[3:0] = o1[4] ? o2[7:4] : o2[3:0];
+ assign az = o1[4] ? o1[4] : o1[3];
+
+endmodule
+
+module pe4(a,b,o);
+
+input [3:0] a;
+output [1:0] b;
+output o;
+
+assign o = |a;
+assign b[1] = |a[3:2];
+assign b[0] = b[1] ? (a[3]) : (a[1]);
+
+endmodule
+
+
+module mux4x1(sel, a , y);
+parameter n=2;
+
+input [4*n-1:0] a;
+input [1:0] sel;
+output [n+1:0] y;
+
+wire [n-1:0] y1;
+
+assign y1 = sel[1] ? (sel[0] ? (a[4*n-1:3*n]) : (a[3*n-1:2*n])) : (sel[0] ? (a[2*n-1:n]) : (a[n-1:0]));
+assign y = {sel, y1};
+
+endmodule
diff --git a/Simulations/pre_synthesis/fxd2float.vcd b/Simulations/pre_synthesis/fxd2float.vcd
new file mode 100644
index 0000000..bc2ce5c
--- /dev/null
+++ b/Simulations/pre_synthesis/fxd2float.vcd
@@ -0,0 +1,186 @@
+$date
+ Thu Oct 28 16:06:10 2021
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1s
+$end
+$scope module fxd2float_tb $end
+$var wire 1 ! zro $end
+$var wire 32 " b [31:0] $end
+$var reg 19 # a [18:0] $end
+$scope module u1 $end
+$var wire 19 $ a [18:0] $end
+$var wire 1 ! zro $end
+$var wire 1 % x $end
+$var wire 8 & o1 [7:0] $end
+$var wire 5 ' o [4:0] $end
+$var wire 32 ( b [31:0] $end
+$scope module t $end
+$var wire 24 ) a [23:0] $end
+$var wire 8 * o2 [7:0] $end
+$var wire 5 + o1 [4:0] $end
+$var wire 18 , o [17:0] $end
+$var wire 5 - b [4:0] $end
+$var wire 1 ! az $end
+$scope module t0 $end
+$var wire 4 . a [3:0] $end
+$var wire 1 / o $end
+$var wire 2 0 b [1:0] $end
+$upscope $end
+$scope module t1 $end
+$var wire 4 1 a [3:0] $end
+$var wire 1 2 o $end
+$var wire 2 3 b [1:0] $end
+$upscope $end
+$scope module t2 $end
+$var wire 4 4 a [3:0] $end
+$var wire 1 5 o $end
+$var wire 2 6 b [1:0] $end
+$upscope $end
+$scope module t3 $end
+$var wire 4 7 a [3:0] $end
+$var wire 1 8 o $end
+$var wire 2 9 b [1:0] $end
+$upscope $end
+$scope module t4 $end
+$var wire 4 : a [3:0] $end
+$var wire 1 ; o $end
+$var wire 2 < b [1:0] $end
+$upscope $end
+$scope module t5 $end
+$var wire 4 = a [3:0] $end
+$var wire 1 > o $end
+$var wire 2 ? b [1:0] $end
+$upscope $end
+$scope module t6 $end
+$var wire 4 @ a [3:0] $end
+$var wire 1 A o $end
+$var wire 2 B b [1:0] $end
+$upscope $end
+$scope module t7 $end
+$var wire 8 C a [7:0] $end
+$var wire 2 D sel [1:0] $end
+$var wire 2 E y1 [1:0] $end
+$var wire 4 F y [3:0] $end
+$upscope $end
+$upscope $end
+$scope module t0 $end
+$var wire 1 G mode $end
+$var wire 8 H p [7:0] $end
+$var wire 8 I q [7:0] $end
+$var wire 9 J temp [8:0] $end
+$var wire 9 K temp3 [8:0] $end
+$var wire 9 L temp2 [8:0] $end
+$var wire 9 M temp1 [8:0] $end
+$var wire 9 N sum [8:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b10001001 N
+b101110111 M
+b1111111 L
+b1010 K
+b10001001 J
+b1010 I
+b1111111 H
+0G
+b1010 F
+b10 E
+b10 D
+b100000 C
+b10 B
+1A
+b100 @
+b0 ?
+0>
+b0 =
+b0 <
+0;
+b0 :
+b0 9
+08
+b0 7
+b10 6
+15
+b100 4
+b0 3
+02
+b0 1
+b0 0
+0/
+b0 .
+b1010 -
+b100000000100000 ,
+b1010 +
+b1010 *
+b10000000000 )
+b1000100100000000000000000000000 (
+b1010 '
+b1010 &
+0%
+b10000000000 $
+b10000000000 #
+b1000100100000000000000000000000 "
+1!
+$end
+#10
+b1000111100000000000000000000000 "
+b1000111100000000000000000000000 (
+b0 E
+b10001111 N
+b101110001 M
+b10001111 J
+b10000 K
+b0 *
+b0 F
+b0 D
+b10000 &
+b10000 I
+b0 B
+b0 C
+b10000 '
+b10000 -
+0A
+b0 @
+b0 6
+b10000 +
+05
+b0 4
+b10000000000000000 ,
+1;
+b1 :
+b10000000000000000 )
+b10000000000000000 #
+b10000000000000000 $
+#20
+b11 E
+b1111 *
+b1111 F
+b11 D
+b1 6
+b11 B
+b11011000 C
+b10 3
+b11011 +
+1A
+b1110 @
+b11 9
+12
+b100 1
+15
+b10 4
+b11110000011011000 ,
+18
+b1110 7
+b1000111111100010010000000000000 "
+b1000111111100010010000000000000 (
+b11110001001000000 )
+b11110001001000000 #
+b11110001001000000 $
+#120
diff --git a/Simulations/pre_synthesis/fxd2float_tb.v b/Simulations/pre_synthesis/fxd2float_tb.v
new file mode 100644
index 0000000..64d596e
--- /dev/null
+++ b/Simulations/pre_synthesis/fxd2float_tb.v
@@ -0,0 +1,28 @@
+module fxd2float_tb;
+parameter in = 19; // input resolution
+parameter man = 23; // Mantisa resolution in bits without hidden bit
+parameter exp = 8; // Exponent Resolution
+reg [in-1:0] a;
+
+wire [exp+man:0] b;
+wire zro;
+
+fxd2flot u1 (a, b, zro);
+
+initial
+begin
+a=19'd 1024;
+# 10 a= 19'd 65536;
+# 10 a=19'd 123456;
+
+#100 $finish;
+end
+
+initial
+begin
+ $dumpfile("fxd2float.vcd");
+ $dumpvars(0, fxd2float_tb);
+ //$monitor("time = %2d, in1 = %d, in2 = %d, out = %d", $time, in1, in2, out);
+end
+
+endmodule
\ No newline at end of file
diff --git a/Simulations/pre_synthesis/sim_res.PNG b/Simulations/pre_synthesis/sim_res.PNG
new file mode 100644
index 0000000..213e51d
--- /dev/null
+++ b/Simulations/pre_synthesis/sim_res.PNG
Binary files differ
