Add files via upload
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..9398841
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,90 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= 2021.09.19_20.25.16
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+
+ @if [ -f ./$*/interactive.tcl ]; then\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+ else\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+ fi
+ mkdir -p ../signoff/$*/
+ cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ make openlane
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/openlane/default.cvcrc b/openlane/default.cvcrc
new file mode 100644
index 0000000..2cdcbaa
--- /dev/null
+++ b/openlane/default.cvcrc
@@ -0,0 +1,35 @@
+CVC_TOP = ''
+CVC_NETLIST = ''
+CVC_MODE = ''
+CVC_MODEL_FILE = ''
+CVC_POWER_FILE = ''
+CVC_FUSE_FILE = ''
+CVC_REPORT_FILE = ''
+CVC_REPORT_TITLE = ''
+CVC_CIRCUIT_ERROR_LIMIT = '100'
+CVC_SEARCH_LIMIT = '100'
+CVC_LEAK_LIMIT = '0.0002'
+CVC_SOI = 'false'
+CVC_SCRC = 'false'
+CVC_VTH_GATES = 'false'
+CVC_MIN_VTH_GATES = 'false'
+CVC_IGNORE_VTH_FLOATING = 'false'
+CVC_IGNORE_NO_LEAK_FLOATING = 'false'
+CVC_LEAK_OVERVOLTAGE = 'true'
+CVC_LOGIC_DIODES = 'false'
+CVC_ANALOG_GATES = 'true'
+CVC_BACKUP_RESULTS = 'false'
+CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
+CVC_SHORT_ERROR_THRESHOLD = '0'
+CVC_BIAS_ERROR_THRESHOLD = '0'
+CVC_FORWARD_ERROR_THRESHOLD = '0'
+CVC_FLOATING_ERROR_THRESHOLD = '0'
+CVC_GATE_ERROR_THRESHOLD = '0'
+CVC_LEAK?_ERROR_THRESHOLD = '0'
+CVC_EXPECTED_ERROR_THRESHOLD = '0'
+CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
+CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
+CVC_CELL_ERROR_LIMIT_FILE = ''
+CVC_CELL_CHECKSUM_FILE = ''
+CVC_LARGE_CIRCUIT_SIZE = '10000000'
+CVC_NET_CHECK_FILE = ''
