| commit | 340cc4a6a8be1caf0eac97c099105ec9f9ed8165 | [log] [tgz] |
|---|---|---|
| author | manarabdelaty <manarabdelatty@aucegypt.edu> | Tue Apr 20 18:28:22 2021 +0200 |
| committer | manarabdelaty <manarabdelatty@aucegypt.edu> | Tue Apr 20 18:28:22 2021 +0200 |
| tree | 3b528e04ed72977ee20da0b2c8d6060e66f78436 | |
| parent | e364bd5664d3a09312d79ff7a77798a7ed7fc218 [diff] [blame] |
Update full chip simulation to run from root
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 73d7868..d87238f 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -26,6 +26,10 @@ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \ done +DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) +$(DV_PATTERNS): verify-% : + cd $* && make + clean: ${PATTERNS} for i in ${PATTERNS}; do \ ( cd $$i && make clean ) ; \