challenge
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index efb083e..35937d8 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 7595de4..bfab0cb 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1634879334
+timestamp 1634924044
<< obsli1 >>
rect 69673 2805 582975 702967
<< obsm1 >>
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 65317ac..62f8e08 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -36,15 +36,15 @@
set ::env(ROUTING_CORES) 16
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) computer.wb_clk_i
+set ::env(CLOCK_NET) computer.wb_clk_i
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) 20
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vccd1 vssd1"
+ computer vccd1 vssd1"
### Macro Placement
# set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..f04c1e6 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+computer 1175 1690 N
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 1e2ffb5..bbeaf81 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h32m22s,0h1m44s,0.19458281444582815,10.2784,0.09729140722291407,-1,535.95,1,0,0,0,0,0,0,0,0,0,-1,-1,1121715,2387,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,40172.26,2.01,6.25,0.97,0.5,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h31m32s,0h1m12s,0.19458281444582815,10.2784,0.09729140722291407,-1,614.03,1,0,0,0,0,0,0,0,0,0,-1,-1,1121715,2387,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,40172.26,2.01,6.25,0.97,0.5,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,50.0,20.0,20,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
