add CLOCK_NET
diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl
index 152cefe..60b9c89 100644
--- a/openlane/computer/config.tcl
+++ b/openlane/computer/config.tcl
@@ -40,6 +40,7 @@
     $script_dir/../../verilog/rtl/jacaranda-8/wishbone.v"
 
 set ::env(CLOCK_PORT) wb_clk_i
+set ::env(CLOCK_NET) wb_clk_i
 set ::env(CLOCK_PERIOD) 10
 
 set ::env(FP_SIZING) absolute