commit a4174fa0a1c89ff6fee4e5d9865147bc9c9fa6ba
author Yuki Azuma <yuhki.yasuda@gmail.com> Sat Oct 09 22:09:23 2021 +0900
committer Yuki Azuma <yuhki.yasuda@gmail.com> Sat Oct 09 22:09:23 2021 +0900
tree 3885d7b8189a317eef4c7963ae474c6588f7651b
parent df0cae8e86325f41f51c450a6f28be906aba3b3e

CPUの産声が聞こえる...

verilog/rtl/jacaranda-8/computer.v

diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 3c409eb..cba21b7 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -89,19 +89,12 @@
     wire [7:0] instr_mem_addr;
     wire [7:0] instr_mem_data; 
 
+    wire reset;
+
+    assign reset = la_data_in[16];
     assign instr_mem_addr = reset ? la_data_in[15:8] : pc;
     assign instr_mem_data = la_data_in[7:0];
 
-    reg reset = 1'b1;
-    wire raw_reset; 
-    assign raw_reset = la_data_in[16];
-
-    //assign reset = ((raw_reset == 1'b0) && (pre_reset == 1'b1));
-    always @(posedge wb_clk_i) begin
-        if(raw_reset == 1'b0) begin
-            reset <= 1'b0;
-        end
-    end
 
     instr_mem instr_mem(.addr(instr_mem_addr),
                         .w_data(instr_mem_data),

verilog/rtl/jacaranda-8/cpu.v

diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v
index b8cadef..d854802 100644
--- a/verilog/rtl/jacaranda-8/cpu.v
+++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -38,7 +38,7 @@
     wire reg_alu_w_sel;
 
     wire clock;
-    assign clock = reset ? 1'b0 : raw_clock;
+    assign clock = reset ? 1'b1 : raw_clock;
 
     //ALUの制御信号
     wire [3:0] alu_ctrl;
@@ -111,7 +111,7 @@
         end
     end
 
-    always @(negedge reset) begin
+    always @(posedge reset) begin
         ret_addr<= 8'h00;
         flag    <= 1'b0;
         pc      <= 8'h00;