commit 9043344b6ca3e8050e21ac4930d5160f1c9230b1
author Yuki Azuma <yuhki.yasuda@gmail.com> Fri Oct 15 20:53:48 2021 +0900
committer Yuki Azuma <yuhki.yasuda@gmail.com> Fri Oct 15 20:53:48 2021 +0900
tree 04bb2540f422ba233a2f6a284f513232ae37a3cc
parent 7c0c5811ca0b594583e24a3cf3628a2e7ef8a640

fix kuso bug

verilog/rtl/jacaranda-8/cpu.v

diff --git a/verilog/rtl/jacaranda-8/cpu.v b/verilog/rtl/jacaranda-8/cpu.v
index 8024a38..a3ed1a2 100644
--- a/verilog/rtl/jacaranda-8/cpu.v
+++ b/verilog/rtl/jacaranda-8/cpu.v
@@ -75,7 +75,7 @@
     always @(posedge clock or posedge reset) begin
         if(reset) begin
             flag <= 0;
-        end if(ret) begin
+        end else if(ret) begin
             flag <= _flag;
         end else if(je_en) begin
             flag <= 0;