なんか知らんけど動いた
diff --git a/verilog/dv/jacaranda_test/jacaranda_test_tb.v b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
index ea53532..fcebc61 100644
--- a/verilog/dv/jacaranda_test/jacaranda_test_tb.v
+++ b/verilog/dv/jacaranda_test/jacaranda_test_tb.v
@@ -46,7 +46,7 @@
$dumpvars(0, jacaranda_test_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (20) begin
+ repeat (70) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
diff --git a/verilog/rtl/jacaranda-8/UART/tx.v b/verilog/rtl/jacaranda-8/UART/tx.v
index f1ceadf..8ec107c 100644
--- a/verilog/rtl/jacaranda-8/UART/tx.v
+++ b/verilog/rtl/jacaranda-8/UART/tx.v
@@ -7,30 +7,32 @@
output reg tx;
output wire busy_flag;
- parameter CLK_FREQ = 50_000_000;
+ parameter CLK_FREQ = 40_000_000;
parameter BAUD_RATE = 115200;
parameter CLK_COUNT_BIT = CLK_FREQ / BAUD_RATE;
- reg[1:0] state = 2'b00;
- reg[31:0] clk_count = 32'd0;
- reg[2:0] bit_count = 3'd0;
+ reg[1:0] state;
+ reg[31:0] clk_count;
+ reg[2:0] bit_count;
wire update_flag;
assign update_flag = (clk_count == CLK_COUNT_BIT - 32'd1);
assign busy_flag = ~(state == 2'b00);
always @(posedge reset) begin
+ clk_count <= 32'd0;
tx <= 1'b1;
state <= 2'b00;
bit_count <= 3'd0;
end
+
always @(posedge clk) begin
case(state)
2'b00: begin
tx <= 1'b1;
clk_count = 32'd0;
bit_count <= 3'd0;
- state <= begin_flag & tx_en ? 2'b01 : state;
+ state <= (begin_flag & tx_en) ? 2'b01 : state;
end
2'b01: begin
tx <= 1'b0;
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 5b20099..4a8692c 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -69,7 +69,8 @@
wire receive_flag;
reg tx_en;
reg rx_en;
- reg begin_flag;
+ //reg begin_flag;
+ wire begin_flag;
reg [7:0] tx_data;
wire [7:0] rx_data;
@@ -145,12 +146,13 @@
always @(posedge clock) begin
if(rs_data == 8'd253 && mem_w_en == 1) begin
tx_data <= rd_data;
- begin_flag = 1;
+ //begin_flag = 1;
end else begin
tx_data <= tx_data;
- begin_flag = 0;
+ //begin_flag = 0;
end
end
+ assign begin_flag = (rs_data == 8'd253) & (mem_w_en == 1);
data_mem data_mem(.addr(rs_data),
.w_data(rd_data),
